1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2011 NetApp, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/param.h> 30 #include <sys/linker_set.h> 31 #include <sys/mman.h> 32 33 #include <ctype.h> 34 #include <err.h> 35 #include <errno.h> 36 #include <pthread.h> 37 #include <stdio.h> 38 #include <stdlib.h> 39 #include <string.h> 40 #include <strings.h> 41 #include <assert.h> 42 #include <stdbool.h> 43 #include <sysexits.h> 44 45 #include <dev/vmm/vmm_mem.h> 46 #include <machine/vmm.h> 47 #include <machine/vmm_snapshot.h> 48 #include <vmmapi.h> 49 50 #include "acpi.h" 51 #include "bhyverun.h" 52 #include "bootrom.h" 53 #include "config.h" 54 #include "debug.h" 55 #ifdef __amd64__ 56 #include "amd64/inout.h" 57 #endif 58 #include "mem.h" 59 #include "pci_emul.h" 60 #ifdef __amd64__ 61 #include "amd64/pci_lpc.h" 62 #include "pci_passthru.h" 63 #endif 64 #include "qemu_fwcfg.h" 65 66 #define CONF1_ADDR_PORT 0x0cf8 67 #define CONF1_DATA_PORT 0x0cfc 68 69 #define CONF1_ENABLE 0x80000000ul 70 71 #define MAXBUSES (PCI_BUSMAX + 1) 72 #define MAXSLOTS (PCI_SLOTMAX + 1) 73 #define MAXFUNCS (PCI_FUNCMAX + 1) 74 75 #define GB (1024 * 1024 * 1024UL) 76 77 struct funcinfo { 78 nvlist_t *fi_config; 79 struct pci_devemu *fi_pde; 80 struct pci_devinst *fi_devi; 81 }; 82 83 struct intxinfo { 84 int ii_count; 85 struct pci_irq ii_irq; 86 }; 87 88 struct slotinfo { 89 struct intxinfo si_intpins[4]; 90 struct funcinfo si_funcs[MAXFUNCS]; 91 }; 92 93 struct businfo { 94 uint16_t iobase, iolimit; /* I/O window */ 95 uint32_t membase32, memlimit32; /* mmio window below 4GB */ 96 uint64_t membase64, memlimit64; /* mmio window above 4GB */ 97 struct slotinfo slotinfo[MAXSLOTS]; 98 }; 99 100 static struct businfo *pci_businfo[MAXBUSES]; 101 102 SET_DECLARE(pci_devemu_set, struct pci_devemu); 103 104 static uint64_t pci_emul_iobase; 105 static uint8_t *pci_emul_rombase; 106 static uint64_t pci_emul_romoffset; 107 static uint8_t *pci_emul_romlim; 108 static uint64_t pci_emul_membase32; 109 static uint64_t pci_emul_membase64; 110 static uint64_t pci_emul_memlim64; 111 112 struct pci_bar_allocation { 113 TAILQ_ENTRY(pci_bar_allocation) chain; 114 struct pci_devinst *pdi; 115 int idx; 116 enum pcibar_type type; 117 uint64_t size; 118 }; 119 120 static TAILQ_HEAD(pci_bar_list, pci_bar_allocation) pci_bars = 121 TAILQ_HEAD_INITIALIZER(pci_bars); 122 123 struct boot_device { 124 TAILQ_ENTRY(boot_device) boot_device_chain; 125 struct pci_devinst *pdi; 126 int bootindex; 127 }; 128 static TAILQ_HEAD(boot_list, boot_device) boot_devices = TAILQ_HEAD_INITIALIZER( 129 boot_devices); 130 131 #if defined(__amd64__) 132 #define PCI_EMUL_IOBASE 0x2000 133 #define PCI_EMUL_IOLIMIT 0x10000 134 #define PCI_EMUL_IOMASK 0xffff 135 /* 136 * OVMF always uses 0xc0000000 as base address for 32 bit PCI MMIO. Don't 137 * change this address without changing it in OVMF. 138 */ 139 #define PCI_EMUL_MEMBASE32 0xc0000000 140 #elif defined(__aarch64__) || defined(__riscv) 141 #define PCI_EMUL_IOBASE 0xdf000000UL 142 #define PCI_EMUL_IOLIMIT 0xe0000000UL 143 #define PCI_EMUL_MEMBASE32 0xa0000000UL 144 #else 145 #error Unsupported platform 146 #endif 147 148 #define PCI_EMUL_ROMSIZE 0x10000000 149 150 #define PCI_EMUL_ECFG_BASE 0xE0000000 /* 3.5GB */ 151 #define PCI_EMUL_ECFG_SIZE (MAXBUSES * 1024 * 1024) /* 1MB per bus */ 152 #ifdef __amd64__ 153 SYSRES_MEM(PCI_EMUL_ECFG_BASE, PCI_EMUL_ECFG_SIZE); 154 #endif 155 156 #define PCI_EMUL_MEMLIMIT32 PCI_EMUL_ECFG_BASE 157 #define PCI_EMUL_MEMSIZE64 (32*GB) 158 159 static void pci_lintr_route(struct pci_devinst *pi); 160 static void pci_lintr_update(struct pci_devinst *pi); 161 162 static struct pci_devemu *pci_emul_finddev(const char *name); 163 static void pci_cfgrw(int in, int bus, int slot, int func, int coff, 164 int bytes, uint32_t *val); 165 166 static __inline void 167 CFGWRITE(struct pci_devinst *pi, int coff, uint32_t val, int bytes) 168 { 169 170 if (bytes == 1) 171 pci_set_cfgdata8(pi, coff, val); 172 else if (bytes == 2) 173 pci_set_cfgdata16(pi, coff, val); 174 else 175 pci_set_cfgdata32(pi, coff, val); 176 } 177 178 static __inline uint32_t 179 CFGREAD(struct pci_devinst *pi, int coff, int bytes) 180 { 181 182 if (bytes == 1) 183 return (pci_get_cfgdata8(pi, coff)); 184 else if (bytes == 2) 185 return (pci_get_cfgdata16(pi, coff)); 186 else 187 return (pci_get_cfgdata32(pi, coff)); 188 } 189 190 static int 191 is_pcir_bar(int coff) 192 { 193 return (coff >= PCIR_BAR(0) && coff < PCIR_BAR(PCI_BARMAX + 1)); 194 } 195 196 static int 197 is_pcir_bios(int coff) 198 { 199 return (coff >= PCIR_BIOS && coff < PCIR_BIOS + 4); 200 } 201 202 /* 203 * I/O access 204 */ 205 206 /* 207 * Slot options are in the form: 208 * 209 * <bus>:<slot>:<func>,<emul>[,<config>] 210 * <slot>[:<func>],<emul>[,<config>] 211 * 212 * slot is 0..31 213 * func is 0..7 214 * emul is a string describing the type of PCI device e.g. virtio-net 215 * config is an optional string, depending on the device, that can be 216 * used for configuration. 217 * Examples are: 218 * 1,virtio-net,tap0 219 * 3:0,dummy 220 */ 221 static void 222 pci_parse_slot_usage(char *aopt) 223 { 224 225 EPRINTLN("Invalid PCI slot info field \"%s\"", aopt); 226 } 227 228 /* 229 * Helper function to parse a list of comma-separated options where 230 * each option is formatted as "name[=value]". If no value is 231 * provided, the option is treated as a boolean and is given a value 232 * of true. 233 */ 234 int 235 pci_parse_legacy_config(nvlist_t *nvl, const char *opt) 236 { 237 char *config, *name, *tofree, *value; 238 239 if (opt == NULL) 240 return (0); 241 242 config = tofree = strdup(opt); 243 while ((name = strsep(&config, ",")) != NULL) { 244 value = strchr(name, '='); 245 if (value != NULL) { 246 *value = '\0'; 247 value++; 248 set_config_value_node(nvl, name, value); 249 } else 250 set_config_bool_node(nvl, name, true); 251 } 252 free(tofree); 253 return (0); 254 } 255 256 /* 257 * PCI device configuration is stored in MIBs that encode the device's 258 * location: 259 * 260 * pci.<bus>.<slot>.<func> 261 * 262 * Where "bus", "slot", and "func" are all decimal values without 263 * leading zeroes. Each valid device must have a "device" node which 264 * identifies the driver model of the device. 265 * 266 * Device backends can provide a parser for the "config" string. If 267 * a custom parser is not provided, pci_parse_legacy_config() is used 268 * to parse the string. 269 */ 270 int 271 pci_parse_slot(char *opt) 272 { 273 char node_name[sizeof("pci.XXX.XX.X")]; 274 struct pci_devemu *pde; 275 char *emul, *config, *str, *cp; 276 int error, bnum, snum, fnum; 277 nvlist_t *nvl; 278 279 error = -1; 280 str = strdup(opt); 281 282 emul = config = NULL; 283 if ((cp = strchr(str, ',')) != NULL) { 284 *cp = '\0'; 285 emul = cp + 1; 286 if ((cp = strchr(emul, ',')) != NULL) { 287 *cp = '\0'; 288 config = cp + 1; 289 } 290 } else { 291 pci_parse_slot_usage(opt); 292 goto done; 293 } 294 295 /* <bus>:<slot>:<func> */ 296 if (sscanf(str, "%d:%d:%d", &bnum, &snum, &fnum) != 3) { 297 bnum = 0; 298 /* <slot>:<func> */ 299 if (sscanf(str, "%d:%d", &snum, &fnum) != 2) { 300 fnum = 0; 301 /* <slot> */ 302 if (sscanf(str, "%d", &snum) != 1) { 303 snum = -1; 304 } 305 } 306 } 307 308 if (bnum < 0 || bnum >= MAXBUSES || snum < 0 || snum >= MAXSLOTS || 309 fnum < 0 || fnum >= MAXFUNCS) { 310 pci_parse_slot_usage(opt); 311 goto done; 312 } 313 314 pde = pci_emul_finddev(emul); 315 if (pde == NULL) { 316 EPRINTLN("pci slot %d:%d:%d: unknown device \"%s\"", bnum, snum, 317 fnum, emul); 318 goto done; 319 } 320 321 snprintf(node_name, sizeof(node_name), "pci.%d.%d.%d", bnum, snum, 322 fnum); 323 nvl = find_config_node(node_name); 324 if (nvl != NULL) { 325 EPRINTLN("pci slot %d:%d:%d already occupied!", bnum, snum, 326 fnum); 327 goto done; 328 } 329 nvl = create_config_node(node_name); 330 if (pde->pe_alias != NULL) 331 set_config_value_node(nvl, "device", pde->pe_alias); 332 else 333 set_config_value_node(nvl, "device", pde->pe_emu); 334 335 if (pde->pe_legacy_config != NULL) 336 error = pde->pe_legacy_config(nvl, config); 337 else 338 error = pci_parse_legacy_config(nvl, config); 339 done: 340 free(str); 341 return (error); 342 } 343 344 void 345 pci_print_supported_devices(void) 346 { 347 struct pci_devemu **pdpp, *pdp; 348 349 SET_FOREACH(pdpp, pci_devemu_set) { 350 pdp = *pdpp; 351 printf("%s\n", pdp->pe_emu); 352 } 353 } 354 355 uint32_t 356 pci_config_read_reg(const struct pci_conf *host_conf, nvlist_t *nvl, 357 const uint32_t reg, const uint8_t size, const uint32_t def) 358 { 359 const char *config; 360 const nvlist_t *pci_regs; 361 uint32_t host; 362 363 assert(size == 1 || size == 2 || size == 4); 364 365 pci_regs = find_relative_config_node(nvl, "pcireg"); 366 if (pci_regs == NULL) { 367 return (def); 368 } 369 370 switch (reg) { 371 case PCIR_DEVICE: 372 config = get_config_value_node(pci_regs, "device"); 373 host = host_conf != NULL ? host_conf->pc_device : 0; 374 break; 375 case PCIR_VENDOR: 376 config = get_config_value_node(pci_regs, "vendor"); 377 host = host_conf != NULL ? host_conf->pc_vendor : 0; 378 break; 379 case PCIR_REVID: 380 config = get_config_value_node(pci_regs, "revid"); 381 host = host_conf != NULL ? host_conf->pc_revid : 0; 382 break; 383 case PCIR_SUBVEND_0: 384 config = get_config_value_node(pci_regs, "subvendor"); 385 host = host_conf != NULL ? host_conf->pc_subvendor : 0; 386 break; 387 case PCIR_SUBDEV_0: 388 config = get_config_value_node(pci_regs, "subdevice"); 389 host = host_conf != NULL ? host_conf->pc_subdevice : 0; 390 break; 391 default: 392 return (-1); 393 } 394 395 if (config == NULL) { 396 return (def); 397 } else if (host_conf != NULL && strcmp(config, "host") == 0) { 398 return (host); 399 } else { 400 return (strtol(config, NULL, 16)); 401 } 402 } 403 404 static int 405 pci_valid_pba_offset(struct pci_devinst *pi, uint64_t offset) 406 { 407 408 if (offset < pi->pi_msix.pba_offset) 409 return (0); 410 411 if (offset >= pi->pi_msix.pba_offset + pi->pi_msix.pba_size) { 412 return (0); 413 } 414 415 return (1); 416 } 417 418 int 419 pci_emul_msix_twrite(struct pci_devinst *pi, uint64_t offset, int size, 420 uint64_t value) 421 { 422 int msix_entry_offset; 423 int tab_index; 424 char *dest; 425 426 /* support only 4 or 8 byte writes */ 427 if (size != 4 && size != 8) 428 return (-1); 429 430 /* 431 * Return if table index is beyond what device supports 432 */ 433 tab_index = offset / MSIX_TABLE_ENTRY_SIZE; 434 if (tab_index >= pi->pi_msix.table_count) 435 return (-1); 436 437 msix_entry_offset = offset % MSIX_TABLE_ENTRY_SIZE; 438 439 /* support only aligned writes */ 440 if ((msix_entry_offset % size) != 0) 441 return (-1); 442 443 dest = (char *)(pi->pi_msix.table + tab_index); 444 dest += msix_entry_offset; 445 446 if (size == 4) 447 *((uint32_t *)dest) = value; 448 else 449 *((uint64_t *)dest) = value; 450 451 return (0); 452 } 453 454 uint64_t 455 pci_emul_msix_tread(struct pci_devinst *pi, uint64_t offset, int size) 456 { 457 char *dest; 458 int msix_entry_offset; 459 int tab_index; 460 uint64_t retval = ~0; 461 462 /* 463 * The PCI standard only allows 4 and 8 byte accesses to the MSI-X 464 * table but we also allow 1 byte access to accommodate reads from 465 * ddb. 466 */ 467 if (size != 1 && size != 4 && size != 8) 468 return (retval); 469 470 msix_entry_offset = offset % MSIX_TABLE_ENTRY_SIZE; 471 472 /* support only aligned reads */ 473 if ((msix_entry_offset % size) != 0) { 474 return (retval); 475 } 476 477 tab_index = offset / MSIX_TABLE_ENTRY_SIZE; 478 479 if (tab_index < pi->pi_msix.table_count) { 480 /* valid MSI-X Table access */ 481 dest = (char *)(pi->pi_msix.table + tab_index); 482 dest += msix_entry_offset; 483 484 if (size == 1) 485 retval = *((uint8_t *)dest); 486 else if (size == 4) 487 retval = *((uint32_t *)dest); 488 else 489 retval = *((uint64_t *)dest); 490 } else if (pci_valid_pba_offset(pi, offset)) { 491 /* return 0 for PBA access */ 492 retval = 0; 493 } 494 495 return (retval); 496 } 497 498 int 499 pci_msix_table_bar(struct pci_devinst *pi) 500 { 501 502 if (pi->pi_msix.table != NULL) 503 return (pi->pi_msix.table_bar); 504 else 505 return (-1); 506 } 507 508 int 509 pci_msix_pba_bar(struct pci_devinst *pi) 510 { 511 512 if (pi->pi_msix.table != NULL) 513 return (pi->pi_msix.pba_bar); 514 else 515 return (-1); 516 } 517 518 #ifdef __amd64__ 519 static int 520 pci_emul_io_handler(struct vmctx *ctx __unused, int in, int port, 521 int bytes, uint32_t *eax, void *arg) 522 { 523 struct pci_devinst *pdi = arg; 524 struct pci_devemu *pe = pdi->pi_d; 525 uint64_t offset; 526 int i; 527 528 assert(port >= 0); 529 530 for (i = 0; i <= PCI_BARMAX; i++) { 531 if (pdi->pi_bar[i].type == PCIBAR_IO && 532 (uint64_t)port >= pdi->pi_bar[i].addr && 533 (uint64_t)port + bytes <= 534 pdi->pi_bar[i].addr + pdi->pi_bar[i].size) { 535 offset = port - pdi->pi_bar[i].addr; 536 if (in) 537 *eax = (*pe->pe_barread)(pdi, i, 538 offset, bytes); 539 else 540 (*pe->pe_barwrite)(pdi, i, offset, 541 bytes, *eax); 542 return (0); 543 } 544 } 545 return (-1); 546 } 547 #else 548 static int 549 pci_emul_iomem_handler(struct vcpu *vcpu __unused, int dir, 550 uint64_t addr, int size, uint64_t *val, void *arg1, long arg2) 551 { 552 struct pci_devinst *pdi = arg1; 553 struct pci_devemu *pe = pdi->pi_d; 554 uint64_t offset; 555 int bidx = (int)arg2; 556 557 assert(bidx <= PCI_BARMAX); 558 assert(pdi->pi_bar[bidx].type == PCIBAR_IO); 559 assert(addr >= pdi->pi_bar[bidx].addr && 560 addr + size <= pdi->pi_bar[bidx].addr + pdi->pi_bar[bidx].size); 561 assert(size == 1 || size == 2 || size == 4); 562 563 offset = addr - pdi->pi_bar[bidx].addr; 564 if (dir == MEM_F_READ) 565 *val = (*pe->pe_barread)(pdi, bidx, offset, size); 566 else 567 (*pe->pe_barwrite)(pdi, bidx, offset, size, *val); 568 569 return (0); 570 } 571 #endif /* !__amd64__ */ 572 573 static int 574 pci_emul_mem_handler(struct vcpu *vcpu __unused, int dir, 575 uint64_t addr, int size, uint64_t *val, void *arg1, long arg2) 576 { 577 struct pci_devinst *pdi = arg1; 578 struct pci_devemu *pe = pdi->pi_d; 579 uint64_t offset; 580 int bidx = (int)arg2; 581 582 assert(bidx <= PCI_BARMAX); 583 assert(pdi->pi_bar[bidx].type == PCIBAR_MEM32 || 584 pdi->pi_bar[bidx].type == PCIBAR_MEM64); 585 assert(addr >= pdi->pi_bar[bidx].addr && 586 addr + size <= pdi->pi_bar[bidx].addr + pdi->pi_bar[bidx].size); 587 588 offset = addr - pdi->pi_bar[bidx].addr; 589 590 if (dir == MEM_F_WRITE) { 591 if (size == 8) { 592 (*pe->pe_barwrite)(pdi, bidx, offset, 593 4, *val & 0xffffffff); 594 (*pe->pe_barwrite)(pdi, bidx, offset + 4, 595 4, *val >> 32); 596 } else { 597 (*pe->pe_barwrite)(pdi, bidx, offset, 598 size, *val); 599 } 600 } else { 601 if (size == 8) { 602 *val = (*pe->pe_barread)(pdi, bidx, 603 offset, 4); 604 *val |= (*pe->pe_barread)(pdi, bidx, 605 offset + 4, 4) << 32; 606 } else { 607 *val = (*pe->pe_barread)(pdi, bidx, 608 offset, size); 609 } 610 } 611 612 return (0); 613 } 614 615 616 static int 617 pci_emul_alloc_resource(uint64_t *baseptr, uint64_t limit, uint64_t size, 618 uint64_t *addr) 619 { 620 uint64_t base; 621 622 assert((size & (size - 1)) == 0); /* must be a power of 2 */ 623 624 base = roundup2(*baseptr, size); 625 626 if (base + size <= limit) { 627 *addr = base; 628 *baseptr = base + size; 629 return (0); 630 } else 631 return (-1); 632 } 633 634 /* 635 * Register (or unregister) the MMIO or I/O region associated with the BAR 636 * register 'idx' of an emulated pci device. 637 */ 638 static void 639 modify_bar_registration(struct pci_devinst *pi, int idx, int registration) 640 { 641 struct pci_devemu *pe; 642 int error; 643 enum pcibar_type type; 644 645 pe = pi->pi_d; 646 type = pi->pi_bar[idx].type; 647 switch (type) { 648 case PCIBAR_IO: 649 { 650 #ifdef __amd64__ 651 struct inout_port iop; 652 653 bzero(&iop, sizeof(struct inout_port)); 654 iop.name = pi->pi_name; 655 iop.port = pi->pi_bar[idx].addr; 656 iop.size = pi->pi_bar[idx].size; 657 if (registration) { 658 iop.flags = IOPORT_F_INOUT; 659 iop.handler = pci_emul_io_handler; 660 iop.arg = pi; 661 error = register_inout(&iop); 662 } else 663 error = unregister_inout(&iop); 664 #else 665 struct mem_range mr; 666 667 bzero(&mr, sizeof(struct mem_range)); 668 mr.name = pi->pi_name; 669 mr.base = pi->pi_bar[idx].addr; 670 mr.size = pi->pi_bar[idx].size; 671 if (registration) { 672 mr.flags = MEM_F_RW; 673 mr.handler = pci_emul_iomem_handler; 674 mr.arg1 = pi; 675 mr.arg2 = idx; 676 error = register_mem(&mr); 677 } else 678 error = unregister_mem(&mr); 679 #endif 680 break; 681 } 682 case PCIBAR_MEM32: 683 case PCIBAR_MEM64: 684 { 685 struct mem_range mr; 686 687 bzero(&mr, sizeof(struct mem_range)); 688 mr.name = pi->pi_name; 689 mr.base = pi->pi_bar[idx].addr; 690 mr.size = pi->pi_bar[idx].size; 691 if (registration) { 692 mr.flags = MEM_F_RW; 693 mr.handler = pci_emul_mem_handler; 694 mr.arg1 = pi; 695 mr.arg2 = idx; 696 error = register_mem(&mr); 697 } else 698 error = unregister_mem(&mr); 699 break; 700 } 701 case PCIBAR_ROM: 702 error = 0; 703 break; 704 default: 705 error = EINVAL; 706 break; 707 } 708 assert(error == 0); 709 710 if (pe->pe_baraddr != NULL) 711 (*pe->pe_baraddr)(pi, idx, registration, pi->pi_bar[idx].addr); 712 } 713 714 static void 715 unregister_bar(struct pci_devinst *pi, int idx) 716 { 717 718 modify_bar_registration(pi, idx, 0); 719 } 720 721 static void 722 register_bar(struct pci_devinst *pi, int idx) 723 { 724 725 modify_bar_registration(pi, idx, 1); 726 } 727 728 /* Is the ROM enabled for the emulated pci device? */ 729 static int 730 romen(struct pci_devinst *pi) 731 { 732 return (pi->pi_bar[PCI_ROM_IDX].lobits & PCIM_BIOS_ENABLE) == 733 PCIM_BIOS_ENABLE; 734 } 735 736 /* Are we decoding i/o port accesses for the emulated pci device? */ 737 static int 738 porten(struct pci_devinst *pi) 739 { 740 uint16_t cmd; 741 742 cmd = pci_get_cfgdata16(pi, PCIR_COMMAND); 743 744 return (cmd & PCIM_CMD_PORTEN); 745 } 746 747 /* Are we decoding memory accesses for the emulated pci device? */ 748 static int 749 memen(struct pci_devinst *pi) 750 { 751 uint16_t cmd; 752 753 cmd = pci_get_cfgdata16(pi, PCIR_COMMAND); 754 755 return (cmd & PCIM_CMD_MEMEN); 756 } 757 758 /* 759 * Update the MMIO or I/O address that is decoded by the BAR register. 760 * 761 * If the pci device has enabled the address space decoding then intercept 762 * the address range decoded by the BAR register. 763 */ 764 static void 765 update_bar_address(struct pci_devinst *pi, uint64_t addr, int idx, int type) 766 { 767 int decode; 768 769 if (pi->pi_bar[idx].type == PCIBAR_IO) 770 decode = porten(pi); 771 else 772 decode = memen(pi); 773 774 if (decode) 775 unregister_bar(pi, idx); 776 777 switch (type) { 778 case PCIBAR_IO: 779 case PCIBAR_MEM32: 780 pi->pi_bar[idx].addr = addr; 781 break; 782 case PCIBAR_MEM64: 783 pi->pi_bar[idx].addr &= ~0xffffffffUL; 784 pi->pi_bar[idx].addr |= addr; 785 break; 786 case PCIBAR_MEMHI64: 787 pi->pi_bar[idx].addr &= 0xffffffff; 788 pi->pi_bar[idx].addr |= addr; 789 break; 790 default: 791 assert(0); 792 } 793 794 if (decode) 795 register_bar(pi, idx); 796 } 797 798 void 799 pci_emul_alloc_bar(struct pci_devinst *pdi, int idx, enum pcibar_type type, 800 uint64_t size) 801 { 802 uint64_t lobits; 803 804 switch (type) { 805 case PCIBAR_ROM: 806 assert(idx == PCI_ROM_IDX); 807 break; 808 case PCIBAR_IO: 809 case PCIBAR_MEM32: 810 assert(idx >= 0 && idx <= PCI_BARMAX); 811 break; 812 case PCIBAR_MEM64: 813 assert(idx >= 0 && idx + 1 <= PCI_BARMAX); 814 break; 815 default: 816 assert(false); 817 } 818 819 if ((size & (size - 1)) != 0) 820 size = 1UL << flsl(size); /* round up to a power of 2 */ 821 822 /* Enforce minimum BAR sizes required by the PCI standard */ 823 if (type == PCIBAR_IO) { 824 if (size < 4) 825 size = 4; 826 } else if (type == PCIBAR_ROM) { 827 if (size < ~PCIM_BIOS_ADDR_MASK + 1) 828 size = ~PCIM_BIOS_ADDR_MASK + 1; 829 } else { 830 if (size < 16) 831 size = 16; 832 } 833 834 switch (type) { 835 case PCIBAR_IO: 836 lobits = PCIM_BAR_IO_SPACE; 837 break; 838 case PCIBAR_MEM64: 839 lobits = PCIM_BAR_MEM_SPACE | PCIM_BAR_MEM_64; 840 break; 841 case PCIBAR_MEM32: 842 lobits = PCIM_BAR_MEM_SPACE | PCIM_BAR_MEM_32; 843 break; 844 case PCIBAR_ROM: 845 lobits = 0; 846 break; 847 default: 848 __assert_unreachable(); 849 } 850 851 /* Initialize the BAR with an address of 0. */ 852 pdi->pi_bar[idx].type = type; 853 pdi->pi_bar[idx].size = size; 854 pdi->pi_bar[idx].addr = 0; 855 pdi->pi_bar[idx].lobits = lobits; 856 pci_set_cfgdata32(pdi, PCIR_BAR(idx), lobits); 857 if (type == PCIBAR_MEM64) { 858 pdi->pi_bar[idx + 1].type = PCIBAR_MEMHI64; 859 pci_set_cfgdata32(pdi, PCIR_BAR(idx + 1), 0); 860 } 861 862 /* 863 * Don't enable or assign an address range for ROM BARs. They 864 * are not used in the non-boot ROM case. 865 */ 866 if (type == PCIBAR_ROM) 867 return; 868 869 /* 870 * To reduce fragmentation of the MMIO space, we allocate the BARs by 871 * size. Therefore, don't allocate the BAR yet. We create a list of all 872 * BAR allocation which is sorted by BAR size. When all PCI devices are 873 * initialized, we will assign an address to the BARs. 874 */ 875 876 /* create a new list entry */ 877 struct pci_bar_allocation *const new_bar = malloc(sizeof(*new_bar)); 878 memset(new_bar, 0, sizeof(*new_bar)); 879 new_bar->pdi = pdi; 880 new_bar->idx = idx; 881 new_bar->type = type; 882 new_bar->size = size; 883 884 /* 885 * Search for a BAR which size is lower than the size of our newly 886 * allocated BAR. 887 */ 888 struct pci_bar_allocation *bar = NULL; 889 TAILQ_FOREACH(bar, &pci_bars, chain) { 890 if (bar->size < size) { 891 break; 892 } 893 } 894 895 if (bar == NULL) { 896 /* 897 * Either the list is empty or new BAR is the smallest BAR of 898 * the list. Append it to the end of our list. 899 */ 900 TAILQ_INSERT_TAIL(&pci_bars, new_bar, chain); 901 } else { 902 /* 903 * The found BAR is smaller than our new BAR. For that reason, 904 * insert our new BAR before the found BAR. 905 */ 906 TAILQ_INSERT_BEFORE(bar, new_bar, chain); 907 } 908 909 /* 910 * Enable PCI BARs only if we don't have a boot ROM, i.e., bhyveload was 911 * used to load the initial guest image. Otherwise, we rely on the boot 912 * ROM to handle this. 913 */ 914 if (!get_config_bool_default("pci.enable_bars", !bootrom_boot())) 915 return; 916 917 /* 918 * pci_passthru devices synchronize their physical and virtual command 919 * register on init. For that reason, the virtual cmd reg should be 920 * updated as early as possible. 921 */ 922 uint16_t enbit = 0; 923 switch (type) { 924 case PCIBAR_IO: 925 enbit = PCIM_CMD_PORTEN; 926 break; 927 case PCIBAR_MEM64: 928 case PCIBAR_MEM32: 929 enbit = PCIM_CMD_MEMEN; 930 break; 931 default: 932 enbit = 0; 933 break; 934 } 935 936 const uint16_t cmd = pci_get_cfgdata16(pdi, PCIR_COMMAND); 937 pci_set_cfgdata16(pdi, PCIR_COMMAND, cmd | enbit); 938 } 939 940 static int 941 pci_emul_assign_bar(struct pci_devinst *const pdi, const int idx, 942 const enum pcibar_type type, const uint64_t size) 943 { 944 int error; 945 uint64_t *baseptr, limit, addr, mask, bar; 946 947 switch (type) { 948 case PCIBAR_IO: 949 baseptr = &pci_emul_iobase; 950 limit = PCI_EMUL_IOLIMIT; 951 mask = PCIM_BAR_IO_BASE; 952 break; 953 case PCIBAR_MEM64: 954 /* 955 * XXX 956 * Some drivers do not work well if the 64-bit BAR is allocated 957 * above 4GB. Allow for this by allocating small requests under 958 * 4GB unless the allocation size is larger than some arbitrary 959 * number (128MB currently). 960 */ 961 if (size > 128 * 1024 * 1024) { 962 baseptr = &pci_emul_membase64; 963 limit = pci_emul_memlim64; 964 mask = PCIM_BAR_MEM_BASE; 965 break; 966 } 967 /* FALLTHROUGH */ 968 case PCIBAR_MEM32: 969 baseptr = &pci_emul_membase32; 970 limit = PCI_EMUL_MEMLIMIT32; 971 mask = PCIM_BAR_MEM_BASE; 972 break; 973 default: 974 __assert_unreachable(); 975 } 976 977 error = pci_emul_alloc_resource(baseptr, limit, size, &addr); 978 if (error != 0) 979 return (error); 980 981 /* Update the BAR address */ 982 pdi->pi_bar[idx].addr = addr; 983 984 bar = (addr & mask) | pdi->pi_bar[idx].lobits; 985 pci_set_cfgdata32(pdi, PCIR_BAR(idx), bar); 986 if (type == PCIBAR_MEM64) 987 pci_set_cfgdata32(pdi, PCIR_BAR(idx + 1), bar >> 32); 988 989 switch (type) { 990 case PCIBAR_IO: 991 if (porten(pdi)) 992 register_bar(pdi, idx); 993 break; 994 case PCIBAR_MEM32: 995 case PCIBAR_MEM64: 996 if (memen(pdi)) 997 register_bar(pdi, idx); 998 break; 999 default: 1000 __assert_unreachable(); 1001 } 1002 1003 return (0); 1004 } 1005 1006 int 1007 pci_emul_alloc_rom(struct pci_devinst *const pdi, const uint64_t size, 1008 void **const addr) 1009 { 1010 /* allocate ROM space once on first call */ 1011 if (pci_emul_rombase == 0) { 1012 pci_emul_rombase = vm_create_devmem(pdi->pi_vmctx, VM_PCIROM, 1013 "pcirom", PCI_EMUL_ROMSIZE); 1014 if (pci_emul_rombase == MAP_FAILED) { 1015 warnx("%s: failed to create rom segment", __func__); 1016 return (-1); 1017 } 1018 pci_emul_romlim = pci_emul_rombase + PCI_EMUL_ROMSIZE; 1019 pci_emul_romoffset = 0; 1020 } 1021 1022 /* ROM size should be a power of 2 and greater than 2 KB */ 1023 const uint64_t rom_size = MAX(1UL << flsl(size), 1024 ~PCIM_BIOS_ADDR_MASK + 1); 1025 1026 /* check if ROM fits into ROM space */ 1027 if (pci_emul_romoffset + rom_size > PCI_EMUL_ROMSIZE) { 1028 warnx("%s: no space left in rom segment:", __func__); 1029 warnx("%16lu bytes left", 1030 PCI_EMUL_ROMSIZE - pci_emul_romoffset); 1031 warnx("%16lu bytes required by %d/%d/%d", rom_size, pdi->pi_bus, 1032 pdi->pi_slot, pdi->pi_func); 1033 return (-1); 1034 } 1035 1036 /* allocate ROM BAR */ 1037 pci_emul_alloc_bar(pdi, PCI_ROM_IDX, PCIBAR_ROM, rom_size); 1038 1039 /* return address */ 1040 *addr = pci_emul_rombase + pci_emul_romoffset; 1041 1042 /* save offset into ROM Space */ 1043 pdi->pi_romoffset = pci_emul_romoffset; 1044 1045 /* increase offset for next ROM */ 1046 pci_emul_romoffset += rom_size; 1047 1048 return (0); 1049 } 1050 1051 int 1052 pci_emul_add_boot_device(struct pci_devinst *pi, int bootindex) 1053 { 1054 struct boot_device *new_device, *device; 1055 1056 /* don't permit a negative bootindex */ 1057 if (bootindex < 0) { 1058 errx(4, "Invalid bootindex %d for %s", bootindex, pi->pi_name); 1059 } 1060 1061 /* alloc new boot device */ 1062 new_device = calloc(1, sizeof(struct boot_device)); 1063 if (new_device == NULL) { 1064 return (ENOMEM); 1065 } 1066 new_device->pdi = pi; 1067 new_device->bootindex = bootindex; 1068 1069 /* search for boot device with higher boot index */ 1070 TAILQ_FOREACH(device, &boot_devices, boot_device_chain) { 1071 if (device->bootindex == bootindex) { 1072 errx(4, 1073 "Could not set bootindex %d for %s. Bootindex already occupied by %s", 1074 bootindex, pi->pi_name, device->pdi->pi_name); 1075 } else if (device->bootindex > bootindex) { 1076 break; 1077 } 1078 } 1079 1080 /* add boot device to queue */ 1081 if (device == NULL) { 1082 TAILQ_INSERT_TAIL(&boot_devices, new_device, boot_device_chain); 1083 } else { 1084 TAILQ_INSERT_BEFORE(device, new_device, boot_device_chain); 1085 } 1086 1087 return (0); 1088 } 1089 1090 #define CAP_START_OFFSET 0x40 1091 static int 1092 pci_emul_add_capability(struct pci_devinst *pi, u_char *capdata, int caplen) 1093 { 1094 int i, capoff, reallen; 1095 uint16_t sts; 1096 1097 assert(caplen > 0); 1098 1099 reallen = roundup2(caplen, 4); /* dword aligned */ 1100 1101 sts = pci_get_cfgdata16(pi, PCIR_STATUS); 1102 if ((sts & PCIM_STATUS_CAPPRESENT) == 0) 1103 capoff = CAP_START_OFFSET; 1104 else 1105 capoff = pi->pi_capend + 1; 1106 1107 /* Check if we have enough space */ 1108 if (capoff + reallen > PCI_REGMAX + 1) 1109 return (-1); 1110 1111 /* Set the previous capability pointer */ 1112 if ((sts & PCIM_STATUS_CAPPRESENT) == 0) { 1113 pci_set_cfgdata8(pi, PCIR_CAP_PTR, capoff); 1114 pci_set_cfgdata16(pi, PCIR_STATUS, sts|PCIM_STATUS_CAPPRESENT); 1115 } else 1116 pci_set_cfgdata8(pi, pi->pi_prevcap + 1, capoff); 1117 1118 /* Copy the capability */ 1119 for (i = 0; i < caplen; i++) 1120 pci_set_cfgdata8(pi, capoff + i, capdata[i]); 1121 1122 /* Set the next capability pointer */ 1123 pci_set_cfgdata8(pi, capoff + 1, 0); 1124 1125 pi->pi_prevcap = capoff; 1126 pi->pi_capend = capoff + reallen - 1; 1127 return (0); 1128 } 1129 1130 static struct pci_devemu * 1131 pci_emul_finddev(const char *name) 1132 { 1133 struct pci_devemu **pdpp, *pdp; 1134 1135 SET_FOREACH(pdpp, pci_devemu_set) { 1136 pdp = *pdpp; 1137 if (!strcmp(pdp->pe_emu, name)) { 1138 return (pdp); 1139 } 1140 } 1141 1142 return (NULL); 1143 } 1144 1145 static int 1146 pci_emul_init(struct vmctx *ctx, struct pci_devemu *pde, int bus, int slot, 1147 int func, struct funcinfo *fi) 1148 { 1149 struct pci_devinst *pdi; 1150 int err; 1151 1152 pdi = calloc(1, sizeof(struct pci_devinst)); 1153 1154 pdi->pi_vmctx = ctx; 1155 pdi->pi_bus = bus; 1156 pdi->pi_slot = slot; 1157 pdi->pi_func = func; 1158 pthread_mutex_init(&pdi->pi_lintr.lock, NULL); 1159 pthread_mutex_init(&pdi->pi_cfg_lock, NULL); 1160 pdi->pi_lintr.pin = 0; 1161 pdi->pi_lintr.state = IDLE; 1162 pci_irq_init_irq(&pdi->pi_lintr.irq); 1163 pdi->pi_d = pde; 1164 snprintf(pdi->pi_name, PI_NAMESZ, "%s@pci.%d.%d.%d", pde->pe_emu, bus, 1165 slot, func); 1166 1167 /* Disable legacy interrupts */ 1168 pci_set_cfgdata8(pdi, PCIR_INTLINE, 255); 1169 pci_set_cfgdata8(pdi, PCIR_INTPIN, 0); 1170 1171 if (get_config_bool_default("pci.enable_bars", !bootrom_boot())) 1172 pci_set_cfgdata8(pdi, PCIR_COMMAND, PCIM_CMD_BUSMASTEREN); 1173 1174 err = (*pde->pe_init)(pdi, fi->fi_config); 1175 if (err == 0) 1176 fi->fi_devi = pdi; 1177 else { 1178 pthread_mutex_destroy(&pdi->pi_cfg_lock); 1179 pthread_mutex_destroy(&pdi->pi_lintr.lock); 1180 free(pdi); 1181 } 1182 1183 return (err); 1184 } 1185 1186 void 1187 pci_populate_msicap(struct msicap *msicap, int msgnum, int nextptr) 1188 { 1189 int mmc; 1190 1191 /* Number of msi messages must be a power of 2 between 1 and 32 */ 1192 assert((msgnum & (msgnum - 1)) == 0 && msgnum >= 1 && msgnum <= 32); 1193 mmc = ffs(msgnum) - 1; 1194 1195 bzero(msicap, sizeof(struct msicap)); 1196 msicap->capid = PCIY_MSI; 1197 msicap->nextptr = nextptr; 1198 msicap->msgctrl = PCIM_MSICTRL_64BIT | (mmc << 1); 1199 } 1200 1201 int 1202 pci_emul_add_msicap(struct pci_devinst *pi, int msgnum) 1203 { 1204 struct msicap msicap; 1205 1206 pci_populate_msicap(&msicap, msgnum, 0); 1207 1208 return (pci_emul_add_capability(pi, (u_char *)&msicap, sizeof(msicap))); 1209 } 1210 1211 static void 1212 pci_populate_msixcap(struct msixcap *msixcap, int msgnum, int barnum, 1213 uint32_t msix_tab_size) 1214 { 1215 1216 assert(msix_tab_size % 4096 == 0); 1217 1218 bzero(msixcap, sizeof(struct msixcap)); 1219 msixcap->capid = PCIY_MSIX; 1220 1221 /* 1222 * Message Control Register, all fields set to 1223 * zero except for the Table Size. 1224 * Note: Table size N is encoded as N-1 1225 */ 1226 msixcap->msgctrl = msgnum - 1; 1227 1228 /* 1229 * MSI-X BAR setup: 1230 * - MSI-X table start at offset 0 1231 * - PBA table starts at a 4K aligned offset after the MSI-X table 1232 */ 1233 msixcap->table_info = barnum & PCIM_MSIX_BIR_MASK; 1234 msixcap->pba_info = msix_tab_size | (barnum & PCIM_MSIX_BIR_MASK); 1235 } 1236 1237 static void 1238 pci_msix_table_init(struct pci_devinst *pi, int table_entries) 1239 { 1240 int i, table_size; 1241 1242 assert(table_entries > 0); 1243 assert(table_entries <= MAX_MSIX_TABLE_ENTRIES); 1244 1245 table_size = table_entries * MSIX_TABLE_ENTRY_SIZE; 1246 pi->pi_msix.table = calloc(1, table_size); 1247 1248 /* set mask bit of vector control register */ 1249 for (i = 0; i < table_entries; i++) 1250 pi->pi_msix.table[i].vector_control |= PCIM_MSIX_VCTRL_MASK; 1251 } 1252 1253 int 1254 pci_emul_add_msixcap(struct pci_devinst *pi, int msgnum, int barnum) 1255 { 1256 uint32_t tab_size; 1257 struct msixcap msixcap; 1258 1259 assert(msgnum >= 1 && msgnum <= MAX_MSIX_TABLE_ENTRIES); 1260 assert(barnum >= 0 && barnum <= PCIR_MAX_BAR_0); 1261 1262 tab_size = msgnum * MSIX_TABLE_ENTRY_SIZE; 1263 1264 /* Align table size to nearest 4K */ 1265 tab_size = roundup2(tab_size, 4096); 1266 1267 pi->pi_msix.table_bar = barnum; 1268 pi->pi_msix.pba_bar = barnum; 1269 pi->pi_msix.table_offset = 0; 1270 pi->pi_msix.table_count = msgnum; 1271 pi->pi_msix.pba_offset = tab_size; 1272 pi->pi_msix.pba_size = PBA_SIZE(msgnum); 1273 1274 pci_msix_table_init(pi, msgnum); 1275 1276 pci_populate_msixcap(&msixcap, msgnum, barnum, tab_size); 1277 1278 /* allocate memory for MSI-X Table and PBA */ 1279 pci_emul_alloc_bar(pi, barnum, PCIBAR_MEM32, 1280 tab_size + pi->pi_msix.pba_size); 1281 1282 return (pci_emul_add_capability(pi, (u_char *)&msixcap, 1283 sizeof(msixcap))); 1284 } 1285 1286 static void 1287 msixcap_cfgwrite(struct pci_devinst *pi, int capoff, int offset, 1288 int bytes, uint32_t val) 1289 { 1290 uint16_t msgctrl, rwmask; 1291 int off; 1292 1293 off = offset - capoff; 1294 /* Message Control Register */ 1295 if (off == 2 && bytes == 2) { 1296 rwmask = PCIM_MSIXCTRL_MSIX_ENABLE | PCIM_MSIXCTRL_FUNCTION_MASK; 1297 msgctrl = pci_get_cfgdata16(pi, offset); 1298 msgctrl &= ~rwmask; 1299 msgctrl |= val & rwmask; 1300 val = msgctrl; 1301 1302 pi->pi_msix.enabled = val & PCIM_MSIXCTRL_MSIX_ENABLE; 1303 pi->pi_msix.function_mask = val & PCIM_MSIXCTRL_FUNCTION_MASK; 1304 pci_lintr_update(pi); 1305 } 1306 1307 CFGWRITE(pi, offset, val, bytes); 1308 } 1309 1310 static void 1311 msicap_cfgwrite(struct pci_devinst *pi, int capoff, int offset, 1312 int bytes, uint32_t val) 1313 { 1314 uint16_t msgctrl, rwmask, msgdata, mme; 1315 uint32_t addrlo; 1316 1317 /* 1318 * If guest is writing to the message control register make sure 1319 * we do not overwrite read-only fields. 1320 */ 1321 if ((offset - capoff) == 2 && bytes == 2) { 1322 rwmask = PCIM_MSICTRL_MME_MASK | PCIM_MSICTRL_MSI_ENABLE; 1323 msgctrl = pci_get_cfgdata16(pi, offset); 1324 msgctrl &= ~rwmask; 1325 msgctrl |= val & rwmask; 1326 val = msgctrl; 1327 } 1328 CFGWRITE(pi, offset, val, bytes); 1329 1330 msgctrl = pci_get_cfgdata16(pi, capoff + 2); 1331 addrlo = pci_get_cfgdata32(pi, capoff + 4); 1332 if (msgctrl & PCIM_MSICTRL_64BIT) 1333 msgdata = pci_get_cfgdata16(pi, capoff + 12); 1334 else 1335 msgdata = pci_get_cfgdata16(pi, capoff + 8); 1336 1337 mme = msgctrl & PCIM_MSICTRL_MME_MASK; 1338 pi->pi_msi.enabled = msgctrl & PCIM_MSICTRL_MSI_ENABLE ? 1 : 0; 1339 if (pi->pi_msi.enabled) { 1340 pi->pi_msi.addr = addrlo; 1341 pi->pi_msi.msg_data = msgdata; 1342 pi->pi_msi.maxmsgnum = 1 << (mme >> 4); 1343 } else { 1344 pi->pi_msi.maxmsgnum = 0; 1345 } 1346 pci_lintr_update(pi); 1347 } 1348 1349 static void 1350 pciecap_cfgwrite(struct pci_devinst *pi, int capoff __unused, int offset, 1351 int bytes, uint32_t val) 1352 { 1353 1354 /* XXX don't write to the readonly parts */ 1355 CFGWRITE(pi, offset, val, bytes); 1356 } 1357 1358 #define PCIECAP_VERSION 0x2 1359 int 1360 pci_emul_add_pciecap(struct pci_devinst *pi, int type) 1361 { 1362 int err; 1363 struct pciecap pciecap; 1364 1365 bzero(&pciecap, sizeof(pciecap)); 1366 1367 /* 1368 * Use the integrated endpoint type for endpoints on a root complex bus. 1369 * 1370 * NB: bhyve currently only supports a single PCI bus that is the root 1371 * complex bus, so all endpoints are integrated. 1372 */ 1373 if ((type == PCIEM_TYPE_ENDPOINT) && (pi->pi_bus == 0)) 1374 type = PCIEM_TYPE_ROOT_INT_EP; 1375 1376 pciecap.capid = PCIY_EXPRESS; 1377 pciecap.pcie_capabilities = PCIECAP_VERSION | type; 1378 if (type != PCIEM_TYPE_ROOT_INT_EP) { 1379 pciecap.link_capabilities = 0x411; /* gen1, x1 */ 1380 pciecap.link_status = 0x11; /* gen1, x1 */ 1381 } 1382 1383 err = pci_emul_add_capability(pi, (u_char *)&pciecap, sizeof(pciecap)); 1384 return (err); 1385 } 1386 1387 /* 1388 * This function assumes that 'coff' is in the capabilities region of the 1389 * config space. A capoff parameter of zero will force a search for the 1390 * offset and type. 1391 */ 1392 void 1393 pci_emul_capwrite(struct pci_devinst *pi, int offset, int bytes, uint32_t val, 1394 uint8_t capoff, int capid) 1395 { 1396 uint8_t nextoff; 1397 1398 /* Do not allow un-aligned writes */ 1399 if ((offset & (bytes - 1)) != 0) 1400 return; 1401 1402 if (capoff == 0) { 1403 /* Find the capability that we want to update */ 1404 capoff = CAP_START_OFFSET; 1405 while (1) { 1406 nextoff = pci_get_cfgdata8(pi, capoff + 1); 1407 if (nextoff == 0) 1408 break; 1409 if (offset >= capoff && offset < nextoff) 1410 break; 1411 1412 capoff = nextoff; 1413 } 1414 assert(offset >= capoff); 1415 capid = pci_get_cfgdata8(pi, capoff); 1416 } 1417 1418 /* 1419 * Capability ID and Next Capability Pointer are readonly. 1420 * However, some o/s's do 4-byte writes that include these. 1421 * For this case, trim the write back to 2 bytes and adjust 1422 * the data. 1423 */ 1424 if (offset == capoff || offset == capoff + 1) { 1425 if (offset == capoff && bytes == 4) { 1426 bytes = 2; 1427 offset += 2; 1428 val >>= 16; 1429 } else 1430 return; 1431 } 1432 1433 switch (capid) { 1434 case PCIY_MSI: 1435 msicap_cfgwrite(pi, capoff, offset, bytes, val); 1436 break; 1437 case PCIY_MSIX: 1438 msixcap_cfgwrite(pi, capoff, offset, bytes, val); 1439 break; 1440 case PCIY_EXPRESS: 1441 pciecap_cfgwrite(pi, capoff, offset, bytes, val); 1442 break; 1443 default: 1444 break; 1445 } 1446 } 1447 1448 static int 1449 pci_emul_iscap(struct pci_devinst *pi, int offset) 1450 { 1451 uint16_t sts; 1452 1453 sts = pci_get_cfgdata16(pi, PCIR_STATUS); 1454 if ((sts & PCIM_STATUS_CAPPRESENT) != 0) { 1455 if (offset >= CAP_START_OFFSET && offset <= pi->pi_capend) 1456 return (1); 1457 } 1458 return (0); 1459 } 1460 1461 static int 1462 pci_emul_fallback_handler(struct vcpu *vcpu __unused, int dir, 1463 uint64_t addr __unused, int size __unused, uint64_t *val, 1464 void *arg1 __unused, long arg2 __unused) 1465 { 1466 /* 1467 * Ignore writes; return 0xff's for reads. The mem read code 1468 * will take care of truncating to the correct size. 1469 */ 1470 if (dir == MEM_F_READ) { 1471 *val = 0xffffffffffffffff; 1472 } 1473 1474 return (0); 1475 } 1476 1477 static int 1478 pci_emul_ecfg_handler(struct vcpu *vcpu __unused, int dir, uint64_t addr, 1479 int bytes, uint64_t *val, void *arg1 __unused, long arg2 __unused) 1480 { 1481 int bus, slot, func, coff, in; 1482 1483 coff = addr & 0xfff; 1484 func = (addr >> 12) & 0x7; 1485 slot = (addr >> 15) & 0x1f; 1486 bus = (addr >> 20) & 0xff; 1487 in = (dir == MEM_F_READ); 1488 if (in) 1489 *val = ~0UL; 1490 pci_cfgrw(in, bus, slot, func, coff, bytes, (uint32_t *)val); 1491 return (0); 1492 } 1493 1494 uint64_t 1495 pci_ecfg_base(void) 1496 { 1497 1498 return (PCI_EMUL_ECFG_BASE); 1499 } 1500 1501 static int 1502 init_bootorder(void) 1503 { 1504 struct boot_device *device; 1505 FILE *fp; 1506 char *bootorder; 1507 size_t bootorder_len; 1508 1509 if (TAILQ_EMPTY(&boot_devices)) 1510 return (0); 1511 1512 fp = open_memstream(&bootorder, &bootorder_len); 1513 TAILQ_FOREACH(device, &boot_devices, boot_device_chain) { 1514 fprintf(fp, "/pci@i0cf8/pci@%d,%d\n", 1515 device->pdi->pi_slot, device->pdi->pi_func); 1516 } 1517 fclose(fp); 1518 1519 return (qemu_fwcfg_add_file("bootorder", bootorder_len + 1, bootorder)); 1520 } 1521 1522 #define BUSIO_ROUNDUP 32 1523 #define BUSMEM32_ROUNDUP (1024 * 1024) 1524 #define BUSMEM64_ROUNDUP (512 * 1024 * 1024) 1525 1526 int 1527 init_pci(struct vmctx *ctx) 1528 { 1529 char node_name[sizeof("pci.XXX.XX.X")]; 1530 struct mem_range mr; 1531 struct pci_devemu *pde; 1532 struct businfo *bi; 1533 struct slotinfo *si; 1534 struct funcinfo *fi; 1535 nvlist_t *nvl; 1536 const char *emul; 1537 size_t lowmem; 1538 int bus, slot, func; 1539 int error; 1540 1541 if (vm_get_lowmem_limit(ctx) > PCI_EMUL_MEMBASE32) 1542 errx(EX_OSERR, "Invalid lowmem limit"); 1543 1544 pci_emul_iobase = PCI_EMUL_IOBASE; 1545 pci_emul_membase32 = PCI_EMUL_MEMBASE32; 1546 1547 pci_emul_membase64 = vm_get_highmem_base(ctx) + 1548 vm_get_highmem_size(ctx); 1549 pci_emul_membase64 = roundup2(pci_emul_membase64, PCI_EMUL_MEMSIZE64); 1550 pci_emul_memlim64 = pci_emul_membase64 + PCI_EMUL_MEMSIZE64; 1551 1552 TAILQ_INIT(&boot_devices); 1553 1554 for (bus = 0; bus < MAXBUSES; bus++) { 1555 snprintf(node_name, sizeof(node_name), "pci.%d", bus); 1556 nvl = find_config_node(node_name); 1557 if (nvl == NULL) 1558 continue; 1559 pci_businfo[bus] = calloc(1, sizeof(struct businfo)); 1560 bi = pci_businfo[bus]; 1561 1562 /* 1563 * Keep track of the i/o and memory resources allocated to 1564 * this bus. 1565 */ 1566 bi->iobase = pci_emul_iobase; 1567 bi->membase32 = pci_emul_membase32; 1568 bi->membase64 = pci_emul_membase64; 1569 1570 /* first run: init devices */ 1571 for (slot = 0; slot < MAXSLOTS; slot++) { 1572 si = &bi->slotinfo[slot]; 1573 for (func = 0; func < MAXFUNCS; func++) { 1574 fi = &si->si_funcs[func]; 1575 snprintf(node_name, sizeof(node_name), 1576 "pci.%d.%d.%d", bus, slot, func); 1577 nvl = find_config_node(node_name); 1578 if (nvl == NULL) 1579 continue; 1580 1581 fi->fi_config = nvl; 1582 emul = get_config_value_node(nvl, "device"); 1583 if (emul == NULL) { 1584 EPRINTLN("pci slot %d:%d:%d: missing " 1585 "\"device\" value", bus, slot, func); 1586 return (EINVAL); 1587 } 1588 pde = pci_emul_finddev(emul); 1589 if (pde == NULL) { 1590 EPRINTLN("pci slot %d:%d:%d: unknown " 1591 "device \"%s\"", bus, slot, func, 1592 emul); 1593 return (EINVAL); 1594 } 1595 if (pde->pe_alias != NULL) { 1596 EPRINTLN("pci slot %d:%d:%d: legacy " 1597 "device \"%s\", use \"%s\" instead", 1598 bus, slot, func, emul, 1599 pde->pe_alias); 1600 return (EINVAL); 1601 } 1602 fi->fi_pde = pde; 1603 error = pci_emul_init(ctx, pde, bus, slot, 1604 func, fi); 1605 if (error) 1606 return (error); 1607 } 1608 } 1609 1610 /* second run: assign BARs and free list */ 1611 struct pci_bar_allocation *bar; 1612 struct pci_bar_allocation *bar_tmp; 1613 TAILQ_FOREACH_SAFE(bar, &pci_bars, chain, bar_tmp) { 1614 pci_emul_assign_bar(bar->pdi, bar->idx, bar->type, 1615 bar->size); 1616 free(bar); 1617 } 1618 TAILQ_INIT(&pci_bars); 1619 1620 /* 1621 * Add some slop to the I/O and memory resources decoded by 1622 * this bus to give a guest some flexibility if it wants to 1623 * reprogram the BARs. 1624 */ 1625 pci_emul_iobase += BUSIO_ROUNDUP; 1626 pci_emul_iobase = roundup2(pci_emul_iobase, BUSIO_ROUNDUP); 1627 bi->iolimit = pci_emul_iobase; 1628 1629 pci_emul_membase32 += BUSMEM32_ROUNDUP; 1630 pci_emul_membase32 = roundup2(pci_emul_membase32, 1631 BUSMEM32_ROUNDUP); 1632 bi->memlimit32 = pci_emul_membase32; 1633 1634 pci_emul_membase64 += BUSMEM64_ROUNDUP; 1635 pci_emul_membase64 = roundup2(pci_emul_membase64, 1636 BUSMEM64_ROUNDUP); 1637 bi->memlimit64 = pci_emul_membase64; 1638 } 1639 1640 /* 1641 * PCI backends are initialized before routing INTx interrupts 1642 * so that LPC devices are able to reserve ISA IRQs before 1643 * routing PIRQ pins. 1644 */ 1645 for (bus = 0; bus < MAXBUSES; bus++) { 1646 if ((bi = pci_businfo[bus]) == NULL) 1647 continue; 1648 1649 for (slot = 0; slot < MAXSLOTS; slot++) { 1650 si = &bi->slotinfo[slot]; 1651 for (func = 0; func < MAXFUNCS; func++) { 1652 fi = &si->si_funcs[func]; 1653 if (fi->fi_devi == NULL) 1654 continue; 1655 pci_lintr_route(fi->fi_devi); 1656 } 1657 } 1658 } 1659 #ifdef __amd64__ 1660 lpc_pirq_routed(); 1661 #endif 1662 1663 if ((error = init_bootorder()) != 0) { 1664 warnx("%s: Unable to init bootorder", __func__); 1665 return (error); 1666 } 1667 1668 /* 1669 * The guest physical memory map looks like the following on amd64: 1670 * [0, lowmem) guest system memory 1671 * [lowmem, 0xC0000000) memory hole (may be absent) 1672 * [0xC0000000, 0xE0000000) PCI hole (32-bit BAR allocation) 1673 * [0xE0000000, 0xF0000000) PCI extended config window 1674 * [0xF0000000, 4GB) LAPIC, IOAPIC, HPET, firmware 1675 * [4GB, 4GB + highmem) guest system memory 1676 * [roundup(4GB + highmem, 32GB), ...) PCI 64-bit BAR allocation 1677 * 1678 * On arm64 the guest physical memory map looks like this: 1679 * [0x0DF00000, 0x10000000) PCI I/O memory 1680 * [0xA0000000, 0xE0000000) PCI 32-bit BAR allocation 1681 * [0xE0000000, 0xF0000000) PCI extended config window 1682 * [4GB, 4GB + highmem) guest system memory 1683 * [roundup(4GB + highmem, 32GB), ...) PCI 64-bit BAR allocation 1684 * 1685 * "lowmem" is guest memory below 0xC0000000. amd64 guests provisioned 1686 * with less than 3GB of RAM will have no memory above the 4GB boundary. 1687 * System memory for arm64 guests is all above the 4GB boundary. 1688 */ 1689 1690 /* 1691 * Accesses to memory addresses that are not allocated to system 1692 * memory or PCI devices return 0xff's. 1693 */ 1694 lowmem = vm_get_lowmem_size(ctx); 1695 bzero(&mr, sizeof(struct mem_range)); 1696 mr.name = "PCI hole"; 1697 mr.flags = MEM_F_RW | MEM_F_IMMUTABLE; 1698 mr.base = lowmem; 1699 mr.size = (4ULL * 1024 * 1024 * 1024) - lowmem; 1700 mr.handler = pci_emul_fallback_handler; 1701 error = register_mem_fallback(&mr); 1702 assert(error == 0); 1703 1704 /* PCI extended config space */ 1705 bzero(&mr, sizeof(struct mem_range)); 1706 mr.name = "PCI ECFG"; 1707 mr.flags = MEM_F_RW | MEM_F_IMMUTABLE; 1708 mr.base = PCI_EMUL_ECFG_BASE; 1709 mr.size = PCI_EMUL_ECFG_SIZE; 1710 mr.handler = pci_emul_ecfg_handler; 1711 error = register_mem(&mr); 1712 assert(error == 0); 1713 1714 return (0); 1715 } 1716 1717 #ifdef __amd64__ 1718 static void 1719 pci_apic_prt_entry(int bus __unused, int slot, int pin, struct pci_irq *irq, 1720 void *arg __unused) 1721 { 1722 1723 dsdt_line(" Package ()"); 1724 dsdt_line(" {"); 1725 dsdt_line(" 0x%X,", slot << 16 | 0xffff); 1726 dsdt_line(" 0x%02X,", pin - 1); 1727 dsdt_line(" Zero,"); 1728 dsdt_line(" 0x%X", irq->ioapic_irq); 1729 dsdt_line(" },"); 1730 } 1731 1732 static void 1733 pci_pirq_prt_entry(int bus __unused, int slot, int pin, struct pci_irq *irq, 1734 void *arg __unused) 1735 { 1736 char *name; 1737 1738 name = lpc_pirq_name(irq->pirq_pin); 1739 if (name == NULL) 1740 return; 1741 dsdt_line(" Package ()"); 1742 dsdt_line(" {"); 1743 dsdt_line(" 0x%X,", slot << 16 | 0xffff); 1744 dsdt_line(" 0x%02X,", pin - 1); 1745 dsdt_line(" %s,", name); 1746 dsdt_line(" 0x00"); 1747 dsdt_line(" },"); 1748 free(name); 1749 } 1750 #endif 1751 1752 /* 1753 * A bhyve virtual machine has a flat PCI hierarchy with a root port 1754 * corresponding to each PCI bus. 1755 */ 1756 static void 1757 pci_bus_write_dsdt(int bus) 1758 { 1759 struct businfo *bi; 1760 struct slotinfo *si; 1761 struct pci_devinst *pi; 1762 int func, slot; 1763 1764 /* 1765 * If there are no devices on this 'bus' then just return. 1766 */ 1767 if ((bi = pci_businfo[bus]) == NULL) { 1768 /* 1769 * Bus 0 is special because it decodes the I/O ports used 1770 * for PCI config space access even if there are no devices 1771 * on it. 1772 */ 1773 if (bus != 0) 1774 return; 1775 } 1776 1777 dsdt_line(" Device (PC%02X)", bus); 1778 dsdt_line(" {"); 1779 dsdt_line(" Name (_HID, EisaId (\"PNP0A03\"))"); 1780 1781 dsdt_line(" Method (_BBN, 0, NotSerialized)"); 1782 dsdt_line(" {"); 1783 dsdt_line(" Return (0x%08X)", bus); 1784 dsdt_line(" }"); 1785 dsdt_line(" Name (_CRS, ResourceTemplate ()"); 1786 dsdt_line(" {"); 1787 dsdt_line(" WordBusNumber (ResourceProducer, MinFixed, " 1788 "MaxFixed, PosDecode,"); 1789 dsdt_line(" 0x0000, // Granularity"); 1790 dsdt_line(" 0x%04X, // Range Minimum", bus); 1791 dsdt_line(" 0x%04X, // Range Maximum", bus); 1792 dsdt_line(" 0x0000, // Translation Offset"); 1793 dsdt_line(" 0x0001, // Length"); 1794 dsdt_line(" ,, )"); 1795 1796 #ifdef __amd64__ 1797 if (bus == 0) { 1798 dsdt_indent(3); 1799 dsdt_fixed_ioport(0xCF8, 8); 1800 dsdt_unindent(3); 1801 1802 dsdt_line(" WordIO (ResourceProducer, MinFixed, MaxFixed, " 1803 "PosDecode, EntireRange,"); 1804 dsdt_line(" 0x0000, // Granularity"); 1805 dsdt_line(" 0x0000, // Range Minimum"); 1806 dsdt_line(" 0x0CF7, // Range Maximum"); 1807 dsdt_line(" 0x0000, // Translation Offset"); 1808 dsdt_line(" 0x0CF8, // Length"); 1809 dsdt_line(" ,, , TypeStatic)"); 1810 1811 dsdt_line(" WordIO (ResourceProducer, MinFixed, MaxFixed, " 1812 "PosDecode, EntireRange,"); 1813 dsdt_line(" 0x0000, // Granularity"); 1814 dsdt_line(" 0x0D00, // Range Minimum"); 1815 dsdt_line(" 0x%04X, // Range Maximum", 1816 PCI_EMUL_IOBASE - 1); 1817 dsdt_line(" 0x0000, // Translation Offset"); 1818 dsdt_line(" 0x%04X, // Length", 1819 PCI_EMUL_IOBASE - 0x0D00); 1820 dsdt_line(" ,, , TypeStatic)"); 1821 1822 if (bi == NULL) { 1823 dsdt_line(" })"); 1824 goto done; 1825 } 1826 } 1827 #endif 1828 assert(bi != NULL); 1829 1830 /* i/o window */ 1831 dsdt_line(" WordIO (ResourceProducer, MinFixed, MaxFixed, " 1832 "PosDecode, EntireRange,"); 1833 dsdt_line(" 0x0000, // Granularity"); 1834 dsdt_line(" 0x%04X, // Range Minimum", bi->iobase); 1835 dsdt_line(" 0x%04X, // Range Maximum", 1836 bi->iolimit - 1); 1837 dsdt_line(" 0x0000, // Translation Offset"); 1838 dsdt_line(" 0x%04X, // Length", 1839 bi->iolimit - bi->iobase); 1840 dsdt_line(" ,, , TypeStatic)"); 1841 1842 /* mmio window (32-bit) */ 1843 dsdt_line(" DWordMemory (ResourceProducer, PosDecode, " 1844 "MinFixed, MaxFixed, NonCacheable, ReadWrite,"); 1845 dsdt_line(" 0x00000000, // Granularity"); 1846 dsdt_line(" 0x%08X, // Range Minimum\n", bi->membase32); 1847 dsdt_line(" 0x%08X, // Range Maximum\n", 1848 bi->memlimit32 - 1); 1849 dsdt_line(" 0x00000000, // Translation Offset"); 1850 dsdt_line(" 0x%08X, // Length\n", 1851 bi->memlimit32 - bi->membase32); 1852 dsdt_line(" ,, , AddressRangeMemory, TypeStatic)"); 1853 1854 /* mmio window (64-bit) */ 1855 dsdt_line(" QWordMemory (ResourceProducer, PosDecode, " 1856 "MinFixed, MaxFixed, NonCacheable, ReadWrite,"); 1857 dsdt_line(" 0x0000000000000000, // Granularity"); 1858 dsdt_line(" 0x%016lX, // Range Minimum\n", bi->membase64); 1859 dsdt_line(" 0x%016lX, // Range Maximum\n", 1860 bi->memlimit64 - 1); 1861 dsdt_line(" 0x0000000000000000, // Translation Offset"); 1862 dsdt_line(" 0x%016lX, // Length\n", 1863 bi->memlimit64 - bi->membase64); 1864 dsdt_line(" ,, , AddressRangeMemory, TypeStatic)"); 1865 dsdt_line(" })"); 1866 1867 #ifdef __amd64__ 1868 if (pci_count_lintr(bus) != 0) { 1869 dsdt_indent(2); 1870 dsdt_line("Name (PPRT, Package ()"); 1871 dsdt_line("{"); 1872 pci_walk_lintr(bus, pci_pirq_prt_entry, NULL); 1873 dsdt_line("})"); 1874 dsdt_line("Name (APRT, Package ()"); 1875 dsdt_line("{"); 1876 pci_walk_lintr(bus, pci_apic_prt_entry, NULL); 1877 dsdt_line("})"); 1878 dsdt_line("Method (_PRT, 0, NotSerialized)"); 1879 dsdt_line("{"); 1880 dsdt_line(" If (PICM)"); 1881 dsdt_line(" {"); 1882 dsdt_line(" Return (APRT)"); 1883 dsdt_line(" }"); 1884 dsdt_line(" Else"); 1885 dsdt_line(" {"); 1886 dsdt_line(" Return (PPRT)"); 1887 dsdt_line(" }"); 1888 dsdt_line("}"); 1889 dsdt_unindent(2); 1890 } 1891 #endif 1892 1893 dsdt_indent(2); 1894 for (slot = 0; slot < MAXSLOTS; slot++) { 1895 si = &bi->slotinfo[slot]; 1896 for (func = 0; func < MAXFUNCS; func++) { 1897 pi = si->si_funcs[func].fi_devi; 1898 if (pi != NULL && pi->pi_d->pe_write_dsdt != NULL) 1899 pi->pi_d->pe_write_dsdt(pi); 1900 } 1901 } 1902 dsdt_unindent(2); 1903 #ifdef __amd64__ 1904 done: 1905 #endif 1906 dsdt_line(" }"); 1907 } 1908 1909 void 1910 pci_write_dsdt(void) 1911 { 1912 int bus; 1913 1914 dsdt_indent(1); 1915 dsdt_line("Name (PICM, 0x00)"); 1916 dsdt_line("Method (_PIC, 1, NotSerialized)"); 1917 dsdt_line("{"); 1918 dsdt_line(" Store (Arg0, PICM)"); 1919 dsdt_line("}"); 1920 dsdt_line(""); 1921 dsdt_line("Scope (_SB)"); 1922 dsdt_line("{"); 1923 for (bus = 0; bus < MAXBUSES; bus++) 1924 pci_bus_write_dsdt(bus); 1925 dsdt_line("}"); 1926 dsdt_unindent(1); 1927 } 1928 1929 int 1930 pci_bus_configured(int bus) 1931 { 1932 assert(bus >= 0 && bus < MAXBUSES); 1933 return (pci_businfo[bus] != NULL); 1934 } 1935 1936 int 1937 pci_msi_enabled(struct pci_devinst *pi) 1938 { 1939 return (pi->pi_msi.enabled); 1940 } 1941 1942 int 1943 pci_msi_maxmsgnum(struct pci_devinst *pi) 1944 { 1945 if (pi->pi_msi.enabled) 1946 return (pi->pi_msi.maxmsgnum); 1947 else 1948 return (0); 1949 } 1950 1951 int 1952 pci_msix_enabled(struct pci_devinst *pi) 1953 { 1954 1955 return (pi->pi_msix.enabled && !pi->pi_msi.enabled); 1956 } 1957 1958 void 1959 pci_generate_msix(struct pci_devinst *pi, int index) 1960 { 1961 struct msix_table_entry *mte; 1962 1963 if (!pci_msix_enabled(pi)) 1964 return; 1965 1966 if (pi->pi_msix.function_mask) 1967 return; 1968 1969 if (index >= pi->pi_msix.table_count) 1970 return; 1971 1972 mte = &pi->pi_msix.table[index]; 1973 if ((mte->vector_control & PCIM_MSIX_VCTRL_MASK) == 0) { 1974 /* XXX Set PBA bit if interrupt is disabled */ 1975 vm_raise_msi(pi->pi_vmctx, mte->addr, mte->msg_data, 1976 pi->pi_bus, pi->pi_slot, pi->pi_func); 1977 } 1978 } 1979 1980 void 1981 pci_generate_msi(struct pci_devinst *pi, int index) 1982 { 1983 1984 if (pci_msi_enabled(pi) && index < pci_msi_maxmsgnum(pi)) { 1985 vm_raise_msi(pi->pi_vmctx, pi->pi_msi.addr, 1986 pi->pi_msi.msg_data + index, 1987 pi->pi_bus, pi->pi_slot, pi->pi_func); 1988 } 1989 } 1990 1991 static bool 1992 pci_lintr_permitted(struct pci_devinst *pi) 1993 { 1994 uint16_t cmd; 1995 1996 cmd = pci_get_cfgdata16(pi, PCIR_COMMAND); 1997 return (!(pi->pi_msi.enabled || pi->pi_msix.enabled || 1998 (cmd & PCIM_CMD_INTxDIS))); 1999 } 2000 2001 void 2002 pci_lintr_request(struct pci_devinst *pi) 2003 { 2004 struct businfo *bi; 2005 struct slotinfo *si; 2006 int bestpin, bestcount, pin; 2007 2008 bi = pci_businfo[pi->pi_bus]; 2009 assert(bi != NULL); 2010 2011 /* 2012 * Just allocate a pin from our slot. The pin will be 2013 * assigned IRQs later when interrupts are routed. 2014 */ 2015 si = &bi->slotinfo[pi->pi_slot]; 2016 bestpin = 0; 2017 bestcount = si->si_intpins[0].ii_count; 2018 for (pin = 1; pin < 4; pin++) { 2019 if (si->si_intpins[pin].ii_count < bestcount) { 2020 bestpin = pin; 2021 bestcount = si->si_intpins[pin].ii_count; 2022 } 2023 } 2024 2025 si->si_intpins[bestpin].ii_count++; 2026 pi->pi_lintr.pin = bestpin + 1; 2027 pci_set_cfgdata8(pi, PCIR_INTPIN, bestpin + 1); 2028 } 2029 2030 static void 2031 pci_lintr_route(struct pci_devinst *pi) 2032 { 2033 struct businfo *bi; 2034 struct intxinfo *ii; 2035 struct pci_irq *irq; 2036 2037 if (pi->pi_lintr.pin == 0) 2038 return; 2039 2040 bi = pci_businfo[pi->pi_bus]; 2041 assert(bi != NULL); 2042 ii = &bi->slotinfo[pi->pi_slot].si_intpins[pi->pi_lintr.pin - 1]; 2043 irq = &ii->ii_irq; 2044 pci_irq_route(pi, irq); 2045 pi->pi_lintr.irq = *irq; 2046 pci_set_cfgdata8(pi, PCIR_INTLINE, pci_irq_intline(irq)); 2047 } 2048 2049 void 2050 pci_lintr_assert(struct pci_devinst *pi) 2051 { 2052 2053 assert(pi->pi_lintr.pin > 0); 2054 2055 pthread_mutex_lock(&pi->pi_lintr.lock); 2056 if (pi->pi_lintr.state == IDLE) { 2057 if (pci_lintr_permitted(pi)) { 2058 pi->pi_lintr.state = ASSERTED; 2059 pci_irq_assert(pi); 2060 } else 2061 pi->pi_lintr.state = PENDING; 2062 } 2063 pthread_mutex_unlock(&pi->pi_lintr.lock); 2064 } 2065 2066 void 2067 pci_lintr_deassert(struct pci_devinst *pi) 2068 { 2069 2070 assert(pi->pi_lintr.pin > 0); 2071 2072 pthread_mutex_lock(&pi->pi_lintr.lock); 2073 if (pi->pi_lintr.state == ASSERTED) { 2074 pi->pi_lintr.state = IDLE; 2075 pci_irq_deassert(pi); 2076 } else if (pi->pi_lintr.state == PENDING) 2077 pi->pi_lintr.state = IDLE; 2078 pthread_mutex_unlock(&pi->pi_lintr.lock); 2079 } 2080 2081 static void 2082 pci_lintr_update(struct pci_devinst *pi) 2083 { 2084 2085 pthread_mutex_lock(&pi->pi_lintr.lock); 2086 if (pi->pi_lintr.state == ASSERTED && !pci_lintr_permitted(pi)) { 2087 pci_irq_deassert(pi); 2088 pi->pi_lintr.state = PENDING; 2089 } else if (pi->pi_lintr.state == PENDING && pci_lintr_permitted(pi)) { 2090 pi->pi_lintr.state = ASSERTED; 2091 pci_irq_assert(pi); 2092 } 2093 pthread_mutex_unlock(&pi->pi_lintr.lock); 2094 } 2095 2096 int 2097 pci_count_lintr(int bus) 2098 { 2099 int count, slot, pin; 2100 struct slotinfo *slotinfo; 2101 2102 count = 0; 2103 if (pci_businfo[bus] != NULL) { 2104 for (slot = 0; slot < MAXSLOTS; slot++) { 2105 slotinfo = &pci_businfo[bus]->slotinfo[slot]; 2106 for (pin = 0; pin < 4; pin++) { 2107 if (slotinfo->si_intpins[pin].ii_count != 0) 2108 count++; 2109 } 2110 } 2111 } 2112 return (count); 2113 } 2114 2115 void 2116 pci_walk_lintr(int bus, pci_lintr_cb cb, void *arg) 2117 { 2118 struct businfo *bi; 2119 struct slotinfo *si; 2120 struct intxinfo *ii; 2121 int slot, pin; 2122 2123 if ((bi = pci_businfo[bus]) == NULL) 2124 return; 2125 2126 for (slot = 0; slot < MAXSLOTS; slot++) { 2127 si = &bi->slotinfo[slot]; 2128 for (pin = 0; pin < 4; pin++) { 2129 ii = &si->si_intpins[pin]; 2130 if (ii->ii_count != 0) 2131 cb(bus, slot, pin + 1, &ii->ii_irq, arg); 2132 } 2133 } 2134 } 2135 2136 /* 2137 * Return 1 if the emulated device in 'slot' is a multi-function device. 2138 * Return 0 otherwise. 2139 */ 2140 static int 2141 pci_emul_is_mfdev(int bus, int slot) 2142 { 2143 struct businfo *bi; 2144 struct slotinfo *si; 2145 int f, numfuncs; 2146 2147 numfuncs = 0; 2148 if ((bi = pci_businfo[bus]) != NULL) { 2149 si = &bi->slotinfo[slot]; 2150 for (f = 0; f < MAXFUNCS; f++) { 2151 if (si->si_funcs[f].fi_devi != NULL) { 2152 numfuncs++; 2153 } 2154 } 2155 } 2156 return (numfuncs > 1); 2157 } 2158 2159 /* 2160 * Ensure that the PCIM_MFDEV bit is properly set (or unset) depending on 2161 * whether or not is a multi-function being emulated in the pci 'slot'. 2162 */ 2163 static void 2164 pci_emul_hdrtype_fixup(int bus, int slot, int off, int bytes, uint32_t *rv) 2165 { 2166 int mfdev; 2167 2168 if (off <= PCIR_HDRTYPE && off + bytes > PCIR_HDRTYPE) { 2169 mfdev = pci_emul_is_mfdev(bus, slot); 2170 switch (bytes) { 2171 case 1: 2172 case 2: 2173 *rv &= ~PCIM_MFDEV; 2174 if (mfdev) { 2175 *rv |= PCIM_MFDEV; 2176 } 2177 break; 2178 case 4: 2179 *rv &= ~(PCIM_MFDEV << 16); 2180 if (mfdev) { 2181 *rv |= (PCIM_MFDEV << 16); 2182 } 2183 break; 2184 } 2185 } 2186 } 2187 2188 /* 2189 * Update device state in response to changes to the PCI command 2190 * register. 2191 */ 2192 void 2193 pci_emul_cmd_changed(struct pci_devinst *pi, uint16_t old) 2194 { 2195 int i; 2196 uint16_t changed, new; 2197 2198 new = pci_get_cfgdata16(pi, PCIR_COMMAND); 2199 changed = old ^ new; 2200 2201 /* 2202 * If the MMIO or I/O address space decoding has changed then 2203 * register/unregister all BARs that decode that address space. 2204 */ 2205 for (i = 0; i <= PCI_BARMAX_WITH_ROM; i++) { 2206 switch (pi->pi_bar[i].type) { 2207 case PCIBAR_NONE: 2208 case PCIBAR_MEMHI64: 2209 break; 2210 case PCIBAR_IO: 2211 /* I/O address space decoding changed? */ 2212 if (changed & PCIM_CMD_PORTEN) { 2213 if (new & PCIM_CMD_PORTEN) 2214 register_bar(pi, i); 2215 else 2216 unregister_bar(pi, i); 2217 } 2218 break; 2219 case PCIBAR_ROM: 2220 /* skip (un-)register of ROM if it disabled */ 2221 if (!romen(pi)) 2222 break; 2223 /* fallthrough */ 2224 case PCIBAR_MEM32: 2225 case PCIBAR_MEM64: 2226 /* MMIO address space decoding changed? */ 2227 if (changed & PCIM_CMD_MEMEN) { 2228 if (new & PCIM_CMD_MEMEN) 2229 register_bar(pi, i); 2230 else 2231 unregister_bar(pi, i); 2232 } 2233 break; 2234 default: 2235 assert(0); 2236 } 2237 } 2238 2239 /* 2240 * If INTx has been unmasked and is pending, assert the 2241 * interrupt. 2242 */ 2243 pci_lintr_update(pi); 2244 } 2245 2246 static void 2247 pci_emul_cmdsts_write(struct pci_devinst *pi, int coff, uint32_t new, int bytes) 2248 { 2249 int rshift; 2250 uint32_t cmd, old, readonly; 2251 2252 cmd = pci_get_cfgdata16(pi, PCIR_COMMAND); /* stash old value */ 2253 2254 /* 2255 * From PCI Local Bus Specification 3.0 sections 6.2.2 and 6.2.3. 2256 * 2257 * XXX Bits 8, 11, 12, 13, 14 and 15 in the status register are 2258 * 'write 1 to clear'. However these bits are not set to '1' by 2259 * any device emulation so it is simpler to treat them as readonly. 2260 */ 2261 rshift = (coff & 0x3) * 8; 2262 readonly = 0xFFFFF880 >> rshift; 2263 2264 old = CFGREAD(pi, coff, bytes); 2265 new &= ~readonly; 2266 new |= (old & readonly); 2267 CFGWRITE(pi, coff, new, bytes); /* update config */ 2268 2269 pci_emul_cmd_changed(pi, cmd); 2270 } 2271 2272 static void 2273 pci_cfgrw(int in, int bus, int slot, int func, int coff, int bytes, 2274 uint32_t *valp) 2275 { 2276 struct businfo *bi; 2277 struct slotinfo *si; 2278 struct pci_devinst *pi; 2279 struct pci_devemu *pe; 2280 int idx, needcfg; 2281 uint64_t addr, bar, mask; 2282 2283 if ((bi = pci_businfo[bus]) != NULL) { 2284 si = &bi->slotinfo[slot]; 2285 pi = si->si_funcs[func].fi_devi; 2286 } else 2287 pi = NULL; 2288 2289 /* 2290 * Just return if there is no device at this slot:func or if the 2291 * guest is doing an un-aligned access. 2292 */ 2293 if (pi == NULL || (bytes != 1 && bytes != 2 && bytes != 4) || 2294 (coff & (bytes - 1)) != 0) { 2295 if (in) 2296 *valp = 0xffffffff; 2297 return; 2298 } 2299 2300 /* 2301 * Ignore all writes beyond the standard config space and return all 2302 * ones on reads. 2303 */ 2304 if (coff >= PCI_REGMAX + 1) { 2305 if (in) { 2306 *valp = 0xffffffff; 2307 /* 2308 * Extended capabilities begin at offset 256 in config 2309 * space. Absence of extended capabilities is signaled 2310 * with all 0s in the extended capability header at 2311 * offset 256. 2312 */ 2313 if (coff <= PCI_REGMAX + 4) 2314 *valp = 0x00000000; 2315 } 2316 return; 2317 } 2318 2319 pe = pi->pi_d; 2320 pthread_mutex_lock(&pi->pi_cfg_lock); 2321 2322 /* 2323 * Config read 2324 */ 2325 if (in) { 2326 /* Let the device emulation override the default handler */ 2327 if (pe->pe_cfgread != NULL) { 2328 needcfg = pe->pe_cfgread(pi, coff, bytes, valp); 2329 } else { 2330 needcfg = 1; 2331 } 2332 2333 if (needcfg) 2334 *valp = CFGREAD(pi, coff, bytes); 2335 2336 pci_emul_hdrtype_fixup(bus, slot, coff, bytes, valp); 2337 } else { 2338 /* Let the device emulation override the default handler */ 2339 if (pe->pe_cfgwrite != NULL && 2340 (*pe->pe_cfgwrite)(pi, coff, bytes, *valp) == 0) 2341 goto out; 2342 2343 /* 2344 * Special handling for write to BAR and ROM registers 2345 */ 2346 if (is_pcir_bar(coff) || is_pcir_bios(coff)) { 2347 /* 2348 * Ignore writes to BAR registers that are not 2349 * 4-byte aligned. 2350 */ 2351 if (bytes != 4 || (coff & 0x3) != 0) 2352 goto out; 2353 2354 if (is_pcir_bar(coff)) { 2355 idx = (coff - PCIR_BAR(0)) / 4; 2356 } else if (is_pcir_bios(coff)) { 2357 idx = PCI_ROM_IDX; 2358 } else { 2359 errx(4, "%s: invalid BAR offset %d", __func__, 2360 coff); 2361 } 2362 2363 mask = ~(pi->pi_bar[idx].size - 1); 2364 switch (pi->pi_bar[idx].type) { 2365 case PCIBAR_NONE: 2366 pi->pi_bar[idx].addr = bar = 0; 2367 break; 2368 case PCIBAR_IO: 2369 addr = *valp & mask; 2370 #if defined(PCI_EMUL_IOMASK) 2371 addr &= PCI_EMUL_IOMASK; 2372 #endif 2373 bar = addr | pi->pi_bar[idx].lobits; 2374 /* 2375 * Register the new BAR value for interception 2376 */ 2377 if (addr != pi->pi_bar[idx].addr) { 2378 update_bar_address(pi, addr, idx, 2379 PCIBAR_IO); 2380 } 2381 break; 2382 case PCIBAR_MEM32: 2383 addr = bar = *valp & mask; 2384 bar |= pi->pi_bar[idx].lobits; 2385 if (addr != pi->pi_bar[idx].addr) { 2386 update_bar_address(pi, addr, idx, 2387 PCIBAR_MEM32); 2388 } 2389 break; 2390 case PCIBAR_MEM64: 2391 addr = bar = *valp & mask; 2392 bar |= pi->pi_bar[idx].lobits; 2393 if (addr != (uint32_t)pi->pi_bar[idx].addr) { 2394 update_bar_address(pi, addr, idx, 2395 PCIBAR_MEM64); 2396 } 2397 break; 2398 case PCIBAR_MEMHI64: 2399 mask = ~(pi->pi_bar[idx - 1].size - 1); 2400 addr = ((uint64_t)*valp << 32) & mask; 2401 bar = addr >> 32; 2402 if (bar != pi->pi_bar[idx - 1].addr >> 32) { 2403 update_bar_address(pi, addr, idx - 1, 2404 PCIBAR_MEMHI64); 2405 } 2406 break; 2407 case PCIBAR_ROM: 2408 addr = bar = *valp & mask; 2409 if (memen(pi) && romen(pi)) { 2410 unregister_bar(pi, idx); 2411 } 2412 pi->pi_bar[idx].addr = addr; 2413 pi->pi_bar[idx].lobits = *valp & 2414 PCIM_BIOS_ENABLE; 2415 /* romen could have changed it value */ 2416 if (memen(pi) && romen(pi)) { 2417 register_bar(pi, idx); 2418 } 2419 bar |= pi->pi_bar[idx].lobits; 2420 break; 2421 default: 2422 assert(0); 2423 } 2424 pci_set_cfgdata32(pi, coff, bar); 2425 2426 } else if (pci_emul_iscap(pi, coff)) { 2427 pci_emul_capwrite(pi, coff, bytes, *valp, 0, 0); 2428 } else if (coff >= PCIR_COMMAND && coff < PCIR_REVID) { 2429 pci_emul_cmdsts_write(pi, coff, *valp, bytes); 2430 } else { 2431 CFGWRITE(pi, coff, *valp, bytes); 2432 } 2433 } 2434 out: 2435 pthread_mutex_unlock(&pi->pi_cfg_lock); 2436 } 2437 2438 #ifdef __amd64__ 2439 static int cfgenable, cfgbus, cfgslot, cfgfunc, cfgoff; 2440 2441 static int 2442 pci_emul_cfgaddr(struct vmctx *ctx __unused, int in, 2443 int port __unused, int bytes, uint32_t *eax, void *arg __unused) 2444 { 2445 uint32_t x; 2446 2447 if (bytes != 4) { 2448 if (in) 2449 *eax = (bytes == 2) ? 0xffff : 0xff; 2450 return (0); 2451 } 2452 2453 if (in) { 2454 x = (cfgbus << 16) | (cfgslot << 11) | (cfgfunc << 8) | cfgoff; 2455 if (cfgenable) 2456 x |= CONF1_ENABLE; 2457 *eax = x; 2458 } else { 2459 x = *eax; 2460 cfgenable = (x & CONF1_ENABLE) == CONF1_ENABLE; 2461 cfgoff = (x & PCI_REGMAX) & ~0x03; 2462 cfgfunc = (x >> 8) & PCI_FUNCMAX; 2463 cfgslot = (x >> 11) & PCI_SLOTMAX; 2464 cfgbus = (x >> 16) & PCI_BUSMAX; 2465 } 2466 2467 return (0); 2468 } 2469 INOUT_PORT(pci_cfgaddr, CONF1_ADDR_PORT, IOPORT_F_INOUT, pci_emul_cfgaddr); 2470 2471 static int 2472 pci_emul_cfgdata(struct vmctx *ctx __unused, int in, int port, 2473 int bytes, uint32_t *eax, void *arg __unused) 2474 { 2475 int coff; 2476 2477 assert(bytes == 1 || bytes == 2 || bytes == 4); 2478 2479 coff = cfgoff + (port - CONF1_DATA_PORT); 2480 if (cfgenable) { 2481 pci_cfgrw(in, cfgbus, cfgslot, cfgfunc, coff, bytes, eax); 2482 } else { 2483 /* Ignore accesses to cfgdata if not enabled by cfgaddr */ 2484 if (in) 2485 *eax = 0xffffffff; 2486 } 2487 return (0); 2488 } 2489 2490 INOUT_PORT(pci_cfgdata, CONF1_DATA_PORT+0, IOPORT_F_INOUT, pci_emul_cfgdata); 2491 INOUT_PORT(pci_cfgdata, CONF1_DATA_PORT+1, IOPORT_F_INOUT, pci_emul_cfgdata); 2492 INOUT_PORT(pci_cfgdata, CONF1_DATA_PORT+2, IOPORT_F_INOUT, pci_emul_cfgdata); 2493 INOUT_PORT(pci_cfgdata, CONF1_DATA_PORT+3, IOPORT_F_INOUT, pci_emul_cfgdata); 2494 #endif 2495 2496 #ifdef BHYVE_SNAPSHOT 2497 /* 2498 * Saves/restores PCI device emulated state. Returns 0 on success. 2499 */ 2500 static int 2501 pci_snapshot_pci_dev(struct vm_snapshot_meta *meta) 2502 { 2503 struct pci_devinst *pi; 2504 int i; 2505 int ret; 2506 2507 pi = meta->dev_data; 2508 2509 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msi.enabled, meta, ret, done); 2510 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msi.addr, meta, ret, done); 2511 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msi.msg_data, meta, ret, done); 2512 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msi.maxmsgnum, meta, ret, done); 2513 2514 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msix.enabled, meta, ret, done); 2515 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msix.table_bar, meta, ret, done); 2516 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msix.pba_bar, meta, ret, done); 2517 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msix.table_offset, meta, ret, done); 2518 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msix.table_count, meta, ret, done); 2519 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msix.pba_offset, meta, ret, done); 2520 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msix.pba_size, meta, ret, done); 2521 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msix.function_mask, meta, ret, done); 2522 2523 SNAPSHOT_BUF_OR_LEAVE(pi->pi_cfgdata, sizeof(pi->pi_cfgdata), 2524 meta, ret, done); 2525 2526 for (i = 0; i < (int)nitems(pi->pi_bar); i++) { 2527 SNAPSHOT_VAR_OR_LEAVE(pi->pi_bar[i].type, meta, ret, done); 2528 SNAPSHOT_VAR_OR_LEAVE(pi->pi_bar[i].size, meta, ret, done); 2529 SNAPSHOT_VAR_OR_LEAVE(pi->pi_bar[i].addr, meta, ret, done); 2530 } 2531 2532 /* Restore MSI-X table. */ 2533 for (i = 0; i < pi->pi_msix.table_count; i++) { 2534 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msix.table[i].addr, 2535 meta, ret, done); 2536 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msix.table[i].msg_data, 2537 meta, ret, done); 2538 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msix.table[i].vector_control, 2539 meta, ret, done); 2540 } 2541 2542 done: 2543 return (ret); 2544 } 2545 2546 int 2547 pci_snapshot(struct vm_snapshot_meta *meta) 2548 { 2549 struct pci_devemu *pde; 2550 struct pci_devinst *pdi; 2551 int ret; 2552 2553 assert(meta->dev_name != NULL); 2554 2555 pdi = meta->dev_data; 2556 pde = pdi->pi_d; 2557 2558 if (pde->pe_snapshot == NULL) 2559 return (ENOTSUP); 2560 2561 ret = pci_snapshot_pci_dev(meta); 2562 if (ret == 0) 2563 ret = (*pde->pe_snapshot)(meta); 2564 2565 return (ret); 2566 } 2567 2568 int 2569 pci_pause(struct pci_devinst *pdi) 2570 { 2571 struct pci_devemu *pde = pdi->pi_d; 2572 2573 if (pde->pe_pause == NULL) { 2574 /* The pause/resume functionality is optional. */ 2575 return (0); 2576 } 2577 2578 return (*pde->pe_pause)(pdi); 2579 } 2580 2581 int 2582 pci_resume(struct pci_devinst *pdi) 2583 { 2584 struct pci_devemu *pde = pdi->pi_d; 2585 2586 if (pde->pe_resume == NULL) { 2587 /* The pause/resume functionality is optional. */ 2588 return (0); 2589 } 2590 2591 return (*pde->pe_resume)(pdi); 2592 } 2593 #endif 2594 2595 #define PCI_EMUL_TEST 2596 #ifdef PCI_EMUL_TEST 2597 /* 2598 * Define a dummy test device 2599 */ 2600 #define DIOSZ 8 2601 #define DMEMSZ 4096 2602 struct pci_emul_dsoftc { 2603 uint8_t ioregs[DIOSZ]; 2604 uint8_t memregs[2][DMEMSZ]; 2605 }; 2606 2607 #define PCI_EMUL_MSI_MSGS 4 2608 #define PCI_EMUL_MSIX_MSGS 16 2609 2610 static int 2611 pci_emul_dinit(struct pci_devinst *pi, nvlist_t *nvl __unused) 2612 { 2613 int error; 2614 struct pci_emul_dsoftc *sc; 2615 2616 sc = calloc(1, sizeof(struct pci_emul_dsoftc)); 2617 2618 pi->pi_arg = sc; 2619 2620 pci_set_cfgdata16(pi, PCIR_DEVICE, 0x0001); 2621 pci_set_cfgdata16(pi, PCIR_VENDOR, 0x10DD); 2622 pci_set_cfgdata8(pi, PCIR_CLASS, 0x02); 2623 2624 error = pci_emul_add_msicap(pi, PCI_EMUL_MSI_MSGS); 2625 assert(error == 0); 2626 2627 pci_emul_alloc_bar(pi, 0, PCIBAR_IO, DIOSZ); 2628 pci_emul_alloc_bar(pi, 1, PCIBAR_MEM32, DMEMSZ); 2629 pci_emul_alloc_bar(pi, 2, PCIBAR_MEM32, DMEMSZ); 2630 2631 return (0); 2632 } 2633 2634 static void 2635 pci_emul_diow(struct pci_devinst *pi, int baridx, uint64_t offset, int size, 2636 uint64_t value) 2637 { 2638 int i; 2639 struct pci_emul_dsoftc *sc = pi->pi_arg; 2640 2641 if (baridx == 0) { 2642 if (offset + size > DIOSZ) { 2643 printf("diow: iow too large, offset %ld size %d\n", 2644 offset, size); 2645 return; 2646 } 2647 2648 if (size == 1) { 2649 sc->ioregs[offset] = value & 0xff; 2650 } else if (size == 2) { 2651 *(uint16_t *)&sc->ioregs[offset] = value & 0xffff; 2652 } else if (size == 4) { 2653 *(uint32_t *)&sc->ioregs[offset] = value; 2654 } else { 2655 printf("diow: iow unknown size %d\n", size); 2656 } 2657 2658 /* 2659 * Special magic value to generate an interrupt 2660 */ 2661 if (offset == 4 && size == 4 && pci_msi_enabled(pi)) 2662 pci_generate_msi(pi, value % pci_msi_maxmsgnum(pi)); 2663 2664 if (value == 0xabcdef) { 2665 for (i = 0; i < pci_msi_maxmsgnum(pi); i++) 2666 pci_generate_msi(pi, i); 2667 } 2668 } 2669 2670 if (baridx == 1 || baridx == 2) { 2671 if (offset + size > DMEMSZ) { 2672 printf("diow: memw too large, offset %ld size %d\n", 2673 offset, size); 2674 return; 2675 } 2676 2677 i = baridx - 1; /* 'memregs' index */ 2678 2679 if (size == 1) { 2680 sc->memregs[i][offset] = value; 2681 } else if (size == 2) { 2682 *(uint16_t *)&sc->memregs[i][offset] = value; 2683 } else if (size == 4) { 2684 *(uint32_t *)&sc->memregs[i][offset] = value; 2685 } else if (size == 8) { 2686 *(uint64_t *)&sc->memregs[i][offset] = value; 2687 } else { 2688 printf("diow: memw unknown size %d\n", size); 2689 } 2690 2691 /* 2692 * magic interrupt ?? 2693 */ 2694 } 2695 2696 if (baridx > 2 || baridx < 0) { 2697 printf("diow: unknown bar idx %d\n", baridx); 2698 } 2699 } 2700 2701 static uint64_t 2702 pci_emul_dior(struct pci_devinst *pi, int baridx, uint64_t offset, int size) 2703 { 2704 struct pci_emul_dsoftc *sc = pi->pi_arg; 2705 uint32_t value; 2706 int i; 2707 2708 if (baridx == 0) { 2709 if (offset + size > DIOSZ) { 2710 printf("dior: ior too large, offset %ld size %d\n", 2711 offset, size); 2712 return (0); 2713 } 2714 2715 value = 0; 2716 if (size == 1) { 2717 value = sc->ioregs[offset]; 2718 } else if (size == 2) { 2719 value = *(uint16_t *) &sc->ioregs[offset]; 2720 } else if (size == 4) { 2721 value = *(uint32_t *) &sc->ioregs[offset]; 2722 } else { 2723 printf("dior: ior unknown size %d\n", size); 2724 } 2725 } 2726 2727 if (baridx == 1 || baridx == 2) { 2728 if (offset + size > DMEMSZ) { 2729 printf("dior: memr too large, offset %ld size %d\n", 2730 offset, size); 2731 return (0); 2732 } 2733 2734 i = baridx - 1; /* 'memregs' index */ 2735 2736 if (size == 1) { 2737 value = sc->memregs[i][offset]; 2738 } else if (size == 2) { 2739 value = *(uint16_t *) &sc->memregs[i][offset]; 2740 } else if (size == 4) { 2741 value = *(uint32_t *) &sc->memregs[i][offset]; 2742 } else if (size == 8) { 2743 value = *(uint64_t *) &sc->memregs[i][offset]; 2744 } else { 2745 printf("dior: ior unknown size %d\n", size); 2746 } 2747 } 2748 2749 2750 if (baridx > 2 || baridx < 0) { 2751 printf("dior: unknown bar idx %d\n", baridx); 2752 return (0); 2753 } 2754 2755 return (value); 2756 } 2757 2758 #ifdef BHYVE_SNAPSHOT 2759 struct pci_devinst * 2760 pci_next(const struct pci_devinst *cursor) 2761 { 2762 unsigned bus = 0, slot = 0, func = 0; 2763 struct businfo *bi; 2764 struct slotinfo *si; 2765 struct funcinfo *fi; 2766 2767 bus = cursor ? cursor->pi_bus : 0; 2768 slot = cursor ? cursor->pi_slot : 0; 2769 func = cursor ? (cursor->pi_func + 1) : 0; 2770 2771 for (; bus < MAXBUSES; bus++) { 2772 if ((bi = pci_businfo[bus]) == NULL) 2773 continue; 2774 2775 if (slot >= MAXSLOTS) 2776 slot = 0; 2777 2778 for (; slot < MAXSLOTS; slot++) { 2779 si = &bi->slotinfo[slot]; 2780 if (func >= MAXFUNCS) 2781 func = 0; 2782 for (; func < MAXFUNCS; func++) { 2783 fi = &si->si_funcs[func]; 2784 if (fi->fi_devi == NULL) 2785 continue; 2786 2787 return (fi->fi_devi); 2788 } 2789 } 2790 } 2791 2792 return (NULL); 2793 } 2794 2795 static int 2796 pci_emul_snapshot(struct vm_snapshot_meta *meta __unused) 2797 { 2798 return (0); 2799 } 2800 #endif 2801 2802 static const struct pci_devemu pci_dummy = { 2803 .pe_emu = "dummy", 2804 .pe_init = pci_emul_dinit, 2805 .pe_barwrite = pci_emul_diow, 2806 .pe_barread = pci_emul_dior, 2807 #ifdef BHYVE_SNAPSHOT 2808 .pe_snapshot = pci_emul_snapshot, 2809 #endif 2810 }; 2811 PCI_EMUL_SET(pci_dummy); 2812 2813 #endif /* PCI_EMUL_TEST */ 2814