1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Rockchip Generic power domain support.
4 *
5 * Copyright (c) 2015 Rockchip Electronics Co., Ltd.
6 */
7
8 #include <linux/arm-smccc.h>
9 #include <linux/io.h>
10 #include <linux/iopoll.h>
11 #include <linux/err.h>
12 #include <linux/mutex.h>
13 #include <linux/platform_device.h>
14 #include <linux/pm_clock.h>
15 #include <linux/pm_domain.h>
16 #include <linux/property.h>
17 #include <linux/of.h>
18 #include <linux/of_address.h>
19 #include <linux/of_clk.h>
20 #include <linux/clk.h>
21 #include <linux/regmap.h>
22 #include <linux/regulator/consumer.h>
23 #include <linux/mfd/syscon.h>
24 #include <soc/rockchip/pm_domains.h>
25 #include <soc/rockchip/rockchip_sip.h>
26 #include <dt-bindings/power/px30-power.h>
27 #include <dt-bindings/power/rockchip,rv1126-power.h>
28 #include <dt-bindings/power/rockchip,rv1126b-power-controller.h>
29 #include <dt-bindings/power/rk3036-power.h>
30 #include <dt-bindings/power/rk3066-power.h>
31 #include <dt-bindings/power/rk3128-power.h>
32 #include <dt-bindings/power/rk3188-power.h>
33 #include <dt-bindings/power/rk3228-power.h>
34 #include <dt-bindings/power/rk3288-power.h>
35 #include <dt-bindings/power/rk3328-power.h>
36 #include <dt-bindings/power/rk3366-power.h>
37 #include <dt-bindings/power/rk3368-power.h>
38 #include <dt-bindings/power/rk3399-power.h>
39 #include <dt-bindings/power/rockchip,rk3528-power.h>
40 #include <dt-bindings/power/rockchip,rk3562-power.h>
41 #include <dt-bindings/power/rk3568-power.h>
42 #include <dt-bindings/power/rockchip,rk3576-power.h>
43 #include <dt-bindings/power/rk3588-power.h>
44
45 struct rockchip_domain_info {
46 const char *name;
47 int pwr_mask;
48 int status_mask;
49 int req_mask;
50 int idle_mask;
51 int ack_mask;
52 bool active_wakeup;
53 bool need_regulator;
54 int pwr_w_mask;
55 int req_w_mask;
56 int clk_ungate_mask;
57 int mem_status_mask;
58 int repair_status_mask;
59 u32 pwr_offset;
60 u32 mem_offset;
61 u32 req_offset;
62 };
63
64 struct rockchip_pmu_info {
65 u32 pwr_offset;
66 u32 status_offset;
67 u32 req_offset;
68 u32 idle_offset;
69 u32 ack_offset;
70 u32 mem_pwr_offset;
71 u32 chain_status_offset;
72 u32 mem_status_offset;
73 u32 repair_status_offset;
74 u32 clk_ungate_offset;
75
76 u32 core_pwrcnt_offset;
77 u32 gpu_pwrcnt_offset;
78
79 unsigned int core_power_transition_time;
80 unsigned int gpu_power_transition_time;
81
82 int num_domains;
83 const struct rockchip_domain_info *domain_info;
84 };
85
86 #define MAX_QOS_REGS_NUM 5
87 #define QOS_PRIORITY 0x08
88 #define QOS_MODE 0x0c
89 #define QOS_BANDWIDTH 0x10
90 #define QOS_SATURATION 0x14
91 #define QOS_EXTCONTROL 0x18
92
93 struct rockchip_pm_domain {
94 struct generic_pm_domain genpd;
95 const struct rockchip_domain_info *info;
96 struct rockchip_pmu *pmu;
97 int num_qos;
98 struct regmap **qos_regmap;
99 u32 *qos_save_regs[MAX_QOS_REGS_NUM];
100 int num_clks;
101 struct clk_bulk_data *clks;
102 struct device_node *node;
103 struct regulator *supply;
104 };
105
106 struct rockchip_pmu {
107 struct device *dev;
108 struct regmap *regmap;
109 const struct rockchip_pmu_info *info;
110 struct mutex mutex; /* mutex lock for pmu */
111 struct genpd_onecell_data genpd_data;
112 struct generic_pm_domain *domains[];
113 };
114
115 #define to_rockchip_pd(gpd) container_of(gpd, struct rockchip_pm_domain, genpd)
116
117 #define DOMAIN(_name, pwr, status, req, idle, ack, wakeup) \
118 { \
119 .name = _name, \
120 .pwr_mask = (pwr), \
121 .status_mask = (status), \
122 .req_mask = (req), \
123 .idle_mask = (idle), \
124 .ack_mask = (ack), \
125 .active_wakeup = (wakeup), \
126 }
127
128 #define DOMAIN_M(_name, pwr, status, req, idle, ack, wakeup) \
129 { \
130 .name = _name, \
131 .pwr_w_mask = (pwr) << 16, \
132 .pwr_mask = (pwr), \
133 .status_mask = (status), \
134 .req_w_mask = (req) << 16, \
135 .req_mask = (req), \
136 .idle_mask = (idle), \
137 .ack_mask = (ack), \
138 .active_wakeup = wakeup, \
139 }
140
141 #define DOMAIN_M_G(_name, pwr, status, req, idle, ack, g_mask, wakeup, keepon) \
142 { \
143 .name = _name, \
144 .pwr_w_mask = (pwr) << 16, \
145 .pwr_mask = (pwr), \
146 .status_mask = (status), \
147 .req_w_mask = (req) << 16, \
148 .req_mask = (req), \
149 .idle_mask = (idle), \
150 .ack_mask = (ack), \
151 .clk_ungate_mask = (g_mask), \
152 .active_wakeup = wakeup, \
153 }
154
155 #define DOMAIN_M_G_SD(_name, pwr, status, req, idle, ack, g_mask, mem, wakeup, keepon) \
156 { \
157 .name = _name, \
158 .pwr_w_mask = (pwr) << 16, \
159 .pwr_mask = (pwr), \
160 .status_mask = (status), \
161 .req_w_mask = (req) << 16, \
162 .req_mask = (req), \
163 .idle_mask = (idle), \
164 .ack_mask = (ack), \
165 .clk_ungate_mask = (g_mask), \
166 .active_wakeup = wakeup, \
167 }
168
169 #define DOMAIN_M_O_R(_name, p_offset, pwr, status, m_offset, m_status, r_status, r_offset, req, idle, ack, wakeup, regulator) \
170 { \
171 .name = _name, \
172 .pwr_offset = p_offset, \
173 .pwr_w_mask = (pwr) << 16, \
174 .pwr_mask = (pwr), \
175 .status_mask = (status), \
176 .mem_offset = m_offset, \
177 .mem_status_mask = (m_status), \
178 .repair_status_mask = (r_status), \
179 .req_offset = r_offset, \
180 .req_w_mask = (req) << 16, \
181 .req_mask = (req), \
182 .idle_mask = (idle), \
183 .ack_mask = (ack), \
184 .active_wakeup = wakeup, \
185 .need_regulator = regulator, \
186 }
187
188 #define DOMAIN_M_O_R_G(_name, p_offset, pwr, status, m_offset, m_status, r_status, r_offset, req, idle, ack, g_mask, wakeup) \
189 { \
190 .name = _name, \
191 .pwr_offset = p_offset, \
192 .pwr_w_mask = (pwr) << 16, \
193 .pwr_mask = (pwr), \
194 .status_mask = (status), \
195 .mem_offset = m_offset, \
196 .mem_status_mask = (m_status), \
197 .repair_status_mask = (r_status), \
198 .req_offset = r_offset, \
199 .req_w_mask = (req) << 16, \
200 .req_mask = (req), \
201 .idle_mask = (idle), \
202 .clk_ungate_mask = (g_mask), \
203 .ack_mask = (ack), \
204 .active_wakeup = wakeup, \
205 }
206
207 #define DOMAIN_M_R(_name, pwr, status, req, idle, ack, wakeup, regulator) \
208 { \
209 .name = _name, \
210 .pwr_w_mask = (pwr) << 16, \
211 .pwr_mask = (pwr), \
212 .status_mask = (status), \
213 .req_w_mask = (req) << 16, \
214 .req_mask = (req), \
215 .idle_mask = (idle), \
216 .ack_mask = (ack), \
217 .active_wakeup = wakeup, \
218 .need_regulator = regulator, \
219 }
220
221 #define DOMAIN_RK3036(_name, req, ack, idle, wakeup) \
222 { \
223 .name = _name, \
224 .req_mask = (req), \
225 .req_w_mask = (req) << 16, \
226 .ack_mask = (ack), \
227 .idle_mask = (idle), \
228 .active_wakeup = wakeup, \
229 }
230
231 #define DOMAIN_PX30(name, pwr, status, req, wakeup) \
232 DOMAIN_M(name, pwr, status, req, (req) << 16, req, wakeup)
233
234 #define DOMAIN_RV1126(name, pwr, req, idle, wakeup) \
235 DOMAIN_M(name, pwr, pwr, req, idle, idle, wakeup)
236
237 #define DOMAIN_RV1126B(name, pwr, req, wakeup) \
238 DOMAIN_M_G(name, pwr, pwr, req, req, req, req, wakeup, true)
239
240 #define DOMAIN_RK3288(name, pwr, status, req, wakeup) \
241 DOMAIN(name, pwr, status, req, req, (req) << 16, wakeup)
242
243 #define DOMAIN_RK3328(name, pwr, status, req, wakeup) \
244 DOMAIN_M(name, pwr, pwr, req, (req) << 10, req, wakeup)
245
246 #define DOMAIN_RK3368(name, pwr, status, req, wakeup) \
247 DOMAIN(name, pwr, status, req, (req) << 16, req, wakeup)
248
249 #define DOMAIN_RK3399(name, pwr, status, req, wakeup) \
250 DOMAIN(name, pwr, status, req, req, req, wakeup)
251
252 #define DOMAIN_RK3528(name, pwr, req) \
253 DOMAIN_M(name, pwr, pwr, req, req, req, false)
254
255 #define DOMAIN_RK3562(name, pwr, req, g_mask, mem, wakeup) \
256 DOMAIN_M_G_SD(name, pwr, pwr, req, req, req, g_mask, mem, wakeup, false)
257
258 #define DOMAIN_RK3568(name, pwr, req, wakeup, regulator) \
259 DOMAIN_M_R(name, pwr, pwr, req, req, req, wakeup, regulator)
260
261 #define DOMAIN_RK3576(name, p_offset, pwr, status, r_status, r_offset, req, idle, g_mask, wakeup) \
262 DOMAIN_M_O_R_G(name, p_offset, pwr, status, 0, r_status, r_status, r_offset, req, idle, idle, g_mask, wakeup)
263
264 /*
265 * Dynamic Memory Controller may need to coordinate with us -- see
266 * rockchip_pmu_block().
267 *
268 * dmc_pmu_mutex protects registration-time races, so DMC driver doesn't try to
269 * block() while we're initializing the PMU.
270 */
271 static DEFINE_MUTEX(dmc_pmu_mutex);
272 static struct rockchip_pmu *dmc_pmu;
273
274 /*
275 * Block PMU transitions and make sure they don't interfere with ARM Trusted
276 * Firmware operations. There are two conflicts, noted in the comments below.
277 *
278 * Caller must unblock PMU transitions via rockchip_pmu_unblock().
279 */
rockchip_pmu_block(void)280 int rockchip_pmu_block(void)
281 {
282 struct rockchip_pmu *pmu;
283 struct generic_pm_domain *genpd;
284 struct rockchip_pm_domain *pd;
285 int i, ret;
286
287 mutex_lock(&dmc_pmu_mutex);
288
289 /* No PMU (yet)? Then we just block rockchip_pmu_probe(). */
290 if (!dmc_pmu)
291 return 0;
292 pmu = dmc_pmu;
293
294 /*
295 * mutex blocks all idle transitions: we can't touch the
296 * PMU_BUS_IDLE_REQ (our ".idle_offset") register while ARM Trusted
297 * Firmware might be using it.
298 */
299 mutex_lock(&pmu->mutex);
300
301 /*
302 * Power domain clocks: Per Rockchip, we *must* keep certain clocks
303 * enabled for the duration of power-domain transitions. Most
304 * transitions are handled by this driver, but some cases (in
305 * particular, DRAM DVFS / memory-controller idle) must be handled by
306 * firmware. Firmware can handle most clock management via a special
307 * "ungate" register (PMU_CRU_GATEDIS_CON0), but unfortunately, this
308 * doesn't handle PLLs. We can assist this transition by doing the
309 * clock management on behalf of firmware.
310 */
311 for (i = 0; i < pmu->genpd_data.num_domains; i++) {
312 genpd = pmu->genpd_data.domains[i];
313 if (genpd) {
314 pd = to_rockchip_pd(genpd);
315 ret = clk_bulk_enable(pd->num_clks, pd->clks);
316 if (ret < 0) {
317 dev_err(pmu->dev,
318 "failed to enable clks for domain '%s': %d\n",
319 genpd->name, ret);
320 goto err;
321 }
322 }
323 }
324
325 return 0;
326
327 err:
328 for (i = i - 1; i >= 0; i--) {
329 genpd = pmu->genpd_data.domains[i];
330 if (genpd) {
331 pd = to_rockchip_pd(genpd);
332 clk_bulk_disable(pd->num_clks, pd->clks);
333 }
334 }
335 mutex_unlock(&pmu->mutex);
336 mutex_unlock(&dmc_pmu_mutex);
337
338 return ret;
339 }
340 EXPORT_SYMBOL_GPL(rockchip_pmu_block);
341
342 /* Unblock PMU transitions. */
rockchip_pmu_unblock(void)343 void rockchip_pmu_unblock(void)
344 {
345 struct rockchip_pmu *pmu;
346 struct generic_pm_domain *genpd;
347 struct rockchip_pm_domain *pd;
348 int i;
349
350 if (dmc_pmu) {
351 pmu = dmc_pmu;
352 for (i = 0; i < pmu->genpd_data.num_domains; i++) {
353 genpd = pmu->genpd_data.domains[i];
354 if (genpd) {
355 pd = to_rockchip_pd(genpd);
356 clk_bulk_disable(pd->num_clks, pd->clks);
357 }
358 }
359
360 mutex_unlock(&pmu->mutex);
361 }
362
363 mutex_unlock(&dmc_pmu_mutex);
364 }
365 EXPORT_SYMBOL_GPL(rockchip_pmu_unblock);
366
367 #define DOMAIN_RK3588(name, p_offset, pwr, status, m_offset, m_status, r_status, r_offset, req, idle, wakeup, regulator) \
368 DOMAIN_M_O_R(name, p_offset, pwr, status, m_offset, m_status, r_status, r_offset, req, idle, idle, wakeup, regulator)
369
rockchip_pmu_domain_is_idle(struct rockchip_pm_domain * pd)370 static bool rockchip_pmu_domain_is_idle(struct rockchip_pm_domain *pd)
371 {
372 struct rockchip_pmu *pmu = pd->pmu;
373 const struct rockchip_domain_info *pd_info = pd->info;
374 unsigned int val;
375
376 regmap_read(pmu->regmap, pmu->info->idle_offset, &val);
377 return (val & pd_info->idle_mask) == pd_info->idle_mask;
378 }
379
rockchip_pmu_read_ack(struct rockchip_pmu * pmu)380 static unsigned int rockchip_pmu_read_ack(struct rockchip_pmu *pmu)
381 {
382 unsigned int val;
383
384 regmap_read(pmu->regmap, pmu->info->ack_offset, &val);
385 return val;
386 }
387
rockchip_pmu_ungate_clk(struct rockchip_pm_domain * pd,bool ungate)388 static int rockchip_pmu_ungate_clk(struct rockchip_pm_domain *pd, bool ungate)
389 {
390 const struct rockchip_domain_info *pd_info = pd->info;
391 struct rockchip_pmu *pmu = pd->pmu;
392 unsigned int val;
393 int clk_ungate_w_mask = pd_info->clk_ungate_mask << 16;
394
395 if (!pd_info->clk_ungate_mask)
396 return 0;
397
398 if (!pmu->info->clk_ungate_offset)
399 return 0;
400
401 val = ungate ? (pd_info->clk_ungate_mask | clk_ungate_w_mask) :
402 clk_ungate_w_mask;
403 regmap_write(pmu->regmap, pmu->info->clk_ungate_offset, val);
404
405 return 0;
406 }
407
rockchip_pmu_set_idle_request(struct rockchip_pm_domain * pd,bool idle)408 static int rockchip_pmu_set_idle_request(struct rockchip_pm_domain *pd,
409 bool idle)
410 {
411 const struct rockchip_domain_info *pd_info = pd->info;
412 struct generic_pm_domain *genpd = &pd->genpd;
413 struct rockchip_pmu *pmu = pd->pmu;
414 u32 pd_req_offset = pd_info->req_offset;
415 unsigned int target_ack;
416 unsigned int val;
417 bool is_idle;
418 int ret;
419
420 if (pd_info->req_mask == 0)
421 return 0;
422 else if (pd_info->req_w_mask)
423 regmap_write(pmu->regmap, pmu->info->req_offset + pd_req_offset,
424 idle ? (pd_info->req_mask | pd_info->req_w_mask) :
425 pd_info->req_w_mask);
426 else
427 regmap_update_bits(pmu->regmap, pmu->info->req_offset + pd_req_offset,
428 pd_info->req_mask, idle ? -1U : 0);
429
430 wmb();
431
432 /* Wait util idle_ack = 1 */
433 target_ack = idle ? pd_info->ack_mask : 0;
434 ret = readx_poll_timeout_atomic(rockchip_pmu_read_ack, pmu, val,
435 (val & pd_info->ack_mask) == target_ack,
436 0, 10000);
437 if (ret) {
438 dev_err(pmu->dev,
439 "failed to get ack on domain '%s', val=0x%x\n",
440 genpd->name, val);
441 return ret;
442 }
443
444 ret = readx_poll_timeout_atomic(rockchip_pmu_domain_is_idle, pd,
445 is_idle, is_idle == idle, 0, 10000);
446 if (ret) {
447 dev_err(pmu->dev,
448 "failed to set idle on domain '%s', val=%d\n",
449 genpd->name, is_idle);
450 return ret;
451 }
452
453 return 0;
454 }
455
rockchip_pmu_save_qos(struct rockchip_pm_domain * pd)456 static int rockchip_pmu_save_qos(struct rockchip_pm_domain *pd)
457 {
458 int i;
459
460 for (i = 0; i < pd->num_qos; i++) {
461 regmap_read(pd->qos_regmap[i],
462 QOS_PRIORITY,
463 &pd->qos_save_regs[0][i]);
464 regmap_read(pd->qos_regmap[i],
465 QOS_MODE,
466 &pd->qos_save_regs[1][i]);
467 regmap_read(pd->qos_regmap[i],
468 QOS_BANDWIDTH,
469 &pd->qos_save_regs[2][i]);
470 regmap_read(pd->qos_regmap[i],
471 QOS_SATURATION,
472 &pd->qos_save_regs[3][i]);
473 regmap_read(pd->qos_regmap[i],
474 QOS_EXTCONTROL,
475 &pd->qos_save_regs[4][i]);
476 }
477 return 0;
478 }
479
rockchip_pmu_restore_qos(struct rockchip_pm_domain * pd)480 static int rockchip_pmu_restore_qos(struct rockchip_pm_domain *pd)
481 {
482 int i;
483
484 for (i = 0; i < pd->num_qos; i++) {
485 regmap_write(pd->qos_regmap[i],
486 QOS_PRIORITY,
487 pd->qos_save_regs[0][i]);
488 regmap_write(pd->qos_regmap[i],
489 QOS_MODE,
490 pd->qos_save_regs[1][i]);
491 regmap_write(pd->qos_regmap[i],
492 QOS_BANDWIDTH,
493 pd->qos_save_regs[2][i]);
494 regmap_write(pd->qos_regmap[i],
495 QOS_SATURATION,
496 pd->qos_save_regs[3][i]);
497 regmap_write(pd->qos_regmap[i],
498 QOS_EXTCONTROL,
499 pd->qos_save_regs[4][i]);
500 }
501
502 return 0;
503 }
504
rockchip_pmu_domain_is_on(struct rockchip_pm_domain * pd)505 static bool rockchip_pmu_domain_is_on(struct rockchip_pm_domain *pd)
506 {
507 struct rockchip_pmu *pmu = pd->pmu;
508 unsigned int val;
509
510 if (pd->info->repair_status_mask) {
511 regmap_read(pmu->regmap, pmu->info->repair_status_offset, &val);
512 /* 1'b1: power on, 1'b0: power off */
513 return val & pd->info->repair_status_mask;
514 }
515
516 /* check idle status for idle-only domains */
517 if (pd->info->status_mask == 0)
518 return !rockchip_pmu_domain_is_idle(pd);
519
520 regmap_read(pmu->regmap, pmu->info->status_offset, &val);
521
522 /* 1'b0: power on, 1'b1: power off */
523 return !(val & pd->info->status_mask);
524 }
525
rockchip_pmu_domain_is_mem_on(struct rockchip_pm_domain * pd)526 static bool rockchip_pmu_domain_is_mem_on(struct rockchip_pm_domain *pd)
527 {
528 struct rockchip_pmu *pmu = pd->pmu;
529 unsigned int val;
530
531 regmap_read(pmu->regmap,
532 pmu->info->mem_status_offset + pd->info->mem_offset, &val);
533
534 /* 1'b0: power on, 1'b1: power off */
535 return !(val & pd->info->mem_status_mask);
536 }
537
rockchip_pmu_domain_is_chain_on(struct rockchip_pm_domain * pd)538 static bool rockchip_pmu_domain_is_chain_on(struct rockchip_pm_domain *pd)
539 {
540 struct rockchip_pmu *pmu = pd->pmu;
541 unsigned int val;
542
543 regmap_read(pmu->regmap,
544 pmu->info->chain_status_offset + pd->info->mem_offset, &val);
545
546 /* 1'b1: power on, 1'b0: power off */
547 return val & pd->info->mem_status_mask;
548 }
549
rockchip_pmu_domain_mem_reset(struct rockchip_pm_domain * pd)550 static int rockchip_pmu_domain_mem_reset(struct rockchip_pm_domain *pd)
551 {
552 struct rockchip_pmu *pmu = pd->pmu;
553 struct generic_pm_domain *genpd = &pd->genpd;
554 bool is_on;
555 int ret = 0;
556
557 ret = readx_poll_timeout_atomic(rockchip_pmu_domain_is_chain_on, pd, is_on,
558 is_on == true, 0, 10000);
559 if (ret) {
560 dev_err(pmu->dev,
561 "failed to get chain status '%s', target_on=1, val=%d\n",
562 genpd->name, is_on);
563 goto error;
564 }
565
566 udelay(20);
567
568 regmap_write(pmu->regmap, pmu->info->mem_pwr_offset + pd->info->pwr_offset,
569 (pd->info->pwr_mask | pd->info->pwr_w_mask));
570 wmb();
571
572 ret = readx_poll_timeout_atomic(rockchip_pmu_domain_is_mem_on, pd, is_on,
573 is_on == false, 0, 10000);
574 if (ret) {
575 dev_err(pmu->dev,
576 "failed to get mem status '%s', target_on=0, val=%d\n",
577 genpd->name, is_on);
578 goto error;
579 }
580
581 regmap_write(pmu->regmap, pmu->info->mem_pwr_offset + pd->info->pwr_offset,
582 pd->info->pwr_w_mask);
583 wmb();
584
585 ret = readx_poll_timeout_atomic(rockchip_pmu_domain_is_mem_on, pd, is_on,
586 is_on == true, 0, 10000);
587 if (ret) {
588 dev_err(pmu->dev,
589 "failed to get mem status '%s', target_on=1, val=%d\n",
590 genpd->name, is_on);
591 }
592
593 error:
594 return ret;
595 }
596
rockchip_do_pmu_set_power_domain(struct rockchip_pm_domain * pd,bool on)597 static int rockchip_do_pmu_set_power_domain(struct rockchip_pm_domain *pd,
598 bool on)
599 {
600 struct rockchip_pmu *pmu = pd->pmu;
601 struct generic_pm_domain *genpd = &pd->genpd;
602 u32 pd_pwr_offset = pd->info->pwr_offset;
603 bool is_on, is_mem_on = false;
604 struct arm_smccc_res res;
605 int ret;
606
607 if (pd->info->pwr_mask == 0)
608 return 0;
609
610 if (on && pd->info->mem_status_mask)
611 is_mem_on = rockchip_pmu_domain_is_mem_on(pd);
612
613 if (pd->info->pwr_w_mask)
614 regmap_write(pmu->regmap, pmu->info->pwr_offset + pd_pwr_offset,
615 on ? pd->info->pwr_w_mask :
616 (pd->info->pwr_mask | pd->info->pwr_w_mask));
617 else
618 regmap_update_bits(pmu->regmap, pmu->info->pwr_offset + pd_pwr_offset,
619 pd->info->pwr_mask, on ? 0 : -1U);
620
621 wmb();
622
623 if (is_mem_on) {
624 ret = rockchip_pmu_domain_mem_reset(pd);
625 if (ret)
626 return ret;
627 }
628
629
630 ret = readx_poll_timeout_atomic(rockchip_pmu_domain_is_on, pd, is_on,
631 is_on == on, 0, 10000);
632 if (ret) {
633 dev_err(pmu->dev, "failed to set domain '%s' %s, val=%d\n",
634 genpd->name, on ? "on" : "off", is_on);
635 return ret;
636 }
637
638 /* Inform firmware to keep this pd on or off */
639 if (arm_smccc_1_1_get_conduit() != SMCCC_CONDUIT_NONE)
640 arm_smccc_smc(ROCKCHIP_SIP_SUSPEND_MODE, ROCKCHIP_SLEEP_PD_CONFIG,
641 pmu->info->pwr_offset + pd_pwr_offset,
642 pd->info->pwr_mask, on, 0, 0, 0, &res);
643
644 return 0;
645 }
646
rockchip_pd_power(struct rockchip_pm_domain * pd,bool power_on)647 static int rockchip_pd_power(struct rockchip_pm_domain *pd, bool power_on)
648 {
649 struct rockchip_pmu *pmu = pd->pmu;
650 int ret;
651
652 guard(mutex)(&pmu->mutex);
653
654 if (rockchip_pmu_domain_is_on(pd) == power_on)
655 return 0;
656
657 ret = clk_bulk_enable(pd->num_clks, pd->clks);
658 if (ret < 0) {
659 dev_err(pmu->dev, "failed to enable clocks\n");
660 return ret;
661 }
662
663 rockchip_pmu_ungate_clk(pd, true);
664
665 if (!power_on) {
666 rockchip_pmu_save_qos(pd);
667
668 /* if powering down, idle request to NIU first */
669 ret = rockchip_pmu_set_idle_request(pd, true);
670 if (ret < 0)
671 goto out;
672 }
673
674 ret = rockchip_do_pmu_set_power_domain(pd, power_on);
675 if (ret < 0)
676 goto out;
677
678 if (power_on) {
679 /* if powering up, leave idle mode */
680 ret = rockchip_pmu_set_idle_request(pd, false);
681 if (ret < 0)
682 goto out;
683
684 rockchip_pmu_restore_qos(pd);
685 }
686
687 out:
688 rockchip_pmu_ungate_clk(pd, false);
689 clk_bulk_disable(pd->num_clks, pd->clks);
690
691 return ret;
692 }
693
rockchip_pd_regulator_disable(struct rockchip_pm_domain * pd)694 static int rockchip_pd_regulator_disable(struct rockchip_pm_domain *pd)
695 {
696 return IS_ERR_OR_NULL(pd->supply) ? 0 : regulator_disable(pd->supply);
697 }
698
rockchip_pd_regulator_enable(struct rockchip_pm_domain * pd)699 static int rockchip_pd_regulator_enable(struct rockchip_pm_domain *pd)
700 {
701 struct rockchip_pmu *pmu = pd->pmu;
702
703 if (!pd->info->need_regulator)
704 return 0;
705
706 if (IS_ERR_OR_NULL(pd->supply)) {
707 pd->supply = devm_of_regulator_get(pmu->dev, pd->node, "domain");
708
709 if (IS_ERR(pd->supply))
710 return PTR_ERR(pd->supply);
711 }
712
713 return regulator_enable(pd->supply);
714 }
715
rockchip_pd_power_on(struct generic_pm_domain * domain)716 static int rockchip_pd_power_on(struct generic_pm_domain *domain)
717 {
718 struct rockchip_pm_domain *pd = to_rockchip_pd(domain);
719 int ret;
720
721 ret = rockchip_pd_regulator_enable(pd);
722 if (ret)
723 return dev_err_probe(pd->pmu->dev, ret,
724 "Failed to enable supply: %d\n", ret);
725
726 ret = rockchip_pd_power(pd, true);
727 if (ret)
728 rockchip_pd_regulator_disable(pd);
729
730 return ret;
731 }
732
rockchip_pd_power_off(struct generic_pm_domain * domain)733 static int rockchip_pd_power_off(struct generic_pm_domain *domain)
734 {
735 struct rockchip_pm_domain *pd = to_rockchip_pd(domain);
736 int ret;
737
738 ret = rockchip_pd_power(pd, false);
739 if (ret)
740 return ret;
741
742 rockchip_pd_regulator_disable(pd);
743 return ret;
744 }
745
rockchip_pd_attach_dev(struct generic_pm_domain * genpd,struct device * dev)746 static int rockchip_pd_attach_dev(struct generic_pm_domain *genpd,
747 struct device *dev)
748 {
749 struct clk *clk;
750 int i;
751 int error;
752
753 dev_dbg(dev, "attaching to power domain '%s'\n", genpd->name);
754
755 error = pm_clk_create(dev);
756 if (error) {
757 dev_err(dev, "pm_clk_create failed %d\n", error);
758 return error;
759 }
760
761 i = 0;
762 while (1) {
763 clk = of_clk_get(dev->of_node, i++);
764 if (IS_ERR(clk)) {
765 error = PTR_ERR(clk);
766 if (error == -ENOENT)
767 break;
768
769 dev_err(dev, "failed to get clock %d: %d\n", i - 1,
770 error);
771 pm_clk_destroy(dev);
772 return error;
773 }
774
775 dev_dbg(dev, "adding clock '%pC' to list of PM clocks\n", clk);
776 error = pm_clk_add_clk(dev, clk);
777 if (error) {
778 dev_err(dev, "pm_clk_add_clk failed %d\n", error);
779 clk_put(clk);
780 pm_clk_destroy(dev);
781 return error;
782 }
783 }
784
785 return 0;
786 }
787
rockchip_pd_detach_dev(struct generic_pm_domain * genpd,struct device * dev)788 static void rockchip_pd_detach_dev(struct generic_pm_domain *genpd,
789 struct device *dev)
790 {
791 dev_dbg(dev, "detaching from power domain '%s'\n", genpd->name);
792
793 pm_clk_destroy(dev);
794 }
795
rockchip_pm_add_one_domain(struct rockchip_pmu * pmu,struct device_node * node)796 static int rockchip_pm_add_one_domain(struct rockchip_pmu *pmu,
797 struct device_node *node)
798 {
799 const struct rockchip_domain_info *pd_info;
800 struct rockchip_pm_domain *pd;
801 struct device_node *qos_node;
802 int i, j;
803 u32 id;
804 int error;
805
806 error = of_property_read_u32(node, "reg", &id);
807 if (error) {
808 dev_err(pmu->dev,
809 "%pOFn: failed to retrieve domain id (reg): %d\n",
810 node, error);
811 return -EINVAL;
812 }
813
814 if (id >= pmu->info->num_domains) {
815 dev_err(pmu->dev, "%pOFn: invalid domain id %d\n",
816 node, id);
817 return -EINVAL;
818 }
819 /* RK3588 has domains with two parents (RKVDEC0/RKVDEC1) */
820 if (pmu->genpd_data.domains[id])
821 return 0;
822
823 pd_info = &pmu->info->domain_info[id];
824 if (!pd_info) {
825 dev_err(pmu->dev, "%pOFn: undefined domain id %d\n",
826 node, id);
827 return -EINVAL;
828 }
829
830 pd = devm_kzalloc(pmu->dev, sizeof(*pd), GFP_KERNEL);
831 if (!pd)
832 return -ENOMEM;
833
834 pd->info = pd_info;
835 pd->pmu = pmu;
836 pd->node = node;
837
838 pd->num_clks = of_clk_get_parent_count(node);
839 if (pd->num_clks > 0) {
840 pd->clks = devm_kcalloc(pmu->dev, pd->num_clks,
841 sizeof(*pd->clks), GFP_KERNEL);
842 if (!pd->clks)
843 return -ENOMEM;
844 } else {
845 dev_dbg(pmu->dev, "%pOFn: doesn't have clocks: %d\n",
846 node, pd->num_clks);
847 pd->num_clks = 0;
848 }
849
850 for (i = 0; i < pd->num_clks; i++) {
851 pd->clks[i].clk = of_clk_get(node, i);
852 if (IS_ERR(pd->clks[i].clk)) {
853 error = PTR_ERR(pd->clks[i].clk);
854 dev_err(pmu->dev,
855 "%pOFn: failed to get clk at index %d: %d\n",
856 node, i, error);
857 goto err_put_clocks;
858 }
859 }
860
861 error = clk_bulk_prepare(pd->num_clks, pd->clks);
862 if (error)
863 goto err_put_clocks;
864
865 pd->num_qos = of_count_phandle_with_args(node, "pm_qos",
866 NULL);
867
868 if (pd->num_qos > 0) {
869 pd->qos_regmap = devm_kcalloc(pmu->dev, pd->num_qos,
870 sizeof(*pd->qos_regmap),
871 GFP_KERNEL);
872 if (!pd->qos_regmap) {
873 error = -ENOMEM;
874 goto err_unprepare_clocks;
875 }
876
877 for (j = 0; j < MAX_QOS_REGS_NUM; j++) {
878 pd->qos_save_regs[j] = devm_kcalloc(pmu->dev,
879 pd->num_qos,
880 sizeof(u32),
881 GFP_KERNEL);
882 if (!pd->qos_save_regs[j]) {
883 error = -ENOMEM;
884 goto err_unprepare_clocks;
885 }
886 }
887
888 for (j = 0; j < pd->num_qos; j++) {
889 qos_node = of_parse_phandle(node, "pm_qos", j);
890 if (!qos_node) {
891 error = -ENODEV;
892 goto err_unprepare_clocks;
893 }
894 pd->qos_regmap[j] = syscon_node_to_regmap(qos_node);
895 of_node_put(qos_node);
896 if (IS_ERR(pd->qos_regmap[j])) {
897 error = -ENODEV;
898 goto err_unprepare_clocks;
899 }
900 }
901 }
902
903 if (pd->info->name)
904 pd->genpd.name = pd->info->name;
905 else
906 pd->genpd.name = kbasename(node->full_name);
907
908 /*
909 * power domain's needing a regulator should default to off, since
910 * the regulator state is unknown at probe time. Also the regulator
911 * state cannot be checked, since that usually requires IP needing
912 * (a different) power domain.
913 */
914 if (pd->info->need_regulator)
915 rockchip_pd_power(pd, false);
916
917 pd->genpd.power_off = rockchip_pd_power_off;
918 pd->genpd.power_on = rockchip_pd_power_on;
919 pd->genpd.attach_dev = rockchip_pd_attach_dev;
920 pd->genpd.detach_dev = rockchip_pd_detach_dev;
921 pd->genpd.flags = GENPD_FLAG_PM_CLK | GENPD_FLAG_NO_STAY_ON;
922 if (pd_info->active_wakeup)
923 pd->genpd.flags |= GENPD_FLAG_ACTIVE_WAKEUP;
924 pm_genpd_init(&pd->genpd, NULL,
925 !rockchip_pmu_domain_is_on(pd) ||
926 (pd->info->mem_status_mask && !rockchip_pmu_domain_is_mem_on(pd)));
927
928 pmu->genpd_data.domains[id] = &pd->genpd;
929 return 0;
930
931 err_unprepare_clocks:
932 clk_bulk_unprepare(pd->num_clks, pd->clks);
933 err_put_clocks:
934 clk_bulk_put(pd->num_clks, pd->clks);
935 return error;
936 }
937
rockchip_pm_remove_one_domain(struct rockchip_pm_domain * pd)938 static void rockchip_pm_remove_one_domain(struct rockchip_pm_domain *pd)
939 {
940 int ret;
941
942 /*
943 * We're in the error cleanup already, so we only complain,
944 * but won't emit another error on top of the original one.
945 */
946 ret = pm_genpd_remove(&pd->genpd);
947 if (ret < 0)
948 dev_err(pd->pmu->dev, "failed to remove domain '%s' : %d - state may be inconsistent\n",
949 pd->genpd.name, ret);
950
951 clk_bulk_unprepare(pd->num_clks, pd->clks);
952 clk_bulk_put(pd->num_clks, pd->clks);
953
954 /* protect the zeroing of pm->num_clks */
955 mutex_lock(&pd->pmu->mutex);
956 pd->num_clks = 0;
957 mutex_unlock(&pd->pmu->mutex);
958
959 /* devm will free our memory */
960 }
961
rockchip_pm_domain_cleanup(struct rockchip_pmu * pmu)962 static void rockchip_pm_domain_cleanup(struct rockchip_pmu *pmu)
963 {
964 struct generic_pm_domain *genpd;
965 struct rockchip_pm_domain *pd;
966 int i;
967
968 for (i = 0; i < pmu->genpd_data.num_domains; i++) {
969 genpd = pmu->genpd_data.domains[i];
970 if (genpd) {
971 pd = to_rockchip_pd(genpd);
972 rockchip_pm_remove_one_domain(pd);
973 }
974 }
975
976 /* devm will free our memory */
977 }
978
rockchip_configure_pd_cnt(struct rockchip_pmu * pmu,u32 domain_reg_offset,unsigned int count)979 static void rockchip_configure_pd_cnt(struct rockchip_pmu *pmu,
980 u32 domain_reg_offset,
981 unsigned int count)
982 {
983 /* First configure domain power down transition count ... */
984 regmap_write(pmu->regmap, domain_reg_offset, count);
985 /* ... and then power up count. */
986 regmap_write(pmu->regmap, domain_reg_offset + 4, count);
987 }
988
rockchip_pm_add_subdomain(struct rockchip_pmu * pmu,struct device_node * parent)989 static int rockchip_pm_add_subdomain(struct rockchip_pmu *pmu,
990 struct device_node *parent)
991 {
992 struct generic_pm_domain *child_domain, *parent_domain;
993 int error;
994
995 for_each_child_of_node_scoped(parent, np) {
996 u32 idx;
997
998 error = of_property_read_u32(parent, "reg", &idx);
999 if (error) {
1000 dev_err(pmu->dev,
1001 "%pOFn: failed to retrieve domain id (reg): %d\n",
1002 parent, error);
1003 return error;
1004 }
1005 parent_domain = pmu->genpd_data.domains[idx];
1006
1007 error = rockchip_pm_add_one_domain(pmu, np);
1008 if (error) {
1009 dev_err(pmu->dev, "failed to handle node %pOFn: %d\n",
1010 np, error);
1011 return error;
1012 }
1013
1014 error = of_property_read_u32(np, "reg", &idx);
1015 if (error) {
1016 dev_err(pmu->dev,
1017 "%pOFn: failed to retrieve domain id (reg): %d\n",
1018 np, error);
1019 return error;
1020 }
1021 child_domain = pmu->genpd_data.domains[idx];
1022
1023 error = pm_genpd_add_subdomain(parent_domain, child_domain);
1024 if (error) {
1025 dev_err(pmu->dev, "%s failed to add subdomain %s: %d\n",
1026 parent_domain->name, child_domain->name, error);
1027 return error;
1028 } else {
1029 dev_dbg(pmu->dev, "%s add subdomain: %s\n",
1030 parent_domain->name, child_domain->name);
1031 }
1032
1033 error = rockchip_pm_add_subdomain(pmu, np);
1034 if (error)
1035 return error;
1036 }
1037
1038 return 0;
1039 }
1040
rockchip_pm_domain_probe(struct platform_device * pdev)1041 static int rockchip_pm_domain_probe(struct platform_device *pdev)
1042 {
1043 struct device *dev = &pdev->dev;
1044 struct device_node *np = dev->of_node;
1045 struct device *parent;
1046 struct rockchip_pmu *pmu;
1047 const struct rockchip_pmu_info *pmu_info;
1048 int error;
1049
1050 if (!np) {
1051 dev_err(dev, "device tree node not found\n");
1052 return -ENODEV;
1053 }
1054
1055 pmu_info = device_get_match_data(dev);
1056
1057 pmu = devm_kzalloc(dev,
1058 struct_size(pmu, domains, pmu_info->num_domains),
1059 GFP_KERNEL);
1060 if (!pmu)
1061 return -ENOMEM;
1062
1063 pmu->dev = &pdev->dev;
1064 mutex_init(&pmu->mutex);
1065
1066 pmu->info = pmu_info;
1067
1068 pmu->genpd_data.domains = pmu->domains;
1069 pmu->genpd_data.num_domains = pmu_info->num_domains;
1070
1071 parent = dev->parent;
1072 if (!parent) {
1073 dev_err(dev, "no parent for syscon devices\n");
1074 return -ENODEV;
1075 }
1076
1077 pmu->regmap = syscon_node_to_regmap(parent->of_node);
1078 if (IS_ERR(pmu->regmap)) {
1079 dev_err(dev, "no regmap available\n");
1080 return PTR_ERR(pmu->regmap);
1081 }
1082
1083 /*
1084 * Configure power up and down transition delays for CORE
1085 * and GPU domains.
1086 */
1087 if (pmu_info->core_power_transition_time)
1088 rockchip_configure_pd_cnt(pmu, pmu_info->core_pwrcnt_offset,
1089 pmu_info->core_power_transition_time);
1090 if (pmu_info->gpu_pwrcnt_offset)
1091 rockchip_configure_pd_cnt(pmu, pmu_info->gpu_pwrcnt_offset,
1092 pmu_info->gpu_power_transition_time);
1093
1094 error = -ENODEV;
1095
1096 /*
1097 * Prevent any rockchip_pmu_block() from racing with the remainder of
1098 * setup (clocks, register initialization).
1099 */
1100 guard(mutex)(&dmc_pmu_mutex);
1101
1102 for_each_available_child_of_node_scoped(np, node) {
1103 error = rockchip_pm_add_one_domain(pmu, node);
1104 if (error) {
1105 dev_err(dev, "failed to handle node %pOFn: %d\n",
1106 node, error);
1107 goto err_out;
1108 }
1109
1110 error = rockchip_pm_add_subdomain(pmu, node);
1111 if (error < 0) {
1112 dev_err(dev, "failed to handle subdomain node %pOFn: %d\n",
1113 node, error);
1114 goto err_out;
1115 }
1116 }
1117
1118 if (error) {
1119 dev_dbg(dev, "no power domains defined\n");
1120 goto err_out;
1121 }
1122
1123 error = of_genpd_add_provider_onecell(np, &pmu->genpd_data);
1124 if (error) {
1125 dev_err(dev, "failed to add provider: %d\n", error);
1126 goto err_out;
1127 }
1128
1129 /* We only expect one PMU. */
1130 if (!WARN_ON_ONCE(dmc_pmu))
1131 dmc_pmu = pmu;
1132
1133 return 0;
1134
1135 err_out:
1136 rockchip_pm_domain_cleanup(pmu);
1137 return error;
1138 }
1139
1140 static const struct rockchip_domain_info px30_pm_domains[] = {
1141 [PX30_PD_USB] = DOMAIN_PX30("usb", BIT(5), BIT(5), BIT(10), false),
1142 [PX30_PD_SDCARD] = DOMAIN_PX30("sdcard", BIT(8), BIT(8), BIT(9), false),
1143 [PX30_PD_GMAC] = DOMAIN_PX30("gmac", BIT(10), BIT(10), BIT(6), false),
1144 [PX30_PD_MMC_NAND] = DOMAIN_PX30("mmc_nand", BIT(11), BIT(11), BIT(5), false),
1145 [PX30_PD_VPU] = DOMAIN_PX30("vpu", BIT(12), BIT(12), BIT(14), false),
1146 [PX30_PD_VO] = DOMAIN_PX30("vo", BIT(13), BIT(13), BIT(7), false),
1147 [PX30_PD_VI] = DOMAIN_PX30("vi", BIT(14), BIT(14), BIT(8), false),
1148 [PX30_PD_GPU] = DOMAIN_PX30("gpu", BIT(15), BIT(15), BIT(2), false),
1149 };
1150
1151 static const struct rockchip_domain_info rv1126_pm_domains[] = {
1152 [RV1126_PD_VEPU] = DOMAIN_RV1126("vepu", BIT(2), BIT(9), BIT(9), false),
1153 [RV1126_PD_VI] = DOMAIN_RV1126("vi", BIT(4), BIT(6), BIT(6), false),
1154 [RV1126_PD_VO] = DOMAIN_RV1126("vo", BIT(5), BIT(7), BIT(7), false),
1155 [RV1126_PD_ISPP] = DOMAIN_RV1126("ispp", BIT(1), BIT(8), BIT(8), false),
1156 [RV1126_PD_VDPU] = DOMAIN_RV1126("vdpu", BIT(3), BIT(10), BIT(10), false),
1157 [RV1126_PD_NVM] = DOMAIN_RV1126("nvm", BIT(7), BIT(11), BIT(11), false),
1158 [RV1126_PD_SDIO] = DOMAIN_RV1126("sdio", BIT(8), BIT(13), BIT(13), false),
1159 [RV1126_PD_USB] = DOMAIN_RV1126("usb", BIT(9), BIT(15), BIT(15), false),
1160 };
1161
1162 static const struct rockchip_domain_info rv1126b_pm_domains[] = {
1163 /* name pwr req wakeup */
1164 [RV1126B_PD_NPU] = DOMAIN_RV1126B("npu", BIT(0), BIT(8), false),
1165 [RV1126B_PD_VDO] = DOMAIN_RV1126B("vdo", BIT(1), BIT(9), false),
1166 [RV1126B_PD_AIISP] = DOMAIN_RV1126B("aiisp", BIT(2), BIT(10), false),
1167 };
1168
1169 static const struct rockchip_domain_info rk3036_pm_domains[] = {
1170 [RK3036_PD_MSCH] = DOMAIN_RK3036("msch", BIT(14), BIT(23), BIT(30), true),
1171 [RK3036_PD_CORE] = DOMAIN_RK3036("core", BIT(13), BIT(17), BIT(24), false),
1172 [RK3036_PD_PERI] = DOMAIN_RK3036("peri", BIT(12), BIT(18), BIT(25), false),
1173 [RK3036_PD_VIO] = DOMAIN_RK3036("vio", BIT(11), BIT(19), BIT(26), false),
1174 [RK3036_PD_VPU] = DOMAIN_RK3036("vpu", BIT(10), BIT(20), BIT(27), false),
1175 [RK3036_PD_GPU] = DOMAIN_RK3036("gpu", BIT(9), BIT(21), BIT(28), false),
1176 [RK3036_PD_SYS] = DOMAIN_RK3036("sys", BIT(8), BIT(22), BIT(29), false),
1177 };
1178
1179 static const struct rockchip_domain_info rk3066_pm_domains[] = {
1180 [RK3066_PD_GPU] = DOMAIN("gpu", BIT(9), BIT(9), BIT(3), BIT(24), BIT(29), false),
1181 [RK3066_PD_VIDEO] = DOMAIN("video", BIT(8), BIT(8), BIT(4), BIT(23), BIT(28), false),
1182 [RK3066_PD_VIO] = DOMAIN("vio", BIT(7), BIT(7), BIT(5), BIT(22), BIT(27), false),
1183 [RK3066_PD_PERI] = DOMAIN("peri", BIT(6), BIT(6), BIT(2), BIT(25), BIT(30), false),
1184 [RK3066_PD_CPU] = DOMAIN("cpu", 0, BIT(5), BIT(1), BIT(26), BIT(31), false),
1185 };
1186
1187 static const struct rockchip_domain_info rk3128_pm_domains[] = {
1188 [RK3128_PD_CORE] = DOMAIN_RK3288("core", BIT(0), BIT(0), BIT(4), false),
1189 [RK3128_PD_MSCH] = DOMAIN_RK3288("msch", 0, 0, BIT(6), true),
1190 [RK3128_PD_VIO] = DOMAIN_RK3288("vio", BIT(3), BIT(3), BIT(2), false),
1191 [RK3128_PD_VIDEO] = DOMAIN_RK3288("video", BIT(2), BIT(2), BIT(1), false),
1192 [RK3128_PD_GPU] = DOMAIN_RK3288("gpu", BIT(1), BIT(1), BIT(3), false),
1193 };
1194
1195 static const struct rockchip_domain_info rk3188_pm_domains[] = {
1196 [RK3188_PD_GPU] = DOMAIN("gpu", BIT(9), BIT(9), BIT(3), BIT(24), BIT(29), false),
1197 [RK3188_PD_VIDEO] = DOMAIN("video", BIT(8), BIT(8), BIT(4), BIT(23), BIT(28), false),
1198 [RK3188_PD_VIO] = DOMAIN("vio", BIT(7), BIT(7), BIT(5), BIT(22), BIT(27), false),
1199 [RK3188_PD_PERI] = DOMAIN("peri", BIT(6), BIT(6), BIT(2), BIT(25), BIT(30), false),
1200 [RK3188_PD_CPU] = DOMAIN("cpu", BIT(5), BIT(5), BIT(1), BIT(26), BIT(31), false),
1201 };
1202
1203 static const struct rockchip_domain_info rk3228_pm_domains[] = {
1204 [RK3228_PD_CORE] = DOMAIN_RK3036("core", BIT(0), BIT(0), BIT(16), true),
1205 [RK3228_PD_MSCH] = DOMAIN_RK3036("msch", BIT(1), BIT(1), BIT(17), true),
1206 [RK3228_PD_BUS] = DOMAIN_RK3036("bus", BIT(2), BIT(2), BIT(18), true),
1207 [RK3228_PD_SYS] = DOMAIN_RK3036("sys", BIT(3), BIT(3), BIT(19), true),
1208 [RK3228_PD_VIO] = DOMAIN_RK3036("vio", BIT(4), BIT(4), BIT(20), false),
1209 [RK3228_PD_VOP] = DOMAIN_RK3036("vop", BIT(5), BIT(5), BIT(21), false),
1210 [RK3228_PD_VPU] = DOMAIN_RK3036("vpu", BIT(6), BIT(6), BIT(22), false),
1211 [RK3228_PD_RKVDEC] = DOMAIN_RK3036("vdec", BIT(7), BIT(7), BIT(23), false),
1212 [RK3228_PD_GPU] = DOMAIN_RK3036("gpu", BIT(8), BIT(8), BIT(24), false),
1213 [RK3228_PD_PERI] = DOMAIN_RK3036("peri", BIT(9), BIT(9), BIT(25), true),
1214 [RK3228_PD_GMAC] = DOMAIN_RK3036("gmac", BIT(10), BIT(10), BIT(26), false),
1215 };
1216
1217 static const struct rockchip_domain_info rk3288_pm_domains[] = {
1218 [RK3288_PD_VIO] = DOMAIN_RK3288("vio", BIT(7), BIT(7), BIT(4), false),
1219 [RK3288_PD_HEVC] = DOMAIN_RK3288("hevc", BIT(14), BIT(10), BIT(9), false),
1220 [RK3288_PD_VIDEO] = DOMAIN_RK3288("video", BIT(8), BIT(8), BIT(3), false),
1221 [RK3288_PD_GPU] = DOMAIN_RK3288("gpu", BIT(9), BIT(9), BIT(2), false),
1222 };
1223
1224 static const struct rockchip_domain_info rk3328_pm_domains[] = {
1225 [RK3328_PD_CORE] = DOMAIN_RK3328("core", 0, BIT(0), BIT(0), false),
1226 [RK3328_PD_GPU] = DOMAIN_RK3328("gpu", 0, BIT(1), BIT(1), false),
1227 [RK3328_PD_BUS] = DOMAIN_RK3328("bus", 0, BIT(2), BIT(2), true),
1228 [RK3328_PD_MSCH] = DOMAIN_RK3328("msch", 0, BIT(3), BIT(3), true),
1229 [RK3328_PD_PERI] = DOMAIN_RK3328("peri", 0, BIT(4), BIT(4), true),
1230 [RK3328_PD_VIDEO] = DOMAIN_RK3328("video", 0, BIT(5), BIT(5), false),
1231 [RK3328_PD_HEVC] = DOMAIN_RK3328("hevc", 0, BIT(6), BIT(6), false),
1232 [RK3328_PD_VIO] = DOMAIN_RK3328("vio", 0, BIT(8), BIT(8), false),
1233 [RK3328_PD_VPU] = DOMAIN_RK3328("vpu", 0, BIT(9), BIT(9), false),
1234 };
1235
1236 static const struct rockchip_domain_info rk3366_pm_domains[] = {
1237 [RK3366_PD_PERI] = DOMAIN_RK3368("peri", BIT(10), BIT(10), BIT(6), true),
1238 [RK3366_PD_VIO] = DOMAIN_RK3368("vio", BIT(14), BIT(14), BIT(8), false),
1239 [RK3366_PD_VIDEO] = DOMAIN_RK3368("video", BIT(13), BIT(13), BIT(7), false),
1240 [RK3366_PD_RKVDEC] = DOMAIN_RK3368("vdec", BIT(11), BIT(11), BIT(7), false),
1241 [RK3366_PD_WIFIBT] = DOMAIN_RK3368("wifibt", BIT(8), BIT(8), BIT(9), false),
1242 [RK3366_PD_VPU] = DOMAIN_RK3368("vpu", BIT(12), BIT(12), BIT(7), false),
1243 [RK3366_PD_GPU] = DOMAIN_RK3368("gpu", BIT(15), BIT(15), BIT(2), false),
1244 };
1245
1246 static const struct rockchip_domain_info rk3368_pm_domains[] = {
1247 [RK3368_PD_PERI] = DOMAIN_RK3368("peri", BIT(13), BIT(12), BIT(6), true),
1248 [RK3368_PD_VIO] = DOMAIN_RK3368("vio", BIT(15), BIT(14), BIT(8), false),
1249 [RK3368_PD_VIDEO] = DOMAIN_RK3368("video", BIT(14), BIT(13), BIT(7), false),
1250 [RK3368_PD_GPU_0] = DOMAIN_RK3368("gpu_0", BIT(16), BIT(15), BIT(2), false),
1251 [RK3368_PD_GPU_1] = DOMAIN_RK3368("gpu_1", BIT(17), BIT(16), BIT(2), false),
1252 };
1253
1254 static const struct rockchip_domain_info rk3399_pm_domains[] = {
1255 [RK3399_PD_TCPD0] = DOMAIN_RK3399("tcpd0", BIT(8), BIT(8), 0, false),
1256 [RK3399_PD_TCPD1] = DOMAIN_RK3399("tcpd1", BIT(9), BIT(9), 0, false),
1257 [RK3399_PD_CCI] = DOMAIN_RK3399("cci", BIT(10), BIT(10), 0, true),
1258 [RK3399_PD_CCI0] = DOMAIN_RK3399("cci0", 0, 0, BIT(15), true),
1259 [RK3399_PD_CCI1] = DOMAIN_RK3399("cci1", 0, 0, BIT(16), true),
1260 [RK3399_PD_PERILP] = DOMAIN_RK3399("perilp", BIT(11), BIT(11), BIT(1), true),
1261 [RK3399_PD_PERIHP] = DOMAIN_RK3399("perihp", BIT(12), BIT(12), BIT(2), true),
1262 [RK3399_PD_CENTER] = DOMAIN_RK3399("center", BIT(13), BIT(13), BIT(14), true),
1263 [RK3399_PD_VIO] = DOMAIN_RK3399("vio", BIT(14), BIT(14), BIT(17), false),
1264 [RK3399_PD_GPU] = DOMAIN_RK3399("gpu", BIT(15), BIT(15), BIT(0), false),
1265 [RK3399_PD_VCODEC] = DOMAIN_RK3399("vcodec", BIT(16), BIT(16), BIT(3), false),
1266 [RK3399_PD_VDU] = DOMAIN_RK3399("vdu", BIT(17), BIT(17), BIT(4), false),
1267 [RK3399_PD_RGA] = DOMAIN_RK3399("rga", BIT(18), BIT(18), BIT(5), false),
1268 [RK3399_PD_IEP] = DOMAIN_RK3399("iep", BIT(19), BIT(19), BIT(6), false),
1269 [RK3399_PD_VO] = DOMAIN_RK3399("vo", BIT(20), BIT(20), 0, false),
1270 [RK3399_PD_VOPB] = DOMAIN_RK3399("vopb", 0, 0, BIT(7), false),
1271 [RK3399_PD_VOPL] = DOMAIN_RK3399("vopl", 0, 0, BIT(8), false),
1272 [RK3399_PD_ISP0] = DOMAIN_RK3399("isp0", BIT(22), BIT(22), BIT(9), false),
1273 [RK3399_PD_ISP1] = DOMAIN_RK3399("isp1", BIT(23), BIT(23), BIT(10), false),
1274 [RK3399_PD_HDCP] = DOMAIN_RK3399("hdcp", BIT(24), BIT(24), BIT(11), false),
1275 [RK3399_PD_GMAC] = DOMAIN_RK3399("gmac", BIT(25), BIT(25), BIT(23), true),
1276 [RK3399_PD_EMMC] = DOMAIN_RK3399("emmc", BIT(26), BIT(26), BIT(24), true),
1277 [RK3399_PD_USB3] = DOMAIN_RK3399("usb3", BIT(27), BIT(27), BIT(12), true),
1278 [RK3399_PD_EDP] = DOMAIN_RK3399("edp", BIT(28), BIT(28), BIT(22), false),
1279 [RK3399_PD_GIC] = DOMAIN_RK3399("gic", BIT(29), BIT(29), BIT(27), true),
1280 [RK3399_PD_SD] = DOMAIN_RK3399("sd", BIT(30), BIT(30), BIT(28), true),
1281 [RK3399_PD_SDIOAUDIO] = DOMAIN_RK3399("sdioaudio", BIT(31), BIT(31), BIT(29), true),
1282 };
1283
1284 static const struct rockchip_domain_info rk3528_pm_domains[] = {
1285 [RK3528_PD_GPU] = DOMAIN_RK3528("gpu", BIT(0), BIT(4)),
1286 [RK3528_PD_RKVDEC] = DOMAIN_RK3528("vdec", 0, BIT(5)),
1287 [RK3528_PD_RKVENC] = DOMAIN_RK3528("venc", 0, BIT(6)),
1288 [RK3528_PD_VO] = DOMAIN_RK3528("vo", 0, BIT(7)),
1289 [RK3528_PD_VPU] = DOMAIN_RK3528("vpu", 0, BIT(8)),
1290 };
1291
1292 static const struct rockchip_domain_info rk3562_pm_domains[] = {
1293 /* name pwr req g_mask mem wakeup */
1294 [RK3562_PD_GPU] = DOMAIN_RK3562("gpu", BIT(0), BIT(1), BIT(1), 0, false),
1295 [RK3562_PD_NPU] = DOMAIN_RK3562("npu", BIT(1), BIT(2), BIT(2), 0, false),
1296 [RK3562_PD_VDPU] = DOMAIN_RK3562("vdpu", BIT(2), BIT(6), BIT(6), 0, false),
1297 [RK3562_PD_VEPU] = DOMAIN_RK3562("vepu", BIT(3), BIT(7), BIT(7) | BIT(3), 0, false),
1298 [RK3562_PD_RGA] = DOMAIN_RK3562("rga", BIT(4), BIT(5), BIT(5) | BIT(4), 0, false),
1299 [RK3562_PD_VI] = DOMAIN_RK3562("vi", BIT(5), BIT(3), BIT(3), 0, false),
1300 [RK3562_PD_VO] = DOMAIN_RK3562("vo", BIT(6), BIT(4), BIT(4), 16, false),
1301 [RK3562_PD_PHP] = DOMAIN_RK3562("php", BIT(7), BIT(8), BIT(8), 0, false),
1302 };
1303
1304 static const struct rockchip_domain_info rk3568_pm_domains[] = {
1305 [RK3568_PD_NPU] = DOMAIN_RK3568("npu", BIT(1), BIT(2), false, true),
1306 [RK3568_PD_GPU] = DOMAIN_RK3568("gpu", BIT(0), BIT(1), false, false),
1307 [RK3568_PD_VI] = DOMAIN_RK3568("vi", BIT(6), BIT(3), false, false),
1308 [RK3568_PD_VO] = DOMAIN_RK3568("vo", BIT(7), BIT(4), false, false),
1309 [RK3568_PD_RGA] = DOMAIN_RK3568("rga", BIT(5), BIT(5), false, false),
1310 [RK3568_PD_VPU] = DOMAIN_RK3568("vpu", BIT(2), BIT(6), false, false),
1311 [RK3568_PD_RKVDEC] = DOMAIN_RK3568("vdec", BIT(4), BIT(8), false, false),
1312 [RK3568_PD_RKVENC] = DOMAIN_RK3568("venc", BIT(3), BIT(7), false, false),
1313 [RK3568_PD_PIPE] = DOMAIN_RK3568("pipe", BIT(8), BIT(11), false, false),
1314 };
1315
1316 static const struct rockchip_domain_info rk3576_pm_domains[] = {
1317 [RK3576_PD_NPU] = DOMAIN_RK3576("npu", 0x0, BIT(0), BIT(0), 0, 0x0, 0, 0, 0, false),
1318 [RK3576_PD_NVM] = DOMAIN_RK3576("nvm", 0x0, BIT(6), 0, BIT(6), 0x4, BIT(2), BIT(18), BIT(2), false),
1319 [RK3576_PD_SDGMAC] = DOMAIN_RK3576("sdgmac", 0x0, BIT(7), 0, BIT(7), 0x4, BIT(1), BIT(17), 0x6, false),
1320 [RK3576_PD_AUDIO] = DOMAIN_RK3576("audio", 0x0, BIT(8), 0, BIT(8), 0x4, BIT(0), BIT(16), BIT(0), false),
1321 [RK3576_PD_PHP] = DOMAIN_RK3576("php", 0x0, BIT(9), 0, BIT(9), 0x0, BIT(15), BIT(15), BIT(15), false),
1322 [RK3576_PD_SUBPHP] = DOMAIN_RK3576("subphp", 0x0, BIT(10), 0, BIT(10), 0x0, 0, 0, 0, false),
1323 [RK3576_PD_VOP] = DOMAIN_RK3576("vop", 0x0, BIT(11), 0, BIT(11), 0x0, 0x6000, 0x6000, 0x6000, false),
1324 [RK3576_PD_VO1] = DOMAIN_RK3576("vo1", 0x0, BIT(14), 0, BIT(14), 0x0, BIT(12), BIT(12), 0x7000, false),
1325 [RK3576_PD_VO0] = DOMAIN_RK3576("vo0", 0x0, BIT(15), 0, BIT(15), 0x0, BIT(11), BIT(11), 0x6800, false),
1326 [RK3576_PD_USB] = DOMAIN_RK3576("usb", 0x4, BIT(0), 0, BIT(16), 0x0, BIT(10), BIT(10), 0x6400, true),
1327 [RK3576_PD_VI] = DOMAIN_RK3576("vi", 0x4, BIT(1), 0, BIT(17), 0x0, BIT(9), BIT(9), BIT(9), false),
1328 [RK3576_PD_VEPU0] = DOMAIN_RK3576("vepu0", 0x4, BIT(2), 0, BIT(18), 0x0, BIT(7), BIT(7), 0x280, false),
1329 [RK3576_PD_VEPU1] = DOMAIN_RK3576("vepu1", 0x4, BIT(3), 0, BIT(19), 0x0, BIT(8), BIT(8), BIT(8), false),
1330 [RK3576_PD_VDEC] = DOMAIN_RK3576("vdec", 0x4, BIT(4), 0, BIT(20), 0x0, BIT(6), BIT(6), BIT(6), false),
1331 [RK3576_PD_VPU] = DOMAIN_RK3576("vpu", 0x4, BIT(5), 0, BIT(21), 0x0, BIT(5), BIT(5), BIT(5), false),
1332 [RK3576_PD_NPUTOP] = DOMAIN_RK3576("nputop", 0x4, BIT(6), 0, BIT(22), 0x0, 0x18, 0x18, 0x18, false),
1333 [RK3576_PD_NPU0] = DOMAIN_RK3576("npu0", 0x4, BIT(7), 0, BIT(23), 0x0, BIT(1), BIT(1), 0x1a, false),
1334 [RK3576_PD_NPU1] = DOMAIN_RK3576("npu1", 0x4, BIT(8), 0, BIT(24), 0x0, BIT(2), BIT(2), 0x1c, false),
1335 [RK3576_PD_GPU] = DOMAIN_RK3576("gpu", 0x4, BIT(9), 0, BIT(25), 0x0, BIT(0), BIT(0), BIT(0), false),
1336 };
1337
1338 static const struct rockchip_domain_info rk3588_pm_domains[] = {
1339 [RK3588_PD_GPU] = DOMAIN_RK3588("gpu", 0x0, BIT(0), 0, 0x0, 0, BIT(1), 0x0, BIT(0), BIT(0), false, true),
1340 [RK3588_PD_NPU] = DOMAIN_RK3588("npu", 0x0, BIT(1), BIT(1), 0x0, 0, 0, 0x0, 0, 0, false, true),
1341 [RK3588_PD_VCODEC] = DOMAIN_RK3588("vcodec", 0x0, BIT(2), BIT(2), 0x0, 0, 0, 0x0, 0, 0, false, true),
1342 [RK3588_PD_NPUTOP] = DOMAIN_RK3588("nputop", 0x0, BIT(3), 0, 0x0, BIT(11), BIT(2), 0x0, BIT(1), BIT(1), false, false),
1343 [RK3588_PD_NPU1] = DOMAIN_RK3588("npu1", 0x0, BIT(4), 0, 0x0, BIT(12), BIT(3), 0x0, BIT(2), BIT(2), false, false),
1344 [RK3588_PD_NPU2] = DOMAIN_RK3588("npu2", 0x0, BIT(5), 0, 0x0, BIT(13), BIT(4), 0x0, BIT(3), BIT(3), false, false),
1345 [RK3588_PD_VENC0] = DOMAIN_RK3588("venc0", 0x0, BIT(6), 0, 0x0, BIT(14), BIT(5), 0x0, BIT(4), BIT(4), false, false),
1346 [RK3588_PD_VENC1] = DOMAIN_RK3588("venc1", 0x0, BIT(7), 0, 0x0, BIT(15), BIT(6), 0x0, BIT(5), BIT(5), false, false),
1347 [RK3588_PD_RKVDEC0] = DOMAIN_RK3588("rkvdec0", 0x0, BIT(8), 0, 0x0, BIT(16), BIT(7), 0x0, BIT(6), BIT(6), false, false),
1348 [RK3588_PD_RKVDEC1] = DOMAIN_RK3588("rkvdec1", 0x0, BIT(9), 0, 0x0, BIT(17), BIT(8), 0x0, BIT(7), BIT(7), false, false),
1349 [RK3588_PD_VDPU] = DOMAIN_RK3588("vdpu", 0x0, BIT(10), 0, 0x0, BIT(18), BIT(9), 0x0, BIT(8), BIT(8), false, false),
1350 [RK3588_PD_RGA30] = DOMAIN_RK3588("rga30", 0x0, BIT(11), 0, 0x0, BIT(19), BIT(10), 0x0, 0, 0, false, false),
1351 [RK3588_PD_AV1] = DOMAIN_RK3588("av1", 0x0, BIT(12), 0, 0x0, BIT(20), BIT(11), 0x0, BIT(9), BIT(9), false, false),
1352 [RK3588_PD_VI] = DOMAIN_RK3588("vi", 0x0, BIT(13), 0, 0x0, BIT(21), BIT(12), 0x0, BIT(10), BIT(10), false, false),
1353 [RK3588_PD_FEC] = DOMAIN_RK3588("fec", 0x0, BIT(14), 0, 0x0, BIT(22), BIT(13), 0x0, 0, 0, false, false),
1354 [RK3588_PD_ISP1] = DOMAIN_RK3588("isp1", 0x0, BIT(15), 0, 0x0, BIT(23), BIT(14), 0x0, BIT(11), BIT(11), false, false),
1355 [RK3588_PD_RGA31] = DOMAIN_RK3588("rga31", 0x4, BIT(0), 0, 0x0, BIT(24), BIT(15), 0x0, BIT(12), BIT(12), false, false),
1356 [RK3588_PD_VOP] = DOMAIN_RK3588("vop", 0x4, BIT(1), 0, 0x0, BIT(25), BIT(16), 0x0, BIT(13) | BIT(14), BIT(13) | BIT(14), false, false),
1357 [RK3588_PD_VO0] = DOMAIN_RK3588("vo0", 0x4, BIT(2), 0, 0x0, BIT(26), BIT(17), 0x0, BIT(15), BIT(15), false, false),
1358 [RK3588_PD_VO1] = DOMAIN_RK3588("vo1", 0x4, BIT(3), 0, 0x0, BIT(27), BIT(18), 0x4, BIT(0), BIT(16), false, false),
1359 [RK3588_PD_AUDIO] = DOMAIN_RK3588("audio", 0x4, BIT(4), 0, 0x0, BIT(28), BIT(19), 0x4, BIT(1), BIT(17), false, false),
1360 [RK3588_PD_PHP] = DOMAIN_RK3588("php", 0x4, BIT(5), 0, 0x0, BIT(29), BIT(20), 0x4, BIT(5), BIT(21), false, false),
1361 [RK3588_PD_GMAC] = DOMAIN_RK3588("gmac", 0x4, BIT(6), 0, 0x0, BIT(30), BIT(21), 0x0, 0, 0, false, false),
1362 [RK3588_PD_PCIE] = DOMAIN_RK3588("pcie", 0x4, BIT(7), 0, 0x0, BIT(31), BIT(22), 0x0, 0, 0, true, false),
1363 [RK3588_PD_NVM] = DOMAIN_RK3588("nvm", 0x4, BIT(8), BIT(24), 0x4, 0, 0, 0x4, BIT(2), BIT(18), false, false),
1364 [RK3588_PD_NVM0] = DOMAIN_RK3588("nvm0", 0x4, BIT(9), 0, 0x4, BIT(1), BIT(23), 0x0, 0, 0, false, false),
1365 [RK3588_PD_SDIO] = DOMAIN_RK3588("sdio", 0x4, BIT(10), 0, 0x4, BIT(2), BIT(24), 0x4, BIT(3), BIT(19), false, false),
1366 [RK3588_PD_USB] = DOMAIN_RK3588("usb", 0x4, BIT(11), 0, 0x4, BIT(3), BIT(25), 0x4, BIT(4), BIT(20), true, false),
1367 [RK3588_PD_SDMMC] = DOMAIN_RK3588("sdmmc", 0x4, BIT(13), 0, 0x4, BIT(5), BIT(26), 0x0, 0, 0, false, false),
1368 };
1369
1370 static const struct rockchip_pmu_info px30_pmu = {
1371 .pwr_offset = 0x18,
1372 .status_offset = 0x20,
1373 .req_offset = 0x64,
1374 .idle_offset = 0x6c,
1375 .ack_offset = 0x6c,
1376
1377 .num_domains = ARRAY_SIZE(px30_pm_domains),
1378 .domain_info = px30_pm_domains,
1379 };
1380
1381 static const struct rockchip_pmu_info rk3036_pmu = {
1382 .req_offset = 0x148,
1383 .idle_offset = 0x14c,
1384 .ack_offset = 0x14c,
1385
1386 .num_domains = ARRAY_SIZE(rk3036_pm_domains),
1387 .domain_info = rk3036_pm_domains,
1388 };
1389
1390 static const struct rockchip_pmu_info rk3066_pmu = {
1391 .pwr_offset = 0x08,
1392 .status_offset = 0x0c,
1393 .req_offset = 0x38, /* PMU_MISC_CON1 */
1394 .idle_offset = 0x0c,
1395 .ack_offset = 0x0c,
1396
1397 .num_domains = ARRAY_SIZE(rk3066_pm_domains),
1398 .domain_info = rk3066_pm_domains,
1399 };
1400
1401 static const struct rockchip_pmu_info rk3128_pmu = {
1402 .pwr_offset = 0x04,
1403 .status_offset = 0x08,
1404 .req_offset = 0x0c,
1405 .idle_offset = 0x10,
1406 .ack_offset = 0x10,
1407
1408 .num_domains = ARRAY_SIZE(rk3128_pm_domains),
1409 .domain_info = rk3128_pm_domains,
1410 };
1411
1412 static const struct rockchip_pmu_info rk3188_pmu = {
1413 .pwr_offset = 0x08,
1414 .status_offset = 0x0c,
1415 .req_offset = 0x38, /* PMU_MISC_CON1 */
1416 .idle_offset = 0x0c,
1417 .ack_offset = 0x0c,
1418
1419 .num_domains = ARRAY_SIZE(rk3188_pm_domains),
1420 .domain_info = rk3188_pm_domains,
1421 };
1422
1423 static const struct rockchip_pmu_info rk3228_pmu = {
1424 .req_offset = 0x40c,
1425 .idle_offset = 0x488,
1426 .ack_offset = 0x488,
1427
1428 .num_domains = ARRAY_SIZE(rk3228_pm_domains),
1429 .domain_info = rk3228_pm_domains,
1430 };
1431
1432 static const struct rockchip_pmu_info rk3288_pmu = {
1433 .pwr_offset = 0x08,
1434 .status_offset = 0x0c,
1435 .req_offset = 0x10,
1436 .idle_offset = 0x14,
1437 .ack_offset = 0x14,
1438
1439 .core_pwrcnt_offset = 0x34,
1440 .gpu_pwrcnt_offset = 0x3c,
1441
1442 .core_power_transition_time = 24, /* 1us */
1443 .gpu_power_transition_time = 24, /* 1us */
1444
1445 .num_domains = ARRAY_SIZE(rk3288_pm_domains),
1446 .domain_info = rk3288_pm_domains,
1447 };
1448
1449 static const struct rockchip_pmu_info rk3328_pmu = {
1450 .req_offset = 0x414,
1451 .idle_offset = 0x484,
1452 .ack_offset = 0x484,
1453
1454 .num_domains = ARRAY_SIZE(rk3328_pm_domains),
1455 .domain_info = rk3328_pm_domains,
1456 };
1457
1458 static const struct rockchip_pmu_info rk3366_pmu = {
1459 .pwr_offset = 0x0c,
1460 .status_offset = 0x10,
1461 .req_offset = 0x3c,
1462 .idle_offset = 0x40,
1463 .ack_offset = 0x40,
1464
1465 .core_pwrcnt_offset = 0x48,
1466 .gpu_pwrcnt_offset = 0x50,
1467
1468 .core_power_transition_time = 24,
1469 .gpu_power_transition_time = 24,
1470
1471 .num_domains = ARRAY_SIZE(rk3366_pm_domains),
1472 .domain_info = rk3366_pm_domains,
1473 };
1474
1475 static const struct rockchip_pmu_info rk3368_pmu = {
1476 .pwr_offset = 0x0c,
1477 .status_offset = 0x10,
1478 .req_offset = 0x3c,
1479 .idle_offset = 0x40,
1480 .ack_offset = 0x40,
1481
1482 .core_pwrcnt_offset = 0x48,
1483 .gpu_pwrcnt_offset = 0x50,
1484
1485 .core_power_transition_time = 24,
1486 .gpu_power_transition_time = 24,
1487
1488 .num_domains = ARRAY_SIZE(rk3368_pm_domains),
1489 .domain_info = rk3368_pm_domains,
1490 };
1491
1492 static const struct rockchip_pmu_info rk3399_pmu = {
1493 .pwr_offset = 0x14,
1494 .status_offset = 0x18,
1495 .req_offset = 0x60,
1496 .idle_offset = 0x64,
1497 .ack_offset = 0x68,
1498
1499 /* ARM Trusted Firmware manages power transition times */
1500
1501 .num_domains = ARRAY_SIZE(rk3399_pm_domains),
1502 .domain_info = rk3399_pm_domains,
1503 };
1504
1505 static const struct rockchip_pmu_info rk3528_pmu = {
1506 .pwr_offset = 0x1210,
1507 .status_offset = 0x1230,
1508 .req_offset = 0x1110,
1509 .idle_offset = 0x1128,
1510 .ack_offset = 0x1120,
1511
1512 .num_domains = ARRAY_SIZE(rk3528_pm_domains),
1513 .domain_info = rk3528_pm_domains,
1514 };
1515
1516 static const struct rockchip_pmu_info rk3562_pmu = {
1517 .pwr_offset = 0x210,
1518 .status_offset = 0x230,
1519 .req_offset = 0x110,
1520 .idle_offset = 0x128,
1521 .ack_offset = 0x120,
1522 .clk_ungate_offset = 0x140,
1523
1524 .num_domains = ARRAY_SIZE(rk3562_pm_domains),
1525 .domain_info = rk3562_pm_domains,
1526 };
1527
1528 static const struct rockchip_pmu_info rk3568_pmu = {
1529 .pwr_offset = 0xa0,
1530 .status_offset = 0x98,
1531 .req_offset = 0x50,
1532 .idle_offset = 0x68,
1533 .ack_offset = 0x60,
1534
1535 .num_domains = ARRAY_SIZE(rk3568_pm_domains),
1536 .domain_info = rk3568_pm_domains,
1537 };
1538
1539 static const struct rockchip_pmu_info rk3576_pmu = {
1540 .pwr_offset = 0x210,
1541 .status_offset = 0x230,
1542 .chain_status_offset = 0x248,
1543 .mem_status_offset = 0x250,
1544 .mem_pwr_offset = 0x300,
1545 .req_offset = 0x110,
1546 .idle_offset = 0x128,
1547 .ack_offset = 0x120,
1548 .repair_status_offset = 0x570,
1549 .clk_ungate_offset = 0x140,
1550
1551 .num_domains = ARRAY_SIZE(rk3576_pm_domains),
1552 .domain_info = rk3576_pm_domains,
1553 };
1554
1555 static const struct rockchip_pmu_info rk3588_pmu = {
1556 .pwr_offset = 0x14c,
1557 .status_offset = 0x180,
1558 .req_offset = 0x10c,
1559 .idle_offset = 0x120,
1560 .ack_offset = 0x118,
1561 .mem_pwr_offset = 0x1a0,
1562 .chain_status_offset = 0x1f0,
1563 .mem_status_offset = 0x1f8,
1564 .repair_status_offset = 0x290,
1565
1566 .num_domains = ARRAY_SIZE(rk3588_pm_domains),
1567 .domain_info = rk3588_pm_domains,
1568 };
1569
1570 static const struct rockchip_pmu_info rv1126_pmu = {
1571 .pwr_offset = 0x110,
1572 .status_offset = 0x108,
1573 .req_offset = 0xc0,
1574 .idle_offset = 0xd8,
1575 .ack_offset = 0xd0,
1576
1577 .num_domains = ARRAY_SIZE(rv1126_pm_domains),
1578 .domain_info = rv1126_pm_domains,
1579 };
1580
1581 static const struct rockchip_pmu_info rv1126b_pmu = {
1582 .pwr_offset = 0x210,
1583 .status_offset = 0x230,
1584 .req_offset = 0x110,
1585 .idle_offset = 0x128,
1586 .ack_offset = 0x120,
1587 .clk_ungate_offset = 0x140,
1588
1589 .num_domains = ARRAY_SIZE(rv1126b_pm_domains),
1590 .domain_info = rv1126b_pm_domains,
1591 };
1592
1593 static const struct of_device_id rockchip_pm_domain_dt_match[] = {
1594 {
1595 .compatible = "rockchip,px30-power-controller",
1596 .data = (void *)&px30_pmu,
1597 },
1598 {
1599 .compatible = "rockchip,rk3036-power-controller",
1600 .data = (void *)&rk3036_pmu,
1601 },
1602 {
1603 .compatible = "rockchip,rk3066-power-controller",
1604 .data = (void *)&rk3066_pmu,
1605 },
1606 {
1607 .compatible = "rockchip,rk3128-power-controller",
1608 .data = (void *)&rk3128_pmu,
1609 },
1610 {
1611 .compatible = "rockchip,rk3188-power-controller",
1612 .data = (void *)&rk3188_pmu,
1613 },
1614 {
1615 .compatible = "rockchip,rk3228-power-controller",
1616 .data = (void *)&rk3228_pmu,
1617 },
1618 {
1619 .compatible = "rockchip,rk3288-power-controller",
1620 .data = (void *)&rk3288_pmu,
1621 },
1622 {
1623 .compatible = "rockchip,rk3328-power-controller",
1624 .data = (void *)&rk3328_pmu,
1625 },
1626 {
1627 .compatible = "rockchip,rk3366-power-controller",
1628 .data = (void *)&rk3366_pmu,
1629 },
1630 {
1631 .compatible = "rockchip,rk3368-power-controller",
1632 .data = (void *)&rk3368_pmu,
1633 },
1634 {
1635 .compatible = "rockchip,rk3399-power-controller",
1636 .data = (void *)&rk3399_pmu,
1637 },
1638 {
1639 .compatible = "rockchip,rk3528-power-controller",
1640 .data = (void *)&rk3528_pmu,
1641 },
1642 {
1643 .compatible = "rockchip,rk3562-power-controller",
1644 .data = (void *)&rk3562_pmu,
1645 },
1646 {
1647 .compatible = "rockchip,rk3568-power-controller",
1648 .data = (void *)&rk3568_pmu,
1649 },
1650 {
1651 .compatible = "rockchip,rk3576-power-controller",
1652 .data = (void *)&rk3576_pmu,
1653 },
1654 {
1655 .compatible = "rockchip,rk3588-power-controller",
1656 .data = (void *)&rk3588_pmu,
1657 },
1658 {
1659 .compatible = "rockchip,rv1126-power-controller",
1660 .data = (void *)&rv1126_pmu,
1661 },
1662 {
1663 .compatible = "rockchip,rv1126b-power-controller",
1664 .data = (void *)&rv1126b_pmu,
1665 },
1666 { /* sentinel */ },
1667 };
1668
1669 static struct platform_driver rockchip_pm_domain_driver = {
1670 .probe = rockchip_pm_domain_probe,
1671 .driver = {
1672 .name = "rockchip-pm-domain",
1673 .of_match_table = rockchip_pm_domain_dt_match,
1674 /*
1675 * We can't forcibly eject devices from the power
1676 * domain, so we can't really remove power domains
1677 * once they were added.
1678 */
1679 .suppress_bind_attrs = true,
1680 },
1681 };
1682
rockchip_pm_domain_drv_register(void)1683 static int __init rockchip_pm_domain_drv_register(void)
1684 {
1685 return platform_driver_register(&rockchip_pm_domain_driver);
1686 }
1687 postcore_initcall(rockchip_pm_domain_drv_register);
1688