1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Common Board Device Tree for 4 * Microsoft Mobile MSM8994 Octagon Platforms 5 * 6 * Copyright (c) 2020, Konrad Dybcio 7 * Copyright (c) 2020, Gustave Monce <gustave.monce@outlook.com> 8 */ 9 10#include "pm8994.dtsi" 11#include "pmi8994.dtsi" 12#include <dt-bindings/gpio/gpio.h> 13#include <dt-bindings/input/gpio-keys.h> 14#include <dt-bindings/pinctrl/qcom,pmic-gpio.h> 15 16/* 17 * Delete all generic (msm8994.dtsi) reserved 18 * memory mappings which are different in this device. 19 */ 20/delete-node/ &adsp_mem; 21/delete-node/ &audio_mem; 22/delete-node/ &cont_splash_mem; 23/delete-node/ &mba_mem; 24/delete-node/ &mpss_mem; 25/delete-node/ &peripheral_region; 26/delete-node/ &res_hyp_mem; 27/delete-node/ &rmtfs_mem; 28/delete-node/ &smem_mem; 29 30/ { 31 /* 32 * Most Lumia 950/XL users use GRUB to load their kernels, 33 * hence there is no need for msm-id and friends. 34 */ 35 36 /* 37 * This enables graphical output via bootloader-enabled display. 38 * acpi=no is required due to WP platforms having ACPI support, but 39 * only for Windows-based OSes. 40 */ 41 chosen { 42 bootargs = "earlycon=efifb console=efifb acpi=no"; 43 44 #address-cells = <2>; 45 #size-cells = <2>; 46 ranges; 47 }; 48 49 clocks { 50 divclk4: divclk4 { 51 compatible = "fixed-clock"; 52 #clock-cells = <0>; 53 54 clock-frequency = <32768>; 55 clock-output-names = "divclk4"; 56 57 pinctrl-names = "default"; 58 pinctrl-0 = <&divclk4_pin_a>; 59 }; 60 }; 61 62 gpio-keys { 63 compatible = "gpio-keys"; 64 autorepeat; 65 66 volup-key { 67 label = "Volume Up"; 68 gpios = <&pm8994_gpios 3 GPIO_ACTIVE_LOW>; 69 linux,input-type = <1>; 70 linux,code = <KEY_VOLUMEUP>; 71 wakeup-source; 72 debounce-interval = <15>; 73 }; 74 75 camsnap-key { 76 label = "Camera Snapshot"; 77 gpios = <&pm8994_gpios 4 GPIO_ACTIVE_LOW>; 78 linux,input-type = <1>; 79 linux,code = <KEY_CAMERA>; 80 wakeup-source; 81 debounce-interval = <15>; 82 }; 83 84 camfocus-key { 85 label = "Camera Focus"; 86 gpios = <&pm8994_gpios 5 GPIO_ACTIVE_LOW>; 87 linux,input-type = <1>; 88 linux,code = <KEY_VOLUMEUP>; 89 wakeup-source; 90 debounce-interval = <15>; 91 }; 92 }; 93 94 gpio-hall-sensor { 95 compatible = "gpio-keys"; 96 97 pinctrl-names = "default"; 98 pinctrl-0 = <&hall_front_default &hall_back_default>; 99 100 label = "GPIO Hall Effect Sensor"; 101 102 event-hall-front-sensor { 103 label = "Hall Effect Front Sensor"; 104 gpios = <&tlmm 42 GPIO_ACTIVE_HIGH>; 105 linux,input-type = <EV_SW>; 106 linux,code = <SW_LID>; 107 linux,can-disable; 108 }; 109 110 event-hall-back-sensor { 111 label = "Hall Effect Back Sensor"; 112 gpios = <&tlmm 75 GPIO_ACTIVE_HIGH>; 113 linux,input-type = <EV_SW>; 114 linux,code = <SW_MACHINE_COVER>; 115 linux,can-disable; 116 }; 117 }; 118 119 reserved-memory { 120 /* 121 * This device being a WP platform has a very different 122 * memory layout than other Android based devices. 123 * This memory layout is directly copied from the original 124 * device UEFI firmware, and adapted based on observations 125 * using JTAG for the Qualcomm Peripheral Image regions. 126 */ 127 128 uefi_mem: memory@200000 { 129 reg = <0 0x00200000 0 0x100000>; 130 no-map; 131 }; 132 133 mppark_mem: memory@300000 { 134 reg = <0 0x00300000 0 0x80000>; 135 no-map; 136 }; 137 138 fbpt_mem: memory@380000 { 139 reg = <0 0x00380000 0 0x1000>; 140 no-map; 141 }; 142 143 dbg2_mem: memory@381000 { 144 reg = <0 0x00381000 0 0x4000>; 145 no-map; 146 }; 147 148 capsule_mem: memory@385000 { 149 reg = <0 0x00385000 0 0x1000>; 150 no-map; 151 }; 152 153 tpmctrl_mem: memory@386000 { 154 reg = <0 0x00386000 0 0x3000>; 155 no-map; 156 }; 157 158 uefiinfo_mem: memory@389000 { 159 reg = <0 0x00389000 0 0x1000>; 160 no-map; 161 }; 162 163 reset_mem: memory@389000 { 164 reg = <0 0x00389000 0 0x1000>; 165 no-map; 166 }; 167 168 resuncached_mem: memory@38e000 { 169 reg = <0 0x0038e000 0 0x72000>; 170 no-map; 171 }; 172 173 disp_mem: memory@400000 { 174 reg = <0 0x00400000 0 0x800000>; 175 no-map; 176 }; 177 178 uefistack_mem: memory@c00000 { 179 reg = <0 0x00c00000 0 0x40000>; 180 no-map; 181 }; 182 183 cpuvect_mem: memory@c40000 { 184 reg = <0 0x00c40000 0 0x10000>; 185 no-map; 186 }; 187 188 rescached_mem: memory@400000 { 189 reg = <0 0x00c50000 0 0xb0000>; 190 no-map; 191 }; 192 193 tzapps_mem: memory@6500000 { 194 reg = <0 0x06500000 0 0x500000>; 195 no-map; 196 }; 197 198 smem_mem: memory@6a00000 { 199 reg = <0 0x06a00000 0 0x200000>; 200 no-map; 201 }; 202 203 hyp_mem: memory@6c00000 { 204 reg = <0 0x06c00000 0 0x100000>; 205 no-map; 206 }; 207 208 tz_mem: memory@6d00000 { 209 reg = <0 0x06d00000 0 0x160000>; 210 no-map; 211 }; 212 213 rfsa_adsp_mem: memory@6e60000 { 214 reg = <0 0x06e60000 0 0x10000>; 215 no-map; 216 }; 217 218 rfsa_mpss_mem: memory@6e70000 { 219 compatible = "qcom,rmtfs-mem"; 220 reg = <0 0x06e70000 0 0x10000>; 221 no-map; 222 223 qcom,client-id = <1>; 224 }; 225 226 /* 227 * Value obtained from the device original ACPI DSDT table 228 * MPSS_EFS / SBL 229 */ 230 mba_mem: memory@6e80000 { 231 reg = <0 0x06e80000 0 0x180000>; 232 no-map; 233 }; 234 235 /* 236 * Peripheral Image loader region begin! 237 * The region reserved for pil is 0x7000000-0xef00000 238 */ 239 240 mpss_mem: memory@7000000 { 241 reg = <0 0x07000000 0 0x5a00000>; 242 no-map; 243 }; 244 245 adsp_mem: memory@ca00000 { 246 reg = <0 0x0ca00000 0 0x1800000>; 247 no-map; 248 }; 249 250 venus_mem: memory@e200000 { 251 reg = <0 0x0e200000 0 0x500000>; 252 no-map; 253 }; 254 255 pil_metadata_mem: memory@e700000 { 256 reg = <0 0x0e700000 0 0x4000>; 257 no-map; 258 }; 259 260 memory@e704000 { 261 reg = <0 0x0e704000 0 0x7fc000>; 262 no-map; 263 }; 264 /* Peripheral Image loader region end */ 265 266 cnss_mem: memory@ef00000 { 267 reg = <0 0x0ef00000 0 0x300000>; 268 no-map; 269 }; 270 }; 271}; 272 273&blsp1_i2c1 { 274 status = "okay"; 275 276 rmi4-i2c-dev@4b { 277 compatible = "syna,rmi4-i2c"; 278 reg = <0x4b>; 279 #address-cells = <1>; 280 #size-cells = <0>; 281 282 interrupt-parent = <&tlmm>; 283 interrupts = <77 IRQ_TYPE_EDGE_FALLING>; 284 285 rmi4-f01@1 { 286 reg = <0x01>; 287 syna,nosleep-mode = <1>; 288 }; 289 290 rmi4-f12@12 { 291 reg = <0x12>; 292 syna,sensor-type = <1>; 293 syna,clip-x-low = <0>; 294 syna,clip-x-high = <1440>; 295 syna,clip-y-low = <0>; 296 syna,clip-y-high = <2560>; 297 }; 298 }; 299}; 300 301&blsp1_i2c2 { 302 status = "okay"; 303 304 /* 305 * This device uses the Texas Instruments TAS2553, however the TAS2552 driver 306 * seems to work here. In the future a proper driver might need to 307 * be written for this device. 308 */ 309 tas2553: tas2553@40 { 310 compatible = "ti,tas2552"; 311 reg = <0x40>; 312 313 vbat-supply = <&vph_pwr>; 314 iovdd-supply = <&vreg_s4a_1p8>; 315 avdd-supply = <&vreg_s4a_1p8>; 316 317 enable-gpio = <&pm8994_gpios 12 GPIO_ACTIVE_HIGH>; 318 }; 319}; 320 321&blsp1_i2c5 { 322 status = "okay"; 323 324 ak09912: magnetometer@c { 325 compatible = "asahi-kasei,ak09912"; 326 reg = <0xc>; 327 328 interrupt-parent = <&tlmm>; 329 interrupts = <26 IRQ_TYPE_EDGE_RISING>; 330 331 vdd-supply = <&vreg_l18a_2p85>; 332 vid-supply = <&vreg_lvs2a_1p8>; 333 }; 334 335 zpa2326: barometer@5c { 336 compatible = "murata,zpa2326"; 337 reg = <0x5c>; 338 339 interrupt-parent = <&tlmm>; 340 interrupts = <74 IRQ_TYPE_EDGE_RISING>; 341 342 vdd-supply = <&vreg_lvs2a_1p8>; 343 }; 344 345 mpu6050: accelerometer@68 { 346 compatible = "invensense,mpu6500"; 347 reg = <0x68>; 348 349 interrupt-parent = <&tlmm>; 350 interrupts = <64 IRQ_TYPE_EDGE_RISING>; 351 352 vdd-supply = <&vreg_lvs2a_1p8>; 353 vddio-supply = <&vreg_lvs2a_1p8>; 354 }; 355}; 356 357&blsp1_i2c6 { 358 status = "okay"; 359 360 pn547: pn547@28 { 361 compatible = "nxp,pn544-i2c"; 362 363 reg = <0x28>; 364 365 interrupt-parent = <&tlmm>; 366 interrupts = <29 IRQ_TYPE_EDGE_RISING>; 367 368 enable-gpios = <&tlmm 30 GPIO_ACTIVE_HIGH>; 369 firmware-gpios = <&tlmm 94 GPIO_ACTIVE_HIGH>; 370 }; 371}; 372 373&blsp1_uart2 { 374 status = "okay"; 375}; 376 377&blsp2_i2c1 { 378 status = "okay"; 379 380 sideinteraction: touch@2c { 381 compatible = "ad,ad7147_captouch"; 382 reg = <0x2c>; 383 384 pinctrl-names = "default", "sleep"; 385 pinctrl-0 = <&grip_default>; 386 pinctrl-1 = <&grip_sleep>; 387 388 interrupts = <&tlmm 96 IRQ_TYPE_EDGE_FALLING>; 389 390 button_num = <8>; 391 touchpad_num = <0>; 392 wheel_num = <0>; 393 slider_num = <0>; 394 395 vcc-supply = <&vreg_l18a_2p85>; 396 }; 397 398 /* 399 * The QPDS-T900/QPDS-T930 is a customized part built for Nokia 400 * by Avago. It is very similar to the Avago APDS-9930 with some 401 * minor differences. In the future a proper driver might need to 402 * be written for this device. For now this works fine. 403 */ 404 qpdst900: qpdst900@39 { 405 compatible = "avago,apds9930"; 406 reg = <0x39>; 407 408 interrupt-parent = <&tlmm>; 409 interrupts = <40 IRQ_TYPE_EDGE_FALLING>; 410 }; 411}; 412 413&blsp2_i2c5 { 414 status = "okay"; 415 416 fm_radio: si4705@11 { 417 compatible = "silabs,si470x"; 418 reg = <0x11>; 419 420 interrupt-parent = <&tlmm>; 421 interrupts = <9 IRQ_TYPE_EDGE_FALLING>; 422 reset-gpios = <&tlmm 93 GPIO_ACTIVE_HIGH>; 423 }; 424 425 vreg_lpddr_1p1: fan53526a@6c { 426 compatible = "fcs,fan53526"; 427 reg = <0x6c>; 428 429 regulator-min-microvolt = <1100000>; 430 regulator-max-microvolt = <1100000>; 431 vin-supply = <&vph_pwr>; 432 fcs,suspend-voltage-selector = <1>; 433 regulator-always-on; /* Turning off DDR power doesn't sound good. */ 434 }; 435 436 /* ANX7816 HDMI bridge (needs MDSS HDMI) */ 437}; 438 439&blsp2_spi4 { 440 status = "okay"; 441 442 /* 443 * This device is a Lattice UC120 USB-C PD PHY. 444 * It is actually a Lattice iCE40 FPGA pre-programmed by 445 * the device firmware with a specific bitstream 446 * enabling USB Type C PHY functionality. 447 * Communication is done via a proprietary protocol over SPI. 448 * 449 * TODO: Once a proper driver is available, replace this. 450 */ 451 uc120: ice5lp2k@0 { 452 compatible = "lattice,ice40-fpga-mgr"; 453 reg = <0>; 454 spi-max-frequency = <5000000>; 455 cdone-gpios = <&tlmm 95 GPIO_ACTIVE_HIGH>; 456 reset-gpios = <&pmi8994_gpios 4 GPIO_ACTIVE_LOW>; 457 }; 458}; 459 460&blsp2_uart2 { 461 status = "okay"; 462 463 qca6174_bt: bluetooth { 464 compatible = "qcom,qca6174-bt"; 465 466 enable-gpios = <&pm8994_gpios 19 GPIO_ACTIVE_HIGH>; 467 clocks = <&divclk4>; 468 }; 469}; 470 471&pm8994_gpios { 472 bt_en_gpios: bt-en-gpios-state { 473 pinconf { 474 pins = "gpio19"; 475 function = PMIC_GPIO_FUNC_NORMAL; 476 output-low; 477 power-source = <PM8994_GPIO_S4>; 478 qcom,drive-strength = <PMIC_GPIO_STRENGTH_LOW>; 479 bias-pull-down; 480 }; 481 }; 482 483 divclk4_pin_a: divclk4-state { 484 pinconf { 485 pins = "gpio18"; 486 function = PMIC_GPIO_FUNC_FUNC2; 487 power-source = <PM8994_GPIO_S4>; 488 bias-disable; 489 }; 490 }; 491}; 492 493&pm8994_pon { 494 pwrkey { 495 compatible = "qcom,pm8941-pwrkey"; 496 interrupts = <0 8 0 IRQ_TYPE_EDGE_BOTH>; 497 debounce = <15625>; 498 linux,code = <KEY_POWER>; 499 }; 500 501 resin { 502 compatible = "qcom,pm8941-resin"; 503 interrupts = <0 8 1 IRQ_TYPE_EDGE_BOTH>; 504 debounce = <15625>; 505 linux,code = <KEY_VOLUMEDOWN>; 506 }; 507}; 508 509&pmi8994_gpios { 510 pinctrl-0 = <&hd3ss460_pol &hd3ss460_amsel &hd3ss460_en>; 511 pinctrl-names = "default"; 512 513 /* 514 * This device uses a TI HD3SS460 Type-C MUX 515 * As this device has no driver currently, 516 * the configuration for USB Face Up is set-up here. 517 * 518 * TODO: remove once a driver is available 519 * TODO: add VBUS GPIO 5 520 */ 521 hd3ss460_pol: pol-low-state { 522 pins = "gpio8"; 523 function = PMIC_GPIO_FUNC_NORMAL; 524 qcom,drive-strength = <3>; 525 bias-pull-down; 526 }; 527 528 hd3ss460_amsel: amsel-high-state { 529 pins = "gpio9"; 530 function = PMIC_GPIO_FUNC_NORMAL; 531 qcom,drive-strength = <1>; 532 bias-pull-up; 533 }; 534 535 hd3ss460_en: en-high-state { 536 pins = "gpio10"; 537 function = PMIC_GPIO_FUNC_NORMAL; 538 qcom,drive-strength = <1>; 539 bias-pull-up; 540 }; 541}; 542 543&pmi8994_spmi_regulators { 544 vdd_gfx: s2 { 545 regulator-min-microvolt = <980000>; 546 regulator-max-microvolt = <980000>; 547 }; 548}; 549 550&rpm_requests { 551 /* These values were taken from the original firmware ACPI tables */ 552 pm8994_regulators: regulators-0 { 553 compatible = "qcom,rpm-pm8994-regulators"; 554 555 vdd_s1-supply = <&vph_pwr>; 556 vdd_s2-supply = <&vph_pwr>; 557 vdd_s3-supply = <&vph_pwr>; 558 vdd_s4-supply = <&vph_pwr>; 559 vdd_s5-supply = <&vph_pwr>; 560 vdd_s6-supply = <&vph_pwr>; 561 vdd_s7-supply = <&vph_pwr>; 562 vdd_s8-supply = <&vph_pwr>; 563 vdd_s9-supply = <&vph_pwr>; 564 vdd_s10-supply = <&vph_pwr>; 565 vdd_s11-supply = <&vph_pwr>; 566 vdd_s12-supply = <&vph_pwr>; 567 vdd_l1-supply = <&vreg_s1b_1p0>; 568 vdd_l2_l26_l28-supply = <&vreg_s3a_1p3>; 569 vdd_l3_l11-supply = <&vreg_s3a_1p3>; 570 vdd_l4_l27_l31-supply = <&vreg_s3a_1p3>; 571 vdd_l5_l7-supply = <&vreg_s5a_2p15>; 572 vdd_l6_l12_l32-supply = <&vreg_s5a_2p15>; 573 vdd_l8_l16_l30-supply = <&vph_pwr>; 574 vdd_l9_l10_l18_l22-supply = <&vph_pwr_bbyp>; 575 vdd_l13_l19_l23_l24-supply = <&vph_pwr_bbyp>; 576 vdd_l14_l15-supply = <&vreg_s5a_2p15>; 577 vdd_l17_l29-supply = <&vph_pwr_bbyp>; 578 vdd_l20_l21-supply = <&vph_pwr_bbyp>; 579 vdd_l25-supply = <&vreg_s5a_2p15>; 580 vdd_lvs1_2-supply = <&vreg_s4a_1p8>; 581 582 /* S1, S2, S6 and S12 are managed by RPMPD */ 583 584 vreg_s3a_1p3: s3 { 585 regulator-min-microvolt = <1300000>; 586 regulator-max-microvolt = <1300000>; 587 regulator-allow-set-load; 588 regulator-system-load = <300000>; 589 }; 590 591 vreg_s4a_1p8: s4 { 592 regulator-min-microvolt = <1800000>; 593 regulator-max-microvolt = <1800000>; 594 regulator-allow-set-load; 595 regulator-always-on; 596 regulator-system-load = <325000>; 597 }; 598 599 vreg_s5a_2p15: s5 { 600 regulator-min-microvolt = <2150000>; 601 regulator-max-microvolt = <2150000>; 602 regulator-allow-set-load; 603 regulator-system-load = <325000>; 604 }; 605 606 vreg_s7a_1p0: s7 { 607 regulator-min-microvolt = <1000000>; 608 regulator-max-microvolt = <1000000>; 609 }; 610 611 /* 612 * S8 - SPMI-managed VDD_APC0 613 * S9, S10 and S11 (the main one) - SPMI-managed VDD_APC1 614 */ 615 616 vreg_l1a_1p0: l1 { 617 regulator-min-microvolt = <1000000>; 618 regulator-max-microvolt = <1000000>; 619 }; 620 621 vreg_l2a_1p25: l2 { 622 regulator-min-microvolt = <1250000>; 623 regulator-max-microvolt = <1250000>; 624 regulator-allow-set-load; 625 regulator-system-load = <4160>; 626 }; 627 628 vreg_l3a_1p2: l3 { 629 regulator-min-microvolt = <1200000>; 630 regulator-max-microvolt = <1200000>; 631 regulator-always-on; 632 regulator-allow-set-load; 633 regulator-system-load = <80000>; 634 }; 635 636 vreg_l4a_1p225: l4 { 637 regulator-min-microvolt = <1225000>; 638 regulator-max-microvolt = <1225000>; 639 }; 640 641 /* L5 is inaccessible from RPM */ 642 643 vreg_l6a_1p8: l6 { 644 regulator-min-microvolt = <1800000>; 645 regulator-max-microvolt = <1800000>; 646 regulator-allow-set-load; 647 regulator-system-load = <1000>; 648 }; 649 650 /* L7 is inaccessible from RPM */ 651 652 vreg_l8a_1p8: l8 { 653 regulator-min-microvolt = <1800000>; 654 regulator-max-microvolt = <1800000>; 655 }; 656 657 vreg_l9a_1p8: l9 { 658 regulator-min-microvolt = <1800000>; 659 regulator-max-microvolt = <1800000>; 660 }; 661 662 vreg_l10a_1p8: l10 { 663 regulator-min-microvolt = <1800000>; 664 regulator-max-microvolt = <1800000>; 665 }; 666 667 vreg_l11a_1p2: l11 { 668 regulator-min-microvolt = <1200000>; 669 regulator-max-microvolt = <1200000>; 670 regulator-always-on; 671 regulator-allow-set-load; 672 regulator-system-load = <35000>; 673 }; 674 675 vreg_l12a_1p8: l12 { 676 regulator-min-microvolt = <1800000>; 677 regulator-max-microvolt = <1800000>; 678 regulator-always-on; 679 regulator-allow-set-load; 680 regulator-system-load = <50000>; 681 }; 682 683 vreg_l13a_2p95: l13 { 684 regulator-min-microvolt = <1850000>; 685 regulator-max-microvolt = <2950000>; 686 regulator-always-on; 687 regulator-allow-set-load; 688 regulator-system-load = <22000>; 689 }; 690 691 vreg_l14a_1p8: l14 { 692 regulator-min-microvolt = <1800000>; 693 regulator-max-microvolt = <1800000>; 694 regulator-always-on; 695 regulator-allow-set-load; 696 regulator-system-load = <52000>; 697 }; 698 699 vreg_l15a_1p8: l15 { 700 regulator-min-microvolt = <1800000>; 701 regulator-max-microvolt = <1800000>; 702 }; 703 704 vreg_l16a_2p7: l16 { 705 regulator-min-microvolt = <2700000>; 706 regulator-max-microvolt = <2700000>; 707 }; 708 709 vreg_l17a_2p7: l17 { 710 regulator-min-microvolt = <2800000>; 711 regulator-max-microvolt = <2800000>; 712 regulator-always-on; 713 regulator-allow-set-load; 714 regulator-system-load = <300000>; 715 }; 716 717 vreg_l18a_2p85: l18 { 718 regulator-min-microvolt = <2850000>; 719 regulator-max-microvolt = <2850000>; 720 regulator-always-on; 721 regulator-allow-set-load; 722 regulator-system-load = <600000>; 723 }; 724 725 vreg_l19a_3p3: l19 { 726 regulator-min-microvolt = <3300000>; 727 regulator-max-microvolt = <3300000>; 728 regulator-always-on; 729 regulator-allow-set-load; 730 regulator-system-load = <500000>; 731 }; 732 733 vreg_l20a_2p95: l20 { 734 regulator-min-microvolt = <2950000>; 735 regulator-max-microvolt = <2950000>; 736 regulator-always-on; 737 regulator-boot-on; 738 regulator-allow-set-load; 739 regulator-system-load = <570000>; 740 }; 741 742 vreg_l21a_2p95: l21 { 743 regulator-min-microvolt = <2950000>; 744 regulator-max-microvolt = <2950000>; 745 regulator-always-on; 746 regulator-allow-set-load; 747 regulator-system-load = <800000>; 748 }; 749 750 vreg_l22a_3p0: l22 { 751 regulator-min-microvolt = <3000000>; 752 regulator-max-microvolt = <3000000>; 753 regulator-always-on; 754 regulator-allow-set-load; 755 regulator-system-load = <150000>; 756 }; 757 758 vreg_l23a_2p8: l23 { 759 regulator-min-microvolt = <2850000>; 760 regulator-max-microvolt = <2850000>; 761 regulator-always-on; 762 regulator-allow-set-load; 763 regulator-system-load = <80000>; 764 }; 765 766 vreg_l24a_3p075: l24 { 767 regulator-min-microvolt = <3075000>; 768 regulator-max-microvolt = <3150000>; 769 regulator-allow-set-load; 770 regulator-system-load = <5800>; 771 }; 772 773 vreg_l25a_1p1: l25 { 774 regulator-min-microvolt = <1150000>; 775 regulator-max-microvolt = <1150000>; 776 regulator-always-on; 777 regulator-allow-set-load; 778 regulator-system-load = <80000>; 779 }; 780 781 vreg_l26a_1p0: l26 { 782 regulator-min-microvolt = <1000000>; 783 regulator-max-microvolt = <1000000>; 784 }; 785 786 vreg_l27a_1p05: l27 { 787 regulator-min-microvolt = <1000000>; 788 regulator-max-microvolt = <1000000>; 789 regulator-always-on; 790 regulator-allow-set-load; 791 regulator-system-load = <500000>; 792 }; 793 794 vreg_l28a_1p0: l28 { 795 regulator-min-microvolt = <1000000>; 796 regulator-max-microvolt = <1000000>; 797 regulator-always-on; 798 regulator-allow-set-load; 799 regulator-system-load = <26000>; 800 }; 801 802 vreg_l29a_2p8: l29 { 803 regulator-min-microvolt = <2850000>; 804 regulator-max-microvolt = <2850000>; 805 regulator-always-on; 806 regulator-allow-set-load; 807 regulator-system-load = <80000>; 808 }; 809 810 vreg_l30a_1p8: l30 { 811 regulator-min-microvolt = <1800000>; 812 regulator-max-microvolt = <1800000>; 813 regulator-always-on; 814 regulator-allow-set-load; 815 regulator-system-load = <2500>; 816 }; 817 818 vreg_l31a_1p2: l31 { 819 regulator-min-microvolt = <1200000>; 820 regulator-max-microvolt = <1200000>; 821 regulator-always-on; 822 regulator-allow-set-load; 823 regulator-system-load = <600000>; 824 }; 825 826 vreg_l32a_1p8: l32 { 827 regulator-min-microvolt = <1800000>; 828 regulator-max-microvolt = <1800000>; 829 }; 830 831 vreg_lvs1a_1p8: lvs1 { }; 832 833 vreg_lvs2a_1p8: lvs2 { }; 834 }; 835 836 pmi8994_regulators: regulators-1 { 837 compatible = "qcom,rpm-pmi8994-regulators"; 838 839 vdd_s1-supply = <&vph_pwr>; 840 vdd_bst_byp-supply = <&vph_pwr>; 841 842 vreg_s1b_1p0: s1 { 843 regulator-min-microvolt = <1025000>; 844 regulator-max-microvolt = <1025000>; 845 }; 846 847 /* S2 & S3 - VDD_GFX */ 848 849 vph_pwr_bbyp: boost-bypass { 850 regulator-min-microvolt = <3300000>; 851 regulator-max-microvolt = <3300000>; 852 }; 853 }; 854}; 855 856&sdhc1 { 857 status = "okay"; 858 859 /* 860 * This device is shipped with HS400 capabable eMMCs 861 * However various brands have been used in various product batches, 862 * including a Samsung eMMC (BGND3R) which features a quirk with HS400. 863 * Set the speed to HS200 as a safety measure. 864 */ 865 mmc-hs200-1_8v; 866}; 867 868&sdhc2 { 869 status = "okay"; 870 871 pinctrl-names = "default", "sleep"; 872 pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on>; 873 pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off>; 874 875 vmmc-supply = <&vreg_l21a_2p95>; 876 vqmmc-supply = <&vreg_l13a_2p95>; 877 878 cd-gpios = <&pm8994_gpios 8 GPIO_ACTIVE_LOW>; 879}; 880 881&tlmm { 882 grip_default: grip-default-state { 883 pins = "gpio39"; 884 function = "gpio"; 885 drive-strength = <6>; 886 bias-pull-down; 887 }; 888 889 grip_sleep: grip-sleep-state { 890 pins = "gpio39"; 891 function = "gpio"; 892 drive-strength = <2>; 893 bias-pull-down; 894 }; 895 896 hall_front_default: hall-front-default-state { 897 pins = "gpio42"; 898 function = "gpio"; 899 drive-strength = <2>; 900 bias-disable; 901 }; 902 903 hall_back_default: hall-back-default-state { 904 pins = "gpio75"; 905 function = "gpio"; 906 drive-strength = <2>; 907 bias-disable; 908 }; 909}; 910