1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. 4 * Copyright (c) 2020-2023, Linaro Limited 5 */ 6 7#include <dt-bindings/clock/qcom,dispcc-sm8250.h> 8#include <dt-bindings/clock/qcom,dsi-phy-28nm.h> 9#include <dt-bindings/clock/qcom,gcc-sc8180x.h> 10#include <dt-bindings/clock/qcom,gpucc-sm8150.h> 11#include <dt-bindings/clock/qcom,rpmh.h> 12#include <dt-bindings/clock/qcom,sc8180x-camcc.h> 13#include <dt-bindings/clock/qcom,videocc-sm8150.h> 14#include <dt-bindings/interconnect/qcom,icc.h> 15#include <dt-bindings/interconnect/qcom,osm-l3.h> 16#include <dt-bindings/interconnect/qcom,sc8180x.h> 17#include <dt-bindings/interrupt-controller/arm-gic.h> 18#include <dt-bindings/phy/phy-qcom-qmp.h> 19#include <dt-bindings/power/qcom-rpmpd.h> 20#include <dt-bindings/soc/qcom,rpmh-rsc.h> 21#include <dt-bindings/thermal/thermal.h> 22 23/ { 24 interrupt-parent = <&intc>; 25 26 #address-cells = <2>; 27 #size-cells = <2>; 28 29 clocks { 30 xo_board_clk: xo-board { 31 compatible = "fixed-clock"; 32 #clock-cells = <0>; 33 clock-frequency = <38400000>; 34 }; 35 36 sleep_clk: sleep-clk { 37 compatible = "fixed-clock"; 38 #clock-cells = <0>; 39 clock-frequency = <32764>; 40 clock-output-names = "sleep_clk"; 41 }; 42 }; 43 44 cpus { 45 #address-cells = <2>; 46 #size-cells = <0>; 47 48 cpu0: cpu@0 { 49 device_type = "cpu"; 50 compatible = "qcom,kryo485"; 51 reg = <0x0 0x0>; 52 enable-method = "psci"; 53 capacity-dmips-mhz = <602>; 54 next-level-cache = <&l2_0>; 55 qcom,freq-domain = <&cpufreq_hw 0>; 56 operating-points-v2 = <&cpu0_opp_table>; 57 interconnects = <&gem_noc MASTER_AMPSS_M0 3 &mc_virt SLAVE_EBI_CH0 3>, 58 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 59 power-domains = <&cpu_pd0>; 60 power-domain-names = "psci"; 61 #cooling-cells = <2>; 62 clocks = <&cpufreq_hw 0>; 63 64 l2_0: l2-cache { 65 compatible = "cache"; 66 cache-level = <2>; 67 cache-unified; 68 next-level-cache = <&l3_0>; 69 l3_0: l3-cache { 70 compatible = "cache"; 71 cache-level = <3>; 72 cache-unified; 73 }; 74 }; 75 }; 76 77 cpu1: cpu@100 { 78 device_type = "cpu"; 79 compatible = "qcom,kryo485"; 80 reg = <0x0 0x100>; 81 enable-method = "psci"; 82 capacity-dmips-mhz = <602>; 83 next-level-cache = <&l2_100>; 84 qcom,freq-domain = <&cpufreq_hw 0>; 85 operating-points-v2 = <&cpu0_opp_table>; 86 interconnects = <&gem_noc MASTER_AMPSS_M0 3 &mc_virt SLAVE_EBI_CH0 3>, 87 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 88 power-domains = <&cpu_pd1>; 89 power-domain-names = "psci"; 90 #cooling-cells = <2>; 91 clocks = <&cpufreq_hw 0>; 92 93 l2_100: l2-cache { 94 compatible = "cache"; 95 cache-level = <2>; 96 cache-unified; 97 next-level-cache = <&l3_0>; 98 }; 99 100 }; 101 102 cpu2: cpu@200 { 103 device_type = "cpu"; 104 compatible = "qcom,kryo485"; 105 reg = <0x0 0x200>; 106 enable-method = "psci"; 107 capacity-dmips-mhz = <602>; 108 next-level-cache = <&l2_200>; 109 qcom,freq-domain = <&cpufreq_hw 0>; 110 operating-points-v2 = <&cpu0_opp_table>; 111 interconnects = <&gem_noc MASTER_AMPSS_M0 3 &mc_virt SLAVE_EBI_CH0 3>, 112 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 113 power-domains = <&cpu_pd2>; 114 power-domain-names = "psci"; 115 #cooling-cells = <2>; 116 clocks = <&cpufreq_hw 0>; 117 118 l2_200: l2-cache { 119 compatible = "cache"; 120 cache-level = <2>; 121 cache-unified; 122 next-level-cache = <&l3_0>; 123 }; 124 }; 125 126 cpu3: cpu@300 { 127 device_type = "cpu"; 128 compatible = "qcom,kryo485"; 129 reg = <0x0 0x300>; 130 enable-method = "psci"; 131 capacity-dmips-mhz = <602>; 132 next-level-cache = <&l2_300>; 133 qcom,freq-domain = <&cpufreq_hw 0>; 134 operating-points-v2 = <&cpu0_opp_table>; 135 interconnects = <&gem_noc MASTER_AMPSS_M0 3 &mc_virt SLAVE_EBI_CH0 3>, 136 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 137 power-domains = <&cpu_pd3>; 138 power-domain-names = "psci"; 139 #cooling-cells = <2>; 140 clocks = <&cpufreq_hw 0>; 141 142 l2_300: l2-cache { 143 compatible = "cache"; 144 cache-unified; 145 cache-level = <2>; 146 next-level-cache = <&l3_0>; 147 }; 148 }; 149 150 cpu4: cpu@400 { 151 device_type = "cpu"; 152 compatible = "qcom,kryo485"; 153 reg = <0x0 0x400>; 154 enable-method = "psci"; 155 capacity-dmips-mhz = <1024>; 156 next-level-cache = <&l2_400>; 157 qcom,freq-domain = <&cpufreq_hw 1>; 158 operating-points-v2 = <&cpu4_opp_table>; 159 interconnects = <&gem_noc MASTER_AMPSS_M0 3 &mc_virt SLAVE_EBI_CH0 3>, 160 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 161 power-domains = <&cpu_pd4>; 162 power-domain-names = "psci"; 163 #cooling-cells = <2>; 164 clocks = <&cpufreq_hw 1>; 165 166 l2_400: l2-cache { 167 compatible = "cache"; 168 cache-unified; 169 cache-level = <2>; 170 next-level-cache = <&l3_0>; 171 }; 172 }; 173 174 cpu5: cpu@500 { 175 device_type = "cpu"; 176 compatible = "qcom,kryo485"; 177 reg = <0x0 0x500>; 178 enable-method = "psci"; 179 capacity-dmips-mhz = <1024>; 180 next-level-cache = <&l2_500>; 181 qcom,freq-domain = <&cpufreq_hw 1>; 182 operating-points-v2 = <&cpu4_opp_table>; 183 interconnects = <&gem_noc MASTER_AMPSS_M0 3 &mc_virt SLAVE_EBI_CH0 3>, 184 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 185 power-domains = <&cpu_pd5>; 186 power-domain-names = "psci"; 187 #cooling-cells = <2>; 188 clocks = <&cpufreq_hw 1>; 189 190 l2_500: l2-cache { 191 compatible = "cache"; 192 cache-unified; 193 cache-level = <2>; 194 next-level-cache = <&l3_0>; 195 }; 196 }; 197 198 cpu6: cpu@600 { 199 device_type = "cpu"; 200 compatible = "qcom,kryo485"; 201 reg = <0x0 0x600>; 202 enable-method = "psci"; 203 capacity-dmips-mhz = <1024>; 204 next-level-cache = <&l2_600>; 205 qcom,freq-domain = <&cpufreq_hw 1>; 206 operating-points-v2 = <&cpu4_opp_table>; 207 interconnects = <&gem_noc MASTER_AMPSS_M0 3 &mc_virt SLAVE_EBI_CH0 3>, 208 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 209 power-domains = <&cpu_pd6>; 210 power-domain-names = "psci"; 211 #cooling-cells = <2>; 212 clocks = <&cpufreq_hw 1>; 213 214 l2_600: l2-cache { 215 compatible = "cache"; 216 cache-unified; 217 cache-level = <2>; 218 next-level-cache = <&l3_0>; 219 }; 220 }; 221 222 cpu7: cpu@700 { 223 device_type = "cpu"; 224 compatible = "qcom,kryo485"; 225 reg = <0x0 0x700>; 226 enable-method = "psci"; 227 capacity-dmips-mhz = <1024>; 228 next-level-cache = <&l2_700>; 229 qcom,freq-domain = <&cpufreq_hw 1>; 230 operating-points-v2 = <&cpu4_opp_table>; 231 interconnects = <&gem_noc MASTER_AMPSS_M0 3 &mc_virt SLAVE_EBI_CH0 3>, 232 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 233 power-domains = <&cpu_pd7>; 234 power-domain-names = "psci"; 235 #cooling-cells = <2>; 236 clocks = <&cpufreq_hw 1>; 237 238 l2_700: l2-cache { 239 compatible = "cache"; 240 cache-unified; 241 cache-level = <2>; 242 next-level-cache = <&l3_0>; 243 }; 244 }; 245 246 cpu-map { 247 cluster0 { 248 core0 { 249 cpu = <&cpu0>; 250 }; 251 252 core1 { 253 cpu = <&cpu1>; 254 }; 255 256 core2 { 257 cpu = <&cpu2>; 258 }; 259 260 core3 { 261 cpu = <&cpu3>; 262 }; 263 264 core4 { 265 cpu = <&cpu4>; 266 }; 267 268 core5 { 269 cpu = <&cpu5>; 270 }; 271 272 core6 { 273 cpu = <&cpu6>; 274 }; 275 276 core7 { 277 cpu = <&cpu7>; 278 }; 279 }; 280 }; 281 282 idle-states { 283 entry-method = "psci"; 284 285 little_cpu_sleep_0: cpu-sleep-0-0 { 286 compatible = "arm,idle-state"; 287 arm,psci-suspend-param = <0x40000004>; 288 entry-latency-us = <355>; 289 exit-latency-us = <909>; 290 min-residency-us = <3934>; 291 local-timer-stop; 292 }; 293 294 big_cpu_sleep_0: cpu-sleep-1-0 { 295 compatible = "arm,idle-state"; 296 arm,psci-suspend-param = <0x40000004>; 297 entry-latency-us = <2411>; 298 exit-latency-us = <1461>; 299 min-residency-us = <4488>; 300 local-timer-stop; 301 }; 302 }; 303 304 domain-idle-states { 305 cluster_sleep_apss_off: cluster-sleep-0 { 306 compatible = "domain-idle-state"; 307 arm,psci-suspend-param = <0x41000044>; 308 entry-latency-us = <3300>; 309 exit-latency-us = <3300>; 310 min-residency-us = <6000>; 311 }; 312 313 cluster_sleep_aoss_sleep: cluster-sleep-1 { 314 compatible = "domain-idle-state"; 315 arm,psci-suspend-param = <0x4100a344>; 316 entry-latency-us = <3263>; 317 exit-latency-us = <6562>; 318 min-residency-us = <9987>; 319 }; 320 }; 321 }; 322 323 cpu0_opp_table: opp-table-cpu0 { 324 compatible = "operating-points-v2"; 325 opp-shared; 326 327 opp-300000000 { 328 opp-hz = /bits/ 64 <300000000>; 329 opp-peak-kBps = <800000 9600000>; 330 }; 331 332 opp-422400000 { 333 opp-hz = /bits/ 64 <422400000>; 334 opp-peak-kBps = <800000 9600000>; 335 }; 336 337 opp-537600000 { 338 opp-hz = /bits/ 64 <537600000>; 339 opp-peak-kBps = <800000 12902400>; 340 }; 341 342 opp-652800000 { 343 opp-hz = /bits/ 64 <652800000>; 344 opp-peak-kBps = <800000 12902400>; 345 }; 346 347 opp-768000000 { 348 opp-hz = /bits/ 64 <768000000>; 349 opp-peak-kBps = <800000 15974400>; 350 }; 351 352 opp-883200000 { 353 opp-hz = /bits/ 64 <883200000>; 354 opp-peak-kBps = <1804000 19660800>; 355 }; 356 357 opp-998400000 { 358 opp-hz = /bits/ 64 <998400000>; 359 opp-peak-kBps = <1804000 19660800>; 360 }; 361 362 opp-1113600000 { 363 opp-hz = /bits/ 64 <1113600000>; 364 opp-peak-kBps = <1804000 22732800>; 365 }; 366 367 opp-1228800000 { 368 opp-hz = /bits/ 64 <1228800000>; 369 opp-peak-kBps = <1804000 22732800>; 370 }; 371 372 opp-1363200000 { 373 opp-hz = /bits/ 64 <1363200000>; 374 opp-peak-kBps = <2188000 25804800>; 375 }; 376 377 opp-1478400000 { 378 opp-hz = /bits/ 64 <1478400000>; 379 opp-peak-kBps = <2188000 31948800>; 380 }; 381 382 opp-1574400000 { 383 opp-hz = /bits/ 64 <1574400000>; 384 opp-peak-kBps = <3072000 31948800>; 385 }; 386 387 opp-1670400000 { 388 opp-hz = /bits/ 64 <1670400000>; 389 opp-peak-kBps = <3072000 31948800>; 390 }; 391 392 opp-1766400000 { 393 opp-hz = /bits/ 64 <1766400000>; 394 opp-peak-kBps = <3072000 31948800>; 395 }; 396 }; 397 398 cpu4_opp_table: opp-table-cpu4 { 399 compatible = "operating-points-v2"; 400 opp-shared; 401 402 opp-825600000 { 403 opp-hz = /bits/ 64 <825600000>; 404 opp-peak-kBps = <1804000 15974400>; 405 }; 406 407 opp-940800000 { 408 opp-hz = /bits/ 64 <940800000>; 409 opp-peak-kBps = <2188000 19660800>; 410 }; 411 412 opp-1056000000 { 413 opp-hz = /bits/ 64 <1056000000>; 414 opp-peak-kBps = <2188000 22732800>; 415 }; 416 417 opp-1171200000 { 418 opp-hz = /bits/ 64 <1171200000>; 419 opp-peak-kBps = <3072000 25804800>; 420 }; 421 422 opp-1286400000 { 423 opp-hz = /bits/ 64 <1286400000>; 424 opp-peak-kBps = <3072000 31948800>; 425 }; 426 427 opp-1420800000 { 428 opp-hz = /bits/ 64 <1420800000>; 429 opp-peak-kBps = <4068000 31948800>; 430 }; 431 432 opp-1536000000 { 433 opp-hz = /bits/ 64 <1536000000>; 434 opp-peak-kBps = <4068000 31948800>; 435 }; 436 437 opp-1651200000 { 438 opp-hz = /bits/ 64 <1651200000>; 439 opp-peak-kBps = <4068000 40550400>; 440 }; 441 442 opp-1766400000 { 443 opp-hz = /bits/ 64 <1766400000>; 444 opp-peak-kBps = <4068000 40550400>; 445 }; 446 447 opp-1881600000 { 448 opp-hz = /bits/ 64 <1881600000>; 449 opp-peak-kBps = <4068000 43008000>; 450 }; 451 452 opp-1996800000 { 453 opp-hz = /bits/ 64 <1996800000>; 454 opp-peak-kBps = <6220000 43008000>; 455 }; 456 457 opp-2131200000 { 458 opp-hz = /bits/ 64 <2131200000>; 459 opp-peak-kBps = <6220000 49152000>; 460 }; 461 462 opp-2246400000 { 463 opp-hz = /bits/ 64 <2246400000>; 464 opp-peak-kBps = <7216000 49152000>; 465 }; 466 467 opp-2361600000 { 468 opp-hz = /bits/ 64 <2361600000>; 469 opp-peak-kBps = <8368000 49152000>; 470 }; 471 472 opp-2457600000 { 473 opp-hz = /bits/ 64 <2457600000>; 474 opp-peak-kBps = <8368000 51609600>; 475 }; 476 477 opp-2553600000 { 478 opp-hz = /bits/ 64 <2553600000>; 479 opp-peak-kBps = <8368000 51609600>; 480 }; 481 482 opp-2649600000 { 483 opp-hz = /bits/ 64 <2649600000>; 484 opp-peak-kBps = <8368000 51609600>; 485 }; 486 487 opp-2745600000 { 488 opp-hz = /bits/ 64 <2745600000>; 489 opp-peak-kBps = <8368000 51609600>; 490 }; 491 492 opp-2841600000 { 493 opp-hz = /bits/ 64 <2841600000>; 494 opp-peak-kBps = <8368000 51609600>; 495 }; 496 497 opp-2918400000 { 498 opp-hz = /bits/ 64 <2918400000>; 499 opp-peak-kBps = <8368000 51609600>; 500 }; 501 502 opp-2995200000 { 503 opp-hz = /bits/ 64 <2995200000>; 504 opp-peak-kBps = <8368000 51609600>; 505 }; 506 }; 507 508 firmware { 509 scm: scm { 510 compatible = "qcom,scm-sc8180x", "qcom,scm"; 511 }; 512 }; 513 514 camnoc_virt: interconnect-camnoc-virt { 515 compatible = "qcom,sc8180x-camnoc-virt"; 516 #interconnect-cells = <2>; 517 qcom,bcm-voters = <&apps_bcm_voter>; 518 }; 519 520 mc_virt: interconnect-mc-virt { 521 compatible = "qcom,sc8180x-mc-virt"; 522 #interconnect-cells = <2>; 523 qcom,bcm-voters = <&apps_bcm_voter>; 524 }; 525 526 qup_virt: interconnect-qup-virt { 527 compatible = "qcom,sc8180x-qup-virt"; 528 #interconnect-cells = <2>; 529 qcom,bcm-voters = <&apps_bcm_voter>; 530 }; 531 532 memory@80000000 { 533 device_type = "memory"; 534 /* We expect the bootloader to fill in the size */ 535 reg = <0x0 0x80000000 0x0 0x0>; 536 }; 537 538 pmu { 539 compatible = "arm,armv8-pmuv3"; 540 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>; 541 }; 542 543 psci { 544 compatible = "arm,psci-1.0"; 545 method = "smc"; 546 547 cpu_pd0: power-domain-cpu0 { 548 #power-domain-cells = <0>; 549 power-domains = <&cluster_pd>; 550 domain-idle-states = <&little_cpu_sleep_0>; 551 }; 552 553 cpu_pd1: power-domain-cpu1 { 554 #power-domain-cells = <0>; 555 power-domains = <&cluster_pd>; 556 domain-idle-states = <&little_cpu_sleep_0>; 557 }; 558 559 cpu_pd2: power-domain-cpu2 { 560 #power-domain-cells = <0>; 561 power-domains = <&cluster_pd>; 562 domain-idle-states = <&little_cpu_sleep_0>; 563 }; 564 565 cpu_pd3: power-domain-cpu3 { 566 #power-domain-cells = <0>; 567 power-domains = <&cluster_pd>; 568 domain-idle-states = <&little_cpu_sleep_0>; 569 }; 570 571 cpu_pd4: power-domain-cpu4 { 572 #power-domain-cells = <0>; 573 power-domains = <&cluster_pd>; 574 domain-idle-states = <&big_cpu_sleep_0>; 575 }; 576 577 cpu_pd5: power-domain-cpu5 { 578 #power-domain-cells = <0>; 579 power-domains = <&cluster_pd>; 580 domain-idle-states = <&big_cpu_sleep_0>; 581 }; 582 583 cpu_pd6: power-domain-cpu6 { 584 #power-domain-cells = <0>; 585 power-domains = <&cluster_pd>; 586 domain-idle-states = <&big_cpu_sleep_0>; 587 }; 588 589 cpu_pd7: power-domain-cpu7 { 590 #power-domain-cells = <0>; 591 power-domains = <&cluster_pd>; 592 domain-idle-states = <&big_cpu_sleep_0>; 593 }; 594 595 cluster_pd: power-domain-cpu-cluster0 { 596 #power-domain-cells = <0>; 597 domain-idle-states = <&cluster_sleep_apss_off &cluster_sleep_aoss_sleep>; 598 }; 599 }; 600 601 reserved-memory { 602 #address-cells = <2>; 603 #size-cells = <2>; 604 ranges; 605 606 hyp_mem: hyp@85700000 { 607 reg = <0x0 0x85700000 0x0 0x600000>; 608 no-map; 609 }; 610 611 xbl_mem: xbl@85d00000 { 612 reg = <0x0 0x85d00000 0x0 0x140000>; 613 no-map; 614 }; 615 616 aop_mem: aop@85f00000 { 617 reg = <0x0 0x85f00000 0x0 0x20000>; 618 no-map; 619 }; 620 621 aop_cmd_db: cmd-db@85f20000 { 622 compatible = "qcom,cmd-db"; 623 reg = <0x0 0x85f20000 0x0 0x20000>; 624 no-map; 625 }; 626 627 reserved@85f40000 { 628 reg = <0x0 0x85f40000 0x0 0x10000>; 629 no-map; 630 }; 631 632 smem_mem: smem@86000000 { 633 compatible = "qcom,smem"; 634 reg = <0x0 0x86000000 0x0 0x200000>; 635 no-map; 636 hwlocks = <&tcsr_mutex 3>; 637 }; 638 639 reserved@86200000 { 640 reg = <0x0 0x86200000 0x0 0x3900000>; 641 no-map; 642 }; 643 644 reserved@89b00000 { 645 reg = <0x0 0x89b00000 0x0 0x1c00000>; 646 no-map; 647 }; 648 649 gpu_mem: memory@98715000 { 650 reg = <0x0 0x98715000 0x0 0x2000>; 651 no-map; 652 }; 653 654 reserved@9d400000 { 655 reg = <0x0 0x9d400000 0x0 0x1000000>; 656 no-map; 657 }; 658 659 reserved@9e400000 { 660 reg = <0x0 0x9e400000 0x0 0x1400000>; 661 no-map; 662 }; 663 664 reserved@9f800000 { 665 reg = <0x0 0x9f800000 0x0 0x800000>; 666 no-map; 667 }; 668 }; 669 670 smp2p-cdsp { 671 compatible = "qcom,smp2p"; 672 qcom,smem = <94>, <432>; 673 674 interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>; 675 676 mboxes = <&apss_shared 6>; 677 678 qcom,local-pid = <0>; 679 qcom,remote-pid = <5>; 680 681 cdsp_smp2p_out: master-kernel { 682 qcom,entry-name = "master-kernel"; 683 #qcom,smem-state-cells = <1>; 684 }; 685 686 cdsp_smp2p_in: slave-kernel { 687 qcom,entry-name = "slave-kernel"; 688 689 interrupt-controller; 690 #interrupt-cells = <2>; 691 }; 692 }; 693 694 smp2p-lpass { 695 compatible = "qcom,smp2p"; 696 qcom,smem = <443>, <429>; 697 698 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; 699 700 mboxes = <&apss_shared 10>; 701 702 qcom,local-pid = <0>; 703 qcom,remote-pid = <2>; 704 705 adsp_smp2p_out: master-kernel { 706 qcom,entry-name = "master-kernel"; 707 #qcom,smem-state-cells = <1>; 708 }; 709 710 adsp_smp2p_in: slave-kernel { 711 qcom,entry-name = "slave-kernel"; 712 713 interrupt-controller; 714 #interrupt-cells = <2>; 715 }; 716 }; 717 718 smp2p-mpss { 719 compatible = "qcom,smp2p"; 720 qcom,smem = <435>, <428>; 721 722 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>; 723 724 mboxes = <&apss_shared 14>; 725 726 qcom,local-pid = <0>; 727 qcom,remote-pid = <1>; 728 729 modem_smp2p_out: master-kernel { 730 qcom,entry-name = "master-kernel"; 731 #qcom,smem-state-cells = <1>; 732 }; 733 734 modem_smp2p_in: slave-kernel { 735 qcom,entry-name = "slave-kernel"; 736 737 interrupt-controller; 738 #interrupt-cells = <2>; 739 }; 740 741 modem_smp2p_ipa_out: ipa-ap-to-modem { 742 qcom,entry-name = "ipa"; 743 #qcom,smem-state-cells = <1>; 744 }; 745 746 modem_smp2p_ipa_in: ipa-modem-to-ap { 747 qcom,entry-name = "ipa"; 748 interrupt-controller; 749 #interrupt-cells = <2>; 750 }; 751 752 modem_smp2p_wlan_in: wlan-wpss-to-ap { 753 qcom,entry-name = "wlan"; 754 interrupt-controller; 755 #interrupt-cells = <2>; 756 }; 757 }; 758 759 smp2p-slpi { 760 compatible = "qcom,smp2p"; 761 qcom,smem = <481>, <430>; 762 763 interrupts = <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>; 764 765 mboxes = <&apss_shared 26>; 766 767 qcom,local-pid = <0>; 768 qcom,remote-pid = <3>; 769 770 slpi_smp2p_out: master-kernel { 771 qcom,entry-name = "master-kernel"; 772 #qcom,smem-state-cells = <1>; 773 }; 774 775 slpi_smp2p_in: slave-kernel { 776 qcom,entry-name = "slave-kernel"; 777 778 interrupt-controller; 779 #interrupt-cells = <2>; 780 }; 781 }; 782 783 soc: soc@0 { 784 compatible = "simple-bus"; 785 #address-cells = <2>; 786 #size-cells = <2>; 787 ranges = <0 0 0 0 0x10 0>; 788 dma-ranges = <0 0 0 0 0x10 0>; 789 790 gcc: clock-controller@100000 { 791 compatible = "qcom,gcc-sc8180x"; 792 reg = <0x0 0x00100000 0x0 0x1f0000>; 793 #clock-cells = <1>; 794 #reset-cells = <1>; 795 #power-domain-cells = <1>; 796 clocks = <&rpmhcc RPMH_CXO_CLK>, 797 <&rpmhcc RPMH_CXO_CLK_A>, 798 <&sleep_clk>; 799 clock-names = "bi_tcxo", 800 "bi_tcxo_ao", 801 "sleep_clk"; 802 power-domains = <&rpmhpd SC8180X_CX>; 803 }; 804 805 qupv3_id_0: geniqup@8c0000 { 806 compatible = "qcom,geni-se-qup"; 807 reg = <0 0x008c0000 0 0x6000>; 808 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 809 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 810 clock-names = "m-ahb", "s-ahb"; 811 #address-cells = <2>; 812 #size-cells = <2>; 813 ranges; 814 iommus = <&apps_smmu 0x4c3 0>; 815 status = "disabled"; 816 817 i2c0: i2c@880000 { 818 compatible = "qcom,geni-i2c"; 819 reg = <0 0x00880000 0 0x4000>; 820 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 821 clock-names = "se"; 822 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 823 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 824 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 825 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; 826 interconnect-names = "qup-core", "qup-config", "qup-memory"; 827 #address-cells = <1>; 828 #size-cells = <0>; 829 status = "disabled"; 830 }; 831 832 spi0: spi@880000 { 833 compatible = "qcom,geni-spi"; 834 reg = <0 0x00880000 0 0x4000>; 835 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 836 clock-names = "se"; 837 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 838 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 839 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; 840 interconnect-names = "qup-core", "qup-config"; 841 #address-cells = <1>; 842 #size-cells = <0>; 843 status = "disabled"; 844 }; 845 846 uart0: serial@880000 { 847 compatible = "qcom,geni-uart"; 848 reg = <0 0x00880000 0 0x4000>; 849 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 850 clock-names = "se"; 851 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 852 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 853 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; 854 interconnect-names = "qup-core", "qup-config"; 855 status = "disabled"; 856 }; 857 858 i2c1: i2c@884000 { 859 compatible = "qcom,geni-i2c"; 860 reg = <0 0x00884000 0 0x4000>; 861 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 862 clock-names = "se"; 863 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 864 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 865 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 866 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; 867 interconnect-names = "qup-core", "qup-config", "qup-memory"; 868 #address-cells = <1>; 869 #size-cells = <0>; 870 status = "disabled"; 871 }; 872 873 spi1: spi@884000 { 874 compatible = "qcom,geni-spi"; 875 reg = <0 0x00884000 0 0x4000>; 876 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 877 clock-names = "se"; 878 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 879 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 880 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; 881 interconnect-names = "qup-core", "qup-config"; 882 #address-cells = <1>; 883 #size-cells = <0>; 884 status = "disabled"; 885 }; 886 887 uart1: serial@884000 { 888 compatible = "qcom,geni-uart"; 889 reg = <0 0x00884000 0 0x4000>; 890 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 891 clock-names = "se"; 892 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 893 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 894 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; 895 interconnect-names = "qup-core", "qup-config"; 896 status = "disabled"; 897 }; 898 899 i2c2: i2c@888000 { 900 compatible = "qcom,geni-i2c"; 901 reg = <0 0x00888000 0 0x4000>; 902 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 903 clock-names = "se"; 904 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 905 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 906 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 907 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; 908 interconnect-names = "qup-core", "qup-config", "qup-memory"; 909 #address-cells = <1>; 910 #size-cells = <0>; 911 status = "disabled"; 912 }; 913 914 spi2: spi@888000 { 915 compatible = "qcom,geni-spi"; 916 reg = <0 0x00888000 0 0x4000>; 917 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 918 clock-names = "se"; 919 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 920 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 921 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; 922 interconnect-names = "qup-core", "qup-config"; 923 #address-cells = <1>; 924 #size-cells = <0>; 925 status = "disabled"; 926 }; 927 928 uart2: serial@888000 { 929 compatible = "qcom,geni-uart"; 930 reg = <0 0x00888000 0 0x4000>; 931 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 932 clock-names = "se"; 933 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 934 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 935 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; 936 interconnect-names = "qup-core", "qup-config"; 937 status = "disabled"; 938 }; 939 940 i2c3: i2c@88c000 { 941 compatible = "qcom,geni-i2c"; 942 reg = <0 0x0088c000 0 0x4000>; 943 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 944 clock-names = "se"; 945 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 946 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 947 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 948 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; 949 interconnect-names = "qup-core", "qup-config", "qup-memory"; 950 #address-cells = <1>; 951 #size-cells = <0>; 952 status = "disabled"; 953 }; 954 955 spi3: spi@88c000 { 956 compatible = "qcom,geni-spi"; 957 reg = <0 0x0088c000 0 0x4000>; 958 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 959 clock-names = "se"; 960 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 961 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 962 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; 963 interconnect-names = "qup-core", "qup-config"; 964 #address-cells = <1>; 965 #size-cells = <0>; 966 status = "disabled"; 967 }; 968 969 uart3: serial@88c000 { 970 compatible = "qcom,geni-uart"; 971 reg = <0 0x0088c000 0 0x4000>; 972 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 973 clock-names = "se"; 974 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 975 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 976 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; 977 interconnect-names = "qup-core", "qup-config"; 978 status = "disabled"; 979 }; 980 981 i2c4: i2c@890000 { 982 compatible = "qcom,geni-i2c"; 983 reg = <0 0x00890000 0 0x4000>; 984 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 985 clock-names = "se"; 986 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 987 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 988 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 989 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; 990 interconnect-names = "qup-core", "qup-config", "qup-memory"; 991 #address-cells = <1>; 992 #size-cells = <0>; 993 status = "disabled"; 994 }; 995 996 spi4: spi@890000 { 997 compatible = "qcom,geni-spi"; 998 reg = <0 0x00890000 0 0x4000>; 999 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1000 clock-names = "se"; 1001 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1002 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1003 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; 1004 interconnect-names = "qup-core", "qup-config"; 1005 #address-cells = <1>; 1006 #size-cells = <0>; 1007 status = "disabled"; 1008 }; 1009 1010 uart4: serial@890000 { 1011 compatible = "qcom,geni-uart"; 1012 reg = <0 0x00890000 0 0x4000>; 1013 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1014 clock-names = "se"; 1015 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1016 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1017 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; 1018 interconnect-names = "qup-core", "qup-config"; 1019 status = "disabled"; 1020 }; 1021 1022 i2c5: i2c@894000 { 1023 compatible = "qcom,geni-i2c"; 1024 reg = <0 0x00894000 0 0x4000>; 1025 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1026 clock-names = "se"; 1027 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1028 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1029 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 1030 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; 1031 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1032 #address-cells = <1>; 1033 #size-cells = <0>; 1034 status = "disabled"; 1035 }; 1036 1037 spi5: spi@894000 { 1038 compatible = "qcom,geni-spi"; 1039 reg = <0 0x00894000 0 0x4000>; 1040 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1041 clock-names = "se"; 1042 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1043 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1044 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; 1045 interconnect-names = "qup-core", "qup-config"; 1046 #address-cells = <1>; 1047 #size-cells = <0>; 1048 status = "disabled"; 1049 }; 1050 1051 uart5: serial@894000 { 1052 compatible = "qcom,geni-uart"; 1053 reg = <0 0x00894000 0 0x4000>; 1054 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1055 clock-names = "se"; 1056 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1057 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1058 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; 1059 interconnect-names = "qup-core", "qup-config"; 1060 status = "disabled"; 1061 }; 1062 1063 i2c6: i2c@898000 { 1064 compatible = "qcom,geni-i2c"; 1065 reg = <0 0x00898000 0 0x4000>; 1066 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1067 clock-names = "se"; 1068 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1069 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1070 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 1071 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; 1072 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1073 #address-cells = <1>; 1074 #size-cells = <0>; 1075 status = "disabled"; 1076 }; 1077 1078 spi6: spi@898000 { 1079 compatible = "qcom,geni-spi"; 1080 reg = <0 0x00898000 0 0x4000>; 1081 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1082 clock-names = "se"; 1083 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1084 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1085 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; 1086 interconnect-names = "qup-core", "qup-config"; 1087 #address-cells = <1>; 1088 #size-cells = <0>; 1089 status = "disabled"; 1090 }; 1091 1092 uart6: serial@898000 { 1093 compatible = "qcom,geni-uart"; 1094 reg = <0 0x00898000 0 0x4000>; 1095 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1096 clock-names = "se"; 1097 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1098 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1099 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; 1100 interconnect-names = "qup-core", "qup-config"; 1101 status = "disabled"; 1102 }; 1103 1104 i2c7: i2c@89c000 { 1105 compatible = "qcom,geni-i2c"; 1106 reg = <0 0x0089c000 0 0x4000>; 1107 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1108 clock-names = "se"; 1109 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1110 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1111 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 1112 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; 1113 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1114 #address-cells = <1>; 1115 #size-cells = <0>; 1116 status = "disabled"; 1117 }; 1118 1119 spi7: spi@89c000 { 1120 compatible = "qcom,geni-spi"; 1121 reg = <0 0x0089c000 0 0x4000>; 1122 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1123 clock-names = "se"; 1124 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1125 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1126 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; 1127 interconnect-names = "qup-core", "qup-config"; 1128 #address-cells = <1>; 1129 #size-cells = <0>; 1130 status = "disabled"; 1131 }; 1132 1133 uart7: serial@89c000 { 1134 compatible = "qcom,geni-uart"; 1135 reg = <0 0x0089c000 0 0x4000>; 1136 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1137 clock-names = "se"; 1138 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1139 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1140 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; 1141 interconnect-names = "qup-core", "qup-config"; 1142 status = "disabled"; 1143 }; 1144 }; 1145 1146 qupv3_id_1: geniqup@ac0000 { 1147 compatible = "qcom,geni-se-qup"; 1148 reg = <0x0 0x00ac0000 0x0 0x6000>; 1149 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1150 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1151 clock-names = "m-ahb", "s-ahb"; 1152 #address-cells = <2>; 1153 #size-cells = <2>; 1154 ranges; 1155 iommus = <&apps_smmu 0x603 0>; 1156 status = "disabled"; 1157 1158 i2c8: i2c@a80000 { 1159 compatible = "qcom,geni-i2c"; 1160 reg = <0 0x00a80000 0 0x4000>; 1161 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1162 clock-names = "se"; 1163 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1164 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1165 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 1166 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>; 1167 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1168 #address-cells = <1>; 1169 #size-cells = <0>; 1170 status = "disabled"; 1171 }; 1172 1173 spi8: spi@a80000 { 1174 compatible = "qcom,geni-spi"; 1175 reg = <0 0x00a80000 0 0x4000>; 1176 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1177 clock-names = "se"; 1178 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1179 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1180 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; 1181 interconnect-names = "qup-core", "qup-config"; 1182 #address-cells = <1>; 1183 #size-cells = <0>; 1184 status = "disabled"; 1185 }; 1186 1187 uart8: serial@a80000 { 1188 compatible = "qcom,geni-uart"; 1189 reg = <0 0x00a80000 0 0x4000>; 1190 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1191 clock-names = "se"; 1192 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1193 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1194 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; 1195 interconnect-names = "qup-core", "qup-config"; 1196 status = "disabled"; 1197 }; 1198 1199 i2c9: i2c@a84000 { 1200 compatible = "qcom,geni-i2c"; 1201 reg = <0 0x00a84000 0 0x4000>; 1202 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1203 clock-names = "se"; 1204 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1205 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1206 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 1207 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>; 1208 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1209 #address-cells = <1>; 1210 #size-cells = <0>; 1211 status = "disabled"; 1212 }; 1213 1214 spi9: spi@a84000 { 1215 compatible = "qcom,geni-spi"; 1216 reg = <0 0x00a84000 0 0x4000>; 1217 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1218 clock-names = "se"; 1219 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1220 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1221 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; 1222 interconnect-names = "qup-core", "qup-config"; 1223 #address-cells = <1>; 1224 #size-cells = <0>; 1225 status = "disabled"; 1226 }; 1227 1228 uart9: serial@a84000 { 1229 compatible = "qcom,geni-debug-uart"; 1230 reg = <0 0x00a84000 0 0x4000>; 1231 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1232 clock-names = "se"; 1233 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1234 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1235 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; 1236 interconnect-names = "qup-core", "qup-config"; 1237 status = "disabled"; 1238 }; 1239 1240 i2c10: i2c@a88000 { 1241 compatible = "qcom,geni-i2c"; 1242 reg = <0 0x00a88000 0 0x4000>; 1243 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1244 clock-names = "se"; 1245 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1246 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1247 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 1248 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>; 1249 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1250 #address-cells = <1>; 1251 #size-cells = <0>; 1252 status = "disabled"; 1253 }; 1254 1255 spi10: spi@a88000 { 1256 compatible = "qcom,geni-spi"; 1257 reg = <0 0x00a88000 0 0x4000>; 1258 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1259 clock-names = "se"; 1260 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1261 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1262 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; 1263 interconnect-names = "qup-core", "qup-config"; 1264 #address-cells = <1>; 1265 #size-cells = <0>; 1266 status = "disabled"; 1267 }; 1268 1269 uart10: serial@a88000 { 1270 compatible = "qcom,geni-uart"; 1271 reg = <0 0x00a88000 0 0x4000>; 1272 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1273 clock-names = "se"; 1274 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1275 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1276 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; 1277 interconnect-names = "qup-core", "qup-config"; 1278 status = "disabled"; 1279 }; 1280 1281 i2c11: i2c@a8c000 { 1282 compatible = "qcom,geni-i2c"; 1283 reg = <0 0x00a8c000 0 0x4000>; 1284 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1285 clock-names = "se"; 1286 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1287 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1288 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 1289 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>; 1290 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1291 #address-cells = <1>; 1292 #size-cells = <0>; 1293 status = "disabled"; 1294 }; 1295 1296 spi11: spi@a8c000 { 1297 compatible = "qcom,geni-spi"; 1298 reg = <0 0x00a8c000 0 0x4000>; 1299 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1300 clock-names = "se"; 1301 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1302 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1303 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; 1304 interconnect-names = "qup-core", "qup-config"; 1305 #address-cells = <1>; 1306 #size-cells = <0>; 1307 status = "disabled"; 1308 }; 1309 1310 uart11: serial@a8c000 { 1311 compatible = "qcom,geni-uart"; 1312 reg = <0 0x00a8c000 0 0x4000>; 1313 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1314 clock-names = "se"; 1315 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1316 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1317 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; 1318 interconnect-names = "qup-core", "qup-config"; 1319 status = "disabled"; 1320 }; 1321 1322 i2c12: i2c@a90000 { 1323 compatible = "qcom,geni-i2c"; 1324 reg = <0 0x00a90000 0 0x4000>; 1325 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1326 clock-names = "se"; 1327 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1328 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1329 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 1330 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>; 1331 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1332 #address-cells = <1>; 1333 #size-cells = <0>; 1334 status = "disabled"; 1335 }; 1336 1337 spi12: spi@a90000 { 1338 compatible = "qcom,geni-spi"; 1339 reg = <0 0x00a90000 0 0x4000>; 1340 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1341 clock-names = "se"; 1342 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1343 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1344 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; 1345 interconnect-names = "qup-core", "qup-config"; 1346 #address-cells = <1>; 1347 #size-cells = <0>; 1348 status = "disabled"; 1349 }; 1350 1351 uart12: serial@a90000 { 1352 compatible = "qcom,geni-uart"; 1353 reg = <0 0x00a90000 0 0x4000>; 1354 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1355 clock-names = "se"; 1356 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1357 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1358 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; 1359 interconnect-names = "qup-core", "qup-config"; 1360 status = "disabled"; 1361 }; 1362 1363 i2c16: i2c@a94000 { 1364 compatible = "qcom,geni-i2c"; 1365 reg = <0 0x00a94000 0 0x4000>; 1366 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1367 clock-names = "se"; 1368 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1369 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1370 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 1371 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>; 1372 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1373 #address-cells = <1>; 1374 #size-cells = <0>; 1375 status = "disabled"; 1376 }; 1377 1378 spi16: spi@a94000 { 1379 compatible = "qcom,geni-spi"; 1380 reg = <0 0x00a94000 0 0x4000>; 1381 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1382 clock-names = "se"; 1383 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1384 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1385 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; 1386 interconnect-names = "qup-core", "qup-config"; 1387 #address-cells = <1>; 1388 #size-cells = <0>; 1389 status = "disabled"; 1390 }; 1391 1392 uart16: serial@a94000 { 1393 compatible = "qcom,geni-uart"; 1394 reg = <0 0x00a94000 0 0x4000>; 1395 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1396 clock-names = "se"; 1397 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1398 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1399 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; 1400 interconnect-names = "qup-core", "qup-config"; 1401 status = "disabled"; 1402 }; 1403 }; 1404 1405 qupv3_id_2: geniqup@cc0000 { 1406 compatible = "qcom,geni-se-qup"; 1407 reg = <0x0 0x00cc0000 0x0 0x6000>; 1408 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 1409 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 1410 clock-names = "m-ahb", "s-ahb"; 1411 #address-cells = <2>; 1412 #size-cells = <2>; 1413 ranges; 1414 iommus = <&apps_smmu 0x7a3 0>; 1415 status = "disabled"; 1416 1417 i2c17: i2c@c80000 { 1418 compatible = "qcom,geni-i2c"; 1419 reg = <0 0x00c80000 0 0x4000>; 1420 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 1421 clock-names = "se"; 1422 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 1423 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1424 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>, 1425 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>; 1426 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1427 #address-cells = <1>; 1428 #size-cells = <0>; 1429 status = "disabled"; 1430 }; 1431 1432 spi17: spi@c80000 { 1433 compatible = "qcom,geni-spi"; 1434 reg = <0 0x00c80000 0 0x4000>; 1435 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 1436 clock-names = "se"; 1437 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 1438 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1439 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>; 1440 interconnect-names = "qup-core", "qup-config"; 1441 #address-cells = <1>; 1442 #size-cells = <0>; 1443 status = "disabled"; 1444 }; 1445 1446 uart17: serial@c80000 { 1447 compatible = "qcom,geni-uart"; 1448 reg = <0 0x00c80000 0 0x4000>; 1449 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 1450 clock-names = "se"; 1451 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 1452 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1453 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>; 1454 interconnect-names = "qup-core", "qup-config"; 1455 status = "disabled"; 1456 }; 1457 1458 i2c18: i2c@c84000 { 1459 compatible = "qcom,geni-i2c"; 1460 reg = <0 0x00c84000 0 0x4000>; 1461 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 1462 clock-names = "se"; 1463 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 1464 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1465 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>, 1466 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>; 1467 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1468 #address-cells = <1>; 1469 #size-cells = <0>; 1470 status = "disabled"; 1471 }; 1472 1473 spi18: spi@c84000 { 1474 compatible = "qcom,geni-spi"; 1475 reg = <0 0x00c84000 0 0x4000>; 1476 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 1477 clock-names = "se"; 1478 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 1479 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1480 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>; 1481 interconnect-names = "qup-core", "qup-config"; 1482 #address-cells = <1>; 1483 #size-cells = <0>; 1484 status = "disabled"; 1485 }; 1486 1487 uart18: serial@c84000 { 1488 compatible = "qcom,geni-uart"; 1489 reg = <0 0x00c84000 0 0x4000>; 1490 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 1491 clock-names = "se"; 1492 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 1493 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1494 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>; 1495 interconnect-names = "qup-core", "qup-config"; 1496 status = "disabled"; 1497 }; 1498 1499 i2c19: i2c@c88000 { 1500 compatible = "qcom,geni-i2c"; 1501 reg = <0 0x00c88000 0 0x4000>; 1502 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1503 clock-names = "se"; 1504 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 1505 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1506 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>, 1507 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>; 1508 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1509 #address-cells = <1>; 1510 #size-cells = <0>; 1511 status = "disabled"; 1512 }; 1513 1514 spi19: spi@c88000 { 1515 compatible = "qcom,geni-spi"; 1516 reg = <0 0x00c88000 0 0x4000>; 1517 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1518 clock-names = "se"; 1519 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 1520 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1521 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>; 1522 interconnect-names = "qup-core", "qup-config"; 1523 #address-cells = <1>; 1524 #size-cells = <0>; 1525 status = "disabled"; 1526 }; 1527 1528 uart19: serial@c88000 { 1529 compatible = "qcom,geni-uart"; 1530 reg = <0 0x00c88000 0 0x4000>; 1531 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1532 clock-names = "se"; 1533 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 1534 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1535 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>; 1536 interconnect-names = "qup-core", "qup-config"; 1537 status = "disabled"; 1538 }; 1539 1540 i2c13: i2c@c8c000 { 1541 compatible = "qcom,geni-i2c"; 1542 reg = <0 0x00c8c000 0 0x4000>; 1543 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1544 clock-names = "se"; 1545 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1546 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1547 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>, 1548 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>; 1549 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1550 #address-cells = <1>; 1551 #size-cells = <0>; 1552 status = "disabled"; 1553 }; 1554 1555 spi13: spi@c8c000 { 1556 compatible = "qcom,geni-spi"; 1557 reg = <0 0x00c8c000 0 0x4000>; 1558 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1559 clock-names = "se"; 1560 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1561 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1562 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>; 1563 interconnect-names = "qup-core", "qup-config"; 1564 #address-cells = <1>; 1565 #size-cells = <0>; 1566 status = "disabled"; 1567 }; 1568 1569 uart13: serial@c8c000 { 1570 compatible = "qcom,geni-uart"; 1571 reg = <0 0x00c8c000 0 0x4000>; 1572 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1573 clock-names = "se"; 1574 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1575 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1576 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>; 1577 interconnect-names = "qup-core", "qup-config"; 1578 status = "disabled"; 1579 }; 1580 1581 i2c14: i2c@c90000 { 1582 compatible = "qcom,geni-i2c"; 1583 reg = <0 0x00c90000 0 0x4000>; 1584 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1585 clock-names = "se"; 1586 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1587 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1588 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>, 1589 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>; 1590 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1591 #address-cells = <1>; 1592 #size-cells = <0>; 1593 status = "disabled"; 1594 }; 1595 1596 spi14: spi@c90000 { 1597 compatible = "qcom,geni-spi"; 1598 reg = <0 0x00c90000 0 0x4000>; 1599 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1600 clock-names = "se"; 1601 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1602 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1603 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>; 1604 interconnect-names = "qup-core", "qup-config"; 1605 #address-cells = <1>; 1606 #size-cells = <0>; 1607 status = "disabled"; 1608 }; 1609 1610 uart14: serial@c90000 { 1611 compatible = "qcom,geni-uart"; 1612 reg = <0 0x00c90000 0 0x4000>; 1613 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1614 clock-names = "se"; 1615 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1616 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1617 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>; 1618 interconnect-names = "qup-core", "qup-config"; 1619 status = "disabled"; 1620 }; 1621 1622 i2c15: i2c@c94000 { 1623 compatible = "qcom,geni-i2c"; 1624 reg = <0 0x00c94000 0 0x4000>; 1625 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1626 clock-names = "se"; 1627 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1628 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1629 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>, 1630 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>; 1631 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1632 #address-cells = <1>; 1633 #size-cells = <0>; 1634 status = "disabled"; 1635 }; 1636 1637 spi15: spi@c94000 { 1638 compatible = "qcom,geni-spi"; 1639 reg = <0 0x00c94000 0 0x4000>; 1640 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1641 clock-names = "se"; 1642 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1643 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1644 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>; 1645 interconnect-names = "qup-core", "qup-config"; 1646 #address-cells = <1>; 1647 #size-cells = <0>; 1648 status = "disabled"; 1649 }; 1650 1651 uart15: serial@c94000 { 1652 compatible = "qcom,geni-uart"; 1653 reg = <0 0x00c94000 0 0x4000>; 1654 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1655 clock-names = "se"; 1656 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1657 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1658 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>; 1659 interconnect-names = "qup-core", "qup-config"; 1660 status = "disabled"; 1661 }; 1662 }; 1663 1664 config_noc: interconnect@1500000 { 1665 compatible = "qcom,sc8180x-config-noc"; 1666 reg = <0 0x01500000 0 0x7400>; 1667 #interconnect-cells = <2>; 1668 qcom,bcm-voters = <&apps_bcm_voter>; 1669 }; 1670 1671 system_noc: interconnect@1620000 { 1672 compatible = "qcom,sc8180x-system-noc"; 1673 reg = <0 0x01620000 0 0x19400>; 1674 #interconnect-cells = <2>; 1675 qcom,bcm-voters = <&apps_bcm_voter>; 1676 }; 1677 1678 aggre1_noc: interconnect@16e0000 { 1679 compatible = "qcom,sc8180x-aggre1-noc"; 1680 reg = <0 0x016e0000 0 0xd080>; 1681 #interconnect-cells = <2>; 1682 qcom,bcm-voters = <&apps_bcm_voter>; 1683 }; 1684 1685 aggre2_noc: interconnect@1700000 { 1686 compatible = "qcom,sc8180x-aggre2-noc"; 1687 reg = <0 0x01700000 0 0x20000>; 1688 #interconnect-cells = <2>; 1689 qcom,bcm-voters = <&apps_bcm_voter>; 1690 }; 1691 1692 compute_noc: interconnect@1720000 { 1693 compatible = "qcom,sc8180x-compute-noc"; 1694 reg = <0 0x01720000 0 0x7000>; 1695 #interconnect-cells = <2>; 1696 qcom,bcm-voters = <&apps_bcm_voter>; 1697 }; 1698 1699 mmss_noc: interconnect@1740000 { 1700 compatible = "qcom,sc8180x-mmss-noc"; 1701 reg = <0 0x01740000 0 0x1c100>; 1702 #interconnect-cells = <2>; 1703 qcom,bcm-voters = <&apps_bcm_voter>; 1704 }; 1705 1706 pcie0: pcie@1c00000 { 1707 compatible = "qcom,pcie-sc8180x"; 1708 reg = <0 0x01c00000 0 0x3000>, 1709 <0 0x60000000 0 0xf1d>, 1710 <0 0x60000f20 0 0xa8>, 1711 <0 0x60001000 0 0x1000>, 1712 <0 0x60100000 0 0x100000>; 1713 reg-names = "parf", 1714 "dbi", 1715 "elbi", 1716 "atu", 1717 "config"; 1718 device_type = "pci"; 1719 linux,pci-domain = <0>; 1720 bus-range = <0x00 0xff>; 1721 num-lanes = <2>; 1722 1723 #address-cells = <3>; 1724 #size-cells = <2>; 1725 1726 ranges = <0x01000000 0x0 0x60200000 0x0 0x60200000 0x0 0x100000>, 1727 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>; 1728 1729 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 1730 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 1731 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 1732 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 1733 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 1734 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 1735 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 1736 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 1737 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 1738 interrupt-names = "msi0", 1739 "msi1", 1740 "msi2", 1741 "msi3", 1742 "msi4", 1743 "msi5", 1744 "msi6", 1745 "msi7", 1746 "global"; 1747 #interrupt-cells = <1>; 1748 interrupt-map-mask = <0 0 0 0x7>; 1749 interrupt-map = <0 0 0 1 &intc GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1750 <0 0 0 2 &intc GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1751 <0 0 0 3 &intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1752 <0 0 0 4 &intc GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1753 1754 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, 1755 <&gcc GCC_PCIE_0_AUX_CLK>, 1756 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1757 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 1758 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 1759 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>; 1760 clock-names = "pipe", 1761 "aux", 1762 "cfg", 1763 "bus_master", 1764 "bus_slave", 1765 "slave_q2a"; 1766 1767 assigned-clocks = <&gcc GCC_PCIE_0_AUX_CLK>; 1768 assigned-clock-rates = <19200000>; 1769 1770 iommu-map = <0x0 &apps_smmu 0x1d80 0x1>, 1771 <0x100 &apps_smmu 0x1d81 0x1>; 1772 1773 resets = <&gcc GCC_PCIE_0_BCR>; 1774 reset-names = "pci"; 1775 1776 power-domains = <&gcc PCIE_0_GDSC>; 1777 1778 interconnects = <&aggre2_noc MASTER_PCIE 0 &mc_virt SLAVE_EBI_CH0 0>, 1779 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_PCIE_0 0>; 1780 interconnect-names = "pcie-mem", "cpu-pcie"; 1781 1782 phys = <&pcie0_phy>; 1783 phy-names = "pciephy"; 1784 dma-coherent; 1785 1786 status = "disabled"; 1787 1788 pcie@0 { 1789 device_type = "pci"; 1790 reg = <0x0 0x0 0x0 0x0 0x0>; 1791 bus-range = <0x01 0xff>; 1792 1793 #address-cells = <3>; 1794 #size-cells = <2>; 1795 ranges; 1796 }; 1797 }; 1798 1799 pcie0_phy: phy@1c06000 { 1800 compatible = "qcom,sc8180x-qmp-pcie-phy"; 1801 reg = <0 0x01c06000 0 0x1000>; 1802 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 1803 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1804 <&gcc GCC_PCIE_0_CLKREF_CLK>, 1805 <&gcc GCC_PCIE0_PHY_REFGEN_CLK>, 1806 <&gcc GCC_PCIE_0_PIPE_CLK>; 1807 clock-names = "aux", 1808 "cfg_ahb", 1809 "ref", 1810 "refgen", 1811 "pipe"; 1812 #clock-cells = <0>; 1813 clock-output-names = "pcie_0_pipe_clk"; 1814 #phy-cells = <0>; 1815 1816 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 1817 reset-names = "phy"; 1818 1819 assigned-clocks = <&gcc GCC_PCIE0_PHY_REFGEN_CLK>; 1820 assigned-clock-rates = <100000000>; 1821 1822 status = "disabled"; 1823 }; 1824 1825 pcie3: pcie@1c08000 { 1826 compatible = "qcom,pcie-sc8180x"; 1827 reg = <0 0x01c08000 0 0x3000>, 1828 <0 0x40000000 0 0xf1d>, 1829 <0 0x40000f20 0 0xa8>, 1830 <0 0x40001000 0 0x1000>, 1831 <0 0x40100000 0 0x100000>; 1832 reg-names = "parf", 1833 "dbi", 1834 "elbi", 1835 "atu", 1836 "config"; 1837 device_type = "pci"; 1838 linux,pci-domain = <3>; 1839 bus-range = <0x00 0xff>; 1840 num-lanes = <2>; 1841 1842 #address-cells = <3>; 1843 #size-cells = <2>; 1844 1845 ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>, 1846 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 1847 1848 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 1849 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 1850 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 1851 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 1852 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 1853 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 1854 <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, 1855 <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>, 1856 <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>; 1857 interrupt-names = "msi0", 1858 "msi1", 1859 "msi2", 1860 "msi3", 1861 "msi4", 1862 "msi5", 1863 "msi6", 1864 "msi7", 1865 "global"; 1866 #interrupt-cells = <1>; 1867 interrupt-map-mask = <0 0 0 0x7>; 1868 interrupt-map = <0 0 0 1 &intc GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1869 <0 0 0 2 &intc GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1870 <0 0 0 3 &intc GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1871 <0 0 0 4 &intc GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1872 1873 clocks = <&gcc GCC_PCIE_3_PIPE_CLK>, 1874 <&gcc GCC_PCIE_3_AUX_CLK>, 1875 <&gcc GCC_PCIE_3_CFG_AHB_CLK>, 1876 <&gcc GCC_PCIE_3_MSTR_AXI_CLK>, 1877 <&gcc GCC_PCIE_3_SLV_AXI_CLK>, 1878 <&gcc GCC_PCIE_3_SLV_Q2A_AXI_CLK>; 1879 clock-names = "pipe", 1880 "aux", 1881 "cfg", 1882 "bus_master", 1883 "bus_slave", 1884 "slave_q2a"; 1885 1886 assigned-clocks = <&gcc GCC_PCIE_3_AUX_CLK>; 1887 assigned-clock-rates = <19200000>; 1888 1889 iommu-map = <0x0 &apps_smmu 0x1e00 0x1>, 1890 <0x100 &apps_smmu 0x1e01 0x1>; 1891 1892 resets = <&gcc GCC_PCIE_3_BCR>; 1893 reset-names = "pci"; 1894 1895 power-domains = <&gcc PCIE_3_GDSC>; 1896 1897 interconnects = <&aggre2_noc MASTER_PCIE_3 0 &mc_virt SLAVE_EBI_CH0 0>, 1898 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_PCIE_3 0>; 1899 interconnect-names = "pcie-mem", "cpu-pcie"; 1900 1901 phys = <&pcie3_phy>; 1902 phy-names = "pciephy"; 1903 dma-coherent; 1904 1905 status = "disabled"; 1906 1907 pcie@0 { 1908 device_type = "pci"; 1909 reg = <0x0 0x0 0x0 0x0 0x0>; 1910 bus-range = <0x01 0xff>; 1911 1912 #address-cells = <3>; 1913 #size-cells = <2>; 1914 ranges; 1915 }; 1916 }; 1917 1918 pcie3_phy: phy@1c0c000 { 1919 compatible = "qcom,sc8180x-qmp-pcie-phy"; 1920 reg = <0 0x01c0c000 0 0x1000>; 1921 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 1922 <&gcc GCC_PCIE_3_CFG_AHB_CLK>, 1923 <&gcc GCC_PCIE_3_CLKREF_CLK>, 1924 <&gcc GCC_PCIE3_PHY_REFGEN_CLK>, 1925 <&gcc GCC_PCIE_3_PIPE_CLK>; 1926 clock-names = "aux", 1927 "cfg_ahb", 1928 "ref", 1929 "refgen", 1930 "pipe"; 1931 #clock-cells = <0>; 1932 clock-output-names = "pcie_3_pipe_clk"; 1933 1934 #phy-cells = <0>; 1935 1936 resets = <&gcc GCC_PCIE_3_PHY_BCR>; 1937 reset-names = "phy"; 1938 1939 assigned-clocks = <&gcc GCC_PCIE3_PHY_REFGEN_CLK>; 1940 assigned-clock-rates = <100000000>; 1941 1942 status = "disabled"; 1943 }; 1944 1945 pcie1: pcie@1c10000 { 1946 compatible = "qcom,pcie-sc8180x"; 1947 reg = <0 0x01c10000 0 0x3000>, 1948 <0 0x68000000 0 0xf1d>, 1949 <0 0x68000f20 0 0xa8>, 1950 <0 0x68001000 0 0x1000>, 1951 <0 0x68100000 0 0x100000>; 1952 reg-names = "parf", 1953 "dbi", 1954 "elbi", 1955 "atu", 1956 "config"; 1957 device_type = "pci"; 1958 linux,pci-domain = <1>; 1959 bus-range = <0x00 0xff>; 1960 num-lanes = <2>; 1961 1962 #address-cells = <3>; 1963 #size-cells = <2>; 1964 1965 ranges = <0x01000000 0x0 0x68200000 0x0 0x68200000 0x0 0x100000>, 1966 <0x02000000 0x0 0x68300000 0x0 0x68300000 0x0 0x3d00000>; 1967 1968 interrupts = <GIC_SPI 756 IRQ_TYPE_LEVEL_HIGH>, 1969 <GIC_SPI 755 IRQ_TYPE_LEVEL_HIGH>, 1970 <GIC_SPI 754 IRQ_TYPE_LEVEL_HIGH>, 1971 <GIC_SPI 753 IRQ_TYPE_LEVEL_HIGH>, 1972 <GIC_SPI 752 IRQ_TYPE_LEVEL_HIGH>, 1973 <GIC_SPI 751 IRQ_TYPE_LEVEL_HIGH>, 1974 <GIC_SPI 750 IRQ_TYPE_LEVEL_HIGH>, 1975 <GIC_SPI 749 IRQ_TYPE_LEVEL_HIGH>, 1976 <GIC_SPI 758 IRQ_TYPE_LEVEL_HIGH>; 1977 interrupt-names = "msi0", 1978 "msi1", 1979 "msi2", 1980 "msi3", 1981 "msi4", 1982 "msi5", 1983 "msi6", 1984 "msi7", 1985 "global"; 1986 #interrupt-cells = <1>; 1987 interrupt-map-mask = <0 0 0 0x7>; 1988 interrupt-map = <0 0 0 1 &intc GIC_SPI 747 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1989 <0 0 0 2 &intc GIC_SPI 746 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1990 <0 0 0 3 &intc GIC_SPI 745 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1991 <0 0 0 4 &intc GIC_SPI 744 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1992 1993 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, 1994 <&gcc GCC_PCIE_1_AUX_CLK>, 1995 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1996 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 1997 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 1998 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>; 1999 clock-names = "pipe", 2000 "aux", 2001 "cfg", 2002 "bus_master", 2003 "bus_slave", 2004 "slave_q2a"; 2005 2006 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; 2007 assigned-clock-rates = <19200000>; 2008 2009 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, 2010 <0x100 &apps_smmu 0x1c81 0x1>; 2011 2012 resets = <&gcc GCC_PCIE_1_BCR>; 2013 reset-names = "pci"; 2014 2015 power-domains = <&gcc PCIE_1_GDSC>; 2016 2017 interconnects = <&aggre2_noc MASTER_PCIE_1 0 &mc_virt SLAVE_EBI_CH0 0>, 2018 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_PCIE_1 0>; 2019 interconnect-names = "pcie-mem", "cpu-pcie"; 2020 2021 phys = <&pcie1_phy>; 2022 phy-names = "pciephy"; 2023 dma-coherent; 2024 2025 status = "disabled"; 2026 2027 pcie@0 { 2028 device_type = "pci"; 2029 reg = <0x0 0x0 0x0 0x0 0x0>; 2030 bus-range = <0x01 0xff>; 2031 2032 #address-cells = <3>; 2033 #size-cells = <2>; 2034 ranges; 2035 }; 2036 }; 2037 2038 pcie1_phy: phy@1c16000 { 2039 compatible = "qcom,sc8180x-qmp-pcie-phy"; 2040 reg = <0 0x01c16000 0 0x1000>; 2041 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 2042 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 2043 <&gcc GCC_PCIE_1_CLKREF_CLK>, 2044 <&gcc GCC_PCIE1_PHY_REFGEN_CLK>, 2045 <&gcc GCC_PCIE_1_PIPE_CLK>; 2046 clock-names = "aux", 2047 "cfg_ahb", 2048 "ref", 2049 "refgen", 2050 "pipe"; 2051 #clock-cells = <0>; 2052 clock-output-names = "pcie_1_pipe_clk"; 2053 2054 #phy-cells = <0>; 2055 2056 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 2057 reset-names = "phy"; 2058 2059 assigned-clocks = <&gcc GCC_PCIE1_PHY_REFGEN_CLK>; 2060 assigned-clock-rates = <100000000>; 2061 2062 status = "disabled"; 2063 }; 2064 2065 pcie2: pcie@1c18000 { 2066 compatible = "qcom,pcie-sc8180x"; 2067 reg = <0 0x01c18000 0 0x3000>, 2068 <0 0x70000000 0 0xf1d>, 2069 <0 0x70000f20 0 0xa8>, 2070 <0 0x70001000 0 0x1000>, 2071 <0 0x70100000 0 0x100000>; 2072 reg-names = "parf", 2073 "dbi", 2074 "elbi", 2075 "atu", 2076 "config"; 2077 device_type = "pci"; 2078 linux,pci-domain = <2>; 2079 bus-range = <0x00 0xff>; 2080 num-lanes = <4>; 2081 2082 #address-cells = <3>; 2083 #size-cells = <2>; 2084 2085 ranges = <0x01000000 0x0 0x70200000 0x0 0x70200000 0x0 0x100000>, 2086 <0x02000000 0x0 0x70300000 0x0 0x70300000 0x0 0x3d00000>; 2087 2088 interrupts = <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>, 2089 <GIC_SPI 671 IRQ_TYPE_LEVEL_HIGH>, 2090 <GIC_SPI 670 IRQ_TYPE_LEVEL_HIGH>, 2091 <GIC_SPI 669 IRQ_TYPE_LEVEL_HIGH>, 2092 <GIC_SPI 668 IRQ_TYPE_LEVEL_HIGH>, 2093 <GIC_SPI 667 IRQ_TYPE_LEVEL_HIGH>, 2094 <GIC_SPI 666 IRQ_TYPE_LEVEL_HIGH>, 2095 <GIC_SPI 665 IRQ_TYPE_LEVEL_HIGH>, 2096 <GIC_SPI 744 IRQ_TYPE_LEVEL_HIGH>; 2097 interrupt-names = "msi0", 2098 "msi1", 2099 "msi2", 2100 "msi3", 2101 "msi4", 2102 "msi5", 2103 "msi6", 2104 "msi7", 2105 "global"; 2106 #interrupt-cells = <1>; 2107 interrupt-map-mask = <0 0 0 0x7>; 2108 interrupt-map = <0 0 0 1 &intc GIC_SPI 663 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 2109 <0 0 0 2 &intc GIC_SPI 662 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 2110 <0 0 0 3 &intc GIC_SPI 661 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 2111 <0 0 0 4 &intc GIC_SPI 660 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 2112 2113 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>, 2114 <&gcc GCC_PCIE_2_AUX_CLK>, 2115 <&gcc GCC_PCIE_2_CFG_AHB_CLK>, 2116 <&gcc GCC_PCIE_2_MSTR_AXI_CLK>, 2117 <&gcc GCC_PCIE_2_SLV_AXI_CLK>, 2118 <&gcc GCC_PCIE_2_SLV_Q2A_AXI_CLK>; 2119 clock-names = "pipe", 2120 "aux", 2121 "cfg", 2122 "bus_master", 2123 "bus_slave", 2124 "slave_q2a"; 2125 2126 assigned-clocks = <&gcc GCC_PCIE_2_AUX_CLK>; 2127 assigned-clock-rates = <19200000>; 2128 2129 iommu-map = <0x0 &apps_smmu 0x1d00 0x1>, 2130 <0x100 &apps_smmu 0x1d01 0x1>; 2131 2132 resets = <&gcc GCC_PCIE_2_BCR>; 2133 reset-names = "pci"; 2134 2135 power-domains = <&gcc PCIE_2_GDSC>; 2136 2137 interconnects = <&aggre2_noc MASTER_PCIE_2 0 &mc_virt SLAVE_EBI_CH0 0>, 2138 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_PCIE_2 0>; 2139 interconnect-names = "pcie-mem", "cpu-pcie"; 2140 2141 phys = <&pcie2_phy>; 2142 phy-names = "pciephy"; 2143 dma-coherent; 2144 2145 status = "disabled"; 2146 2147 pcie@0 { 2148 device_type = "pci"; 2149 reg = <0x0 0x0 0x0 0x0 0x0>; 2150 bus-range = <0x01 0xff>; 2151 2152 #address-cells = <3>; 2153 #size-cells = <2>; 2154 ranges; 2155 }; 2156 }; 2157 2158 pcie2_phy: phy@1c1c000 { 2159 compatible = "qcom,sc8180x-qmp-pcie-phy"; 2160 reg = <0 0x01c1c000 0 0x1000>; 2161 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 2162 <&gcc GCC_PCIE_2_CFG_AHB_CLK>, 2163 <&gcc GCC_PCIE_2_CLKREF_CLK>, 2164 <&gcc GCC_PCIE2_PHY_REFGEN_CLK>, 2165 <&gcc GCC_PCIE_2_PIPE_CLK>; 2166 clock-names = "aux", 2167 "cfg_ahb", 2168 "ref", 2169 "refgen", 2170 "pipe"; 2171 #clock-cells = <0>; 2172 clock-output-names = "pcie_2_pipe_clk"; 2173 2174 #phy-cells = <0>; 2175 2176 resets = <&gcc GCC_PCIE_2_PHY_BCR>; 2177 reset-names = "phy"; 2178 2179 assigned-clocks = <&gcc GCC_PCIE2_PHY_REFGEN_CLK>; 2180 assigned-clock-rates = <100000000>; 2181 2182 status = "disabled"; 2183 }; 2184 2185 ufs_mem_hc: ufshc@1d84000 { 2186 compatible = "qcom,sc8180x-ufshc", "qcom,ufshc", 2187 "jedec,ufs-2.0"; 2188 reg = <0 0x01d84000 0 0x2500>; 2189 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 2190 phys = <&ufs_mem_phy>; 2191 phy-names = "ufsphy"; 2192 lanes-per-direction = <2>; 2193 #reset-cells = <1>; 2194 resets = <&gcc GCC_UFS_PHY_BCR>; 2195 reset-names = "rst"; 2196 2197 iommus = <&apps_smmu 0x300 0>; 2198 2199 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, 2200 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 2201 <&gcc GCC_UFS_PHY_AHB_CLK>, 2202 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 2203 <&rpmhcc RPMH_CXO_CLK>, 2204 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 2205 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 2206 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; 2207 clock-names = "core_clk", 2208 "bus_aggr_clk", 2209 "iface_clk", 2210 "core_clk_unipro", 2211 "ref_clk", 2212 "tx_lane0_sync_clk", 2213 "rx_lane0_sync_clk", 2214 "rx_lane1_sync_clk"; 2215 freq-table-hz = <37500000 300000000>, 2216 <0 0>, 2217 <0 0>, 2218 <37500000 300000000>, 2219 <0 0>, 2220 <0 0>, 2221 <0 0>, 2222 <0 0>; 2223 2224 power-domains = <&gcc UFS_PHY_GDSC>; 2225 2226 interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS 2227 &mc_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ALWAYS>, 2228 <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ALWAYS 2229 &config_noc SLAVE_UFS_MEM_0_CFG QCOM_ICC_TAG_ALWAYS>; 2230 interconnect-names = "ufs-ddr", "cpu-ufs"; 2231 2232 status = "disabled"; 2233 }; 2234 2235 ufs_mem_phy: phy-wrapper@1d87000 { 2236 compatible = "qcom,sc8180x-qmp-ufs-phy"; 2237 reg = <0 0x01d87000 0 0x1000>; 2238 2239 clocks = <&rpmhcc RPMH_CXO_CLK>, 2240 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, 2241 <&gcc GCC_UFS_MEM_CLKREF_EN>; 2242 clock-names = "ref", 2243 "ref_aux", 2244 "qref"; 2245 2246 resets = <&ufs_mem_hc 0>; 2247 reset-names = "ufsphy"; 2248 2249 power-domains = <&gcc UFS_PHY_GDSC>; 2250 2251 #phy-cells = <0>; 2252 2253 status = "disabled"; 2254 }; 2255 2256 tcsr_mutex: hwlock@1f40000 { 2257 compatible = "qcom,tcsr-mutex"; 2258 reg = <0x0 0x01f40000 0x0 0x40000>; 2259 #hwlock-cells = <1>; 2260 }; 2261 2262 gpu: gpu@2c00000 { 2263 compatible = "qcom,adreno-680.1", "qcom,adreno"; 2264 2265 reg = <0 0x02c00000 0 0x40000>; 2266 reg-names = "kgsl_3d0_reg_memory"; 2267 2268 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 2269 2270 iommus = <&adreno_smmu 0 0xc01>; 2271 2272 operating-points-v2 = <&gpu_opp_table>; 2273 2274 interconnects = <&gem_noc MASTER_GRAPHICS_3D 0 &mc_virt SLAVE_EBI_CH0 0>; 2275 interconnect-names = "gfx-mem"; 2276 2277 qcom,gmu = <&gmu>; 2278 #cooling-cells = <2>; 2279 2280 status = "disabled"; 2281 2282 gpu_zap_shader: zap-shader { 2283 memory-region = <&gpu_mem>; 2284 }; 2285 2286 gpu_opp_table: opp-table { 2287 compatible = "operating-points-v2"; 2288 2289 opp-514000000 { 2290 opp-hz = /bits/ 64 <514000000>; 2291 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 2292 }; 2293 2294 opp-500000000 { 2295 opp-hz = /bits/ 64 <500000000>; 2296 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 2297 }; 2298 2299 opp-461000000 { 2300 opp-hz = /bits/ 64 <461000000>; 2301 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 2302 }; 2303 2304 opp-405000000 { 2305 opp-hz = /bits/ 64 <405000000>; 2306 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 2307 }; 2308 2309 opp-315000000 { 2310 opp-hz = /bits/ 64 <315000000>; 2311 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2312 }; 2313 2314 opp-256000000 { 2315 opp-hz = /bits/ 64 <256000000>; 2316 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2317 }; 2318 2319 opp-177000000 { 2320 opp-hz = /bits/ 64 <177000000>; 2321 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2322 }; 2323 }; 2324 }; 2325 2326 gmu: gmu@2c6a000 { 2327 compatible = "qcom,adreno-gmu-680.1", "qcom,adreno-gmu"; 2328 2329 reg = <0 0x02c6a000 0 0x30000>, 2330 <0 0x0b290000 0 0x10000>, 2331 <0 0x0b490000 0 0x10000>; 2332 reg-names = "gmu", 2333 "gmu_pdc", 2334 "gmu_pdc_seq"; 2335 2336 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 2337 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 2338 interrupt-names = "hfi", "gmu"; 2339 2340 clocks = <&gpucc GPU_CC_AHB_CLK>, 2341 <&gpucc GPU_CC_CX_GMU_CLK>, 2342 <&gpucc GPU_CC_CXO_CLK>, 2343 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 2344 <&gcc GCC_GPU_MEMNOC_GFX_CLK>; 2345 clock-names = "ahb", "gmu", "cxo", "axi", "memnoc"; 2346 2347 power-domains = <&gpucc GPU_CX_GDSC>, 2348 <&gpucc GPU_GX_GDSC>; 2349 power-domain-names = "cx", "gx"; 2350 2351 iommus = <&adreno_smmu 5 0xc00>; 2352 2353 operating-points-v2 = <&gmu_opp_table>; 2354 2355 gmu_opp_table: opp-table { 2356 compatible = "operating-points-v2"; 2357 2358 opp-200000000 { 2359 opp-hz = /bits/ 64 <200000000>; 2360 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 2361 }; 2362 2363 opp-500000000 { 2364 opp-hz = /bits/ 64 <500000000>; 2365 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2366 }; 2367 }; 2368 }; 2369 2370 gpucc: clock-controller@2c90000 { 2371 compatible = "qcom,sc8180x-gpucc"; 2372 reg = <0 0x02c90000 0 0x9000>; 2373 clocks = <&rpmhcc RPMH_CXO_CLK>, 2374 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 2375 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 2376 clock-names = "bi_tcxo", 2377 "gcc_gpu_gpll0_clk_src", 2378 "gcc_gpu_gpll0_div_clk_src"; 2379 #clock-cells = <1>; 2380 #reset-cells = <1>; 2381 #power-domain-cells = <1>; 2382 }; 2383 2384 adreno_smmu: iommu@2ca0000 { 2385 compatible = "qcom,sc8180x-smmu-500", "qcom,adreno-smmu", 2386 "qcom,smmu-500", "arm,mmu-500"; 2387 reg = <0 0x02ca0000 0 0x10000>; 2388 #iommu-cells = <2>; 2389 #global-interrupts = <1>; 2390 interrupts = <GIC_SPI 674 IRQ_TYPE_LEVEL_HIGH>, 2391 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 2392 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 2393 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 2394 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 2395 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, 2396 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, 2397 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>, 2398 <GIC_SPI 688 IRQ_TYPE_LEVEL_HIGH>; 2399 clocks = <&gpucc GPU_CC_AHB_CLK>, 2400 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2401 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>; 2402 clock-names = "ahb", "bus", "iface"; 2403 2404 power-domains = <&gpucc GPU_CX_GDSC>; 2405 }; 2406 2407 tlmm: pinctrl@3100000 { 2408 compatible = "qcom,sc8180x-tlmm"; 2409 reg = <0 0x03100000 0 0x300000>, 2410 <0 0x03500000 0 0x700000>, 2411 <0 0x03d00000 0 0x300000>; 2412 reg-names = "west", "east", "south"; 2413 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 2414 gpio-controller; 2415 #gpio-cells = <2>; 2416 interrupt-controller; 2417 #interrupt-cells = <2>; 2418 gpio-ranges = <&tlmm 0 0 191>; 2419 wakeup-parent = <&pdc>; 2420 }; 2421 2422 remoteproc_mpss: remoteproc@4080000 { 2423 compatible = "qcom,sc8180x-mpss-pas"; 2424 reg = <0x0 0x04080000 0x0 0x4040>; 2425 2426 interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>, 2427 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2428 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2429 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2430 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 2431 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 2432 interrupt-names = "wdog", "fatal", "ready", "handover", 2433 "stop-ack", "shutdown-ack"; 2434 2435 clocks = <&rpmhcc RPMH_CXO_CLK>; 2436 clock-names = "xo"; 2437 2438 power-domains = <&rpmhpd SC8180X_CX>, 2439 <&rpmhpd SC8180X_MSS>; 2440 power-domain-names = "cx", "mss"; 2441 2442 qcom,qmp = <&aoss_qmp>; 2443 2444 qcom,smem-states = <&modem_smp2p_out 0>; 2445 qcom,smem-state-names = "stop"; 2446 2447 glink-edge { 2448 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>; 2449 label = "modem"; 2450 qcom,remote-pid = <1>; 2451 mboxes = <&apss_shared 12>; 2452 }; 2453 }; 2454 2455 remoteproc_cdsp: remoteproc@8300000 { 2456 compatible = "qcom,sc8180x-cdsp-pas"; 2457 reg = <0x0 0x08300000 0x0 0x4040>; 2458 2459 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 2460 <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2461 <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2462 <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2463 <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 2464 interrupt-names = "wdog", "fatal", "ready", 2465 "handover", "stop-ack"; 2466 2467 clocks = <&rpmhcc RPMH_CXO_CLK>; 2468 clock-names = "xo"; 2469 2470 power-domains = <&rpmhpd SC8180X_CX>; 2471 power-domain-names = "cx"; 2472 2473 qcom,qmp = <&aoss_qmp>; 2474 2475 qcom,smem-states = <&cdsp_smp2p_out 0>; 2476 qcom,smem-state-names = "stop"; 2477 2478 status = "disabled"; 2479 2480 glink-edge { 2481 interrupts = <GIC_SPI 574 IRQ_TYPE_EDGE_RISING>; 2482 label = "cdsp"; 2483 qcom,remote-pid = <5>; 2484 mboxes = <&apss_shared 4>; 2485 }; 2486 }; 2487 2488 usb_prim_hsphy: phy@88e2000 { 2489 compatible = "qcom,sc8180x-usb-hs-phy", 2490 "qcom,usb-snps-hs-7nm-phy"; 2491 reg = <0 0x088e2000 0 0x400>; 2492 clocks = <&rpmhcc RPMH_CXO_CLK>; 2493 clock-names = "ref"; 2494 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 2495 2496 #phy-cells = <0>; 2497 2498 status = "disabled"; 2499 }; 2500 2501 usb_sec_hsphy: phy@88e3000 { 2502 compatible = "qcom,sc8180x-usb-hs-phy", 2503 "qcom,usb-snps-hs-7nm-phy"; 2504 reg = <0 0x088e3000 0 0x400>; 2505 clocks = <&rpmhcc RPMH_CXO_CLK>; 2506 clock-names = "ref"; 2507 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 2508 2509 #phy-cells = <0>; 2510 2511 status = "disabled"; 2512 }; 2513 2514 usb_mp_hsphy0: phy@88e4000 { 2515 compatible = "qcom,sc8180x-usb-hs-phy", 2516 "qcom,usb-snps-hs-7nm-phy"; 2517 reg = <0 0x088e4000 0 0x400>; 2518 #phy-cells = <0>; 2519 2520 clocks = <&rpmhcc RPMH_CXO_CLK>; 2521 clock-names = "ref"; 2522 2523 resets = <&gcc GCC_QUSB2PHY_MP0_BCR>; 2524 2525 status = "disabled"; 2526 }; 2527 2528 usb_mp_hsphy1: phy@88e5000 { 2529 compatible = "qcom,sc8180x-usb-hs-phy", 2530 "qcom,usb-snps-hs-7nm-phy"; 2531 reg = <0 0x088e5000 0 0x400>; 2532 #phy-cells = <0>; 2533 2534 clocks = <&rpmhcc RPMH_CXO_CLK>; 2535 clock-names = "ref"; 2536 2537 resets = <&gcc GCC_QUSB2PHY_MP1_BCR>; 2538 2539 status = "disabled"; 2540 }; 2541 2542 refgen: regulator@88e7000 { 2543 compatible = "qcom,sc8180x-refgen-regulator", 2544 "qcom,sdm845-refgen-regulator"; 2545 reg = <0x0 0x088e7000 0x0 0x60>; 2546 }; 2547 2548 usb_prim_qmpphy: phy@88e8000 { 2549 compatible = "qcom,sc8180x-qmp-usb3-dp-phy"; 2550 reg = <0 0x088e8000 0 0x3000>; 2551 2552 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 2553 <&gcc GCC_USB3_PRIM_CLKREF_CLK>, 2554 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 2555 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 2556 clock-names = "aux", 2557 "ref", 2558 "com_aux", 2559 "usb3_pipe"; 2560 2561 resets = <&gcc GCC_USB3_DP_PHY_PRIM_SP0_BCR>, 2562 <&gcc GCC_USB3_PHY_PRIM_SP0_BCR>; 2563 reset-names = "phy", "common"; 2564 2565 #clock-cells = <1>; 2566 #phy-cells = <1>; 2567 2568 status = "disabled"; 2569 2570 ports { 2571 #address-cells = <1>; 2572 #size-cells = <0>; 2573 2574 port@0 { 2575 reg = <0>; 2576 2577 usb_prim_qmpphy_out: endpoint {}; 2578 }; 2579 2580 port@1 { 2581 reg = <1>; 2582 2583 usb_prim_qmpphy_usb_ss_in: endpoint { 2584 remote-endpoint = <&usb_prim_dwc3_ss>; 2585 }; 2586 }; 2587 2588 port@2 { 2589 reg = <2>; 2590 2591 usb_prim_qmpphy_dp_in: endpoint {}; 2592 }; 2593 }; 2594 }; 2595 2596 usb_mp_qmpphy0: phy@88eb000 { 2597 compatible = "qcom,sc8180x-qmp-usb3-uni-phy"; 2598 reg = <0 0x088eb000 0 0x1000>; 2599 2600 clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>, 2601 <&gcc GCC_USB3_PRIM_CLKREF_CLK>, 2602 <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>, 2603 <&gcc GCC_USB3_MP_PHY_PIPE_0_CLK>; 2604 clock-names = "aux", 2605 "ref", 2606 "com_aux", 2607 "pipe"; 2608 2609 resets = <&gcc GCC_USB3_UNIPHY_MP0_BCR>, 2610 <&gcc GCC_USB3UNIPHY_PHY_MP0_BCR>; 2611 reset-names = "phy", "phy_phy"; 2612 2613 power-domains = <&gcc USB30_MP_GDSC>; 2614 2615 #clock-cells = <0>; 2616 clock-output-names = "usb2_phy0_pipe_clk"; 2617 2618 #phy-cells = <0>; 2619 2620 status = "disabled"; 2621 }; 2622 2623 usb_mp_qmpphy1: phy@88ec000 { 2624 compatible = "qcom,sc8180x-qmp-usb3-uni-phy"; 2625 reg = <0 0x088ec000 0 0x1000>; 2626 2627 clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>, 2628 <&gcc GCC_USB3_PRIM_CLKREF_CLK>, 2629 <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>, 2630 <&gcc GCC_USB3_MP_PHY_PIPE_1_CLK>; 2631 clock-names = "aux", 2632 "ref", 2633 "com_aux", 2634 "pipe"; 2635 2636 resets = <&gcc GCC_USB3_UNIPHY_MP1_BCR>, 2637 <&gcc GCC_USB3UNIPHY_PHY_MP1_BCR>; 2638 reset-names = "phy", "phy_phy"; 2639 2640 power-domains = <&gcc USB30_MP_GDSC>; 2641 2642 #clock-cells = <0>; 2643 clock-output-names = "usb2_phy1_pipe_clk"; 2644 2645 #phy-cells = <0>; 2646 2647 status = "disabled"; 2648 }; 2649 2650 usb_sec_qmpphy: phy@88ee000 { 2651 compatible = "qcom,sc8180x-qmp-usb3-dp-phy"; 2652 reg = <0 0x088ed000 0 0x3000>; 2653 2654 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, 2655 <&gcc GCC_USB3_SEC_CLKREF_CLK>, 2656 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>, 2657 <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; 2658 clock-names = "aux", 2659 "ref", 2660 "com_aux", 2661 "usb3_pipe"; 2662 resets = <&gcc GCC_USB3_DP_PHY_SEC_BCR>, 2663 <&gcc GCC_USB3_PHY_SEC_BCR>; 2664 reset-names = "phy", "common"; 2665 2666 #clock-cells = <1>; 2667 #phy-cells = <1>; 2668 2669 status = "disabled"; 2670 2671 ports { 2672 #address-cells = <1>; 2673 #size-cells = <0>; 2674 2675 port@0 { 2676 reg = <0>; 2677 2678 usb_sec_qmpphy_out: endpoint {}; 2679 }; 2680 2681 port@1 { 2682 reg = <1>; 2683 2684 usb_sec_qmpphy_usb_ss_in: endpoint { 2685 remote-endpoint = <&usb_sec_dwc3_ss>; 2686 }; 2687 }; 2688 2689 port@2 { 2690 reg = <2>; 2691 2692 usb_sec_qmpphy_dp_in: endpoint {}; 2693 }; 2694 }; 2695 }; 2696 2697 system-cache-controller@9200000 { 2698 compatible = "qcom,sc8180x-llcc"; 2699 reg = <0 0x09200000 0 0x58000>, <0 0x09280000 0 0x58000>, 2700 <0 0x09300000 0 0x58000>, <0 0x09380000 0 0x58000>, 2701 <0 0x09400000 0 0x58000>, <0 0x09480000 0 0x58000>, 2702 <0 0x09500000 0 0x58000>, <0 0x09580000 0 0x58000>, 2703 <0 0x09600000 0 0x58000>; 2704 reg-names = "llcc0_base", "llcc1_base", "llcc2_base", 2705 "llcc3_base", "llcc4_base", "llcc5_base", 2706 "llcc6_base", "llcc7_base", "llcc_broadcast_base"; 2707 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 2708 }; 2709 2710 gem_noc: interconnect@9680000 { 2711 compatible = "qcom,sc8180x-gem-noc"; 2712 reg = <0 0x09680000 0 0x58200>; 2713 #interconnect-cells = <2>; 2714 qcom,bcm-voters = <&apps_bcm_voter>; 2715 }; 2716 2717 usb_mp: usb@a4f8800 { 2718 compatible = "qcom,sc8180x-dwc3-mp", "qcom,dwc3"; 2719 reg = <0 0x0a4f8800 0 0x400>; 2720 #address-cells = <2>; 2721 #size-cells = <2>; 2722 ranges; 2723 dma-ranges; 2724 2725 clocks = <&gcc GCC_CFG_NOC_USB3_MP_AXI_CLK>, 2726 <&gcc GCC_USB30_MP_MASTER_CLK>, 2727 <&gcc GCC_AGGRE_USB3_MP_AXI_CLK>, 2728 <&gcc GCC_USB30_MP_SLEEP_CLK>, 2729 <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>, 2730 <&gcc GCC_USB3_SEC_CLKREF_CLK>; 2731 clock-names = "cfg_noc", 2732 "core", 2733 "iface", 2734 "sleep", 2735 "mock_utmi", 2736 "xo"; 2737 2738 interconnects = <&aggre1_noc MASTER_USB3_2 0 &mc_virt SLAVE_EBI_CH0 0>, 2739 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3_2 0>; 2740 interconnect-names = "usb-ddr", "apps-usb"; 2741 2742 assigned-clocks = <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>, 2743 <&gcc GCC_USB30_MP_MASTER_CLK>; 2744 assigned-clock-rates = <19200000>, <200000000>; 2745 2746 interrupts-extended = <&intc GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH>, 2747 <&intc GIC_SPI 655 IRQ_TYPE_LEVEL_HIGH>, 2748 <&intc GIC_SPI 658 IRQ_TYPE_LEVEL_HIGH>, 2749 <&intc GIC_SPI 657 IRQ_TYPE_LEVEL_HIGH>, 2750 <&pdc 59 IRQ_TYPE_EDGE_BOTH>, 2751 <&pdc 46 IRQ_TYPE_EDGE_BOTH>, 2752 <&pdc 71 IRQ_TYPE_EDGE_BOTH>, 2753 <&pdc 68 IRQ_TYPE_EDGE_BOTH>, 2754 <&pdc 7 IRQ_TYPE_LEVEL_HIGH>, 2755 <&pdc 30 IRQ_TYPE_LEVEL_HIGH>; 2756 interrupt-names = "pwr_event_1", "pwr_event_2", 2757 "hs_phy_1", "hs_phy_2", 2758 "dp_hs_phy_1", "dm_hs_phy_1", 2759 "dp_hs_phy_2", "dm_hs_phy_2", 2760 "ss_phy_1", "ss_phy_2"; 2761 2762 power-domains = <&gcc USB30_MP_GDSC>; 2763 2764 resets = <&gcc GCC_USB30_MP_BCR>; 2765 2766 status = "disabled"; 2767 2768 usb_mp_dwc3: usb@a400000 { 2769 compatible = "snps,dwc3"; 2770 reg = <0 0x0a400000 0 0xcd00>; 2771 interrupts = <GIC_SPI 654 IRQ_TYPE_LEVEL_HIGH>; 2772 iommus = <&apps_smmu 0x60 0>; 2773 snps,dis_u2_susphy_quirk; 2774 snps,dis_enblslpm_quirk; 2775 snps,dis-u1-entry-quirk; 2776 snps,dis-u2-entry-quirk; 2777 phys = <&usb_mp_hsphy0>, 2778 <&usb_mp_qmpphy0>, 2779 <&usb_mp_hsphy1>, 2780 <&usb_mp_qmpphy1>; 2781 phy-names = "usb2-0", 2782 "usb3-0", 2783 "usb2-1", 2784 "usb3-1"; 2785 dr_mode = "host"; 2786 }; 2787 }; 2788 2789 usb_prim: usb@a6f8800 { 2790 compatible = "qcom,sc8180x-dwc3", "qcom,dwc3"; 2791 reg = <0 0x0a6f8800 0 0x400>; 2792 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 2793 <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 2794 <&pdc 9 IRQ_TYPE_EDGE_BOTH>, 2795 <&pdc 8 IRQ_TYPE_EDGE_BOTH>, 2796 <&pdc 6 IRQ_TYPE_LEVEL_HIGH>; 2797 interrupt-names = "pwr_event", 2798 "hs_phy_irq", 2799 "dp_hs_phy_irq", 2800 "dm_hs_phy_irq", 2801 "ss_phy_irq"; 2802 2803 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 2804 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 2805 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 2806 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 2807 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 2808 <&gcc GCC_USB3_SEC_CLKREF_CLK>; 2809 clock-names = "cfg_noc", 2810 "core", 2811 "iface", 2812 "sleep", 2813 "mock_utmi", 2814 "xo"; 2815 resets = <&gcc GCC_USB30_PRIM_BCR>; 2816 power-domains = <&gcc USB30_PRIM_GDSC>; 2817 2818 interconnects = <&aggre1_noc MASTER_USB3 0 &mc_virt SLAVE_EBI_CH0 0>, 2819 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3 0>; 2820 interconnect-names = "usb-ddr", "apps-usb"; 2821 2822 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 2823 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 2824 assigned-clock-rates = <19200000>, <200000000>; 2825 2826 #address-cells = <2>; 2827 #size-cells = <2>; 2828 ranges; 2829 dma-ranges; 2830 2831 status = "disabled"; 2832 2833 usb_prim_dwc3: usb@a600000 { 2834 compatible = "snps,dwc3"; 2835 reg = <0 0x0a600000 0 0xcd00>; 2836 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 2837 iommus = <&apps_smmu 0x140 0>; 2838 snps,dis_u2_susphy_quirk; 2839 snps,dis_enblslpm_quirk; 2840 snps,dis-u1-entry-quirk; 2841 snps,dis-u2-entry-quirk; 2842 phys = <&usb_prim_hsphy>, <&usb_prim_qmpphy QMP_USB43DP_USB3_PHY>; 2843 phy-names = "usb2-phy", "usb3-phy"; 2844 2845 ports { 2846 #address-cells = <1>; 2847 #size-cells = <0>; 2848 2849 port@0 { 2850 reg = <0>; 2851 2852 usb_prim_dwc3_hs: endpoint { 2853 }; 2854 }; 2855 2856 port@1 { 2857 reg = <1>; 2858 2859 usb_prim_dwc3_ss: endpoint { 2860 remote-endpoint = <&usb_prim_qmpphy_usb_ss_in>; 2861 }; 2862 }; 2863 }; 2864 }; 2865 }; 2866 2867 usb_sec: usb@a8f8800 { 2868 compatible = "qcom,sc8180x-dwc3", "qcom,dwc3"; 2869 reg = <0 0x0a8f8800 0 0x400>; 2870 2871 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 2872 <&gcc GCC_USB30_SEC_MASTER_CLK>, 2873 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 2874 <&gcc GCC_USB30_SEC_SLEEP_CLK>, 2875 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 2876 <&gcc GCC_USB3_SEC_CLKREF_CLK>; 2877 clock-names = "cfg_noc", 2878 "core", 2879 "iface", 2880 "sleep", 2881 "mock_utmi", 2882 "xo"; 2883 resets = <&gcc GCC_USB30_SEC_BCR>; 2884 power-domains = <&gcc USB30_SEC_GDSC>; 2885 2886 interrupts-extended = <&intc GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 2887 <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 2888 <&pdc 11 IRQ_TYPE_EDGE_BOTH>, 2889 <&pdc 10 IRQ_TYPE_EDGE_BOTH>, 2890 <&pdc 40 IRQ_TYPE_LEVEL_HIGH>; 2891 interrupt-names = "pwr_event", 2892 "hs_phy_irq", 2893 "dp_hs_phy_irq", 2894 "dm_hs_phy_irq", 2895 "ss_phy_irq"; 2896 2897 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 2898 <&gcc GCC_USB30_SEC_MASTER_CLK>; 2899 assigned-clock-rates = <19200000>, <200000000>; 2900 2901 interconnects = <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI_CH0 0>, 2902 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3_1 0>; 2903 interconnect-names = "usb-ddr", "apps-usb"; 2904 2905 #address-cells = <2>; 2906 #size-cells = <2>; 2907 ranges; 2908 dma-ranges; 2909 2910 status = "disabled"; 2911 2912 usb_sec_dwc3: usb@a800000 { 2913 compatible = "snps,dwc3"; 2914 reg = <0 0x0a800000 0 0xcd00>; 2915 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 2916 iommus = <&apps_smmu 0x160 0>; 2917 snps,dis_u2_susphy_quirk; 2918 snps,dis_enblslpm_quirk; 2919 snps,dis-u1-entry-quirk; 2920 snps,dis-u2-entry-quirk; 2921 phys = <&usb_sec_hsphy>, <&usb_sec_qmpphy QMP_USB43DP_USB3_PHY>; 2922 phy-names = "usb2-phy", "usb3-phy"; 2923 2924 ports { 2925 #address-cells = <1>; 2926 #size-cells = <0>; 2927 2928 port@0 { 2929 reg = <0>; 2930 2931 usb_sec_dwc3_hs: endpoint { 2932 }; 2933 }; 2934 2935 port@1 { 2936 reg = <1>; 2937 2938 usb_sec_dwc3_ss: endpoint { 2939 remote-endpoint = <&usb_sec_qmpphy_usb_ss_in>; 2940 }; 2941 }; 2942 }; 2943 }; 2944 }; 2945 2946 videocc: clock-controller@ab00000 { 2947 compatible = "qcom,sc8180x-videocc", 2948 "qcom,sm8150-videocc"; 2949 reg = <0 0x0ab00000 0 0x10000>; 2950 clocks = <&gcc GCC_VIDEO_AHB_CLK>, 2951 <&rpmhcc RPMH_CXO_CLK>; 2952 clock-names = "iface", "bi_tcxo"; 2953 power-domains = <&rpmhpd SC8180X_MMCX>; 2954 required-opps = <&rpmhpd_opp_low_svs>; 2955 #clock-cells = <1>; 2956 #reset-cells = <1>; 2957 #power-domain-cells = <1>; 2958 }; 2959 2960 camcc: clock-controller@ad00000 { 2961 compatible = "qcom,sc8180x-camcc"; 2962 reg = <0 0x0ad00000 0 0x20000>; 2963 clocks = <&gcc GCC_CAMERA_AHB_CLK>, 2964 <&rpmhcc RPMH_CXO_CLK>, 2965 <&sleep_clk>; 2966 power-domains = <&rpmhpd SC8180X_MMCX>; 2967 required-opps = <&rpmhpd_opp_low_svs>; 2968 #clock-cells = <1>; 2969 #reset-cells = <1>; 2970 #power-domain-cells = <1>; 2971 }; 2972 2973 mdss: display-subsystem@ae00000 { 2974 compatible = "qcom,sc8180x-mdss"; 2975 reg = <0 0x0ae00000 0 0x1000>; 2976 reg-names = "mdss"; 2977 2978 power-domains = <&dispcc MDSS_GDSC>; 2979 2980 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2981 <&gcc GCC_DISP_HF_AXI_CLK>, 2982 <&gcc GCC_DISP_SF_AXI_CLK>, 2983 <&dispcc DISP_CC_MDSS_MDP_CLK>; 2984 clock-names = "iface", 2985 "bus", 2986 "nrt_bus", 2987 "core"; 2988 2989 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; 2990 2991 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 2992 interrupt-controller; 2993 #interrupt-cells = <1>; 2994 2995 interconnects = <&mmss_noc MASTER_MDP_PORT0 QCOM_ICC_TAG_ALWAYS 2996 &mc_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ALWAYS>, 2997 <&mmss_noc MASTER_MDP_PORT1 QCOM_ICC_TAG_ALWAYS 2998 &mc_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ALWAYS>, 2999 <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ALWAYS 3000 &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ALWAYS>; 3001 interconnect-names = "mdp0-mem", 3002 "mdp1-mem", 3003 "cpu-cfg"; 3004 3005 iommus = <&apps_smmu 0x800 0x420>; 3006 3007 #address-cells = <2>; 3008 #size-cells = <2>; 3009 ranges; 3010 3011 status = "disabled"; 3012 3013 mdss_mdp: display-controller@ae01000 { 3014 compatible = "qcom,sc8180x-dpu"; 3015 reg = <0 0x0ae01000 0 0x8f000>, 3016 <0 0x0aeb0000 0 0x3000>; 3017 reg-names = "mdp", "vbif"; 3018 3019 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3020 <&gcc GCC_DISP_HF_AXI_CLK>, 3021 <&dispcc DISP_CC_MDSS_MDP_CLK>, 3022 <&dispcc DISP_CC_MDSS_VSYNC_CLK>, 3023 <&dispcc DISP_CC_MDSS_ROT_CLK>, 3024 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>; 3025 clock-names = "iface", 3026 "bus", 3027 "core", 3028 "vsync", 3029 "rot", 3030 "lut"; 3031 3032 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 3033 assigned-clock-rates = <19200000>; 3034 3035 operating-points-v2 = <&mdp_opp_table>; 3036 power-domains = <&rpmhpd SC8180X_MMCX>; 3037 3038 interrupt-parent = <&mdss>; 3039 interrupts = <0>; 3040 3041 ports { 3042 #address-cells = <1>; 3043 #size-cells = <0>; 3044 3045 port@0 { 3046 reg = <0>; 3047 dpu_intf0_out: endpoint { 3048 remote-endpoint = <&dp0_in>; 3049 }; 3050 }; 3051 3052 port@1 { 3053 reg = <1>; 3054 dpu_intf1_out: endpoint { 3055 remote-endpoint = <&mdss_dsi0_in>; 3056 }; 3057 }; 3058 3059 port@2 { 3060 reg = <2>; 3061 dpu_intf2_out: endpoint { 3062 remote-endpoint = <&mdss_dsi1_in>; 3063 }; 3064 }; 3065 3066 port@4 { 3067 reg = <4>; 3068 dpu_intf4_out: endpoint { 3069 remote-endpoint = <&dp1_in>; 3070 }; 3071 }; 3072 3073 port@5 { 3074 reg = <5>; 3075 dpu_intf5_out: endpoint { 3076 remote-endpoint = <&edp_in>; 3077 }; 3078 }; 3079 }; 3080 3081 mdp_opp_table: opp-table { 3082 compatible = "operating-points-v2"; 3083 3084 opp-200000000 { 3085 opp-hz = /bits/ 64 <200000000>; 3086 required-opps = <&rpmhpd_opp_low_svs>; 3087 }; 3088 3089 opp-300000000 { 3090 opp-hz = /bits/ 64 <300000000>; 3091 required-opps = <&rpmhpd_opp_svs>; 3092 }; 3093 3094 opp-345000000 { 3095 opp-hz = /bits/ 64 <345000000>; 3096 required-opps = <&rpmhpd_opp_svs_l1>; 3097 }; 3098 3099 opp-460000000 { 3100 opp-hz = /bits/ 64 <460000000>; 3101 required-opps = <&rpmhpd_opp_nom>; 3102 }; 3103 }; 3104 }; 3105 3106 mdss_dsi0: dsi@ae94000 { 3107 compatible = "qcom,sc8180x-dsi-ctrl", 3108 "qcom,mdss-dsi-ctrl"; 3109 reg = <0 0x0ae94000 0 0x400>; 3110 reg-names = "dsi_ctrl"; 3111 3112 interrupt-parent = <&mdss>; 3113 interrupts = <4>; 3114 3115 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 3116 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 3117 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 3118 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 3119 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3120 <&gcc GCC_DISP_HF_AXI_CLK>; 3121 clock-names = "byte", 3122 "byte_intf", 3123 "pixel", 3124 "core", 3125 "iface", 3126 "bus"; 3127 3128 operating-points-v2 = <&dsi_opp_table>; 3129 power-domains = <&rpmhpd SC8180X_MMCX>; 3130 3131 phys = <&mdss_dsi0_phy>; 3132 phy-names = "dsi"; 3133 3134 refgen-supply = <&refgen>; 3135 3136 status = "disabled"; 3137 3138 ports { 3139 #address-cells = <1>; 3140 #size-cells = <0>; 3141 3142 port@0 { 3143 reg = <0>; 3144 mdss_dsi0_in: endpoint { 3145 remote-endpoint = <&dpu_intf1_out>; 3146 }; 3147 }; 3148 3149 port@1 { 3150 reg = <1>; 3151 mdss_dsi0_out: endpoint { 3152 }; 3153 }; 3154 }; 3155 3156 dsi_opp_table: opp-table { 3157 compatible = "operating-points-v2"; 3158 3159 opp-187500000 { 3160 opp-hz = /bits/ 64 <187500000>; 3161 required-opps = <&rpmhpd_opp_low_svs>; 3162 }; 3163 3164 opp-300000000 { 3165 opp-hz = /bits/ 64 <300000000>; 3166 required-opps = <&rpmhpd_opp_svs>; 3167 }; 3168 3169 opp-358000000 { 3170 opp-hz = /bits/ 64 <358000000>; 3171 required-opps = <&rpmhpd_opp_svs_l1>; 3172 }; 3173 }; 3174 }; 3175 3176 mdss_dsi0_phy: phy@ae94400 { 3177 compatible = "qcom,dsi-phy-7nm"; 3178 reg = <0 0x0ae94400 0 0x200>, 3179 <0 0x0ae94600 0 0x280>, 3180 <0 0x0ae94900 0 0x260>; 3181 reg-names = "dsi_phy", 3182 "dsi_phy_lane", 3183 "dsi_pll"; 3184 3185 #clock-cells = <1>; 3186 #phy-cells = <0>; 3187 3188 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3189 <&rpmhcc RPMH_CXO_CLK>; 3190 clock-names = "iface", "ref"; 3191 3192 status = "disabled"; 3193 }; 3194 3195 mdss_dsi1: dsi@ae96000 { 3196 compatible = "qcom,sc8180x-dsi-ctrl", 3197 "qcom,mdss-dsi-ctrl"; 3198 reg = <0 0x0ae96000 0 0x400>; 3199 reg-names = "dsi_ctrl"; 3200 3201 interrupt-parent = <&mdss>; 3202 interrupts = <5>; 3203 3204 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, 3205 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, 3206 <&dispcc DISP_CC_MDSS_PCLK1_CLK>, 3207 <&dispcc DISP_CC_MDSS_ESC1_CLK>, 3208 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3209 <&gcc GCC_DISP_HF_AXI_CLK>; 3210 clock-names = "byte", 3211 "byte_intf", 3212 "pixel", 3213 "core", 3214 "iface", 3215 "bus"; 3216 3217 operating-points-v2 = <&dsi_opp_table>; 3218 power-domains = <&rpmhpd SC8180X_MMCX>; 3219 3220 phys = <&mdss_dsi1_phy>; 3221 phy-names = "dsi"; 3222 3223 refgen-supply = <&refgen>; 3224 3225 status = "disabled"; 3226 3227 ports { 3228 #address-cells = <1>; 3229 #size-cells = <0>; 3230 3231 port@0 { 3232 reg = <0>; 3233 mdss_dsi1_in: endpoint { 3234 remote-endpoint = <&dpu_intf2_out>; 3235 }; 3236 }; 3237 3238 port@1 { 3239 reg = <1>; 3240 mdss_dsi1_out: endpoint { 3241 }; 3242 }; 3243 }; 3244 }; 3245 3246 mdss_dsi1_phy: phy@ae96400 { 3247 compatible = "qcom,dsi-phy-7nm"; 3248 reg = <0 0x0ae96400 0 0x200>, 3249 <0 0x0ae96600 0 0x280>, 3250 <0 0x0ae96900 0 0x260>; 3251 reg-names = "dsi_phy", 3252 "dsi_phy_lane", 3253 "dsi_pll"; 3254 3255 #clock-cells = <1>; 3256 #phy-cells = <0>; 3257 3258 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3259 <&rpmhcc RPMH_CXO_CLK>; 3260 clock-names = "iface", "ref"; 3261 3262 status = "disabled"; 3263 }; 3264 3265 mdss_dp0: displayport-controller@ae90000 { 3266 compatible = "qcom,sc8180x-dp"; 3267 reg = <0 0xae90000 0 0x200>, 3268 <0 0xae90200 0 0x200>, 3269 <0 0xae90400 0 0x600>, 3270 <0 0xae90a00 0 0x400>, 3271 <0 0xae91000 0 0x400>; 3272 interrupt-parent = <&mdss>; 3273 interrupts = <12>; 3274 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3275 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, 3276 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, 3277 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, 3278 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>, 3279 <&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK>; 3280 clock-names = "core_iface", 3281 "core_aux", 3282 "ctrl_link", 3283 "ctrl_link_iface", 3284 "stream_pixel", 3285 "stream_1_pixel"; 3286 3287 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, 3288 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>, 3289 <&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK_SRC>; 3290 assigned-clock-parents = <&usb_prim_qmpphy QMP_USB43DP_DP_LINK_CLK>, 3291 <&usb_prim_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 3292 <&usb_prim_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 3293 3294 phys = <&usb_prim_qmpphy QMP_USB43DP_DP_PHY>; 3295 phy-names = "dp"; 3296 3297 #sound-dai-cells = <0>; 3298 3299 operating-points-v2 = <&dp0_opp_table>; 3300 power-domains = <&rpmhpd SC8180X_MMCX>; 3301 3302 status = "disabled"; 3303 3304 ports { 3305 #address-cells = <1>; 3306 #size-cells = <0>; 3307 3308 port@0 { 3309 reg = <0>; 3310 dp0_in: endpoint { 3311 remote-endpoint = <&dpu_intf0_out>; 3312 }; 3313 }; 3314 3315 port@1 { 3316 reg = <1>; 3317 mdss_dp0_out: endpoint { 3318 }; 3319 }; 3320 }; 3321 3322 dp0_opp_table: opp-table { 3323 compatible = "operating-points-v2"; 3324 3325 opp-160000000 { 3326 opp-hz = /bits/ 64 <160000000>; 3327 required-opps = <&rpmhpd_opp_low_svs>; 3328 }; 3329 3330 opp-270000000 { 3331 opp-hz = /bits/ 64 <270000000>; 3332 required-opps = <&rpmhpd_opp_svs>; 3333 }; 3334 3335 opp-540000000 { 3336 opp-hz = /bits/ 64 <540000000>; 3337 required-opps = <&rpmhpd_opp_svs_l1>; 3338 }; 3339 3340 opp-810000000 { 3341 opp-hz = /bits/ 64 <810000000>; 3342 required-opps = <&rpmhpd_opp_nom>; 3343 }; 3344 }; 3345 }; 3346 3347 mdss_dp1: displayport-controller@ae98000 { 3348 compatible = "qcom,sc8180x-dp"; 3349 reg = <0 0xae98000 0 0x200>, 3350 <0 0xae98200 0 0x200>, 3351 <0 0xae98400 0 0x600>, 3352 <0 0xae98a00 0 0x400>, 3353 <0 0xae99000 0 0x400>; 3354 interrupt-parent = <&mdss>; 3355 interrupts = <13>; 3356 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3357 <&dispcc DISP_CC_MDSS_DP_AUX1_CLK>, 3358 <&dispcc DISP_CC_MDSS_DP_LINK1_CLK>, 3359 <&dispcc DISP_CC_MDSS_DP_LINK1_INTF_CLK>, 3360 <&dispcc DISP_CC_MDSS_DP_PIXEL2_CLK>, 3361 <&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK>; 3362 clock-names = "core_iface", 3363 "core_aux", 3364 "ctrl_link", 3365 "ctrl_link_iface", 3366 "stream_pixel", 3367 "stream_1_pixel"; 3368 3369 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK1_CLK_SRC>, 3370 <&dispcc DISP_CC_MDSS_DP_PIXEL2_CLK_SRC>, 3371 <&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK_SRC>; 3372 assigned-clock-parents = <&usb_sec_qmpphy QMP_USB43DP_DP_LINK_CLK>, 3373 <&usb_sec_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 3374 <&usb_sec_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 3375 3376 phys = <&usb_sec_qmpphy QMP_USB43DP_DP_PHY>; 3377 phy-names = "dp"; 3378 3379 #sound-dai-cells = <0>; 3380 3381 operating-points-v2 = <&dp0_opp_table>; 3382 power-domains = <&rpmhpd SC8180X_MMCX>; 3383 3384 status = "disabled"; 3385 3386 ports { 3387 #address-cells = <1>; 3388 #size-cells = <0>; 3389 3390 port@0 { 3391 reg = <0>; 3392 dp1_in: endpoint { 3393 remote-endpoint = <&dpu_intf4_out>; 3394 }; 3395 }; 3396 3397 port@1 { 3398 reg = <1>; 3399 mdss_dp1_out: endpoint { 3400 }; 3401 }; 3402 }; 3403 3404 dp1_opp_table: opp-table { 3405 compatible = "operating-points-v2"; 3406 3407 opp-160000000 { 3408 opp-hz = /bits/ 64 <160000000>; 3409 required-opps = <&rpmhpd_opp_low_svs>; 3410 }; 3411 3412 opp-270000000 { 3413 opp-hz = /bits/ 64 <270000000>; 3414 required-opps = <&rpmhpd_opp_svs>; 3415 }; 3416 3417 opp-540000000 { 3418 opp-hz = /bits/ 64 <540000000>; 3419 required-opps = <&rpmhpd_opp_svs_l1>; 3420 }; 3421 3422 opp-810000000 { 3423 opp-hz = /bits/ 64 <810000000>; 3424 required-opps = <&rpmhpd_opp_nom>; 3425 }; 3426 }; 3427 }; 3428 3429 mdss_edp: displayport-controller@ae9a000 { 3430 compatible = "qcom,sc8180x-edp"; 3431 reg = <0 0xae9a000 0 0x200>, 3432 <0 0xae9a200 0 0x200>, 3433 <0 0xae9a400 0 0x600>, 3434 <0 0xae9aa00 0 0x400>, 3435 <0 0xae9b000 0 0x400>; 3436 interrupt-parent = <&mdss>; 3437 interrupts = <14>; 3438 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3439 <&dispcc DISP_CC_MDSS_EDP_AUX_CLK>, 3440 <&dispcc DISP_CC_MDSS_EDP_LINK_CLK>, 3441 <&dispcc DISP_CC_MDSS_EDP_LINK_INTF_CLK>, 3442 <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK>; 3443 clock-names = "core_iface", 3444 "core_aux", 3445 "ctrl_link", 3446 "ctrl_link_iface", 3447 "stream_pixel"; 3448 3449 assigned-clocks = <&dispcc DISP_CC_MDSS_EDP_LINK_CLK_SRC>, 3450 <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK_SRC>; 3451 assigned-clock-parents = <&edp_phy 0>, <&edp_phy 1>; 3452 3453 phys = <&edp_phy>; 3454 phy-names = "dp"; 3455 3456 operating-points-v2 = <&edp_opp_table>; 3457 power-domains = <&rpmhpd SC8180X_MMCX>; 3458 3459 status = "disabled"; 3460 3461 ports { 3462 #address-cells = <1>; 3463 #size-cells = <0>; 3464 3465 port@0 { 3466 reg = <0>; 3467 edp_in: endpoint { 3468 remote-endpoint = <&dpu_intf5_out>; 3469 }; 3470 }; 3471 3472 port@1 { 3473 reg = <1>; 3474 3475 mdss_edp_out: endpoint { 3476 }; 3477 }; 3478 }; 3479 3480 edp_opp_table: opp-table { 3481 compatible = "operating-points-v2"; 3482 3483 opp-160000000 { 3484 opp-hz = /bits/ 64 <160000000>; 3485 required-opps = <&rpmhpd_opp_low_svs>; 3486 }; 3487 3488 opp-270000000 { 3489 opp-hz = /bits/ 64 <270000000>; 3490 required-opps = <&rpmhpd_opp_svs>; 3491 }; 3492 3493 opp-540000000 { 3494 opp-hz = /bits/ 64 <540000000>; 3495 required-opps = <&rpmhpd_opp_svs_l1>; 3496 }; 3497 3498 opp-810000000 { 3499 opp-hz = /bits/ 64 <810000000>; 3500 required-opps = <&rpmhpd_opp_nom>; 3501 }; 3502 }; 3503 }; 3504 }; 3505 3506 edp_phy: phy@aec2a00 { 3507 compatible = "qcom,sc8180x-edp-phy"; 3508 reg = <0 0x0aec2a00 0 0x1c0>, 3509 <0 0x0aec2200 0 0xa0>, 3510 <0 0x0aec2600 0 0xa0>, 3511 <0 0x0aec2000 0 0x19c>; 3512 3513 clocks = <&dispcc DISP_CC_MDSS_EDP_AUX_CLK>, 3514 <&dispcc DISP_CC_MDSS_AHB_CLK>; 3515 clock-names = "aux", "cfg_ahb"; 3516 3517 power-domains = <&rpmhpd SC8180X_MX>; 3518 3519 #clock-cells = <1>; 3520 #phy-cells = <0>; 3521 }; 3522 3523 dispcc: clock-controller@af00000 { 3524 compatible = "qcom,sc8180x-dispcc"; 3525 reg = <0 0x0af00000 0 0x20000>; 3526 clocks = <&rpmhcc RPMH_CXO_CLK>, 3527 <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, 3528 <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>, 3529 <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>, 3530 <&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>, 3531 <&usb_prim_qmpphy QMP_USB43DP_DP_LINK_CLK>, 3532 <&usb_prim_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 3533 <&edp_phy 0>, 3534 <&edp_phy 1>, 3535 <&usb_sec_qmpphy QMP_USB43DP_DP_LINK_CLK>, 3536 <&usb_sec_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 3537 clock-names = "bi_tcxo", 3538 "dsi0_phy_pll_out_byteclk", 3539 "dsi0_phy_pll_out_dsiclk", 3540 "dsi1_phy_pll_out_byteclk", 3541 "dsi1_phy_pll_out_dsiclk", 3542 "dp_phy_pll_link_clk", 3543 "dp_phy_pll_vco_div_clk", 3544 "edp_phy_pll_link_clk", 3545 "edp_phy_pll_vco_div_clk", 3546 "dptx1_phy_pll_link_clk", 3547 "dptx1_phy_pll_vco_div_clk"; 3548 power-domains = <&rpmhpd SC8180X_MMCX>; 3549 required-opps = <&rpmhpd_opp_low_svs>; 3550 #clock-cells = <1>; 3551 #reset-cells = <1>; 3552 #power-domain-cells = <1>; 3553 }; 3554 3555 pdc: interrupt-controller@b220000 { 3556 compatible = "qcom,sc8180x-pdc", "qcom,pdc"; 3557 reg = <0 0x0b220000 0 0x30000>; 3558 qcom,pdc-ranges = <0 480 94>, <94 609 31>; 3559 #interrupt-cells = <2>; 3560 interrupt-parent = <&intc>; 3561 interrupt-controller; 3562 }; 3563 3564 tsens0: thermal-sensor@c263000 { 3565 compatible = "qcom,sc8180x-tsens", "qcom,tsens-v2"; 3566 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 3567 <0 0x0c222000 0 0x1ff>; /* SROT */ 3568 #qcom,sensors = <16>; 3569 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 3570 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 3571 interrupt-names = "uplow", "critical"; 3572 #thermal-sensor-cells = <1>; 3573 }; 3574 3575 tsens1: thermal-sensor@c265000 { 3576 compatible = "qcom,sc8180x-tsens", "qcom,tsens-v2"; 3577 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 3578 <0 0x0c223000 0 0x1ff>; /* SROT */ 3579 #qcom,sensors = <9>; 3580 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 3581 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 3582 interrupt-names = "uplow", "critical"; 3583 #thermal-sensor-cells = <1>; 3584 }; 3585 3586 aoss_qmp: power-management@c300000 { 3587 compatible = "qcom,sc8180x-aoss-qmp", "qcom,aoss-qmp"; 3588 reg = <0x0 0x0c300000 0x0 0x400>; 3589 interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>; 3590 mboxes = <&apss_shared 0>; 3591 3592 #clock-cells = <0>; 3593 }; 3594 3595 sram@c3f0000 { 3596 compatible = "qcom,rpmh-stats"; 3597 reg = <0x0 0x0c3f0000 0x0 0x400>; 3598 }; 3599 3600 spmi_bus: spmi@c440000 { 3601 compatible = "qcom,spmi-pmic-arb"; 3602 reg = <0x0 0x0c440000 0x0 0x0001100>, 3603 <0x0 0x0c600000 0x0 0x2000000>, 3604 <0x0 0x0e600000 0x0 0x0100000>, 3605 <0x0 0x0e700000 0x0 0x00a0000>, 3606 <0x0 0x0c40a000 0x0 0x0026000>; 3607 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 3608 interrupt-names = "periph_irq"; 3609 interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>; 3610 qcom,ee = <0>; 3611 qcom,channel = <0>; 3612 #address-cells = <2>; 3613 #size-cells = <0>; 3614 interrupt-controller; 3615 #interrupt-cells = <4>; 3616 }; 3617 3618 apps_smmu: iommu@15000000 { 3619 compatible = "qcom,sc8180x-smmu-500", "arm,mmu-500"; 3620 reg = <0 0x15000000 0 0x100000>; 3621 #iommu-cells = <2>; 3622 #global-interrupts = <1>; 3623 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 3624 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 3625 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 3626 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 3627 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 3628 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 3629 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 3630 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 3631 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 3632 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 3633 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 3634 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 3635 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 3636 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 3637 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 3638 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 3639 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 3640 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 3641 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 3642 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 3643 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 3644 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 3645 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 3646 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 3647 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 3648 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 3649 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 3650 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 3651 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 3652 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 3653 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 3654 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 3655 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 3656 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 3657 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 3658 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 3659 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 3660 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 3661 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 3662 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 3663 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 3664 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 3665 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 3666 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 3667 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 3668 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 3669 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 3670 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 3671 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 3672 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 3673 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 3674 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 3675 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 3676 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 3677 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 3678 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 3679 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 3680 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 3681 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 3682 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 3683 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 3684 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 3685 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 3686 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 3687 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 3688 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 3689 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 3690 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 3691 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 3692 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 3693 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 3694 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 3695 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 3696 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 3697 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 3698 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 3699 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 3700 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 3701 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 3702 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 3703 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 3704 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, 3705 <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>, 3706 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 3707 <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>, 3708 <GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH>, 3709 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>, 3710 <GIC_SPI 708 IRQ_TYPE_LEVEL_HIGH>, 3711 <GIC_SPI 709 IRQ_TYPE_LEVEL_HIGH>, 3712 <GIC_SPI 710 IRQ_TYPE_LEVEL_HIGH>, 3713 <GIC_SPI 711 IRQ_TYPE_LEVEL_HIGH>, 3714 <GIC_SPI 712 IRQ_TYPE_LEVEL_HIGH>, 3715 <GIC_SPI 713 IRQ_TYPE_LEVEL_HIGH>, 3716 <GIC_SPI 714 IRQ_TYPE_LEVEL_HIGH>, 3717 <GIC_SPI 715 IRQ_TYPE_LEVEL_HIGH>, 3718 <GIC_SPI 643 IRQ_TYPE_LEVEL_HIGH>, 3719 <GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH>, 3720 <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>, 3721 <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH>, 3722 <GIC_SPI 768 IRQ_TYPE_LEVEL_HIGH>, 3723 <GIC_SPI 769 IRQ_TYPE_LEVEL_HIGH>, 3724 <GIC_SPI 770 IRQ_TYPE_LEVEL_HIGH>, 3725 <GIC_SPI 771 IRQ_TYPE_LEVEL_HIGH>, 3726 <GIC_SPI 772 IRQ_TYPE_LEVEL_HIGH>, 3727 <GIC_SPI 773 IRQ_TYPE_LEVEL_HIGH>, 3728 <GIC_SPI 774 IRQ_TYPE_LEVEL_HIGH>, 3729 <GIC_SPI 775 IRQ_TYPE_LEVEL_HIGH>; 3730 dma-coherent; 3731 }; 3732 3733 remoteproc_adsp: remoteproc@17300000 { 3734 compatible = "qcom,sc8180x-adsp-pas"; 3735 reg = <0x0 0x17300000 0x0 0x4040>; 3736 3737 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, 3738 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 3739 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 3740 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 3741 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 3742 interrupt-names = "wdog", "fatal", "ready", 3743 "handover", "stop-ack"; 3744 3745 clocks = <&rpmhcc RPMH_CXO_CLK>; 3746 clock-names = "xo"; 3747 3748 power-domains = <&rpmhpd SC8180X_CX>; 3749 power-domain-names = "cx"; 3750 3751 qcom,qmp = <&aoss_qmp>; 3752 3753 qcom,smem-states = <&adsp_smp2p_out 0>; 3754 qcom,smem-state-names = "stop"; 3755 3756 status = "disabled"; 3757 3758 remoteproc_adsp_glink: glink-edge { 3759 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>; 3760 label = "lpass"; 3761 qcom,remote-pid = <2>; 3762 mboxes = <&apss_shared 8>; 3763 }; 3764 }; 3765 3766 intc: interrupt-controller@17a00000 { 3767 compatible = "arm,gic-v3"; 3768 interrupt-controller; 3769 #address-cells = <0>; 3770 #interrupt-cells = <3>; 3771 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ 3772 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ 3773 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 3774 #redistributor-regions = <1>; 3775 redistributor-stride = <0 0x20000>; 3776 }; 3777 3778 apss_shared: mailbox@17c00000 { 3779 compatible = "qcom,sc8180x-apss-shared", "qcom,sdm845-apss-shared"; 3780 reg = <0x0 0x17c00000 0x0 0x1000>; 3781 #mbox-cells = <1>; 3782 }; 3783 3784 timer@17c20000 { 3785 compatible = "arm,armv7-timer-mem"; 3786 reg = <0x0 0x17c20000 0x0 0x1000>; 3787 3788 #address-cells = <1>; 3789 #size-cells = <1>; 3790 ranges = <0 0 0 0x20000000>; 3791 3792 frame@17c21000 { 3793 reg = <0x17c21000 0x1000>, 3794 <0x17c22000 0x1000>; 3795 frame-number = <0>; 3796 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 3797 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 3798 }; 3799 3800 frame@17c23000 { 3801 reg = <0x17c23000 0x1000>; 3802 frame-number = <1>; 3803 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 3804 status = "disabled"; 3805 }; 3806 3807 frame@17c25000 { 3808 reg = <0x17c25000 0x1000>; 3809 frame-number = <2>; 3810 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 3811 status = "disabled"; 3812 }; 3813 3814 frame@17c27000 { 3815 reg = <0x17c26000 0x1000>; 3816 frame-number = <3>; 3817 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 3818 status = "disabled"; 3819 }; 3820 3821 frame@17c29000 { 3822 reg = <0x17c29000 0x1000>; 3823 frame-number = <4>; 3824 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 3825 status = "disabled"; 3826 }; 3827 3828 frame@17c2b000 { 3829 reg = <0x17c2b000 0x1000>; 3830 frame-number = <5>; 3831 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 3832 status = "disabled"; 3833 }; 3834 3835 frame@17c2d000 { 3836 reg = <0x17c2d000 0x1000>; 3837 frame-number = <6>; 3838 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 3839 status = "disabled"; 3840 }; 3841 }; 3842 3843 apps_rsc: rsc@18200000 { 3844 compatible = "qcom,rpmh-rsc"; 3845 reg = <0x0 0x18200000 0x0 0x10000>, 3846 <0x0 0x18210000 0x0 0x10000>, 3847 <0x0 0x18220000 0x0 0x10000>; 3848 reg-names = "drv-0", "drv-1", "drv-2"; 3849 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 3850 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 3851 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 3852 qcom,tcs-offset = <0xd00>; 3853 qcom,drv-id = <2>; 3854 qcom,tcs-config = <ACTIVE_TCS 2>, 3855 <SLEEP_TCS 1>, 3856 <WAKE_TCS 1>, 3857 <CONTROL_TCS 0>; 3858 label = "apps_rsc"; 3859 power-domains = <&cluster_pd>; 3860 3861 apps_bcm_voter: bcm-voter { 3862 compatible = "qcom,bcm-voter"; 3863 }; 3864 3865 rpmhcc: clock-controller { 3866 compatible = "qcom,sc8180x-rpmh-clk"; 3867 #clock-cells = <1>; 3868 clock-names = "xo"; 3869 clocks = <&xo_board_clk>; 3870 }; 3871 3872 rpmhpd: power-controller { 3873 compatible = "qcom,sc8180x-rpmhpd"; 3874 #power-domain-cells = <1>; 3875 operating-points-v2 = <&rpmhpd_opp_table>; 3876 3877 rpmhpd_opp_table: opp-table { 3878 compatible = "operating-points-v2"; 3879 3880 rpmhpd_opp_ret: opp1 { 3881 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 3882 }; 3883 3884 rpmhpd_opp_min_svs: opp2 { 3885 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 3886 }; 3887 3888 rpmhpd_opp_low_svs: opp3 { 3889 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 3890 }; 3891 3892 rpmhpd_opp_svs: opp4 { 3893 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 3894 }; 3895 3896 rpmhpd_opp_svs_l1: opp5 { 3897 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 3898 }; 3899 3900 rpmhpd_opp_nom: opp6 { 3901 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 3902 }; 3903 3904 rpmhpd_opp_nom_l1: opp7 { 3905 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 3906 }; 3907 3908 rpmhpd_opp_nom_l2: opp8 { 3909 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 3910 }; 3911 3912 rpmhpd_opp_turbo: opp9 { 3913 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 3914 }; 3915 3916 rpmhpd_opp_turbo_l1: opp10 { 3917 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 3918 }; 3919 }; 3920 }; 3921 }; 3922 3923 osm_l3: interconnect@18321000 { 3924 compatible = "qcom,sc8180x-osm-l3", "qcom,osm-l3"; 3925 reg = <0 0x18321000 0 0x1400>; 3926 3927 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 3928 clock-names = "xo", "alternate"; 3929 3930 #interconnect-cells = <1>; 3931 }; 3932 3933 lmh@18350800 { 3934 compatible = "qcom,sc8180x-lmh"; 3935 reg = <0 0x18350800 0 0x400>; 3936 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 3937 cpus = <&cpu4>; 3938 qcom,lmh-temp-arm-millicelsius = <65000>; 3939 qcom,lmh-temp-low-millicelsius = <94500>; 3940 qcom,lmh-temp-high-millicelsius = <95000>; 3941 interrupt-controller; 3942 #interrupt-cells = <1>; 3943 }; 3944 3945 lmh@18358800 { 3946 compatible = "qcom,sc8180x-lmh"; 3947 reg = <0 0x18358800 0 0x400>; 3948 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 3949 cpus = <&cpu0>; 3950 qcom,lmh-temp-arm-millicelsius = <65000>; 3951 qcom,lmh-temp-low-millicelsius = <94500>; 3952 qcom,lmh-temp-high-millicelsius = <95000>; 3953 interrupt-controller; 3954 #interrupt-cells = <1>; 3955 }; 3956 3957 cpufreq_hw: cpufreq@18323000 { 3958 compatible = "qcom,sc8180x-cpufreq-hw", "qcom,cpufreq-hw"; 3959 reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>; 3960 reg-names = "freq-domain0", "freq-domain1"; 3961 3962 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 3963 clock-names = "xo", "alternate"; 3964 3965 #freq-domain-cells = <1>; 3966 #clock-cells = <1>; 3967 }; 3968 3969 wifi: wifi@18800000 { 3970 compatible = "qcom,wcn3990-wifi"; 3971 reg = <0 0x18800000 0 0x800000>; 3972 reg-names = "membase"; 3973 clock-names = "cxo_ref_clk_pin"; 3974 clocks = <&rpmhcc RPMH_RF_CLK2>; 3975 interrupts = <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>, 3976 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>, 3977 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, 3978 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>, 3979 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 3980 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 3981 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 3982 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 3983 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 3984 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 3985 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 3986 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>; 3987 iommus = <&apps_smmu 0x0640 0x1>; 3988 qcom,msa-fixed-perm; 3989 status = "disabled"; 3990 }; 3991 }; 3992 3993 thermal-zones { 3994 cpu0-thermal { 3995 polling-delay-passive = <250>; 3996 3997 thermal-sensors = <&tsens0 1>; 3998 3999 trips { 4000 cpu-crit { 4001 temperature = <110000>; 4002 hysteresis = <1000>; 4003 type = "critical"; 4004 }; 4005 }; 4006 }; 4007 4008 cpu1-thermal { 4009 polling-delay-passive = <250>; 4010 4011 thermal-sensors = <&tsens0 2>; 4012 4013 trips { 4014 cpu-crit { 4015 temperature = <110000>; 4016 hysteresis = <1000>; 4017 type = "critical"; 4018 }; 4019 }; 4020 }; 4021 4022 cpu2-thermal { 4023 polling-delay-passive = <250>; 4024 4025 thermal-sensors = <&tsens0 3>; 4026 4027 trips { 4028 cpu-crit { 4029 temperature = <110000>; 4030 hysteresis = <1000>; 4031 type = "critical"; 4032 }; 4033 }; 4034 }; 4035 4036 cpu3-thermal { 4037 polling-delay-passive = <250>; 4038 4039 thermal-sensors = <&tsens0 4>; 4040 4041 trips { 4042 cpu-crit { 4043 temperature = <110000>; 4044 hysteresis = <1000>; 4045 type = "critical"; 4046 }; 4047 }; 4048 }; 4049 4050 cpu4-top-thermal { 4051 polling-delay-passive = <250>; 4052 4053 thermal-sensors = <&tsens0 7>; 4054 4055 trips { 4056 cpu-crit { 4057 temperature = <110000>; 4058 hysteresis = <1000>; 4059 type = "critical"; 4060 }; 4061 }; 4062 }; 4063 4064 cpu5-top-thermal { 4065 polling-delay-passive = <250>; 4066 4067 thermal-sensors = <&tsens0 8>; 4068 4069 trips { 4070 cpu-crit { 4071 temperature = <110000>; 4072 hysteresis = <1000>; 4073 type = "critical"; 4074 }; 4075 }; 4076 }; 4077 4078 cpu6-top-thermal { 4079 polling-delay-passive = <250>; 4080 4081 thermal-sensors = <&tsens0 9>; 4082 4083 trips { 4084 cpu-crit { 4085 temperature = <110000>; 4086 hysteresis = <1000>; 4087 type = "critical"; 4088 }; 4089 }; 4090 }; 4091 4092 cpu7-top-thermal { 4093 polling-delay-passive = <250>; 4094 4095 thermal-sensors = <&tsens0 10>; 4096 4097 trips { 4098 cpu-crit { 4099 temperature = <110000>; 4100 hysteresis = <1000>; 4101 type = "critical"; 4102 }; 4103 }; 4104 }; 4105 4106 cpu4-bottom-thermal { 4107 polling-delay-passive = <250>; 4108 4109 thermal-sensors = <&tsens0 11>; 4110 4111 trips { 4112 cpu-crit { 4113 temperature = <110000>; 4114 hysteresis = <1000>; 4115 type = "critical"; 4116 }; 4117 }; 4118 }; 4119 4120 cpu5-bottom-thermal { 4121 polling-delay-passive = <250>; 4122 4123 thermal-sensors = <&tsens0 12>; 4124 4125 trips { 4126 cpu-crit { 4127 temperature = <110000>; 4128 hysteresis = <1000>; 4129 type = "critical"; 4130 }; 4131 }; 4132 }; 4133 4134 cpu6-bottom-thermal { 4135 polling-delay-passive = <250>; 4136 4137 thermal-sensors = <&tsens0 13>; 4138 4139 trips { 4140 cpu-crit { 4141 temperature = <110000>; 4142 hysteresis = <1000>; 4143 type = "critical"; 4144 }; 4145 }; 4146 }; 4147 4148 cpu7-bottom-thermal { 4149 polling-delay-passive = <250>; 4150 4151 thermal-sensors = <&tsens0 14>; 4152 4153 trips { 4154 cpu-crit { 4155 temperature = <110000>; 4156 hysteresis = <1000>; 4157 type = "critical"; 4158 }; 4159 }; 4160 }; 4161 4162 aoss0-thermal { 4163 polling-delay-passive = <250>; 4164 4165 thermal-sensors = <&tsens0 0>; 4166 4167 trips { 4168 trip-point0 { 4169 temperature = <90000>; 4170 hysteresis = <2000>; 4171 type = "hot"; 4172 }; 4173 }; 4174 }; 4175 4176 cluster0-thermal { 4177 polling-delay-passive = <250>; 4178 4179 thermal-sensors = <&tsens0 5>; 4180 4181 trips { 4182 cluster-crit { 4183 temperature = <110000>; 4184 hysteresis = <2000>; 4185 type = "critical"; 4186 }; 4187 }; 4188 }; 4189 4190 cluster1-thermal { 4191 polling-delay-passive = <250>; 4192 4193 thermal-sensors = <&tsens0 6>; 4194 4195 trips { 4196 cluster-crit { 4197 temperature = <110000>; 4198 hysteresis = <2000>; 4199 type = "critical"; 4200 }; 4201 }; 4202 }; 4203 4204 gpu-top-thermal { 4205 polling-delay-passive = <250>; 4206 4207 thermal-sensors = <&tsens0 15>; 4208 4209 cooling-maps { 4210 map0 { 4211 trip = <&gpu_top_alert0>; 4212 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4213 }; 4214 }; 4215 4216 trips { 4217 gpu_top_alert0: trip-point0 { 4218 temperature = <85000>; 4219 hysteresis = <1000>; 4220 type = "passive"; 4221 }; 4222 4223 trip-point1 { 4224 temperature = <90000>; 4225 hysteresis = <1000>; 4226 type = "hot"; 4227 }; 4228 4229 trip-point2 { 4230 temperature = <110000>; 4231 hysteresis = <1000>; 4232 type = "critical"; 4233 }; 4234 }; 4235 }; 4236 4237 aoss1-thermal { 4238 polling-delay-passive = <250>; 4239 4240 thermal-sensors = <&tsens1 0>; 4241 4242 trips { 4243 trip-point0 { 4244 temperature = <90000>; 4245 hysteresis = <2000>; 4246 type = "hot"; 4247 }; 4248 }; 4249 }; 4250 4251 wlan-thermal { 4252 polling-delay-passive = <250>; 4253 4254 thermal-sensors = <&tsens1 1>; 4255 4256 trips { 4257 trip-point0 { 4258 temperature = <90000>; 4259 hysteresis = <2000>; 4260 type = "hot"; 4261 }; 4262 }; 4263 }; 4264 4265 video-thermal { 4266 polling-delay-passive = <250>; 4267 4268 thermal-sensors = <&tsens1 2>; 4269 4270 trips { 4271 trip-point0 { 4272 temperature = <90000>; 4273 hysteresis = <2000>; 4274 type = "hot"; 4275 }; 4276 }; 4277 }; 4278 4279 mem-thermal { 4280 polling-delay-passive = <250>; 4281 4282 thermal-sensors = <&tsens1 3>; 4283 4284 trips { 4285 trip-point0 { 4286 temperature = <90000>; 4287 hysteresis = <2000>; 4288 type = "hot"; 4289 }; 4290 }; 4291 }; 4292 4293 q6-hvx-thermal { 4294 polling-delay-passive = <250>; 4295 4296 thermal-sensors = <&tsens1 4>; 4297 4298 trips { 4299 trip-point0 { 4300 temperature = <90000>; 4301 hysteresis = <2000>; 4302 type = "hot"; 4303 }; 4304 }; 4305 }; 4306 4307 camera-thermal { 4308 polling-delay-passive = <250>; 4309 4310 thermal-sensors = <&tsens1 5>; 4311 4312 trips { 4313 trip-point0 { 4314 temperature = <90000>; 4315 hysteresis = <2000>; 4316 type = "hot"; 4317 }; 4318 }; 4319 }; 4320 4321 compute-thermal { 4322 polling-delay-passive = <250>; 4323 4324 thermal-sensors = <&tsens1 6>; 4325 4326 trips { 4327 trip-point0 { 4328 temperature = <90000>; 4329 hysteresis = <2000>; 4330 type = "hot"; 4331 }; 4332 }; 4333 }; 4334 4335 mdm-dsp-thermal { 4336 polling-delay-passive = <250>; 4337 4338 thermal-sensors = <&tsens1 7>; 4339 4340 trips { 4341 trip-point0 { 4342 temperature = <90000>; 4343 hysteresis = <2000>; 4344 type = "hot"; 4345 }; 4346 }; 4347 }; 4348 4349 npu-thermal { 4350 polling-delay-passive = <250>; 4351 4352 thermal-sensors = <&tsens1 8>; 4353 4354 trips { 4355 trip-point0 { 4356 temperature = <90000>; 4357 hysteresis = <2000>; 4358 type = "hot"; 4359 }; 4360 }; 4361 }; 4362 4363 gpu-bottom-thermal { 4364 polling-delay-passive = <250>; 4365 4366 thermal-sensors = <&tsens1 11>; 4367 4368 cooling-maps { 4369 map0 { 4370 trip = <&gpu_bottom_alert0>; 4371 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4372 }; 4373 }; 4374 4375 trips { 4376 gpu_bottom_alert0: trip-point0 { 4377 temperature = <85000>; 4378 hysteresis = <1000>; 4379 type = "passive"; 4380 }; 4381 4382 trip-point1 { 4383 temperature = <90000>; 4384 hysteresis = <1000>; 4385 type = "hot"; 4386 }; 4387 4388 trip-point2 { 4389 temperature = <110000>; 4390 hysteresis = <1000>; 4391 type = "critical"; 4392 }; 4393 }; 4394 }; 4395 }; 4396 4397 timer { 4398 compatible = "arm,armv8-timer"; 4399 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>, 4400 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>, 4401 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>, 4402 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>; 4403 }; 4404}; 4405