1 /*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21
22 /*
23 * Copyright 2009 Sun Microsystems, Inc. All rights reserved.
24 * Use is subject to license terms.
25 */
26
27 /*
28 * Copyright (c) 2018, Joyent, Inc.
29 */
30
31 #include "nge.h"
32 static uint32_t nge_watchdog_count = 1 << 5;
33 static uint32_t nge_watchdog_check = 1 << 3;
34 extern boolean_t nge_enable_msi;
35 static void nge_sync_mac_modes(nge_t *);
36
37 #undef NGE_DBG
38 #define NGE_DBG NGE_DBG_CHIP
39
40 /*
41 * Operating register get/set access routines
42 */
43 uint8_t nge_reg_get8(nge_t *ngep, nge_regno_t regno);
44
45 uint8_t
nge_reg_get8(nge_t * ngep,nge_regno_t regno)46 nge_reg_get8(nge_t *ngep, nge_regno_t regno)
47 {
48 NGE_TRACE(("nge_reg_get8($%p, 0x%lx)", (void *)ngep, regno));
49
50 return (ddi_get8(ngep->io_handle, PIO_ADDR(ngep, regno)));
51 }
52
53 void nge_reg_put8(nge_t *ngep, nge_regno_t regno, uint8_t data);
54
55 void
nge_reg_put8(nge_t * ngep,nge_regno_t regno,uint8_t data)56 nge_reg_put8(nge_t *ngep, nge_regno_t regno, uint8_t data)
57 {
58 NGE_TRACE(("nge_reg_put8($%p, 0x%lx, 0x%x)",
59 (void *)ngep, regno, data));
60 ddi_put8(ngep->io_handle, PIO_ADDR(ngep, regno), data);
61
62 }
63
64 uint16_t nge_reg_get16(nge_t *ngep, nge_regno_t regno);
65
66 uint16_t
nge_reg_get16(nge_t * ngep,nge_regno_t regno)67 nge_reg_get16(nge_t *ngep, nge_regno_t regno)
68 {
69 NGE_TRACE(("nge_reg_get16($%p, 0x%lx)", (void *)ngep, regno));
70 return (ddi_get16(ngep->io_handle, PIO_ADDR(ngep, regno)));
71 }
72
73 void nge_reg_put16(nge_t *ngep, nge_regno_t regno, uint16_t data);
74
75 void
nge_reg_put16(nge_t * ngep,nge_regno_t regno,uint16_t data)76 nge_reg_put16(nge_t *ngep, nge_regno_t regno, uint16_t data)
77 {
78 NGE_TRACE(("nge_reg_put16($%p, 0x%lx, 0x%x)",
79 (void *)ngep, regno, data));
80 ddi_put16(ngep->io_handle, PIO_ADDR(ngep, regno), data);
81
82 }
83
84 uint32_t nge_reg_get32(nge_t *ngep, nge_regno_t regno);
85
86 uint32_t
nge_reg_get32(nge_t * ngep,nge_regno_t regno)87 nge_reg_get32(nge_t *ngep, nge_regno_t regno)
88 {
89 NGE_TRACE(("nge_reg_get32($%p, 0x%lx)", (void *)ngep, regno));
90 return (ddi_get32(ngep->io_handle, PIO_ADDR(ngep, regno)));
91 }
92
93 void nge_reg_put32(nge_t *ngep, nge_regno_t regno, uint32_t data);
94
95 void
nge_reg_put32(nge_t * ngep,nge_regno_t regno,uint32_t data)96 nge_reg_put32(nge_t *ngep, nge_regno_t regno, uint32_t data)
97 {
98 NGE_TRACE(("nge_reg_put32($%p, 0x%lx, 0x%x)",
99 (void *)ngep, regno, data));
100 ddi_put32(ngep->io_handle, PIO_ADDR(ngep, regno), data);
101
102 }
103
104 #if NGE_DEBUGGING
105 static int nge_chip_peek_cfg(nge_t *ngep, nge_peekpoke_t *ppd);
106
107 static int
nge_chip_peek_cfg(nge_t * ngep,nge_peekpoke_t * ppd)108 nge_chip_peek_cfg(nge_t *ngep, nge_peekpoke_t *ppd)
109 {
110 int err;
111 uint64_t regval;
112 uint64_t regno;
113
114 NGE_TRACE(("nge_chip_peek_cfg($%p, $%p)",
115 (void *)ngep, (void *)ppd));
116
117 err = DDI_SUCCESS;
118 regno = ppd->pp_acc_offset;
119
120 switch (ppd->pp_acc_size) {
121 case 1:
122 regval = pci_config_get8(ngep->cfg_handle, regno);
123 break;
124
125 case 2:
126 regval = pci_config_get16(ngep->cfg_handle, regno);
127 break;
128
129 case 4:
130 regval = pci_config_get32(ngep->cfg_handle, regno);
131 break;
132
133 case 8:
134 regval = pci_config_get64(ngep->cfg_handle, regno);
135 break;
136 }
137 ppd->pp_acc_data = regval;
138 return (err);
139 }
140
141 static int nge_chip_poke_cfg(nge_t *ngep, nge_peekpoke_t *ppd);
142
143 static int
nge_chip_poke_cfg(nge_t * ngep,nge_peekpoke_t * ppd)144 nge_chip_poke_cfg(nge_t *ngep, nge_peekpoke_t *ppd)
145 {
146 int err;
147 uint64_t regval;
148 uint64_t regno;
149
150 NGE_TRACE(("nge_chip_poke_cfg($%p, $%p)",
151 (void *)ngep, (void *)ppd));
152
153 err = DDI_SUCCESS;
154 regno = ppd->pp_acc_offset;
155 regval = ppd->pp_acc_data;
156
157 switch (ppd->pp_acc_size) {
158 case 1:
159 pci_config_put8(ngep->cfg_handle, regno, regval);
160 break;
161
162 case 2:
163 pci_config_put16(ngep->cfg_handle, regno, regval);
164 break;
165
166 case 4:
167 pci_config_put32(ngep->cfg_handle, regno, regval);
168 break;
169
170 case 8:
171 pci_config_put64(ngep->cfg_handle, regno, regval);
172 break;
173 }
174
175 return (err);
176
177 }
178
179 static int nge_chip_peek_reg(nge_t *ngep, nge_peekpoke_t *ppd);
180
181 static int
nge_chip_peek_reg(nge_t * ngep,nge_peekpoke_t * ppd)182 nge_chip_peek_reg(nge_t *ngep, nge_peekpoke_t *ppd)
183 {
184 int err;
185 uint64_t regval;
186 void *regaddr;
187
188 NGE_TRACE(("nge_chip_peek_reg($%p, $%p)",
189 (void *)ngep, (void *)ppd));
190
191 err = DDI_SUCCESS;
192 regaddr = PIO_ADDR(ngep, ppd->pp_acc_offset);
193
194 switch (ppd->pp_acc_size) {
195 case 1:
196 regval = ddi_get8(ngep->io_handle, regaddr);
197 break;
198
199 case 2:
200 regval = ddi_get16(ngep->io_handle, regaddr);
201 break;
202
203 case 4:
204 regval = ddi_get32(ngep->io_handle, regaddr);
205 break;
206
207 case 8:
208 regval = ddi_get64(ngep->io_handle, regaddr);
209 break;
210
211 default:
212 regval = 0x0ull;
213 break;
214 }
215 ppd->pp_acc_data = regval;
216 return (err);
217 }
218
219 static int nge_chip_poke_reg(nge_t *ngep, nge_peekpoke_t *ppd);
220
221 static int
nge_chip_poke_reg(nge_t * ngep,nge_peekpoke_t * ppd)222 nge_chip_poke_reg(nge_t *ngep, nge_peekpoke_t *ppd)
223 {
224 int err;
225 uint64_t regval;
226 void *regaddr;
227
228 NGE_TRACE(("nge_chip_poke_reg($%p, $%p)",
229 (void *)ngep, (void *)ppd));
230
231 err = DDI_SUCCESS;
232 regaddr = PIO_ADDR(ngep, ppd->pp_acc_offset);
233 regval = ppd->pp_acc_data;
234
235 switch (ppd->pp_acc_size) {
236 case 1:
237 ddi_put8(ngep->io_handle, regaddr, regval);
238 break;
239
240 case 2:
241 ddi_put16(ngep->io_handle, regaddr, regval);
242 break;
243
244 case 4:
245 ddi_put32(ngep->io_handle, regaddr, regval);
246 break;
247
248 case 8:
249 ddi_put64(ngep->io_handle, regaddr, regval);
250 break;
251 }
252 return (err);
253 }
254
255 static int nge_chip_peek_mii(nge_t *ngep, nge_peekpoke_t *ppd);
256
257 static int
nge_chip_peek_mii(nge_t * ngep,nge_peekpoke_t * ppd)258 nge_chip_peek_mii(nge_t *ngep, nge_peekpoke_t *ppd)
259 {
260 int err;
261
262 err = DDI_SUCCESS;
263 ppd->pp_acc_data = nge_mii_get16(ngep, ppd->pp_acc_offset/2);
264 return (err);
265 }
266
267 static int nge_chip_poke_mii(nge_t *ngep, nge_peekpoke_t *ppd);
268
269 static int
nge_chip_poke_mii(nge_t * ngep,nge_peekpoke_t * ppd)270 nge_chip_poke_mii(nge_t *ngep, nge_peekpoke_t *ppd)
271 {
272 int err;
273 err = DDI_SUCCESS;
274 nge_mii_put16(ngep, ppd->pp_acc_offset/2, ppd->pp_acc_data);
275 return (err);
276 }
277
278 /*
279 * Basic SEEPROM get/set access routine
280 *
281 * This uses the chip's SEEPROM auto-access method, controlled by the
282 * Serial EEPROM Address/Data Registers at 0x504h, so the CPU
283 * doesn't have to fiddle with the individual bits.
284 *
285 * The caller should hold <genlock> and *also* have already acquired
286 * the right to access the SEEPROM.
287 *
288 * Return value:
289 * 0 on success,
290 * ENODATA on access timeout (maybe retryable: device may just be busy)
291 * EPROTO on other h/w or s/w errors.
292 *
293 * <*dp> is an input to a SEEPROM_ACCESS_WRITE operation, or an output
294 * from a (successful) SEEPROM_ACCESS_READ.
295 */
296
297 static int
nge_seeprom_access(nge_t * ngep,uint32_t cmd,nge_regno_t addr,uint16_t * dp)298 nge_seeprom_access(nge_t *ngep, uint32_t cmd, nge_regno_t addr, uint16_t *dp)
299 {
300 uint32_t tries;
301 nge_ep_cmd cmd_reg;
302 nge_ep_data data_reg;
303
304 NGE_TRACE(("nge_seeprom_access($%p, %d, %x, $%p)",
305 (void *)ngep, cmd, addr, (void *)dp));
306
307 ASSERT(mutex_owned(ngep->genlock));
308
309 /*
310 * Check there's no command in progress.
311 *
312 * Note: this *shouldn't* ever find that there is a command
313 * in progress, because we already hold the <genlock> mutex.
314 * Also, to ensure we don't have a conflict with the chip's
315 * internal firmware or a process accessing the same (shared)
316 * So this is just a final consistency check: we shouldn't
317 * see EITHER the START bit (command started but not complete)
318 * OR the COMPLETE bit (command completed but not cleared).
319 */
320 cmd_reg.cmd_val = nge_reg_get32(ngep, NGE_EP_CMD);
321 for (tries = 0; tries < 30; tries++) {
322 if (cmd_reg.cmd_bits.sts == SEEPROM_READY)
323 break;
324 drv_usecwait(10);
325 cmd_reg.cmd_val = nge_reg_get32(ngep, NGE_EP_CMD);
326 }
327
328 /*
329 * This should not happen. If so, we have to restart eeprom
330 * state machine
331 */
332 if (tries == 30) {
333 cmd_reg.cmd_bits.sts = SEEPROM_READY;
334 nge_reg_put32(ngep, NGE_EP_CMD, cmd_reg.cmd_val);
335 drv_usecwait(10);
336 /*
337 * Polling the status bit to make assure the eeprom is ready
338 */
339 cmd_reg.cmd_val = nge_reg_get32(ngep, NGE_EP_CMD);
340 for (tries = 0; tries < 30; tries++) {
341 if (cmd_reg.cmd_bits.sts == SEEPROM_READY)
342 break;
343 drv_usecwait(10);
344 cmd_reg.cmd_val = nge_reg_get32(ngep, NGE_EP_CMD);
345 }
346 }
347
348 /*
349 * Assemble the command ...
350 */
351 cmd_reg.cmd_bits.addr = (uint32_t)addr;
352 cmd_reg.cmd_bits.cmd = cmd;
353 cmd_reg.cmd_bits.sts = 0;
354
355 nge_reg_put32(ngep, NGE_EP_CMD, cmd_reg.cmd_val);
356
357 /*
358 * Polling whether the access is successful.
359 *
360 */
361 cmd_reg.cmd_val = nge_reg_get32(ngep, NGE_EP_CMD);
362 for (tries = 0; tries < 30; tries++) {
363 if (cmd_reg.cmd_bits.sts == SEEPROM_READY)
364 break;
365 drv_usecwait(10);
366 cmd_reg.cmd_val = nge_reg_get32(ngep, NGE_EP_CMD);
367 }
368
369 if (tries == 30) {
370 nge_report(ngep, NGE_HW_ROM);
371 return (DDI_FAILURE);
372 }
373 switch (cmd) {
374 default:
375 case SEEPROM_CMD_WRITE_ENABLE:
376 case SEEPROM_CMD_ERASE:
377 case SEEPROM_CMD_ERALSE_ALL:
378 case SEEPROM_CMD_WRITE_DIS:
379 break;
380
381 case SEEPROM_CMD_READ:
382 data_reg.data_val = nge_reg_get32(ngep, NGE_EP_DATA);
383 *dp = data_reg.data_bits.data;
384 break;
385
386 case SEEPROM_CMD_WRITE:
387 data_reg.data_val = nge_reg_get32(ngep, NGE_EP_DATA);
388 data_reg.data_bits.data = *dp;
389 nge_reg_put32(ngep, NGE_EP_DATA, data_reg.data_val);
390 break;
391 }
392
393 return (DDI_SUCCESS);
394 }
395
396
397 static int
nge_chip_peek_seeprom(nge_t * ngep,nge_peekpoke_t * ppd)398 nge_chip_peek_seeprom(nge_t *ngep, nge_peekpoke_t *ppd)
399 {
400 uint16_t data;
401 int err;
402
403 err = nge_seeprom_access(ngep, SEEPROM_CMD_READ,
404 ppd->pp_acc_offset, &data);
405 ppd->pp_acc_data = data;
406 return (err);
407 }
408
409 static int
nge_chip_poke_seeprom(nge_t * ngep,nge_peekpoke_t * ppd)410 nge_chip_poke_seeprom(nge_t *ngep, nge_peekpoke_t *ppd)
411 {
412 uint16_t data;
413 int err;
414
415 data = ppd->pp_acc_data;
416 err = nge_seeprom_access(ngep, SEEPROM_CMD_WRITE,
417 ppd->pp_acc_offset, &data);
418 return (err);
419 }
420 #endif /* NGE_DEBUGGING */
421
422 void
nge_init_dev_spec_param(nge_t * ngep)423 nge_init_dev_spec_param(nge_t *ngep)
424 {
425 nge_dev_spec_param_t *dev_param_p;
426 chip_info_t *infop;
427
428 dev_param_p = &ngep->dev_spec_param;
429 infop = (chip_info_t *)&ngep->chipinfo;
430
431 switch (infop->device) {
432 case DEVICE_ID_NF3_E6:
433 case DEVICE_ID_NF3_DF:
434 case DEVICE_ID_MCP04_37:
435 case DEVICE_ID_MCP04_38:
436 dev_param_p->msi = B_FALSE;
437 dev_param_p->msi_x = B_FALSE;
438 dev_param_p->vlan = B_FALSE;
439 dev_param_p->advanced_pm = B_FALSE;
440 dev_param_p->mac_addr_order = B_FALSE;
441 dev_param_p->tx_pause_frame = B_FALSE;
442 dev_param_p->rx_pause_frame = B_FALSE;
443 dev_param_p->jumbo = B_FALSE;
444 dev_param_p->tx_rx_64byte = B_FALSE;
445 dev_param_p->rx_hw_checksum = B_FALSE;
446 dev_param_p->tx_hw_checksum = 0;
447 dev_param_p->desc_type = DESC_OFFLOAD;
448 dev_param_p->rx_desc_num = NGE_RECV_SLOTS_DESC_1024;
449 dev_param_p->tx_desc_num = NGE_SEND_SLOTS_DESC_1024;
450 dev_param_p->nge_split = NGE_SPLIT_32;
451 break;
452
453 case DEVICE_ID_CK804_56:
454 case DEVICE_ID_CK804_57:
455 dev_param_p->msi = B_TRUE;
456 dev_param_p->msi_x = B_TRUE;
457 dev_param_p->vlan = B_FALSE;
458 dev_param_p->advanced_pm = B_FALSE;
459 dev_param_p->mac_addr_order = B_FALSE;
460 dev_param_p->tx_pause_frame = B_FALSE;
461 dev_param_p->rx_pause_frame = B_TRUE;
462 dev_param_p->jumbo = B_TRUE;
463 dev_param_p->tx_rx_64byte = B_FALSE;
464 dev_param_p->rx_hw_checksum = B_TRUE;
465 dev_param_p->tx_hw_checksum = HCKSUM_IPHDRCKSUM;
466 dev_param_p->desc_type = DESC_HOT;
467 dev_param_p->rx_desc_num = NGE_RECV_SLOTS_DESC_3072;
468 dev_param_p->tx_desc_num = NGE_SEND_SLOTS_DESC_3072;
469 dev_param_p->nge_split = NGE_SPLIT_96;
470 break;
471
472 case DEVICE_ID_MCP51_268:
473 case DEVICE_ID_MCP51_269:
474 dev_param_p->msi = B_FALSE;
475 dev_param_p->msi_x = B_FALSE;
476 dev_param_p->vlan = B_FALSE;
477 dev_param_p->advanced_pm = B_TRUE;
478 dev_param_p->mac_addr_order = B_FALSE;
479 dev_param_p->tx_pause_frame = B_FALSE;
480 dev_param_p->rx_pause_frame = B_FALSE;
481 dev_param_p->jumbo = B_FALSE;
482 dev_param_p->tx_rx_64byte = B_TRUE;
483 dev_param_p->rx_hw_checksum = B_FALSE;
484 dev_param_p->tx_hw_checksum = 0;
485 dev_param_p->desc_type = DESC_OFFLOAD;
486 dev_param_p->rx_desc_num = NGE_RECV_SLOTS_DESC_1024;
487 dev_param_p->tx_desc_num = NGE_SEND_SLOTS_DESC_1024;
488 dev_param_p->nge_split = NGE_SPLIT_32;
489 break;
490
491 case DEVICE_ID_MCP55_372:
492 case DEVICE_ID_MCP55_373:
493 dev_param_p->msi = B_TRUE;
494 dev_param_p->msi_x = B_TRUE;
495 dev_param_p->vlan = B_TRUE;
496 dev_param_p->advanced_pm = B_TRUE;
497 dev_param_p->mac_addr_order = B_FALSE;
498 dev_param_p->tx_pause_frame = B_TRUE;
499 dev_param_p->rx_pause_frame = B_TRUE;
500 dev_param_p->jumbo = B_TRUE;
501 dev_param_p->tx_rx_64byte = B_TRUE;
502 dev_param_p->rx_hw_checksum = B_TRUE;
503 dev_param_p->tx_hw_checksum = HCKSUM_IPHDRCKSUM;
504 dev_param_p->desc_type = DESC_HOT;
505 dev_param_p->rx_desc_num = NGE_RECV_SLOTS_DESC_3072;
506 dev_param_p->tx_desc_num = NGE_SEND_SLOTS_DESC_3072;
507 dev_param_p->nge_split = NGE_SPLIT_96;
508 break;
509
510 case DEVICE_ID_MCP61_3EE:
511 case DEVICE_ID_MCP61_3EF:
512 dev_param_p->msi = B_FALSE;
513 dev_param_p->msi_x = B_FALSE;
514 dev_param_p->vlan = B_FALSE;
515 dev_param_p->advanced_pm = B_TRUE;
516 dev_param_p->mac_addr_order = B_TRUE;
517 dev_param_p->tx_pause_frame = B_FALSE;
518 dev_param_p->rx_pause_frame = B_FALSE;
519 dev_param_p->jumbo = B_FALSE;
520 dev_param_p->tx_rx_64byte = B_TRUE;
521 dev_param_p->rx_hw_checksum = B_FALSE;
522 dev_param_p->tx_hw_checksum = 0;
523 dev_param_p->desc_type = DESC_OFFLOAD;
524 dev_param_p->rx_desc_num = NGE_RECV_SLOTS_DESC_1024;
525 dev_param_p->tx_desc_num = NGE_SEND_SLOTS_DESC_1024;
526 dev_param_p->nge_split = NGE_SPLIT_32;
527 break;
528
529 case DEVICE_ID_MCP77_760:
530 case DEVICE_ID_MCP79_AB0:
531 dev_param_p->msi = B_FALSE;
532 dev_param_p->msi_x = B_FALSE;
533 dev_param_p->vlan = B_FALSE;
534 dev_param_p->advanced_pm = B_TRUE;
535 dev_param_p->mac_addr_order = B_TRUE;
536 dev_param_p->tx_pause_frame = B_FALSE;
537 dev_param_p->rx_pause_frame = B_FALSE;
538 dev_param_p->jumbo = B_FALSE;
539 dev_param_p->tx_rx_64byte = B_TRUE;
540 dev_param_p->rx_hw_checksum = B_FALSE;
541 dev_param_p->tx_hw_checksum = 0;
542 dev_param_p->desc_type = DESC_HOT;
543 dev_param_p->rx_desc_num = NGE_RECV_SLOTS_DESC_1024;
544 dev_param_p->tx_desc_num = NGE_SEND_SLOTS_DESC_1024;
545 dev_param_p->nge_split = NGE_SPLIT_32;
546 break;
547
548 default:
549 dev_param_p->msi = B_FALSE;
550 dev_param_p->msi_x = B_FALSE;
551 dev_param_p->vlan = B_FALSE;
552 dev_param_p->advanced_pm = B_FALSE;
553 dev_param_p->mac_addr_order = B_FALSE;
554 dev_param_p->tx_pause_frame = B_FALSE;
555 dev_param_p->rx_pause_frame = B_FALSE;
556 dev_param_p->jumbo = B_FALSE;
557 dev_param_p->tx_rx_64byte = B_FALSE;
558 dev_param_p->rx_hw_checksum = B_FALSE;
559 dev_param_p->tx_hw_checksum = 0;
560 dev_param_p->desc_type = DESC_OFFLOAD;
561 dev_param_p->rx_desc_num = NGE_RECV_SLOTS_DESC_1024;
562 dev_param_p->tx_desc_num = NGE_SEND_SLOTS_DESC_1024;
563 dev_param_p->nge_split = NGE_SPLIT_32;
564 return;
565 }
566 }
567 /*
568 * Perform first-stage chip (re-)initialisation, using only config-space
569 * accesses:
570 *
571 * + Read the vendor/device/revision/subsystem/cache-line-size registers,
572 * returning the data in the structure pointed to by <infop>.
573 */
574 void nge_chip_cfg_init(nge_t *ngep, chip_info_t *infop, boolean_t reset);
575
576 void
nge_chip_cfg_init(nge_t * ngep,chip_info_t * infop,boolean_t reset)577 nge_chip_cfg_init(nge_t *ngep, chip_info_t *infop, boolean_t reset)
578 {
579 uint16_t command;
580 ddi_acc_handle_t handle;
581 nge_interbus_conf interbus_conf;
582 nge_msi_mask_conf msi_mask_conf;
583 nge_msi_map_cap_conf cap_conf;
584
585 NGE_TRACE(("nge_chip_cfg_init($%p, $%p, %d)",
586 (void *)ngep, (void *)infop, reset));
587
588 /*
589 * save PCI cache line size and subsystem vendor ID
590 *
591 * Read all the config-space registers that characterise the
592 * chip, specifically vendor/device/revision/subsystem vendor
593 * and subsystem device id. We expect (but don't check) that
594 */
595 handle = ngep->cfg_handle;
596 /* reading the vendor information once */
597 if (reset == B_FALSE) {
598 infop->command = pci_config_get16(handle,
599 PCI_CONF_COMM);
600 infop->vendor = pci_config_get16(handle,
601 PCI_CONF_VENID);
602 infop->device = pci_config_get16(handle,
603 PCI_CONF_DEVID);
604 infop->subven = pci_config_get16(handle,
605 PCI_CONF_SUBVENID);
606 infop->subdev = pci_config_get16(handle,
607 PCI_CONF_SUBSYSID);
608 infop->class_code = pci_config_get8(handle,
609 PCI_CONF_BASCLASS);
610 infop->revision = pci_config_get8(handle,
611 PCI_CONF_REVID);
612 infop->clsize = pci_config_get8(handle,
613 PCI_CONF_CACHE_LINESZ);
614 infop->latency = pci_config_get8(handle,
615 PCI_CONF_LATENCY_TIMER);
616 }
617 if (nge_enable_msi) {
618 /* Disable the hidden for MSI support */
619 interbus_conf.conf_val = pci_config_get32(handle,
620 PCI_CONF_HT_INTERNAL);
621 if ((infop->device == DEVICE_ID_MCP55_373) ||
622 (infop->device == DEVICE_ID_MCP55_372))
623 interbus_conf.conf_bits.msix_off = NGE_SET;
624 interbus_conf.conf_bits.msi_off = NGE_CLEAR;
625 pci_config_put32(handle, PCI_CONF_HT_INTERNAL,
626 interbus_conf.conf_val);
627
628 if ((infop->device == DEVICE_ID_MCP55_373) ||
629 (infop->device == DEVICE_ID_MCP55_372)) {
630
631 /* Disable the vector off for mcp55 */
632 msi_mask_conf.msi_mask_conf_val =
633 pci_config_get32(handle, PCI_CONF_HT_MSI_MASK);
634 msi_mask_conf.msi_mask_bits.vec0_off = NGE_CLEAR;
635 msi_mask_conf.msi_mask_bits.vec1_off = NGE_CLEAR;
636 msi_mask_conf.msi_mask_bits.vec2_off = NGE_CLEAR;
637 msi_mask_conf.msi_mask_bits.vec3_off = NGE_CLEAR;
638 msi_mask_conf.msi_mask_bits.vec4_off = NGE_CLEAR;
639 msi_mask_conf.msi_mask_bits.vec5_off = NGE_CLEAR;
640 msi_mask_conf.msi_mask_bits.vec6_off = NGE_CLEAR;
641 msi_mask_conf.msi_mask_bits.vec7_off = NGE_CLEAR;
642 pci_config_put32(handle, PCI_CONF_HT_MSI_MASK,
643 msi_mask_conf.msi_mask_conf_val);
644
645 /* Enable the MSI mapping */
646 cap_conf.msi_map_cap_conf_val =
647 pci_config_get32(handle, PCI_CONF_HT_MSI_MAP_CAP);
648 cap_conf.map_cap_conf_bits.map_en = NGE_SET;
649 pci_config_put32(handle, PCI_CONF_HT_MSI_MAP_CAP,
650 cap_conf.msi_map_cap_conf_val);
651 }
652 } else {
653 interbus_conf.conf_val = pci_config_get32(handle,
654 PCI_CONF_HT_INTERNAL);
655 interbus_conf.conf_bits.msi_off = NGE_SET;
656 pci_config_put32(handle, PCI_CONF_HT_INTERNAL,
657 interbus_conf.conf_val);
658 }
659 command = infop->command | PCI_COMM_MAE;
660 command &= ~PCI_COMM_MEMWR_INVAL;
661 command |= PCI_COMM_ME;
662 pci_config_put16(handle, PCI_CONF_COMM, command);
663 pci_config_put16(handle, PCI_CONF_STAT, ~0);
664
665 }
666
667 int
nge_chip_stop(nge_t * ngep,boolean_t fault)668 nge_chip_stop(nge_t *ngep, boolean_t fault)
669 {
670 int err;
671 uint32_t reg_val;
672 uint32_t tries;
673 nge_mintr_src mintr_src;
674 nge_mii_cs mii_cs;
675 nge_rx_poll rx_poll;
676 nge_tx_poll tx_poll;
677 nge_rx_en rx_en;
678 nge_tx_en tx_en;
679 nge_tx_sta tx_sta;
680 nge_rx_sta rx_sta;
681 nge_mode_cntl mode;
682 nge_pmu_cntl2 pmu_cntl2;
683
684 NGE_TRACE(("nge_chip_stop($%p, %d)", (void *)ngep, fault));
685
686 err = DDI_SUCCESS;
687
688 /* Clear any pending PHY interrupt */
689 mintr_src.src_val = nge_reg_get8(ngep, NGE_MINTR_SRC);
690 nge_reg_put8(ngep, NGE_MINTR_SRC, mintr_src.src_val);
691
692 /* Mask all interrupts */
693 reg_val = nge_reg_get32(ngep, NGE_INTR_MASK);
694 reg_val &= ~NGE_INTR_ALL_EN;
695 nge_reg_put32(ngep, NGE_INTR_MASK, reg_val);
696
697 /* Disable auto-polling of phy */
698 mii_cs.cs_val = nge_reg_get32(ngep, NGE_MII_CS);
699 mii_cs.cs_bits.ap_en = NGE_CLEAR;
700 nge_reg_put32(ngep, NGE_MII_CS, mii_cs.cs_val);
701
702 /* Reset buffer management & DMA */
703 mode.mode_val = nge_reg_get32(ngep, NGE_MODE_CNTL);
704 mode.mode_bits.dma_dis = NGE_SET;
705 mode.mode_bits.desc_type = ngep->desc_mode;
706 nge_reg_put32(ngep, NGE_MODE_CNTL, mode.mode_val);
707
708 for (tries = 0; tries < 10000; tries++) {
709 drv_usecwait(10);
710 mode.mode_val = nge_reg_get32(ngep, NGE_MODE_CNTL);
711 if (mode.mode_bits.dma_status == NGE_SET)
712 break;
713 }
714 if (tries == 10000) {
715 ngep->nge_chip_state = NGE_CHIP_ERROR;
716 return (DDI_FAILURE);
717 }
718
719 /* Disable rx's machine */
720 rx_en.val = nge_reg_get8(ngep, NGE_RX_EN);
721 rx_en.bits.rx_en = NGE_CLEAR;
722 nge_reg_put8(ngep, NGE_RX_EN, rx_en.val);
723
724 /* Disable tx's machine */
725 tx_en.val = nge_reg_get8(ngep, NGE_TX_EN);
726 tx_en.bits.tx_en = NGE_CLEAR;
727 nge_reg_put8(ngep, NGE_TX_EN, tx_en.val);
728
729 /*
730 * Clean the status of tx's state machine
731 * and Make assure the tx's channel is idle
732 */
733 tx_sta.sta_val = nge_reg_get32(ngep, NGE_TX_STA);
734 for (tries = 0; tries < 1000; tries++) {
735 if (tx_sta.sta_bits.tx_chan_sta == NGE_CLEAR)
736 break;
737 drv_usecwait(10);
738 tx_sta.sta_val = nge_reg_get32(ngep, NGE_TX_STA);
739 }
740 if (tries == 1000) {
741 ngep->nge_chip_state = NGE_CHIP_ERROR;
742 return (DDI_FAILURE);
743 }
744 nge_reg_put32(ngep, NGE_TX_STA, tx_sta.sta_val);
745
746 /*
747 * Clean the status of rx's state machine
748 * and Make assure the tx's channel is idle
749 */
750 rx_sta.sta_val = nge_reg_get32(ngep, NGE_RX_STA);
751 for (tries = 0; tries < 1000; tries++) {
752 if (rx_sta.sta_bits.rx_chan_sta == NGE_CLEAR)
753 break;
754 drv_usecwait(10);
755 rx_sta.sta_val = nge_reg_get32(ngep, NGE_RX_STA);
756 }
757 if (tries == 1000) {
758 ngep->nge_chip_state = NGE_CHIP_ERROR;
759 return (DDI_FAILURE);
760 }
761 nge_reg_put32(ngep, NGE_RX_STA, rx_sta.sta_val);
762
763 /* Disable auto-poll of rx's state machine */
764 rx_poll.poll_val = nge_reg_get32(ngep, NGE_RX_POLL);
765 rx_poll.poll_bits.rpen = NGE_CLEAR;
766 rx_poll.poll_bits.rpi = NGE_CLEAR;
767 nge_reg_put32(ngep, NGE_RX_POLL, rx_poll.poll_val);
768
769 /* Disable auto-polling of tx's state machine */
770 tx_poll.poll_val = nge_reg_get32(ngep, NGE_TX_POLL);
771 tx_poll.poll_bits.tpen = NGE_CLEAR;
772 tx_poll.poll_bits.tpi = NGE_CLEAR;
773 nge_reg_put32(ngep, NGE_TX_POLL, tx_poll.poll_val);
774
775 /* Restore buffer management */
776 mode.mode_val = nge_reg_get32(ngep, NGE_MODE_CNTL);
777 mode.mode_bits.bm_reset = NGE_SET;
778 mode.mode_bits.tx_rcom_en = NGE_SET;
779 nge_reg_put32(ngep, NGE_MODE_CNTL, mode.mode_val);
780
781 if (ngep->dev_spec_param.advanced_pm) {
782
783 nge_reg_put32(ngep, NGE_PMU_CIDLE_LIMIT, 0);
784 nge_reg_put32(ngep, NGE_PMU_DIDLE_LIMIT, 0);
785
786 pmu_cntl2.cntl2_val = nge_reg_get32(ngep, NGE_PMU_CNTL2);
787 pmu_cntl2.cntl2_bits.cidle_timer = NGE_CLEAR;
788 pmu_cntl2.cntl2_bits.didle_timer = NGE_CLEAR;
789 nge_reg_put32(ngep, NGE_PMU_CNTL2, pmu_cntl2.cntl2_val);
790 }
791 if (fault)
792 ngep->nge_chip_state = NGE_CHIP_FAULT;
793 else
794 ngep->nge_chip_state = NGE_CHIP_STOPPED;
795
796 return (err);
797 }
798
799 static void
nge_rx_setup(nge_t * ngep)800 nge_rx_setup(nge_t *ngep)
801 {
802 uint64_t desc_addr;
803 nge_rxtx_dlen dlen;
804 nge_rx_poll rx_poll;
805
806 /*
807 * Filling the address and length of rx's descriptors
808 */
809 desc_addr = ngep->recv->desc.cookie.dmac_laddress;
810 nge_reg_put32(ngep, NGE_RX_DADR, desc_addr);
811 nge_reg_put32(ngep, NGE_RX_DADR_HI, desc_addr >> 32);
812 dlen.dlen_val = nge_reg_get32(ngep, NGE_RXTX_DLEN);
813 dlen.dlen_bits.rdlen = ngep->recv->desc.nslots - 1;
814 nge_reg_put32(ngep, NGE_RXTX_DLEN, dlen.dlen_val);
815
816 rx_poll.poll_val = nge_reg_get32(ngep, NGE_RX_POLL);
817 rx_poll.poll_bits.rpi = RX_POLL_INTV_1G;
818 rx_poll.poll_bits.rpen = NGE_SET;
819 nge_reg_put32(ngep, NGE_RX_POLL, rx_poll.poll_val);
820 }
821
822 static void
nge_tx_setup(nge_t * ngep)823 nge_tx_setup(nge_t *ngep)
824 {
825 uint64_t desc_addr;
826 nge_rxtx_dlen dlen;
827
828 /*
829 * Filling the address and length of tx's descriptors
830 */
831 desc_addr = ngep->send->desc.cookie.dmac_laddress;
832 nge_reg_put32(ngep, NGE_TX_DADR, desc_addr);
833 nge_reg_put32(ngep, NGE_TX_DADR_HI, desc_addr >> 32);
834 dlen.dlen_val = nge_reg_get32(ngep, NGE_RXTX_DLEN);
835 dlen.dlen_bits.tdlen = ngep->send->desc.nslots - 1;
836 nge_reg_put32(ngep, NGE_RXTX_DLEN, dlen.dlen_val);
837 }
838
839 static int
nge_buff_setup(nge_t * ngep)840 nge_buff_setup(nge_t *ngep)
841 {
842 nge_mode_cntl mode_cntl;
843 nge_dev_spec_param_t *dev_param_p;
844
845 dev_param_p = &ngep->dev_spec_param;
846
847 /*
848 * Configure Rx&Tx's buffer
849 */
850 nge_rx_setup(ngep);
851 nge_tx_setup(ngep);
852
853 /*
854 * Configure buffer attribute
855 */
856 mode_cntl.mode_val = nge_reg_get32(ngep, NGE_MODE_CNTL);
857
858 /*
859 * Enable Dma access request
860 */
861 mode_cntl.mode_bits.dma_dis = NGE_CLEAR;
862
863 /*
864 * Enbale Buffer management
865 */
866 mode_cntl.mode_bits.bm_reset = NGE_CLEAR;
867
868 /*
869 * Support Standoffload Descriptor
870 */
871 mode_cntl.mode_bits.desc_type = ngep->desc_mode;
872
873 /*
874 * Support receive hardware checksum
875 */
876 if (dev_param_p->rx_hw_checksum) {
877 mode_cntl.mode_bits.rx_sum_en = NGE_SET;
878 } else
879 mode_cntl.mode_bits.rx_sum_en = NGE_CLEAR;
880
881 /*
882 * Disable Tx PRD coarse update
883 */
884 mode_cntl.mode_bits.tx_prd_cu_en = NGE_CLEAR;
885
886 /*
887 * Disable 64-byte access
888 */
889 mode_cntl.mode_bits.w64_dis = NGE_SET;
890
891 /*
892 * Skip Rx Error Frame is not supported and if
893 * enable it, jumbo frame does not work any more.
894 */
895 mode_cntl.mode_bits.rx_filter_en = NGE_CLEAR;
896
897 /*
898 * Can not support hot mode now
899 */
900 mode_cntl.mode_bits.resv15 = NGE_CLEAR;
901
902 if (dev_param_p->vlan) {
903 /* Disable the vlan strip for devices which support vlan */
904 mode_cntl.mode_bits.vlan_strip = NGE_CLEAR;
905
906 /* Disable the vlan insert for devices which supprot vlan */
907 mode_cntl.mode_bits.vlan_ins = NGE_CLEAR;
908 }
909
910 if (dev_param_p->tx_rx_64byte) {
911
912 /* Set the maximum TX PRD fetch size to 64 bytes */
913 mode_cntl.mode_bits.tx_fetch_prd = NGE_SET;
914
915 /* Set the maximum RX PRD fetch size to 64 bytes */
916 mode_cntl.mode_bits.rx_fetch_prd = NGE_SET;
917 }
918 /*
919 * Upload Rx data as it arrives, rather than waiting for full frame
920 */
921 mode_cntl.mode_bits.resv16 = NGE_CLEAR;
922
923 /*
924 * Normal HOT table accesses
925 */
926 mode_cntl.mode_bits.resv17 = NGE_CLEAR;
927
928 /*
929 * Normal HOT buffer requesting
930 */
931 mode_cntl.mode_bits.resv18 = NGE_CLEAR;
932 nge_reg_put32(ngep, NGE_MODE_CNTL, mode_cntl.mode_val);
933
934 /*
935 * Signal controller to check for new Rx descriptors
936 */
937 mode_cntl.mode_val = nge_reg_get32(ngep, NGE_MODE_CNTL);
938 mode_cntl.mode_bits.rxdm = NGE_SET;
939 mode_cntl.mode_bits.tx_rcom_en = NGE_SET;
940 nge_reg_put32(ngep, NGE_MODE_CNTL, mode_cntl.mode_val);
941
942
943 return (DDI_SUCCESS);
944 }
945
946 /*
947 * When chipset resets, the chipset can not restore the orignial
948 * mac address to the mac address registers.
949 *
950 * When the driver is dettached, the function will write the orignial
951 * mac address to the mac address registers.
952 */
953
954 void
nge_restore_mac_addr(nge_t * ngep)955 nge_restore_mac_addr(nge_t *ngep)
956 {
957 uint32_t mac_addr;
958
959 mac_addr = (uint32_t)ngep->chipinfo.hw_mac_addr;
960 nge_reg_put32(ngep, NGE_UNI_ADDR0, mac_addr);
961 mac_addr = (uint32_t)(ngep->chipinfo.hw_mac_addr >> 32);
962 nge_reg_put32(ngep, NGE_UNI_ADDR1, mac_addr);
963 }
964
965 int
nge_chip_reset(nge_t * ngep)966 nge_chip_reset(nge_t *ngep)
967 {
968 int err;
969 uint8_t i;
970 uint32_t regno;
971 uint64_t mac = 0;
972 nge_uni_addr1 uaddr1;
973 nge_cp_cntl ee_cntl;
974 nge_soft_misc soft_misc;
975 nge_pmu_cntl0 pmu_cntl0;
976 nge_pmu_cntl2 pmu_cntl2;
977 nge_pm_cntl2 pm_cntl2;
978 const nge_ksindex_t *ksip;
979
980 NGE_TRACE(("nge_chip_reset($%p)", (void *)ngep));
981
982 /*
983 * Clear the statistics by reading the statistics register
984 */
985 for (ksip = nge_statistics; ksip->name != NULL; ++ksip) {
986 regno = KS_BASE + ksip->index * sizeof (uint32_t);
987 (void) nge_reg_get32(ngep, regno);
988 }
989
990 /*
991 * Setup seeprom control
992 */
993 ee_cntl.cntl_val = nge_reg_get32(ngep, NGE_EP_CNTL);
994 ee_cntl.cntl_bits.clkdiv = EEPROM_CLKDIV;
995 ee_cntl.cntl_bits.rom_size = EEPROM_32K;
996 ee_cntl.cntl_bits.word_wid = ACCESS_16BIT;
997 ee_cntl.cntl_bits.wait_slots = EEPROM_WAITCLK;
998 nge_reg_put32(ngep, NGE_EP_CNTL, ee_cntl.cntl_val);
999
1000 /*
1001 * Reading the unicast mac address table
1002 */
1003 if (ngep->nge_chip_state == NGE_CHIP_INITIAL) {
1004 uaddr1.addr_val = nge_reg_get32(ngep, NGE_UNI_ADDR1);
1005 mac = uaddr1.addr_bits.addr;
1006 mac <<= 32;
1007 mac |= nge_reg_get32(ngep, NGE_UNI_ADDR0);
1008 ngep->chipinfo.hw_mac_addr = mac;
1009 if (ngep->dev_spec_param.mac_addr_order) {
1010 for (i = 0; i < ETHERADDRL; i++) {
1011 ngep->chipinfo.vendor_addr.addr[i] =
1012 (uchar_t)mac;
1013 ngep->cur_uni_addr.addr[i] =
1014 (uchar_t)mac;
1015 mac >>= 8;
1016 }
1017 } else {
1018 for (i = ETHERADDRL; i-- != 0; ) {
1019 ngep->chipinfo.vendor_addr.addr[i] =
1020 (uchar_t)mac;
1021 ngep->cur_uni_addr.addr[i] =
1022 (uchar_t)mac;
1023 mac >>= 8;
1024 }
1025 }
1026 ngep->chipinfo.vendor_addr.set = 1;
1027 }
1028 pci_config_put8(ngep->cfg_handle, PCI_CONF_CACHE_LINESZ,
1029 ngep->chipinfo.clsize);
1030 pci_config_put8(ngep->cfg_handle, PCI_CONF_LATENCY_TIMER,
1031 ngep->chipinfo.latency);
1032
1033
1034 if (ngep->dev_spec_param.advanced_pm) {
1035
1036 /* Program software misc register */
1037 soft_misc.misc_val = nge_reg_get32(ngep, NGE_SOFT_MISC);
1038 soft_misc.misc_bits.rx_clk_vx_rst = NGE_SET;
1039 soft_misc.misc_bits.tx_clk_vx_rst = NGE_SET;
1040 soft_misc.misc_bits.clk12m_vx_rst = NGE_SET;
1041 soft_misc.misc_bits.fpci_clk_vx_rst = NGE_SET;
1042 soft_misc.misc_bits.rx_clk_vc_rst = NGE_SET;
1043 soft_misc.misc_bits.tx_clk_vc_rst = NGE_SET;
1044 soft_misc.misc_bits.fs_clk_vc_rst = NGE_SET;
1045 soft_misc.misc_bits.rst_ex_m2pintf = NGE_SET;
1046 nge_reg_put32(ngep, NGE_SOFT_MISC, soft_misc.misc_val);
1047
1048 /* wait for 32 us */
1049 drv_usecwait(32);
1050
1051 soft_misc.misc_val = nge_reg_get32(ngep, NGE_SOFT_MISC);
1052 soft_misc.misc_bits.rx_clk_vx_rst = NGE_CLEAR;
1053 soft_misc.misc_bits.tx_clk_vx_rst = NGE_CLEAR;
1054 soft_misc.misc_bits.clk12m_vx_rst = NGE_CLEAR;
1055 soft_misc.misc_bits.fpci_clk_vx_rst = NGE_CLEAR;
1056 soft_misc.misc_bits.rx_clk_vc_rst = NGE_CLEAR;
1057 soft_misc.misc_bits.tx_clk_vc_rst = NGE_CLEAR;
1058 soft_misc.misc_bits.fs_clk_vc_rst = NGE_CLEAR;
1059 soft_misc.misc_bits.rst_ex_m2pintf = NGE_CLEAR;
1060 nge_reg_put32(ngep, NGE_SOFT_MISC, soft_misc.misc_val);
1061
1062 /* Program PMU registers */
1063 pmu_cntl0.cntl0_val = nge_reg_get32(ngep, NGE_PMU_CNTL0);
1064 pmu_cntl0.cntl0_bits.core_spd10_fp =
1065 NGE_PMU_CORE_SPD10_BUSY;
1066 pmu_cntl0.cntl0_bits.core_spd10_idle =
1067 NGE_PMU_CORE_SPD10_IDLE;
1068 pmu_cntl0.cntl0_bits.core_spd100_fp =
1069 NGE_PMU_CORE_SPD100_BUSY;
1070 pmu_cntl0.cntl0_bits.core_spd100_idle =
1071 NGE_PMU_CORE_SPD100_IDLE;
1072 pmu_cntl0.cntl0_bits.core_spd1000_fp =
1073 NGE_PMU_CORE_SPD1000_BUSY;
1074 pmu_cntl0.cntl0_bits.core_spd1000_idle =
1075 NGE_PMU_CORE_SPD100_IDLE;
1076 pmu_cntl0.cntl0_bits.core_spd10_idle =
1077 NGE_PMU_CORE_SPD10_IDLE;
1078 nge_reg_put32(ngep, NGE_PMU_CNTL0, pmu_cntl0.cntl0_val);
1079
1080 /* Set the core idle limit value */
1081 nge_reg_put32(ngep, NGE_PMU_CIDLE_LIMIT,
1082 NGE_PMU_CIDLE_LIMIT_DEF);
1083
1084 /* Set the device idle limit value */
1085 nge_reg_put32(ngep, NGE_PMU_DIDLE_LIMIT,
1086 NGE_PMU_DIDLE_LIMIT_DEF);
1087
1088 /* Enable the core/device idle timer in PMU control 2 */
1089 pmu_cntl2.cntl2_val = nge_reg_get32(ngep, NGE_PMU_CNTL2);
1090 pmu_cntl2.cntl2_bits.cidle_timer = NGE_SET;
1091 pmu_cntl2.cntl2_bits.didle_timer = NGE_SET;
1092 pmu_cntl2.cntl2_bits.core_enable = NGE_SET;
1093 pmu_cntl2.cntl2_bits.dev_enable = NGE_SET;
1094 nge_reg_put32(ngep, NGE_PMU_CNTL2, pmu_cntl2.cntl2_val);
1095 }
1096 /*
1097 * Stop the chipset and clear buffer management
1098 */
1099 err = nge_chip_stop(ngep, B_FALSE);
1100 if (err == DDI_FAILURE)
1101 return (err);
1102 /*
1103 * Clear the power state bits for phy since interface no longer
1104 * works after rebooting from Windows on a multi-boot machine
1105 */
1106 if (ngep->chipinfo.device == DEVICE_ID_MCP51_268 ||
1107 ngep->chipinfo.device == DEVICE_ID_MCP51_269 ||
1108 ngep->chipinfo.device == DEVICE_ID_MCP55_372 ||
1109 ngep->chipinfo.device == DEVICE_ID_MCP55_373 ||
1110 ngep->chipinfo.device == DEVICE_ID_MCP61_3EE ||
1111 ngep->chipinfo.device == DEVICE_ID_MCP61_3EF ||
1112 ngep->chipinfo.device == DEVICE_ID_MCP77_760 ||
1113 ngep->chipinfo.device == DEVICE_ID_MCP79_AB0) {
1114
1115 pm_cntl2.cntl_val = nge_reg_get32(ngep, NGE_PM_CNTL2);
1116 /* bring phy out of coma mode */
1117 pm_cntl2.cntl_bits.phy_coma_set = NGE_CLEAR;
1118 /* disable auto reset coma bits */
1119 pm_cntl2.cntl_bits.resv4 = NGE_CLEAR;
1120 /* restore power to gated clocks */
1121 pm_cntl2.cntl_bits.resv8_11 = NGE_CLEAR;
1122 nge_reg_put32(ngep, NGE_PM_CNTL2, pm_cntl2.cntl_val);
1123 }
1124
1125 ngep->nge_chip_state = NGE_CHIP_RESET;
1126 return (DDI_SUCCESS);
1127 }
1128
1129 int
nge_chip_start(nge_t * ngep)1130 nge_chip_start(nge_t *ngep)
1131 {
1132 int err;
1133 nge_itc itc;
1134 nge_tx_cntl tx_cntl;
1135 nge_rx_cntrl0 rx_cntl0;
1136 nge_rx_cntl1 rx_cntl1;
1137 nge_tx_en tx_en;
1138 nge_rx_en rx_en;
1139 nge_mii_cs mii_cs;
1140 nge_swtr_cntl swtr_cntl;
1141 nge_rx_fifo_wm rx_fifo;
1142 nge_intr_mask intr_mask;
1143 nge_mintr_mask mintr_mask;
1144 nge_dev_spec_param_t *dev_param_p;
1145
1146 NGE_TRACE(("nge_chip_start($%p)", (void *)ngep));
1147
1148 /*
1149 * Setup buffer management
1150 */
1151 err = nge_buff_setup(ngep);
1152 if (err == DDI_FAILURE)
1153 return (err);
1154
1155 dev_param_p = &ngep->dev_spec_param;
1156
1157 /*
1158 * Enable polling attribute
1159 */
1160 mii_cs.cs_val = nge_reg_get32(ngep, NGE_MII_CS);
1161 mii_cs.cs_bits.ap_paddr = ngep->phy_xmii_addr;
1162 mii_cs.cs_bits.ap_en = NGE_SET;
1163 mii_cs.cs_bits.ap_intv = MII_POLL_INTV;
1164 nge_reg_put32(ngep, NGE_MII_CS, mii_cs.cs_val);
1165
1166 /*
1167 * Setup link
1168 */
1169 (*ngep->physops->phys_update)(ngep);
1170
1171 /*
1172 * Configure the tx's parameters
1173 */
1174 tx_cntl.cntl_val = nge_reg_get32(ngep, NGE_TX_CNTL);
1175 if (dev_param_p->tx_pause_frame)
1176 tx_cntl.cntl_bits.paen = NGE_SET;
1177 else
1178 tx_cntl.cntl_bits.paen = NGE_CLEAR;
1179 tx_cntl.cntl_bits.retry_en = NGE_SET;
1180 tx_cntl.cntl_bits.pad_en = NGE_SET;
1181 tx_cntl.cntl_bits.fappend_en = NGE_SET;
1182 tx_cntl.cntl_bits.two_def_en = NGE_SET;
1183 tx_cntl.cntl_bits.max_retry = 15;
1184 tx_cntl.cntl_bits.burst_en = NGE_CLEAR;
1185 tx_cntl.cntl_bits.uflo_err_mask = NGE_CLEAR;
1186 tx_cntl.cntl_bits.tlcol_mask = NGE_CLEAR;
1187 tx_cntl.cntl_bits.lcar_mask = NGE_CLEAR;
1188 tx_cntl.cntl_bits.def_mask = NGE_CLEAR;
1189 tx_cntl.cntl_bits.exdef_mask = NGE_SET;
1190 tx_cntl.cntl_bits.lcar_mask = NGE_SET;
1191 tx_cntl.cntl_bits.tlcol_mask = NGE_SET;
1192 tx_cntl.cntl_bits.uflo_err_mask = NGE_SET;
1193 tx_cntl.cntl_bits.jam_seq_en = NGE_CLEAR;
1194 nge_reg_put32(ngep, NGE_TX_CNTL, tx_cntl.cntl_val);
1195
1196
1197 /*
1198 * Configure the parameters of Rx's state machine
1199 * Enabe the parameters:
1200 * 1). Pad Strip
1201 * 2). FCS Relay
1202 * 3). Pause
1203 * 4). Address filter
1204 * 5). Runt Packet receive
1205 * 6). Broadcast
1206 * 7). Receive Deferral
1207 *
1208 * Disable the following parameters for decreasing
1209 * the number of interrupts:
1210 * 1). Runt Inerrupt.
1211 * 2). Rx's Late Collision interrupt.
1212 * 3). Rx's Max length Error Interrupt.
1213 * 4). Rx's Length Field error Interrupt.
1214 * 5). Rx's FCS error interrupt.
1215 * 6). Rx's overflow error interrupt.
1216 * 7). Rx's Frame alignment error interrupt.
1217 */
1218 rx_cntl0.cntl_val = nge_reg_get32(ngep, NGE_RX_CNTL0);
1219 rx_cntl0.cntl_bits.padsen = NGE_CLEAR;
1220 rx_cntl0.cntl_bits.fcsren = NGE_CLEAR;
1221 if (dev_param_p->rx_pause_frame)
1222 rx_cntl0.cntl_bits.paen = NGE_SET;
1223 else
1224 rx_cntl0.cntl_bits.paen = NGE_CLEAR;
1225 rx_cntl0.cntl_bits.lben = NGE_CLEAR;
1226 rx_cntl0.cntl_bits.afen = NGE_SET;
1227 rx_cntl0.cntl_bits.runten = NGE_CLEAR;
1228 rx_cntl0.cntl_bits.brdis = NGE_CLEAR;
1229 rx_cntl0.cntl_bits.rdfen = NGE_CLEAR;
1230 rx_cntl0.cntl_bits.runtm = NGE_CLEAR;
1231 rx_cntl0.cntl_bits.slfb = NGE_CLEAR;
1232 rx_cntl0.cntl_bits.rlcolm = NGE_CLEAR;
1233 rx_cntl0.cntl_bits.maxerm = NGE_CLEAR;
1234 rx_cntl0.cntl_bits.lferm = NGE_CLEAR;
1235 rx_cntl0.cntl_bits.crcm = NGE_CLEAR;
1236 rx_cntl0.cntl_bits.ofolm = NGE_CLEAR;
1237 rx_cntl0.cntl_bits.framerm = NGE_CLEAR;
1238 nge_reg_put32(ngep, NGE_RX_CNTL0, rx_cntl0.cntl_val);
1239
1240 /*
1241 * Configure the watermark for the rx's statemachine
1242 */
1243 rx_fifo.wm_val = nge_reg_get32(ngep, NGE_RX_FIFO_WM);
1244 rx_fifo.wm_bits.data_hwm = ngep->rx_datahwm;
1245 rx_fifo.wm_bits.prd_lwm = ngep->rx_prdlwm;
1246 rx_fifo.wm_bits.prd_hwm = ngep->rx_prdhwm;
1247 nge_reg_put32(ngep, NGE_RX_FIFO_WM, rx_fifo.wm_val);
1248
1249 /*
1250 * Configure the deffer time slot for rx's state machine
1251 */
1252 nge_reg_put8(ngep, NGE_RX_DEf, ngep->rx_def);
1253
1254 /*
1255 * Configure the length of rx's packet
1256 */
1257 rx_cntl1.cntl_val = nge_reg_get32(ngep, NGE_RX_CNTL1);
1258 rx_cntl1.cntl_bits.length = ngep->max_sdu;
1259 nge_reg_put32(ngep, NGE_RX_CNTL1, rx_cntl1.cntl_val);
1260 /*
1261 * Enable Tx's state machine
1262 */
1263 tx_en.val = nge_reg_get8(ngep, NGE_TX_EN);
1264 tx_en.bits.tx_en = NGE_SET;
1265 nge_reg_put8(ngep, NGE_TX_EN, tx_en.val);
1266
1267 /*
1268 * Enable Rx's state machine
1269 */
1270 rx_en.val = nge_reg_get8(ngep, NGE_RX_EN);
1271 rx_en.bits.rx_en = NGE_SET;
1272 nge_reg_put8(ngep, NGE_RX_EN, rx_en.val);
1273
1274 itc.itc_val = nge_reg_get32(ngep, NGE_SWTR_ITC);
1275 itc.itc_bits.sw_intv = ngep->sw_intr_intv;
1276 nge_reg_put32(ngep, NGE_SWTR_ITC, itc.itc_val);
1277
1278 swtr_cntl.ctrl_val = nge_reg_get8(ngep, NGE_SWTR_CNTL);
1279 swtr_cntl.cntl_bits.sten = NGE_SET;
1280 swtr_cntl.cntl_bits.stren = NGE_SET;
1281 nge_reg_put32(ngep, NGE_SWTR_CNTL, swtr_cntl.ctrl_val);
1282
1283 /*
1284 * Disable all mii read/write operation Interrupt
1285 */
1286 mintr_mask.mask_val = nge_reg_get8(ngep, NGE_MINTR_MASK);
1287 mintr_mask.mask_bits.mrei = NGE_CLEAR;
1288 mintr_mask.mask_bits.mcc2 = NGE_CLEAR;
1289 mintr_mask.mask_bits.mcc1 = NGE_CLEAR;
1290 mintr_mask.mask_bits.mapi = NGE_SET;
1291 mintr_mask.mask_bits.mpdi = NGE_SET;
1292 nge_reg_put8(ngep, NGE_MINTR_MASK, mintr_mask.mask_val);
1293
1294 /*
1295 * Enable all interrupt event
1296 */
1297 intr_mask.mask_val = nge_reg_get32(ngep, NGE_INTR_MASK);
1298 intr_mask.mask_bits.reint = NGE_SET;
1299 intr_mask.mask_bits.rcint = NGE_SET;
1300 intr_mask.mask_bits.miss = NGE_SET;
1301 intr_mask.mask_bits.teint = NGE_SET;
1302 intr_mask.mask_bits.tcint = NGE_CLEAR;
1303 intr_mask.mask_bits.stint = NGE_CLEAR;
1304 intr_mask.mask_bits.mint = NGE_CLEAR;
1305 intr_mask.mask_bits.rfint = NGE_CLEAR;
1306 intr_mask.mask_bits.tfint = NGE_SET;
1307 intr_mask.mask_bits.feint = NGE_SET;
1308 intr_mask.mask_bits.resv10 = NGE_CLEAR;
1309 intr_mask.mask_bits.resv11 = NGE_CLEAR;
1310 intr_mask.mask_bits.resv12 = NGE_CLEAR;
1311 intr_mask.mask_bits.resv13 = NGE_CLEAR;
1312 intr_mask.mask_bits.phyint = NGE_CLEAR;
1313 ngep->intr_masks = intr_mask.mask_val;
1314 nge_reg_put32(ngep, NGE_INTR_MASK, intr_mask.mask_val);
1315 ngep->nge_chip_state = NGE_CHIP_RUNNING;
1316 return (DDI_SUCCESS);
1317 }
1318
1319 /*
1320 * nge_chip_sync() -- program the chip with the unicast MAC address,
1321 * the multicast hash table, the required level of promiscuity.
1322 */
1323 void
nge_chip_sync(nge_t * ngep)1324 nge_chip_sync(nge_t *ngep)
1325 {
1326 uint8_t i;
1327 uint64_t macaddr;
1328 uint64_t mul_addr;
1329 uint64_t mul_mask;
1330 nge_rx_cntrl0 rx_cntl;
1331 nge_uni_addr1 uni_adr1;
1332
1333 NGE_TRACE(("nge_chip_sync($%p)", (void *)ngep));
1334
1335 macaddr = 0x0ull;
1336 mul_addr = 0x0ull;
1337 mul_mask = 0x0ull;
1338 rx_cntl.cntl_val = nge_reg_get32(ngep, NGE_RX_CNTL0);
1339
1340 if (ngep->promisc) {
1341 rx_cntl.cntl_bits.afen = NGE_CLEAR;
1342 rx_cntl.cntl_bits.brdis = NGE_SET;
1343 } else {
1344 rx_cntl.cntl_bits.afen = NGE_SET;
1345 rx_cntl.cntl_bits.brdis = NGE_CLEAR;
1346 }
1347
1348 /*
1349 * Transform the MAC address from host to chip format, the unicast
1350 * MAC address(es) ...
1351 */
1352 for (i = ETHERADDRL, macaddr = 0ull; i != 0; --i) {
1353 macaddr |= ngep->cur_uni_addr.addr[i-1];
1354 macaddr <<= (i > 1) ? 8 : 0;
1355 }
1356
1357 nge_reg_put32(ngep, NGE_UNI_ADDR0, (uint32_t)macaddr);
1358 macaddr = macaddr >>32;
1359 uni_adr1.addr_val = nge_reg_get32(ngep, NGE_UNI_ADDR1);
1360 uni_adr1.addr_bits.addr = (uint16_t)macaddr;
1361 uni_adr1.addr_bits.resv16_31 = (uint16_t)0;
1362 nge_reg_put32(ngep, NGE_UNI_ADDR1, uni_adr1.addr_val);
1363
1364 /*
1365 * Reprogram the multicast address table ...
1366 */
1367 for (i = ETHERADDRL, mul_addr = 0ull; i != 0; --i) {
1368 mul_addr |= ngep->cur_mul_addr.addr[i-1];
1369 mul_addr <<= (i > 1) ? 8 : 0;
1370 mul_mask |= ngep->cur_mul_mask.addr[i-1];
1371 mul_mask <<= (i > 1) ? 8 : 0;
1372 }
1373 nge_reg_put32(ngep, NGE_MUL_ADDR0, (uint32_t)mul_addr);
1374 mul_addr >>= 32;
1375 nge_reg_put32(ngep, NGE_MUL_ADDR1, mul_addr);
1376 nge_reg_put32(ngep, NGE_MUL_MASK, (uint32_t)mul_mask);
1377 mul_mask >>= 32;
1378 nge_reg_put32(ngep, NGE_MUL_MASK1, mul_mask);
1379 /*
1380 * Set or clear the PROMISCUOUS mode bit
1381 */
1382 nge_reg_put32(ngep, NGE_RX_CNTL0, rx_cntl.cntl_val);
1383 /*
1384 * For internal PHY loopback, the link will
1385 * not be up, so it need to sync mac modes directly.
1386 */
1387 if (ngep->param_loop_mode == NGE_LOOP_INTERNAL_PHY)
1388 nge_sync_mac_modes(ngep);
1389 }
1390
1391 static void
nge_chip_err(nge_t * ngep)1392 nge_chip_err(nge_t *ngep)
1393 {
1394 nge_reg010 reg010_ins;
1395 nge_sw_statistics_t *psw_stat;
1396 nge_intr_mask intr_mask;
1397
1398 NGE_TRACE(("nge_chip_err($%p)", (void *)ngep));
1399
1400 psw_stat = (nge_sw_statistics_t *)&ngep->statistics.sw_statistics;
1401 reg010_ins.reg010_val = nge_reg_get32(ngep, NGE_REG010);
1402 if (reg010_ins.reg010_bits.resv0)
1403 psw_stat->fe_err.tso_err_mss ++;
1404
1405 if (reg010_ins.reg010_bits.resv1)
1406 psw_stat->fe_err.tso_dis ++;
1407
1408 if (reg010_ins.reg010_bits.resv2)
1409 psw_stat->fe_err.tso_err_nosum ++;
1410
1411 if (reg010_ins.reg010_bits.resv3)
1412 psw_stat->fe_err.tso_err_hov ++;
1413
1414 if (reg010_ins.reg010_bits.resv4)
1415 psw_stat->fe_err.tso_err_huf ++;
1416
1417 if (reg010_ins.reg010_bits.resv5)
1418 psw_stat->fe_err.tso_err_l2 ++;
1419
1420 if (reg010_ins.reg010_bits.resv6)
1421 psw_stat->fe_err.tso_err_ip ++;
1422
1423 if (reg010_ins.reg010_bits.resv7)
1424 psw_stat->fe_err.tso_err_l4 ++;
1425
1426 if (reg010_ins.reg010_bits.resv8)
1427 psw_stat->fe_err.tso_err_tcp ++;
1428
1429 if (reg010_ins.reg010_bits.resv9)
1430 psw_stat->fe_err.hsum_err_ip ++;
1431
1432 if (reg010_ins.reg010_bits.resv10)
1433 psw_stat->fe_err.hsum_err_l4 ++;
1434
1435 if (reg010_ins.reg010_val != 0) {
1436
1437 /*
1438 * Fatal error is triggered by malformed driver commands.
1439 * Disable unless debugging.
1440 */
1441 intr_mask.mask_val = nge_reg_get32(ngep, NGE_INTR_MASK);
1442 intr_mask.mask_bits.feint = NGE_CLEAR;
1443 nge_reg_put32(ngep, NGE_INTR_MASK, intr_mask.mask_val);
1444 ngep->intr_masks = intr_mask.mask_val;
1445
1446 }
1447 }
1448
1449 static void
nge_sync_mac_modes(nge_t * ngep)1450 nge_sync_mac_modes(nge_t *ngep)
1451 {
1452 nge_tx_def tx_def;
1453 nge_tx_fifo_wm tx_fifo;
1454 nge_bkoff_cntl bk_cntl;
1455 nge_mac2phy m2p;
1456 nge_rx_cntrl0 rx_cntl0;
1457 nge_tx_cntl tx_cntl;
1458 nge_dev_spec_param_t *dev_param_p;
1459
1460 dev_param_p = &ngep->dev_spec_param;
1461
1462 tx_def.def_val = nge_reg_get32(ngep, NGE_TX_DEF);
1463 m2p.m2p_val = nge_reg_get32(ngep, NGE_MAC2PHY);
1464 tx_fifo.wm_val = nge_reg_get32(ngep, NGE_TX_FIFO_WM);
1465 bk_cntl.cntl_val = nge_reg_get32(ngep, NGE_BKOFF_CNTL);
1466 bk_cntl.bkoff_bits.rseed = BKOFF_RSEED;
1467 switch (ngep->param_link_speed) {
1468 case 10:
1469 m2p.m2p_bits.speed = low_speed;
1470 tx_def.def_bits.ifg1_def = TX_IFG1_DEFAULT;
1471 if (ngep->phy_mode == RGMII_IN) {
1472 tx_def.def_bits.ifg2_def = TX_IFG2_RGMII_10_100;
1473 tx_def.def_bits.if_def = TX_IFG_RGMII_OTHER;
1474 } else {
1475 tx_def.def_bits.if_def = TX_TIFG_MII;
1476 tx_def.def_bits.ifg2_def = TX_IFG2_MII;
1477 }
1478 tx_fifo.wm_bits.nbfb_wm = TX_FIFO_NOB_WM_MII;
1479 bk_cntl.bkoff_bits.sltm = BKOFF_SLIM_MII;
1480 break;
1481
1482 case 100:
1483 m2p.m2p_bits.speed = fast_speed;
1484 tx_def.def_bits.ifg1_def = TX_IFG1_DEFAULT;
1485 if (ngep->phy_mode == RGMII_IN) {
1486 tx_def.def_bits.ifg2_def = TX_IFG2_RGMII_10_100;
1487 tx_def.def_bits.if_def = TX_IFG_RGMII_OTHER;
1488 } else {
1489 tx_def.def_bits.if_def = TX_TIFG_MII;
1490 tx_def.def_bits.ifg2_def = TX_IFG2_MII;
1491 }
1492 tx_fifo.wm_bits.nbfb_wm = TX_FIFO_NOB_WM_MII;
1493 bk_cntl.bkoff_bits.sltm = BKOFF_SLIM_MII;
1494 break;
1495
1496 case 1000:
1497 m2p.m2p_bits.speed = giga_speed;
1498 tx_def.def_bits.ifg1_def = TX_IFG1_DEFAULT;
1499 if (ngep->param_link_duplex == LINK_DUPLEX_FULL) {
1500 tx_def.def_bits.ifg2_def = TX_IFG2_RGMII_1000;
1501 tx_def.def_bits.if_def = TX_IFG_RGMII_1000_FD;
1502 } else {
1503 tx_def.def_bits.ifg2_def = TX_IFG2_RGMII_1000;
1504 tx_def.def_bits.if_def = TX_IFG_RGMII_OTHER;
1505 }
1506
1507 tx_fifo.wm_bits.nbfb_wm = TX_FIFO_NOB_WM_GMII;
1508 bk_cntl.bkoff_bits.sltm = BKOFF_SLIM_GMII;
1509 break;
1510 }
1511
1512 if (ngep->chipinfo.device == DEVICE_ID_MCP55_373 ||
1513 ngep->chipinfo.device == DEVICE_ID_MCP55_372) {
1514 m2p.m2p_bits.phyintr = NGE_CLEAR;
1515 m2p.m2p_bits.phyintrlvl = NGE_CLEAR;
1516 }
1517 if (ngep->param_link_duplex == LINK_DUPLEX_HALF) {
1518 m2p.m2p_bits.hdup_en = NGE_SET;
1519 }
1520 else
1521 m2p.m2p_bits.hdup_en = NGE_CLEAR;
1522 nge_reg_put32(ngep, NGE_MAC2PHY, m2p.m2p_val);
1523 nge_reg_put32(ngep, NGE_TX_DEF, tx_def.def_val);
1524
1525 tx_fifo.wm_bits.data_lwm = TX_FIFO_DATA_LWM;
1526 tx_fifo.wm_bits.prd_lwm = TX_FIFO_PRD_LWM;
1527 tx_fifo.wm_bits.uprd_hwm = TX_FIFO_PRD_HWM;
1528 tx_fifo.wm_bits.fb_wm = TX_FIFO_TBFW;
1529 nge_reg_put32(ngep, NGE_TX_FIFO_WM, tx_fifo.wm_val);
1530
1531 nge_reg_put32(ngep, NGE_BKOFF_CNTL, bk_cntl.cntl_val);
1532
1533 rx_cntl0.cntl_val = nge_reg_get32(ngep, NGE_RX_CNTL0);
1534 if (ngep->param_link_rx_pause && dev_param_p->rx_pause_frame) {
1535 if (rx_cntl0.cntl_bits.paen == NGE_CLEAR) {
1536 rx_cntl0.cntl_bits.paen = NGE_SET;
1537 nge_reg_put32(ngep, NGE_RX_CNTL0, rx_cntl0.cntl_val);
1538 }
1539 } else {
1540 if (rx_cntl0.cntl_bits.paen == NGE_SET) {
1541 rx_cntl0.cntl_bits.paen = NGE_CLEAR;
1542 nge_reg_put32(ngep, NGE_RX_CNTL0, rx_cntl0.cntl_val);
1543 }
1544 }
1545
1546 tx_cntl.cntl_val = nge_reg_get32(ngep, NGE_TX_CNTL);
1547 if (ngep->param_link_tx_pause && dev_param_p->tx_pause_frame) {
1548 if (tx_cntl.cntl_bits.paen == NGE_CLEAR) {
1549 tx_cntl.cntl_bits.paen = NGE_SET;
1550 nge_reg_put32(ngep, NGE_TX_CNTL, tx_cntl.cntl_val);
1551 }
1552 } else {
1553 if (tx_cntl.cntl_bits.paen == NGE_SET) {
1554 tx_cntl.cntl_bits.paen = NGE_CLEAR;
1555 nge_reg_put32(ngep, NGE_TX_CNTL, tx_cntl.cntl_val);
1556 }
1557 }
1558 }
1559
1560 /*
1561 * Handler for hardware link state change.
1562 *
1563 * When this routine is called, the hardware link state has changed
1564 * and the new state is reflected in the param_* variables. Here
1565 * we must update the softstate, reprogram the MAC to match, and
1566 * record the change in the log and/or on the console.
1567 */
1568 static void
nge_factotum_link_handler(nge_t * ngep)1569 nge_factotum_link_handler(nge_t *ngep)
1570 {
1571 /*
1572 * Update the s/w link_state
1573 */
1574 if (ngep->param_link_up)
1575 ngep->link_state = LINK_STATE_UP;
1576 else
1577 ngep->link_state = LINK_STATE_DOWN;
1578
1579 /*
1580 * Reprogram the MAC modes to match
1581 */
1582 nge_sync_mac_modes(ngep);
1583 }
1584
1585 static boolean_t
nge_factotum_link_check(nge_t * ngep)1586 nge_factotum_link_check(nge_t *ngep)
1587 {
1588 boolean_t lchg;
1589 boolean_t check;
1590
1591 ASSERT(mutex_owned(ngep->genlock));
1592
1593 (*ngep->physops->phys_check)(ngep);
1594 switch (ngep->link_state) {
1595 case LINK_STATE_UP:
1596 lchg = (ngep->param_link_up == B_FALSE);
1597 check = (ngep->param_link_up == B_FALSE);
1598 break;
1599
1600 case LINK_STATE_DOWN:
1601 lchg = (ngep->param_link_up == B_TRUE);
1602 check = (ngep->param_link_up == B_TRUE);
1603 break;
1604
1605 default:
1606 check = B_TRUE;
1607 break;
1608 }
1609
1610 /*
1611 * If <check> is false, we're sure the link hasn't changed.
1612 * If true, however, it's not yet definitive; we have to call
1613 * nge_phys_check() to determine whether the link has settled
1614 * into a new state yet ... and if it has, then call the link
1615 * state change handler.But when the chip is 5700 in Dell 6650
1616 * ,even if check is false, the link may have changed.So we
1617 * have to call nge_phys_check() to determine the link state.
1618 */
1619 if (check)
1620 nge_factotum_link_handler(ngep);
1621
1622 return (lchg);
1623 }
1624
1625 /*
1626 * Factotum routine to check for Tx stall, using the 'watchdog' counter
1627 */
1628 static boolean_t nge_factotum_stall_check(nge_t *ngep);
1629
1630 static boolean_t
nge_factotum_stall_check(nge_t * ngep)1631 nge_factotum_stall_check(nge_t *ngep)
1632 {
1633 uint32_t dogval;
1634 send_ring_t *srp;
1635 srp = ngep->send;
1636 /*
1637 * Specific check for Tx stall ...
1638 *
1639 * The 'watchdog' counter is incremented whenever a packet
1640 * is queued, reset to 1 when some (but not all) buffers
1641 * are reclaimed, reset to 0 (disabled) when all buffers
1642 * are reclaimed, and shifted left here. If it exceeds the
1643 * threshold value, the chip is assumed to have stalled and
1644 * is put into the ERROR state. The factotum will then reset
1645 * it on the next pass.
1646 *
1647 * All of which should ensure that we don't get into a state
1648 * where packets are left pending indefinitely!
1649 */
1650 if (ngep->watchdog == 0 &&
1651 srp->tx_free < srp->desc.nslots)
1652 ngep->watchdog = 1;
1653 dogval = nge_atomic_shl32(&ngep->watchdog, 1);
1654 if (dogval >= nge_watchdog_check)
1655 nge_tx_recycle(ngep, B_FALSE);
1656 if (dogval < nge_watchdog_count)
1657 return (B_FALSE);
1658 else {
1659 ngep->statistics.sw_statistics.tx_stall++;
1660 return (B_TRUE);
1661 }
1662 }
1663
1664
1665 /*
1666 * The factotum is woken up when there's something to do that we'd rather
1667 * not do from inside a hardware interrupt handler or high-level cyclic.
1668 * Its two main tasks are:
1669 * reset & restart the chip after an error
1670 * check the link status whenever necessary
1671 */
1672 /* ARGSUSED */
1673 uint_t
nge_chip_factotum(caddr_t args1,caddr_t args2)1674 nge_chip_factotum(caddr_t args1, caddr_t args2)
1675 {
1676 uint_t result;
1677 nge_t *ngep;
1678 boolean_t err;
1679 boolean_t linkchg;
1680
1681 ngep = (nge_t *)args1;
1682
1683 NGE_TRACE(("nge_chip_factotum($%p)", (void *)ngep));
1684
1685 mutex_enter(ngep->softlock);
1686 if (ngep->factotum_flag == 0) {
1687 mutex_exit(ngep->softlock);
1688 return (DDI_INTR_UNCLAIMED);
1689 }
1690 ngep->factotum_flag = 0;
1691 mutex_exit(ngep->softlock);
1692 err = B_FALSE;
1693 linkchg = B_FALSE;
1694 result = DDI_INTR_CLAIMED;
1695
1696 mutex_enter(ngep->genlock);
1697 switch (ngep->nge_chip_state) {
1698 default:
1699 break;
1700
1701 case NGE_CHIP_RUNNING:
1702 linkchg = nge_factotum_link_check(ngep);
1703 err = nge_factotum_stall_check(ngep);
1704 break;
1705
1706 case NGE_CHIP_FAULT:
1707 (void) nge_restart(ngep);
1708 NGE_REPORT((ngep, "automatic recovery activated"));
1709 break;
1710 }
1711
1712 if (err)
1713 (void) nge_chip_stop(ngep, B_TRUE);
1714 mutex_exit(ngep->genlock);
1715
1716 /*
1717 * If the link state changed, tell the world about it (if
1718 * this version of MAC supports link state notification).
1719 * Note: can't do this while still holding the mutex.
1720 */
1721 if (linkchg)
1722 mac_link_update(ngep->mh, ngep->link_state);
1723
1724 return (result);
1725
1726 }
1727
1728 static void
nge_intr_handle(nge_t * ngep,nge_intr_src * pintr_src)1729 nge_intr_handle(nge_t *ngep, nge_intr_src *pintr_src)
1730 {
1731 boolean_t brx;
1732 boolean_t btx;
1733 nge_mintr_src mintr_src;
1734
1735 brx = B_FALSE;
1736 btx = B_FALSE;
1737 ngep->statistics.sw_statistics.intr_count++;
1738 ngep->statistics.sw_statistics.intr_lval = pintr_src->intr_val;
1739 brx = (pintr_src->int_bits.reint | pintr_src->int_bits.miss
1740 | pintr_src->int_bits.rcint | pintr_src->int_bits.stint)
1741 != 0 ? B_TRUE : B_FALSE;
1742 if (pintr_src->int_bits.reint)
1743 ngep->statistics.sw_statistics.rx_err++;
1744 if (pintr_src->int_bits.miss)
1745 ngep->statistics.sw_statistics.rx_nobuffer++;
1746
1747 btx = (pintr_src->int_bits.teint | pintr_src->int_bits.tfint)
1748 != 0 ? B_TRUE : B_FALSE;
1749 if (btx)
1750 nge_tx_recycle(ngep, B_TRUE);
1751 if (brx)
1752 nge_receive(ngep);
1753 if (pintr_src->int_bits.teint)
1754 ngep->statistics.sw_statistics.tx_stop_err++;
1755 if (ngep->intr_moderation && brx) {
1756 if (ngep->poll) {
1757 if (ngep->recv_count < ngep->param_rx_intr_hwater) {
1758 ngep->quiet_time++;
1759 if (ngep->quiet_time ==
1760 ngep->param_poll_quiet_time) {
1761 ngep->poll = B_FALSE;
1762 ngep->quiet_time = 0;
1763 }
1764 } else
1765 ngep->quiet_time = 0;
1766 } else {
1767 if (ngep->recv_count > ngep->param_rx_intr_lwater) {
1768 ngep->busy_time++;
1769 if (ngep->busy_time ==
1770 ngep->param_poll_busy_time) {
1771 ngep->poll = B_TRUE;
1772 ngep->busy_time = 0;
1773 }
1774 } else
1775 ngep->busy_time = 0;
1776 }
1777 }
1778 ngep->recv_count = 0;
1779 if (pintr_src->int_bits.feint)
1780 nge_chip_err(ngep);
1781 /* link interrupt, check the link state */
1782 if (pintr_src->int_bits.mint) {
1783 mintr_src.src_val = nge_reg_get32(ngep, NGE_MINTR_SRC);
1784 nge_reg_put32(ngep, NGE_MINTR_SRC, mintr_src.src_val);
1785 nge_wake_factotum(ngep);
1786 }
1787 }
1788
1789 /*
1790 * nge_chip_intr() -- handle chip interrupts
1791 */
1792 /* ARGSUSED */
1793 uint_t
nge_chip_intr(caddr_t arg1,caddr_t arg2)1794 nge_chip_intr(caddr_t arg1, caddr_t arg2)
1795 {
1796 nge_t *ngep = (nge_t *)arg1;
1797 nge_intr_src intr_src;
1798 nge_intr_mask intr_mask;
1799
1800 mutex_enter(ngep->genlock);
1801
1802 if (ngep->suspended) {
1803 mutex_exit(ngep->genlock);
1804 return (DDI_INTR_UNCLAIMED);
1805 }
1806
1807 /*
1808 * Check whether chip's says it's asserting #INTA;
1809 * if not, don't process or claim the interrupt.
1810 */
1811 intr_src.intr_val = nge_reg_get32(ngep, NGE_INTR_SRC);
1812 if (intr_src.intr_val == 0) {
1813 mutex_exit(ngep->genlock);
1814 return (DDI_INTR_UNCLAIMED);
1815 }
1816 /*
1817 * Ack the interrupt
1818 */
1819 nge_reg_put32(ngep, NGE_INTR_SRC, intr_src.intr_val);
1820
1821 if (ngep->nge_chip_state != NGE_CHIP_RUNNING) {
1822 mutex_exit(ngep->genlock);
1823 return (DDI_INTR_CLAIMED);
1824 }
1825 nge_intr_handle(ngep, &intr_src);
1826 if (ngep->poll && !ngep->ch_intr_mode) {
1827 intr_mask.mask_val = nge_reg_get32(ngep, NGE_INTR_MASK);
1828 intr_mask.mask_bits.stint = NGE_SET;
1829 intr_mask.mask_bits.rcint = NGE_CLEAR;
1830 nge_reg_put32(ngep, NGE_INTR_MASK, intr_mask.mask_val);
1831 ngep->ch_intr_mode = B_TRUE;
1832 } else if ((ngep->ch_intr_mode) && (!ngep->poll)) {
1833 nge_reg_put32(ngep, NGE_INTR_MASK, ngep->intr_masks);
1834 ngep->ch_intr_mode = B_FALSE;
1835 }
1836 mutex_exit(ngep->genlock);
1837 return (DDI_INTR_CLAIMED);
1838 }
1839
1840 #if NGE_DEBUGGING
1841 static enum ioc_reply
nge_pp_ioctl(nge_t * ngep,int cmd,mblk_t * mp,struct iocblk * iocp)1842 nge_pp_ioctl(nge_t *ngep, int cmd, mblk_t *mp, struct iocblk *iocp)
1843 {
1844 int err;
1845 uint64_t sizemask;
1846 uint64_t mem_va;
1847 uint64_t maxoff;
1848 boolean_t peek;
1849 nge_peekpoke_t *ppd;
1850 int (*ppfn)(nge_t *ngep, nge_peekpoke_t *ppd);
1851
1852 switch (cmd) {
1853 default:
1854 return (IOC_INVAL);
1855
1856 case NGE_PEEK:
1857 peek = B_TRUE;
1858 break;
1859
1860 case NGE_POKE:
1861 peek = B_FALSE;
1862 break;
1863 }
1864
1865 /*
1866 * Validate format of ioctl
1867 */
1868 if (iocp->ioc_count != sizeof (nge_peekpoke_t))
1869 return (IOC_INVAL);
1870 if (mp->b_cont == NULL)
1871 return (IOC_INVAL);
1872 ppd = (nge_peekpoke_t *)mp->b_cont->b_rptr;
1873
1874 /*
1875 * Validate request parameters
1876 */
1877 switch (ppd->pp_acc_space) {
1878 default:
1879 return (IOC_INVAL);
1880
1881 case NGE_PP_SPACE_CFG:
1882 /*
1883 * Config space
1884 */
1885 sizemask = 8|4|2|1;
1886 mem_va = 0;
1887 maxoff = PCI_CONF_HDR_SIZE;
1888 ppfn = peek ? nge_chip_peek_cfg : nge_chip_poke_cfg;
1889 break;
1890
1891 case NGE_PP_SPACE_REG:
1892 /*
1893 * Memory-mapped I/O space
1894 */
1895 sizemask = 8|4|2|1;
1896 mem_va = 0;
1897 maxoff = NGE_REG_SIZE;
1898 ppfn = peek ? nge_chip_peek_reg : nge_chip_poke_reg;
1899 break;
1900
1901 case NGE_PP_SPACE_MII:
1902 sizemask = 4|2|1;
1903 mem_va = 0;
1904 maxoff = NGE_MII_SIZE;
1905 ppfn = peek ? nge_chip_peek_mii : nge_chip_poke_mii;
1906 break;
1907
1908 case NGE_PP_SPACE_SEEPROM:
1909 sizemask = 4|2|1;
1910 mem_va = 0;
1911 maxoff = NGE_SEEROM_SIZE;
1912 ppfn = peek ? nge_chip_peek_seeprom : nge_chip_poke_seeprom;
1913 break;
1914 }
1915
1916 switch (ppd->pp_acc_size) {
1917 default:
1918 return (IOC_INVAL);
1919
1920 case 8:
1921 case 4:
1922 case 2:
1923 case 1:
1924 if ((ppd->pp_acc_size & sizemask) == 0)
1925 return (IOC_INVAL);
1926 break;
1927 }
1928
1929 if ((ppd->pp_acc_offset % ppd->pp_acc_size) != 0)
1930 return (IOC_INVAL);
1931
1932 if (ppd->pp_acc_offset >= maxoff)
1933 return (IOC_INVAL);
1934
1935 if (ppd->pp_acc_offset+ppd->pp_acc_size > maxoff)
1936 return (IOC_INVAL);
1937
1938 /*
1939 * All OK - go do it!
1940 */
1941 ppd->pp_acc_offset += mem_va;
1942 if (ppfn)
1943 err = (*ppfn)(ngep, ppd);
1944 if (err != DDI_SUCCESS)
1945 return (IOC_INVAL);
1946 return (peek ? IOC_REPLY : IOC_ACK);
1947 }
1948
1949 static enum ioc_reply nge_diag_ioctl(nge_t *ngep, int cmd, mblk_t *mp,
1950 struct iocblk *iocp);
1951
1952 static enum ioc_reply
nge_diag_ioctl(nge_t * ngep,int cmd,mblk_t * mp,struct iocblk * iocp)1953 nge_diag_ioctl(nge_t *ngep, int cmd, mblk_t *mp, struct iocblk *iocp)
1954 {
1955 ASSERT(mutex_owned(ngep->genlock));
1956
1957 switch (cmd) {
1958 default:
1959 nge_error(ngep, "nge_diag_ioctl: invalid cmd 0x%x", cmd);
1960 return (IOC_INVAL);
1961
1962 case NGE_DIAG:
1963 return (IOC_ACK);
1964
1965 case NGE_PEEK:
1966 case NGE_POKE:
1967 return (nge_pp_ioctl(ngep, cmd, mp, iocp));
1968
1969 case NGE_PHY_RESET:
1970 return (IOC_RESTART_ACK);
1971
1972 case NGE_SOFT_RESET:
1973 case NGE_HARD_RESET:
1974 return (IOC_ACK);
1975 }
1976
1977 /* NOTREACHED */
1978 }
1979 #endif /* NGE_DEBUGGING */
1980
1981 enum ioc_reply
nge_chip_ioctl(nge_t * ngep,mblk_t * mp,struct iocblk * iocp)1982 nge_chip_ioctl(nge_t *ngep, mblk_t *mp, struct iocblk *iocp)
1983 {
1984 int cmd;
1985
1986 ASSERT(mutex_owned(ngep->genlock));
1987
1988 cmd = iocp->ioc_cmd;
1989
1990 switch (cmd) {
1991 default:
1992 return (IOC_INVAL);
1993
1994 case NGE_DIAG:
1995 case NGE_PEEK:
1996 case NGE_POKE:
1997 case NGE_PHY_RESET:
1998 case NGE_SOFT_RESET:
1999 case NGE_HARD_RESET:
2000 #if NGE_DEBUGGING
2001 return (nge_diag_ioctl(ngep, cmd, mp, iocp));
2002 #else
2003 return (IOC_INVAL);
2004 #endif
2005
2006 case NGE_MII_READ:
2007 case NGE_MII_WRITE:
2008 return (IOC_INVAL);
2009
2010 #if NGE_SEE_IO32
2011 case NGE_SEE_READ:
2012 case NGE_SEE_WRITE:
2013 return (IOC_INVAL);
2014 #endif
2015
2016 #if NGE_FLASH_IO32
2017 case NGE_FLASH_READ:
2018 case NGE_FLASH_WRITE:
2019 return (IOC_INVAL);
2020 #endif
2021 }
2022 }
2023