1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /* Copyright(c) 2023 Realtek Corporation
3 */
4
5 #include "chan.h"
6 #include "coex.h"
7 #include "debug.h"
8 #include "efuse.h"
9 #include "fw.h"
10 #include "mac.h"
11 #include "phy.h"
12 #include "reg.h"
13 #include "rtw8922a.h"
14 #include "rtw8922a_rfk.h"
15 #include "sar.h"
16 #include "util.h"
17
18 #define RTW8922A_FW_FORMAT_MAX 4
19 #define RTW8922A_FW_BASENAME "rtw89/rtw8922a_fw"
20 #define RTW8922A_MODULE_FIRMWARE \
21 RTW8922A_FW_BASENAME "-" __stringify(RTW8922A_FW_FORMAT_MAX) ".bin"
22
23 #define HE_N_USER_MAX_8922A 4
24
25 static const struct rtw89_hfc_ch_cfg rtw8922a_hfc_chcfg_pcie[] = {
26 {2, 1641, grp_0}, /* ACH 0 */
27 {2, 1641, grp_0}, /* ACH 1 */
28 {2, 1641, grp_0}, /* ACH 2 */
29 {2, 1641, grp_0}, /* ACH 3 */
30 {2, 1641, grp_1}, /* ACH 4 */
31 {2, 1641, grp_1}, /* ACH 5 */
32 {2, 1641, grp_1}, /* ACH 6 */
33 {2, 1641, grp_1}, /* ACH 7 */
34 {2, 1641, grp_0}, /* B0MGQ */
35 {2, 1641, grp_0}, /* B0HIQ */
36 {2, 1641, grp_1}, /* B1MGQ */
37 {2, 1641, grp_1}, /* B1HIQ */
38 {0, 0, 0}, /* FWCMDQ */
39 {0, 0, 0}, /* BMC */
40 {0, 0, 0}, /* H2D */
41 };
42
43 static const struct rtw89_hfc_pub_cfg rtw8922a_hfc_pubcfg_pcie = {
44 1651, /* Group 0 */
45 1651, /* Group 1 */
46 3302, /* Public Max */
47 0, /* WP threshold */
48 };
49
50 static const struct rtw89_hfc_param_ini rtw8922a_hfc_param_ini_pcie[] = {
51 [RTW89_QTA_SCC] = {rtw8922a_hfc_chcfg_pcie, &rtw8922a_hfc_pubcfg_pcie,
52 &rtw89_mac_size.hfc_prec_cfg_c0, RTW89_HCIFC_POH},
53 [RTW89_QTA_DBCC] = {rtw8922a_hfc_chcfg_pcie, &rtw8922a_hfc_pubcfg_pcie,
54 &rtw89_mac_size.hfc_prec_cfg_c0, RTW89_HCIFC_POH},
55 [RTW89_QTA_DLFW] = {NULL, NULL, &rtw89_mac_size.hfc_prec_cfg_c2,
56 RTW89_HCIFC_POH},
57 [RTW89_QTA_INVALID] = {NULL},
58 };
59
60 static const struct rtw89_dle_mem rtw8922a_dle_mem_pcie[] = {
61 [RTW89_QTA_SCC] = {RTW89_QTA_SCC, &rtw89_mac_size.wde_size0_v1,
62 &rtw89_mac_size.ple_size0_v1, &rtw89_mac_size.wde_qt0_v1,
63 &rtw89_mac_size.wde_qt0_v1, &rtw89_mac_size.ple_qt0,
64 &rtw89_mac_size.ple_qt1, &rtw89_mac_size.ple_rsvd_qt0,
65 &rtw89_mac_size.rsvd0_size0, &rtw89_mac_size.rsvd1_size0},
66 [RTW89_QTA_DBCC] = {RTW89_QTA_DBCC, &rtw89_mac_size.wde_size0_v1,
67 &rtw89_mac_size.ple_size0_v1, &rtw89_mac_size.wde_qt0_v1,
68 &rtw89_mac_size.wde_qt0_v1, &rtw89_mac_size.ple_qt0,
69 &rtw89_mac_size.ple_qt1, &rtw89_mac_size.ple_rsvd_qt0,
70 &rtw89_mac_size.rsvd0_size0, &rtw89_mac_size.rsvd1_size0},
71 [RTW89_QTA_DLFW] = {RTW89_QTA_DLFW, &rtw89_mac_size.wde_size4_v1,
72 &rtw89_mac_size.ple_size3_v1, &rtw89_mac_size.wde_qt4,
73 &rtw89_mac_size.wde_qt4, &rtw89_mac_size.ple_qt9,
74 &rtw89_mac_size.ple_qt9, &rtw89_mac_size.ple_rsvd_qt1,
75 &rtw89_mac_size.rsvd0_size0, &rtw89_mac_size.rsvd1_size0},
76 [RTW89_QTA_INVALID] = {RTW89_QTA_INVALID, NULL, NULL, NULL, NULL, NULL,
77 NULL},
78 };
79
80 static const u32 rtw8922a_h2c_regs[RTW89_H2CREG_MAX] = {
81 R_BE_H2CREG_DATA0, R_BE_H2CREG_DATA1, R_BE_H2CREG_DATA2,
82 R_BE_H2CREG_DATA3
83 };
84
85 static const u32 rtw8922a_c2h_regs[RTW89_H2CREG_MAX] = {
86 R_BE_C2HREG_DATA0, R_BE_C2HREG_DATA1, R_BE_C2HREG_DATA2,
87 R_BE_C2HREG_DATA3
88 };
89
90 static const u32 rtw8922a_wow_wakeup_regs[RTW89_WOW_REASON_NUM] = {
91 R_AX_C2HREG_DATA3_V1 + 3, R_BE_DBG_WOW,
92 };
93
94 static const struct rtw89_page_regs rtw8922a_page_regs = {
95 .hci_fc_ctrl = R_BE_HCI_FC_CTRL,
96 .ch_page_ctrl = R_BE_CH_PAGE_CTRL,
97 .ach_page_ctrl = R_BE_CH0_PAGE_CTRL,
98 .ach_page_info = R_BE_CH0_PAGE_INFO,
99 .pub_page_info3 = R_BE_PUB_PAGE_INFO3,
100 .pub_page_ctrl1 = R_BE_PUB_PAGE_CTRL1,
101 .pub_page_ctrl2 = R_BE_PUB_PAGE_CTRL2,
102 .pub_page_info1 = R_BE_PUB_PAGE_INFO1,
103 .pub_page_info2 = R_BE_PUB_PAGE_INFO2,
104 .wp_page_ctrl1 = R_BE_WP_PAGE_CTRL1,
105 .wp_page_ctrl2 = R_BE_WP_PAGE_CTRL2,
106 .wp_page_info1 = R_BE_WP_PAGE_INFO1,
107 };
108
109 static const struct rtw89_reg_imr rtw8922a_imr_dmac_regs[] = {
110 {R_BE_DISP_HOST_IMR, B_BE_DISP_HOST_IMR_CLR, B_BE_DISP_HOST_IMR_SET},
111 {R_BE_DISP_CPU_IMR, B_BE_DISP_CPU_IMR_CLR, B_BE_DISP_CPU_IMR_SET},
112 {R_BE_DISP_OTHER_IMR, B_BE_DISP_OTHER_IMR_CLR, B_BE_DISP_OTHER_IMR_SET},
113 {R_BE_PKTIN_ERR_IMR, B_BE_PKTIN_ERR_IMR_CLR, B_BE_PKTIN_ERR_IMR_SET},
114 {R_BE_INTERRUPT_MASK_REG, B_BE_INTERRUPT_MASK_REG_CLR, B_BE_INTERRUPT_MASK_REG_SET},
115 {R_BE_MLO_ERR_IDCT_IMR, B_BE_MLO_ERR_IDCT_IMR_CLR, B_BE_MLO_ERR_IDCT_IMR_SET},
116 {R_BE_MPDU_TX_ERR_IMR, B_BE_MPDU_TX_ERR_IMR_CLR, B_BE_MPDU_TX_ERR_IMR_SET},
117 {R_BE_MPDU_RX_ERR_IMR, B_BE_MPDU_RX_ERR_IMR_CLR, B_BE_MPDU_RX_ERR_IMR_SET},
118 {R_BE_SEC_ERROR_IMR, B_BE_SEC_ERROR_IMR_CLR, B_BE_SEC_ERROR_IMR_SET},
119 {R_BE_CPUIO_ERR_IMR, B_BE_CPUIO_ERR_IMR_CLR, B_BE_CPUIO_ERR_IMR_SET},
120 {R_BE_WDE_ERR_IMR, B_BE_WDE_ERR_IMR_CLR, B_BE_WDE_ERR_IMR_SET},
121 {R_BE_WDE_ERR1_IMR, B_BE_WDE_ERR1_IMR_CLR, B_BE_WDE_ERR1_IMR_SET},
122 {R_BE_PLE_ERR_IMR, B_BE_PLE_ERR_IMR_CLR, B_BE_PLE_ERR_IMR_SET},
123 {R_BE_PLE_ERRFLAG1_IMR, B_BE_PLE_ERRFLAG1_IMR_CLR, B_BE_PLE_ERRFLAG1_IMR_SET},
124 {R_BE_WDRLS_ERR_IMR, B_BE_WDRLS_ERR_IMR_CLR, B_BE_WDRLS_ERR_IMR_SET},
125 {R_BE_TXPKTCTL_B0_ERRFLAG_IMR, B_BE_TXPKTCTL_B0_ERRFLAG_IMR_CLR,
126 B_BE_TXPKTCTL_B0_ERRFLAG_IMR_SET},
127 {R_BE_TXPKTCTL_B1_ERRFLAG_IMR, B_BE_TXPKTCTL_B1_ERRFLAG_IMR_CLR,
128 B_BE_TXPKTCTL_B1_ERRFLAG_IMR_SET},
129 {R_BE_BBRPT_COM_ERR_IMR, B_BE_BBRPT_COM_ERR_IMR_CLR, B_BE_BBRPT_COM_ERR_IMR_SET},
130 {R_BE_BBRPT_CHINFO_ERR_IMR, B_BE_BBRPT_CHINFO_ERR_IMR_CLR,
131 B_BE_BBRPT_CHINFO_ERR_IMR_SET},
132 {R_BE_BBRPT_DFS_ERR_IMR, B_BE_BBRPT_DFS_ERR_IMR_CLR, B_BE_BBRPT_DFS_ERR_IMR_SET},
133 {R_BE_LA_ERRFLAG_IMR, B_BE_LA_ERRFLAG_IMR_CLR, B_BE_LA_ERRFLAG_IMR_SET},
134 {R_BE_CH_INFO_DBGFLAG_IMR, B_BE_CH_INFO_DBGFLAG_IMR_CLR, B_BE_CH_INFO_DBGFLAG_IMR_SET},
135 {R_BE_PLRLS_ERR_IMR, B_BE_PLRLS_ERR_IMR_CLR, B_BE_PLRLS_ERR_IMR_SET},
136 {R_BE_HAXI_IDCT_MSK, B_BE_HAXI_IDCT_MSK_CLR, B_BE_HAXI_IDCT_MSK_SET},
137 };
138
139 static const struct rtw89_imr_table rtw8922a_imr_dmac_table = {
140 .regs = rtw8922a_imr_dmac_regs,
141 .n_regs = ARRAY_SIZE(rtw8922a_imr_dmac_regs),
142 };
143
144 static const struct rtw89_reg_imr rtw8922a_imr_cmac_regs[] = {
145 {R_BE_RESP_IMR, B_BE_RESP_IMR_CLR, B_BE_RESP_IMR_SET},
146 {R_BE_RX_ERROR_FLAG_IMR, B_BE_RX_ERROR_FLAG_IMR_CLR, B_BE_RX_ERROR_FLAG_IMR_SET},
147 {R_BE_TX_ERROR_FLAG_IMR, B_BE_TX_ERROR_FLAG_IMR_CLR, B_BE_TX_ERROR_FLAG_IMR_SET},
148 {R_BE_RX_ERROR_FLAG_IMR_1, B_BE_TX_ERROR_FLAG_IMR_1_CLR, B_BE_TX_ERROR_FLAG_IMR_1_SET},
149 {R_BE_PTCL_IMR1, B_BE_PTCL_IMR1_CLR, B_BE_PTCL_IMR1_SET},
150 {R_BE_PTCL_IMR0, B_BE_PTCL_IMR0_CLR, B_BE_PTCL_IMR0_SET},
151 {R_BE_PTCL_IMR_2, B_BE_PTCL_IMR_2_CLR, B_BE_PTCL_IMR_2_SET},
152 {R_BE_SCHEDULE_ERR_IMR, B_BE_SCHEDULE_ERR_IMR_CLR, B_BE_SCHEDULE_ERR_IMR_SET},
153 {R_BE_C0_TXPWR_IMR, B_BE_C0_TXPWR_IMR_CLR, B_BE_C0_TXPWR_IMR_SET},
154 {R_BE_TRXPTCL_ERROR_INDICA_MASK, B_BE_TRXPTCL_ERROR_INDICA_MASK_CLR,
155 B_BE_TRXPTCL_ERROR_INDICA_MASK_SET},
156 {R_BE_RX_ERR_IMR, B_BE_RX_ERR_IMR_CLR, B_BE_RX_ERR_IMR_SET},
157 {R_BE_PHYINFO_ERR_IMR_V1, B_BE_PHYINFO_ERR_IMR_V1_CLR, B_BE_PHYINFO_ERR_IMR_V1_SET},
158 };
159
160 static const struct rtw89_imr_table rtw8922a_imr_cmac_table = {
161 .regs = rtw8922a_imr_cmac_regs,
162 .n_regs = ARRAY_SIZE(rtw8922a_imr_cmac_regs),
163 };
164
165 static const struct rtw89_rrsr_cfgs rtw8922a_rrsr_cfgs = {
166 .ref_rate = {R_BE_TRXPTCL_RESP_1, B_BE_WMAC_RESP_REF_RATE_SEL, 0},
167 .rsc = {R_BE_PTCL_RRSR1, B_BE_RSC_MASK, 2},
168 };
169
170 static const struct rtw89_rfkill_regs rtw8922a_rfkill_regs = {
171 .pinmux = {R_BE_GPIO8_15_FUNC_SEL,
172 B_BE_PINMUX_GPIO9_FUNC_SEL_MASK,
173 0xf},
174 .mode = {R_BE_GPIO_EXT_CTRL + 2,
175 (B_BE_GPIO_MOD_9 | B_BE_GPIO_IO_SEL_9) >> 16,
176 0x0},
177 };
178
179 static const struct rtw89_dig_regs rtw8922a_dig_regs = {
180 .seg0_pd_reg = R_SEG0R_PD_V2,
181 .pd_lower_bound_mask = B_SEG0R_PD_LOWER_BOUND_MSK,
182 .pd_spatial_reuse_en = B_SEG0R_PD_SPATIAL_REUSE_EN_MSK_V1,
183 .bmode_pd_reg = R_BMODE_PDTH_EN_V2,
184 .bmode_cca_rssi_limit_en = B_BMODE_PDTH_LIMIT_EN_MSK_V1,
185 .bmode_pd_lower_bound_reg = R_BMODE_PDTH_V2,
186 .bmode_rssi_nocca_low_th_mask = B_BMODE_PDTH_LOWER_BOUND_MSK_V1,
187 .p0_lna_init = {R_PATH0_LNA_INIT_V1, B_PATH0_LNA_INIT_IDX_MSK},
188 .p1_lna_init = {R_PATH1_LNA_INIT_V1, B_PATH1_LNA_INIT_IDX_MSK},
189 .p0_tia_init = {R_PATH0_TIA_INIT_V1, B_PATH0_TIA_INIT_IDX_MSK_V1},
190 .p1_tia_init = {R_PATH1_TIA_INIT_V1, B_PATH1_TIA_INIT_IDX_MSK_V1},
191 .p0_rxb_init = {R_PATH0_RXB_INIT_V1, B_PATH0_RXB_INIT_IDX_MSK_V1},
192 .p1_rxb_init = {R_PATH1_RXB_INIT_V1, B_PATH1_RXB_INIT_IDX_MSK_V1},
193 .p0_p20_pagcugc_en = {R_PATH0_P20_FOLLOW_BY_PAGCUGC_V3,
194 B_PATH0_P20_FOLLOW_BY_PAGCUGC_EN_MSK},
195 .p0_s20_pagcugc_en = {R_PATH0_S20_FOLLOW_BY_PAGCUGC_V3,
196 B_PATH0_S20_FOLLOW_BY_PAGCUGC_EN_MSK},
197 .p1_p20_pagcugc_en = {R_PATH1_P20_FOLLOW_BY_PAGCUGC_V3,
198 B_PATH1_P20_FOLLOW_BY_PAGCUGC_EN_MSK},
199 .p1_s20_pagcugc_en = {R_PATH1_S20_FOLLOW_BY_PAGCUGC_V3,
200 B_PATH1_S20_FOLLOW_BY_PAGCUGC_EN_MSK},
201 };
202
203 static const struct rtw89_edcca_regs rtw8922a_edcca_regs = {
204 .edcca_level = R_SEG0R_EDCCA_LVL_BE,
205 .edcca_mask = B_EDCCA_LVL_MSK0,
206 .edcca_p_mask = B_EDCCA_LVL_MSK1,
207 .ppdu_level = R_SEG0R_PPDU_LVL_BE,
208 .ppdu_mask = B_EDCCA_LVL_MSK1,
209 .p = {{
210 .rpt_a = R_EDCCA_RPT_A_BE,
211 .rpt_b = R_EDCCA_RPT_B_BE,
212 .rpt_sel = R_EDCCA_RPT_SEL_BE,
213 .rpt_sel_mask = B_EDCCA_RPT_SEL_MSK,
214 }, {
215 .rpt_a = R_EDCCA_RPT_P1_A_BE,
216 .rpt_b = R_EDCCA_RPT_P1_B_BE,
217 .rpt_sel = R_EDCCA_RPT_SEL_BE,
218 .rpt_sel_mask = B_EDCCA_RPT_SEL_P1_MSK,
219 }},
220 .rpt_sel_be = R_EDCCA_RPTREG_SEL_BE,
221 .rpt_sel_be_mask = B_EDCCA_RPTREG_SEL_BE_MSK,
222 .tx_collision_t2r_st = R_TX_COLLISION_T2R_ST_BE,
223 .tx_collision_t2r_st_mask = B_TX_COLLISION_T2R_ST_BE_M,
224 };
225
226 static const struct rtw89_efuse_block_cfg rtw8922a_efuse_blocks[] = {
227 [RTW89_EFUSE_BLOCK_SYS] = {.offset = 0x00000, .size = 0x310},
228 [RTW89_EFUSE_BLOCK_RF] = {.offset = 0x10000, .size = 0x240},
229 [RTW89_EFUSE_BLOCK_HCI_DIG_PCIE_SDIO] = {.offset = 0x20000, .size = 0x4800},
230 [RTW89_EFUSE_BLOCK_HCI_DIG_USB] = {.offset = 0x30000, .size = 0x890},
231 [RTW89_EFUSE_BLOCK_HCI_PHY_PCIE] = {.offset = 0x40000, .size = 0x200},
232 [RTW89_EFUSE_BLOCK_HCI_PHY_USB3] = {.offset = 0x50000, .size = 0x80},
233 [RTW89_EFUSE_BLOCK_HCI_PHY_USB2] = {.offset = 0x60000, .size = 0x0},
234 [RTW89_EFUSE_BLOCK_ADIE] = {.offset = 0x70000, .size = 0x10},
235 };
236
rtw8922a_ctrl_btg_bt_rx(struct rtw89_dev * rtwdev,bool en,enum rtw89_phy_idx phy_idx)237 static void rtw8922a_ctrl_btg_bt_rx(struct rtw89_dev *rtwdev, bool en,
238 enum rtw89_phy_idx phy_idx)
239 {
240 if (en) {
241 rtw89_phy_write32_idx(rtwdev, R_BT_SHARE_A, B_BT_SHARE_A, 0x1, phy_idx);
242 rtw89_phy_write32_idx(rtwdev, R_BT_SHARE_A, B_BTG_PATH_A, 0x0, phy_idx);
243 rtw89_phy_write32_idx(rtwdev, R_BT_SHARE_B, B_BT_SHARE_B, 0x1, phy_idx);
244 rtw89_phy_write32_idx(rtwdev, R_BT_SHARE_B, B_BTG_PATH_B, 0x1, phy_idx);
245 rtw89_phy_write32_idx(rtwdev, R_LNA_OP, B_LNA6, 0x20, phy_idx);
246 rtw89_phy_write32_idx(rtwdev, R_LNA_TIA, B_TIA0_B, 0x30, phy_idx);
247 rtw89_phy_write32_idx(rtwdev, R_PMAC_GNT, B_PMAC_GNT_P1, 0x0, phy_idx);
248 rtw89_phy_write32_idx(rtwdev, R_ANT_CHBW, B_ANT_BT_SHARE, 0x1, phy_idx);
249 rtw89_phy_write32_idx(rtwdev, R_FC0INV_SBW, B_RX_BT_SG0, 0x2, phy_idx);
250 rtw89_phy_write32_idx(rtwdev, R_GNT_BT_WGT_EN, B_GNT_BT_WGT_EN,
251 0x1, phy_idx);
252 } else {
253 rtw89_phy_write32_idx(rtwdev, R_BT_SHARE_A, B_BT_SHARE_A, 0x0, phy_idx);
254 rtw89_phy_write32_idx(rtwdev, R_BT_SHARE_A, B_BTG_PATH_A, 0x0, phy_idx);
255 rtw89_phy_write32_idx(rtwdev, R_BT_SHARE_B, B_BT_SHARE_B, 0x0, phy_idx);
256 rtw89_phy_write32_idx(rtwdev, R_BT_SHARE_B, B_BTG_PATH_B, 0x0, phy_idx);
257 rtw89_phy_write32_idx(rtwdev, R_LNA_OP, B_LNA6, 0x1a, phy_idx);
258 rtw89_phy_write32_idx(rtwdev, R_LNA_TIA, B_TIA0_B, 0x2a, phy_idx);
259 rtw89_phy_write32_idx(rtwdev, R_PMAC_GNT, B_PMAC_GNT_P1, 0xc, phy_idx);
260 rtw89_phy_write32_idx(rtwdev, R_ANT_CHBW, B_ANT_BT_SHARE, 0x0, phy_idx);
261 rtw89_phy_write32_idx(rtwdev, R_FC0INV_SBW, B_RX_BT_SG0, 0x0, phy_idx);
262 rtw89_phy_write32_idx(rtwdev, R_GNT_BT_WGT_EN, B_GNT_BT_WGT_EN,
263 0x0, phy_idx);
264 }
265 }
266
rtw8922a_pwr_on_func(struct rtw89_dev * rtwdev)267 static int rtw8922a_pwr_on_func(struct rtw89_dev *rtwdev)
268 {
269 struct rtw89_hal *hal = &rtwdev->hal;
270 u32 val32;
271 int ret;
272
273 rtw89_write32_clr(rtwdev, R_BE_SYS_PW_CTRL, B_BE_AFSM_WLSUS_EN |
274 B_BE_AFSM_PCIE_SUS_EN);
275 rtw89_write32_set(rtwdev, R_BE_SYS_PW_CTRL, B_BE_DIS_WLBT_PDNSUSEN_SOPC);
276 rtw89_write32_set(rtwdev, R_BE_WLLPS_CTRL, B_BE_DIS_WLBT_LPSEN_LOPC);
277 rtw89_write32_clr(rtwdev, R_BE_SYS_PW_CTRL, B_BE_APDM_HPDN);
278 rtw89_write32_clr(rtwdev, R_BE_SYS_PW_CTRL, B_BE_APFM_SWLPS);
279
280 ret = read_poll_timeout(rtw89_read32, val32, val32 & B_BE_RDY_SYSPWR,
281 1000, 3000000, false, rtwdev, R_BE_SYS_PW_CTRL);
282 if (ret)
283 return ret;
284
285 rtw89_write32_set(rtwdev, R_BE_SYS_PW_CTRL, B_BE_EN_WLON);
286 rtw89_write32_set(rtwdev, R_BE_WLRESUME_CTRL, B_BE_LPSROP_CMAC0 |
287 B_BE_LPSROP_CMAC1);
288 rtw89_write32_set(rtwdev, R_BE_SYS_PW_CTRL, B_BE_APFN_ONMAC);
289
290 ret = read_poll_timeout(rtw89_read32, val32, !(val32 & B_BE_APFN_ONMAC),
291 1000, 3000000, false, rtwdev, R_BE_SYS_PW_CTRL);
292 if (ret)
293 return ret;
294
295 rtw89_write32_clr(rtwdev, R_BE_AFE_ON_CTRL1, B_BE_REG_CK_MON_CK960M_EN);
296 rtw89_write8_set(rtwdev, R_BE_ANAPAR_POW_MAC, B_BE_POW_PC_LDO_PORT0 |
297 B_BE_POW_PC_LDO_PORT1);
298 rtw89_write32_clr(rtwdev, R_BE_FEN_RST_ENABLE, B_BE_R_SYM_ISO_ADDA_P02PP |
299 B_BE_R_SYM_ISO_ADDA_P12PP);
300 rtw89_write8_set(rtwdev, R_BE_PLATFORM_ENABLE, B_BE_PLATFORM_EN);
301 rtw89_write32_set(rtwdev, R_BE_HCI_OPT_CTRL, B_BE_HAXIDMA_IO_EN);
302
303 ret = read_poll_timeout(rtw89_read32, val32, val32 & B_BE_HAXIDMA_IO_ST,
304 1000, 3000000, false, rtwdev, R_BE_HCI_OPT_CTRL);
305 if (ret)
306 return ret;
307
308 ret = read_poll_timeout(rtw89_read32, val32, !(val32 & B_BE_HAXIDMA_BACKUP_RESTORE_ST),
309 1000, 3000000, false, rtwdev, R_BE_HCI_OPT_CTRL);
310 if (ret)
311 return ret;
312
313 rtw89_write32_set(rtwdev, R_BE_HCI_OPT_CTRL, B_BE_HCI_WLAN_IO_EN);
314
315 ret = read_poll_timeout(rtw89_read32, val32, val32 & B_BE_HCI_WLAN_IO_ST,
316 1000, 3000000, false, rtwdev, R_BE_HCI_OPT_CTRL);
317 if (ret)
318 return ret;
319
320 rtw89_write32_clr(rtwdev, R_BE_SYS_SDIO_CTRL, B_BE_PCIE_FORCE_IBX_EN);
321
322 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_PLL, 0x02, 0x02);
323 if (ret)
324 return ret;
325 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_PLL, 0x01, 0x01);
326 if (ret)
327 return ret;
328
329 rtw89_write32_set(rtwdev, R_BE_SYS_ADIE_PAD_PWR_CTRL, B_BE_SYM_PADPDN_WL_RFC1_1P3);
330
331 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0x40, 0x40);
332 if (ret)
333 return ret;
334
335 rtw89_write32_set(rtwdev, R_BE_SYS_ADIE_PAD_PWR_CTRL, B_BE_SYM_PADPDN_WL_RFC0_1P3);
336
337 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0x20, 0x20);
338 if (ret)
339 return ret;
340 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0x04, 0x04);
341 if (ret)
342 return ret;
343 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0x08, 0x08);
344 if (ret)
345 return ret;
346 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, 0x10);
347 if (ret)
348 return ret;
349 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S0, 0xEB, 0xFF);
350 if (ret)
351 return ret;
352 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S1, 0xEB, 0xFF);
353 if (ret)
354 return ret;
355 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0x01, 0x01);
356 if (ret)
357 return ret;
358 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0x02, 0x02);
359 if (ret)
360 return ret;
361 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, 0x80);
362 if (ret)
363 return ret;
364 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_XREF_RF1, 0, 0x40);
365 if (ret)
366 return ret;
367 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_XREF_RF2, 0, 0x40);
368 if (ret)
369 return ret;
370 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_PLL_1, 0x40, 0x60);
371 if (ret)
372 return ret;
373
374 if (hal->cv != CHIP_CAV) {
375 rtw89_write32_set(rtwdev, R_BE_PMC_DBG_CTRL2, B_BE_SYSON_DIS_PMCR_BE_WRMSK);
376 rtw89_write32_set(rtwdev, R_BE_SYS_ISO_CTRL, B_BE_ISO_EB2CORE);
377 rtw89_write32_clr(rtwdev, R_BE_SYS_ISO_CTRL, B_BE_PWC_EV2EF_B);
378
379 mdelay(1);
380
381 rtw89_write32_clr(rtwdev, R_BE_SYS_ISO_CTRL, B_BE_PWC_EV2EF_S);
382 rtw89_write32_clr(rtwdev, R_BE_PMC_DBG_CTRL2, B_BE_SYSON_DIS_PMCR_BE_WRMSK);
383 }
384
385 rtw89_write32_set(rtwdev, R_BE_DMAC_FUNC_EN,
386 B_BE_MAC_FUNC_EN | B_BE_DMAC_FUNC_EN | B_BE_MPDU_PROC_EN |
387 B_BE_WD_RLS_EN | B_BE_DLE_WDE_EN | B_BE_TXPKT_CTRL_EN |
388 B_BE_STA_SCH_EN | B_BE_DLE_PLE_EN | B_BE_PKT_BUF_EN |
389 B_BE_DMAC_TBL_EN | B_BE_PKT_IN_EN | B_BE_DLE_CPUIO_EN |
390 B_BE_DISPATCHER_EN | B_BE_BBRPT_EN | B_BE_MAC_SEC_EN |
391 B_BE_H_AXIDMA_EN | B_BE_DMAC_MLO_EN | B_BE_PLRLS_EN |
392 B_BE_P_AXIDMA_EN | B_BE_DLE_DATACPUIO_EN | B_BE_LTR_CTL_EN);
393
394 set_bit(RTW89_FLAG_DMAC_FUNC, rtwdev->flags);
395
396 rtw89_write32_set(rtwdev, R_BE_CMAC_SHARE_FUNC_EN,
397 B_BE_CMAC_SHARE_EN | B_BE_RESPBA_EN | B_BE_ADDRSRCH_EN |
398 B_BE_BTCOEX_EN);
399 rtw89_write32_set(rtwdev, R_BE_CMAC_FUNC_EN,
400 B_BE_CMAC_EN | B_BE_CMAC_TXEN | B_BE_CMAC_RXEN |
401 B_BE_SIGB_EN | B_BE_PHYINTF_EN | B_BE_CMAC_DMA_EN |
402 B_BE_PTCLTOP_EN | B_BE_SCHEDULER_EN | B_BE_TMAC_EN |
403 B_BE_RMAC_EN | B_BE_TXTIME_EN | B_BE_RESP_PKTCTL_EN);
404
405 set_bit(RTW89_FLAG_CMAC0_FUNC, rtwdev->flags);
406
407 rtw89_write32_set(rtwdev, R_BE_FEN_RST_ENABLE, B_BE_FEN_BB_IP_RSTN |
408 B_BE_FEN_BBPLAT_RSTB);
409
410 return 0;
411 }
412
rtw8922a_pwr_off_func(struct rtw89_dev * rtwdev)413 static int rtw8922a_pwr_off_func(struct rtw89_dev *rtwdev)
414 {
415 u32 val32;
416 int ret;
417
418 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0x10, 0x10);
419 if (ret)
420 return ret;
421 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, 0x08);
422 if (ret)
423 return ret;
424 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, 0x04);
425 if (ret)
426 return ret;
427 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S0, 0xC6, 0xFF);
428 if (ret)
429 return ret;
430 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S1, 0xC6, 0xFF);
431 if (ret)
432 return ret;
433 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0x80, 0x80);
434 if (ret)
435 return ret;
436 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, 0x02);
437 if (ret)
438 return ret;
439 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, 0x01);
440 if (ret)
441 return ret;
442 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_PLL, 0x02, 0xFF);
443 if (ret)
444 return ret;
445 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_PLL, 0x00, 0xFF);
446 if (ret)
447 return ret;
448
449 rtw89_write32_set(rtwdev, R_BE_FEN_RST_ENABLE, B_BE_R_SYM_ISO_ADDA_P02PP |
450 B_BE_R_SYM_ISO_ADDA_P12PP);
451 rtw89_write8_clr(rtwdev, R_BE_ANAPAR_POW_MAC, B_BE_POW_PC_LDO_PORT0 |
452 B_BE_POW_PC_LDO_PORT1);
453 rtw89_write32_set(rtwdev, R_BE_SYS_PW_CTRL, B_BE_EN_WLON);
454 rtw89_write8_clr(rtwdev, R_BE_FEN_RST_ENABLE, B_BE_FEN_BB_IP_RSTN |
455 B_BE_FEN_BBPLAT_RSTB);
456 rtw89_write32_clr(rtwdev, R_BE_SYS_ADIE_PAD_PWR_CTRL, B_BE_SYM_PADPDN_WL_RFC0_1P3);
457
458 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, 0x20);
459 if (ret)
460 return ret;
461
462 rtw89_write32_clr(rtwdev, R_BE_SYS_ADIE_PAD_PWR_CTRL, B_BE_SYM_PADPDN_WL_RFC1_1P3);
463
464 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, 0x40);
465 if (ret)
466 return ret;
467
468 rtw89_write32_clr(rtwdev, R_BE_HCI_OPT_CTRL, B_BE_HAXIDMA_IO_EN);
469
470 ret = read_poll_timeout(rtw89_read32, val32, !(val32 & B_BE_HAXIDMA_IO_ST),
471 1000, 3000000, false, rtwdev, R_BE_HCI_OPT_CTRL);
472 if (ret)
473 return ret;
474
475 ret = read_poll_timeout(rtw89_read32, val32, !(val32 & B_BE_HAXIDMA_BACKUP_RESTORE_ST),
476 1000, 3000000, false, rtwdev, R_BE_HCI_OPT_CTRL);
477 if (ret)
478 return ret;
479
480 rtw89_write32_clr(rtwdev, R_BE_HCI_OPT_CTRL, B_BE_HCI_WLAN_IO_EN);
481
482 ret = read_poll_timeout(rtw89_read32, val32, !(val32 & B_BE_HCI_WLAN_IO_ST),
483 1000, 3000000, false, rtwdev, R_BE_HCI_OPT_CTRL);
484 if (ret)
485 return ret;
486
487 rtw89_write32_set(rtwdev, R_BE_SYS_PW_CTRL, B_BE_APFM_OFFMAC);
488
489 ret = read_poll_timeout(rtw89_read32, val32, !(val32 & B_BE_APFM_OFFMAC),
490 1000, 3000000, false, rtwdev, R_BE_SYS_PW_CTRL);
491 if (ret)
492 return ret;
493
494 rtw89_write32(rtwdev, R_BE_WLLPS_CTRL, 0x0000A1B2);
495 rtw89_write32_set(rtwdev, R_BE_SYS_PW_CTRL, B_BE_XTAL_OFF_A_DIE);
496 rtw89_write32_set(rtwdev, R_BE_SYS_PW_CTRL, B_BE_APFM_SWLPS);
497 rtw89_write32(rtwdev, R_BE_UDM1, 0);
498
499 return 0;
500 }
501
rtw8922a_efuse_parsing_tssi(struct rtw89_dev * rtwdev,struct rtw8922a_efuse * map)502 static void rtw8922a_efuse_parsing_tssi(struct rtw89_dev *rtwdev,
503 struct rtw8922a_efuse *map)
504 {
505 struct rtw8922a_tssi_offset *ofst[] = {&map->path_a_tssi, &map->path_b_tssi};
506 u8 *bw40_1s_tssi_6g_ofst[] = {map->bw40_1s_tssi_6g_a, map->bw40_1s_tssi_6g_b};
507 struct rtw89_tssi_info *tssi = &rtwdev->tssi;
508 u8 i, j;
509
510 tssi->thermal[RF_PATH_A] = map->path_a_therm;
511 tssi->thermal[RF_PATH_B] = map->path_b_therm;
512
513 for (i = 0; i < RF_PATH_NUM_8922A; i++) {
514 memcpy(tssi->tssi_cck[i], ofst[i]->cck_tssi,
515 sizeof(ofst[i]->cck_tssi));
516
517 for (j = 0; j < TSSI_CCK_CH_GROUP_NUM; j++)
518 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
519 "[TSSI][EFUSE] path=%d cck[%d]=0x%x\n",
520 i, j, tssi->tssi_cck[i][j]);
521
522 memcpy(tssi->tssi_mcs[i], ofst[i]->bw40_tssi,
523 sizeof(ofst[i]->bw40_tssi));
524 memcpy(tssi->tssi_mcs[i] + TSSI_MCS_2G_CH_GROUP_NUM,
525 ofst[i]->bw40_1s_tssi_5g, sizeof(ofst[i]->bw40_1s_tssi_5g));
526 memcpy(tssi->tssi_6g_mcs[i], bw40_1s_tssi_6g_ofst[i],
527 sizeof(tssi->tssi_6g_mcs[i]));
528
529 for (j = 0; j < TSSI_MCS_CH_GROUP_NUM; j++)
530 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
531 "[TSSI][EFUSE] path=%d mcs[%d]=0x%x\n",
532 i, j, tssi->tssi_mcs[i][j]);
533 }
534 }
535
rtw8922a_efuse_parsing_gain_offset(struct rtw89_dev * rtwdev,struct rtw8922a_efuse * map)536 static void rtw8922a_efuse_parsing_gain_offset(struct rtw89_dev *rtwdev,
537 struct rtw8922a_efuse *map)
538 {
539 struct rtw89_phy_efuse_gain *gain = &rtwdev->efuse_gain;
540 bool all_0xff = true, all_0x00 = true;
541 int i, j;
542 u8 t;
543
544 gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_2G_CCK] = map->rx_gain_a._2g_cck;
545 gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_2G_CCK] = map->rx_gain_b._2g_cck;
546 gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_2G_OFDM] = map->rx_gain_a._2g_ofdm;
547 gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_2G_OFDM] = map->rx_gain_b._2g_ofdm;
548 gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_5G_LOW] = map->rx_gain_a._5g_low;
549 gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_5G_LOW] = map->rx_gain_b._5g_low;
550 gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_5G_MID] = map->rx_gain_a._5g_mid;
551 gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_5G_MID] = map->rx_gain_b._5g_mid;
552 gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_5G_HIGH] = map->rx_gain_a._5g_high;
553 gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_5G_HIGH] = map->rx_gain_b._5g_high;
554 gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_6G_L0] = map->rx_gain_6g_a._6g_l0;
555 gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_6G_L0] = map->rx_gain_6g_b._6g_l0;
556 gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_6G_L1] = map->rx_gain_6g_a._6g_l1;
557 gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_6G_L1] = map->rx_gain_6g_b._6g_l1;
558 gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_6G_M0] = map->rx_gain_6g_a._6g_m0;
559 gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_6G_M0] = map->rx_gain_6g_b._6g_m0;
560 gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_6G_M1] = map->rx_gain_6g_a._6g_m1;
561 gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_6G_M1] = map->rx_gain_6g_b._6g_m1;
562 gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_6G_H0] = map->rx_gain_6g_a._6g_h0;
563 gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_6G_H0] = map->rx_gain_6g_b._6g_h0;
564 gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_6G_H1] = map->rx_gain_6g_a._6g_h1;
565 gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_6G_H1] = map->rx_gain_6g_b._6g_h1;
566 gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_6G_UH0] = map->rx_gain_6g_a._6g_uh0;
567 gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_6G_UH0] = map->rx_gain_6g_b._6g_uh0;
568 gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_6G_UH1] = map->rx_gain_6g_a._6g_uh1;
569 gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_6G_UH1] = map->rx_gain_6g_b._6g_uh1;
570
571 for (i = RF_PATH_A; i <= RF_PATH_B; i++)
572 for (j = 0; j < RTW89_GAIN_OFFSET_NR; j++) {
573 t = gain->offset[i][j];
574 if (t != 0xff)
575 all_0xff = false;
576 if (t != 0x0)
577 all_0x00 = false;
578
579 /* transform: sign-bit + U(7,2) to S(8,2) */
580 if (t & 0x80)
581 gain->offset[i][j] = (t ^ 0x7f) + 1;
582 }
583
584 gain->offset_valid = !all_0xff && !all_0x00;
585 }
586
rtw8922a_read_efuse_mac_addr(struct rtw89_dev * rtwdev,u32 addr)587 static void rtw8922a_read_efuse_mac_addr(struct rtw89_dev *rtwdev, u32 addr)
588 {
589 struct rtw89_efuse *efuse = &rtwdev->efuse;
590 u16 val;
591 int i;
592
593 for (i = 0; i < ETH_ALEN; i += 2, addr += 2) {
594 val = rtw89_read16(rtwdev, addr);
595 efuse->addr[i] = val & 0xff;
596 efuse->addr[i + 1] = val >> 8;
597 }
598 }
599
rtw8922a_read_efuse_pci_sdio(struct rtw89_dev * rtwdev,u8 * log_map)600 static int rtw8922a_read_efuse_pci_sdio(struct rtw89_dev *rtwdev, u8 *log_map)
601 {
602 struct rtw89_efuse *efuse = &rtwdev->efuse;
603
604 if (rtwdev->hci.type == RTW89_HCI_TYPE_PCIE)
605 rtw8922a_read_efuse_mac_addr(rtwdev, 0x3104);
606 else
607 ether_addr_copy(efuse->addr, log_map + 0x001A);
608
609 return 0;
610 }
611
rtw8922a_read_efuse_usb(struct rtw89_dev * rtwdev,u8 * log_map)612 static int rtw8922a_read_efuse_usb(struct rtw89_dev *rtwdev, u8 *log_map)
613 {
614 rtw8922a_read_efuse_mac_addr(rtwdev, 0x4078);
615
616 return 0;
617 }
618
rtw8922a_read_efuse_rf(struct rtw89_dev * rtwdev,u8 * log_map)619 static int rtw8922a_read_efuse_rf(struct rtw89_dev *rtwdev, u8 *log_map)
620 {
621 struct rtw8922a_efuse *map = (struct rtw8922a_efuse *)log_map;
622 struct rtw89_efuse *efuse = &rtwdev->efuse;
623
624 efuse->rfe_type = map->rfe_type;
625 efuse->xtal_cap = map->xtal_k;
626 efuse->country_code[0] = map->country_code[0];
627 efuse->country_code[1] = map->country_code[1];
628 rtw8922a_efuse_parsing_tssi(rtwdev, map);
629 rtw8922a_efuse_parsing_gain_offset(rtwdev, map);
630
631 return 0;
632 }
633
rtw8922a_read_efuse(struct rtw89_dev * rtwdev,u8 * log_map,enum rtw89_efuse_block block)634 static int rtw8922a_read_efuse(struct rtw89_dev *rtwdev, u8 *log_map,
635 enum rtw89_efuse_block block)
636 {
637 struct rtw89_efuse *efuse = &rtwdev->efuse;
638 int ret;
639
640 switch (block) {
641 case RTW89_EFUSE_BLOCK_HCI_DIG_PCIE_SDIO:
642 ret = rtw8922a_read_efuse_pci_sdio(rtwdev, log_map);
643 break;
644 case RTW89_EFUSE_BLOCK_HCI_DIG_USB:
645 ret = rtw8922a_read_efuse_usb(rtwdev, log_map);
646 break;
647 case RTW89_EFUSE_BLOCK_RF:
648 ret = rtw8922a_read_efuse_rf(rtwdev, log_map);
649 break;
650 default:
651 ret = 0;
652 break;
653 }
654
655 if (!ret && is_zero_ether_addr(efuse->addr)) {
656 rtw89_info(rtwdev, "efuse mac address is zero, using random mac\n");
657 eth_random_addr(efuse->addr);
658 }
659
660 return ret;
661 }
662
663 #define THM_TRIM_POSITIVE_MASK BIT(6)
664 #define THM_TRIM_MAGNITUDE_MASK GENMASK(5, 0)
665
rtw8922a_phycap_parsing_thermal_trim(struct rtw89_dev * rtwdev,u8 * phycap_map)666 static void rtw8922a_phycap_parsing_thermal_trim(struct rtw89_dev *rtwdev,
667 u8 *phycap_map)
668 {
669 static const u32 thm_trim_addr[RF_PATH_NUM_8922A] = {0x1706, 0x1733};
670 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim;
671 u32 addr = rtwdev->chip->phycap_addr;
672 bool pg = true;
673 u8 pg_th;
674 s8 val;
675 u8 i;
676
677 for (i = 0; i < RF_PATH_NUM_8922A; i++) {
678 pg_th = phycap_map[thm_trim_addr[i] - addr];
679 if (pg_th == 0xff) {
680 info->thermal_trim[i] = 0;
681 pg = false;
682 break;
683 }
684
685 val = u8_get_bits(pg_th, THM_TRIM_MAGNITUDE_MASK);
686
687 if (!(pg_th & THM_TRIM_POSITIVE_MASK))
688 val *= -1;
689
690 info->thermal_trim[i] = val;
691
692 rtw89_debug(rtwdev, RTW89_DBG_RFK,
693 "[THERMAL][TRIM] path=%d thermal_trim=0x%x (%d)\n",
694 i, pg_th, val);
695 }
696
697 info->pg_thermal_trim = pg;
698 }
699
rtw8922a_phycap_parsing_pa_bias_trim(struct rtw89_dev * rtwdev,u8 * phycap_map)700 static void rtw8922a_phycap_parsing_pa_bias_trim(struct rtw89_dev *rtwdev,
701 u8 *phycap_map)
702 {
703 static const u32 pabias_trim_addr[RF_PATH_NUM_8922A] = {0x1707, 0x1734};
704 static const u32 check_pa_pad_trim_addr = 0x1700;
705 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim;
706 u32 addr = rtwdev->chip->phycap_addr;
707 u8 val;
708 u8 i;
709
710 val = phycap_map[check_pa_pad_trim_addr - addr];
711 if (val != 0xff)
712 info->pg_pa_bias_trim = true;
713
714 for (i = 0; i < RF_PATH_NUM_8922A; i++) {
715 info->pa_bias_trim[i] = phycap_map[pabias_trim_addr[i] - addr];
716
717 rtw89_debug(rtwdev, RTW89_DBG_RFK,
718 "[PA_BIAS][TRIM] path=%d pa_bias_trim=0x%x\n",
719 i, info->pa_bias_trim[i]);
720 }
721 }
722
rtw8922a_pa_bias_trim(struct rtw89_dev * rtwdev)723 static void rtw8922a_pa_bias_trim(struct rtw89_dev *rtwdev)
724 {
725 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim;
726 u8 pabias_2g, pabias_5g;
727 u8 i;
728
729 if (!info->pg_pa_bias_trim) {
730 rtw89_debug(rtwdev, RTW89_DBG_RFK,
731 "[PA_BIAS][TRIM] no PG, do nothing\n");
732
733 return;
734 }
735
736 for (i = 0; i < RF_PATH_NUM_8922A; i++) {
737 pabias_2g = FIELD_GET(GENMASK(3, 0), info->pa_bias_trim[i]);
738 pabias_5g = FIELD_GET(GENMASK(7, 4), info->pa_bias_trim[i]);
739
740 rtw89_debug(rtwdev, RTW89_DBG_RFK,
741 "[PA_BIAS][TRIM] path=%d 2G=0x%x 5G=0x%x\n",
742 i, pabias_2g, pabias_5g);
743
744 rtw89_write_rf(rtwdev, i, RR_BIASA, RR_BIASA_TXG_V1, pabias_2g);
745 rtw89_write_rf(rtwdev, i, RR_BIASA, RR_BIASA_TXA_V1, pabias_5g);
746 }
747 }
748
rtw8922a_phycap_parsing_pad_bias_trim(struct rtw89_dev * rtwdev,u8 * phycap_map)749 static void rtw8922a_phycap_parsing_pad_bias_trim(struct rtw89_dev *rtwdev,
750 u8 *phycap_map)
751 {
752 static const u32 pad_bias_trim_addr[RF_PATH_NUM_8922A] = {0x1708, 0x1735};
753 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim;
754 u32 addr = rtwdev->chip->phycap_addr;
755 u8 i;
756
757 for (i = 0; i < RF_PATH_NUM_8922A; i++) {
758 info->pad_bias_trim[i] = phycap_map[pad_bias_trim_addr[i] - addr];
759
760 rtw89_debug(rtwdev, RTW89_DBG_RFK,
761 "[PAD_BIAS][TRIM] path=%d pad_bias_trim=0x%x\n",
762 i, info->pad_bias_trim[i]);
763 }
764 }
765
rtw8922a_pad_bias_trim(struct rtw89_dev * rtwdev)766 static void rtw8922a_pad_bias_trim(struct rtw89_dev *rtwdev)
767 {
768 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim;
769 u8 pad_bias_2g, pad_bias_5g;
770 u8 i;
771
772 if (!info->pg_pa_bias_trim) {
773 rtw89_debug(rtwdev, RTW89_DBG_RFK,
774 "[PAD_BIAS][TRIM] no PG, do nothing\n");
775 return;
776 }
777
778 for (i = 0; i < RF_PATH_NUM_8922A; i++) {
779 pad_bias_2g = u8_get_bits(info->pad_bias_trim[i], GENMASK(3, 0));
780 pad_bias_5g = u8_get_bits(info->pad_bias_trim[i], GENMASK(7, 4));
781
782 rtw89_debug(rtwdev, RTW89_DBG_RFK,
783 "[PAD_BIAS][TRIM] path=%d 2G=0x%x 5G=0x%x\n",
784 i, pad_bias_2g, pad_bias_5g);
785
786 rtw89_write_rf(rtwdev, i, RR_BIASA, RR_BIASD_TXG_V1, pad_bias_2g);
787 rtw89_write_rf(rtwdev, i, RR_BIASA, RR_BIASD_TXA_V1, pad_bias_5g);
788 }
789 }
790
rtw8922a_read_phycap(struct rtw89_dev * rtwdev,u8 * phycap_map)791 static int rtw8922a_read_phycap(struct rtw89_dev *rtwdev, u8 *phycap_map)
792 {
793 rtw8922a_phycap_parsing_thermal_trim(rtwdev, phycap_map);
794 rtw8922a_phycap_parsing_pa_bias_trim(rtwdev, phycap_map);
795 rtw8922a_phycap_parsing_pad_bias_trim(rtwdev, phycap_map);
796
797 return 0;
798 }
799
rtw8922a_power_trim(struct rtw89_dev * rtwdev)800 static void rtw8922a_power_trim(struct rtw89_dev *rtwdev)
801 {
802 rtw8922a_pa_bias_trim(rtwdev);
803 rtw8922a_pad_bias_trim(rtwdev);
804 }
805
rtw8922a_set_channel_mac(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,u8 mac_idx)806 static void rtw8922a_set_channel_mac(struct rtw89_dev *rtwdev,
807 const struct rtw89_chan *chan,
808 u8 mac_idx)
809 {
810 u32 sub_carr = rtw89_mac_reg_by_idx(rtwdev, R_BE_TX_SUB_BAND_VALUE, mac_idx);
811 u32 chk_rate = rtw89_mac_reg_by_idx(rtwdev, R_BE_TXRATE_CHK, mac_idx);
812 u32 rf_mod = rtw89_mac_reg_by_idx(rtwdev, R_BE_WMAC_RFMOD, mac_idx);
813 u8 txsb20 = 0, txsb40 = 0, txsb80 = 0;
814 u8 rf_mod_val, chk_rate_mask;
815 u32 txsb;
816 u32 reg;
817
818 switch (chan->band_width) {
819 case RTW89_CHANNEL_WIDTH_160:
820 txsb80 = rtw89_phy_get_txsb(rtwdev, chan, RTW89_CHANNEL_WIDTH_80);
821 fallthrough;
822 case RTW89_CHANNEL_WIDTH_80:
823 txsb40 = rtw89_phy_get_txsb(rtwdev, chan, RTW89_CHANNEL_WIDTH_40);
824 fallthrough;
825 case RTW89_CHANNEL_WIDTH_40:
826 txsb20 = rtw89_phy_get_txsb(rtwdev, chan, RTW89_CHANNEL_WIDTH_20);
827 break;
828 default:
829 break;
830 }
831
832 switch (chan->band_width) {
833 case RTW89_CHANNEL_WIDTH_160:
834 rf_mod_val = BE_WMAC_RFMOD_160M;
835 txsb = u32_encode_bits(txsb20, B_BE_TXSB_20M_MASK) |
836 u32_encode_bits(txsb40, B_BE_TXSB_40M_MASK) |
837 u32_encode_bits(txsb80, B_BE_TXSB_80M_MASK);
838 break;
839 case RTW89_CHANNEL_WIDTH_80:
840 rf_mod_val = BE_WMAC_RFMOD_80M;
841 txsb = u32_encode_bits(txsb20, B_BE_TXSB_20M_MASK) |
842 u32_encode_bits(txsb40, B_BE_TXSB_40M_MASK);
843 break;
844 case RTW89_CHANNEL_WIDTH_40:
845 rf_mod_val = BE_WMAC_RFMOD_40M;
846 txsb = u32_encode_bits(txsb20, B_BE_TXSB_20M_MASK);
847 break;
848 case RTW89_CHANNEL_WIDTH_20:
849 default:
850 rf_mod_val = BE_WMAC_RFMOD_20M;
851 txsb = 0;
852 break;
853 }
854
855 if (txsb20 <= BE_PRI20_BITMAP_MAX)
856 txsb |= u32_encode_bits(BIT(txsb20), B_BE_PRI20_BITMAP_MASK);
857
858 rtw89_write8_mask(rtwdev, rf_mod, B_BE_WMAC_RFMOD_MASK, rf_mod_val);
859 rtw89_write32(rtwdev, sub_carr, txsb);
860
861 switch (chan->band_type) {
862 case RTW89_BAND_2G:
863 chk_rate_mask = B_BE_BAND_MODE;
864 break;
865 case RTW89_BAND_5G:
866 case RTW89_BAND_6G:
867 chk_rate_mask = B_BE_CHECK_CCK_EN | B_BE_RTS_LIMIT_IN_OFDM6;
868 break;
869 default:
870 rtw89_warn(rtwdev, "Invalid band_type:%d\n", chan->band_type);
871 return;
872 }
873
874 rtw89_write8_clr(rtwdev, chk_rate, B_BE_BAND_MODE | B_BE_CHECK_CCK_EN |
875 B_BE_RTS_LIMIT_IN_OFDM6);
876 rtw89_write8_set(rtwdev, chk_rate, chk_rate_mask);
877
878 switch (chan->band_width) {
879 case RTW89_CHANNEL_WIDTH_320:
880 case RTW89_CHANNEL_WIDTH_160:
881 case RTW89_CHANNEL_WIDTH_80:
882 case RTW89_CHANNEL_WIDTH_40:
883 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_PREBKF_CFG_1, mac_idx);
884 rtw89_write32_mask(rtwdev, reg, B_BE_SIFS_MACTXEN_T1_MASK, 0x41);
885 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_MUEDCA_EN, mac_idx);
886 rtw89_write32_mask(rtwdev, reg, B_BE_SIFS_MACTXEN_TB_T1_MASK, 0x41);
887 break;
888 default:
889 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_PREBKF_CFG_1, mac_idx);
890 rtw89_write32_mask(rtwdev, reg, B_BE_SIFS_MACTXEN_T1_MASK, 0x3f);
891 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_MUEDCA_EN, mac_idx);
892 rtw89_write32_mask(rtwdev, reg, B_BE_SIFS_MACTXEN_TB_T1_MASK, 0x3e);
893 break;
894 }
895 }
896
897 static const u32 rtw8922a_sco_barker_threshold[14] = {
898 0x1fe4f, 0x1ff5e, 0x2006c, 0x2017b, 0x2028a, 0x20399, 0x204a8, 0x205b6,
899 0x206c5, 0x207d4, 0x208e3, 0x209f2, 0x20b00, 0x20d8a
900 };
901
902 static const u32 rtw8922a_sco_cck_threshold[14] = {
903 0x2bdac, 0x2bf21, 0x2c095, 0x2c209, 0x2c37e, 0x2c4f2, 0x2c666, 0x2c7db,
904 0x2c94f, 0x2cac3, 0x2cc38, 0x2cdac, 0x2cf21, 0x2d29e
905 };
906
rtw8922a_ctrl_sco_cck(struct rtw89_dev * rtwdev,u8 primary_ch,enum rtw89_bandwidth bw,enum rtw89_phy_idx phy_idx)907 static int rtw8922a_ctrl_sco_cck(struct rtw89_dev *rtwdev,
908 u8 primary_ch, enum rtw89_bandwidth bw,
909 enum rtw89_phy_idx phy_idx)
910 {
911 u8 ch_element;
912
913 if (primary_ch >= 14)
914 return -EINVAL;
915
916 ch_element = primary_ch - 1;
917
918 rtw89_phy_write32_idx(rtwdev, R_BK_FC0INV, B_BK_FC0INV,
919 rtw8922a_sco_barker_threshold[ch_element],
920 phy_idx);
921 rtw89_phy_write32_idx(rtwdev, R_CCK_FC0INV, B_CCK_FC0INV,
922 rtw8922a_sco_cck_threshold[ch_element],
923 phy_idx);
924
925 return 0;
926 }
927
928 struct rtw8922a_bb_gain {
929 u32 gain_g[BB_PATH_NUM_8922A];
930 u32 gain_a[BB_PATH_NUM_8922A];
931 u32 gain_g_mask;
932 u32 gain_a_mask;
933 };
934
935 static const struct rtw89_reg_def rpl_comp_bw160[RTW89_BW20_SC_160M] = {
936 { .addr = 0x41E8, .mask = 0xFF00},
937 { .addr = 0x41E8, .mask = 0xFF0000},
938 { .addr = 0x41E8, .mask = 0xFF000000},
939 { .addr = 0x41EC, .mask = 0xFF},
940 { .addr = 0x41EC, .mask = 0xFF00},
941 { .addr = 0x41EC, .mask = 0xFF0000},
942 { .addr = 0x41EC, .mask = 0xFF000000},
943 { .addr = 0x41F0, .mask = 0xFF}
944 };
945
946 static const struct rtw89_reg_def rpl_comp_bw80[RTW89_BW20_SC_80M] = {
947 { .addr = 0x41F4, .mask = 0xFF},
948 { .addr = 0x41F4, .mask = 0xFF00},
949 { .addr = 0x41F4, .mask = 0xFF0000},
950 { .addr = 0x41F4, .mask = 0xFF000000}
951 };
952
953 static const struct rtw89_reg_def rpl_comp_bw40[RTW89_BW20_SC_40M] = {
954 { .addr = 0x41F0, .mask = 0xFF0000},
955 { .addr = 0x41F0, .mask = 0xFF000000}
956 };
957
958 static const struct rtw89_reg_def rpl_comp_bw20[RTW89_BW20_SC_20M] = {
959 { .addr = 0x41F0, .mask = 0xFF00}
960 };
961
962 static const struct rtw8922a_bb_gain bb_gain_lna[LNA_GAIN_NUM] = {
963 { .gain_g = {0x409c, 0x449c}, .gain_a = {0x406C, 0x446C},
964 .gain_g_mask = 0xFF00, .gain_a_mask = 0xFF},
965 { .gain_g = {0x409c, 0x449c}, .gain_a = {0x406C, 0x446C},
966 .gain_g_mask = 0xFF000000, .gain_a_mask = 0xFF0000},
967 { .gain_g = {0x40a0, 0x44a0}, .gain_a = {0x4070, 0x4470},
968 .gain_g_mask = 0xFF00, .gain_a_mask = 0xFF},
969 { .gain_g = {0x40a0, 0x44a0}, .gain_a = {0x4070, 0x4470},
970 .gain_g_mask = 0xFF000000, .gain_a_mask = 0xFF0000},
971 { .gain_g = {0x40a4, 0x44a4}, .gain_a = {0x4074, 0x4474},
972 .gain_g_mask = 0xFF00, .gain_a_mask = 0xFF},
973 { .gain_g = {0x40a4, 0x44a4}, .gain_a = {0x4074, 0x4474},
974 .gain_g_mask = 0xFF000000, .gain_a_mask = 0xFF0000},
975 { .gain_g = {0x40a8, 0x44a8}, .gain_a = {0x4078, 0x4478},
976 .gain_g_mask = 0xFF00, .gain_a_mask = 0xFF},
977 };
978
979 static const struct rtw8922a_bb_gain bb_gain_tia[TIA_GAIN_NUM] = {
980 { .gain_g = {0x4054, 0x4454}, .gain_a = {0x4054, 0x4454},
981 .gain_g_mask = 0x7FC0000, .gain_a_mask = 0x1FF},
982 { .gain_g = {0x4058, 0x4458}, .gain_a = {0x4054, 0x4454},
983 .gain_g_mask = 0x1FF, .gain_a_mask = 0x3FE00 },
984 };
985
986 static const struct rtw8922a_bb_gain bb_op1db_lna[LNA_GAIN_NUM] = {
987 { .gain_g = {0x40ac, 0x44ac}, .gain_a = {0x4078, 0x4478},
988 .gain_g_mask = 0xFF00, .gain_a_mask = 0xFF000000},
989 { .gain_g = {0x40ac, 0x44ac}, .gain_a = {0x407c, 0x447c},
990 .gain_g_mask = 0xFF0000, .gain_a_mask = 0xFF},
991 { .gain_g = {0x40ac, 0x44ac}, .gain_a = {0x407c, 0x447c},
992 .gain_g_mask = 0xFF000000, .gain_a_mask = 0xFF00},
993 { .gain_g = {0x40b0, 0x44b0}, .gain_a = {0x407c, 0x447c},
994 .gain_g_mask = 0xFF, .gain_a_mask = 0xFF0000},
995 { .gain_g = {0x40b0, 0x44b0}, .gain_a = {0x407c, 0x447c},
996 .gain_g_mask = 0xFF00, .gain_a_mask = 0xFF000000},
997 { .gain_g = {0x40b0, 0x44b0}, .gain_a = {0x4080, 0x4480},
998 .gain_g_mask = 0xFF0000, .gain_a_mask = 0xFF},
999 { .gain_g = {0x40b0, 0x44b0}, .gain_a = {0x4080, 0x4480},
1000 .gain_g_mask = 0xFF000000, .gain_a_mask = 0xFF00},
1001 };
1002
1003 static const struct rtw8922a_bb_gain bb_op1db_tia_lna[TIA_LNA_OP1DB_NUM] = {
1004 { .gain_g = {0x40b4, 0x44b4}, .gain_a = {0x4080, 0x4480},
1005 .gain_g_mask = 0xFF0000, .gain_a_mask = 0xFF000000},
1006 { .gain_g = {0x40b4, 0x44b4}, .gain_a = {0x4084, 0x4484},
1007 .gain_g_mask = 0xFF000000, .gain_a_mask = 0xFF},
1008 { .gain_g = {0x40b8, 0x44b8}, .gain_a = {0x4084, 0x4484},
1009 .gain_g_mask = 0xFF, .gain_a_mask = 0xFF00},
1010 { .gain_g = {0x40b8, 0x44b8}, .gain_a = {0x4084, 0x4484},
1011 .gain_g_mask = 0xFF00, .gain_a_mask = 0xFF0000},
1012 { .gain_g = {0x40b8, 0x44b8}, .gain_a = {0x4084, 0x4484},
1013 .gain_g_mask = 0xFF0000, .gain_a_mask = 0xFF000000},
1014 { .gain_g = {0x40b8, 0x44b8}, .gain_a = {0x4088, 0x4488},
1015 .gain_g_mask = 0xFF000000, .gain_a_mask = 0xFF},
1016 { .gain_g = {0x40bc, 0x44bc}, .gain_a = {0x4088, 0x4488},
1017 .gain_g_mask = 0xFF, .gain_a_mask = 0xFF00},
1018 { .gain_g = {0x40bc, 0x44bc}, .gain_a = {0x4088, 0x4488},
1019 .gain_g_mask = 0xFF00, .gain_a_mask = 0xFF0000},
1020 };
1021
1022 struct rtw8922a_bb_gain_bypass {
1023 u32 gain_g[BB_PATH_NUM_8922A];
1024 u32 gain_a[BB_PATH_NUM_8922A];
1025 u32 gain_mask_g;
1026 u32 gain_mask_a;
1027 };
1028
rtw8922a_set_rpl_gain(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_rf_path path,enum rtw89_phy_idx phy_idx)1029 static void rtw8922a_set_rpl_gain(struct rtw89_dev *rtwdev,
1030 const struct rtw89_chan *chan,
1031 enum rtw89_rf_path path,
1032 enum rtw89_phy_idx phy_idx)
1033 {
1034 const struct rtw89_phy_bb_gain_info_be *gain = &rtwdev->bb_gain.be;
1035 u8 gain_band = rtw89_subband_to_gain_band_be(chan->subband_type);
1036 u32 reg_path_ofst = 0;
1037 u32 mask;
1038 s32 val;
1039 u32 reg;
1040 int i;
1041
1042 if (path == RF_PATH_B)
1043 reg_path_ofst = 0x400;
1044
1045 for (i = 0; i < RTW89_BW20_SC_160M; i++) {
1046 reg = rpl_comp_bw160[i].addr | reg_path_ofst;
1047 mask = rpl_comp_bw160[i].mask;
1048 val = gain->rpl_ofst_160[gain_band][path][i];
1049 rtw89_phy_write32_idx(rtwdev, reg, mask, val, phy_idx);
1050 }
1051
1052 for (i = 0; i < RTW89_BW20_SC_80M; i++) {
1053 reg = rpl_comp_bw80[i].addr | reg_path_ofst;
1054 mask = rpl_comp_bw80[i].mask;
1055 val = gain->rpl_ofst_80[gain_band][path][i];
1056 rtw89_phy_write32_idx(rtwdev, reg, mask, val, phy_idx);
1057 }
1058
1059 for (i = 0; i < RTW89_BW20_SC_40M; i++) {
1060 reg = rpl_comp_bw40[i].addr | reg_path_ofst;
1061 mask = rpl_comp_bw40[i].mask;
1062 val = gain->rpl_ofst_40[gain_band][path][i];
1063 rtw89_phy_write32_idx(rtwdev, reg, mask, val, phy_idx);
1064 }
1065
1066 for (i = 0; i < RTW89_BW20_SC_20M; i++) {
1067 reg = rpl_comp_bw20[i].addr | reg_path_ofst;
1068 mask = rpl_comp_bw20[i].mask;
1069 val = gain->rpl_ofst_20[gain_band][path][i];
1070 rtw89_phy_write32_idx(rtwdev, reg, mask, val, phy_idx);
1071 }
1072 }
1073
rtw8922a_set_lna_tia_gain(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_rf_path path,enum rtw89_phy_idx phy_idx)1074 static void rtw8922a_set_lna_tia_gain(struct rtw89_dev *rtwdev,
1075 const struct rtw89_chan *chan,
1076 enum rtw89_rf_path path,
1077 enum rtw89_phy_idx phy_idx)
1078 {
1079 const struct rtw89_phy_bb_gain_info_be *gain = &rtwdev->bb_gain.be;
1080 u8 gain_band = rtw89_subband_to_gain_band_be(chan->subband_type);
1081 enum rtw89_phy_bb_bw_be bw_type;
1082 s32 val;
1083 u32 reg;
1084 u32 mask;
1085 int i;
1086
1087 bw_type = chan->band_width <= RTW89_CHANNEL_WIDTH_40 ?
1088 RTW89_BB_BW_20_40 : RTW89_BB_BW_80_160_320;
1089
1090 for (i = 0; i < LNA_GAIN_NUM; i++) {
1091 if (chan->band_type == RTW89_BAND_2G) {
1092 reg = bb_gain_lna[i].gain_g[path];
1093 mask = bb_gain_lna[i].gain_g_mask;
1094 } else {
1095 reg = bb_gain_lna[i].gain_a[path];
1096 mask = bb_gain_lna[i].gain_a_mask;
1097 }
1098 val = gain->lna_gain[gain_band][bw_type][path][i];
1099 rtw89_phy_write32_idx(rtwdev, reg, mask, val, phy_idx);
1100 }
1101
1102 for (i = 0; i < TIA_GAIN_NUM; i++) {
1103 if (chan->band_type == RTW89_BAND_2G) {
1104 reg = bb_gain_tia[i].gain_g[path];
1105 mask = bb_gain_tia[i].gain_g_mask;
1106 } else {
1107 reg = bb_gain_tia[i].gain_a[path];
1108 mask = bb_gain_tia[i].gain_a_mask;
1109 }
1110 val = gain->tia_gain[gain_band][bw_type][path][i];
1111 rtw89_phy_write32_idx(rtwdev, reg, mask, val, phy_idx);
1112 }
1113
1114 for (i = 0; i < LNA_GAIN_NUM; i++) {
1115 if (chan->band_type == RTW89_BAND_2G) {
1116 reg = bb_op1db_lna[i].gain_g[path];
1117 mask = bb_op1db_lna[i].gain_g_mask;
1118 } else {
1119 reg = bb_op1db_lna[i].gain_a[path];
1120 mask = bb_op1db_lna[i].gain_a_mask;
1121 }
1122 val = gain->lna_op1db[gain_band][bw_type][path][i];
1123 rtw89_phy_write32_idx(rtwdev, reg, mask, val, phy_idx);
1124 }
1125
1126 for (i = 0; i < TIA_LNA_OP1DB_NUM; i++) {
1127 if (chan->band_type == RTW89_BAND_2G) {
1128 reg = bb_op1db_tia_lna[i].gain_g[path];
1129 mask = bb_op1db_tia_lna[i].gain_g_mask;
1130 } else {
1131 reg = bb_op1db_tia_lna[i].gain_a[path];
1132 mask = bb_op1db_tia_lna[i].gain_a_mask;
1133 }
1134 val = gain->tia_lna_op1db[gain_band][bw_type][path][i];
1135 rtw89_phy_write32_idx(rtwdev, reg, mask, val, phy_idx);
1136 }
1137 }
1138
rtw8922a_set_gain(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_rf_path path,enum rtw89_phy_idx phy_idx)1139 static void rtw8922a_set_gain(struct rtw89_dev *rtwdev,
1140 const struct rtw89_chan *chan,
1141 enum rtw89_rf_path path,
1142 enum rtw89_phy_idx phy_idx)
1143 {
1144 rtw8922a_set_lna_tia_gain(rtwdev, chan, path, phy_idx);
1145 rtw8922a_set_rpl_gain(rtwdev, chan, path, phy_idx);
1146 }
1147
rtw8922a_set_rx_gain_normal_cck(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_rf_path path)1148 static void rtw8922a_set_rx_gain_normal_cck(struct rtw89_dev *rtwdev,
1149 const struct rtw89_chan *chan,
1150 enum rtw89_rf_path path)
1151 {
1152 struct rtw89_phy_efuse_gain *gain = &rtwdev->efuse_gain;
1153 s8 value = -gain->offset[path][RTW89_GAIN_OFFSET_2G_CCK]; /* S(8,2) */
1154 u8 fraction = value & 0x3;
1155
1156 if (fraction) {
1157 rtw89_phy_write32_mask(rtwdev, R_MGAIN_BIAS, B_MGAIN_BIAS_BW20,
1158 (0x4 - fraction) << 1);
1159 rtw89_phy_write32_mask(rtwdev, R_MGAIN_BIAS, B_MGAIN_BIAS_BW40,
1160 (0x4 - fraction) << 1);
1161
1162 value >>= 2;
1163 rtw89_phy_write32_mask(rtwdev, R_CCK_RPL_OFST, B_CCK_RPL_OFST,
1164 value + 1 + 0xdc);
1165 } else {
1166 rtw89_phy_write32_mask(rtwdev, R_MGAIN_BIAS, B_MGAIN_BIAS_BW20, 0);
1167 rtw89_phy_write32_mask(rtwdev, R_MGAIN_BIAS, B_MGAIN_BIAS_BW40, 0);
1168
1169 value >>= 2;
1170 rtw89_phy_write32_mask(rtwdev, R_CCK_RPL_OFST, B_CCK_RPL_OFST,
1171 value + 0xdc);
1172 }
1173 }
1174
rtw8922a_set_rx_gain_normal_ofdm(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_rf_path path)1175 static void rtw8922a_set_rx_gain_normal_ofdm(struct rtw89_dev *rtwdev,
1176 const struct rtw89_chan *chan,
1177 enum rtw89_rf_path path)
1178 {
1179 static const u32 rssi_tb_bias_comp[2] = {0x41f8, 0x45f8};
1180 static const u32 rssi_tb_ext_comp[2] = {0x4208, 0x4608};
1181 static const u32 rssi_ofst_addr[2] = {0x40c8, 0x44c8};
1182 static const u32 rpl_bias_comp[2] = {0x41e8, 0x45e8};
1183 static const u32 rpl_ext_comp[2] = {0x41f8, 0x45f8};
1184 struct rtw89_phy_efuse_gain *gain = &rtwdev->efuse_gain;
1185 enum rtw89_gain_offset gain_band;
1186 s8 v1, v2, v3;
1187 s32 value;
1188
1189 gain_band = rtw89_subband_to_gain_offset_band_of_ofdm(chan->subband_type);
1190 value = gain->offset[path][gain_band];
1191 rtw89_phy_write32_mask(rtwdev, rssi_ofst_addr[path], 0xff000000, value + 0xF8);
1192
1193 value *= -4;
1194 v1 = clamp_t(s32, value, S8_MIN, S8_MAX);
1195 value -= v1;
1196 v2 = clamp_t(s32, value, S8_MIN, S8_MAX);
1197 value -= v2;
1198 v3 = clamp_t(s32, value, S8_MIN, S8_MAX);
1199
1200 rtw89_phy_write32_mask(rtwdev, rpl_bias_comp[path], 0xff, v1);
1201 rtw89_phy_write32_mask(rtwdev, rpl_ext_comp[path], 0xff, v2);
1202 rtw89_phy_write32_mask(rtwdev, rpl_ext_comp[path], 0xff00, v3);
1203
1204 rtw89_phy_write32_mask(rtwdev, rssi_tb_bias_comp[path], 0xff0000, v1);
1205 rtw89_phy_write32_mask(rtwdev, rssi_tb_ext_comp[path], 0xff0000, v2);
1206 rtw89_phy_write32_mask(rtwdev, rssi_tb_ext_comp[path], 0xff000000, v3);
1207 }
1208
rtw8922a_set_rx_gain_normal(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_rf_path path)1209 static void rtw8922a_set_rx_gain_normal(struct rtw89_dev *rtwdev,
1210 const struct rtw89_chan *chan,
1211 enum rtw89_rf_path path)
1212 {
1213 struct rtw89_phy_efuse_gain *gain = &rtwdev->efuse_gain;
1214
1215 if (!gain->offset_valid)
1216 return;
1217
1218 if (chan->band_type == RTW89_BAND_2G)
1219 rtw8922a_set_rx_gain_normal_cck(rtwdev, chan, path);
1220
1221 rtw8922a_set_rx_gain_normal_ofdm(rtwdev, chan, path);
1222 }
1223
rtw8922a_set_cck_parameters(struct rtw89_dev * rtwdev,u8 central_ch,enum rtw89_phy_idx phy_idx)1224 static void rtw8922a_set_cck_parameters(struct rtw89_dev *rtwdev, u8 central_ch,
1225 enum rtw89_phy_idx phy_idx)
1226 {
1227 if (central_ch == 14) {
1228 rtw89_phy_write32_idx(rtwdev, R_PCOEFF01, B_PCOEFF01, 0x3b13ff, phy_idx);
1229 rtw89_phy_write32_idx(rtwdev, R_PCOEFF23, B_PCOEFF23, 0x1c42de, phy_idx);
1230 rtw89_phy_write32_idx(rtwdev, R_PCOEFF45, B_PCOEFF45, 0xfdb0ad, phy_idx);
1231 rtw89_phy_write32_idx(rtwdev, R_PCOEFF67, B_PCOEFF67, 0xf60f6e, phy_idx);
1232 rtw89_phy_write32_idx(rtwdev, R_PCOEFF89, B_PCOEFF89, 0xfd8f92, phy_idx);
1233 rtw89_phy_write32_idx(rtwdev, R_PCOEFFAB, B_PCOEFFAB, 0x02d011, phy_idx);
1234 rtw89_phy_write32_idx(rtwdev, R_PCOEFFCD, B_PCOEFFCD, 0x01c02c, phy_idx);
1235 rtw89_phy_write32_idx(rtwdev, R_PCOEFFEF, B_PCOEFFEF, 0xfff00a, phy_idx);
1236 } else {
1237 rtw89_phy_write32_idx(rtwdev, R_PCOEFF01, B_PCOEFF01, 0x3a63ca, phy_idx);
1238 rtw89_phy_write32_idx(rtwdev, R_PCOEFF23, B_PCOEFF23, 0x2a833f, phy_idx);
1239 rtw89_phy_write32_idx(rtwdev, R_PCOEFF45, B_PCOEFF45, 0x1491f8, phy_idx);
1240 rtw89_phy_write32_idx(rtwdev, R_PCOEFF67, B_PCOEFF67, 0x03c0b0, phy_idx);
1241 rtw89_phy_write32_idx(rtwdev, R_PCOEFF89, B_PCOEFF89, 0xfccff1, phy_idx);
1242 rtw89_phy_write32_idx(rtwdev, R_PCOEFFAB, B_PCOEFFAB, 0xfccfc3, phy_idx);
1243 rtw89_phy_write32_idx(rtwdev, R_PCOEFFCD, B_PCOEFFCD, 0xfebfdc, phy_idx);
1244 rtw89_phy_write32_idx(rtwdev, R_PCOEFFEF, B_PCOEFFEF, 0xffdff7, phy_idx);
1245 }
1246 }
1247
rtw8922a_ctrl_ch(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_phy_idx phy_idx)1248 static void rtw8922a_ctrl_ch(struct rtw89_dev *rtwdev,
1249 const struct rtw89_chan *chan,
1250 enum rtw89_phy_idx phy_idx)
1251 {
1252 static const u32 band_sel[2] = {0x4160, 0x4560};
1253 u16 central_freq = chan->freq;
1254 u8 central_ch = chan->channel;
1255 u8 band = chan->band_type;
1256 bool is_2g = band == RTW89_BAND_2G;
1257 u8 chan_idx;
1258 u8 path;
1259 u8 sco;
1260
1261 if (!central_freq) {
1262 rtw89_warn(rtwdev, "Invalid central_freq\n");
1263 return;
1264 }
1265
1266 rtw8922a_set_gain(rtwdev, chan, RF_PATH_A, phy_idx);
1267 rtw8922a_set_gain(rtwdev, chan, RF_PATH_B, phy_idx);
1268
1269 for (path = RF_PATH_A; path < BB_PATH_NUM_8922A; path++)
1270 rtw89_phy_write32_idx(rtwdev, band_sel[path], BIT((26)), is_2g, phy_idx);
1271
1272 rtw8922a_set_rx_gain_normal(rtwdev, chan, RF_PATH_A);
1273 rtw8922a_set_rx_gain_normal(rtwdev, chan, RF_PATH_B);
1274
1275 rtw89_phy_write32_idx(rtwdev, R_FC0, B_FC0, central_freq, phy_idx);
1276 sco = DIV_ROUND_CLOSEST(1 << 18, central_freq);
1277 rtw89_phy_write32_idx(rtwdev, R_FC0INV_SBW, B_FC0_INV, sco, phy_idx);
1278
1279 if (band == RTW89_BAND_2G)
1280 rtw8922a_set_cck_parameters(rtwdev, central_ch, phy_idx);
1281
1282 chan_idx = rtw89_encode_chan_idx(rtwdev, chan->primary_channel, band);
1283 rtw89_phy_write32_idx(rtwdev, R_MAC_PIN_SEL, B_CH_IDX_SEG0, chan_idx, phy_idx);
1284 }
1285
1286 static void
rtw8922a_ctrl_bw(struct rtw89_dev * rtwdev,u8 pri_sb,u8 bw,enum rtw89_phy_idx phy_idx)1287 rtw8922a_ctrl_bw(struct rtw89_dev *rtwdev, u8 pri_sb, u8 bw,
1288 enum rtw89_phy_idx phy_idx)
1289 {
1290 switch (bw) {
1291 case RTW89_CHANNEL_WIDTH_5:
1292 rtw89_phy_write32_idx(rtwdev, R_ANT_CHBW, B_CHBW_BW, 0x0, phy_idx);
1293 rtw89_phy_write32_idx(rtwdev, R_FC0INV_SBW, B_SMALLBW, 0x1, phy_idx);
1294 rtw89_phy_write32_idx(rtwdev, R_ANT_CHBW, B_CHBW_PRICH, 0x0, phy_idx);
1295 rtw89_phy_write32_idx(rtwdev, R_DAC_CLK, B_DAC_CLK, 0x1, phy_idx);
1296 rtw89_phy_write32_idx(rtwdev, R_GAIN_MAP0, B_GAIN_MAP0_EN, 0x0, phy_idx);
1297 rtw89_phy_write32_idx(rtwdev, R_GAIN_MAP1, B_GAIN_MAP1_EN, 0x0, phy_idx);
1298 break;
1299 case RTW89_CHANNEL_WIDTH_10:
1300 rtw89_phy_write32_idx(rtwdev, R_ANT_CHBW, B_CHBW_BW, 0x0, phy_idx);
1301 rtw89_phy_write32_idx(rtwdev, R_FC0INV_SBW, B_SMALLBW, 0x2, phy_idx);
1302 rtw89_phy_write32_idx(rtwdev, R_ANT_CHBW, B_CHBW_PRICH, 0x0, phy_idx);
1303 rtw89_phy_write32_idx(rtwdev, R_DAC_CLK, B_DAC_CLK, 0x1, phy_idx);
1304 rtw89_phy_write32_idx(rtwdev, R_GAIN_MAP0, B_GAIN_MAP0_EN, 0x0, phy_idx);
1305 rtw89_phy_write32_idx(rtwdev, R_GAIN_MAP1, B_GAIN_MAP1_EN, 0x0, phy_idx);
1306 break;
1307 case RTW89_CHANNEL_WIDTH_20:
1308 rtw89_phy_write32_idx(rtwdev, R_ANT_CHBW, B_CHBW_BW, 0x0, phy_idx);
1309 rtw89_phy_write32_idx(rtwdev, R_FC0INV_SBW, B_SMALLBW, 0x0, phy_idx);
1310 rtw89_phy_write32_idx(rtwdev, R_ANT_CHBW, B_CHBW_PRICH, 0x0, phy_idx);
1311 rtw89_phy_write32_idx(rtwdev, R_DAC_CLK, B_DAC_CLK, 0x1, phy_idx);
1312 rtw89_phy_write32_idx(rtwdev, R_GAIN_MAP0, B_GAIN_MAP0_EN, 0x0, phy_idx);
1313 rtw89_phy_write32_idx(rtwdev, R_GAIN_MAP1, B_GAIN_MAP1_EN, 0x0, phy_idx);
1314 break;
1315 case RTW89_CHANNEL_WIDTH_40:
1316 rtw89_phy_write32_idx(rtwdev, R_ANT_CHBW, B_CHBW_BW, 0x1, phy_idx);
1317 rtw89_phy_write32_idx(rtwdev, R_FC0INV_SBW, B_SMALLBW, 0x0, phy_idx);
1318 rtw89_phy_write32_idx(rtwdev, R_ANT_CHBW, B_CHBW_PRICH, pri_sb, phy_idx);
1319 rtw89_phy_write32_idx(rtwdev, R_DAC_CLK, B_DAC_CLK, 0x1, phy_idx);
1320 rtw89_phy_write32_idx(rtwdev, R_GAIN_MAP0, B_GAIN_MAP0_EN, 0x0, phy_idx);
1321 rtw89_phy_write32_idx(rtwdev, R_GAIN_MAP1, B_GAIN_MAP1_EN, 0x0, phy_idx);
1322 break;
1323 case RTW89_CHANNEL_WIDTH_80:
1324 rtw89_phy_write32_idx(rtwdev, R_ANT_CHBW, B_CHBW_BW, 0x2, phy_idx);
1325 rtw89_phy_write32_idx(rtwdev, R_FC0INV_SBW, B_SMALLBW, 0x0, phy_idx);
1326 rtw89_phy_write32_idx(rtwdev, R_ANT_CHBW, B_CHBW_PRICH, pri_sb, phy_idx);
1327 rtw89_phy_write32_idx(rtwdev, R_DAC_CLK, B_DAC_CLK, 0x1, phy_idx);
1328 rtw89_phy_write32_idx(rtwdev, R_GAIN_MAP0, B_GAIN_MAP0_EN, 0x1, phy_idx);
1329 rtw89_phy_write32_idx(rtwdev, R_GAIN_MAP1, B_GAIN_MAP1_EN, 0x1, phy_idx);
1330 break;
1331 case RTW89_CHANNEL_WIDTH_160:
1332 rtw89_phy_write32_idx(rtwdev, R_ANT_CHBW, B_CHBW_BW, 0x3, phy_idx);
1333 rtw89_phy_write32_idx(rtwdev, R_FC0INV_SBW, B_SMALLBW, 0x0, phy_idx);
1334 rtw89_phy_write32_idx(rtwdev, R_ANT_CHBW, B_CHBW_PRICH, pri_sb, phy_idx);
1335 rtw89_phy_write32_idx(rtwdev, R_DAC_CLK, B_DAC_CLK, 0x1, phy_idx);
1336 rtw89_phy_write32_idx(rtwdev, R_GAIN_MAP0, B_GAIN_MAP0_EN, 0x1, phy_idx);
1337 rtw89_phy_write32_idx(rtwdev, R_GAIN_MAP1, B_GAIN_MAP1_EN, 0x1, phy_idx);
1338 break;
1339 default:
1340 rtw89_warn(rtwdev, "Fail to switch bw (bw:%d, pri_sb:%d)\n", bw,
1341 pri_sb);
1342 break;
1343 }
1344
1345 if (bw == RTW89_CHANNEL_WIDTH_40)
1346 rtw89_phy_write32_idx(rtwdev, R_FC0, B_BW40_2XFFT, 1, phy_idx);
1347 else
1348 rtw89_phy_write32_idx(rtwdev, R_FC0, B_BW40_2XFFT, 0, phy_idx);
1349 }
1350
rtw8922a_spur_freq(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan)1351 static u32 rtw8922a_spur_freq(struct rtw89_dev *rtwdev,
1352 const struct rtw89_chan *chan)
1353 {
1354 return 0;
1355 }
1356
1357 #define CARRIER_SPACING_312_5 312500 /* 312.5 kHz */
1358 #define CARRIER_SPACING_78_125 78125 /* 78.125 kHz */
1359 #define MAX_TONE_NUM 2048
1360
rtw8922a_set_csi_tone_idx(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_phy_idx phy_idx)1361 static void rtw8922a_set_csi_tone_idx(struct rtw89_dev *rtwdev,
1362 const struct rtw89_chan *chan,
1363 enum rtw89_phy_idx phy_idx)
1364 {
1365 s32 freq_diff, csi_idx, csi_tone_idx;
1366 u32 spur_freq;
1367
1368 spur_freq = rtw8922a_spur_freq(rtwdev, chan);
1369 if (spur_freq == 0) {
1370 rtw89_phy_write32_idx(rtwdev, R_S0S1_CSI_WGT, B_S0S1_CSI_WGT_EN,
1371 0, phy_idx);
1372 return;
1373 }
1374
1375 freq_diff = (spur_freq - chan->freq) * 1000000;
1376 csi_idx = s32_div_u32_round_closest(freq_diff, CARRIER_SPACING_78_125);
1377 s32_div_u32_round_down(csi_idx, MAX_TONE_NUM, &csi_tone_idx);
1378
1379 rtw89_phy_write32_idx(rtwdev, R_S0S1_CSI_WGT, B_S0S1_CSI_WGT_TONE_IDX,
1380 csi_tone_idx, phy_idx);
1381 rtw89_phy_write32_idx(rtwdev, R_S0S1_CSI_WGT, B_S0S1_CSI_WGT_EN, 1, phy_idx);
1382 }
1383
1384 static const struct rtw89_nbi_reg_def rtw8922a_nbi_reg_def[] = {
1385 [RF_PATH_A] = {
1386 .notch1_idx = {0x41a0, 0xFF},
1387 .notch1_frac_idx = {0x41a0, 0xC00},
1388 .notch1_en = {0x41a0, 0x1000},
1389 .notch2_idx = {0x41ac, 0xFF},
1390 .notch2_frac_idx = {0x41ac, 0xC00},
1391 .notch2_en = {0x41ac, 0x1000},
1392 },
1393 [RF_PATH_B] = {
1394 .notch1_idx = {0x45a0, 0xFF},
1395 .notch1_frac_idx = {0x45a0, 0xC00},
1396 .notch1_en = {0x45a0, 0x1000},
1397 .notch2_idx = {0x45ac, 0xFF},
1398 .notch2_frac_idx = {0x45ac, 0xC00},
1399 .notch2_en = {0x45ac, 0x1000},
1400 },
1401 };
1402
rtw8922a_set_nbi_tone_idx(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_rf_path path,enum rtw89_phy_idx phy_idx)1403 static void rtw8922a_set_nbi_tone_idx(struct rtw89_dev *rtwdev,
1404 const struct rtw89_chan *chan,
1405 enum rtw89_rf_path path,
1406 enum rtw89_phy_idx phy_idx)
1407 {
1408 const struct rtw89_nbi_reg_def *nbi = &rtw8922a_nbi_reg_def[path];
1409 s32 nbi_frac_idx, nbi_frac_tone_idx;
1410 s32 nbi_idx, nbi_tone_idx;
1411 bool notch2_chk = false;
1412 u32 spur_freq, fc;
1413 s32 freq_diff;
1414
1415 spur_freq = rtw8922a_spur_freq(rtwdev, chan);
1416 if (spur_freq == 0) {
1417 rtw89_phy_write32_idx(rtwdev, nbi->notch1_en.addr,
1418 nbi->notch1_en.mask, 0, phy_idx);
1419 rtw89_phy_write32_idx(rtwdev, nbi->notch2_en.addr,
1420 nbi->notch2_en.mask, 0, phy_idx);
1421 return;
1422 }
1423
1424 fc = chan->freq;
1425 if (chan->band_width == RTW89_CHANNEL_WIDTH_160) {
1426 fc = (spur_freq > fc) ? fc + 40 : fc - 40;
1427 if ((fc > spur_freq &&
1428 chan->channel < chan->primary_channel) ||
1429 (fc < spur_freq &&
1430 chan->channel > chan->primary_channel))
1431 notch2_chk = true;
1432 }
1433
1434 freq_diff = (spur_freq - fc) * 1000000;
1435 nbi_idx = s32_div_u32_round_down(freq_diff, CARRIER_SPACING_312_5,
1436 &nbi_frac_idx);
1437
1438 if (chan->band_width == RTW89_CHANNEL_WIDTH_20) {
1439 s32_div_u32_round_down(nbi_idx + 32, 64, &nbi_tone_idx);
1440 } else {
1441 u16 tone_para = (chan->band_width == RTW89_CHANNEL_WIDTH_40) ?
1442 128 : 256;
1443
1444 s32_div_u32_round_down(nbi_idx, tone_para, &nbi_tone_idx);
1445 }
1446 nbi_frac_tone_idx =
1447 s32_div_u32_round_closest(nbi_frac_idx, CARRIER_SPACING_78_125);
1448
1449 if (chan->band_width == RTW89_CHANNEL_WIDTH_160 && notch2_chk) {
1450 rtw89_phy_write32_idx(rtwdev, nbi->notch2_idx.addr,
1451 nbi->notch2_idx.mask, nbi_tone_idx, phy_idx);
1452 rtw89_phy_write32_idx(rtwdev, nbi->notch2_frac_idx.addr,
1453 nbi->notch2_frac_idx.mask, nbi_frac_tone_idx,
1454 phy_idx);
1455 rtw89_phy_write32_idx(rtwdev, nbi->notch2_en.addr,
1456 nbi->notch2_en.mask, 0, phy_idx);
1457 rtw89_phy_write32_idx(rtwdev, nbi->notch2_en.addr,
1458 nbi->notch2_en.mask, 1, phy_idx);
1459 rtw89_phy_write32_idx(rtwdev, nbi->notch1_en.addr,
1460 nbi->notch1_en.mask, 0, phy_idx);
1461 } else {
1462 rtw89_phy_write32_idx(rtwdev, nbi->notch1_idx.addr,
1463 nbi->notch1_idx.mask, nbi_tone_idx, phy_idx);
1464 rtw89_phy_write32_idx(rtwdev, nbi->notch1_frac_idx.addr,
1465 nbi->notch1_frac_idx.mask, nbi_frac_tone_idx,
1466 phy_idx);
1467 rtw89_phy_write32_idx(rtwdev, nbi->notch1_en.addr,
1468 nbi->notch1_en.mask, 0, phy_idx);
1469 rtw89_phy_write32_idx(rtwdev, nbi->notch1_en.addr,
1470 nbi->notch1_en.mask, 1, phy_idx);
1471 rtw89_phy_write32_idx(rtwdev, nbi->notch2_en.addr,
1472 nbi->notch2_en.mask, 0, phy_idx);
1473 }
1474 }
1475
rtw8922a_spur_elimination(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_phy_idx phy_idx)1476 static void rtw8922a_spur_elimination(struct rtw89_dev *rtwdev,
1477 const struct rtw89_chan *chan,
1478 enum rtw89_phy_idx phy_idx)
1479 {
1480 rtw8922a_set_csi_tone_idx(rtwdev, chan, phy_idx);
1481 rtw8922a_set_nbi_tone_idx(rtwdev, chan, RF_PATH_A, phy_idx);
1482 rtw8922a_set_nbi_tone_idx(rtwdev, chan, RF_PATH_B, phy_idx);
1483 }
1484
rtw8922a_ctrl_afe_dac(struct rtw89_dev * rtwdev,enum rtw89_bandwidth bw,enum rtw89_rf_path path)1485 static void rtw8922a_ctrl_afe_dac(struct rtw89_dev *rtwdev, enum rtw89_bandwidth bw,
1486 enum rtw89_rf_path path)
1487 {
1488 u32 cr_ofst = 0x0;
1489
1490 if (path == RF_PATH_B)
1491 cr_ofst = 0x100;
1492
1493 switch (bw) {
1494 case RTW89_CHANNEL_WIDTH_5:
1495 case RTW89_CHANNEL_WIDTH_10:
1496 case RTW89_CHANNEL_WIDTH_20:
1497 case RTW89_CHANNEL_WIDTH_40:
1498 case RTW89_CHANNEL_WIDTH_80:
1499 rtw89_phy_write32_mask(rtwdev, R_AFEDAC0 + cr_ofst, B_AFEDAC0, 0xE);
1500 rtw89_phy_write32_mask(rtwdev, R_AFEDAC1 + cr_ofst, B_AFEDAC1, 0x7);
1501 break;
1502 case RTW89_CHANNEL_WIDTH_160:
1503 rtw89_phy_write32_mask(rtwdev, R_AFEDAC0 + cr_ofst, B_AFEDAC0, 0xD);
1504 rtw89_phy_write32_mask(rtwdev, R_AFEDAC1 + cr_ofst, B_AFEDAC1, 0x6);
1505 break;
1506 default:
1507 break;
1508 }
1509 }
1510
1511 static const struct rtw89_reg2_def bb_mcu0_init_reg[] = {
1512 {0x6990, 0x00000000},
1513 {0x6994, 0x00000000},
1514 {0x6998, 0x00000000},
1515 {0x6820, 0xFFFFFFFE},
1516 {0x6800, 0xC0000FFE},
1517 {0x6808, 0x76543210},
1518 {0x6814, 0xBFBFB000},
1519 {0x6818, 0x0478C009},
1520 {0x6800, 0xC0000FFF},
1521 {0x6820, 0xFFFFFFFF},
1522 };
1523
1524 static const struct rtw89_reg2_def bb_mcu1_init_reg[] = {
1525 {0x6990, 0x00000000},
1526 {0x6994, 0x00000000},
1527 {0x6998, 0x00000000},
1528 {0x6820, 0xFFFFFFFE},
1529 {0x6800, 0xC0000FFE},
1530 {0x6808, 0x76543210},
1531 {0x6814, 0xBFBFB000},
1532 {0x6818, 0x0478C009},
1533 {0x6800, 0xC0000FFF},
1534 {0x6820, 0xFFFFFFFF},
1535 };
1536
rtw8922a_bbmcu_cr_init(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx)1537 static void rtw8922a_bbmcu_cr_init(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx)
1538 {
1539 const struct rtw89_reg2_def *reg;
1540 int size;
1541 int i;
1542
1543 if (phy_idx == RTW89_PHY_0) {
1544 reg = bb_mcu0_init_reg;
1545 size = ARRAY_SIZE(bb_mcu0_init_reg);
1546 } else {
1547 reg = bb_mcu1_init_reg;
1548 size = ARRAY_SIZE(bb_mcu1_init_reg);
1549 }
1550
1551 for (i = 0; i < size; i++, reg++)
1552 rtw89_bbmcu_write32(rtwdev, reg->addr, reg->data, phy_idx);
1553 }
1554
1555 static const u32 dmac_sys_mask[2] = {B_BE_DMAC_BB_PHY0_MASK, B_BE_DMAC_BB_PHY1_MASK};
1556 static const u32 bbrst_mask[2] = {B_BE_FEN_BBPLAT_RSTB, B_BE_FEN_BB1PLAT_RSTB};
1557 static const u32 glbrst_mask[2] = {B_BE_FEN_BB_IP_RSTN, B_BE_FEN_BB1_IP_RSTN};
1558 static const u32 mcu_bootrdy_mask[2] = {B_BE_BOOT_RDY0, B_BE_BOOT_RDY1};
1559
rtw8922a_bb_preinit(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx)1560 static void rtw8922a_bb_preinit(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx)
1561 {
1562 u32 rdy = 0;
1563
1564 if (phy_idx == RTW89_PHY_1)
1565 rdy = 1;
1566
1567 rtw89_write32_mask(rtwdev, R_BE_DMAC_SYS_CR32B, dmac_sys_mask[phy_idx], 0x7FF9);
1568 rtw89_write32_mask(rtwdev, R_BE_FEN_RST_ENABLE, glbrst_mask[phy_idx], 0x0);
1569 rtw89_write32_mask(rtwdev, R_BE_FEN_RST_ENABLE, bbrst_mask[phy_idx], 0x0);
1570 rtw89_write32_mask(rtwdev, R_BE_FEN_RST_ENABLE, glbrst_mask[phy_idx], 0x1);
1571 rtw89_write32_mask(rtwdev, R_BE_FEN_RST_ENABLE, mcu_bootrdy_mask[phy_idx], rdy);
1572 rtw89_write32_mask(rtwdev, R_BE_MEM_PWR_CTRL, B_BE_MEM_BBMCU0_DS_V1, 0);
1573
1574 fsleep(1);
1575 rtw8922a_bbmcu_cr_init(rtwdev, phy_idx);
1576 }
1577
rtw8922a_bb_postinit(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx)1578 static void rtw8922a_bb_postinit(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx)
1579 {
1580 if (phy_idx == RTW89_PHY_0)
1581 rtw89_write32_set(rtwdev, R_BE_FEN_RST_ENABLE, mcu_bootrdy_mask[phy_idx]);
1582 rtw89_write32_set(rtwdev, R_BE_FEN_RST_ENABLE, bbrst_mask[phy_idx]);
1583
1584 rtw89_phy_write32_set(rtwdev, R_BBCLK, B_CLK_640M);
1585 rtw89_phy_write32_clr(rtwdev, R_TXSCALE, B_TXFCTR_EN);
1586 rtw89_phy_set_phy_regs(rtwdev, R_TXFCTR, B_TXFCTR_THD, 0x200);
1587 rtw89_phy_set_phy_regs(rtwdev, R_SLOPE, B_EHT_RATE_TH, 0xA);
1588 rtw89_phy_set_phy_regs(rtwdev, R_BEDGE, B_HE_RATE_TH, 0xA);
1589 rtw89_phy_set_phy_regs(rtwdev, R_BEDGE2, B_HT_VHT_TH, 0xAAA);
1590 rtw89_phy_set_phy_regs(rtwdev, R_BEDGE, B_EHT_MCS14, 0x1);
1591 rtw89_phy_set_phy_regs(rtwdev, R_BEDGE2, B_EHT_MCS15, 0x1);
1592 rtw89_phy_set_phy_regs(rtwdev, R_BEDGE3, B_EHTTB_EN, 0x0);
1593 rtw89_phy_set_phy_regs(rtwdev, R_BEDGE3, B_HEERSU_EN, 0x0);
1594 rtw89_phy_set_phy_regs(rtwdev, R_BEDGE3, B_HEMU_EN, 0x0);
1595 rtw89_phy_set_phy_regs(rtwdev, R_BEDGE3, B_TB_EN, 0x0);
1596 rtw89_phy_set_phy_regs(rtwdev, R_SU_PUNC, B_SU_PUNC_EN, 0x1);
1597 rtw89_phy_set_phy_regs(rtwdev, R_BEDGE5, B_HWGEN_EN, 0x1);
1598 rtw89_phy_set_phy_regs(rtwdev, R_BEDGE5, B_PWROFST_COMP, 0x1);
1599 rtw89_phy_set_phy_regs(rtwdev, R_MAG_AB, B_BY_SLOPE, 0x1);
1600 rtw89_phy_set_phy_regs(rtwdev, R_MAG_A, B_MGA_AEND, 0xe0);
1601 rtw89_phy_set_phy_regs(rtwdev, R_MAG_AB, B_MAG_AB, 0xe0c000);
1602 rtw89_phy_set_phy_regs(rtwdev, R_SLOPE, B_SLOPE_A, 0x3FE0);
1603 rtw89_phy_set_phy_regs(rtwdev, R_SLOPE, B_SLOPE_B, 0x3FE0);
1604 rtw89_phy_set_phy_regs(rtwdev, R_SC_CORNER, B_SC_CORNER, 0x200);
1605 rtw89_phy_write32_idx(rtwdev, R_UDP_COEEF, B_UDP_COEEF, 0x0, phy_idx);
1606 rtw89_phy_write32_idx(rtwdev, R_UDP_COEEF, B_UDP_COEEF, 0x1, phy_idx);
1607 }
1608
rtw8922a_bb_reset_en(struct rtw89_dev * rtwdev,enum rtw89_band band,bool en,enum rtw89_phy_idx phy_idx)1609 static void rtw8922a_bb_reset_en(struct rtw89_dev *rtwdev, enum rtw89_band band,
1610 bool en, enum rtw89_phy_idx phy_idx)
1611 {
1612 if (en) {
1613 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1, phy_idx);
1614 if (band == RTW89_BAND_2G)
1615 rtw89_phy_write32_idx(rtwdev, R_RXCCA_BE1,
1616 B_RXCCA_BE1_DIS, 0x0, phy_idx);
1617 rtw89_phy_write32_idx(rtwdev, R_PD_CTRL, B_PD_HIT_DIS, 0x0, phy_idx);
1618 } else {
1619 rtw89_phy_write32_idx(rtwdev, R_RXCCA_BE1, B_RXCCA_BE1_DIS, 0x1, phy_idx);
1620 rtw89_phy_write32_idx(rtwdev, R_PD_CTRL, B_PD_HIT_DIS, 0x1, phy_idx);
1621 fsleep(1);
1622 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 0, phy_idx);
1623 }
1624 }
1625
rtw8922a_ctrl_tx_path_tmac(struct rtw89_dev * rtwdev,enum rtw89_rf_path tx_path,enum rtw89_phy_idx phy_idx)1626 static int rtw8922a_ctrl_tx_path_tmac(struct rtw89_dev *rtwdev,
1627 enum rtw89_rf_path tx_path,
1628 enum rtw89_phy_idx phy_idx)
1629 {
1630 struct rtw89_reg2_def path_com_cr[] = {
1631 {0x11A00, 0x21C86900},
1632 {0x11A04, 0x00E4E433},
1633 {0x11A08, 0x39390CC9},
1634 {0x11A0C, 0x4E433240},
1635 {0x11A10, 0x90CC900E},
1636 {0x11A14, 0x00240393},
1637 {0x11A18, 0x201C8600},
1638 };
1639 int ret = 0;
1640 u32 reg;
1641 int i;
1642
1643 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL, 0x0, phy_idx);
1644
1645 if (phy_idx == RTW89_PHY_1 && !rtwdev->dbcc_en)
1646 return 0;
1647
1648 if (tx_path == RF_PATH_A) {
1649 path_com_cr[0].data = 0x21C82900;
1650 path_com_cr[1].data = 0x00E4E431;
1651 path_com_cr[2].data = 0x39390C49;
1652 path_com_cr[3].data = 0x4E431240;
1653 path_com_cr[4].data = 0x90C4900E;
1654 path_com_cr[6].data = 0x201C8200;
1655 } else if (tx_path == RF_PATH_B) {
1656 path_com_cr[0].data = 0x21C04900;
1657 path_com_cr[1].data = 0x00E4E032;
1658 path_com_cr[2].data = 0x39380C89;
1659 path_com_cr[3].data = 0x4E032240;
1660 path_com_cr[4].data = 0x80C8900E;
1661 path_com_cr[6].data = 0x201C0400;
1662 } else if (tx_path == RF_PATH_AB) {
1663 path_com_cr[0].data = 0x21C86900;
1664 path_com_cr[1].data = 0x00E4E433;
1665 path_com_cr[2].data = 0x39390CC9;
1666 path_com_cr[3].data = 0x4E433240;
1667 path_com_cr[4].data = 0x90CC900E;
1668 path_com_cr[6].data = 0x201C8600;
1669 } else {
1670 ret = -EINVAL;
1671 }
1672
1673 for (i = 0; i < ARRAY_SIZE(path_com_cr); i++) {
1674 reg = rtw89_mac_reg_by_idx(rtwdev, path_com_cr[i].addr, phy_idx);
1675 rtw89_write32(rtwdev, reg, path_com_cr[i].data);
1676 }
1677
1678 return ret;
1679 }
1680
rtw8922a_bb_reset(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx)1681 static void rtw8922a_bb_reset(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx)
1682 {
1683 }
1684
rtw8922a_cfg_rx_nss_limit(struct rtw89_dev * rtwdev,u8 rx_nss,enum rtw89_phy_idx phy_idx)1685 static int rtw8922a_cfg_rx_nss_limit(struct rtw89_dev *rtwdev, u8 rx_nss,
1686 enum rtw89_phy_idx phy_idx)
1687 {
1688 if (rx_nss == 1) {
1689 rtw89_phy_write32_idx(rtwdev, R_BRK_R, B_HTMCS_LMT, 0, phy_idx);
1690 rtw89_phy_write32_idx(rtwdev, R_BRK_R, B_VHTMCS_LMT, 0, phy_idx);
1691 rtw89_phy_write32_idx(rtwdev, R_BRK_HE, B_N_USR_MAX,
1692 HE_N_USER_MAX_8922A, phy_idx);
1693 rtw89_phy_write32_idx(rtwdev, R_BRK_HE, B_NSS_MAX, 0, phy_idx);
1694 rtw89_phy_write32_idx(rtwdev, R_BRK_HE, B_TB_NSS_MAX, 0, phy_idx);
1695 rtw89_phy_write32_idx(rtwdev, R_BRK_EHT, B_RXEHT_NSS_MAX, 0, phy_idx);
1696 rtw89_phy_write32_idx(rtwdev, R_BRK_RXEHT, B_RXEHTTB_NSS_MAX, 0,
1697 phy_idx);
1698 rtw89_phy_write32_idx(rtwdev, R_BRK_RXEHT, B_RXEHT_N_USER_MAX,
1699 HE_N_USER_MAX_8922A, phy_idx);
1700 } else if (rx_nss == 2) {
1701 rtw89_phy_write32_idx(rtwdev, R_BRK_R, B_HTMCS_LMT, 1, phy_idx);
1702 rtw89_phy_write32_idx(rtwdev, R_BRK_R, B_VHTMCS_LMT, 1, phy_idx);
1703 rtw89_phy_write32_idx(rtwdev, R_BRK_HE, B_N_USR_MAX,
1704 HE_N_USER_MAX_8922A, phy_idx);
1705 rtw89_phy_write32_idx(rtwdev, R_BRK_HE, B_NSS_MAX, 1, phy_idx);
1706 rtw89_phy_write32_idx(rtwdev, R_BRK_HE, B_TB_NSS_MAX, 1, phy_idx);
1707 rtw89_phy_write32_idx(rtwdev, R_BRK_EHT, B_RXEHT_NSS_MAX, 1, phy_idx);
1708 rtw89_phy_write32_idx(rtwdev, R_BRK_RXEHT, B_RXEHTTB_NSS_MAX, 1,
1709 phy_idx);
1710 rtw89_phy_write32_idx(rtwdev, R_BRK_RXEHT, B_RXEHT_N_USER_MAX,
1711 HE_N_USER_MAX_8922A, phy_idx);
1712 } else {
1713 return -EINVAL;
1714 }
1715
1716 return 0;
1717 }
1718
rtw8922a_tssi_reset(struct rtw89_dev * rtwdev,enum rtw89_rf_path path,enum rtw89_phy_idx phy_idx)1719 static void rtw8922a_tssi_reset(struct rtw89_dev *rtwdev,
1720 enum rtw89_rf_path path,
1721 enum rtw89_phy_idx phy_idx)
1722 {
1723 if (rtwdev->mlo_dbcc_mode == MLO_1_PLUS_1_1RF) {
1724 if (phy_idx == RTW89_PHY_0) {
1725 rtw89_phy_write32_mask(rtwdev, R_TXPWR_RSTA, B_TXPWR_RSTA, 0x0);
1726 rtw89_phy_write32_mask(rtwdev, R_TXPWR_RSTA, B_TXPWR_RSTA, 0x1);
1727 } else {
1728 rtw89_phy_write32_mask(rtwdev, R_TXPWR_RSTB, B_TXPWR_RSTB, 0x0);
1729 rtw89_phy_write32_mask(rtwdev, R_TXPWR_RSTB, B_TXPWR_RSTB, 0x1);
1730 }
1731 } else {
1732 rtw89_phy_write32_mask(rtwdev, R_TXPWR_RSTA, B_TXPWR_RSTA, 0x0);
1733 rtw89_phy_write32_mask(rtwdev, R_TXPWR_RSTA, B_TXPWR_RSTA, 0x1);
1734 rtw89_phy_write32_mask(rtwdev, R_TXPWR_RSTB, B_TXPWR_RSTB, 0x0);
1735 rtw89_phy_write32_mask(rtwdev, R_TXPWR_RSTB, B_TXPWR_RSTB, 0x1);
1736 }
1737 }
1738
rtw8922a_ctrl_rx_path_tmac(struct rtw89_dev * rtwdev,enum rtw89_rf_path rx_path,enum rtw89_phy_idx phy_idx)1739 static int rtw8922a_ctrl_rx_path_tmac(struct rtw89_dev *rtwdev,
1740 enum rtw89_rf_path rx_path,
1741 enum rtw89_phy_idx phy_idx)
1742 {
1743 u8 rx_nss = (rx_path == RF_PATH_AB) ? 2 : 1;
1744
1745 /* Set to 0 first to avoid abnormal EDCCA report */
1746 rtw89_phy_write32_idx(rtwdev, R_ANT_CHBW, B_ANT_RX_SG0, 0x0, phy_idx);
1747
1748 if (rx_path == RF_PATH_A) {
1749 rtw89_phy_write32_idx(rtwdev, R_ANT_CHBW, B_ANT_RX_SG0, 0x1, phy_idx);
1750 rtw89_phy_write32_idx(rtwdev, R_FC0INV_SBW, B_RX_1RCCA, 1, phy_idx);
1751 rtw8922a_cfg_rx_nss_limit(rtwdev, rx_nss, phy_idx);
1752 rtw8922a_tssi_reset(rtwdev, rx_path, phy_idx);
1753 } else if (rx_path == RF_PATH_B) {
1754 rtw89_phy_write32_idx(rtwdev, R_ANT_CHBW, B_ANT_RX_SG0, 0x2, phy_idx);
1755 rtw89_phy_write32_idx(rtwdev, R_FC0INV_SBW, B_RX_1RCCA, 2, phy_idx);
1756 rtw8922a_cfg_rx_nss_limit(rtwdev, rx_nss, phy_idx);
1757 rtw8922a_tssi_reset(rtwdev, rx_path, phy_idx);
1758 } else if (rx_path == RF_PATH_AB) {
1759 rtw89_phy_write32_idx(rtwdev, R_ANT_CHBW, B_ANT_RX_SG0, 0x3, phy_idx);
1760 rtw89_phy_write32_idx(rtwdev, R_FC0INV_SBW, B_RX_1RCCA, 3, phy_idx);
1761 rtw8922a_cfg_rx_nss_limit(rtwdev, rx_nss, phy_idx);
1762 rtw8922a_tssi_reset(rtwdev, rx_path, phy_idx);
1763 } else {
1764 return -EINVAL;
1765 }
1766
1767 return 0;
1768 }
1769
1770 #define DIGITAL_PWR_COMP_REG_NUM 22
1771 static const u32 rtw8922a_digital_pwr_comp_2g_s0_val[][DIGITAL_PWR_COMP_REG_NUM] = {
1772 {0x012C0064, 0x04B00258, 0x00432710, 0x019000A7, 0x06400320,
1773 0x0D05091D, 0x14D50FA0, 0x00000000, 0x01010000, 0x00000101,
1774 0x01010101, 0x02020201, 0x02010000, 0x03030202, 0x00000303,
1775 0x03020101, 0x06060504, 0x01010000, 0x06050403, 0x01000606,
1776 0x05040202, 0x07070706},
1777 {0x012C0064, 0x04B00258, 0x00432710, 0x019000A7, 0x06400320,
1778 0x0D05091D, 0x14D50FA0, 0x00000000, 0x01010100, 0x00000101,
1779 0x01000000, 0x01010101, 0x01010000, 0x02020202, 0x00000404,
1780 0x03020101, 0x04040303, 0x02010000, 0x03030303, 0x00000505,
1781 0x03030201, 0x05050303},
1782 };
1783
1784 static const u32 rtw8922a_digital_pwr_comp_2g_s1_val[][DIGITAL_PWR_COMP_REG_NUM] = {
1785 {0x012C0064, 0x04B00258, 0x00432710, 0x019000A7, 0x06400320,
1786 0x0D05091D, 0x14D50FA0, 0x01010000, 0x01010101, 0x00000101,
1787 0x01010100, 0x01010101, 0x01010000, 0x02020202, 0x01000202,
1788 0x02020101, 0x03030202, 0x02010000, 0x05040403, 0x01000606,
1789 0x05040302, 0x07070605},
1790 {0x012C0064, 0x04B00258, 0x00432710, 0x019000A7, 0x06400320,
1791 0x0D05091D, 0x14D50FA0, 0x00000000, 0x01010100, 0x00000101,
1792 0x01010000, 0x02020201, 0x02010100, 0x03030202, 0x01000404,
1793 0x04030201, 0x05050404, 0x01010100, 0x04030303, 0x01000505,
1794 0x03030101, 0x05050404},
1795 };
1796
1797 static const u32 rtw8922a_digital_pwr_comp_val[][DIGITAL_PWR_COMP_REG_NUM] = {
1798 {0x012C0096, 0x044C02BC, 0x00322710, 0x015E0096, 0x03C8028A,
1799 0x0BB80708, 0x17701194, 0x02020100, 0x03030303, 0x01000303,
1800 0x05030302, 0x06060605, 0x06050300, 0x0A090807, 0x02000B0B,
1801 0x09080604, 0x0D0D0C0B, 0x08060400, 0x110F0C0B, 0x05001111,
1802 0x0D0C0907, 0x12121210},
1803 {0x012C0096, 0x044C02BC, 0x00322710, 0x015E0096, 0x03C8028A,
1804 0x0BB80708, 0x17701194, 0x04030201, 0x05050505, 0x01000505,
1805 0x07060504, 0x09090908, 0x09070400, 0x0E0D0C0B, 0x03000E0E,
1806 0x0D0B0907, 0x1010100F, 0x0B080500, 0x1512100D, 0x05001515,
1807 0x100D0B08, 0x15151512},
1808 };
1809
rtw8922a_set_digital_pwr_comp(struct rtw89_dev * rtwdev,u8 band,u8 nss,enum rtw89_rf_path path)1810 static void rtw8922a_set_digital_pwr_comp(struct rtw89_dev *rtwdev,
1811 u8 band, u8 nss,
1812 enum rtw89_rf_path path)
1813 {
1814 static const u32 ltpc_t0[2] = {R_BE_LTPC_T0_PATH0, R_BE_LTPC_T0_PATH1};
1815 const u32 *digital_pwr_comp;
1816 u32 addr, val;
1817 u32 i;
1818
1819 if (nss == 1) {
1820 if (band == RTW89_BAND_2G)
1821 digital_pwr_comp = path == RF_PATH_A ?
1822 rtw8922a_digital_pwr_comp_2g_s0_val[0] :
1823 rtw8922a_digital_pwr_comp_2g_s1_val[0];
1824 else
1825 digital_pwr_comp = rtw8922a_digital_pwr_comp_val[0];
1826 } else {
1827 if (band == RTW89_BAND_2G)
1828 digital_pwr_comp = path == RF_PATH_A ?
1829 rtw8922a_digital_pwr_comp_2g_s0_val[1] :
1830 rtw8922a_digital_pwr_comp_2g_s1_val[1];
1831 else
1832 digital_pwr_comp = rtw8922a_digital_pwr_comp_val[1];
1833 }
1834
1835 addr = ltpc_t0[path];
1836 for (i = 0; i < DIGITAL_PWR_COMP_REG_NUM; i++, addr += 4) {
1837 val = digital_pwr_comp[i];
1838 rtw89_phy_write32(rtwdev, addr, val);
1839 }
1840 }
1841
rtw8922a_digital_pwr_comp(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx)1842 static void rtw8922a_digital_pwr_comp(struct rtw89_dev *rtwdev,
1843 enum rtw89_phy_idx phy_idx)
1844 {
1845 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_CHANCTX_0);
1846 u8 band = chan->band_type;
1847 u8 path;
1848
1849 if (rtwdev->mlo_dbcc_mode == MLO_1_PLUS_1_1RF) {
1850 if (phy_idx == RTW89_PHY_0)
1851 path = RF_PATH_A;
1852 else
1853 path = RF_PATH_B;
1854 rtw8922a_set_digital_pwr_comp(rtwdev, band, 1, path);
1855 } else {
1856 rtw8922a_set_digital_pwr_comp(rtwdev, band, 2, RF_PATH_A);
1857 rtw8922a_set_digital_pwr_comp(rtwdev, band, 2, RF_PATH_B);
1858 }
1859 }
1860
rtw8922a_ctrl_mlo(struct rtw89_dev * rtwdev,enum rtw89_mlo_dbcc_mode mode)1861 static int rtw8922a_ctrl_mlo(struct rtw89_dev *rtwdev, enum rtw89_mlo_dbcc_mode mode)
1862 {
1863 const struct rtw89_chan *chan0, *chan1;
1864
1865 if (mode == MLO_1_PLUS_1_1RF || mode == DBCC_LEGACY) {
1866 rtw89_phy_write32_mask(rtwdev, R_DBCC, B_DBCC_EN, 0x1);
1867 rtw89_phy_write32_mask(rtwdev, R_DBCC_FA, B_DBCC_FA, 0x0);
1868 } else if (mode == MLO_2_PLUS_0_1RF || mode == MLO_0_PLUS_2_1RF ||
1869 mode == MLO_DBCC_NOT_SUPPORT) {
1870 rtw89_phy_write32_mask(rtwdev, R_DBCC, B_DBCC_EN, 0x0);
1871 rtw89_phy_write32_mask(rtwdev, R_DBCC_FA, B_DBCC_FA, 0x1);
1872 } else {
1873 return -EOPNOTSUPP;
1874 }
1875
1876 if (mode == MLO_1_PLUS_1_1RF) {
1877 chan0 = rtw89_mgnt_chan_get(rtwdev, 0);
1878 chan1 = rtw89_mgnt_chan_get(rtwdev, 1);
1879 } else if (mode == MLO_0_PLUS_2_1RF) {
1880 chan1 = rtw89_mgnt_chan_get(rtwdev, 1);
1881 chan0 = chan1;
1882 } else {
1883 chan0 = rtw89_mgnt_chan_get(rtwdev, 0);
1884 chan1 = chan0;
1885 }
1886
1887 rtw8922a_ctrl_afe_dac(rtwdev, chan0->band_width, RF_PATH_A);
1888 rtw8922a_ctrl_afe_dac(rtwdev, chan1->band_width, RF_PATH_B);
1889
1890 rtw89_phy_write32_mask(rtwdev, R_EMLSR, B_EMLSR_PARM, 0x6180);
1891
1892 if (mode == MLO_2_PLUS_0_1RF) {
1893 rtw89_phy_write32_mask(rtwdev, R_EMLSR, B_EMLSR_PARM, 0xBBAB);
1894 rtw89_phy_write32_mask(rtwdev, R_EMLSR, B_EMLSR_PARM, 0xABA9);
1895 rtw89_phy_write32_mask(rtwdev, R_EMLSR, B_EMLSR_PARM, 0xEBA9);
1896 rtw89_phy_write32_mask(rtwdev, R_EMLSR, B_EMLSR_PARM, 0xEAA9);
1897 } else if (mode == MLO_0_PLUS_2_1RF) {
1898 rtw89_phy_write32_mask(rtwdev, R_EMLSR, B_EMLSR_PARM, 0xBBAB);
1899 rtw89_phy_write32_mask(rtwdev, R_EMLSR, B_EMLSR_PARM, 0xAFFF);
1900 rtw89_phy_write32_mask(rtwdev, R_EMLSR, B_EMLSR_PARM, 0xEFFF);
1901 rtw89_phy_write32_mask(rtwdev, R_EMLSR, B_EMLSR_PARM, 0xEEFF);
1902 } else if ((mode == MLO_1_PLUS_1_1RF) || (mode == DBCC_LEGACY)) {
1903 rtw89_phy_write32_mask(rtwdev, R_EMLSR, B_EMLSR_PARM, 0x7BAB);
1904 rtw89_phy_write32_mask(rtwdev, R_EMLSR, B_EMLSR_PARM, 0x3BAB);
1905 rtw89_phy_write32_mask(rtwdev, R_EMLSR, B_EMLSR_PARM, 0x3AAB);
1906 } else {
1907 rtw89_phy_write32_mask(rtwdev, R_EMLSR, B_EMLSR_PARM, 0x180);
1908 rtw89_phy_write32_mask(rtwdev, R_EMLSR, B_EMLSR_PARM, 0x0);
1909 }
1910
1911 return 0;
1912 }
1913
rtw8922a_bb_sethw(struct rtw89_dev * rtwdev)1914 static void rtw8922a_bb_sethw(struct rtw89_dev *rtwdev)
1915 {
1916 u32 reg;
1917
1918 rtw89_phy_write32_clr(rtwdev, R_EN_SND_WO_NDP, B_EN_SND_WO_NDP);
1919 rtw89_phy_write32_clr(rtwdev, R_EN_SND_WO_NDP_C1, B_EN_SND_WO_NDP);
1920
1921 rtw89_write32_mask(rtwdev, R_BE_PWR_BOOST, B_BE_PWR_CTRL_SEL, 0);
1922 if (rtwdev->dbcc_en) {
1923 reg = rtw89_mac_reg_by_idx(rtwdev, R_BE_PWR_BOOST, RTW89_MAC_1);
1924 rtw89_write32_mask(rtwdev, reg, B_BE_PWR_CTRL_SEL, 0);
1925 }
1926
1927 rtw8922a_ctrl_mlo(rtwdev, rtwdev->mlo_dbcc_mode);
1928 }
1929
rtw8922a_ctrl_cck_en(struct rtw89_dev * rtwdev,bool cck_en,enum rtw89_phy_idx phy_idx)1930 static void rtw8922a_ctrl_cck_en(struct rtw89_dev *rtwdev, bool cck_en,
1931 enum rtw89_phy_idx phy_idx)
1932 {
1933 if (cck_en) {
1934 rtw89_phy_write32_idx(rtwdev, R_RXCCA_BE1, B_RXCCA_BE1_DIS, 0, phy_idx);
1935 rtw89_phy_write32_idx(rtwdev, R_UPD_CLK_ADC, B_ENABLE_CCK, 1, phy_idx);
1936 rtw89_phy_write32_idx(rtwdev, R_PD_ARBITER_OFF, B_PD_ARBITER_OFF,
1937 0, phy_idx);
1938 } else {
1939 rtw89_phy_write32_idx(rtwdev, R_RXCCA_BE1, B_RXCCA_BE1_DIS, 1, phy_idx);
1940 rtw89_phy_write32_idx(rtwdev, R_UPD_CLK_ADC, B_ENABLE_CCK, 0, phy_idx);
1941 rtw89_phy_write32_idx(rtwdev, R_PD_ARBITER_OFF, B_PD_ARBITER_OFF,
1942 1, phy_idx);
1943 }
1944 }
1945
rtw8922a_set_channel_bb(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_phy_idx phy_idx)1946 static void rtw8922a_set_channel_bb(struct rtw89_dev *rtwdev,
1947 const struct rtw89_chan *chan,
1948 enum rtw89_phy_idx phy_idx)
1949 {
1950 bool cck_en = chan->band_type == RTW89_BAND_2G;
1951 u8 pri_sb = chan->pri_sb_idx;
1952
1953 if (cck_en)
1954 rtw8922a_ctrl_sco_cck(rtwdev, chan->primary_channel,
1955 chan->band_width, phy_idx);
1956
1957 rtw8922a_ctrl_ch(rtwdev, chan, phy_idx);
1958 rtw8922a_ctrl_bw(rtwdev, pri_sb, chan->band_width, phy_idx);
1959 rtw8922a_ctrl_cck_en(rtwdev, cck_en, phy_idx);
1960 rtw8922a_spur_elimination(rtwdev, chan, phy_idx);
1961
1962 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1, phy_idx);
1963 rtw8922a_tssi_reset(rtwdev, RF_PATH_AB, phy_idx);
1964 }
1965
rtw8922a_pre_set_channel_bb(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx)1966 static void rtw8922a_pre_set_channel_bb(struct rtw89_dev *rtwdev,
1967 enum rtw89_phy_idx phy_idx)
1968 {
1969 if (!rtwdev->dbcc_en)
1970 return;
1971
1972 if (phy_idx == RTW89_PHY_0) {
1973 rtw89_phy_write32_mask(rtwdev, R_DBCC, B_DBCC_EN, 0x0);
1974 rtw89_phy_write32_mask(rtwdev, R_EMLSR, B_EMLSR_PARM, 0x6180);
1975 rtw89_phy_write32_mask(rtwdev, R_EMLSR, B_EMLSR_PARM, 0xBBAB);
1976 rtw89_phy_write32_mask(rtwdev, R_EMLSR, B_EMLSR_PARM, 0xABA9);
1977 rtw89_phy_write32_mask(rtwdev, R_EMLSR, B_EMLSR_PARM, 0xEBA9);
1978 rtw89_phy_write32_mask(rtwdev, R_EMLSR, B_EMLSR_PARM, 0xEAA9);
1979 } else {
1980 rtw89_phy_write32_mask(rtwdev, R_DBCC, B_DBCC_EN, 0x0);
1981 rtw89_phy_write32_mask(rtwdev, R_EMLSR, B_EMLSR_PARM, 0xBBAB);
1982 rtw89_phy_write32_mask(rtwdev, R_EMLSR, B_EMLSR_PARM, 0xAFFF);
1983 rtw89_phy_write32_mask(rtwdev, R_EMLSR, B_EMLSR_PARM, 0xEFFF);
1984 rtw89_phy_write32_mask(rtwdev, R_EMLSR, B_EMLSR_PARM, 0xEEFF);
1985 }
1986 }
1987
rtw8922a_post_set_channel_bb(struct rtw89_dev * rtwdev,enum rtw89_mlo_dbcc_mode mode,enum rtw89_phy_idx phy_idx)1988 static void rtw8922a_post_set_channel_bb(struct rtw89_dev *rtwdev,
1989 enum rtw89_mlo_dbcc_mode mode,
1990 enum rtw89_phy_idx phy_idx)
1991 {
1992 if (!rtwdev->dbcc_en)
1993 return;
1994
1995 rtw8922a_digital_pwr_comp(rtwdev, phy_idx);
1996 rtw8922a_ctrl_mlo(rtwdev, mode);
1997 }
1998
rtw8922a_set_channel(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_mac_idx mac_idx,enum rtw89_phy_idx phy_idx)1999 static void rtw8922a_set_channel(struct rtw89_dev *rtwdev,
2000 const struct rtw89_chan *chan,
2001 enum rtw89_mac_idx mac_idx,
2002 enum rtw89_phy_idx phy_idx)
2003 {
2004 rtw8922a_set_channel_mac(rtwdev, chan, mac_idx);
2005 rtw8922a_set_channel_bb(rtwdev, chan, phy_idx);
2006 rtw8922a_set_channel_rf(rtwdev, chan, phy_idx);
2007 }
2008
rtw8922a_dfs_en_idx(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx,enum rtw89_rf_path path,bool en)2009 static void rtw8922a_dfs_en_idx(struct rtw89_dev *rtwdev,
2010 enum rtw89_phy_idx phy_idx, enum rtw89_rf_path path,
2011 bool en)
2012 {
2013 u32 path_ofst = (path == RF_PATH_B) ? 0x100 : 0x0;
2014
2015 if (en)
2016 rtw89_phy_write32_idx(rtwdev, 0x2800 + path_ofst, BIT(1), 1,
2017 phy_idx);
2018 else
2019 rtw89_phy_write32_idx(rtwdev, 0x2800 + path_ofst, BIT(1), 0,
2020 phy_idx);
2021 }
2022
rtw8922a_dfs_en(struct rtw89_dev * rtwdev,bool en,enum rtw89_phy_idx phy_idx)2023 static void rtw8922a_dfs_en(struct rtw89_dev *rtwdev, bool en,
2024 enum rtw89_phy_idx phy_idx)
2025 {
2026 rtw8922a_dfs_en_idx(rtwdev, phy_idx, RF_PATH_A, en);
2027 rtw8922a_dfs_en_idx(rtwdev, phy_idx, RF_PATH_B, en);
2028 }
2029
rtw8922a_adc_en_path(struct rtw89_dev * rtwdev,enum rtw89_rf_path path,bool en)2030 static void rtw8922a_adc_en_path(struct rtw89_dev *rtwdev,
2031 enum rtw89_rf_path path, bool en)
2032 {
2033 u32 val;
2034
2035 val = rtw89_phy_read32_mask(rtwdev, R_ADC_FIFO_V1, B_ADC_FIFO_EN_V1);
2036
2037 if (en) {
2038 if (path == RF_PATH_A)
2039 val &= ~0x1;
2040 else
2041 val &= ~0x2;
2042 } else {
2043 if (path == RF_PATH_A)
2044 val |= 0x1;
2045 else
2046 val |= 0x2;
2047 }
2048
2049 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO_V1, B_ADC_FIFO_EN_V1, val);
2050 }
2051
rtw8922a_adc_en(struct rtw89_dev * rtwdev,bool en,u8 phy_idx)2052 static void rtw8922a_adc_en(struct rtw89_dev *rtwdev, bool en, u8 phy_idx)
2053 {
2054 if (rtwdev->mlo_dbcc_mode == MLO_1_PLUS_1_1RF) {
2055 if (phy_idx == RTW89_PHY_0)
2056 rtw8922a_adc_en_path(rtwdev, RF_PATH_A, en);
2057 else
2058 rtw8922a_adc_en_path(rtwdev, RF_PATH_B, en);
2059 } else {
2060 rtw8922a_adc_en_path(rtwdev, RF_PATH_A, en);
2061 rtw8922a_adc_en_path(rtwdev, RF_PATH_B, en);
2062 }
2063 }
2064
2065 static
rtw8922a_hal_reset(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx,enum rtw89_mac_idx mac_idx,enum rtw89_band band,u32 * tx_en,bool enter)2066 void rtw8922a_hal_reset(struct rtw89_dev *rtwdev,
2067 enum rtw89_phy_idx phy_idx, enum rtw89_mac_idx mac_idx,
2068 enum rtw89_band band, u32 *tx_en, bool enter)
2069 {
2070 if (enter) {
2071 rtw89_chip_stop_sch_tx(rtwdev, mac_idx, tx_en, RTW89_SCH_TX_SEL_ALL);
2072 rtw89_mac_cfg_ppdu_status(rtwdev, mac_idx, false);
2073 rtw8922a_dfs_en(rtwdev, false, phy_idx);
2074 rtw8922a_tssi_cont_en_phyidx(rtwdev, false, phy_idx);
2075 rtw8922a_adc_en(rtwdev, false, phy_idx);
2076 fsleep(40);
2077 rtw8922a_bb_reset_en(rtwdev, band, false, phy_idx);
2078 } else {
2079 rtw89_mac_cfg_ppdu_status(rtwdev, mac_idx, true);
2080 rtw8922a_adc_en(rtwdev, true, phy_idx);
2081 rtw8922a_dfs_en(rtwdev, true, phy_idx);
2082 rtw8922a_tssi_cont_en_phyidx(rtwdev, true, phy_idx);
2083 rtw8922a_bb_reset_en(rtwdev, band, true, phy_idx);
2084 rtw89_chip_resume_sch_tx(rtwdev, mac_idx, *tx_en);
2085 }
2086 }
2087
rtw8922a_set_channel_help(struct rtw89_dev * rtwdev,bool enter,struct rtw89_channel_help_params * p,const struct rtw89_chan * chan,enum rtw89_mac_idx mac_idx,enum rtw89_phy_idx phy_idx)2088 static void rtw8922a_set_channel_help(struct rtw89_dev *rtwdev, bool enter,
2089 struct rtw89_channel_help_params *p,
2090 const struct rtw89_chan *chan,
2091 enum rtw89_mac_idx mac_idx,
2092 enum rtw89_phy_idx phy_idx)
2093 {
2094 if (enter) {
2095 rtw8922a_pre_set_channel_bb(rtwdev, phy_idx);
2096 rtw8922a_pre_set_channel_rf(rtwdev, phy_idx);
2097 }
2098
2099 rtw8922a_hal_reset(rtwdev, phy_idx, mac_idx, chan->band_type, &p->tx_en, enter);
2100
2101 if (!enter) {
2102 rtw8922a_post_set_channel_bb(rtwdev, rtwdev->mlo_dbcc_mode, phy_idx);
2103 rtw8922a_post_set_channel_rf(rtwdev, phy_idx);
2104 }
2105 }
2106
rtw8922a_rfk_init(struct rtw89_dev * rtwdev)2107 static void rtw8922a_rfk_init(struct rtw89_dev *rtwdev)
2108 {
2109 struct rtw89_rfk_mcc_info *rfk_mcc = &rtwdev->rfk_mcc;
2110
2111 rtwdev->is_tssi_mode[RF_PATH_A] = false;
2112 rtwdev->is_tssi_mode[RF_PATH_B] = false;
2113 memset(rfk_mcc, 0, sizeof(*rfk_mcc));
2114 }
2115
__rtw8922a_rfk_init_late(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx,const struct rtw89_chan * chan)2116 static void __rtw8922a_rfk_init_late(struct rtw89_dev *rtwdev,
2117 enum rtw89_phy_idx phy_idx,
2118 const struct rtw89_chan *chan)
2119 {
2120 rtw89_phy_rfk_pre_ntfy_and_wait(rtwdev, phy_idx, 5);
2121
2122 rtw89_phy_rfk_dack_and_wait(rtwdev, phy_idx, chan, 58);
2123 if (!test_bit(RTW89_FLAG_SER_HANDLING, rtwdev->flags))
2124 rtw89_phy_rfk_rxdck_and_wait(rtwdev, phy_idx, chan, false, 128);
2125 }
2126
rtw8922a_rfk_init_late(struct rtw89_dev * rtwdev)2127 static void rtw8922a_rfk_init_late(struct rtw89_dev *rtwdev)
2128 {
2129 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_CHANCTX_0);
2130
2131 __rtw8922a_rfk_init_late(rtwdev, RTW89_PHY_0, chan);
2132 if (rtwdev->dbcc_en)
2133 __rtw8922a_rfk_init_late(rtwdev, RTW89_PHY_1, chan);
2134 }
2135
_wait_rx_mode(struct rtw89_dev * rtwdev,u8 kpath)2136 static void _wait_rx_mode(struct rtw89_dev *rtwdev, u8 kpath)
2137 {
2138 u32 rf_mode;
2139 u8 path;
2140 int ret;
2141
2142 for (path = 0; path < RF_PATH_NUM_8922A; path++) {
2143 if (!(kpath & BIT(path)))
2144 continue;
2145
2146 ret = read_poll_timeout_atomic(rtw89_read_rf, rf_mode, rf_mode != 2,
2147 2, 5000, false, rtwdev, path, 0x00,
2148 RR_MOD_MASK);
2149 rtw89_debug(rtwdev, RTW89_DBG_RFK,
2150 "[RFK] Wait S%d to Rx mode!! (ret = %d)\n",
2151 path, ret);
2152 }
2153 }
2154
rtw8922a_rfk_channel(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link)2155 static void rtw8922a_rfk_channel(struct rtw89_dev *rtwdev,
2156 struct rtw89_vif_link *rtwvif_link)
2157 {
2158 enum rtw89_chanctx_idx chanctx_idx = rtwvif_link->chanctx_idx;
2159 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, chanctx_idx);
2160 enum rtw89_phy_idx phy_idx = rtwvif_link->phy_idx;
2161 u8 phy_map = rtw89_btc_phymap(rtwdev, phy_idx, RF_AB, chanctx_idx);
2162 u32 tx_en;
2163
2164 rtw89_btc_ntfy_wl_rfk(rtwdev, phy_map, BTC_WRFKT_CHLK, BTC_WRFK_START);
2165 rtw89_chip_stop_sch_tx(rtwdev, phy_idx, &tx_en, RTW89_SCH_TX_SEL_ALL);
2166 _wait_rx_mode(rtwdev, RF_AB);
2167
2168 rtw89_phy_rfk_pre_ntfy_and_wait(rtwdev, phy_idx, 5);
2169 rtw89_phy_rfk_txgapk_and_wait(rtwdev, phy_idx, chan, 54);
2170 rtw89_phy_rfk_iqk_and_wait(rtwdev, phy_idx, chan, 84);
2171 rtw89_phy_rfk_tssi_and_wait(rtwdev, phy_idx, chan, RTW89_TSSI_NORMAL, 20);
2172 rtw89_phy_rfk_dpk_and_wait(rtwdev, phy_idx, chan, 34);
2173 rtw89_phy_rfk_rxdck_and_wait(rtwdev, RTW89_PHY_0, chan, true, 32);
2174
2175 rtw89_chip_resume_sch_tx(rtwdev, phy_idx, tx_en);
2176 rtw89_btc_ntfy_wl_rfk(rtwdev, phy_map, BTC_WRFKT_CHLK, BTC_WRFK_STOP);
2177 }
2178
rtw8922a_rfk_band_changed(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx,const struct rtw89_chan * chan)2179 static void rtw8922a_rfk_band_changed(struct rtw89_dev *rtwdev,
2180 enum rtw89_phy_idx phy_idx,
2181 const struct rtw89_chan *chan)
2182 {
2183 rtw89_phy_rfk_tssi_and_wait(rtwdev, phy_idx, chan, RTW89_TSSI_SCAN, 6);
2184 }
2185
rtw8922a_rfk_scan(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link,bool start)2186 static void rtw8922a_rfk_scan(struct rtw89_dev *rtwdev,
2187 struct rtw89_vif_link *rtwvif_link,
2188 bool start)
2189 {
2190 }
2191
rtw8922a_rfk_track(struct rtw89_dev * rtwdev)2192 static void rtw8922a_rfk_track(struct rtw89_dev *rtwdev)
2193 {
2194 }
2195
rtw8922a_set_txpwr_ref(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx)2196 static void rtw8922a_set_txpwr_ref(struct rtw89_dev *rtwdev,
2197 enum rtw89_phy_idx phy_idx)
2198 {
2199 s16 ref_ofdm = 0;
2200 s16 ref_cck = 0;
2201
2202 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set txpwr reference\n");
2203
2204 rtw89_mac_txpwr_write32_mask(rtwdev, phy_idx, R_BE_PWR_REF_CTRL,
2205 B_BE_PWR_REF_CTRL_OFDM, ref_ofdm);
2206 rtw89_mac_txpwr_write32_mask(rtwdev, phy_idx, R_BE_PWR_REF_CTRL,
2207 B_BE_PWR_REF_CTRL_CCK, ref_cck);
2208 }
2209
2210 static const struct rtw89_reg_def rtw8922a_txpwr_ref[][3] = {
2211 {{ .addr = R_TXAGC_REF_DBM_P0, .mask = B_TXAGC_OFDM_REF_DBM_P0},
2212 { .addr = R_TXAGC_REF_DBM_P0, .mask = B_TXAGC_CCK_REF_DBM_P0},
2213 { .addr = R_TSSI_K_P0, .mask = B_TSSI_K_OFDM_P0}
2214 },
2215 {{ .addr = R_TXAGC_REF_DBM_RF1_P0, .mask = B_TXAGC_OFDM_REF_DBM_RF1_P0},
2216 { .addr = R_TXAGC_REF_DBM_RF1_P0, .mask = B_TXAGC_CCK_REF_DBM_RF1_P0},
2217 { .addr = R_TSSI_K_RF1_P0, .mask = B_TSSI_K_OFDM_RF1_P0}
2218 },
2219 };
2220
rtw8922a_set_txpwr_diff(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_phy_idx phy_idx)2221 static void rtw8922a_set_txpwr_diff(struct rtw89_dev *rtwdev,
2222 const struct rtw89_chan *chan,
2223 enum rtw89_phy_idx phy_idx)
2224 {
2225 s16 pwr_ofst = rtw89_phy_ant_gain_pwr_offset(rtwdev, chan);
2226 const struct rtw89_chip_info *chip = rtwdev->chip;
2227 static const u32 path_ofst[] = {0x0, 0x100};
2228 const struct rtw89_reg_def *txpwr_ref;
2229 static const s16 tssi_k_base = 0x12;
2230 s16 tssi_k_ofst = abs(pwr_ofst) + tssi_k_base;
2231 s16 ofst_dec[RF_PATH_NUM_8922A];
2232 s16 tssi_k[RF_PATH_NUM_8922A];
2233 s16 pwr_ref_ofst;
2234 s16 pwr_ref = 0;
2235 u8 i;
2236
2237 if (rtwdev->hal.cv == CHIP_CAV)
2238 pwr_ref = 16;
2239
2240 pwr_ref <<= chip->txpwr_factor_rf;
2241 pwr_ref_ofst = pwr_ref - rtw89_phy_txpwr_bb_to_rf(rtwdev, abs(pwr_ofst));
2242
2243 ofst_dec[RF_PATH_A] = pwr_ofst > 0 ? pwr_ref : pwr_ref_ofst;
2244 ofst_dec[RF_PATH_B] = pwr_ofst > 0 ? pwr_ref_ofst : pwr_ref;
2245 tssi_k[RF_PATH_A] = pwr_ofst > 0 ? tssi_k_base : tssi_k_ofst;
2246 tssi_k[RF_PATH_B] = pwr_ofst > 0 ? tssi_k_ofst : tssi_k_base;
2247
2248 for (i = 0; i < RF_PATH_NUM_8922A; i++) {
2249 txpwr_ref = rtw8922a_txpwr_ref[phy_idx];
2250
2251 rtw89_phy_write32_mask(rtwdev, txpwr_ref[0].addr + path_ofst[i],
2252 txpwr_ref[0].mask, ofst_dec[i]);
2253 rtw89_phy_write32_mask(rtwdev, txpwr_ref[1].addr + path_ofst[i],
2254 txpwr_ref[1].mask, ofst_dec[i]);
2255 rtw89_phy_write32_mask(rtwdev, txpwr_ref[2].addr + path_ofst[i],
2256 txpwr_ref[2].mask, tssi_k[i]);
2257 }
2258 }
2259
rtw8922a_bb_tx_triangular(struct rtw89_dev * rtwdev,bool en,enum rtw89_phy_idx phy_idx)2260 static void rtw8922a_bb_tx_triangular(struct rtw89_dev *rtwdev, bool en,
2261 enum rtw89_phy_idx phy_idx)
2262 {
2263 u8 ctrl = en ? 0x1 : 0x0;
2264
2265 rtw89_phy_write32_idx(rtwdev, R_BEDGE3, B_BEDGE_CFG, ctrl, phy_idx);
2266 }
2267
rtw8922a_set_tx_shape(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_phy_idx phy_idx)2268 static void rtw8922a_set_tx_shape(struct rtw89_dev *rtwdev,
2269 const struct rtw89_chan *chan,
2270 enum rtw89_phy_idx phy_idx)
2271 {
2272 const struct rtw89_rfe_parms *rfe_parms = rtwdev->rfe_parms;
2273 const struct rtw89_tx_shape *tx_shape = &rfe_parms->tx_shape;
2274 u8 tx_shape_idx;
2275 u8 band, regd;
2276
2277 band = chan->band_type;
2278 regd = rtw89_regd_get(rtwdev, band);
2279 tx_shape_idx = (*tx_shape->lmt)[band][RTW89_RS_OFDM][regd];
2280
2281 if (tx_shape_idx == 0)
2282 rtw8922a_bb_tx_triangular(rtwdev, false, phy_idx);
2283 else
2284 rtw8922a_bb_tx_triangular(rtwdev, true, phy_idx);
2285 }
2286
rtw8922a_set_txpwr_sar_diff(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_phy_idx phy_idx)2287 static void rtw8922a_set_txpwr_sar_diff(struct rtw89_dev *rtwdev,
2288 const struct rtw89_chan *chan,
2289 enum rtw89_phy_idx phy_idx)
2290 {
2291 struct rtw89_sar_parm sar_parm = {
2292 .center_freq = chan->freq,
2293 .force_path = true,
2294 };
2295 s16 sar_rf;
2296 s8 sar_mac;
2297
2298 if (phy_idx != RTW89_PHY_0)
2299 return;
2300
2301 sar_parm.path = RF_PATH_A;
2302 sar_mac = rtw89_query_sar(rtwdev, &sar_parm);
2303 sar_rf = rtw89_phy_txpwr_mac_to_rf(rtwdev, sar_mac);
2304 rtw89_phy_write32_mask(rtwdev, R_P0_TXPWRB_BE, B_TXPWRB_MAX_BE, sar_rf);
2305
2306 sar_parm.path = RF_PATH_B;
2307 sar_mac = rtw89_query_sar(rtwdev, &sar_parm);
2308 sar_rf = rtw89_phy_txpwr_mac_to_rf(rtwdev, sar_mac);
2309 rtw89_phy_write32_mask(rtwdev, R_P1_TXPWRB_BE, B_TXPWRB_MAX_BE, sar_rf);
2310 }
2311
rtw8922a_set_txpwr(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_phy_idx phy_idx)2312 static void rtw8922a_set_txpwr(struct rtw89_dev *rtwdev,
2313 const struct rtw89_chan *chan,
2314 enum rtw89_phy_idx phy_idx)
2315 {
2316 rtw89_phy_set_txpwr_byrate(rtwdev, chan, phy_idx);
2317 rtw89_phy_set_txpwr_offset(rtwdev, chan, phy_idx);
2318 rtw8922a_set_tx_shape(rtwdev, chan, phy_idx);
2319 rtw89_phy_set_txpwr_limit(rtwdev, chan, phy_idx);
2320 rtw89_phy_set_txpwr_limit_ru(rtwdev, chan, phy_idx);
2321 rtw8922a_set_txpwr_diff(rtwdev, chan, phy_idx);
2322 rtw8922a_set_txpwr_ref(rtwdev, phy_idx);
2323 rtw8922a_set_txpwr_sar_diff(rtwdev, chan, phy_idx);
2324 }
2325
rtw8922a_set_txpwr_ctrl(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx)2326 static void rtw8922a_set_txpwr_ctrl(struct rtw89_dev *rtwdev,
2327 enum rtw89_phy_idx phy_idx)
2328 {
2329 rtw8922a_set_txpwr_ref(rtwdev, phy_idx);
2330 }
2331
rtw8922a_ctrl_trx_path(struct rtw89_dev * rtwdev,enum rtw89_rf_path tx_path,u8 tx_nss,enum rtw89_rf_path rx_path,u8 rx_nss)2332 static void rtw8922a_ctrl_trx_path(struct rtw89_dev *rtwdev,
2333 enum rtw89_rf_path tx_path, u8 tx_nss,
2334 enum rtw89_rf_path rx_path, u8 rx_nss)
2335 {
2336 enum rtw89_phy_idx phy_idx;
2337
2338 for (phy_idx = RTW89_PHY_0; phy_idx <= RTW89_PHY_1; phy_idx++) {
2339 rtw8922a_ctrl_tx_path_tmac(rtwdev, tx_path, phy_idx);
2340 rtw8922a_ctrl_rx_path_tmac(rtwdev, rx_path, phy_idx);
2341 rtw8922a_cfg_rx_nss_limit(rtwdev, rx_nss, phy_idx);
2342 }
2343 }
2344
rtw8922a_ctrl_nbtg_bt_tx(struct rtw89_dev * rtwdev,bool en,enum rtw89_phy_idx phy_idx)2345 static void rtw8922a_ctrl_nbtg_bt_tx(struct rtw89_dev *rtwdev, bool en,
2346 enum rtw89_phy_idx phy_idx)
2347 {
2348 if (en) {
2349 rtw89_phy_write32_idx(rtwdev, R_FORCE_FIR_A, B_FORCE_FIR_A, 0x3, phy_idx);
2350 rtw89_phy_write32_idx(rtwdev, R_RXBY_WBADC_A, B_RXBY_WBADC_A,
2351 0xf, phy_idx);
2352 rtw89_phy_write32_idx(rtwdev, R_BT_RXBY_WBADC_A, B_BT_RXBY_WBADC_A,
2353 0x0, phy_idx);
2354 rtw89_phy_write32_idx(rtwdev, R_BT_SHARE_A, B_BT_TRK_OFF_A, 0x0, phy_idx);
2355 rtw89_phy_write32_idx(rtwdev, R_OP1DB_A, B_OP1DB_A, 0x80, phy_idx);
2356 rtw89_phy_write32_idx(rtwdev, R_OP1DB1_A, B_TIA10_A, 0x8080, phy_idx);
2357 rtw89_phy_write32_idx(rtwdev, R_BACKOFF_A, B_LNA_IBADC_A, 0x34, phy_idx);
2358 rtw89_phy_write32_idx(rtwdev, R_BKOFF_A, B_BKOFF_IBADC_A, 0x34, phy_idx);
2359 rtw89_phy_write32_idx(rtwdev, R_FORCE_FIR_B, B_FORCE_FIR_B, 0x3, phy_idx);
2360 rtw89_phy_write32_idx(rtwdev, R_RXBY_WBADC_B, B_RXBY_WBADC_B,
2361 0xf, phy_idx);
2362 rtw89_phy_write32_idx(rtwdev, R_BT_RXBY_WBADC_B, B_BT_RXBY_WBADC_B,
2363 0x0, phy_idx);
2364 rtw89_phy_write32_idx(rtwdev, R_BT_SHARE_B, B_BT_TRK_OFF_B, 0x0, phy_idx);
2365 rtw89_phy_write32_idx(rtwdev, R_LNA_OP, B_LNA6, 0x80, phy_idx);
2366 rtw89_phy_write32_idx(rtwdev, R_LNA_TIA, B_TIA10_B, 0x8080, phy_idx);
2367 rtw89_phy_write32_idx(rtwdev, R_BACKOFF_B, B_LNA_IBADC_B, 0x34, phy_idx);
2368 rtw89_phy_write32_idx(rtwdev, R_BKOFF_B, B_BKOFF_IBADC_B, 0x34, phy_idx);
2369 } else {
2370 rtw89_phy_write32_idx(rtwdev, R_FORCE_FIR_A, B_FORCE_FIR_A, 0x0, phy_idx);
2371 rtw89_phy_write32_idx(rtwdev, R_RXBY_WBADC_A, B_RXBY_WBADC_A,
2372 0x0, phy_idx);
2373 rtw89_phy_write32_idx(rtwdev, R_BT_RXBY_WBADC_A, B_BT_RXBY_WBADC_A,
2374 0x1, phy_idx);
2375 rtw89_phy_write32_idx(rtwdev, R_BT_SHARE_A, B_BT_TRK_OFF_A, 0x1, phy_idx);
2376 rtw89_phy_write32_idx(rtwdev, R_OP1DB_A, B_OP1DB_A, 0x1a, phy_idx);
2377 rtw89_phy_write32_idx(rtwdev, R_OP1DB1_A, B_TIA10_A, 0x2a2a, phy_idx);
2378 rtw89_phy_write32_idx(rtwdev, R_BACKOFF_A, B_LNA_IBADC_A, 0x7a6, phy_idx);
2379 rtw89_phy_write32_idx(rtwdev, R_BKOFF_A, B_BKOFF_IBADC_A, 0x26, phy_idx);
2380 rtw89_phy_write32_idx(rtwdev, R_FORCE_FIR_B, B_FORCE_FIR_B, 0x0, phy_idx);
2381 rtw89_phy_write32_idx(rtwdev, R_RXBY_WBADC_B, B_RXBY_WBADC_B,
2382 0x0, phy_idx);
2383 rtw89_phy_write32_idx(rtwdev, R_BT_RXBY_WBADC_B, B_BT_RXBY_WBADC_B,
2384 0x1, phy_idx);
2385 rtw89_phy_write32_idx(rtwdev, R_BT_SHARE_B, B_BT_TRK_OFF_B, 0x1, phy_idx);
2386 rtw89_phy_write32_idx(rtwdev, R_LNA_OP, B_LNA6, 0x20, phy_idx);
2387 rtw89_phy_write32_idx(rtwdev, R_LNA_TIA, B_TIA10_B, 0x2a30, phy_idx);
2388 rtw89_phy_write32_idx(rtwdev, R_BACKOFF_B, B_LNA_IBADC_B, 0x7a6, phy_idx);
2389 rtw89_phy_write32_idx(rtwdev, R_BKOFF_B, B_BKOFF_IBADC_B, 0x26, phy_idx);
2390 }
2391 }
2392
rtw8922a_bb_cfg_txrx_path(struct rtw89_dev * rtwdev)2393 static void rtw8922a_bb_cfg_txrx_path(struct rtw89_dev *rtwdev)
2394 {
2395 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_CHANCTX_0);
2396 enum rtw89_band band = chan->band_type;
2397 struct rtw89_hal *hal = &rtwdev->hal;
2398 u8 ntx_path = RF_PATH_AB;
2399 u8 nrx_path = RF_PATH_AB;
2400 u32 tx_en0, tx_en1;
2401 u8 rx_nss = 2;
2402
2403 if (hal->antenna_tx == RF_A)
2404 ntx_path = RF_PATH_A;
2405 else if (hal->antenna_tx == RF_B)
2406 ntx_path = RF_PATH_B;
2407
2408 if (hal->antenna_rx == RF_A)
2409 nrx_path = RF_PATH_A;
2410 else if (hal->antenna_rx == RF_B)
2411 nrx_path = RF_PATH_B;
2412
2413 if (nrx_path != RF_PATH_AB)
2414 rx_nss = 1;
2415
2416 rtw8922a_hal_reset(rtwdev, RTW89_PHY_0, RTW89_MAC_0, band, &tx_en0, true);
2417 if (rtwdev->dbcc_en)
2418 rtw8922a_hal_reset(rtwdev, RTW89_PHY_1, RTW89_MAC_1, band,
2419 &tx_en1, true);
2420
2421 rtw8922a_ctrl_trx_path(rtwdev, ntx_path, 2, nrx_path, rx_nss);
2422
2423 rtw8922a_hal_reset(rtwdev, RTW89_PHY_0, RTW89_MAC_0, band, &tx_en0, false);
2424 if (rtwdev->dbcc_en)
2425 rtw8922a_hal_reset(rtwdev, RTW89_PHY_1, RTW89_MAC_1, band,
2426 &tx_en1, false);
2427 }
2428
rtw8922a_get_thermal(struct rtw89_dev * rtwdev,enum rtw89_rf_path rf_path)2429 static u8 rtw8922a_get_thermal(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path)
2430 {
2431 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim;
2432 struct rtw89_hal *hal = &rtwdev->hal;
2433 int th;
2434
2435 /* read thermal only if debugging or thermal protection enabled */
2436 if (!rtw89_debug_is_enabled(rtwdev, RTW89_DBG_CFO | RTW89_DBG_RFK_TRACK) &&
2437 !hal->thermal_prot_th)
2438 return 80;
2439
2440 rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x1);
2441 rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x0);
2442 rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x1);
2443
2444 fsleep(200);
2445
2446 th = rtw89_read_rf(rtwdev, rf_path, RR_TM, RR_TM_VAL_V1);
2447 th += (s8)info->thermal_trim[rf_path];
2448
2449 return clamp_t(int, th, 0, U8_MAX);
2450 }
2451
rtw8922a_chan_to_rf18_val(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan)2452 static u32 rtw8922a_chan_to_rf18_val(struct rtw89_dev *rtwdev,
2453 const struct rtw89_chan *chan)
2454 {
2455 u32 val = u32_encode_bits(chan->channel, RR_CFGCH_CH);
2456
2457 switch (chan->band_type) {
2458 case RTW89_BAND_2G:
2459 default:
2460 break;
2461 case RTW89_BAND_5G:
2462 val |= u32_encode_bits(CFGCH_BAND1_5G, RR_CFGCH_BAND1) |
2463 u32_encode_bits(CFGCH_BAND0_5G, RR_CFGCH_BAND0);
2464 break;
2465 case RTW89_BAND_6G:
2466 val |= u32_encode_bits(CFGCH_BAND1_6G, RR_CFGCH_BAND1) |
2467 u32_encode_bits(CFGCH_BAND0_6G, RR_CFGCH_BAND0);
2468 break;
2469 }
2470
2471 switch (chan->band_width) {
2472 case RTW89_CHANNEL_WIDTH_5:
2473 case RTW89_CHANNEL_WIDTH_10:
2474 case RTW89_CHANNEL_WIDTH_20:
2475 default:
2476 break;
2477 case RTW89_CHANNEL_WIDTH_40:
2478 val |= u32_encode_bits(CFGCH_BW_V2_40M, RR_CFGCH_BW_V2);
2479 break;
2480 case RTW89_CHANNEL_WIDTH_80:
2481 val |= u32_encode_bits(CFGCH_BW_V2_80M, RR_CFGCH_BW_V2);
2482 break;
2483 case RTW89_CHANNEL_WIDTH_160:
2484 val |= u32_encode_bits(CFGCH_BW_V2_160M, RR_CFGCH_BW_V2);
2485 break;
2486 case RTW89_CHANNEL_WIDTH_320:
2487 val |= u32_encode_bits(CFGCH_BW_V2_320M, RR_CFGCH_BW_V2);
2488 break;
2489 }
2490
2491 return val;
2492 }
2493
rtw8922a_btc_set_rfe(struct rtw89_dev * rtwdev)2494 static void rtw8922a_btc_set_rfe(struct rtw89_dev *rtwdev)
2495 {
2496 union rtw89_btc_module_info *md = &rtwdev->btc.mdinfo;
2497 struct rtw89_btc_module_v7 *module = &md->md_v7;
2498
2499 module->rfe_type = rtwdev->efuse.rfe_type;
2500 module->kt_ver = rtwdev->hal.cv;
2501 module->bt_solo = 0;
2502 module->switch_type = BTC_SWITCH_INTERNAL;
2503 module->wa_type = 0;
2504
2505 module->ant.type = BTC_ANT_SHARED;
2506 module->ant.num = 2;
2507 module->ant.isolation = 10;
2508 module->ant.diversity = 0;
2509 module->ant.single_pos = RF_PATH_A;
2510 module->ant.btg_pos = RF_PATH_B;
2511
2512 if (module->kt_ver <= 1)
2513 module->wa_type |= BTC_WA_HFP_ZB;
2514
2515 rtwdev->btc.cx.other.type = BTC_3CX_NONE;
2516
2517 if (module->rfe_type == 0) {
2518 rtwdev->btc.dm.error.map.rfe_type0 = true;
2519 return;
2520 }
2521
2522 module->ant.num = (module->rfe_type % 2) ? 2 : 3;
2523
2524 if (module->kt_ver == 0)
2525 module->ant.num = 2;
2526
2527 if (module->ant.num == 3) {
2528 module->ant.type = BTC_ANT_DEDICATED;
2529 module->bt_pos = BTC_BT_ALONE;
2530 } else {
2531 module->ant.type = BTC_ANT_SHARED;
2532 module->bt_pos = BTC_BT_BTG;
2533 }
2534 rtwdev->btc.btg_pos = module->ant.btg_pos;
2535 rtwdev->btc.ant_type = module->ant.type;
2536 }
2537
2538 static
rtw8922a_set_trx_mask(struct rtw89_dev * rtwdev,u8 path,u8 group,u32 val)2539 void rtw8922a_set_trx_mask(struct rtw89_dev *rtwdev, u8 path, u8 group, u32 val)
2540 {
2541 rtw89_write_rf(rtwdev, path, RR_LUTWA, RFREG_MASK, group);
2542 rtw89_write_rf(rtwdev, path, RR_LUTWD0, RFREG_MASK, val);
2543 }
2544
rtw8922a_btc_init_cfg(struct rtw89_dev * rtwdev)2545 static void rtw8922a_btc_init_cfg(struct rtw89_dev *rtwdev)
2546 {
2547 struct rtw89_btc *btc = &rtwdev->btc;
2548 struct rtw89_btc_ant_info_v7 *ant = &btc->mdinfo.md_v7.ant;
2549 u32 wl_pri, path_min, path_max;
2550 u8 path;
2551
2552 /* for 1-Ant && 1-ss case: only 1-path */
2553 if (ant->num == 1) {
2554 path_min = ant->single_pos;
2555 path_max = path_min;
2556 } else {
2557 path_min = RF_PATH_A;
2558 path_max = RF_PATH_B;
2559 }
2560
2561 path = path_min;
2562
2563 for (path = path_min; path <= path_max; path++) {
2564 /* set DEBUG_LUT_RFMODE_MASK = 1 to start trx-mask-setup */
2565 rtw89_write_rf(rtwdev, path, RR_LUTWE, RFREG_MASK, BIT(17));
2566
2567 /* if GNT_WL=0 && BT=SS_group --> WL Tx/Rx = THRU */
2568 rtw8922a_set_trx_mask(rtwdev, path, BTC_BT_SS_GROUP, 0x5ff);
2569
2570 /* if GNT_WL=0 && BT=Rx_group --> WL-Rx = THRU + WL-Tx = MASK */
2571 rtw8922a_set_trx_mask(rtwdev, path, BTC_BT_RX_GROUP, 0x5df);
2572
2573 /* if GNT_WL = 0 && BT = Tx_group -->
2574 * Shared-Ant && BTG-path:WL mask(0x55f), others:WL THRU(0x5ff)
2575 */
2576 if (btc->ant_type == BTC_ANT_SHARED && btc->btg_pos == path)
2577 rtw8922a_set_trx_mask(rtwdev, path, BTC_BT_TX_GROUP, 0x55f);
2578 else
2579 rtw8922a_set_trx_mask(rtwdev, path, BTC_BT_TX_GROUP, 0x5ff);
2580
2581 rtw89_write_rf(rtwdev, path, RR_LUTWE, RFREG_MASK, 0);
2582 }
2583
2584 /* set WL PTA Hi-Pri: Ack-Tx, beacon-tx, Trig-frame-Tx, Null-Tx*/
2585 wl_pri = B_BTC_RSP_ACK_HI | B_BTC_TX_BCN_HI | B_BTC_TX_TRI_HI |
2586 B_BTC_TX_NULL_HI;
2587 rtw89_write32(rtwdev, R_BTC_COEX_WL_REQ_BE, wl_pri);
2588
2589 /* set PTA break table */
2590 rtw89_write32(rtwdev, R_BE_BT_BREAK_TABLE, BTC_BREAK_PARAM);
2591
2592 /* ZB coex table init for HFP PTA req-cmd bit-4 define issue COEX-900*/
2593 rtw89_write32(rtwdev, R_BTC_ZB_COEX_TBL_0, 0xda5a5a5a);
2594
2595 rtw89_write32(rtwdev, R_BTC_ZB_COEX_TBL_1, 0xda5a5a5a);
2596
2597 rtw89_write32(rtwdev, R_BTC_ZB_BREAK_TBL, 0xf0ffffff);
2598 btc->cx.wl.status.map.init_ok = true;
2599 }
2600
2601 static void
rtw8922a_btc_set_wl_txpwr_ctrl(struct rtw89_dev * rtwdev,u32 txpwr_val)2602 rtw8922a_btc_set_wl_txpwr_ctrl(struct rtw89_dev *rtwdev, u32 txpwr_val)
2603 {
2604 u16 ctrl_all_time = u32_get_bits(txpwr_val, GENMASK(15, 0));
2605 u16 ctrl_gnt_bt = u32_get_bits(txpwr_val, GENMASK(31, 16));
2606
2607 switch (ctrl_all_time) {
2608 case 0xffff:
2609 rtw89_mac_txpwr_write32_mask(rtwdev, RTW89_PHY_0, R_BE_PWR_RATE_CTRL,
2610 B_BE_FORCE_PWR_BY_RATE_EN, 0x0);
2611 rtw89_mac_txpwr_write32_mask(rtwdev, RTW89_PHY_0, R_BE_PWR_RATE_CTRL,
2612 B_BE_FORCE_PWR_BY_RATE_VAL, 0x0);
2613 break;
2614 default:
2615 rtw89_mac_txpwr_write32_mask(rtwdev, RTW89_PHY_0, R_BE_PWR_RATE_CTRL,
2616 B_BE_FORCE_PWR_BY_RATE_VAL, ctrl_all_time);
2617 rtw89_mac_txpwr_write32_mask(rtwdev, RTW89_PHY_0, R_BE_PWR_RATE_CTRL,
2618 B_BE_FORCE_PWR_BY_RATE_EN, 0x1);
2619 break;
2620 }
2621
2622 switch (ctrl_gnt_bt) {
2623 case 0xffff:
2624 rtw89_mac_txpwr_write32_mask(rtwdev, RTW89_PHY_0, R_BE_PWR_REG_CTRL,
2625 B_BE_PWR_BT_EN, 0x0);
2626 rtw89_mac_txpwr_write32_mask(rtwdev, RTW89_PHY_0, R_BE_PWR_COEX_CTRL,
2627 B_BE_PWR_BT_VAL, 0x0);
2628 break;
2629 default:
2630 rtw89_mac_txpwr_write32_mask(rtwdev, RTW89_PHY_0, R_BE_PWR_COEX_CTRL,
2631 B_BE_PWR_BT_VAL, ctrl_gnt_bt);
2632 rtw89_mac_txpwr_write32_mask(rtwdev, RTW89_PHY_0, R_BE_PWR_REG_CTRL,
2633 B_BE_PWR_BT_EN, 0x1);
2634 break;
2635 }
2636 }
2637
2638 static
rtw8922a_btc_get_bt_rssi(struct rtw89_dev * rtwdev,s8 val)2639 s8 rtw8922a_btc_get_bt_rssi(struct rtw89_dev *rtwdev, s8 val)
2640 {
2641 return clamp_t(s8, val, -100, 0) + 100;
2642 }
2643
2644 static const struct rtw89_btc_rf_trx_para rtw89_btc_8922a_rf_ul[] = {
2645 {255, 0, 0, 7}, /* 0 -> original */
2646 {255, 2, 0, 7}, /* 1 -> for BT-connected ACI issue && BTG co-rx */
2647 {255, 0, 0, 7}, /* 2 ->reserved for shared-antenna */
2648 {255, 0, 0, 7}, /* 3- >reserved for shared-antenna */
2649 {255, 0, 0, 7}, /* 4 ->reserved for shared-antenna */
2650 {255, 1, 0, 7}, /* the below id is for non-shared-antenna free-run */
2651 {6, 1, 0, 7},
2652 {13, 1, 0, 7},
2653 {13, 1, 0, 7}
2654 };
2655
2656 static const struct rtw89_btc_rf_trx_para rtw89_btc_8922a_rf_dl[] = {
2657 {255, 0, 0, 7}, /* 0 -> original */
2658 {255, 2, 0, 7}, /* 1 -> reserved for shared-antenna */
2659 {255, 0, 0, 7}, /* 2 ->reserved for shared-antenna */
2660 {255, 0, 0, 7}, /* 3- >reserved for shared-antenna */
2661 {255, 0, 0, 7}, /* 4 ->reserved for shared-antenna */
2662 {255, 1, 0, 7}, /* the below id is for non-shared-antenna free-run */
2663 {255, 1, 0, 7},
2664 {255, 1, 0, 7},
2665 {255, 1, 0, 7}
2666 };
2667
2668 static const u8 rtw89_btc_8922a_wl_rssi_thres[BTC_WL_RSSI_THMAX] = {60, 50, 40, 30};
2669 static const u8 rtw89_btc_8922a_bt_rssi_thres[BTC_BT_RSSI_THMAX] = {50, 40, 30, 20};
2670
2671 static const struct rtw89_btc_fbtc_mreg rtw89_btc_8922a_mon_reg[] = {
2672 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xe300),
2673 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xe320),
2674 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xe324),
2675 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xe328),
2676 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xe32c),
2677 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xe330),
2678 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xe334),
2679 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xe338),
2680 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xe344),
2681 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xe348),
2682 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xe34c),
2683 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xe350),
2684 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0x11a2c),
2685 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0x11a50),
2686 RTW89_DEF_FBTC_MREG(REG_BB, 4, 0x980),
2687 RTW89_DEF_FBTC_MREG(REG_BB, 4, 0x660),
2688 RTW89_DEF_FBTC_MREG(REG_BB, 4, 0x1660),
2689 RTW89_DEF_FBTC_MREG(REG_BB, 4, 0x418c),
2690 RTW89_DEF_FBTC_MREG(REG_BB, 4, 0x518c),
2691 };
2692
2693 static
rtw8922a_btc_update_bt_cnt(struct rtw89_dev * rtwdev)2694 void rtw8922a_btc_update_bt_cnt(struct rtw89_dev *rtwdev)
2695 {
2696 /* Feature move to firmware */
2697 }
2698
2699 static
rtw8922a_btc_wl_s1_standby(struct rtw89_dev * rtwdev,bool state)2700 void rtw8922a_btc_wl_s1_standby(struct rtw89_dev *rtwdev, bool state)
2701 {
2702 if (!state) {
2703 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x80000);
2704 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x1);
2705 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD1, RFREG_MASK, 0x0c110);
2706 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x01018);
2707 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x00000);
2708
2709 rtw89_write_rf(rtwdev, RF_PATH_A, RR_LUTWE, RFREG_MASK, 0x80000);
2710 rtw89_write_rf(rtwdev, RF_PATH_A, RR_LUTWA, RFREG_MASK, 0x1);
2711 rtw89_write_rf(rtwdev, RF_PATH_A, RR_LUTWD1, RFREG_MASK, 0x0c110);
2712 rtw89_write_rf(rtwdev, RF_PATH_A, RR_LUTWD0, RFREG_MASK, 0x01018);
2713 rtw89_write_rf(rtwdev, RF_PATH_A, RR_LUTWE, RFREG_MASK, 0x00000);
2714 } else {
2715 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x80000);
2716 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x1);
2717 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD1, RFREG_MASK, 0x0c110);
2718 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x09018);
2719 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x00000);
2720
2721 rtw89_write_rf(rtwdev, RF_PATH_A, RR_LUTWE, RFREG_MASK, 0x80000);
2722 rtw89_write_rf(rtwdev, RF_PATH_A, RR_LUTWA, RFREG_MASK, 0x1);
2723 rtw89_write_rf(rtwdev, RF_PATH_A, RR_LUTWD1, RFREG_MASK, 0x0c110);
2724 rtw89_write_rf(rtwdev, RF_PATH_A, RR_LUTWD0, RFREG_MASK, 0x09018);
2725 rtw89_write_rf(rtwdev, RF_PATH_A, RR_LUTWE, RFREG_MASK, 0x00000);
2726 }
2727 }
2728
rtw8922a_btc_set_wl_rx_gain(struct rtw89_dev * rtwdev,u32 level)2729 static void rtw8922a_btc_set_wl_rx_gain(struct rtw89_dev *rtwdev, u32 level)
2730 {
2731 }
2732
rtw8922a_fill_freq_with_ppdu(struct rtw89_dev * rtwdev,struct rtw89_rx_phy_ppdu * phy_ppdu,struct ieee80211_rx_status * status)2733 static void rtw8922a_fill_freq_with_ppdu(struct rtw89_dev *rtwdev,
2734 struct rtw89_rx_phy_ppdu *phy_ppdu,
2735 struct ieee80211_rx_status *status)
2736 {
2737 u8 chan_idx = phy_ppdu->chan_idx;
2738 enum nl80211_band band;
2739 u8 ch;
2740
2741 if (chan_idx == 0)
2742 return;
2743
2744 rtw89_decode_chan_idx(rtwdev, chan_idx, &ch, &band);
2745 status->freq = ieee80211_channel_to_frequency(ch, band);
2746 status->band = band;
2747 }
2748
rtw8922a_query_ppdu(struct rtw89_dev * rtwdev,struct rtw89_rx_phy_ppdu * phy_ppdu,struct ieee80211_rx_status * status)2749 static void rtw8922a_query_ppdu(struct rtw89_dev *rtwdev,
2750 struct rtw89_rx_phy_ppdu *phy_ppdu,
2751 struct ieee80211_rx_status *status)
2752 {
2753 u8 path;
2754 u8 *rx_power = phy_ppdu->rssi;
2755
2756 if (!status->signal)
2757 status->signal = RTW89_RSSI_RAW_TO_DBM(max(rx_power[RF_PATH_A],
2758 rx_power[RF_PATH_B]));
2759
2760 for (path = 0; path < rtwdev->chip->rf_path_num; path++) {
2761 status->chains |= BIT(path);
2762 status->chain_signal[path] = RTW89_RSSI_RAW_TO_DBM(rx_power[path]);
2763 }
2764 if (phy_ppdu->valid)
2765 rtw8922a_fill_freq_with_ppdu(rtwdev, phy_ppdu, status);
2766 }
2767
rtw8922a_convert_rpl_to_rssi(struct rtw89_dev * rtwdev,struct rtw89_rx_phy_ppdu * phy_ppdu)2768 static void rtw8922a_convert_rpl_to_rssi(struct rtw89_dev *rtwdev,
2769 struct rtw89_rx_phy_ppdu *phy_ppdu)
2770 {
2771 /* Mapping to BW: 5, 10, 20, 40, 80, 160, 80_80 */
2772 static const u8 bw_compensate[] = {0, 0, 0, 6, 12, 18, 0};
2773 u8 *rssi = phy_ppdu->rssi;
2774 u8 compensate = 0;
2775 u16 rpl_tmp;
2776 u8 i;
2777
2778 if (phy_ppdu->bw_idx < ARRAY_SIZE(bw_compensate))
2779 compensate = bw_compensate[phy_ppdu->bw_idx];
2780
2781 for (i = 0; i < RF_PATH_NUM_8922A; i++) {
2782 if (!(phy_ppdu->rx_path_en & BIT(i))) {
2783 rssi[i] = 0;
2784 phy_ppdu->rpl_path[i] = 0;
2785 phy_ppdu->rpl_fd[i] = 0;
2786 }
2787 if (phy_ppdu->rate >= RTW89_HW_RATE_OFDM6) {
2788 rpl_tmp = phy_ppdu->rpl_fd[i];
2789 if (rpl_tmp)
2790 rpl_tmp += compensate;
2791
2792 phy_ppdu->rpl_path[i] = rpl_tmp;
2793 }
2794 rssi[i] = phy_ppdu->rpl_path[i];
2795 }
2796
2797 phy_ppdu->rssi_avg = phy_ppdu->rpl_avg;
2798 }
2799
rtw8922a_phy_rpt_to_rssi(struct rtw89_dev * rtwdev,struct rtw89_rx_desc_info * desc_info,struct ieee80211_rx_status * rx_status)2800 static void rtw8922a_phy_rpt_to_rssi(struct rtw89_dev *rtwdev,
2801 struct rtw89_rx_desc_info *desc_info,
2802 struct ieee80211_rx_status *rx_status)
2803 {
2804 if (desc_info->rssi <= 0x1 || (desc_info->rssi >> 2) > MAX_RSSI)
2805 return;
2806
2807 rx_status->signal = (desc_info->rssi >> 2) - MAX_RSSI;
2808 }
2809
rtw8922a_mac_enable_bb_rf(struct rtw89_dev * rtwdev)2810 static int rtw8922a_mac_enable_bb_rf(struct rtw89_dev *rtwdev)
2811 {
2812 rtw89_write8_set(rtwdev, R_BE_FEN_RST_ENABLE,
2813 B_BE_FEN_BBPLAT_RSTB | B_BE_FEN_BB_IP_RSTN);
2814 rtw89_write32(rtwdev, R_BE_DMAC_SYS_CR32B, 0x7FF97FF9);
2815
2816 return 0;
2817 }
2818
rtw8922a_mac_disable_bb_rf(struct rtw89_dev * rtwdev)2819 static int rtw8922a_mac_disable_bb_rf(struct rtw89_dev *rtwdev)
2820 {
2821 rtw89_write8_clr(rtwdev, R_BE_FEN_RST_ENABLE,
2822 B_BE_FEN_BBPLAT_RSTB | B_BE_FEN_BB_IP_RSTN);
2823
2824 return 0;
2825 }
2826
2827 static const struct rtw89_chanctx_listener rtw8922a_chanctx_listener = {
2828 .callbacks[RTW89_CHANCTX_CALLBACK_TAS] = rtw89_tas_chanctx_cb,
2829 };
2830
2831 #ifdef CONFIG_PM
2832 static const struct wiphy_wowlan_support rtw_wowlan_stub_8922a = {
2833 .flags = WIPHY_WOWLAN_MAGIC_PKT | WIPHY_WOWLAN_DISCONNECT |
2834 WIPHY_WOWLAN_NET_DETECT,
2835 .n_patterns = RTW89_MAX_PATTERN_NUM,
2836 .pattern_max_len = RTW89_MAX_PATTERN_SIZE,
2837 .pattern_min_len = 1,
2838 .max_nd_match_sets = RTW89_SCANOFLD_MAX_SSID,
2839 };
2840 #endif
2841
2842 static const struct rtw89_chip_ops rtw8922a_chip_ops = {
2843 .enable_bb_rf = rtw8922a_mac_enable_bb_rf,
2844 .disable_bb_rf = rtw8922a_mac_disable_bb_rf,
2845 .bb_preinit = rtw8922a_bb_preinit,
2846 .bb_postinit = rtw8922a_bb_postinit,
2847 .bb_reset = rtw8922a_bb_reset,
2848 .bb_sethw = rtw8922a_bb_sethw,
2849 .read_rf = rtw89_phy_read_rf_v2,
2850 .write_rf = rtw89_phy_write_rf_v2,
2851 .set_channel = rtw8922a_set_channel,
2852 .set_channel_help = rtw8922a_set_channel_help,
2853 .read_efuse = rtw8922a_read_efuse,
2854 .read_phycap = rtw8922a_read_phycap,
2855 .fem_setup = NULL,
2856 .rfe_gpio = NULL,
2857 .rfk_hw_init = rtw8922a_rfk_hw_init,
2858 .rfk_init = rtw8922a_rfk_init,
2859 .rfk_init_late = rtw8922a_rfk_init_late,
2860 .rfk_channel = rtw8922a_rfk_channel,
2861 .rfk_band_changed = rtw8922a_rfk_band_changed,
2862 .rfk_scan = rtw8922a_rfk_scan,
2863 .rfk_track = rtw8922a_rfk_track,
2864 .power_trim = rtw8922a_power_trim,
2865 .set_txpwr = rtw8922a_set_txpwr,
2866 .set_txpwr_ctrl = rtw8922a_set_txpwr_ctrl,
2867 .init_txpwr_unit = NULL,
2868 .get_thermal = rtw8922a_get_thermal,
2869 .chan_to_rf18_val = rtw8922a_chan_to_rf18_val,
2870 .ctrl_btg_bt_rx = rtw8922a_ctrl_btg_bt_rx,
2871 .query_ppdu = rtw8922a_query_ppdu,
2872 .convert_rpl_to_rssi = rtw8922a_convert_rpl_to_rssi,
2873 .phy_rpt_to_rssi = rtw8922a_phy_rpt_to_rssi,
2874 .ctrl_nbtg_bt_tx = rtw8922a_ctrl_nbtg_bt_tx,
2875 .cfg_txrx_path = rtw8922a_bb_cfg_txrx_path,
2876 .set_txpwr_ul_tb_offset = NULL,
2877 .digital_pwr_comp = rtw8922a_digital_pwr_comp,
2878 .calc_rx_gain_normal = NULL,
2879 .pwr_on_func = rtw8922a_pwr_on_func,
2880 .pwr_off_func = rtw8922a_pwr_off_func,
2881 .query_rxdesc = rtw89_core_query_rxdesc_v2,
2882 .fill_txdesc = rtw89_core_fill_txdesc_v2,
2883 .fill_txdesc_fwcmd = rtw89_core_fill_txdesc_fwcmd_v2,
2884 .get_ch_dma = {rtw89_core_get_ch_dma,
2885 rtw89_core_get_ch_dma_v2,
2886 NULL,},
2887 .cfg_ctrl_path = rtw89_mac_cfg_ctrl_path_v2,
2888 .mac_cfg_gnt = rtw89_mac_cfg_gnt_v2,
2889 .stop_sch_tx = rtw89_mac_stop_sch_tx_v2,
2890 .resume_sch_tx = rtw89_mac_resume_sch_tx_v2,
2891 .h2c_dctl_sec_cam = rtw89_fw_h2c_dctl_sec_cam_v2,
2892 .h2c_default_cmac_tbl = rtw89_fw_h2c_default_cmac_tbl_g7,
2893 .h2c_assoc_cmac_tbl = rtw89_fw_h2c_assoc_cmac_tbl_g7,
2894 .h2c_ampdu_cmac_tbl = rtw89_fw_h2c_ampdu_cmac_tbl_g7,
2895 .h2c_txtime_cmac_tbl = rtw89_fw_h2c_txtime_cmac_tbl_g7,
2896 .h2c_punctured_cmac_tbl = rtw89_fw_h2c_punctured_cmac_tbl_g7,
2897 .h2c_default_dmac_tbl = rtw89_fw_h2c_default_dmac_tbl_v2,
2898 .h2c_update_beacon = rtw89_fw_h2c_update_beacon_be,
2899 .h2c_ba_cam = rtw89_fw_h2c_ba_cam_v1,
2900 .h2c_wow_cam_update = rtw89_fw_h2c_wow_cam_update,
2901
2902 .btc_set_rfe = rtw8922a_btc_set_rfe,
2903 .btc_init_cfg = rtw8922a_btc_init_cfg,
2904 .btc_set_wl_pri = NULL,
2905 .btc_set_wl_txpwr_ctrl = rtw8922a_btc_set_wl_txpwr_ctrl,
2906 .btc_get_bt_rssi = rtw8922a_btc_get_bt_rssi,
2907 .btc_update_bt_cnt = rtw8922a_btc_update_bt_cnt,
2908 .btc_wl_s1_standby = rtw8922a_btc_wl_s1_standby,
2909 .btc_set_wl_rx_gain = rtw8922a_btc_set_wl_rx_gain,
2910 .btc_set_policy = rtw89_btc_set_policy_v1,
2911 };
2912
2913 const struct rtw89_chip_info rtw8922a_chip_info = {
2914 .chip_id = RTL8922A,
2915 .chip_gen = RTW89_CHIP_BE,
2916 .ops = &rtw8922a_chip_ops,
2917 .mac_def = &rtw89_mac_gen_be,
2918 .phy_def = &rtw89_phy_gen_be,
2919 .fw_basename = RTW8922A_FW_BASENAME,
2920 .fw_format_max = RTW8922A_FW_FORMAT_MAX,
2921 .try_ce_fw = false,
2922 .bbmcu_nr = 1,
2923 .needed_fw_elms = RTW89_BE_GEN_DEF_NEEDED_FW_ELEMENTS,
2924 .fw_blacklist = &rtw89_fw_blacklist_default,
2925 .fifo_size = 589824,
2926 .small_fifo_size = false,
2927 .dle_scc_rsvd_size = 0,
2928 .max_amsdu_limit = 8000,
2929 .max_vht_mpdu_cap = IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454,
2930 .max_eht_mpdu_cap = IEEE80211_EHT_MAC_CAP0_MAX_MPDU_LEN_7991,
2931 .max_tx_agg_num = 128,
2932 .max_rx_agg_num = 64,
2933 .dis_2g_40m_ul_ofdma = false,
2934 .rsvd_ple_ofst = 0x8f800,
2935 .hfc_param_ini = {rtw8922a_hfc_param_ini_pcie, NULL, NULL},
2936 .dle_mem = {rtw8922a_dle_mem_pcie, NULL, NULL, NULL},
2937 .wde_qempty_acq_grpnum = 4,
2938 .wde_qempty_mgq_grpsel = 4,
2939 .rf_base_addr = {0xe000, 0xf000},
2940 .thermal_th = {0xad, 0xb4},
2941 .pwr_on_seq = NULL,
2942 .pwr_off_seq = NULL,
2943 .bb_table = NULL,
2944 .bb_gain_table = NULL,
2945 .rf_table = {},
2946 .nctl_table = NULL,
2947 .nctl_post_table = NULL,
2948 .dflt_parms = NULL, /* load parm from fw */
2949 .rfe_parms_conf = NULL, /* load parm from fw */
2950 .chanctx_listener = &rtw8922a_chanctx_listener,
2951 .txpwr_factor_bb = 3,
2952 .txpwr_factor_rf = 2,
2953 .txpwr_factor_mac = 1,
2954 .dig_table = NULL,
2955 .dig_regs = &rtw8922a_dig_regs,
2956 .tssi_dbw_table = NULL,
2957 .support_macid_num = 32,
2958 .support_link_num = 2,
2959 .support_chanctx_num = 2,
2960 .support_rnr = true,
2961 .support_bands = BIT(NL80211_BAND_2GHZ) |
2962 BIT(NL80211_BAND_5GHZ) |
2963 BIT(NL80211_BAND_6GHZ),
2964 .support_bandwidths = BIT(NL80211_CHAN_WIDTH_20) |
2965 BIT(NL80211_CHAN_WIDTH_40) |
2966 BIT(NL80211_CHAN_WIDTH_80) |
2967 BIT(NL80211_CHAN_WIDTH_160),
2968 .support_unii4 = true,
2969 .support_ant_gain = true,
2970 .support_tas = true,
2971 .support_sar_by_ant = true,
2972 .support_noise = false,
2973 .ul_tb_waveform_ctrl = false,
2974 .ul_tb_pwr_diff = false,
2975 .rx_freq_frome_ie = false,
2976 .hw_sec_hdr = true,
2977 .hw_mgmt_tx_encrypt = true,
2978 .hw_tkip_crypto = true,
2979 .hw_mlo_bmc_crypto = false,
2980 .rf_path_num = 2,
2981 .tx_nss = 2,
2982 .rx_nss = 2,
2983 .acam_num = 128,
2984 .bcam_num = 20,
2985 .scam_num = 32,
2986 .bacam_num = 24,
2987 .bacam_dynamic_num = 8,
2988 .bacam_ver = RTW89_BACAM_V1,
2989 .addrcam_ver = 0,
2990 .ppdu_max_usr = 16,
2991 .sec_ctrl_efuse_size = 4,
2992 .physical_efuse_size = 0x1300,
2993 .logical_efuse_size = 0x70000,
2994 .limit_efuse_size = 0x40000,
2995 .dav_phy_efuse_size = 0,
2996 .dav_log_efuse_size = 0,
2997 .efuse_blocks = rtw8922a_efuse_blocks,
2998 .phycap_addr = 0x1700,
2999 .phycap_size = 0x38,
3000 .para_ver = 0xf,
3001 .wlcx_desired = 0x07110000,
3002 .scbd = 0x1,
3003 .mailbox = 0x1,
3004
3005 .afh_guard_ch = 6,
3006 .wl_rssi_thres = rtw89_btc_8922a_wl_rssi_thres,
3007 .bt_rssi_thres = rtw89_btc_8922a_bt_rssi_thres,
3008 .rssi_tol = 2,
3009 .mon_reg_num = ARRAY_SIZE(rtw89_btc_8922a_mon_reg),
3010 .mon_reg = rtw89_btc_8922a_mon_reg,
3011 .rf_para_ulink_num = ARRAY_SIZE(rtw89_btc_8922a_rf_ul),
3012 .rf_para_ulink = rtw89_btc_8922a_rf_ul,
3013 .rf_para_dlink_num = ARRAY_SIZE(rtw89_btc_8922a_rf_dl),
3014 .rf_para_dlink = rtw89_btc_8922a_rf_dl,
3015 .ps_mode_supported = BIT(RTW89_PS_MODE_RFOFF) |
3016 BIT(RTW89_PS_MODE_CLK_GATED) |
3017 BIT(RTW89_PS_MODE_PWR_GATED),
3018 .low_power_hci_modes = 0,
3019 .h2c_cctl_func_id = H2C_FUNC_MAC_CCTLINFO_UD_G7,
3020 .hci_func_en_addr = R_BE_HCI_FUNC_EN,
3021 .h2c_desc_size = sizeof(struct rtw89_rxdesc_short_v2),
3022 .txwd_body_size = sizeof(struct rtw89_txwd_body_v2),
3023 .txwd_info_size = sizeof(struct rtw89_txwd_info_v2),
3024 .h2c_ctrl_reg = R_BE_H2CREG_CTRL,
3025 .h2c_counter_reg = {R_BE_UDM1 + 1, B_BE_UDM1_HALMAC_H2C_DEQ_CNT_MASK >> 8},
3026 .h2c_regs = rtw8922a_h2c_regs,
3027 .c2h_ctrl_reg = R_BE_C2HREG_CTRL,
3028 .c2h_counter_reg = {R_BE_UDM1 + 1, B_BE_UDM1_HALMAC_C2H_ENQ_CNT_MASK >> 8},
3029 .c2h_regs = rtw8922a_c2h_regs,
3030 .page_regs = &rtw8922a_page_regs,
3031 .wow_reason_reg = rtw8922a_wow_wakeup_regs,
3032 .cfo_src_fd = true,
3033 .cfo_hw_comp = true,
3034 .dcfo_comp = NULL,
3035 .dcfo_comp_sft = 0,
3036 .nhm_report = NULL,
3037 .nhm_th = NULL,
3038 .imr_info = NULL,
3039 .imr_dmac_table = &rtw8922a_imr_dmac_table,
3040 .imr_cmac_table = &rtw8922a_imr_cmac_table,
3041 .rrsr_cfgs = &rtw8922a_rrsr_cfgs,
3042 .bss_clr_vld = {R_BSS_CLR_VLD_V2, B_BSS_CLR_VLD0_V2},
3043 .bss_clr_map_reg = R_BSS_CLR_MAP_V2,
3044 .rfkill_init = &rtw8922a_rfkill_regs,
3045 .rfkill_get = {R_BE_GPIO_EXT_CTRL, B_BE_GPIO_IN_9},
3046 .btc_sb = {{{R_BE_SCOREBOARD, R_BE_SCOREBOARD},}},
3047 .dma_ch_mask = 0,
3048 .edcca_regs = &rtw8922a_edcca_regs,
3049 #ifdef CONFIG_PM
3050 .wowlan_stub = &rtw_wowlan_stub_8922a,
3051 #endif
3052 .xtal_info = NULL,
3053 .default_quirks = 0,
3054 };
3055 EXPORT_SYMBOL(rtw8922a_chip_info);
3056
3057 const struct rtw89_chip_variant rtw8922ae_vs_variant = {
3058 .no_mcs_12_13 = true,
3059 .fw_min_ver_code = RTW89_FW_VER_CODE(0, 35, 54, 0),
3060 };
3061 EXPORT_SYMBOL(rtw8922ae_vs_variant);
3062
3063 MODULE_FIRMWARE(RTW8922A_MODULE_FIRMWARE);
3064 MODULE_AUTHOR("Realtek Corporation");
3065 MODULE_DESCRIPTION("Realtek 802.11be wireless 8922A driver");
3066 MODULE_LICENSE("Dual BSD/GPL");
3067