1 // SPDX-License-Identifier: ISC
2 /*
3 * Copyright (c) 2005-2011 Atheros Communications Inc.
4 * Copyright (c) 2011-2017 Qualcomm Atheros, Inc.
5 * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved.
6 * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
7 */
8
9 #if defined(__FreeBSD__)
10 #define LINUXKPI_PARAM_PREFIX ath10k_pci_
11 #endif
12
13 #include <linux/pci.h>
14 #include <linux/module.h>
15 #include <linux/interrupt.h>
16 #include <linux/spinlock.h>
17 #include <linux/bitops.h>
18 #if defined(__FreeBSD__)
19 #include <linux/delay.h>
20 #include <sys/rman.h>
21 #endif
22
23 #include "core.h"
24 #include "debug.h"
25 #include "coredump.h"
26
27 #include "targaddrs.h"
28 #include "bmi.h"
29
30 #include "hif.h"
31 #include "htc.h"
32
33 #include "ce.h"
34 #include "pci.h"
35
36 enum ath10k_pci_reset_mode {
37 ATH10K_PCI_RESET_AUTO = 0,
38 ATH10K_PCI_RESET_WARM_ONLY = 1,
39 };
40
41 static unsigned int ath10k_pci_irq_mode = ATH10K_PCI_IRQ_AUTO;
42 static unsigned int ath10k_pci_reset_mode = ATH10K_PCI_RESET_AUTO;
43
44 module_param_named(irq_mode, ath10k_pci_irq_mode, uint, 0644);
45 MODULE_PARM_DESC(irq_mode, "0: auto, 1: legacy, 2: msi (default: 0)");
46
47 module_param_named(reset_mode, ath10k_pci_reset_mode, uint, 0644);
48 MODULE_PARM_DESC(reset_mode, "0: auto, 1: warm only (default: 0)");
49
50 /* how long wait to wait for target to initialise, in ms */
51 #define ATH10K_PCI_TARGET_WAIT 3000
52 #define ATH10K_PCI_NUM_WARM_RESET_ATTEMPTS 3
53
54 /* Maximum number of bytes that can be handled atomically by
55 * diag read and write.
56 */
57 #define ATH10K_DIAG_TRANSFER_LIMIT 0x5000
58
59 #define QCA99X0_PCIE_BAR0_START_REG 0x81030
60 #define QCA99X0_CPU_MEM_ADDR_REG 0x4d00c
61 #define QCA99X0_CPU_MEM_DATA_REG 0x4d010
62
63 static const struct pci_device_id ath10k_pci_id_table[] = {
64 /* PCI-E QCA988X V2 (Ubiquiti branded) */
65 { PCI_VDEVICE(UBIQUITI, QCA988X_2_0_DEVICE_ID_UBNT) },
66
67 { PCI_VDEVICE(ATHEROS, QCA988X_2_0_DEVICE_ID) }, /* PCI-E QCA988X V2 */
68 { PCI_VDEVICE(ATHEROS, QCA6164_2_1_DEVICE_ID) }, /* PCI-E QCA6164 V2.1 */
69 { PCI_VDEVICE(ATHEROS, QCA6174_2_1_DEVICE_ID) }, /* PCI-E QCA6174 V2.1 */
70 { PCI_VDEVICE(ATHEROS, QCA99X0_2_0_DEVICE_ID) }, /* PCI-E QCA99X0 V2 */
71 { PCI_VDEVICE(ATHEROS, QCA9888_2_0_DEVICE_ID) }, /* PCI-E QCA9888 V2 */
72 { PCI_VDEVICE(ATHEROS, QCA9984_1_0_DEVICE_ID) }, /* PCI-E QCA9984 V1 */
73 { PCI_VDEVICE(ATHEROS, QCA9377_1_0_DEVICE_ID) }, /* PCI-E QCA9377 V1 */
74 { PCI_VDEVICE(ATHEROS, QCA9887_1_0_DEVICE_ID) }, /* PCI-E QCA9887 */
75 {}
76 };
77
78 static const struct ath10k_pci_supp_chip ath10k_pci_supp_chips[] = {
79 /* QCA988X pre 2.0 chips are not supported because they need some nasty
80 * hacks. ath10k doesn't have them and these devices crash horribly
81 * because of that.
82 */
83 { QCA988X_2_0_DEVICE_ID_UBNT, QCA988X_HW_2_0_CHIP_ID_REV },
84 { QCA988X_2_0_DEVICE_ID, QCA988X_HW_2_0_CHIP_ID_REV },
85
86 { QCA6164_2_1_DEVICE_ID, QCA6174_HW_2_1_CHIP_ID_REV },
87 { QCA6164_2_1_DEVICE_ID, QCA6174_HW_2_2_CHIP_ID_REV },
88 { QCA6164_2_1_DEVICE_ID, QCA6174_HW_3_0_CHIP_ID_REV },
89 { QCA6164_2_1_DEVICE_ID, QCA6174_HW_3_1_CHIP_ID_REV },
90 { QCA6164_2_1_DEVICE_ID, QCA6174_HW_3_2_CHIP_ID_REV },
91
92 { QCA6174_2_1_DEVICE_ID, QCA6174_HW_2_1_CHIP_ID_REV },
93 { QCA6174_2_1_DEVICE_ID, QCA6174_HW_2_2_CHIP_ID_REV },
94 { QCA6174_2_1_DEVICE_ID, QCA6174_HW_3_0_CHIP_ID_REV },
95 { QCA6174_2_1_DEVICE_ID, QCA6174_HW_3_1_CHIP_ID_REV },
96 { QCA6174_2_1_DEVICE_ID, QCA6174_HW_3_2_CHIP_ID_REV },
97
98 { QCA99X0_2_0_DEVICE_ID, QCA99X0_HW_2_0_CHIP_ID_REV },
99
100 { QCA9984_1_0_DEVICE_ID, QCA9984_HW_1_0_CHIP_ID_REV },
101
102 { QCA9888_2_0_DEVICE_ID, QCA9888_HW_2_0_CHIP_ID_REV },
103
104 { QCA9377_1_0_DEVICE_ID, QCA9377_HW_1_0_CHIP_ID_REV },
105 { QCA9377_1_0_DEVICE_ID, QCA9377_HW_1_1_CHIP_ID_REV },
106
107 { QCA9887_1_0_DEVICE_ID, QCA9887_HW_1_0_CHIP_ID_REV },
108 };
109
110 static void ath10k_pci_buffer_cleanup(struct ath10k *ar);
111 static int ath10k_pci_cold_reset(struct ath10k *ar);
112 static int ath10k_pci_safe_chip_reset(struct ath10k *ar);
113 static int ath10k_pci_init_irq(struct ath10k *ar);
114 static int ath10k_pci_deinit_irq(struct ath10k *ar);
115 static int ath10k_pci_request_irq(struct ath10k *ar);
116 static void ath10k_pci_free_irq(struct ath10k *ar);
117 static int ath10k_pci_bmi_wait(struct ath10k *ar,
118 struct ath10k_ce_pipe *tx_pipe,
119 struct ath10k_ce_pipe *rx_pipe,
120 struct bmi_xfer *xfer);
121 static int ath10k_pci_qca99x0_chip_reset(struct ath10k *ar);
122 static void ath10k_pci_htc_tx_cb(struct ath10k_ce_pipe *ce_state);
123 static void ath10k_pci_htc_rx_cb(struct ath10k_ce_pipe *ce_state);
124 static void ath10k_pci_htt_tx_cb(struct ath10k_ce_pipe *ce_state);
125 static void ath10k_pci_htt_rx_cb(struct ath10k_ce_pipe *ce_state);
126 static void ath10k_pci_htt_htc_rx_cb(struct ath10k_ce_pipe *ce_state);
127 static void ath10k_pci_pktlog_rx_cb(struct ath10k_ce_pipe *ce_state);
128
129 static const struct ce_attr pci_host_ce_config_wlan[] = {
130 /* CE0: host->target HTC control and raw streams */
131 {
132 .flags = CE_ATTR_FLAGS,
133 .src_nentries = 16,
134 .src_sz_max = 256,
135 .dest_nentries = 0,
136 .send_cb = ath10k_pci_htc_tx_cb,
137 },
138
139 /* CE1: target->host HTT + HTC control */
140 {
141 .flags = CE_ATTR_FLAGS,
142 .src_nentries = 0,
143 .src_sz_max = 2048,
144 .dest_nentries = 512,
145 .recv_cb = ath10k_pci_htt_htc_rx_cb,
146 },
147
148 /* CE2: target->host WMI */
149 {
150 .flags = CE_ATTR_FLAGS,
151 .src_nentries = 0,
152 .src_sz_max = 2048,
153 .dest_nentries = 128,
154 .recv_cb = ath10k_pci_htc_rx_cb,
155 },
156
157 /* CE3: host->target WMI */
158 {
159 .flags = CE_ATTR_FLAGS,
160 .src_nentries = 32,
161 .src_sz_max = 2048,
162 .dest_nentries = 0,
163 .send_cb = ath10k_pci_htc_tx_cb,
164 },
165
166 /* CE4: host->target HTT */
167 {
168 .flags = CE_ATTR_FLAGS | CE_ATTR_DIS_INTR,
169 .src_nentries = CE_HTT_H2T_MSG_SRC_NENTRIES,
170 .src_sz_max = 256,
171 .dest_nentries = 0,
172 .send_cb = ath10k_pci_htt_tx_cb,
173 },
174
175 /* CE5: target->host HTT (HIF->HTT) */
176 {
177 .flags = CE_ATTR_FLAGS,
178 .src_nentries = 0,
179 .src_sz_max = 512,
180 .dest_nentries = 512,
181 .recv_cb = ath10k_pci_htt_rx_cb,
182 },
183
184 /* CE6: target autonomous hif_memcpy */
185 {
186 .flags = CE_ATTR_FLAGS,
187 .src_nentries = 0,
188 .src_sz_max = 0,
189 .dest_nentries = 0,
190 },
191
192 /* CE7: ce_diag, the Diagnostic Window */
193 {
194 .flags = CE_ATTR_FLAGS | CE_ATTR_POLL,
195 .src_nentries = 2,
196 .src_sz_max = DIAG_TRANSFER_LIMIT,
197 .dest_nentries = 2,
198 },
199
200 /* CE8: target->host pktlog */
201 {
202 .flags = CE_ATTR_FLAGS,
203 .src_nentries = 0,
204 .src_sz_max = 2048,
205 .dest_nentries = 128,
206 .recv_cb = ath10k_pci_pktlog_rx_cb,
207 },
208
209 /* CE9 target autonomous qcache memcpy */
210 {
211 .flags = CE_ATTR_FLAGS,
212 .src_nentries = 0,
213 .src_sz_max = 0,
214 .dest_nentries = 0,
215 },
216
217 /* CE10: target autonomous hif memcpy */
218 {
219 .flags = CE_ATTR_FLAGS,
220 .src_nentries = 0,
221 .src_sz_max = 0,
222 .dest_nentries = 0,
223 },
224
225 /* CE11: target autonomous hif memcpy */
226 {
227 .flags = CE_ATTR_FLAGS,
228 .src_nentries = 0,
229 .src_sz_max = 0,
230 .dest_nentries = 0,
231 },
232 };
233
234 /* Target firmware's Copy Engine configuration. */
235 static const struct ce_pipe_config pci_target_ce_config_wlan[] = {
236 /* CE0: host->target HTC control and raw streams */
237 {
238 .pipenum = __cpu_to_le32(0),
239 .pipedir = __cpu_to_le32(PIPEDIR_OUT),
240 .nentries = __cpu_to_le32(32),
241 .nbytes_max = __cpu_to_le32(256),
242 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
243 .reserved = __cpu_to_le32(0),
244 },
245
246 /* CE1: target->host HTT + HTC control */
247 {
248 .pipenum = __cpu_to_le32(1),
249 .pipedir = __cpu_to_le32(PIPEDIR_IN),
250 .nentries = __cpu_to_le32(32),
251 .nbytes_max = __cpu_to_le32(2048),
252 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
253 .reserved = __cpu_to_le32(0),
254 },
255
256 /* CE2: target->host WMI */
257 {
258 .pipenum = __cpu_to_le32(2),
259 .pipedir = __cpu_to_le32(PIPEDIR_IN),
260 .nentries = __cpu_to_le32(64),
261 .nbytes_max = __cpu_to_le32(2048),
262 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
263 .reserved = __cpu_to_le32(0),
264 },
265
266 /* CE3: host->target WMI */
267 {
268 .pipenum = __cpu_to_le32(3),
269 .pipedir = __cpu_to_le32(PIPEDIR_OUT),
270 .nentries = __cpu_to_le32(32),
271 .nbytes_max = __cpu_to_le32(2048),
272 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
273 .reserved = __cpu_to_le32(0),
274 },
275
276 /* CE4: host->target HTT */
277 {
278 .pipenum = __cpu_to_le32(4),
279 .pipedir = __cpu_to_le32(PIPEDIR_OUT),
280 .nentries = __cpu_to_le32(256),
281 .nbytes_max = __cpu_to_le32(256),
282 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
283 .reserved = __cpu_to_le32(0),
284 },
285
286 /* NB: 50% of src nentries, since tx has 2 frags */
287
288 /* CE5: target->host HTT (HIF->HTT) */
289 {
290 .pipenum = __cpu_to_le32(5),
291 .pipedir = __cpu_to_le32(PIPEDIR_IN),
292 .nentries = __cpu_to_le32(32),
293 .nbytes_max = __cpu_to_le32(512),
294 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
295 .reserved = __cpu_to_le32(0),
296 },
297
298 /* CE6: Reserved for target autonomous hif_memcpy */
299 {
300 .pipenum = __cpu_to_le32(6),
301 .pipedir = __cpu_to_le32(PIPEDIR_INOUT),
302 .nentries = __cpu_to_le32(32),
303 .nbytes_max = __cpu_to_le32(4096),
304 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
305 .reserved = __cpu_to_le32(0),
306 },
307
308 /* CE7 used only by Host */
309 {
310 .pipenum = __cpu_to_le32(7),
311 .pipedir = __cpu_to_le32(PIPEDIR_INOUT),
312 .nentries = __cpu_to_le32(0),
313 .nbytes_max = __cpu_to_le32(0),
314 .flags = __cpu_to_le32(0),
315 .reserved = __cpu_to_le32(0),
316 },
317
318 /* CE8 target->host packtlog */
319 {
320 .pipenum = __cpu_to_le32(8),
321 .pipedir = __cpu_to_le32(PIPEDIR_IN),
322 .nentries = __cpu_to_le32(64),
323 .nbytes_max = __cpu_to_le32(2048),
324 .flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR),
325 .reserved = __cpu_to_le32(0),
326 },
327
328 /* CE9 target autonomous qcache memcpy */
329 {
330 .pipenum = __cpu_to_le32(9),
331 .pipedir = __cpu_to_le32(PIPEDIR_INOUT),
332 .nentries = __cpu_to_le32(32),
333 .nbytes_max = __cpu_to_le32(2048),
334 .flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR),
335 .reserved = __cpu_to_le32(0),
336 },
337
338 /* It not necessary to send target wlan configuration for CE10 & CE11
339 * as these CEs are not actively used in target.
340 */
341 };
342
343 /*
344 * Map from service/endpoint to Copy Engine.
345 * This table is derived from the CE_PCI TABLE, above.
346 * It is passed to the Target at startup for use by firmware.
347 */
348 static const struct ce_service_to_pipe pci_target_service_to_ce_map_wlan[] = {
349 {
350 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_VO),
351 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
352 __cpu_to_le32(3),
353 },
354 {
355 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_VO),
356 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
357 __cpu_to_le32(2),
358 },
359 {
360 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_BK),
361 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
362 __cpu_to_le32(3),
363 },
364 {
365 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_BK),
366 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
367 __cpu_to_le32(2),
368 },
369 {
370 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_BE),
371 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
372 __cpu_to_le32(3),
373 },
374 {
375 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_BE),
376 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
377 __cpu_to_le32(2),
378 },
379 {
380 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_VI),
381 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
382 __cpu_to_le32(3),
383 },
384 {
385 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_VI),
386 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
387 __cpu_to_le32(2),
388 },
389 {
390 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_CONTROL),
391 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
392 __cpu_to_le32(3),
393 },
394 {
395 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_CONTROL),
396 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
397 __cpu_to_le32(2),
398 },
399 {
400 __cpu_to_le32(ATH10K_HTC_SVC_ID_RSVD_CTRL),
401 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
402 __cpu_to_le32(0),
403 },
404 {
405 __cpu_to_le32(ATH10K_HTC_SVC_ID_RSVD_CTRL),
406 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
407 __cpu_to_le32(1),
408 },
409 { /* not used */
410 __cpu_to_le32(ATH10K_HTC_SVC_ID_TEST_RAW_STREAMS),
411 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
412 __cpu_to_le32(0),
413 },
414 { /* not used */
415 __cpu_to_le32(ATH10K_HTC_SVC_ID_TEST_RAW_STREAMS),
416 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
417 __cpu_to_le32(1),
418 },
419 {
420 __cpu_to_le32(ATH10K_HTC_SVC_ID_HTT_DATA_MSG),
421 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
422 __cpu_to_le32(4),
423 },
424 {
425 __cpu_to_le32(ATH10K_HTC_SVC_ID_HTT_DATA_MSG),
426 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
427 __cpu_to_le32(5),
428 },
429
430 /* (Additions here) */
431
432 { /* must be last */
433 __cpu_to_le32(0),
434 __cpu_to_le32(0),
435 __cpu_to_le32(0),
436 },
437 };
438
ath10k_pci_is_awake(struct ath10k * ar)439 static bool ath10k_pci_is_awake(struct ath10k *ar)
440 {
441 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
442 #if defined(__linux__)
443 u32 val = ioread32(ar_pci->mem + PCIE_LOCAL_BASE_ADDRESS +
444 RTC_STATE_ADDRESS);
445 #elif defined(__FreeBSD__)
446 u32 val = bus_read_4((struct resource *)ar_pci->mem, PCIE_LOCAL_BASE_ADDRESS +
447 RTC_STATE_ADDRESS);
448 #endif
449
450 return RTC_STATE_V_GET(val) == RTC_STATE_V_ON;
451 }
452
__ath10k_pci_wake(struct ath10k * ar)453 static void __ath10k_pci_wake(struct ath10k *ar)
454 {
455 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
456
457 lockdep_assert_held(&ar_pci->ps_lock);
458
459 ath10k_dbg(ar, ATH10K_DBG_PCI_PS, "pci ps wake reg refcount %lu awake %d\n",
460 ar_pci->ps_wake_refcount, ar_pci->ps_awake);
461
462 #if defined(__linux__)
463 iowrite32(PCIE_SOC_WAKE_V_MASK,
464 ar_pci->mem + PCIE_LOCAL_BASE_ADDRESS +
465 PCIE_SOC_WAKE_ADDRESS);
466 #elif defined(__FreeBSD__)
467 bus_write_4((struct resource *)ar_pci->mem,
468 PCIE_LOCAL_BASE_ADDRESS + PCIE_SOC_WAKE_ADDRESS,
469 PCIE_SOC_WAKE_V_MASK);
470 #endif
471 }
472
__ath10k_pci_sleep(struct ath10k * ar)473 static void __ath10k_pci_sleep(struct ath10k *ar)
474 {
475 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
476
477 lockdep_assert_held(&ar_pci->ps_lock);
478
479 ath10k_dbg(ar, ATH10K_DBG_PCI_PS, "pci ps sleep reg refcount %lu awake %d\n",
480 ar_pci->ps_wake_refcount, ar_pci->ps_awake);
481
482 #if defined(__linux__)
483 iowrite32(PCIE_SOC_WAKE_RESET,
484 ar_pci->mem + PCIE_LOCAL_BASE_ADDRESS +
485 PCIE_SOC_WAKE_ADDRESS);
486 #elif defined(__FreeBSD__)
487 bus_write_4((struct resource *)ar_pci->mem,
488 PCIE_LOCAL_BASE_ADDRESS + PCIE_SOC_WAKE_ADDRESS,
489 PCIE_SOC_WAKE_RESET);
490 #endif
491 ar_pci->ps_awake = false;
492 }
493
ath10k_pci_wake_wait(struct ath10k * ar)494 static int ath10k_pci_wake_wait(struct ath10k *ar)
495 {
496 int tot_delay = 0;
497 int curr_delay = 5;
498
499 while (tot_delay < PCIE_WAKE_TIMEOUT) {
500 if (ath10k_pci_is_awake(ar)) {
501 if (tot_delay > PCIE_WAKE_LATE_US)
502 ath10k_warn(ar, "device wakeup took %d ms which is unusually long, otherwise it works normally.\n",
503 tot_delay / 1000);
504 return 0;
505 }
506
507 udelay(curr_delay);
508 tot_delay += curr_delay;
509
510 if (curr_delay < 50)
511 curr_delay += 5;
512 }
513
514 return -ETIMEDOUT;
515 }
516
ath10k_pci_force_wake(struct ath10k * ar)517 static int ath10k_pci_force_wake(struct ath10k *ar)
518 {
519 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
520 unsigned long flags;
521 int ret = 0;
522
523 if (ar_pci->pci_ps)
524 return ret;
525
526 spin_lock_irqsave(&ar_pci->ps_lock, flags);
527
528 if (!ar_pci->ps_awake) {
529 #if defined(__linux__)
530 iowrite32(PCIE_SOC_WAKE_V_MASK,
531 ar_pci->mem + PCIE_LOCAL_BASE_ADDRESS +
532 PCIE_SOC_WAKE_ADDRESS);
533 #elif defined(__FreeBSD__)
534 bus_write_4((struct resource *)ar_pci->mem,
535 PCIE_LOCAL_BASE_ADDRESS + PCIE_SOC_WAKE_ADDRESS,
536 PCIE_SOC_WAKE_V_MASK);
537 #endif
538
539 ret = ath10k_pci_wake_wait(ar);
540 if (ret == 0)
541 ar_pci->ps_awake = true;
542 }
543
544 spin_unlock_irqrestore(&ar_pci->ps_lock, flags);
545
546 return ret;
547 }
548
ath10k_pci_force_sleep(struct ath10k * ar)549 static void ath10k_pci_force_sleep(struct ath10k *ar)
550 {
551 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
552 unsigned long flags;
553
554 spin_lock_irqsave(&ar_pci->ps_lock, flags);
555
556 #if defined(__linux__)
557 iowrite32(PCIE_SOC_WAKE_RESET,
558 ar_pci->mem + PCIE_LOCAL_BASE_ADDRESS +
559 PCIE_SOC_WAKE_ADDRESS);
560 #elif defined(__FreeBSD__)
561 bus_write_4((struct resource *)ar_pci->mem,
562 PCIE_LOCAL_BASE_ADDRESS + PCIE_SOC_WAKE_ADDRESS,
563 PCIE_SOC_WAKE_RESET);
564 #endif
565 ar_pci->ps_awake = false;
566
567 spin_unlock_irqrestore(&ar_pci->ps_lock, flags);
568 }
569
ath10k_pci_wake(struct ath10k * ar)570 static int ath10k_pci_wake(struct ath10k *ar)
571 {
572 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
573 unsigned long flags;
574 int ret = 0;
575
576 if (ar_pci->pci_ps == 0)
577 return ret;
578
579 spin_lock_irqsave(&ar_pci->ps_lock, flags);
580
581 ath10k_dbg(ar, ATH10K_DBG_PCI_PS, "pci ps wake refcount %lu awake %d\n",
582 ar_pci->ps_wake_refcount, ar_pci->ps_awake);
583
584 /* This function can be called very frequently. To avoid excessive
585 * CPU stalls for MMIO reads use a cache var to hold the device state.
586 */
587 if (!ar_pci->ps_awake) {
588 __ath10k_pci_wake(ar);
589
590 ret = ath10k_pci_wake_wait(ar);
591 if (ret == 0)
592 ar_pci->ps_awake = true;
593 }
594
595 if (ret == 0) {
596 ar_pci->ps_wake_refcount++;
597 WARN_ON(ar_pci->ps_wake_refcount == 0);
598 }
599
600 spin_unlock_irqrestore(&ar_pci->ps_lock, flags);
601
602 return ret;
603 }
604
ath10k_pci_sleep(struct ath10k * ar)605 static void ath10k_pci_sleep(struct ath10k *ar)
606 {
607 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
608 unsigned long flags;
609
610 if (ar_pci->pci_ps == 0)
611 return;
612
613 spin_lock_irqsave(&ar_pci->ps_lock, flags);
614
615 ath10k_dbg(ar, ATH10K_DBG_PCI_PS, "pci ps sleep refcount %lu awake %d\n",
616 ar_pci->ps_wake_refcount, ar_pci->ps_awake);
617
618 if (WARN_ON(ar_pci->ps_wake_refcount == 0))
619 goto skip;
620
621 ar_pci->ps_wake_refcount--;
622
623 mod_timer(&ar_pci->ps_timer, jiffies +
624 msecs_to_jiffies(ATH10K_PCI_SLEEP_GRACE_PERIOD_MSEC));
625
626 skip:
627 spin_unlock_irqrestore(&ar_pci->ps_lock, flags);
628 }
629
ath10k_pci_ps_timer(struct timer_list * t)630 static void ath10k_pci_ps_timer(struct timer_list *t)
631 {
632 struct ath10k_pci *ar_pci = timer_container_of(ar_pci, t, ps_timer);
633 struct ath10k *ar = ar_pci->ar;
634 unsigned long flags;
635
636 spin_lock_irqsave(&ar_pci->ps_lock, flags);
637
638 ath10k_dbg(ar, ATH10K_DBG_PCI_PS, "pci ps timer refcount %lu awake %d\n",
639 ar_pci->ps_wake_refcount, ar_pci->ps_awake);
640
641 if (ar_pci->ps_wake_refcount > 0)
642 goto skip;
643
644 __ath10k_pci_sleep(ar);
645
646 skip:
647 spin_unlock_irqrestore(&ar_pci->ps_lock, flags);
648 }
649
ath10k_pci_sleep_sync(struct ath10k * ar)650 static void ath10k_pci_sleep_sync(struct ath10k *ar)
651 {
652 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
653 unsigned long flags;
654
655 if (ar_pci->pci_ps == 0) {
656 ath10k_pci_force_sleep(ar);
657 return;
658 }
659
660 timer_delete_sync(&ar_pci->ps_timer);
661
662 spin_lock_irqsave(&ar_pci->ps_lock, flags);
663 WARN_ON(ar_pci->ps_wake_refcount > 0);
664 __ath10k_pci_sleep(ar);
665 spin_unlock_irqrestore(&ar_pci->ps_lock, flags);
666 }
667
ath10k_bus_pci_write32(struct ath10k * ar,u32 offset,u32 value)668 static void ath10k_bus_pci_write32(struct ath10k *ar, u32 offset, u32 value)
669 {
670 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
671 int ret;
672
673 if (unlikely(offset + sizeof(value) > ar_pci->mem_len)) {
674 ath10k_warn(ar, "refusing to write mmio out of bounds at 0x%08x - 0x%08zx (max 0x%08zx)\n",
675 offset, offset + sizeof(value), ar_pci->mem_len);
676 return;
677 }
678
679 ret = ath10k_pci_wake(ar);
680 if (ret) {
681 ath10k_warn(ar, "failed to wake target for write32 of 0x%08x at 0x%08x: %d\n",
682 value, offset, ret);
683 return;
684 }
685
686 #if defined(__linux__)
687 iowrite32(value, ar_pci->mem + offset);
688 #elif defined(__FreeBSD__)
689 bus_write_4((struct resource *)ar_pci->mem, offset, value);
690 #endif
691 ath10k_pci_sleep(ar);
692 }
693
ath10k_bus_pci_read32(struct ath10k * ar,u32 offset)694 static u32 ath10k_bus_pci_read32(struct ath10k *ar, u32 offset)
695 {
696 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
697 u32 val;
698 int ret;
699
700 if (unlikely(offset + sizeof(val) > ar_pci->mem_len)) {
701 ath10k_warn(ar, "refusing to read mmio out of bounds at 0x%08x - 0x%08zx (max 0x%08zx)\n",
702 offset, offset + sizeof(val), ar_pci->mem_len);
703 return 0;
704 }
705
706 ret = ath10k_pci_wake(ar);
707 if (ret) {
708 ath10k_warn(ar, "failed to wake target for read32 at 0x%08x: %d\n",
709 offset, ret);
710 return 0xffffffff;
711 }
712
713 #if defined(__linux__)
714 val = ioread32(ar_pci->mem + offset);
715 #elif defined(__FreeBSD__)
716 val = bus_read_4((struct resource *)ar_pci->mem, offset);
717 #endif
718 ath10k_pci_sleep(ar);
719
720 return val;
721 }
722
ath10k_pci_write32(struct ath10k * ar,u32 offset,u32 value)723 inline void ath10k_pci_write32(struct ath10k *ar, u32 offset, u32 value)
724 {
725 struct ath10k_ce *ce = ath10k_ce_priv(ar);
726
727 ce->bus_ops->write32(ar, offset, value);
728 }
729
ath10k_pci_read32(struct ath10k * ar,u32 offset)730 inline u32 ath10k_pci_read32(struct ath10k *ar, u32 offset)
731 {
732 struct ath10k_ce *ce = ath10k_ce_priv(ar);
733
734 return ce->bus_ops->read32(ar, offset);
735 }
736
ath10k_pci_soc_read32(struct ath10k * ar,u32 addr)737 u32 ath10k_pci_soc_read32(struct ath10k *ar, u32 addr)
738 {
739 return ath10k_pci_read32(ar, RTC_SOC_BASE_ADDRESS + addr);
740 }
741
ath10k_pci_soc_write32(struct ath10k * ar,u32 addr,u32 val)742 void ath10k_pci_soc_write32(struct ath10k *ar, u32 addr, u32 val)
743 {
744 ath10k_pci_write32(ar, RTC_SOC_BASE_ADDRESS + addr, val);
745 }
746
ath10k_pci_reg_read32(struct ath10k * ar,u32 addr)747 u32 ath10k_pci_reg_read32(struct ath10k *ar, u32 addr)
748 {
749 return ath10k_pci_read32(ar, PCIE_LOCAL_BASE_ADDRESS + addr);
750 }
751
ath10k_pci_reg_write32(struct ath10k * ar,u32 addr,u32 val)752 void ath10k_pci_reg_write32(struct ath10k *ar, u32 addr, u32 val)
753 {
754 ath10k_pci_write32(ar, PCIE_LOCAL_BASE_ADDRESS + addr, val);
755 }
756
ath10k_pci_irq_pending(struct ath10k * ar)757 bool ath10k_pci_irq_pending(struct ath10k *ar)
758 {
759 u32 cause;
760
761 /* Check if the shared legacy irq is for us */
762 cause = ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS +
763 PCIE_INTR_CAUSE_ADDRESS);
764 if (cause & (PCIE_INTR_FIRMWARE_MASK | PCIE_INTR_CE_MASK_ALL))
765 return true;
766
767 return false;
768 }
769
ath10k_pci_disable_and_clear_intx_irq(struct ath10k * ar)770 void ath10k_pci_disable_and_clear_intx_irq(struct ath10k *ar)
771 {
772 /* IMPORTANT: INTR_CLR register has to be set after
773 * INTR_ENABLE is set to 0, otherwise interrupt can not be
774 * really cleared.
775 */
776 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + PCIE_INTR_ENABLE_ADDRESS,
777 0);
778 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + PCIE_INTR_CLR_ADDRESS,
779 PCIE_INTR_FIRMWARE_MASK | PCIE_INTR_CE_MASK_ALL);
780
781 /* IMPORTANT: this extra read transaction is required to
782 * flush the posted write buffer.
783 */
784 (void)ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS +
785 PCIE_INTR_ENABLE_ADDRESS);
786 }
787
ath10k_pci_enable_intx_irq(struct ath10k * ar)788 void ath10k_pci_enable_intx_irq(struct ath10k *ar)
789 {
790 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS +
791 PCIE_INTR_ENABLE_ADDRESS,
792 PCIE_INTR_FIRMWARE_MASK | PCIE_INTR_CE_MASK_ALL);
793
794 /* IMPORTANT: this extra read transaction is required to
795 * flush the posted write buffer.
796 */
797 (void)ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS +
798 PCIE_INTR_ENABLE_ADDRESS);
799 }
800
ath10k_pci_get_irq_method(struct ath10k * ar)801 static inline const char *ath10k_pci_get_irq_method(struct ath10k *ar)
802 {
803 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
804
805 if (ar_pci->oper_irq_mode == ATH10K_PCI_IRQ_MSI)
806 return "msi";
807
808 return "legacy";
809 }
810
__ath10k_pci_rx_post_buf(struct ath10k_pci_pipe * pipe)811 static int __ath10k_pci_rx_post_buf(struct ath10k_pci_pipe *pipe)
812 {
813 struct ath10k *ar = pipe->hif_ce_state;
814 struct ath10k_ce *ce = ath10k_ce_priv(ar);
815 struct ath10k_ce_pipe *ce_pipe = pipe->ce_hdl;
816 struct sk_buff *skb;
817 dma_addr_t paddr;
818 int ret;
819
820 skb = dev_alloc_skb(pipe->buf_sz);
821 if (!skb)
822 return -ENOMEM;
823
824 WARN_ONCE((unsigned long)skb->data & 3, "unaligned skb");
825
826 paddr = dma_map_single(ar->dev, skb->data,
827 skb->len + skb_tailroom(skb),
828 DMA_FROM_DEVICE);
829 if (unlikely(dma_mapping_error(ar->dev, paddr))) {
830 ath10k_warn(ar, "failed to dma map pci rx buf\n");
831 dev_kfree_skb_any(skb);
832 return -EIO;
833 }
834
835 ATH10K_SKB_RXCB(skb)->paddr = paddr;
836
837 spin_lock_bh(&ce->ce_lock);
838 ret = ce_pipe->ops->ce_rx_post_buf(ce_pipe, skb, paddr);
839 spin_unlock_bh(&ce->ce_lock);
840 if (ret) {
841 dma_unmap_single(ar->dev, paddr, skb->len + skb_tailroom(skb),
842 DMA_FROM_DEVICE);
843 dev_kfree_skb_any(skb);
844 return ret;
845 }
846
847 return 0;
848 }
849
ath10k_pci_rx_post_pipe(struct ath10k_pci_pipe * pipe)850 static void ath10k_pci_rx_post_pipe(struct ath10k_pci_pipe *pipe)
851 {
852 struct ath10k *ar = pipe->hif_ce_state;
853 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
854 struct ath10k_ce *ce = ath10k_ce_priv(ar);
855 struct ath10k_ce_pipe *ce_pipe = pipe->ce_hdl;
856 int ret, num;
857
858 if (pipe->buf_sz == 0)
859 return;
860
861 if (!ce_pipe->dest_ring)
862 return;
863
864 spin_lock_bh(&ce->ce_lock);
865 num = __ath10k_ce_rx_num_free_bufs(ce_pipe);
866 spin_unlock_bh(&ce->ce_lock);
867
868 while (num >= 0) {
869 ret = __ath10k_pci_rx_post_buf(pipe);
870 if (ret) {
871 if (ret == -ENOSPC)
872 break;
873 ath10k_warn(ar, "failed to post pci rx buf: %d\n", ret);
874 mod_timer(&ar_pci->rx_post_retry, jiffies +
875 ATH10K_PCI_RX_POST_RETRY_MS);
876 break;
877 }
878 num--;
879 }
880 }
881
ath10k_pci_rx_post(struct ath10k * ar)882 void ath10k_pci_rx_post(struct ath10k *ar)
883 {
884 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
885 int i;
886
887 for (i = 0; i < CE_COUNT; i++)
888 ath10k_pci_rx_post_pipe(&ar_pci->pipe_info[i]);
889 }
890
ath10k_pci_rx_replenish_retry(struct timer_list * t)891 void ath10k_pci_rx_replenish_retry(struct timer_list *t)
892 {
893 struct ath10k_pci *ar_pci = timer_container_of(ar_pci, t,
894 rx_post_retry);
895 struct ath10k *ar = ar_pci->ar;
896
897 ath10k_pci_rx_post(ar);
898 }
899
ath10k_pci_qca988x_targ_cpu_to_ce_addr(struct ath10k * ar,u32 addr)900 static u32 ath10k_pci_qca988x_targ_cpu_to_ce_addr(struct ath10k *ar, u32 addr)
901 {
902 u32 val = 0, region = addr & 0xfffff;
903
904 val = (ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS + CORE_CTRL_ADDRESS)
905 & 0x7ff) << 21;
906 val |= 0x100000 | region;
907 return val;
908 }
909
910 /* Refactor from ath10k_pci_qca988x_targ_cpu_to_ce_addr.
911 * Support to access target space below 1M for qca6174 and qca9377.
912 * If target space is below 1M, the bit[20] of converted CE addr is 0.
913 * Otherwise bit[20] of converted CE addr is 1.
914 */
ath10k_pci_qca6174_targ_cpu_to_ce_addr(struct ath10k * ar,u32 addr)915 static u32 ath10k_pci_qca6174_targ_cpu_to_ce_addr(struct ath10k *ar, u32 addr)
916 {
917 u32 val = 0, region = addr & 0xfffff;
918
919 val = (ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS + CORE_CTRL_ADDRESS)
920 & 0x7ff) << 21;
921 val |= ((addr >= 0x100000) ? 0x100000 : 0) | region;
922 return val;
923 }
924
ath10k_pci_qca99x0_targ_cpu_to_ce_addr(struct ath10k * ar,u32 addr)925 static u32 ath10k_pci_qca99x0_targ_cpu_to_ce_addr(struct ath10k *ar, u32 addr)
926 {
927 u32 val = 0, region = addr & 0xfffff;
928
929 val = ath10k_pci_read32(ar, PCIE_BAR_REG_ADDRESS);
930 val |= 0x100000 | region;
931 return val;
932 }
933
ath10k_pci_targ_cpu_to_ce_addr(struct ath10k * ar,u32 addr)934 static u32 ath10k_pci_targ_cpu_to_ce_addr(struct ath10k *ar, u32 addr)
935 {
936 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
937
938 if (WARN_ON_ONCE(!ar_pci->targ_cpu_to_ce_addr))
939 return -EOPNOTSUPP;
940
941 return ar_pci->targ_cpu_to_ce_addr(ar, addr);
942 }
943
944 /*
945 * Diagnostic read/write access is provided for startup/config/debug usage.
946 * Caller must guarantee proper alignment, when applicable, and single user
947 * at any moment.
948 */
949 #if defined(__linux__)
ath10k_pci_diag_read_mem(struct ath10k * ar,u32 address,void * data,int nbytes)950 static int ath10k_pci_diag_read_mem(struct ath10k *ar, u32 address, void *data,
951 #elif defined(__FreeBSD__)
952 static int ath10k_pci_diag_read_mem(struct ath10k *ar, u32 address, u8 *data,
953 #endif
954 int nbytes)
955 {
956 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
957 int ret = 0;
958 u32 *buf;
959 unsigned int completed_nbytes, alloc_nbytes, remaining_bytes;
960 struct ath10k_ce_pipe *ce_diag;
961 /* Host buffer address in CE space */
962 u32 ce_data;
963 dma_addr_t ce_data_base = 0;
964 void *data_buf;
965 int i;
966
967 mutex_lock(&ar_pci->ce_diag_mutex);
968 ce_diag = ar_pci->ce_diag;
969
970 /*
971 * Allocate a temporary bounce buffer to hold caller's data
972 * to be DMA'ed from Target. This guarantees
973 * 1) 4-byte alignment
974 * 2) Buffer in DMA-able space
975 */
976 alloc_nbytes = min_t(unsigned int, nbytes, DIAG_TRANSFER_LIMIT);
977
978 data_buf = dma_alloc_coherent(ar->dev, alloc_nbytes, &ce_data_base,
979 GFP_ATOMIC);
980 if (!data_buf) {
981 ret = -ENOMEM;
982 goto done;
983 }
984
985 /* The address supplied by the caller is in the
986 * Target CPU virtual address space.
987 *
988 * In order to use this address with the diagnostic CE,
989 * convert it from Target CPU virtual address space
990 * to CE address space
991 */
992 address = ath10k_pci_targ_cpu_to_ce_addr(ar, address);
993
994 remaining_bytes = nbytes;
995 ce_data = ce_data_base;
996 while (remaining_bytes) {
997 nbytes = min_t(unsigned int, remaining_bytes,
998 DIAG_TRANSFER_LIMIT);
999
1000 ret = ath10k_ce_rx_post_buf(ce_diag, &ce_data, ce_data);
1001 if (ret != 0)
1002 goto done;
1003
1004 /* Request CE to send from Target(!) address to Host buffer */
1005 ret = ath10k_ce_send(ce_diag, NULL, (u32)address, nbytes, 0, 0);
1006 if (ret)
1007 goto done;
1008
1009 i = 0;
1010 while (ath10k_ce_completed_send_next(ce_diag, NULL) != 0) {
1011 udelay(DIAG_ACCESS_CE_WAIT_US);
1012 i += DIAG_ACCESS_CE_WAIT_US;
1013
1014 if (i > DIAG_ACCESS_CE_TIMEOUT_US) {
1015 ret = -EBUSY;
1016 goto done;
1017 }
1018 }
1019
1020 i = 0;
1021 while (ath10k_ce_completed_recv_next(ce_diag, (void **)&buf,
1022 &completed_nbytes) != 0) {
1023 udelay(DIAG_ACCESS_CE_WAIT_US);
1024 i += DIAG_ACCESS_CE_WAIT_US;
1025
1026 if (i > DIAG_ACCESS_CE_TIMEOUT_US) {
1027 ret = -EBUSY;
1028 goto done;
1029 }
1030 }
1031
1032 if (nbytes != completed_nbytes) {
1033 ret = -EIO;
1034 goto done;
1035 }
1036
1037 if (*buf != ce_data) {
1038 ret = -EIO;
1039 goto done;
1040 }
1041
1042 remaining_bytes -= nbytes;
1043 memcpy(data, data_buf, nbytes);
1044
1045 address += nbytes;
1046 data += nbytes;
1047 }
1048
1049 done:
1050
1051 if (data_buf)
1052 dma_free_coherent(ar->dev, alloc_nbytes, data_buf,
1053 ce_data_base);
1054
1055 mutex_unlock(&ar_pci->ce_diag_mutex);
1056
1057 return ret;
1058 }
1059
ath10k_pci_diag_read32(struct ath10k * ar,u32 address,u32 * value)1060 static int ath10k_pci_diag_read32(struct ath10k *ar, u32 address, u32 *value)
1061 {
1062 __le32 val = 0;
1063 int ret;
1064
1065 #if defined(__linux__)
1066 ret = ath10k_pci_diag_read_mem(ar, address, &val, sizeof(val));
1067 #elif defined(__FreeBSD__)
1068 ret = ath10k_pci_diag_read_mem(ar, address, (u8 *)&val, sizeof(val));
1069 #endif
1070 *value = __le32_to_cpu(val);
1071
1072 return ret;
1073 }
1074
__ath10k_pci_diag_read_hi(struct ath10k * ar,void * dest,u32 src,u32 len)1075 static int __ath10k_pci_diag_read_hi(struct ath10k *ar, void *dest,
1076 u32 src, u32 len)
1077 {
1078 u32 host_addr, addr;
1079 int ret;
1080
1081 host_addr = host_interest_item_address(src);
1082
1083 ret = ath10k_pci_diag_read32(ar, host_addr, &addr);
1084 if (ret != 0) {
1085 ath10k_warn(ar, "failed to get memcpy hi address for firmware address %d: %d\n",
1086 src, ret);
1087 return ret;
1088 }
1089
1090 ret = ath10k_pci_diag_read_mem(ar, addr, dest, len);
1091 if (ret != 0) {
1092 ath10k_warn(ar, "failed to memcpy firmware memory from %d (%d B): %d\n",
1093 addr, len, ret);
1094 return ret;
1095 }
1096
1097 return 0;
1098 }
1099
1100 #define ath10k_pci_diag_read_hi(ar, dest, src, len) \
1101 __ath10k_pci_diag_read_hi(ar, dest, HI_ITEM(src), len)
1102
ath10k_pci_diag_write_mem(struct ath10k * ar,u32 address,const void * data,int nbytes)1103 int ath10k_pci_diag_write_mem(struct ath10k *ar, u32 address,
1104 #if defined(__linux__)
1105 const void *data, int nbytes)
1106 #elif defined(__FreeBSD__)
1107 const void *_d, int nbytes)
1108 #endif
1109 {
1110 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1111 int ret = 0;
1112 u32 *buf;
1113 unsigned int completed_nbytes, alloc_nbytes, remaining_bytes;
1114 struct ath10k_ce_pipe *ce_diag;
1115 void *data_buf;
1116 dma_addr_t ce_data_base = 0;
1117 int i;
1118 #if defined(__FreeBSD__)
1119 const u8 *data = _d;
1120 #endif
1121
1122 mutex_lock(&ar_pci->ce_diag_mutex);
1123 ce_diag = ar_pci->ce_diag;
1124
1125 /*
1126 * Allocate a temporary bounce buffer to hold caller's data
1127 * to be DMA'ed to Target. This guarantees
1128 * 1) 4-byte alignment
1129 * 2) Buffer in DMA-able space
1130 */
1131 alloc_nbytes = min_t(unsigned int, nbytes, DIAG_TRANSFER_LIMIT);
1132
1133 data_buf = dma_alloc_coherent(ar->dev, alloc_nbytes, &ce_data_base,
1134 GFP_ATOMIC);
1135 if (!data_buf) {
1136 ret = -ENOMEM;
1137 goto done;
1138 }
1139
1140 /*
1141 * The address supplied by the caller is in the
1142 * Target CPU virtual address space.
1143 *
1144 * In order to use this address with the diagnostic CE,
1145 * convert it from
1146 * Target CPU virtual address space
1147 * to
1148 * CE address space
1149 */
1150 address = ath10k_pci_targ_cpu_to_ce_addr(ar, address);
1151
1152 remaining_bytes = nbytes;
1153 while (remaining_bytes) {
1154 /* FIXME: check cast */
1155 nbytes = min_t(int, remaining_bytes, DIAG_TRANSFER_LIMIT);
1156
1157 /* Copy caller's data to allocated DMA buf */
1158 memcpy(data_buf, data, nbytes);
1159
1160 /* Set up to receive directly into Target(!) address */
1161 ret = ath10k_ce_rx_post_buf(ce_diag, &address, address);
1162 if (ret != 0)
1163 goto done;
1164
1165 /*
1166 * Request CE to send caller-supplied data that
1167 * was copied to bounce buffer to Target(!) address.
1168 */
1169 ret = ath10k_ce_send(ce_diag, NULL, ce_data_base, nbytes, 0, 0);
1170 if (ret != 0)
1171 goto done;
1172
1173 i = 0;
1174 while (ath10k_ce_completed_send_next(ce_diag, NULL) != 0) {
1175 udelay(DIAG_ACCESS_CE_WAIT_US);
1176 i += DIAG_ACCESS_CE_WAIT_US;
1177
1178 if (i > DIAG_ACCESS_CE_TIMEOUT_US) {
1179 ret = -EBUSY;
1180 goto done;
1181 }
1182 }
1183
1184 i = 0;
1185 while (ath10k_ce_completed_recv_next(ce_diag, (void **)&buf,
1186 &completed_nbytes) != 0) {
1187 udelay(DIAG_ACCESS_CE_WAIT_US);
1188 i += DIAG_ACCESS_CE_WAIT_US;
1189
1190 if (i > DIAG_ACCESS_CE_TIMEOUT_US) {
1191 ret = -EBUSY;
1192 goto done;
1193 }
1194 }
1195
1196 if (nbytes != completed_nbytes) {
1197 ret = -EIO;
1198 goto done;
1199 }
1200
1201 if (*buf != address) {
1202 ret = -EIO;
1203 goto done;
1204 }
1205
1206 remaining_bytes -= nbytes;
1207 address += nbytes;
1208 data += nbytes;
1209 }
1210
1211 done:
1212 if (data_buf) {
1213 dma_free_coherent(ar->dev, alloc_nbytes, data_buf,
1214 ce_data_base);
1215 }
1216
1217 if (ret != 0)
1218 ath10k_warn(ar, "failed to write diag value at 0x%x: %d\n",
1219 address, ret);
1220
1221 mutex_unlock(&ar_pci->ce_diag_mutex);
1222
1223 return ret;
1224 }
1225
ath10k_pci_diag_write32(struct ath10k * ar,u32 address,u32 value)1226 static int ath10k_pci_diag_write32(struct ath10k *ar, u32 address, u32 value)
1227 {
1228 __le32 val = __cpu_to_le32(value);
1229
1230 return ath10k_pci_diag_write_mem(ar, address, &val, sizeof(val));
1231 }
1232
1233 /* Called by lower (CE) layer when a send to Target completes. */
ath10k_pci_htc_tx_cb(struct ath10k_ce_pipe * ce_state)1234 static void ath10k_pci_htc_tx_cb(struct ath10k_ce_pipe *ce_state)
1235 {
1236 struct ath10k *ar = ce_state->ar;
1237 struct sk_buff_head list;
1238 struct sk_buff *skb;
1239
1240 __skb_queue_head_init(&list);
1241 while (ath10k_ce_completed_send_next(ce_state, (void **)&skb) == 0) {
1242 /* no need to call tx completion for NULL pointers */
1243 if (skb == NULL)
1244 continue;
1245
1246 __skb_queue_tail(&list, skb);
1247 }
1248
1249 while ((skb = __skb_dequeue(&list)))
1250 ath10k_htc_tx_completion_handler(ar, skb);
1251 }
1252
ath10k_pci_process_rx_cb(struct ath10k_ce_pipe * ce_state,void (* callback)(struct ath10k * ar,struct sk_buff * skb))1253 static void ath10k_pci_process_rx_cb(struct ath10k_ce_pipe *ce_state,
1254 void (*callback)(struct ath10k *ar,
1255 struct sk_buff *skb))
1256 {
1257 struct ath10k *ar = ce_state->ar;
1258 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1259 struct ath10k_pci_pipe *pipe_info = &ar_pci->pipe_info[ce_state->id];
1260 struct sk_buff *skb;
1261 struct sk_buff_head list;
1262 void *transfer_context;
1263 unsigned int nbytes, max_nbytes;
1264
1265 __skb_queue_head_init(&list);
1266 while (ath10k_ce_completed_recv_next(ce_state, &transfer_context,
1267 &nbytes) == 0) {
1268 skb = transfer_context;
1269 max_nbytes = skb->len + skb_tailroom(skb);
1270 dma_unmap_single(ar->dev, ATH10K_SKB_RXCB(skb)->paddr,
1271 max_nbytes, DMA_FROM_DEVICE);
1272
1273 if (unlikely(max_nbytes < nbytes)) {
1274 ath10k_warn(ar, "rxed more than expected (nbytes %d, max %d)",
1275 nbytes, max_nbytes);
1276 dev_kfree_skb_any(skb);
1277 continue;
1278 }
1279
1280 skb_put(skb, nbytes);
1281 __skb_queue_tail(&list, skb);
1282 }
1283
1284 while ((skb = __skb_dequeue(&list))) {
1285 ath10k_dbg(ar, ATH10K_DBG_PCI, "pci rx ce pipe %d len %d\n",
1286 ce_state->id, skb->len);
1287 ath10k_dbg_dump(ar, ATH10K_DBG_PCI_DUMP, NULL, "pci rx: ",
1288 skb->data, skb->len);
1289
1290 callback(ar, skb);
1291 }
1292
1293 ath10k_pci_rx_post_pipe(pipe_info);
1294 }
1295
ath10k_pci_process_htt_rx_cb(struct ath10k_ce_pipe * ce_state,void (* callback)(struct ath10k * ar,struct sk_buff * skb))1296 static void ath10k_pci_process_htt_rx_cb(struct ath10k_ce_pipe *ce_state,
1297 void (*callback)(struct ath10k *ar,
1298 struct sk_buff *skb))
1299 {
1300 struct ath10k *ar = ce_state->ar;
1301 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1302 struct ath10k_pci_pipe *pipe_info = &ar_pci->pipe_info[ce_state->id];
1303 struct ath10k_ce_pipe *ce_pipe = pipe_info->ce_hdl;
1304 struct sk_buff *skb;
1305 struct sk_buff_head list;
1306 void *transfer_context;
1307 unsigned int nbytes, max_nbytes, nentries;
1308 int orig_len;
1309
1310 /* No need to acquire ce_lock for CE5, since this is the only place CE5
1311 * is processed other than init and deinit. Before releasing CE5
1312 * buffers, interrupts are disabled. Thus CE5 access is serialized.
1313 */
1314 __skb_queue_head_init(&list);
1315 while (ath10k_ce_completed_recv_next_nolock(ce_state, &transfer_context,
1316 &nbytes) == 0) {
1317 skb = transfer_context;
1318 max_nbytes = skb->len + skb_tailroom(skb);
1319
1320 if (unlikely(max_nbytes < nbytes)) {
1321 ath10k_warn(ar, "rxed more than expected (nbytes %d, max %d)",
1322 nbytes, max_nbytes);
1323 continue;
1324 }
1325
1326 dma_sync_single_for_cpu(ar->dev, ATH10K_SKB_RXCB(skb)->paddr,
1327 max_nbytes, DMA_FROM_DEVICE);
1328 skb_put(skb, nbytes);
1329 __skb_queue_tail(&list, skb);
1330 }
1331
1332 nentries = skb_queue_len(&list);
1333 while ((skb = __skb_dequeue(&list))) {
1334 ath10k_dbg(ar, ATH10K_DBG_PCI, "pci rx ce pipe %d len %d\n",
1335 ce_state->id, skb->len);
1336 ath10k_dbg_dump(ar, ATH10K_DBG_PCI_DUMP, NULL, "pci rx: ",
1337 skb->data, skb->len);
1338
1339 orig_len = skb->len;
1340 callback(ar, skb);
1341 skb_push(skb, orig_len - skb->len);
1342 skb_reset_tail_pointer(skb);
1343 skb_trim(skb, 0);
1344
1345 /*let device gain the buffer again*/
1346 dma_sync_single_for_device(ar->dev, ATH10K_SKB_RXCB(skb)->paddr,
1347 skb->len + skb_tailroom(skb),
1348 DMA_FROM_DEVICE);
1349 }
1350 ath10k_ce_rx_update_write_idx(ce_pipe, nentries);
1351 }
1352
1353 /* Called by lower (CE) layer when data is received from the Target. */
ath10k_pci_htc_rx_cb(struct ath10k_ce_pipe * ce_state)1354 static void ath10k_pci_htc_rx_cb(struct ath10k_ce_pipe *ce_state)
1355 {
1356 ath10k_pci_process_rx_cb(ce_state, ath10k_htc_rx_completion_handler);
1357 }
1358
ath10k_pci_htt_htc_rx_cb(struct ath10k_ce_pipe * ce_state)1359 static void ath10k_pci_htt_htc_rx_cb(struct ath10k_ce_pipe *ce_state)
1360 {
1361 /* CE4 polling needs to be done whenever CE pipe which transports
1362 * HTT Rx (target->host) is processed.
1363 */
1364 ath10k_ce_per_engine_service(ce_state->ar, 4);
1365
1366 ath10k_pci_process_rx_cb(ce_state, ath10k_htc_rx_completion_handler);
1367 }
1368
1369 /* Called by lower (CE) layer when data is received from the Target.
1370 * Only 10.4 firmware uses separate CE to transfer pktlog data.
1371 */
ath10k_pci_pktlog_rx_cb(struct ath10k_ce_pipe * ce_state)1372 static void ath10k_pci_pktlog_rx_cb(struct ath10k_ce_pipe *ce_state)
1373 {
1374 ath10k_pci_process_rx_cb(ce_state,
1375 ath10k_htt_rx_pktlog_completion_handler);
1376 }
1377
1378 /* Called by lower (CE) layer when a send to HTT Target completes. */
ath10k_pci_htt_tx_cb(struct ath10k_ce_pipe * ce_state)1379 static void ath10k_pci_htt_tx_cb(struct ath10k_ce_pipe *ce_state)
1380 {
1381 struct ath10k *ar = ce_state->ar;
1382 struct sk_buff *skb;
1383
1384 while (ath10k_ce_completed_send_next(ce_state, (void **)&skb) == 0) {
1385 /* no need to call tx completion for NULL pointers */
1386 if (!skb)
1387 continue;
1388
1389 dma_unmap_single(ar->dev, ATH10K_SKB_CB(skb)->paddr,
1390 skb->len, DMA_TO_DEVICE);
1391 ath10k_htt_hif_tx_complete(ar, skb);
1392 }
1393 }
1394
ath10k_pci_htt_rx_deliver(struct ath10k * ar,struct sk_buff * skb)1395 static void ath10k_pci_htt_rx_deliver(struct ath10k *ar, struct sk_buff *skb)
1396 {
1397 skb_pull(skb, sizeof(struct ath10k_htc_hdr));
1398 ath10k_htt_t2h_msg_handler(ar, skb);
1399 }
1400
1401 /* Called by lower (CE) layer when HTT data is received from the Target. */
ath10k_pci_htt_rx_cb(struct ath10k_ce_pipe * ce_state)1402 static void ath10k_pci_htt_rx_cb(struct ath10k_ce_pipe *ce_state)
1403 {
1404 /* CE4 polling needs to be done whenever CE pipe which transports
1405 * HTT Rx (target->host) is processed.
1406 */
1407 ath10k_ce_per_engine_service(ce_state->ar, 4);
1408
1409 ath10k_pci_process_htt_rx_cb(ce_state, ath10k_pci_htt_rx_deliver);
1410 }
1411
ath10k_pci_hif_tx_sg(struct ath10k * ar,u8 pipe_id,struct ath10k_hif_sg_item * items,int n_items)1412 int ath10k_pci_hif_tx_sg(struct ath10k *ar, u8 pipe_id,
1413 struct ath10k_hif_sg_item *items, int n_items)
1414 {
1415 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1416 struct ath10k_ce *ce = ath10k_ce_priv(ar);
1417 struct ath10k_pci_pipe *pci_pipe = &ar_pci->pipe_info[pipe_id];
1418 struct ath10k_ce_pipe *ce_pipe = pci_pipe->ce_hdl;
1419 struct ath10k_ce_ring *src_ring = ce_pipe->src_ring;
1420 unsigned int nentries_mask;
1421 unsigned int sw_index;
1422 unsigned int write_index;
1423 int err, i = 0;
1424
1425 spin_lock_bh(&ce->ce_lock);
1426
1427 nentries_mask = src_ring->nentries_mask;
1428 sw_index = src_ring->sw_index;
1429 write_index = src_ring->write_index;
1430
1431 if (unlikely(CE_RING_DELTA(nentries_mask,
1432 write_index, sw_index - 1) < n_items)) {
1433 err = -ENOBUFS;
1434 goto err;
1435 }
1436
1437 for (i = 0; i < n_items - 1; i++) {
1438 ath10k_dbg(ar, ATH10K_DBG_PCI,
1439 "pci tx item %d paddr %pad len %d n_items %d\n",
1440 i, &items[i].paddr, items[i].len, n_items);
1441 ath10k_dbg_dump(ar, ATH10K_DBG_PCI_DUMP, NULL, "pci tx data: ",
1442 items[i].vaddr, items[i].len);
1443
1444 err = ath10k_ce_send_nolock(ce_pipe,
1445 items[i].transfer_context,
1446 items[i].paddr,
1447 items[i].len,
1448 items[i].transfer_id,
1449 CE_SEND_FLAG_GATHER);
1450 if (err)
1451 goto err;
1452 }
1453
1454 /* `i` is equal to `n_items -1` after for() */
1455
1456 ath10k_dbg(ar, ATH10K_DBG_PCI,
1457 #if defined(__linux__)
1458 "pci tx item %d paddr %pad len %d n_items %d\n",
1459 i, &items[i].paddr, items[i].len, n_items);
1460 #elif defined(__FreeBSD__)
1461 "pci tx item %d paddr %pad len %d n_items %d pipe_id %u\n",
1462 i, &items[i].paddr, items[i].len, n_items, pipe_id);
1463 #endif
1464 ath10k_dbg_dump(ar, ATH10K_DBG_PCI_DUMP, NULL, "pci tx data: ",
1465 items[i].vaddr, items[i].len);
1466
1467 err = ath10k_ce_send_nolock(ce_pipe,
1468 items[i].transfer_context,
1469 items[i].paddr,
1470 items[i].len,
1471 items[i].transfer_id,
1472 0);
1473 if (err)
1474 goto err;
1475
1476 spin_unlock_bh(&ce->ce_lock);
1477 return 0;
1478
1479 err:
1480 for (; i > 0; i--)
1481 __ath10k_ce_send_revert(ce_pipe);
1482
1483 spin_unlock_bh(&ce->ce_lock);
1484 return err;
1485 }
1486
ath10k_pci_hif_diag_read(struct ath10k * ar,u32 address,void * buf,size_t buf_len)1487 int ath10k_pci_hif_diag_read(struct ath10k *ar, u32 address, void *buf,
1488 size_t buf_len)
1489 {
1490 return ath10k_pci_diag_read_mem(ar, address, buf, buf_len);
1491 }
1492
ath10k_pci_hif_get_free_queue_number(struct ath10k * ar,u8 pipe)1493 u16 ath10k_pci_hif_get_free_queue_number(struct ath10k *ar, u8 pipe)
1494 {
1495 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1496
1497 ath10k_dbg(ar, ATH10K_DBG_PCI, "pci hif get free queue number\n");
1498
1499 return ath10k_ce_num_free_src_entries(ar_pci->pipe_info[pipe].ce_hdl);
1500 }
1501
ath10k_pci_dump_registers(struct ath10k * ar,struct ath10k_fw_crash_data * crash_data)1502 static void ath10k_pci_dump_registers(struct ath10k *ar,
1503 struct ath10k_fw_crash_data *crash_data)
1504 {
1505 __le32 reg_dump_values[REG_DUMP_COUNT_QCA988X] = {};
1506 int i, ret;
1507
1508 lockdep_assert_held(&ar->dump_mutex);
1509
1510 ret = ath10k_pci_diag_read_hi(ar, ®_dump_values[0],
1511 hi_failure_state,
1512 REG_DUMP_COUNT_QCA988X * sizeof(__le32));
1513 if (ret) {
1514 ath10k_err(ar, "failed to read firmware dump area: %d\n", ret);
1515 return;
1516 }
1517
1518 BUILD_BUG_ON(REG_DUMP_COUNT_QCA988X % 4);
1519
1520 ath10k_err(ar, "firmware register dump:\n");
1521 for (i = 0; i < REG_DUMP_COUNT_QCA988X; i += 4)
1522 ath10k_err(ar, "[%02d]: 0x%08X 0x%08X 0x%08X 0x%08X\n",
1523 i,
1524 __le32_to_cpu(reg_dump_values[i]),
1525 __le32_to_cpu(reg_dump_values[i + 1]),
1526 __le32_to_cpu(reg_dump_values[i + 2]),
1527 __le32_to_cpu(reg_dump_values[i + 3]));
1528
1529 if (!crash_data)
1530 return;
1531
1532 for (i = 0; i < REG_DUMP_COUNT_QCA988X; i++)
1533 crash_data->registers[i] = reg_dump_values[i];
1534 }
1535
ath10k_pci_dump_memory_section(struct ath10k * ar,const struct ath10k_mem_region * mem_region,u8 * buf,size_t buf_len)1536 static int ath10k_pci_dump_memory_section(struct ath10k *ar,
1537 const struct ath10k_mem_region *mem_region,
1538 u8 *buf, size_t buf_len)
1539 {
1540 const struct ath10k_mem_section *cur_section, *next_section;
1541 unsigned int count, section_size, skip_size;
1542 int ret, i, j;
1543
1544 if (!mem_region || !buf)
1545 return 0;
1546
1547 cur_section = &mem_region->section_table.sections[0];
1548
1549 if (mem_region->start > cur_section->start) {
1550 ath10k_warn(ar, "incorrect memdump region 0x%x with section start address 0x%x.\n",
1551 mem_region->start, cur_section->start);
1552 return 0;
1553 }
1554
1555 skip_size = cur_section->start - mem_region->start;
1556
1557 /* fill the gap between the first register section and register
1558 * start address
1559 */
1560 for (i = 0; i < skip_size; i++) {
1561 *buf = ATH10K_MAGIC_NOT_COPIED;
1562 buf++;
1563 }
1564
1565 count = 0;
1566
1567 for (i = 0; cur_section != NULL; i++) {
1568 section_size = cur_section->end - cur_section->start;
1569
1570 if (section_size <= 0) {
1571 ath10k_warn(ar, "incorrect ramdump format with start address 0x%x and stop address 0x%x\n",
1572 cur_section->start,
1573 cur_section->end);
1574 break;
1575 }
1576
1577 if ((i + 1) == mem_region->section_table.size) {
1578 /* last section */
1579 next_section = NULL;
1580 skip_size = 0;
1581 } else {
1582 next_section = cur_section + 1;
1583
1584 if (cur_section->end > next_section->start) {
1585 ath10k_warn(ar, "next ramdump section 0x%x is smaller than current end address 0x%x\n",
1586 next_section->start,
1587 cur_section->end);
1588 break;
1589 }
1590
1591 skip_size = next_section->start - cur_section->end;
1592 }
1593
1594 if (buf_len < (skip_size + section_size)) {
1595 ath10k_warn(ar, "ramdump buffer is too small: %zu\n", buf_len);
1596 break;
1597 }
1598
1599 buf_len -= skip_size + section_size;
1600
1601 /* read section to dest memory */
1602 ret = ath10k_pci_diag_read_mem(ar, cur_section->start,
1603 buf, section_size);
1604 if (ret) {
1605 ath10k_warn(ar, "failed to read ramdump from section 0x%x: %d\n",
1606 cur_section->start, ret);
1607 break;
1608 }
1609
1610 buf += section_size;
1611 count += section_size;
1612
1613 /* fill in the gap between this section and the next */
1614 for (j = 0; j < skip_size; j++) {
1615 *buf = ATH10K_MAGIC_NOT_COPIED;
1616 buf++;
1617 }
1618
1619 count += skip_size;
1620
1621 if (!next_section)
1622 /* this was the last section */
1623 break;
1624
1625 cur_section = next_section;
1626 }
1627
1628 return count;
1629 }
1630
ath10k_pci_set_ram_config(struct ath10k * ar,u32 config)1631 static int ath10k_pci_set_ram_config(struct ath10k *ar, u32 config)
1632 {
1633 u32 val;
1634
1635 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS +
1636 FW_RAM_CONFIG_ADDRESS, config);
1637
1638 val = ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS +
1639 FW_RAM_CONFIG_ADDRESS);
1640 if (val != config) {
1641 ath10k_warn(ar, "failed to set RAM config from 0x%x to 0x%x\n",
1642 val, config);
1643 return -EIO;
1644 }
1645
1646 return 0;
1647 }
1648
1649 /* Always returns the length */
ath10k_pci_dump_memory_sram(struct ath10k * ar,const struct ath10k_mem_region * region,u8 * buf)1650 static int ath10k_pci_dump_memory_sram(struct ath10k *ar,
1651 const struct ath10k_mem_region *region,
1652 u8 *buf)
1653 {
1654 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1655 u32 base_addr, i;
1656
1657 #if defined(__linux__)
1658 base_addr = ioread32(ar_pci->mem + QCA99X0_PCIE_BAR0_START_REG);
1659 #elif defined(__FreeBSD__)
1660 base_addr = bus_read_4((struct resource *)ar_pci->mem, QCA99X0_PCIE_BAR0_START_REG);
1661 #endif
1662 base_addr += region->start;
1663
1664 for (i = 0; i < region->len; i += 4) {
1665 #if defined(__linux__)
1666 iowrite32(base_addr + i, ar_pci->mem + QCA99X0_CPU_MEM_ADDR_REG);
1667 *(u32 *)(buf + i) = ioread32(ar_pci->mem + QCA99X0_CPU_MEM_DATA_REG);
1668 #elif defined(__FreeBSD__)
1669 bus_write_4((struct resource *)ar_pci->mem, QCA99X0_CPU_MEM_ADDR_REG, base_addr + i);
1670 *(u32 *)(buf + i) = bus_read_4((struct resource *)ar_pci->mem, QCA99X0_CPU_MEM_DATA_REG);
1671 #endif
1672 }
1673
1674 return region->len;
1675 }
1676
1677 /* if an error happened returns < 0, otherwise the length */
ath10k_pci_dump_memory_reg(struct ath10k * ar,const struct ath10k_mem_region * region,u8 * buf)1678 static int ath10k_pci_dump_memory_reg(struct ath10k *ar,
1679 const struct ath10k_mem_region *region,
1680 u8 *buf)
1681 {
1682 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1683 u32 i;
1684 int ret;
1685
1686 mutex_lock(&ar->conf_mutex);
1687 if (ar->state != ATH10K_STATE_ON) {
1688 ath10k_warn(ar, "Skipping pci_dump_memory_reg invalid state\n");
1689 ret = -EIO;
1690 goto done;
1691 }
1692
1693 for (i = 0; i < region->len; i += 4)
1694 #if defined(__linux__)
1695 *(u32 *)(buf + i) = ioread32(ar_pci->mem + region->start + i);
1696 #elif defined(__FreeBSD__)
1697 *(u32 *)(buf + i) = bus_read_4((struct resource *)ar_pci->mem, region->start + i);
1698 #endif
1699
1700 ret = region->len;
1701 done:
1702 mutex_unlock(&ar->conf_mutex);
1703 return ret;
1704 }
1705
1706 /* if an error happened returns < 0, otherwise the length */
ath10k_pci_dump_memory_generic(struct ath10k * ar,const struct ath10k_mem_region * current_region,u8 * buf)1707 static int ath10k_pci_dump_memory_generic(struct ath10k *ar,
1708 const struct ath10k_mem_region *current_region,
1709 u8 *buf)
1710 {
1711 int ret;
1712
1713 if (current_region->section_table.size > 0)
1714 /* Copy each section individually. */
1715 return ath10k_pci_dump_memory_section(ar,
1716 current_region,
1717 buf,
1718 current_region->len);
1719
1720 /* No individual memory sections defined so we can
1721 * copy the entire memory region.
1722 */
1723 ret = ath10k_pci_diag_read_mem(ar,
1724 current_region->start,
1725 buf,
1726 current_region->len);
1727 if (ret) {
1728 ath10k_warn(ar, "failed to copy ramdump region %s: %d\n",
1729 current_region->name, ret);
1730 return ret;
1731 }
1732
1733 return current_region->len;
1734 }
1735
ath10k_pci_dump_memory(struct ath10k * ar,struct ath10k_fw_crash_data * crash_data)1736 static void ath10k_pci_dump_memory(struct ath10k *ar,
1737 struct ath10k_fw_crash_data *crash_data)
1738 {
1739 const struct ath10k_hw_mem_layout *mem_layout;
1740 const struct ath10k_mem_region *current_region;
1741 struct ath10k_dump_ram_data_hdr *hdr;
1742 u32 count, shift;
1743 size_t buf_len;
1744 int ret, i;
1745 u8 *buf;
1746
1747 lockdep_assert_held(&ar->dump_mutex);
1748
1749 if (!crash_data)
1750 return;
1751
1752 mem_layout = ath10k_coredump_get_mem_layout(ar);
1753 if (!mem_layout)
1754 return;
1755
1756 current_region = &mem_layout->region_table.regions[0];
1757
1758 buf = crash_data->ramdump_buf;
1759 buf_len = crash_data->ramdump_buf_len;
1760
1761 memset(buf, 0, buf_len);
1762
1763 for (i = 0; i < mem_layout->region_table.size; i++) {
1764 count = 0;
1765
1766 if (current_region->len > buf_len) {
1767 ath10k_warn(ar, "memory region %s size %d is larger that remaining ramdump buffer size %zu\n",
1768 current_region->name,
1769 current_region->len,
1770 buf_len);
1771 break;
1772 }
1773
1774 /* To get IRAM dump, the host driver needs to switch target
1775 * ram config from DRAM to IRAM.
1776 */
1777 if (current_region->type == ATH10K_MEM_REGION_TYPE_IRAM1 ||
1778 current_region->type == ATH10K_MEM_REGION_TYPE_IRAM2) {
1779 shift = current_region->start >> 20;
1780
1781 ret = ath10k_pci_set_ram_config(ar, shift);
1782 if (ret) {
1783 ath10k_warn(ar, "failed to switch ram config to IRAM for section %s: %d\n",
1784 current_region->name, ret);
1785 break;
1786 }
1787 }
1788
1789 /* Reserve space for the header. */
1790 hdr = (void *)buf;
1791 buf += sizeof(*hdr);
1792 buf_len -= sizeof(*hdr);
1793
1794 switch (current_region->type) {
1795 case ATH10K_MEM_REGION_TYPE_IOSRAM:
1796 count = ath10k_pci_dump_memory_sram(ar, current_region, buf);
1797 break;
1798 case ATH10K_MEM_REGION_TYPE_IOREG:
1799 ret = ath10k_pci_dump_memory_reg(ar, current_region, buf);
1800 if (ret < 0)
1801 break;
1802
1803 count = ret;
1804 break;
1805 default:
1806 ret = ath10k_pci_dump_memory_generic(ar, current_region, buf);
1807 if (ret < 0)
1808 break;
1809
1810 count = ret;
1811 break;
1812 }
1813
1814 hdr->region_type = cpu_to_le32(current_region->type);
1815 hdr->start = cpu_to_le32(current_region->start);
1816 hdr->length = cpu_to_le32(count);
1817
1818 if (count == 0)
1819 /* Note: the header remains, just with zero length. */
1820 break;
1821
1822 buf += count;
1823 buf_len -= count;
1824
1825 current_region++;
1826 }
1827 }
1828
ath10k_pci_fw_dump_work(struct work_struct * work)1829 static void ath10k_pci_fw_dump_work(struct work_struct *work)
1830 {
1831 struct ath10k_pci *ar_pci = container_of(work, struct ath10k_pci,
1832 dump_work);
1833 struct ath10k_fw_crash_data *crash_data;
1834 struct ath10k *ar = ar_pci->ar;
1835 char guid[UUID_STRING_LEN + 1];
1836
1837 mutex_lock(&ar->dump_mutex);
1838
1839 spin_lock_bh(&ar->data_lock);
1840 ar->stats.fw_crash_counter++;
1841 spin_unlock_bh(&ar->data_lock);
1842
1843 crash_data = ath10k_coredump_new(ar);
1844
1845 if (crash_data)
1846 scnprintf(guid, sizeof(guid), "%pUl", &crash_data->guid);
1847 else
1848 scnprintf(guid, sizeof(guid), "n/a");
1849
1850 ath10k_err(ar, "firmware crashed! (guid %s)\n", guid);
1851 ath10k_print_driver_info(ar);
1852 ath10k_pci_dump_registers(ar, crash_data);
1853 ath10k_ce_dump_registers(ar, crash_data);
1854 ath10k_pci_dump_memory(ar, crash_data);
1855
1856 mutex_unlock(&ar->dump_mutex);
1857
1858 ath10k_core_start_recovery(ar);
1859 }
1860
ath10k_pci_fw_crashed_dump(struct ath10k * ar)1861 static void ath10k_pci_fw_crashed_dump(struct ath10k *ar)
1862 {
1863 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1864
1865 queue_work(ar->workqueue, &ar_pci->dump_work);
1866 }
1867
ath10k_pci_hif_send_complete_check(struct ath10k * ar,u8 pipe,int force)1868 void ath10k_pci_hif_send_complete_check(struct ath10k *ar, u8 pipe,
1869 int force)
1870 {
1871 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1872
1873 ath10k_dbg(ar, ATH10K_DBG_PCI, "pci hif send complete check\n");
1874
1875 if (!force) {
1876 int resources;
1877 /*
1878 * Decide whether to actually poll for completions, or just
1879 * wait for a later chance.
1880 * If there seem to be plenty of resources left, then just wait
1881 * since checking involves reading a CE register, which is a
1882 * relatively expensive operation.
1883 */
1884 resources = ath10k_pci_hif_get_free_queue_number(ar, pipe);
1885
1886 /*
1887 * If at least 50% of the total resources are still available,
1888 * don't bother checking again yet.
1889 */
1890 if (resources > (ar_pci->attr[pipe].src_nentries >> 1))
1891 return;
1892 }
1893 ath10k_ce_per_engine_service(ar, pipe);
1894 }
1895
ath10k_pci_rx_retry_sync(struct ath10k * ar)1896 static void ath10k_pci_rx_retry_sync(struct ath10k *ar)
1897 {
1898 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1899
1900 timer_delete_sync(&ar_pci->rx_post_retry);
1901 }
1902
ath10k_pci_hif_map_service_to_pipe(struct ath10k * ar,u16 service_id,u8 * ul_pipe,u8 * dl_pipe)1903 int ath10k_pci_hif_map_service_to_pipe(struct ath10k *ar, u16 service_id,
1904 u8 *ul_pipe, u8 *dl_pipe)
1905 {
1906 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1907 const struct ce_service_to_pipe *entry;
1908 bool ul_set = false, dl_set = false;
1909 int i;
1910
1911 ath10k_dbg(ar, ATH10K_DBG_PCI, "pci hif map service\n");
1912
1913 for (i = 0; i < ARRAY_SIZE(pci_target_service_to_ce_map_wlan); i++) {
1914 entry = &ar_pci->serv_to_pipe[i];
1915
1916 if (__le32_to_cpu(entry->service_id) != service_id)
1917 continue;
1918
1919 switch (__le32_to_cpu(entry->pipedir)) {
1920 case PIPEDIR_NONE:
1921 break;
1922 case PIPEDIR_IN:
1923 WARN_ON(dl_set);
1924 *dl_pipe = __le32_to_cpu(entry->pipenum);
1925 dl_set = true;
1926 break;
1927 case PIPEDIR_OUT:
1928 WARN_ON(ul_set);
1929 *ul_pipe = __le32_to_cpu(entry->pipenum);
1930 ul_set = true;
1931 break;
1932 case PIPEDIR_INOUT:
1933 WARN_ON(dl_set);
1934 WARN_ON(ul_set);
1935 *dl_pipe = __le32_to_cpu(entry->pipenum);
1936 *ul_pipe = __le32_to_cpu(entry->pipenum);
1937 dl_set = true;
1938 ul_set = true;
1939 break;
1940 }
1941 }
1942
1943 if (!ul_set || !dl_set)
1944 return -ENOENT;
1945
1946 return 0;
1947 }
1948
ath10k_pci_hif_get_default_pipe(struct ath10k * ar,u8 * ul_pipe,u8 * dl_pipe)1949 void ath10k_pci_hif_get_default_pipe(struct ath10k *ar,
1950 u8 *ul_pipe, u8 *dl_pipe)
1951 {
1952 ath10k_dbg(ar, ATH10K_DBG_PCI, "pci hif get default pipe\n");
1953
1954 (void)ath10k_pci_hif_map_service_to_pipe(ar,
1955 ATH10K_HTC_SVC_ID_RSVD_CTRL,
1956 ul_pipe, dl_pipe);
1957 }
1958
ath10k_pci_irq_msi_fw_mask(struct ath10k * ar)1959 void ath10k_pci_irq_msi_fw_mask(struct ath10k *ar)
1960 {
1961 u32 val;
1962
1963 switch (ar->hw_rev) {
1964 case ATH10K_HW_QCA988X:
1965 case ATH10K_HW_QCA9887:
1966 case ATH10K_HW_QCA6174:
1967 case ATH10K_HW_QCA9377:
1968 val = ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS +
1969 CORE_CTRL_ADDRESS);
1970 val &= ~CORE_CTRL_PCIE_REG_31_MASK;
1971 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS +
1972 CORE_CTRL_ADDRESS, val);
1973 break;
1974 case ATH10K_HW_QCA99X0:
1975 case ATH10K_HW_QCA9984:
1976 case ATH10K_HW_QCA9888:
1977 case ATH10K_HW_QCA4019:
1978 /* TODO: Find appropriate register configuration for QCA99X0
1979 * to mask irq/MSI.
1980 */
1981 break;
1982 case ATH10K_HW_WCN3990:
1983 break;
1984 }
1985 }
1986
ath10k_pci_irq_msi_fw_unmask(struct ath10k * ar)1987 static void ath10k_pci_irq_msi_fw_unmask(struct ath10k *ar)
1988 {
1989 u32 val;
1990
1991 switch (ar->hw_rev) {
1992 case ATH10K_HW_QCA988X:
1993 case ATH10K_HW_QCA9887:
1994 case ATH10K_HW_QCA6174:
1995 case ATH10K_HW_QCA9377:
1996 val = ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS +
1997 CORE_CTRL_ADDRESS);
1998 val |= CORE_CTRL_PCIE_REG_31_MASK;
1999 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS +
2000 CORE_CTRL_ADDRESS, val);
2001 break;
2002 case ATH10K_HW_QCA99X0:
2003 case ATH10K_HW_QCA9984:
2004 case ATH10K_HW_QCA9888:
2005 case ATH10K_HW_QCA4019:
2006 /* TODO: Find appropriate register configuration for QCA99X0
2007 * to unmask irq/MSI.
2008 */
2009 break;
2010 case ATH10K_HW_WCN3990:
2011 break;
2012 }
2013 }
2014
ath10k_pci_irq_disable(struct ath10k * ar)2015 static void ath10k_pci_irq_disable(struct ath10k *ar)
2016 {
2017 ath10k_ce_disable_interrupts(ar);
2018 ath10k_pci_disable_and_clear_intx_irq(ar);
2019 ath10k_pci_irq_msi_fw_mask(ar);
2020 }
2021
ath10k_pci_irq_sync(struct ath10k * ar)2022 static void ath10k_pci_irq_sync(struct ath10k *ar)
2023 {
2024 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2025
2026 synchronize_irq(ar_pci->pdev->irq);
2027 }
2028
ath10k_pci_irq_enable(struct ath10k * ar)2029 static void ath10k_pci_irq_enable(struct ath10k *ar)
2030 {
2031 ath10k_ce_enable_interrupts(ar);
2032 ath10k_pci_enable_intx_irq(ar);
2033 ath10k_pci_irq_msi_fw_unmask(ar);
2034 }
2035
ath10k_pci_hif_start(struct ath10k * ar)2036 static int ath10k_pci_hif_start(struct ath10k *ar)
2037 {
2038 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2039
2040 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot hif start\n");
2041
2042 ath10k_core_napi_enable(ar);
2043
2044 ath10k_pci_irq_enable(ar);
2045 ath10k_pci_rx_post(ar);
2046
2047 pcie_capability_clear_and_set_word(ar_pci->pdev, PCI_EXP_LNKCTL,
2048 PCI_EXP_LNKCTL_ASPMC,
2049 ar_pci->link_ctl & PCI_EXP_LNKCTL_ASPMC);
2050
2051 return 0;
2052 }
2053
ath10k_pci_rx_pipe_cleanup(struct ath10k_pci_pipe * pci_pipe)2054 static void ath10k_pci_rx_pipe_cleanup(struct ath10k_pci_pipe *pci_pipe)
2055 {
2056 struct ath10k *ar;
2057 struct ath10k_ce_pipe *ce_pipe;
2058 struct ath10k_ce_ring *ce_ring;
2059 struct sk_buff *skb;
2060 int i;
2061
2062 ar = pci_pipe->hif_ce_state;
2063 ce_pipe = pci_pipe->ce_hdl;
2064 ce_ring = ce_pipe->dest_ring;
2065
2066 if (!ce_ring)
2067 return;
2068
2069 if (!pci_pipe->buf_sz)
2070 return;
2071
2072 for (i = 0; i < ce_ring->nentries; i++) {
2073 skb = ce_ring->per_transfer_context[i];
2074 if (!skb)
2075 continue;
2076
2077 ce_ring->per_transfer_context[i] = NULL;
2078
2079 dma_unmap_single(ar->dev, ATH10K_SKB_RXCB(skb)->paddr,
2080 skb->len + skb_tailroom(skb),
2081 DMA_FROM_DEVICE);
2082 dev_kfree_skb_any(skb);
2083 }
2084 }
2085
ath10k_pci_tx_pipe_cleanup(struct ath10k_pci_pipe * pci_pipe)2086 static void ath10k_pci_tx_pipe_cleanup(struct ath10k_pci_pipe *pci_pipe)
2087 {
2088 struct ath10k *ar;
2089 struct ath10k_ce_pipe *ce_pipe;
2090 struct ath10k_ce_ring *ce_ring;
2091 struct sk_buff *skb;
2092 int i;
2093
2094 ar = pci_pipe->hif_ce_state;
2095 ce_pipe = pci_pipe->ce_hdl;
2096 ce_ring = ce_pipe->src_ring;
2097
2098 if (!ce_ring)
2099 return;
2100
2101 if (!pci_pipe->buf_sz)
2102 return;
2103
2104 for (i = 0; i < ce_ring->nentries; i++) {
2105 skb = ce_ring->per_transfer_context[i];
2106 if (!skb)
2107 continue;
2108
2109 ce_ring->per_transfer_context[i] = NULL;
2110
2111 ath10k_htc_tx_completion_handler(ar, skb);
2112 }
2113 }
2114
2115 /*
2116 * Cleanup residual buffers for device shutdown:
2117 * buffers that were enqueued for receive
2118 * buffers that were to be sent
2119 * Note: Buffers that had completed but which were
2120 * not yet processed are on a completion queue. They
2121 * are handled when the completion thread shuts down.
2122 */
ath10k_pci_buffer_cleanup(struct ath10k * ar)2123 static void ath10k_pci_buffer_cleanup(struct ath10k *ar)
2124 {
2125 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2126 int pipe_num;
2127
2128 for (pipe_num = 0; pipe_num < CE_COUNT; pipe_num++) {
2129 struct ath10k_pci_pipe *pipe_info;
2130
2131 pipe_info = &ar_pci->pipe_info[pipe_num];
2132 ath10k_pci_rx_pipe_cleanup(pipe_info);
2133 ath10k_pci_tx_pipe_cleanup(pipe_info);
2134 }
2135 }
2136
ath10k_pci_ce_deinit(struct ath10k * ar)2137 void ath10k_pci_ce_deinit(struct ath10k *ar)
2138 {
2139 int i;
2140
2141 for (i = 0; i < CE_COUNT; i++)
2142 ath10k_ce_deinit_pipe(ar, i);
2143 }
2144
ath10k_pci_flush(struct ath10k * ar)2145 void ath10k_pci_flush(struct ath10k *ar)
2146 {
2147 ath10k_pci_rx_retry_sync(ar);
2148 ath10k_pci_buffer_cleanup(ar);
2149 }
2150
ath10k_pci_hif_stop(struct ath10k * ar)2151 static void ath10k_pci_hif_stop(struct ath10k *ar)
2152 {
2153 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2154 unsigned long flags;
2155
2156 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot hif stop\n");
2157
2158 ath10k_pci_irq_disable(ar);
2159 ath10k_pci_irq_sync(ar);
2160
2161 ath10k_core_napi_sync_disable(ar);
2162
2163 cancel_work_sync(&ar_pci->dump_work);
2164
2165 /* Most likely the device has HTT Rx ring configured. The only way to
2166 * prevent the device from accessing (and possible corrupting) host
2167 * memory is to reset the chip now.
2168 *
2169 * There's also no known way of masking MSI interrupts on the device.
2170 * For ranged MSI the CE-related interrupts can be masked. However
2171 * regardless how many MSI interrupts are assigned the first one
2172 * is always used for firmware indications (crashes) and cannot be
2173 * masked. To prevent the device from asserting the interrupt reset it
2174 * before proceeding with cleanup.
2175 */
2176 ath10k_pci_safe_chip_reset(ar);
2177
2178 ath10k_pci_flush(ar);
2179
2180 spin_lock_irqsave(&ar_pci->ps_lock, flags);
2181 WARN_ON(ar_pci->ps_wake_refcount > 0);
2182 spin_unlock_irqrestore(&ar_pci->ps_lock, flags);
2183 }
2184
ath10k_pci_hif_exchange_bmi_msg(struct ath10k * ar,void * req,u32 req_len,void * resp,u32 * resp_len)2185 int ath10k_pci_hif_exchange_bmi_msg(struct ath10k *ar,
2186 void *req, u32 req_len,
2187 void *resp, u32 *resp_len)
2188 {
2189 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2190 struct ath10k_pci_pipe *pci_tx = &ar_pci->pipe_info[BMI_CE_NUM_TO_TARG];
2191 struct ath10k_pci_pipe *pci_rx = &ar_pci->pipe_info[BMI_CE_NUM_TO_HOST];
2192 struct ath10k_ce_pipe *ce_tx = pci_tx->ce_hdl;
2193 struct ath10k_ce_pipe *ce_rx = pci_rx->ce_hdl;
2194 dma_addr_t req_paddr = 0;
2195 dma_addr_t resp_paddr = 0;
2196 struct bmi_xfer xfer = {};
2197 void *treq, *tresp = NULL;
2198 int ret = 0;
2199
2200 might_sleep();
2201
2202 if (resp && !resp_len)
2203 return -EINVAL;
2204
2205 if (resp && resp_len && *resp_len == 0)
2206 return -EINVAL;
2207
2208 treq = kmemdup(req, req_len, GFP_KERNEL);
2209 if (!treq)
2210 return -ENOMEM;
2211
2212 req_paddr = dma_map_single(ar->dev, treq, req_len, DMA_TO_DEVICE);
2213 ret = dma_mapping_error(ar->dev, req_paddr);
2214 if (ret) {
2215 ret = -EIO;
2216 goto err_dma;
2217 }
2218
2219 if (resp && resp_len) {
2220 tresp = kzalloc(*resp_len, GFP_KERNEL);
2221 if (!tresp) {
2222 ret = -ENOMEM;
2223 goto err_req;
2224 }
2225
2226 resp_paddr = dma_map_single(ar->dev, tresp, *resp_len,
2227 DMA_FROM_DEVICE);
2228 ret = dma_mapping_error(ar->dev, resp_paddr);
2229 if (ret) {
2230 ret = -EIO;
2231 goto err_req;
2232 }
2233
2234 xfer.wait_for_resp = true;
2235 xfer.resp_len = 0;
2236
2237 ath10k_ce_rx_post_buf(ce_rx, &xfer, resp_paddr);
2238 }
2239
2240 ret = ath10k_ce_send(ce_tx, &xfer, req_paddr, req_len, -1, 0);
2241 if (ret)
2242 goto err_resp;
2243
2244 ret = ath10k_pci_bmi_wait(ar, ce_tx, ce_rx, &xfer);
2245 if (ret) {
2246 dma_addr_t unused_buffer;
2247 unsigned int unused_nbytes;
2248 unsigned int unused_id;
2249
2250 ath10k_ce_cancel_send_next(ce_tx, NULL, &unused_buffer,
2251 &unused_nbytes, &unused_id);
2252 } else {
2253 /* non-zero means we did not time out */
2254 ret = 0;
2255 }
2256
2257 err_resp:
2258 if (resp) {
2259 dma_addr_t unused_buffer;
2260
2261 ath10k_ce_revoke_recv_next(ce_rx, NULL, &unused_buffer);
2262 dma_unmap_single(ar->dev, resp_paddr,
2263 *resp_len, DMA_FROM_DEVICE);
2264 }
2265 err_req:
2266 dma_unmap_single(ar->dev, req_paddr, req_len, DMA_TO_DEVICE);
2267
2268 if (ret == 0 && resp_len) {
2269 *resp_len = min(*resp_len, xfer.resp_len);
2270 memcpy(resp, tresp, *resp_len);
2271 }
2272 err_dma:
2273 kfree(treq);
2274 kfree(tresp);
2275
2276 return ret;
2277 }
2278
ath10k_pci_bmi_send_done(struct ath10k_ce_pipe * ce_state)2279 static void ath10k_pci_bmi_send_done(struct ath10k_ce_pipe *ce_state)
2280 {
2281 struct bmi_xfer *xfer;
2282
2283 if (ath10k_ce_completed_send_next(ce_state, (void **)&xfer))
2284 return;
2285
2286 xfer->tx_done = true;
2287 }
2288
ath10k_pci_bmi_recv_data(struct ath10k_ce_pipe * ce_state)2289 static void ath10k_pci_bmi_recv_data(struct ath10k_ce_pipe *ce_state)
2290 {
2291 struct ath10k *ar = ce_state->ar;
2292 struct bmi_xfer *xfer;
2293 unsigned int nbytes;
2294
2295 if (ath10k_ce_completed_recv_next(ce_state, (void **)&xfer,
2296 &nbytes))
2297 return;
2298
2299 if (WARN_ON_ONCE(!xfer))
2300 return;
2301
2302 if (!xfer->wait_for_resp) {
2303 ath10k_warn(ar, "unexpected: BMI data received; ignoring\n");
2304 return;
2305 }
2306
2307 xfer->resp_len = nbytes;
2308 xfer->rx_done = true;
2309 }
2310
ath10k_pci_bmi_wait(struct ath10k * ar,struct ath10k_ce_pipe * tx_pipe,struct ath10k_ce_pipe * rx_pipe,struct bmi_xfer * xfer)2311 static int ath10k_pci_bmi_wait(struct ath10k *ar,
2312 struct ath10k_ce_pipe *tx_pipe,
2313 struct ath10k_ce_pipe *rx_pipe,
2314 struct bmi_xfer *xfer)
2315 {
2316 unsigned long timeout = jiffies + BMI_COMMUNICATION_TIMEOUT_HZ;
2317 unsigned long started = jiffies;
2318 unsigned long dur;
2319 int ret;
2320
2321 while (time_before_eq(jiffies, timeout)) {
2322 ath10k_pci_bmi_send_done(tx_pipe);
2323 ath10k_pci_bmi_recv_data(rx_pipe);
2324
2325 if (xfer->tx_done && (xfer->rx_done == xfer->wait_for_resp)) {
2326 ret = 0;
2327 goto out;
2328 }
2329
2330 #if defined(__linux__)
2331 schedule();
2332 #elif defined(__FreeBSD__)
2333 /*
2334 * Using LinuxKPI's schedule() will hang for-ever as there is
2335 * no wake_up. Poll about 100 times per second until timeout.
2336 */
2337 schedule_timeout(BMI_COMMUNICATION_TIMEOUT_HZ/300);
2338 #endif
2339 }
2340
2341 ret = -ETIMEDOUT;
2342
2343 out:
2344 dur = jiffies - started;
2345 if (dur > HZ)
2346 ath10k_dbg(ar, ATH10K_DBG_BMI,
2347 "bmi cmd took %lu jiffies hz %d ret %d\n",
2348 dur, HZ, ret);
2349 return ret;
2350 }
2351
2352 /*
2353 * Send an interrupt to the device to wake up the Target CPU
2354 * so it has an opportunity to notice any changed state.
2355 */
ath10k_pci_wake_target_cpu(struct ath10k * ar)2356 static int ath10k_pci_wake_target_cpu(struct ath10k *ar)
2357 {
2358 u32 addr, val;
2359
2360 addr = SOC_CORE_BASE_ADDRESS + CORE_CTRL_ADDRESS;
2361 val = ath10k_pci_read32(ar, addr);
2362 val |= CORE_CTRL_CPU_INTR_MASK;
2363 ath10k_pci_write32(ar, addr, val);
2364
2365 return 0;
2366 }
2367
ath10k_pci_get_num_banks(struct ath10k * ar)2368 static int ath10k_pci_get_num_banks(struct ath10k *ar)
2369 {
2370 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2371
2372 switch (ar_pci->pdev->device) {
2373 case QCA988X_2_0_DEVICE_ID_UBNT:
2374 case QCA988X_2_0_DEVICE_ID:
2375 case QCA99X0_2_0_DEVICE_ID:
2376 case QCA9888_2_0_DEVICE_ID:
2377 case QCA9984_1_0_DEVICE_ID:
2378 case QCA9887_1_0_DEVICE_ID:
2379 return 1;
2380 case QCA6164_2_1_DEVICE_ID:
2381 case QCA6174_2_1_DEVICE_ID:
2382 switch (MS(ar->bus_param.chip_id, SOC_CHIP_ID_REV)) {
2383 case QCA6174_HW_1_0_CHIP_ID_REV:
2384 case QCA6174_HW_1_1_CHIP_ID_REV:
2385 case QCA6174_HW_2_1_CHIP_ID_REV:
2386 case QCA6174_HW_2_2_CHIP_ID_REV:
2387 return 3;
2388 case QCA6174_HW_1_3_CHIP_ID_REV:
2389 return 2;
2390 case QCA6174_HW_3_0_CHIP_ID_REV:
2391 case QCA6174_HW_3_1_CHIP_ID_REV:
2392 case QCA6174_HW_3_2_CHIP_ID_REV:
2393 return 9;
2394 }
2395 break;
2396 case QCA9377_1_0_DEVICE_ID:
2397 return 9;
2398 }
2399
2400 ath10k_warn(ar, "unknown number of banks, assuming 1\n");
2401 return 1;
2402 }
2403
ath10k_bus_get_num_banks(struct ath10k * ar)2404 static int ath10k_bus_get_num_banks(struct ath10k *ar)
2405 {
2406 struct ath10k_ce *ce = ath10k_ce_priv(ar);
2407
2408 return ce->bus_ops->get_num_banks(ar);
2409 }
2410
ath10k_pci_init_config(struct ath10k * ar)2411 int ath10k_pci_init_config(struct ath10k *ar)
2412 {
2413 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2414 u32 interconnect_targ_addr;
2415 u32 pcie_state_targ_addr = 0;
2416 u32 pipe_cfg_targ_addr = 0;
2417 u32 svc_to_pipe_map = 0;
2418 u32 pcie_config_flags = 0;
2419 u32 ealloc_value;
2420 u32 ealloc_targ_addr;
2421 u32 flag2_value;
2422 u32 flag2_targ_addr;
2423 int ret = 0;
2424
2425 /* Download to Target the CE Config and the service-to-CE map */
2426 interconnect_targ_addr =
2427 host_interest_item_address(HI_ITEM(hi_interconnect_state));
2428
2429 /* Supply Target-side CE configuration */
2430 ret = ath10k_pci_diag_read32(ar, interconnect_targ_addr,
2431 &pcie_state_targ_addr);
2432 if (ret != 0) {
2433 ath10k_err(ar, "Failed to get pcie state addr: %d\n", ret);
2434 return ret;
2435 }
2436
2437 if (pcie_state_targ_addr == 0) {
2438 ret = -EIO;
2439 ath10k_err(ar, "Invalid pcie state addr\n");
2440 return ret;
2441 }
2442
2443 ret = ath10k_pci_diag_read32(ar, (pcie_state_targ_addr +
2444 offsetof(struct pcie_state,
2445 pipe_cfg_addr)),
2446 &pipe_cfg_targ_addr);
2447 if (ret != 0) {
2448 ath10k_err(ar, "Failed to get pipe cfg addr: %d\n", ret);
2449 return ret;
2450 }
2451
2452 if (pipe_cfg_targ_addr == 0) {
2453 ret = -EIO;
2454 ath10k_err(ar, "Invalid pipe cfg addr\n");
2455 return ret;
2456 }
2457
2458 ret = ath10k_pci_diag_write_mem(ar, pipe_cfg_targ_addr,
2459 ar_pci->pipe_config,
2460 sizeof(struct ce_pipe_config) *
2461 NUM_TARGET_CE_CONFIG_WLAN);
2462
2463 if (ret != 0) {
2464 ath10k_err(ar, "Failed to write pipe cfg: %d\n", ret);
2465 return ret;
2466 }
2467
2468 ret = ath10k_pci_diag_read32(ar, (pcie_state_targ_addr +
2469 offsetof(struct pcie_state,
2470 svc_to_pipe_map)),
2471 &svc_to_pipe_map);
2472 if (ret != 0) {
2473 ath10k_err(ar, "Failed to get svc/pipe map: %d\n", ret);
2474 return ret;
2475 }
2476
2477 if (svc_to_pipe_map == 0) {
2478 ret = -EIO;
2479 ath10k_err(ar, "Invalid svc_to_pipe map\n");
2480 return ret;
2481 }
2482
2483 ret = ath10k_pci_diag_write_mem(ar, svc_to_pipe_map,
2484 ar_pci->serv_to_pipe,
2485 sizeof(pci_target_service_to_ce_map_wlan));
2486 if (ret != 0) {
2487 ath10k_err(ar, "Failed to write svc/pipe map: %d\n", ret);
2488 return ret;
2489 }
2490
2491 ret = ath10k_pci_diag_read32(ar, (pcie_state_targ_addr +
2492 offsetof(struct pcie_state,
2493 config_flags)),
2494 &pcie_config_flags);
2495 if (ret != 0) {
2496 ath10k_err(ar, "Failed to get pcie config_flags: %d\n", ret);
2497 return ret;
2498 }
2499
2500 pcie_config_flags &= ~PCIE_CONFIG_FLAG_ENABLE_L1;
2501
2502 ret = ath10k_pci_diag_write32(ar, (pcie_state_targ_addr +
2503 offsetof(struct pcie_state,
2504 config_flags)),
2505 pcie_config_flags);
2506 if (ret != 0) {
2507 ath10k_err(ar, "Failed to write pcie config_flags: %d\n", ret);
2508 return ret;
2509 }
2510
2511 /* configure early allocation */
2512 ealloc_targ_addr = host_interest_item_address(HI_ITEM(hi_early_alloc));
2513
2514 ret = ath10k_pci_diag_read32(ar, ealloc_targ_addr, &ealloc_value);
2515 if (ret != 0) {
2516 ath10k_err(ar, "Failed to get early alloc val: %d\n", ret);
2517 return ret;
2518 }
2519
2520 /* first bank is switched to IRAM */
2521 ealloc_value |= ((HI_EARLY_ALLOC_MAGIC << HI_EARLY_ALLOC_MAGIC_SHIFT) &
2522 HI_EARLY_ALLOC_MAGIC_MASK);
2523 ealloc_value |= ((ath10k_bus_get_num_banks(ar) <<
2524 HI_EARLY_ALLOC_IRAM_BANKS_SHIFT) &
2525 HI_EARLY_ALLOC_IRAM_BANKS_MASK);
2526
2527 ret = ath10k_pci_diag_write32(ar, ealloc_targ_addr, ealloc_value);
2528 if (ret != 0) {
2529 ath10k_err(ar, "Failed to set early alloc val: %d\n", ret);
2530 return ret;
2531 }
2532
2533 /* Tell Target to proceed with initialization */
2534 flag2_targ_addr = host_interest_item_address(HI_ITEM(hi_option_flag2));
2535
2536 ret = ath10k_pci_diag_read32(ar, flag2_targ_addr, &flag2_value);
2537 if (ret != 0) {
2538 ath10k_err(ar, "Failed to get option val: %d\n", ret);
2539 return ret;
2540 }
2541
2542 flag2_value |= HI_OPTION_EARLY_CFG_DONE;
2543
2544 ret = ath10k_pci_diag_write32(ar, flag2_targ_addr, flag2_value);
2545 if (ret != 0) {
2546 ath10k_err(ar, "Failed to set option val: %d\n", ret);
2547 return ret;
2548 }
2549
2550 return 0;
2551 }
2552
ath10k_pci_override_ce_config(struct ath10k * ar)2553 static void ath10k_pci_override_ce_config(struct ath10k *ar)
2554 {
2555 struct ce_attr *attr;
2556 struct ce_pipe_config *config;
2557 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2558
2559 /* For QCA6174 we're overriding the Copy Engine 5 configuration,
2560 * since it is currently used for other feature.
2561 */
2562
2563 /* Override Host's Copy Engine 5 configuration */
2564 attr = &ar_pci->attr[5];
2565 attr->src_sz_max = 0;
2566 attr->dest_nentries = 0;
2567
2568 /* Override Target firmware's Copy Engine configuration */
2569 config = &ar_pci->pipe_config[5];
2570 config->pipedir = __cpu_to_le32(PIPEDIR_OUT);
2571 config->nbytes_max = __cpu_to_le32(2048);
2572
2573 /* Map from service/endpoint to Copy Engine */
2574 ar_pci->serv_to_pipe[15].pipenum = __cpu_to_le32(1);
2575 }
2576
ath10k_pci_alloc_pipes(struct ath10k * ar)2577 int ath10k_pci_alloc_pipes(struct ath10k *ar)
2578 {
2579 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2580 struct ath10k_pci_pipe *pipe;
2581 struct ath10k_ce *ce = ath10k_ce_priv(ar);
2582 int i, ret;
2583
2584 for (i = 0; i < CE_COUNT; i++) {
2585 pipe = &ar_pci->pipe_info[i];
2586 pipe->ce_hdl = &ce->ce_states[i];
2587 pipe->pipe_num = i;
2588 pipe->hif_ce_state = ar;
2589
2590 ret = ath10k_ce_alloc_pipe(ar, i, &ar_pci->attr[i]);
2591 if (ret) {
2592 ath10k_err(ar, "failed to allocate copy engine pipe %d: %d\n",
2593 i, ret);
2594 return ret;
2595 }
2596
2597 /* Last CE is Diagnostic Window */
2598 if (i == CE_DIAG_PIPE) {
2599 ar_pci->ce_diag = pipe->ce_hdl;
2600 continue;
2601 }
2602
2603 pipe->buf_sz = (size_t)(ar_pci->attr[i].src_sz_max);
2604 }
2605
2606 return 0;
2607 }
2608
ath10k_pci_free_pipes(struct ath10k * ar)2609 void ath10k_pci_free_pipes(struct ath10k *ar)
2610 {
2611 int i;
2612
2613 for (i = 0; i < CE_COUNT; i++)
2614 ath10k_ce_free_pipe(ar, i);
2615 }
2616
ath10k_pci_init_pipes(struct ath10k * ar)2617 int ath10k_pci_init_pipes(struct ath10k *ar)
2618 {
2619 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2620 int i, ret;
2621
2622 for (i = 0; i < CE_COUNT; i++) {
2623 ret = ath10k_ce_init_pipe(ar, i, &ar_pci->attr[i]);
2624 if (ret) {
2625 ath10k_err(ar, "failed to initialize copy engine pipe %d: %d\n",
2626 i, ret);
2627 return ret;
2628 }
2629 }
2630
2631 return 0;
2632 }
2633
ath10k_pci_has_fw_crashed(struct ath10k * ar)2634 static bool ath10k_pci_has_fw_crashed(struct ath10k *ar)
2635 {
2636 return ath10k_pci_read32(ar, FW_INDICATOR_ADDRESS) &
2637 FW_IND_EVENT_PENDING;
2638 }
2639
ath10k_pci_fw_crashed_clear(struct ath10k * ar)2640 static void ath10k_pci_fw_crashed_clear(struct ath10k *ar)
2641 {
2642 u32 val;
2643
2644 val = ath10k_pci_read32(ar, FW_INDICATOR_ADDRESS);
2645 val &= ~FW_IND_EVENT_PENDING;
2646 ath10k_pci_write32(ar, FW_INDICATOR_ADDRESS, val);
2647 }
2648
ath10k_pci_has_device_gone(struct ath10k * ar)2649 static bool ath10k_pci_has_device_gone(struct ath10k *ar)
2650 {
2651 u32 val;
2652
2653 val = ath10k_pci_read32(ar, FW_INDICATOR_ADDRESS);
2654 return (val == 0xffffffff);
2655 }
2656
2657 /* this function effectively clears target memory controller assert line */
ath10k_pci_warm_reset_si0(struct ath10k * ar)2658 static void ath10k_pci_warm_reset_si0(struct ath10k *ar)
2659 {
2660 u32 val;
2661
2662 val = ath10k_pci_soc_read32(ar, SOC_RESET_CONTROL_ADDRESS);
2663 ath10k_pci_soc_write32(ar, SOC_RESET_CONTROL_ADDRESS,
2664 val | SOC_RESET_CONTROL_SI0_RST_MASK);
2665 val = ath10k_pci_soc_read32(ar, SOC_RESET_CONTROL_ADDRESS);
2666
2667 msleep(10);
2668
2669 val = ath10k_pci_soc_read32(ar, SOC_RESET_CONTROL_ADDRESS);
2670 ath10k_pci_soc_write32(ar, SOC_RESET_CONTROL_ADDRESS,
2671 val & ~SOC_RESET_CONTROL_SI0_RST_MASK);
2672 val = ath10k_pci_soc_read32(ar, SOC_RESET_CONTROL_ADDRESS);
2673
2674 msleep(10);
2675 }
2676
ath10k_pci_warm_reset_cpu(struct ath10k * ar)2677 static void ath10k_pci_warm_reset_cpu(struct ath10k *ar)
2678 {
2679 u32 val;
2680
2681 ath10k_pci_write32(ar, FW_INDICATOR_ADDRESS, 0);
2682
2683 val = ath10k_pci_soc_read32(ar, SOC_RESET_CONTROL_ADDRESS);
2684 ath10k_pci_soc_write32(ar, SOC_RESET_CONTROL_ADDRESS,
2685 val | SOC_RESET_CONTROL_CPU_WARM_RST_MASK);
2686 }
2687
ath10k_pci_warm_reset_ce(struct ath10k * ar)2688 static void ath10k_pci_warm_reset_ce(struct ath10k *ar)
2689 {
2690 u32 val;
2691
2692 val = ath10k_pci_soc_read32(ar, SOC_RESET_CONTROL_ADDRESS);
2693
2694 ath10k_pci_soc_write32(ar, SOC_RESET_CONTROL_ADDRESS,
2695 val | SOC_RESET_CONTROL_CE_RST_MASK);
2696 msleep(10);
2697 ath10k_pci_soc_write32(ar, SOC_RESET_CONTROL_ADDRESS,
2698 val & ~SOC_RESET_CONTROL_CE_RST_MASK);
2699 }
2700
ath10k_pci_warm_reset_clear_lf(struct ath10k * ar)2701 static void ath10k_pci_warm_reset_clear_lf(struct ath10k *ar)
2702 {
2703 u32 val;
2704
2705 val = ath10k_pci_soc_read32(ar, SOC_LF_TIMER_CONTROL0_ADDRESS);
2706 ath10k_pci_soc_write32(ar, SOC_LF_TIMER_CONTROL0_ADDRESS,
2707 val & ~SOC_LF_TIMER_CONTROL0_ENABLE_MASK);
2708 }
2709
ath10k_pci_warm_reset(struct ath10k * ar)2710 static int ath10k_pci_warm_reset(struct ath10k *ar)
2711 {
2712 int ret;
2713
2714 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot warm reset\n");
2715
2716 spin_lock_bh(&ar->data_lock);
2717 ar->stats.fw_warm_reset_counter++;
2718 spin_unlock_bh(&ar->data_lock);
2719
2720 ath10k_pci_irq_disable(ar);
2721
2722 /* Make sure the target CPU is not doing anything dangerous, e.g. if it
2723 * were to access copy engine while host performs copy engine reset
2724 * then it is possible for the device to confuse pci-e controller to
2725 * the point of bringing host system to a complete stop (i.e. hang).
2726 */
2727 ath10k_pci_warm_reset_si0(ar);
2728 ath10k_pci_warm_reset_cpu(ar);
2729 ath10k_pci_init_pipes(ar);
2730 ath10k_pci_wait_for_target_init(ar);
2731
2732 ath10k_pci_warm_reset_clear_lf(ar);
2733 ath10k_pci_warm_reset_ce(ar);
2734 ath10k_pci_warm_reset_cpu(ar);
2735 ath10k_pci_init_pipes(ar);
2736
2737 ret = ath10k_pci_wait_for_target_init(ar);
2738 if (ret) {
2739 ath10k_warn(ar, "failed to wait for target init: %d\n", ret);
2740 return ret;
2741 }
2742
2743 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot warm reset complete\n");
2744
2745 return 0;
2746 }
2747
ath10k_pci_qca99x0_soft_chip_reset(struct ath10k * ar)2748 static int ath10k_pci_qca99x0_soft_chip_reset(struct ath10k *ar)
2749 {
2750 ath10k_pci_irq_disable(ar);
2751 return ath10k_pci_qca99x0_chip_reset(ar);
2752 }
2753
ath10k_pci_safe_chip_reset(struct ath10k * ar)2754 static int ath10k_pci_safe_chip_reset(struct ath10k *ar)
2755 {
2756 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2757
2758 if (!ar_pci->pci_soft_reset)
2759 return -EOPNOTSUPP;
2760
2761 return ar_pci->pci_soft_reset(ar);
2762 }
2763
ath10k_pci_qca988x_chip_reset(struct ath10k * ar)2764 static int ath10k_pci_qca988x_chip_reset(struct ath10k *ar)
2765 {
2766 int i, ret;
2767 u32 val;
2768
2769 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot 988x chip reset\n");
2770
2771 /* Some hardware revisions (e.g. CUS223v2) has issues with cold reset.
2772 * It is thus preferred to use warm reset which is safer but may not be
2773 * able to recover the device from all possible fail scenarios.
2774 *
2775 * Warm reset doesn't always work on first try so attempt it a few
2776 * times before giving up.
2777 */
2778 for (i = 0; i < ATH10K_PCI_NUM_WARM_RESET_ATTEMPTS; i++) {
2779 ret = ath10k_pci_warm_reset(ar);
2780 if (ret) {
2781 ath10k_warn(ar, "failed to warm reset attempt %d of %d: %d\n",
2782 i + 1, ATH10K_PCI_NUM_WARM_RESET_ATTEMPTS,
2783 ret);
2784 continue;
2785 }
2786
2787 /* FIXME: Sometimes copy engine doesn't recover after warm
2788 * reset. In most cases this needs cold reset. In some of these
2789 * cases the device is in such a state that a cold reset may
2790 * lock up the host.
2791 *
2792 * Reading any host interest register via copy engine is
2793 * sufficient to verify if device is capable of booting
2794 * firmware blob.
2795 */
2796 ret = ath10k_pci_init_pipes(ar);
2797 if (ret) {
2798 ath10k_warn(ar, "failed to init copy engine: %d\n",
2799 ret);
2800 continue;
2801 }
2802
2803 ret = ath10k_pci_diag_read32(ar, QCA988X_HOST_INTEREST_ADDRESS,
2804 &val);
2805 if (ret) {
2806 ath10k_warn(ar, "failed to poke copy engine: %d\n",
2807 ret);
2808 continue;
2809 }
2810
2811 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot chip reset complete (warm)\n");
2812 return 0;
2813 }
2814
2815 if (ath10k_pci_reset_mode == ATH10K_PCI_RESET_WARM_ONLY) {
2816 ath10k_warn(ar, "refusing cold reset as requested\n");
2817 return -EPERM;
2818 }
2819
2820 ret = ath10k_pci_cold_reset(ar);
2821 if (ret) {
2822 ath10k_warn(ar, "failed to cold reset: %d\n", ret);
2823 return ret;
2824 }
2825
2826 ret = ath10k_pci_wait_for_target_init(ar);
2827 if (ret) {
2828 ath10k_warn(ar, "failed to wait for target after cold reset: %d\n",
2829 ret);
2830 return ret;
2831 }
2832
2833 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot qca988x chip reset complete (cold)\n");
2834
2835 return 0;
2836 }
2837
ath10k_pci_qca6174_chip_reset(struct ath10k * ar)2838 static int ath10k_pci_qca6174_chip_reset(struct ath10k *ar)
2839 {
2840 int ret;
2841
2842 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot qca6174 chip reset\n");
2843
2844 /* FIXME: QCA6174 requires cold + warm reset to work. */
2845
2846 ret = ath10k_pci_cold_reset(ar);
2847 if (ret) {
2848 ath10k_warn(ar, "failed to cold reset: %d\n", ret);
2849 return ret;
2850 }
2851
2852 ret = ath10k_pci_wait_for_target_init(ar);
2853 if (ret) {
2854 ath10k_warn(ar, "failed to wait for target after cold reset: %d\n",
2855 ret);
2856 return ret;
2857 }
2858
2859 ret = ath10k_pci_warm_reset(ar);
2860 if (ret) {
2861 ath10k_warn(ar, "failed to warm reset: %d\n", ret);
2862 return ret;
2863 }
2864
2865 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot qca6174 chip reset complete (cold)\n");
2866
2867 return 0;
2868 }
2869
ath10k_pci_qca99x0_chip_reset(struct ath10k * ar)2870 static int ath10k_pci_qca99x0_chip_reset(struct ath10k *ar)
2871 {
2872 int ret;
2873
2874 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot qca99x0 chip reset\n");
2875
2876 ret = ath10k_pci_cold_reset(ar);
2877 if (ret) {
2878 ath10k_warn(ar, "failed to cold reset: %d\n", ret);
2879 return ret;
2880 }
2881
2882 ret = ath10k_pci_wait_for_target_init(ar);
2883 if (ret) {
2884 ath10k_warn(ar, "failed to wait for target after cold reset: %d\n",
2885 ret);
2886 return ret;
2887 }
2888
2889 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot qca99x0 chip reset complete (cold)\n");
2890
2891 return 0;
2892 }
2893
ath10k_pci_chip_reset(struct ath10k * ar)2894 static int ath10k_pci_chip_reset(struct ath10k *ar)
2895 {
2896 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2897
2898 if (WARN_ON(!ar_pci->pci_hard_reset))
2899 return -EOPNOTSUPP;
2900
2901 return ar_pci->pci_hard_reset(ar);
2902 }
2903
ath10k_pci_hif_power_up(struct ath10k * ar,enum ath10k_firmware_mode fw_mode)2904 static int ath10k_pci_hif_power_up(struct ath10k *ar,
2905 enum ath10k_firmware_mode fw_mode)
2906 {
2907 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2908 int ret;
2909
2910 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot hif power up\n");
2911
2912 pcie_capability_read_word(ar_pci->pdev, PCI_EXP_LNKCTL,
2913 &ar_pci->link_ctl);
2914 pcie_capability_clear_word(ar_pci->pdev, PCI_EXP_LNKCTL,
2915 PCI_EXP_LNKCTL_ASPMC);
2916
2917 /*
2918 * Bring the target up cleanly.
2919 *
2920 * The target may be in an undefined state with an AUX-powered Target
2921 * and a Host in WoW mode. If the Host crashes, loses power, or is
2922 * restarted (without unloading the driver) then the Target is left
2923 * (aux) powered and running. On a subsequent driver load, the Target
2924 * is in an unexpected state. We try to catch that here in order to
2925 * reset the Target and retry the probe.
2926 */
2927 ret = ath10k_pci_chip_reset(ar);
2928 if (ret) {
2929 if (ath10k_pci_has_fw_crashed(ar)) {
2930 ath10k_warn(ar, "firmware crashed during chip reset\n");
2931 ath10k_pci_fw_crashed_clear(ar);
2932 ath10k_pci_fw_crashed_dump(ar);
2933 }
2934
2935 ath10k_err(ar, "failed to reset chip: %d\n", ret);
2936 goto err_sleep;
2937 }
2938
2939 ret = ath10k_pci_init_pipes(ar);
2940 if (ret) {
2941 ath10k_err(ar, "failed to initialize CE: %d\n", ret);
2942 goto err_sleep;
2943 }
2944
2945 ret = ath10k_pci_init_config(ar);
2946 if (ret) {
2947 ath10k_err(ar, "failed to setup init config: %d\n", ret);
2948 goto err_ce;
2949 }
2950
2951 ret = ath10k_pci_wake_target_cpu(ar);
2952 if (ret) {
2953 ath10k_err(ar, "could not wake up target CPU: %d\n", ret);
2954 goto err_ce;
2955 }
2956
2957 return 0;
2958
2959 err_ce:
2960 ath10k_pci_ce_deinit(ar);
2961
2962 err_sleep:
2963 return ret;
2964 }
2965
ath10k_pci_hif_power_down(struct ath10k * ar)2966 void ath10k_pci_hif_power_down(struct ath10k *ar)
2967 {
2968 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot hif power down\n");
2969
2970 /* Currently hif_power_up performs effectively a reset and hif_stop
2971 * resets the chip as well so there's no point in resetting here.
2972 */
2973 }
2974
ath10k_pci_hif_suspend(struct ath10k * ar)2975 static int ath10k_pci_hif_suspend(struct ath10k *ar)
2976 {
2977 /* Nothing to do; the important stuff is in the driver suspend. */
2978 return 0;
2979 }
2980
2981 #ifdef CONFIG_PM
ath10k_pci_suspend(struct ath10k * ar)2982 static int ath10k_pci_suspend(struct ath10k *ar)
2983 {
2984 /* The grace timer can still be counting down and ar->ps_awake be true.
2985 * It is known that the device may be asleep after resuming regardless
2986 * of the SoC powersave state before suspending. Hence make sure the
2987 * device is asleep before proceeding.
2988 */
2989 ath10k_pci_sleep_sync(ar);
2990
2991 return 0;
2992 }
2993 #endif
2994
ath10k_pci_hif_resume(struct ath10k * ar)2995 static int ath10k_pci_hif_resume(struct ath10k *ar)
2996 {
2997 /* Nothing to do; the important stuff is in the driver resume. */
2998 return 0;
2999 }
3000
3001 #ifdef CONFIG_PM
ath10k_pci_resume(struct ath10k * ar)3002 static int ath10k_pci_resume(struct ath10k *ar)
3003 {
3004 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
3005 struct pci_dev *pdev = ar_pci->pdev;
3006 u32 val;
3007 int ret = 0;
3008
3009 ret = ath10k_pci_force_wake(ar);
3010 if (ret) {
3011 ath10k_err(ar, "failed to wake up target: %d\n", ret);
3012 return ret;
3013 }
3014
3015 /* Suspend/Resume resets the PCI configuration space, so we have to
3016 * re-disable the RETRY_TIMEOUT register (0x41) to keep PCI Tx retries
3017 * from interfering with C3 CPU state. pci_restore_state won't help
3018 * here since it only restores the first 64 bytes pci config header.
3019 */
3020 pci_read_config_dword(pdev, 0x40, &val);
3021 if ((val & 0x0000ff00) != 0)
3022 pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);
3023
3024 return ret;
3025 }
3026 #endif
3027
ath10k_pci_validate_cal(void * data,size_t size)3028 static bool ath10k_pci_validate_cal(void *data, size_t size)
3029 {
3030 __le16 *cal_words = data;
3031 u16 checksum = 0;
3032 size_t i;
3033
3034 if (size % 2 != 0)
3035 return false;
3036
3037 for (i = 0; i < size / 2; i++)
3038 checksum ^= le16_to_cpu(cal_words[i]);
3039
3040 return checksum == 0xffff;
3041 }
3042
ath10k_pci_enable_eeprom(struct ath10k * ar)3043 static void ath10k_pci_enable_eeprom(struct ath10k *ar)
3044 {
3045 /* Enable SI clock */
3046 ath10k_pci_soc_write32(ar, CLOCK_CONTROL_OFFSET, 0x0);
3047
3048 /* Configure GPIOs for I2C operation */
3049 ath10k_pci_write32(ar,
3050 GPIO_BASE_ADDRESS + GPIO_PIN0_OFFSET +
3051 4 * QCA9887_1_0_I2C_SDA_GPIO_PIN,
3052 SM(QCA9887_1_0_I2C_SDA_PIN_CONFIG,
3053 GPIO_PIN0_CONFIG) |
3054 SM(1, GPIO_PIN0_PAD_PULL));
3055
3056 ath10k_pci_write32(ar,
3057 GPIO_BASE_ADDRESS + GPIO_PIN0_OFFSET +
3058 4 * QCA9887_1_0_SI_CLK_GPIO_PIN,
3059 SM(QCA9887_1_0_SI_CLK_PIN_CONFIG, GPIO_PIN0_CONFIG) |
3060 SM(1, GPIO_PIN0_PAD_PULL));
3061
3062 ath10k_pci_write32(ar,
3063 GPIO_BASE_ADDRESS +
3064 QCA9887_1_0_GPIO_ENABLE_W1TS_LOW_ADDRESS,
3065 1u << QCA9887_1_0_SI_CLK_GPIO_PIN);
3066
3067 /* In Swift ASIC - EEPROM clock will be (110MHz/512) = 214KHz */
3068 ath10k_pci_write32(ar,
3069 SI_BASE_ADDRESS + SI_CONFIG_OFFSET,
3070 SM(1, SI_CONFIG_ERR_INT) |
3071 SM(1, SI_CONFIG_BIDIR_OD_DATA) |
3072 SM(1, SI_CONFIG_I2C) |
3073 SM(1, SI_CONFIG_POS_SAMPLE) |
3074 SM(1, SI_CONFIG_INACTIVE_DATA) |
3075 SM(1, SI_CONFIG_INACTIVE_CLK) |
3076 SM(8, SI_CONFIG_DIVIDER));
3077 }
3078
ath10k_pci_read_eeprom(struct ath10k * ar,u16 addr,u8 * out)3079 static int ath10k_pci_read_eeprom(struct ath10k *ar, u16 addr, u8 *out)
3080 {
3081 u32 reg;
3082 int wait_limit;
3083
3084 /* set device select byte and for the read operation */
3085 reg = QCA9887_EEPROM_SELECT_READ |
3086 SM(addr, QCA9887_EEPROM_ADDR_LO) |
3087 SM(addr >> 8, QCA9887_EEPROM_ADDR_HI);
3088 ath10k_pci_write32(ar, SI_BASE_ADDRESS + SI_TX_DATA0_OFFSET, reg);
3089
3090 /* write transmit data, transfer length, and START bit */
3091 ath10k_pci_write32(ar, SI_BASE_ADDRESS + SI_CS_OFFSET,
3092 SM(1, SI_CS_START) | SM(1, SI_CS_RX_CNT) |
3093 SM(4, SI_CS_TX_CNT));
3094
3095 /* wait max 1 sec */
3096 wait_limit = 100000;
3097
3098 /* wait for SI_CS_DONE_INT */
3099 do {
3100 reg = ath10k_pci_read32(ar, SI_BASE_ADDRESS + SI_CS_OFFSET);
3101 if (MS(reg, SI_CS_DONE_INT))
3102 break;
3103
3104 wait_limit--;
3105 udelay(10);
3106 } while (wait_limit > 0);
3107
3108 if (!MS(reg, SI_CS_DONE_INT)) {
3109 ath10k_err(ar, "timeout while reading device EEPROM at %04x\n",
3110 addr);
3111 return -ETIMEDOUT;
3112 }
3113
3114 /* clear SI_CS_DONE_INT */
3115 ath10k_pci_write32(ar, SI_BASE_ADDRESS + SI_CS_OFFSET, reg);
3116
3117 if (MS(reg, SI_CS_DONE_ERR)) {
3118 ath10k_err(ar, "failed to read device EEPROM at %04x\n", addr);
3119 return -EIO;
3120 }
3121
3122 /* extract receive data */
3123 reg = ath10k_pci_read32(ar, SI_BASE_ADDRESS + SI_RX_DATA0_OFFSET);
3124 *out = reg;
3125
3126 return 0;
3127 }
3128
ath10k_pci_hif_fetch_cal_eeprom(struct ath10k * ar,void ** data,size_t * data_len)3129 static int ath10k_pci_hif_fetch_cal_eeprom(struct ath10k *ar, void **data,
3130 size_t *data_len)
3131 {
3132 u8 *caldata = NULL;
3133 size_t calsize, i;
3134 int ret;
3135
3136 if (!QCA_REV_9887(ar))
3137 return -EOPNOTSUPP;
3138
3139 calsize = ar->hw_params.cal_data_len;
3140 caldata = kmalloc(calsize, GFP_KERNEL);
3141 if (!caldata)
3142 return -ENOMEM;
3143
3144 ath10k_pci_enable_eeprom(ar);
3145
3146 for (i = 0; i < calsize; i++) {
3147 ret = ath10k_pci_read_eeprom(ar, i, &caldata[i]);
3148 if (ret)
3149 goto err_free;
3150 }
3151
3152 if (!ath10k_pci_validate_cal(caldata, calsize))
3153 goto err_free;
3154
3155 *data = caldata;
3156 *data_len = calsize;
3157
3158 return 0;
3159
3160 err_free:
3161 kfree(caldata);
3162
3163 return -EINVAL;
3164 }
3165
3166 static const struct ath10k_hif_ops ath10k_pci_hif_ops = {
3167 .tx_sg = ath10k_pci_hif_tx_sg,
3168 .diag_read = ath10k_pci_hif_diag_read,
3169 .diag_write = ath10k_pci_diag_write_mem,
3170 .exchange_bmi_msg = ath10k_pci_hif_exchange_bmi_msg,
3171 .start = ath10k_pci_hif_start,
3172 .stop = ath10k_pci_hif_stop,
3173 .map_service_to_pipe = ath10k_pci_hif_map_service_to_pipe,
3174 .get_default_pipe = ath10k_pci_hif_get_default_pipe,
3175 .send_complete_check = ath10k_pci_hif_send_complete_check,
3176 .get_free_queue_number = ath10k_pci_hif_get_free_queue_number,
3177 .power_up = ath10k_pci_hif_power_up,
3178 .power_down = ath10k_pci_hif_power_down,
3179 .read32 = ath10k_pci_read32,
3180 .write32 = ath10k_pci_write32,
3181 .suspend = ath10k_pci_hif_suspend,
3182 .resume = ath10k_pci_hif_resume,
3183 .fetch_cal_eeprom = ath10k_pci_hif_fetch_cal_eeprom,
3184 };
3185
3186 /*
3187 * Top-level interrupt handler for all PCI interrupts from a Target.
3188 * When a block of MSI interrupts is allocated, this top-level handler
3189 * is not used; instead, we directly call the correct sub-handler.
3190 */
ath10k_pci_interrupt_handler(int irq,void * arg)3191 static irqreturn_t ath10k_pci_interrupt_handler(int irq, void *arg)
3192 {
3193 struct ath10k *ar = arg;
3194 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
3195 int ret;
3196
3197 if (ath10k_pci_has_device_gone(ar))
3198 return IRQ_NONE;
3199
3200 ret = ath10k_pci_force_wake(ar);
3201 if (ret) {
3202 ath10k_warn(ar, "failed to wake device up on irq: %d\n", ret);
3203 return IRQ_NONE;
3204 }
3205
3206 if ((ar_pci->oper_irq_mode == ATH10K_PCI_IRQ_INTX) &&
3207 !ath10k_pci_irq_pending(ar))
3208 return IRQ_NONE;
3209
3210 ath10k_pci_disable_and_clear_intx_irq(ar);
3211 ath10k_pci_irq_msi_fw_mask(ar);
3212 napi_schedule(&ar->napi);
3213
3214 return IRQ_HANDLED;
3215 }
3216
ath10k_pci_napi_poll(struct napi_struct * ctx,int budget)3217 static int ath10k_pci_napi_poll(struct napi_struct *ctx, int budget)
3218 {
3219 struct ath10k *ar = container_of(ctx, struct ath10k, napi);
3220 int done = 0;
3221
3222 if (ath10k_pci_has_fw_crashed(ar)) {
3223 ath10k_pci_fw_crashed_clear(ar);
3224 ath10k_pci_fw_crashed_dump(ar);
3225 napi_complete(ctx);
3226 return done;
3227 }
3228
3229 ath10k_ce_per_engine_service_any(ar);
3230
3231 done = ath10k_htt_txrx_compl_task(ar, budget);
3232
3233 if (done < budget) {
3234 napi_complete_done(ctx, done);
3235 /* In case of MSI, it is possible that interrupts are received
3236 * while NAPI poll is inprogress. So pending interrupts that are
3237 * received after processing all copy engine pipes by NAPI poll
3238 * will not be handled again. This is causing failure to
3239 * complete boot sequence in x86 platform. So before enabling
3240 * interrupts safer to check for pending interrupts for
3241 * immediate servicing.
3242 */
3243 if (ath10k_ce_interrupt_summary(ar)) {
3244 napi_schedule(ctx);
3245 goto out;
3246 }
3247 ath10k_pci_enable_intx_irq(ar);
3248 ath10k_pci_irq_msi_fw_unmask(ar);
3249 }
3250
3251 out:
3252 return done;
3253 }
3254
ath10k_pci_request_irq_msi(struct ath10k * ar)3255 static int ath10k_pci_request_irq_msi(struct ath10k *ar)
3256 {
3257 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
3258 int ret;
3259
3260 ret = request_irq(ar_pci->pdev->irq,
3261 ath10k_pci_interrupt_handler,
3262 IRQF_SHARED, "ath10k_pci", ar);
3263 if (ret) {
3264 ath10k_warn(ar, "failed to request MSI irq %d: %d\n",
3265 ar_pci->pdev->irq, ret);
3266 return ret;
3267 }
3268
3269 return 0;
3270 }
3271
ath10k_pci_request_irq_intx(struct ath10k * ar)3272 static int ath10k_pci_request_irq_intx(struct ath10k *ar)
3273 {
3274 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
3275 int ret;
3276
3277 ret = request_irq(ar_pci->pdev->irq,
3278 ath10k_pci_interrupt_handler,
3279 IRQF_SHARED, "ath10k_pci", ar);
3280 if (ret) {
3281 ath10k_warn(ar, "failed to request legacy irq %d: %d\n",
3282 ar_pci->pdev->irq, ret);
3283 return ret;
3284 }
3285
3286 return 0;
3287 }
3288
ath10k_pci_request_irq(struct ath10k * ar)3289 static int ath10k_pci_request_irq(struct ath10k *ar)
3290 {
3291 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
3292
3293 switch (ar_pci->oper_irq_mode) {
3294 case ATH10K_PCI_IRQ_INTX:
3295 return ath10k_pci_request_irq_intx(ar);
3296 case ATH10K_PCI_IRQ_MSI:
3297 return ath10k_pci_request_irq_msi(ar);
3298 default:
3299 return -EINVAL;
3300 }
3301 }
3302
ath10k_pci_free_irq(struct ath10k * ar)3303 static void ath10k_pci_free_irq(struct ath10k *ar)
3304 {
3305 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
3306
3307 free_irq(ar_pci->pdev->irq, ar);
3308 }
3309
ath10k_pci_init_napi(struct ath10k * ar)3310 void ath10k_pci_init_napi(struct ath10k *ar)
3311 {
3312 netif_napi_add(ar->napi_dev, &ar->napi, ath10k_pci_napi_poll);
3313 }
3314
ath10k_pci_init_irq(struct ath10k * ar)3315 static int ath10k_pci_init_irq(struct ath10k *ar)
3316 {
3317 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
3318 int ret;
3319
3320 ath10k_pci_init_napi(ar);
3321
3322 if (ath10k_pci_irq_mode != ATH10K_PCI_IRQ_AUTO)
3323 ath10k_info(ar, "limiting irq mode to: %d\n",
3324 ath10k_pci_irq_mode);
3325
3326 /* Try MSI */
3327 if (ath10k_pci_irq_mode != ATH10K_PCI_IRQ_INTX) {
3328 ar_pci->oper_irq_mode = ATH10K_PCI_IRQ_MSI;
3329 ret = pci_enable_msi(ar_pci->pdev);
3330 if (ret == 0)
3331 return 0;
3332
3333 /* MHI failed, try legacy irq next */
3334 }
3335
3336 /* Try legacy irq
3337 *
3338 * A potential race occurs here: The CORE_BASE write
3339 * depends on target correctly decoding AXI address but
3340 * host won't know when target writes BAR to CORE_CTRL.
3341 * This write might get lost if target has NOT written BAR.
3342 * For now, fix the race by repeating the write in below
3343 * synchronization checking.
3344 */
3345 ar_pci->oper_irq_mode = ATH10K_PCI_IRQ_INTX;
3346
3347 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + PCIE_INTR_ENABLE_ADDRESS,
3348 PCIE_INTR_FIRMWARE_MASK | PCIE_INTR_CE_MASK_ALL);
3349
3350 return 0;
3351 }
3352
ath10k_pci_deinit_irq_intx(struct ath10k * ar)3353 static void ath10k_pci_deinit_irq_intx(struct ath10k *ar)
3354 {
3355 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + PCIE_INTR_ENABLE_ADDRESS,
3356 0);
3357 }
3358
ath10k_pci_deinit_irq(struct ath10k * ar)3359 static int ath10k_pci_deinit_irq(struct ath10k *ar)
3360 {
3361 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
3362
3363 switch (ar_pci->oper_irq_mode) {
3364 case ATH10K_PCI_IRQ_INTX:
3365 ath10k_pci_deinit_irq_intx(ar);
3366 break;
3367 default:
3368 pci_disable_msi(ar_pci->pdev);
3369 break;
3370 }
3371
3372 return 0;
3373 }
3374
ath10k_pci_wait_for_target_init(struct ath10k * ar)3375 int ath10k_pci_wait_for_target_init(struct ath10k *ar)
3376 {
3377 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
3378 unsigned long timeout;
3379 u32 val;
3380
3381 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot waiting target to initialise\n");
3382
3383 timeout = jiffies + msecs_to_jiffies(ATH10K_PCI_TARGET_WAIT);
3384
3385 do {
3386 val = ath10k_pci_read32(ar, FW_INDICATOR_ADDRESS);
3387
3388 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot target indicator %x\n",
3389 val);
3390
3391 /* target should never return this */
3392 if (val == 0xffffffff)
3393 continue;
3394
3395 /* the device has crashed so don't bother trying anymore */
3396 if (val & FW_IND_EVENT_PENDING)
3397 break;
3398
3399 if (val & FW_IND_INITIALIZED)
3400 break;
3401
3402 if (ar_pci->oper_irq_mode == ATH10K_PCI_IRQ_INTX)
3403 /* Fix potential race by repeating CORE_BASE writes */
3404 ath10k_pci_enable_intx_irq(ar);
3405
3406 mdelay(10);
3407 } while (time_before(jiffies, timeout));
3408
3409 ath10k_pci_disable_and_clear_intx_irq(ar);
3410 ath10k_pci_irq_msi_fw_mask(ar);
3411
3412 if (val == 0xffffffff) {
3413 ath10k_err(ar, "failed to read device register, device is gone\n");
3414 return -EIO;
3415 }
3416
3417 if (val & FW_IND_EVENT_PENDING) {
3418 ath10k_warn(ar, "device has crashed during init\n");
3419 return -ECOMM;
3420 }
3421
3422 if (!(val & FW_IND_INITIALIZED)) {
3423 ath10k_err(ar, "failed to receive initialized event from target: %08x\n",
3424 val);
3425 return -ETIMEDOUT;
3426 }
3427
3428 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot target initialised\n");
3429 return 0;
3430 }
3431
ath10k_pci_cold_reset(struct ath10k * ar)3432 static int ath10k_pci_cold_reset(struct ath10k *ar)
3433 {
3434 u32 val;
3435
3436 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot cold reset\n");
3437
3438 spin_lock_bh(&ar->data_lock);
3439
3440 ar->stats.fw_cold_reset_counter++;
3441
3442 spin_unlock_bh(&ar->data_lock);
3443
3444 /* Put Target, including PCIe, into RESET. */
3445 val = ath10k_pci_reg_read32(ar, SOC_GLOBAL_RESET_ADDRESS);
3446 val |= 1;
3447 ath10k_pci_reg_write32(ar, SOC_GLOBAL_RESET_ADDRESS, val);
3448
3449 /* After writing into SOC_GLOBAL_RESET to put device into
3450 * reset and pulling out of reset pcie may not be stable
3451 * for any immediate pcie register access and cause bus error,
3452 * add delay before any pcie access request to fix this issue.
3453 */
3454 msleep(20);
3455
3456 /* Pull Target, including PCIe, out of RESET. */
3457 val &= ~1;
3458 ath10k_pci_reg_write32(ar, SOC_GLOBAL_RESET_ADDRESS, val);
3459
3460 msleep(20);
3461
3462 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot cold reset complete\n");
3463
3464 return 0;
3465 }
3466
ath10k_pci_claim(struct ath10k * ar)3467 static int ath10k_pci_claim(struct ath10k *ar)
3468 {
3469 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
3470 struct pci_dev *pdev = ar_pci->pdev;
3471 int ret;
3472
3473 pci_set_drvdata(pdev, ar);
3474
3475 ret = pci_enable_device(pdev);
3476 if (ret) {
3477 ath10k_err(ar, "failed to enable pci device: %d\n", ret);
3478 return ret;
3479 }
3480
3481 ret = pci_request_region(pdev, BAR_NUM, "ath");
3482 if (ret) {
3483 ath10k_err(ar, "failed to request region BAR%d: %d\n", BAR_NUM,
3484 ret);
3485 goto err_device;
3486 }
3487
3488 /* Target expects 32 bit DMA. Enforce it. */
3489 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
3490 if (ret) {
3491 ath10k_err(ar, "failed to set dma mask to 32-bit: %d\n", ret);
3492 goto err_region;
3493 }
3494
3495 pci_set_master(pdev);
3496
3497 #if defined(__FreeBSD__)
3498 linuxkpi_pcim_want_to_use_bus_functions(pdev);
3499 #endif
3500
3501 /* Arrange for access to Target SoC registers. */
3502 ar_pci->mem_len = pci_resource_len(pdev, BAR_NUM);
3503 ar_pci->mem = pci_iomap(pdev, BAR_NUM, 0);
3504 if (!ar_pci->mem) {
3505 ath10k_err(ar, "failed to iomap BAR%d\n", BAR_NUM);
3506 ret = -EIO;
3507 goto err_region;
3508 }
3509
3510 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot pci_mem 0x%p\n", ar_pci->mem);
3511 return 0;
3512
3513 err_region:
3514 pci_release_region(pdev, BAR_NUM);
3515
3516 err_device:
3517 pci_disable_device(pdev);
3518
3519 return ret;
3520 }
3521
ath10k_pci_release(struct ath10k * ar)3522 static void ath10k_pci_release(struct ath10k *ar)
3523 {
3524 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
3525 struct pci_dev *pdev = ar_pci->pdev;
3526
3527 pci_iounmap(pdev, ar_pci->mem);
3528 pci_release_region(pdev, BAR_NUM);
3529 pci_disable_device(pdev);
3530 }
3531
ath10k_pci_chip_is_supported(u32 dev_id,u32 chip_id)3532 static bool ath10k_pci_chip_is_supported(u32 dev_id, u32 chip_id)
3533 {
3534 const struct ath10k_pci_supp_chip *supp_chip;
3535 int i;
3536 u32 rev_id = MS(chip_id, SOC_CHIP_ID_REV);
3537
3538 for (i = 0; i < ARRAY_SIZE(ath10k_pci_supp_chips); i++) {
3539 supp_chip = &ath10k_pci_supp_chips[i];
3540
3541 if (supp_chip->dev_id == dev_id &&
3542 supp_chip->rev_id == rev_id)
3543 return true;
3544 }
3545
3546 return false;
3547 }
3548
ath10k_pci_setup_resource(struct ath10k * ar)3549 int ath10k_pci_setup_resource(struct ath10k *ar)
3550 {
3551 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
3552 struct ath10k_ce *ce = ath10k_ce_priv(ar);
3553 int ret;
3554
3555 spin_lock_init(&ce->ce_lock);
3556 spin_lock_init(&ar_pci->ps_lock);
3557 mutex_init(&ar_pci->ce_diag_mutex);
3558
3559 INIT_WORK(&ar_pci->dump_work, ath10k_pci_fw_dump_work);
3560
3561 timer_setup(&ar_pci->rx_post_retry, ath10k_pci_rx_replenish_retry, 0);
3562
3563 ar_pci->attr = kmemdup(pci_host_ce_config_wlan,
3564 sizeof(pci_host_ce_config_wlan),
3565 GFP_KERNEL);
3566 if (!ar_pci->attr)
3567 return -ENOMEM;
3568
3569 ar_pci->pipe_config = kmemdup(pci_target_ce_config_wlan,
3570 sizeof(pci_target_ce_config_wlan),
3571 GFP_KERNEL);
3572 if (!ar_pci->pipe_config) {
3573 ret = -ENOMEM;
3574 goto err_free_attr;
3575 }
3576
3577 ar_pci->serv_to_pipe = kmemdup(pci_target_service_to_ce_map_wlan,
3578 sizeof(pci_target_service_to_ce_map_wlan),
3579 GFP_KERNEL);
3580 if (!ar_pci->serv_to_pipe) {
3581 ret = -ENOMEM;
3582 goto err_free_pipe_config;
3583 }
3584
3585 if (QCA_REV_6174(ar) || QCA_REV_9377(ar))
3586 ath10k_pci_override_ce_config(ar);
3587
3588 ret = ath10k_pci_alloc_pipes(ar);
3589 if (ret) {
3590 ath10k_err(ar, "failed to allocate copy engine pipes: %d\n",
3591 ret);
3592 goto err_free_serv_to_pipe;
3593 }
3594
3595 return 0;
3596
3597 err_free_serv_to_pipe:
3598 kfree(ar_pci->serv_to_pipe);
3599 err_free_pipe_config:
3600 kfree(ar_pci->pipe_config);
3601 err_free_attr:
3602 kfree(ar_pci->attr);
3603 return ret;
3604 }
3605
ath10k_pci_release_resource(struct ath10k * ar)3606 void ath10k_pci_release_resource(struct ath10k *ar)
3607 {
3608 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
3609
3610 ath10k_pci_rx_retry_sync(ar);
3611 netif_napi_del(&ar->napi);
3612 ath10k_pci_ce_deinit(ar);
3613 ath10k_pci_free_pipes(ar);
3614 kfree(ar_pci->attr);
3615 kfree(ar_pci->pipe_config);
3616 kfree(ar_pci->serv_to_pipe);
3617 }
3618
3619 static const struct ath10k_bus_ops ath10k_pci_bus_ops = {
3620 .read32 = ath10k_bus_pci_read32,
3621 .write32 = ath10k_bus_pci_write32,
3622 .get_num_banks = ath10k_pci_get_num_banks,
3623 };
3624
ath10k_pci_probe(struct pci_dev * pdev,const struct pci_device_id * pci_dev)3625 static int ath10k_pci_probe(struct pci_dev *pdev,
3626 const struct pci_device_id *pci_dev)
3627 {
3628 int ret = 0;
3629 struct ath10k *ar;
3630 struct ath10k_pci *ar_pci;
3631 enum ath10k_hw_rev hw_rev;
3632 struct ath10k_bus_params bus_params = {};
3633 bool pci_ps, is_qca988x = false;
3634 int (*pci_soft_reset)(struct ath10k *ar);
3635 int (*pci_hard_reset)(struct ath10k *ar);
3636 u32 (*targ_cpu_to_ce_addr)(struct ath10k *ar, u32 addr);
3637
3638 switch (pci_dev->device) {
3639 case QCA988X_2_0_DEVICE_ID_UBNT:
3640 case QCA988X_2_0_DEVICE_ID:
3641 hw_rev = ATH10K_HW_QCA988X;
3642 pci_ps = false;
3643 is_qca988x = true;
3644 pci_soft_reset = ath10k_pci_warm_reset;
3645 pci_hard_reset = ath10k_pci_qca988x_chip_reset;
3646 targ_cpu_to_ce_addr = ath10k_pci_qca988x_targ_cpu_to_ce_addr;
3647 break;
3648 case QCA9887_1_0_DEVICE_ID:
3649 hw_rev = ATH10K_HW_QCA9887;
3650 pci_ps = false;
3651 pci_soft_reset = ath10k_pci_warm_reset;
3652 pci_hard_reset = ath10k_pci_qca988x_chip_reset;
3653 targ_cpu_to_ce_addr = ath10k_pci_qca988x_targ_cpu_to_ce_addr;
3654 break;
3655 case QCA6164_2_1_DEVICE_ID:
3656 case QCA6174_2_1_DEVICE_ID:
3657 hw_rev = ATH10K_HW_QCA6174;
3658 pci_ps = true;
3659 pci_soft_reset = ath10k_pci_warm_reset;
3660 pci_hard_reset = ath10k_pci_qca6174_chip_reset;
3661 targ_cpu_to_ce_addr = ath10k_pci_qca6174_targ_cpu_to_ce_addr;
3662 break;
3663 case QCA99X0_2_0_DEVICE_ID:
3664 hw_rev = ATH10K_HW_QCA99X0;
3665 pci_ps = false;
3666 pci_soft_reset = ath10k_pci_qca99x0_soft_chip_reset;
3667 pci_hard_reset = ath10k_pci_qca99x0_chip_reset;
3668 targ_cpu_to_ce_addr = ath10k_pci_qca99x0_targ_cpu_to_ce_addr;
3669 break;
3670 case QCA9984_1_0_DEVICE_ID:
3671 hw_rev = ATH10K_HW_QCA9984;
3672 pci_ps = false;
3673 pci_soft_reset = ath10k_pci_qca99x0_soft_chip_reset;
3674 pci_hard_reset = ath10k_pci_qca99x0_chip_reset;
3675 targ_cpu_to_ce_addr = ath10k_pci_qca99x0_targ_cpu_to_ce_addr;
3676 break;
3677 case QCA9888_2_0_DEVICE_ID:
3678 hw_rev = ATH10K_HW_QCA9888;
3679 pci_ps = false;
3680 pci_soft_reset = ath10k_pci_qca99x0_soft_chip_reset;
3681 pci_hard_reset = ath10k_pci_qca99x0_chip_reset;
3682 targ_cpu_to_ce_addr = ath10k_pci_qca99x0_targ_cpu_to_ce_addr;
3683 break;
3684 case QCA9377_1_0_DEVICE_ID:
3685 hw_rev = ATH10K_HW_QCA9377;
3686 pci_ps = true;
3687 pci_soft_reset = ath10k_pci_warm_reset;
3688 pci_hard_reset = ath10k_pci_qca6174_chip_reset;
3689 targ_cpu_to_ce_addr = ath10k_pci_qca6174_targ_cpu_to_ce_addr;
3690 break;
3691 default:
3692 WARN_ON(1);
3693 return -EOPNOTSUPP;
3694 }
3695
3696 ar = ath10k_core_create(sizeof(*ar_pci), &pdev->dev, ATH10K_BUS_PCI,
3697 hw_rev, &ath10k_pci_hif_ops);
3698 if (!ar) {
3699 dev_err(&pdev->dev, "failed to allocate core\n");
3700 return -ENOMEM;
3701 }
3702
3703 ath10k_dbg(ar, ATH10K_DBG_BOOT, "pci probe %04x:%04x %04x:%04x\n",
3704 pdev->vendor, pdev->device,
3705 pdev->subsystem_vendor, pdev->subsystem_device);
3706
3707 ar_pci = ath10k_pci_priv(ar);
3708 ar_pci->pdev = pdev;
3709 ar_pci->dev = &pdev->dev;
3710 ar_pci->ar = ar;
3711 ar->dev_id = pci_dev->device;
3712 ar_pci->pci_ps = pci_ps;
3713 ar_pci->ce.bus_ops = &ath10k_pci_bus_ops;
3714 ar_pci->pci_soft_reset = pci_soft_reset;
3715 ar_pci->pci_hard_reset = pci_hard_reset;
3716 ar_pci->targ_cpu_to_ce_addr = targ_cpu_to_ce_addr;
3717 ar->ce_priv = &ar_pci->ce;
3718
3719 ar->id.vendor = pdev->vendor;
3720 ar->id.device = pdev->device;
3721 ar->id.subsystem_vendor = pdev->subsystem_vendor;
3722 ar->id.subsystem_device = pdev->subsystem_device;
3723
3724 timer_setup(&ar_pci->ps_timer, ath10k_pci_ps_timer, 0);
3725
3726 ret = ath10k_pci_setup_resource(ar);
3727 if (ret) {
3728 ath10k_err(ar, "failed to setup resource: %d\n", ret);
3729 goto err_core_destroy;
3730 }
3731
3732 ret = ath10k_pci_claim(ar);
3733 if (ret) {
3734 ath10k_err(ar, "failed to claim device: %d\n", ret);
3735 goto err_free_pipes;
3736 }
3737
3738 ret = ath10k_pci_force_wake(ar);
3739 if (ret) {
3740 ath10k_warn(ar, "failed to wake up device : %d\n", ret);
3741 goto err_sleep;
3742 }
3743
3744 ath10k_pci_ce_deinit(ar);
3745 ath10k_pci_irq_disable(ar);
3746
3747 ret = ath10k_pci_init_irq(ar);
3748 if (ret) {
3749 ath10k_err(ar, "failed to init irqs: %d\n", ret);
3750 goto err_sleep;
3751 }
3752
3753 ath10k_info(ar, "pci irq %s oper_irq_mode %d irq_mode %d reset_mode %d\n",
3754 ath10k_pci_get_irq_method(ar), ar_pci->oper_irq_mode,
3755 ath10k_pci_irq_mode, ath10k_pci_reset_mode);
3756
3757 ret = ath10k_pci_request_irq(ar);
3758 if (ret) {
3759 ath10k_warn(ar, "failed to request irqs: %d\n", ret);
3760 goto err_deinit_irq;
3761 }
3762
3763 bus_params.dev_type = ATH10K_DEV_TYPE_LL;
3764 bus_params.link_can_suspend = true;
3765 /* Read CHIP_ID before reset to catch QCA9880-AR1A v1 devices that
3766 * fall off the bus during chip_reset. These chips have the same pci
3767 * device id as the QCA9880 BR4A or 2R4E. So that's why the check.
3768 */
3769 if (is_qca988x) {
3770 bus_params.chip_id =
3771 ath10k_pci_soc_read32(ar, SOC_CHIP_ID_ADDRESS);
3772 if (bus_params.chip_id != 0xffffffff) {
3773 if (!ath10k_pci_chip_is_supported(pdev->device,
3774 bus_params.chip_id)) {
3775 ret = -ENODEV;
3776 goto err_unsupported;
3777 }
3778 }
3779 }
3780
3781 ret = ath10k_pci_chip_reset(ar);
3782 if (ret) {
3783 ath10k_err(ar, "failed to reset chip: %d\n", ret);
3784 goto err_free_irq;
3785 }
3786
3787 bus_params.chip_id = ath10k_pci_soc_read32(ar, SOC_CHIP_ID_ADDRESS);
3788 if (bus_params.chip_id == 0xffffffff) {
3789 ret = -ENODEV;
3790 goto err_unsupported;
3791 }
3792
3793 if (!ath10k_pci_chip_is_supported(pdev->device, bus_params.chip_id)) {
3794 ret = -ENODEV;
3795 goto err_unsupported;
3796 }
3797
3798 ret = ath10k_core_register(ar, &bus_params);
3799 if (ret) {
3800 ath10k_err(ar, "failed to register driver core: %d\n", ret);
3801 goto err_free_irq;
3802 }
3803
3804 return 0;
3805
3806 err_unsupported:
3807 ath10k_err(ar, "device %04x with chip_id %08x isn't supported\n",
3808 pdev->device, bus_params.chip_id);
3809
3810 err_free_irq:
3811 ath10k_pci_free_irq(ar);
3812
3813 err_deinit_irq:
3814 ath10k_pci_release_resource(ar);
3815
3816 err_sleep:
3817 ath10k_pci_sleep_sync(ar);
3818 ath10k_pci_release(ar);
3819
3820 err_free_pipes:
3821 ath10k_pci_free_pipes(ar);
3822
3823 err_core_destroy:
3824 ath10k_core_destroy(ar);
3825
3826 return ret;
3827 }
3828
ath10k_pci_remove(struct pci_dev * pdev)3829 static void ath10k_pci_remove(struct pci_dev *pdev)
3830 {
3831 struct ath10k *ar = pci_get_drvdata(pdev);
3832
3833 ath10k_dbg(ar, ATH10K_DBG_PCI, "pci remove\n");
3834
3835 if (!ar)
3836 return;
3837
3838 ath10k_core_unregister(ar);
3839 ath10k_pci_free_irq(ar);
3840 ath10k_pci_deinit_irq(ar);
3841 ath10k_pci_release_resource(ar);
3842 ath10k_pci_sleep_sync(ar);
3843 ath10k_pci_release(ar);
3844 ath10k_core_destroy(ar);
3845 }
3846
3847 MODULE_DEVICE_TABLE(pci, ath10k_pci_id_table);
3848
3849 #ifdef CONFIG_PM
ath10k_pci_pm_suspend(struct device * dev)3850 static __maybe_unused int ath10k_pci_pm_suspend(struct device *dev)
3851 {
3852 struct ath10k *ar = dev_get_drvdata(dev);
3853 int ret;
3854
3855 ret = ath10k_pci_suspend(ar);
3856 if (ret)
3857 ath10k_warn(ar, "failed to suspend hif: %d\n", ret);
3858
3859 return ret;
3860 }
3861
ath10k_pci_pm_resume(struct device * dev)3862 static __maybe_unused int ath10k_pci_pm_resume(struct device *dev)
3863 {
3864 struct ath10k *ar = dev_get_drvdata(dev);
3865 int ret;
3866
3867 ret = ath10k_pci_resume(ar);
3868 if (ret)
3869 ath10k_warn(ar, "failed to resume hif: %d\n", ret);
3870
3871 return ret;
3872 }
3873
3874 static SIMPLE_DEV_PM_OPS(ath10k_pci_pm_ops,
3875 ath10k_pci_pm_suspend,
3876 ath10k_pci_pm_resume);
3877 #endif
3878
3879 static struct pci_driver ath10k_pci_driver = {
3880 .name = "ath10k_pci",
3881 .id_table = ath10k_pci_id_table,
3882 .probe = ath10k_pci_probe,
3883 .remove = ath10k_pci_remove,
3884 #ifdef CONFIG_PM
3885 .driver.pm = &ath10k_pci_pm_ops,
3886 #endif
3887 #if defined(__FreeBSD__)
3888 .bsddriver.name = KBUILD_MODNAME,
3889 /* Allow a possible native driver to attach. */
3890 .bsd_probe_return = (BUS_PROBE_DEFAULT - 1),
3891 #endif
3892 };
3893
ath10k_pci_init(void)3894 static int __init ath10k_pci_init(void)
3895 {
3896 int ret1, ret2;
3897
3898 ret1 = pci_register_driver(&ath10k_pci_driver);
3899 if (ret1)
3900 printk(KERN_ERR "failed to register ath10k pci driver: %d\n",
3901 ret1);
3902
3903 ret2 = ath10k_ahb_init();
3904 if (ret2)
3905 printk(KERN_ERR "ahb init failed: %d\n", ret2);
3906
3907 if (ret1 && ret2)
3908 return ret1;
3909
3910 /* registered to at least one bus */
3911 return 0;
3912 }
3913 module_init(ath10k_pci_init);
3914
ath10k_pci_exit(void)3915 static void __exit ath10k_pci_exit(void)
3916 {
3917 pci_unregister_driver(&ath10k_pci_driver);
3918 ath10k_ahb_exit();
3919 }
3920
3921 module_exit(ath10k_pci_exit);
3922
3923 MODULE_AUTHOR("Qualcomm Atheros");
3924 MODULE_DESCRIPTION("Driver support for Qualcomm Atheros PCIe/AHB 802.11ac WLAN devices");
3925 MODULE_LICENSE("Dual BSD/GPL");
3926
3927 /* QCA988x 2.0 firmware files */
3928 MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR "/" ATH10K_FW_API2_FILE);
3929 MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR "/" ATH10K_FW_API3_FILE);
3930 MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR "/" ATH10K_FW_API4_FILE);
3931 MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR "/" ATH10K_FW_API5_FILE);
3932 MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR "/" ATH10K_BOARD_DATA_FILE);
3933 MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR "/" ATH10K_BOARD_API2_FILE);
3934
3935 /* QCA9887 1.0 firmware files */
3936 MODULE_FIRMWARE(QCA9887_HW_1_0_FW_DIR "/" ATH10K_FW_API5_FILE);
3937 MODULE_FIRMWARE(QCA9887_HW_1_0_FW_DIR "/" ATH10K_BOARD_DATA_FILE);
3938 MODULE_FIRMWARE(QCA9887_HW_1_0_FW_DIR "/" ATH10K_BOARD_API2_FILE);
3939
3940 /* QCA6174 2.1 firmware files */
3941 MODULE_FIRMWARE(QCA6174_HW_2_1_FW_DIR "/" ATH10K_FW_API4_FILE);
3942 MODULE_FIRMWARE(QCA6174_HW_2_1_FW_DIR "/" ATH10K_FW_API5_FILE);
3943 MODULE_FIRMWARE(QCA6174_HW_2_1_FW_DIR "/" ATH10K_BOARD_DATA_FILE);
3944 MODULE_FIRMWARE(QCA6174_HW_2_1_FW_DIR "/" ATH10K_BOARD_API2_FILE);
3945
3946 /* QCA6174 3.1 firmware files */
3947 MODULE_FIRMWARE(QCA6174_HW_3_0_FW_DIR "/" ATH10K_FW_API4_FILE);
3948 MODULE_FIRMWARE(QCA6174_HW_3_0_FW_DIR "/" ATH10K_FW_API5_FILE);
3949 MODULE_FIRMWARE(QCA6174_HW_3_0_FW_DIR "/" ATH10K_FW_API6_FILE);
3950 MODULE_FIRMWARE(QCA6174_HW_3_0_FW_DIR "/" ATH10K_BOARD_DATA_FILE);
3951 MODULE_FIRMWARE(QCA6174_HW_3_0_FW_DIR "/" ATH10K_BOARD_API2_FILE);
3952
3953 /* QCA9377 1.0 firmware files */
3954 MODULE_FIRMWARE(QCA9377_HW_1_0_FW_DIR "/" ATH10K_FW_API6_FILE);
3955 MODULE_FIRMWARE(QCA9377_HW_1_0_FW_DIR "/" ATH10K_FW_API5_FILE);
3956 MODULE_FIRMWARE(QCA9377_HW_1_0_FW_DIR "/" ATH10K_BOARD_DATA_FILE);
3957