1 /* 2 * Copyright (c) 2007 Cisco Systems, Inc. All rights reserved. 3 * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved. 4 * 5 * This software is available to you under a choice of one of two 6 * licenses. You may choose to be licensed under the terms of the GNU 7 * General Public License (GPL) Version 2, available from the file 8 * COPYING in the main directory of this source tree, or the 9 * OpenIB.org BSD license below: 10 * 11 * Redistribution and use in source and binary forms, with or 12 * without modification, are permitted provided that the following 13 * conditions are met: 14 * 15 * - Redistributions of source code must retain the above 16 * copyright notice, this list of conditions and the following 17 * disclaimer. 18 * 19 * - Redistributions in binary form must reproduce the above 20 * copyright notice, this list of conditions and the following 21 * disclaimer in the documentation and/or other materials 22 * provided with the distribution. 23 * 24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 31 * SOFTWARE. 32 */ 33 34 #include <linux/log2.h> 35 #include <linux/slab.h> 36 #include <linux/netdevice.h> 37 #include <linux/bitops.h> 38 #include <linux/rcupdate.h> 39 #include <linux/etherdevice.h> 40 41 #include <rdma/ib_cache.h> 42 #include <rdma/ib_pack.h> 43 #include <rdma/ib_addr.h> 44 #include <rdma/ib_mad.h> 45 #include <rdma/uverbs_ioctl.h> 46 47 #include <dev/mlx4/cmd.h> 48 #include <dev/mlx4/qp.h> 49 #include <dev/mlx4/driver.h> 50 #include <linux/io.h> 51 52 #include "mlx4_ib.h" 53 #include <rdma/mlx4-abi.h> 54 55 static void mlx4_ib_lock_cqs(struct mlx4_ib_cq *send_cq, 56 struct mlx4_ib_cq *recv_cq); 57 static void mlx4_ib_unlock_cqs(struct mlx4_ib_cq *send_cq, 58 struct mlx4_ib_cq *recv_cq); 59 60 enum { 61 MLX4_IB_ACK_REQ_FREQ = 8, 62 }; 63 64 enum { 65 MLX4_IB_DEFAULT_SCHED_QUEUE = 0x83, 66 MLX4_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f, 67 MLX4_IB_LINK_TYPE_IB = 0, 68 MLX4_IB_LINK_TYPE_ETH = 1 69 }; 70 71 enum { 72 /* 73 * Largest possible UD header: send with GRH and immediate 74 * data plus 18 bytes for an Ethernet header with VLAN/802.1Q 75 * tag. (LRH would only use 8 bytes, so Ethernet is the 76 * biggest case) 77 */ 78 MLX4_IB_UD_HEADER_SIZE = 82, 79 MLX4_IB_LSO_HEADER_SPARE = 128, 80 }; 81 82 enum { 83 MLX4_IB_IBOE_ETHERTYPE = 0x8915 84 }; 85 86 struct mlx4_ib_sqp { 87 struct mlx4_ib_qp qp; 88 int pkey_index; 89 u32 qkey; 90 u32 send_psn; 91 struct ib_ud_header ud_header; 92 u8 header_buf[MLX4_IB_UD_HEADER_SIZE]; 93 struct ib_qp *roce_v2_gsi; 94 }; 95 96 enum { 97 MLX4_IB_MIN_SQ_STRIDE = 6, 98 MLX4_IB_CACHE_LINE_SIZE = 64, 99 }; 100 101 enum { 102 MLX4_RAW_QP_MTU = 7, 103 MLX4_RAW_QP_MSGMAX = 31, 104 }; 105 106 #ifndef ETH_ALEN 107 #define ETH_ALEN 6 108 #endif 109 110 static const __be32 mlx4_ib_opcode[] = { 111 [IB_WR_SEND] = cpu_to_be32(MLX4_OPCODE_SEND), 112 [IB_WR_LSO] = cpu_to_be32(MLX4_OPCODE_LSO), 113 [IB_WR_SEND_WITH_IMM] = cpu_to_be32(MLX4_OPCODE_SEND_IMM), 114 [IB_WR_RDMA_WRITE] = cpu_to_be32(MLX4_OPCODE_RDMA_WRITE), 115 [IB_WR_RDMA_WRITE_WITH_IMM] = cpu_to_be32(MLX4_OPCODE_RDMA_WRITE_IMM), 116 [IB_WR_RDMA_READ] = cpu_to_be32(MLX4_OPCODE_RDMA_READ), 117 [IB_WR_ATOMIC_CMP_AND_SWP] = cpu_to_be32(MLX4_OPCODE_ATOMIC_CS), 118 [IB_WR_ATOMIC_FETCH_AND_ADD] = cpu_to_be32(MLX4_OPCODE_ATOMIC_FA), 119 [IB_WR_SEND_WITH_INV] = cpu_to_be32(MLX4_OPCODE_SEND_INVAL), 120 [IB_WR_LOCAL_INV] = cpu_to_be32(MLX4_OPCODE_LOCAL_INVAL), 121 [IB_WR_REG_MR] = cpu_to_be32(MLX4_OPCODE_FMR), 122 [IB_WR_MASKED_ATOMIC_CMP_AND_SWP] = cpu_to_be32(MLX4_OPCODE_MASKED_ATOMIC_CS), 123 [IB_WR_MASKED_ATOMIC_FETCH_AND_ADD] = cpu_to_be32(MLX4_OPCODE_MASKED_ATOMIC_FA), 124 }; 125 126 static struct mlx4_ib_sqp *to_msqp(struct mlx4_ib_qp *mqp) 127 { 128 return container_of(mqp, struct mlx4_ib_sqp, qp); 129 } 130 131 static int is_tunnel_qp(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp) 132 { 133 if (!mlx4_is_master(dev->dev)) 134 return 0; 135 136 return qp->mqp.qpn >= dev->dev->phys_caps.base_tunnel_sqpn && 137 qp->mqp.qpn < dev->dev->phys_caps.base_tunnel_sqpn + 138 8 * MLX4_MFUNC_MAX; 139 } 140 141 static int is_sqp(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp) 142 { 143 int proxy_sqp = 0; 144 int real_sqp = 0; 145 int i; 146 /* PPF or Native -- real SQP */ 147 real_sqp = ((mlx4_is_master(dev->dev) || !mlx4_is_mfunc(dev->dev)) && 148 qp->mqp.qpn >= dev->dev->phys_caps.base_sqpn && 149 qp->mqp.qpn <= dev->dev->phys_caps.base_sqpn + 3); 150 if (real_sqp) 151 return 1; 152 /* VF or PF -- proxy SQP */ 153 if (mlx4_is_mfunc(dev->dev)) { 154 for (i = 0; i < dev->dev->caps.num_ports; i++) { 155 if (qp->mqp.qpn == dev->dev->caps.qp0_proxy[i] || 156 qp->mqp.qpn == dev->dev->caps.qp1_proxy[i]) { 157 proxy_sqp = 1; 158 break; 159 } 160 } 161 } 162 if (proxy_sqp) 163 return 1; 164 165 return !!(qp->flags & MLX4_IB_ROCE_V2_GSI_QP); 166 } 167 168 /* used for INIT/CLOSE port logic */ 169 static int is_qp0(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp) 170 { 171 int proxy_qp0 = 0; 172 int real_qp0 = 0; 173 int i; 174 /* PPF or Native -- real QP0 */ 175 real_qp0 = ((mlx4_is_master(dev->dev) || !mlx4_is_mfunc(dev->dev)) && 176 qp->mqp.qpn >= dev->dev->phys_caps.base_sqpn && 177 qp->mqp.qpn <= dev->dev->phys_caps.base_sqpn + 1); 178 if (real_qp0) 179 return 1; 180 /* VF or PF -- proxy QP0 */ 181 if (mlx4_is_mfunc(dev->dev)) { 182 for (i = 0; i < dev->dev->caps.num_ports; i++) { 183 if (qp->mqp.qpn == dev->dev->caps.qp0_proxy[i]) { 184 proxy_qp0 = 1; 185 break; 186 } 187 } 188 } 189 return proxy_qp0; 190 } 191 192 static void *get_wqe(struct mlx4_ib_qp *qp, int offset) 193 { 194 return mlx4_buf_offset(&qp->buf, offset); 195 } 196 197 static void *get_recv_wqe(struct mlx4_ib_qp *qp, int n) 198 { 199 return get_wqe(qp, qp->rq.offset + (n << qp->rq.wqe_shift)); 200 } 201 202 static void *get_send_wqe(struct mlx4_ib_qp *qp, int n) 203 { 204 return get_wqe(qp, qp->sq.offset + (n << qp->sq.wqe_shift)); 205 } 206 207 /* 208 * Stamp a SQ WQE so that it is invalid if prefetched by marking the 209 * first four bytes of every 64 byte chunk with 210 * 0x7FFFFFF | (invalid_ownership_value << 31). 211 * 212 * When the max work request size is less than or equal to the WQE 213 * basic block size, as an optimization, we can stamp all WQEs with 214 * 0xffffffff, and skip the very first chunk of each WQE. 215 */ 216 static void stamp_send_wqe(struct mlx4_ib_qp *qp, int n, int size) 217 { 218 __be32 *wqe; 219 int i; 220 int s; 221 int ind; 222 void *buf; 223 __be32 stamp; 224 struct mlx4_wqe_ctrl_seg *ctrl; 225 226 if (qp->sq_max_wqes_per_wr > 1) { 227 s = roundup(size, 1U << qp->sq.wqe_shift); 228 for (i = 0; i < s; i += 64) { 229 ind = (i >> qp->sq.wqe_shift) + n; 230 stamp = ind & qp->sq.wqe_cnt ? cpu_to_be32(0x7fffffff) : 231 cpu_to_be32(0xffffffff); 232 buf = get_send_wqe(qp, ind & (qp->sq.wqe_cnt - 1)); 233 wqe = buf + (i & ((1 << qp->sq.wqe_shift) - 1)); 234 *wqe = stamp; 235 } 236 } else { 237 ctrl = buf = get_send_wqe(qp, n & (qp->sq.wqe_cnt - 1)); 238 s = (ctrl->fence_size & 0x3f) << 4; 239 for (i = 64; i < s; i += 64) { 240 wqe = buf + i; 241 *wqe = cpu_to_be32(0xffffffff); 242 } 243 } 244 } 245 246 static void post_nop_wqe(struct mlx4_ib_qp *qp, int n, int size) 247 { 248 struct mlx4_wqe_ctrl_seg *ctrl; 249 struct mlx4_wqe_inline_seg *inl; 250 void *wqe; 251 int s; 252 253 ctrl = wqe = get_send_wqe(qp, n & (qp->sq.wqe_cnt - 1)); 254 s = sizeof(struct mlx4_wqe_ctrl_seg); 255 256 if (qp->ibqp.qp_type == IB_QPT_UD) { 257 struct mlx4_wqe_datagram_seg *dgram = wqe + sizeof *ctrl; 258 struct mlx4_av *av = (struct mlx4_av *)dgram->av; 259 memset(dgram, 0, sizeof *dgram); 260 av->port_pd = cpu_to_be32((qp->port << 24) | to_mpd(qp->ibqp.pd)->pdn); 261 s += sizeof(struct mlx4_wqe_datagram_seg); 262 } 263 264 /* Pad the remainder of the WQE with an inline data segment. */ 265 if (size > s) { 266 inl = wqe + s; 267 inl->byte_count = cpu_to_be32(1U << 31 | (size - s - sizeof *inl)); 268 } 269 ctrl->srcrb_flags = 0; 270 ctrl->fence_size = size / 16; 271 /* 272 * Make sure descriptor is fully written before setting ownership bit 273 * (because HW can start executing as soon as we do). 274 */ 275 wmb(); 276 277 ctrl->owner_opcode = cpu_to_be32(MLX4_OPCODE_NOP | MLX4_WQE_CTRL_NEC) | 278 (n & qp->sq.wqe_cnt ? cpu_to_be32(1U << 31) : 0); 279 280 stamp_send_wqe(qp, n + qp->sq_spare_wqes, size); 281 } 282 283 /* Post NOP WQE to prevent wrap-around in the middle of WR */ 284 static inline unsigned pad_wraparound(struct mlx4_ib_qp *qp, int ind) 285 { 286 unsigned s = qp->sq.wqe_cnt - (ind & (qp->sq.wqe_cnt - 1)); 287 if (unlikely(s < qp->sq_max_wqes_per_wr)) { 288 post_nop_wqe(qp, ind, s << qp->sq.wqe_shift); 289 ind += s; 290 } 291 return ind; 292 } 293 294 static void mlx4_ib_qp_event(struct mlx4_qp *qp, enum mlx4_event type) 295 { 296 struct ib_event event; 297 struct ib_qp *ibqp = &to_mibqp(qp)->ibqp; 298 299 if (type == MLX4_EVENT_TYPE_PATH_MIG) 300 to_mibqp(qp)->port = to_mibqp(qp)->alt_port; 301 302 if (ibqp->event_handler) { 303 event.device = ibqp->device; 304 event.element.qp = ibqp; 305 switch (type) { 306 case MLX4_EVENT_TYPE_PATH_MIG: 307 event.event = IB_EVENT_PATH_MIG; 308 break; 309 case MLX4_EVENT_TYPE_COMM_EST: 310 event.event = IB_EVENT_COMM_EST; 311 break; 312 case MLX4_EVENT_TYPE_SQ_DRAINED: 313 event.event = IB_EVENT_SQ_DRAINED; 314 break; 315 case MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE: 316 event.event = IB_EVENT_QP_LAST_WQE_REACHED; 317 break; 318 case MLX4_EVENT_TYPE_WQ_CATAS_ERROR: 319 event.event = IB_EVENT_QP_FATAL; 320 break; 321 case MLX4_EVENT_TYPE_PATH_MIG_FAILED: 322 event.event = IB_EVENT_PATH_MIG_ERR; 323 break; 324 case MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR: 325 event.event = IB_EVENT_QP_REQ_ERR; 326 break; 327 case MLX4_EVENT_TYPE_WQ_ACCESS_ERROR: 328 event.event = IB_EVENT_QP_ACCESS_ERR; 329 break; 330 default: 331 pr_warn("Unexpected event type %d " 332 "on QP %06x\n", type, qp->qpn); 333 return; 334 } 335 336 ibqp->event_handler(&event, ibqp->qp_context); 337 } 338 } 339 340 static int send_wqe_overhead(enum mlx4_ib_qp_type type, u32 flags) 341 { 342 /* 343 * UD WQEs must have a datagram segment. 344 * RC and UC WQEs might have a remote address segment. 345 * MLX WQEs need two extra inline data segments (for the UD 346 * header and space for the ICRC). 347 */ 348 switch (type) { 349 case MLX4_IB_QPT_UD: 350 return sizeof (struct mlx4_wqe_ctrl_seg) + 351 sizeof (struct mlx4_wqe_datagram_seg) + 352 ((flags & MLX4_IB_QP_LSO) ? MLX4_IB_LSO_HEADER_SPARE : 0); 353 case MLX4_IB_QPT_PROXY_SMI_OWNER: 354 case MLX4_IB_QPT_PROXY_SMI: 355 case MLX4_IB_QPT_PROXY_GSI: 356 return sizeof (struct mlx4_wqe_ctrl_seg) + 357 sizeof (struct mlx4_wqe_datagram_seg) + 64; 358 case MLX4_IB_QPT_TUN_SMI_OWNER: 359 case MLX4_IB_QPT_TUN_GSI: 360 return sizeof (struct mlx4_wqe_ctrl_seg) + 361 sizeof (struct mlx4_wqe_datagram_seg); 362 363 case MLX4_IB_QPT_UC: 364 return sizeof (struct mlx4_wqe_ctrl_seg) + 365 sizeof (struct mlx4_wqe_raddr_seg); 366 case MLX4_IB_QPT_RC: 367 return sizeof (struct mlx4_wqe_ctrl_seg) + 368 sizeof (struct mlx4_wqe_masked_atomic_seg) + 369 sizeof (struct mlx4_wqe_raddr_seg); 370 case MLX4_IB_QPT_SMI: 371 case MLX4_IB_QPT_GSI: 372 return sizeof (struct mlx4_wqe_ctrl_seg) + 373 ALIGN(MLX4_IB_UD_HEADER_SIZE + 374 DIV_ROUND_UP(MLX4_IB_UD_HEADER_SIZE, 375 MLX4_INLINE_ALIGN) * 376 sizeof (struct mlx4_wqe_inline_seg), 377 sizeof (struct mlx4_wqe_data_seg)) + 378 ALIGN(4 + 379 sizeof (struct mlx4_wqe_inline_seg), 380 sizeof (struct mlx4_wqe_data_seg)); 381 default: 382 return sizeof (struct mlx4_wqe_ctrl_seg); 383 } 384 } 385 386 static int set_rq_size(struct mlx4_ib_dev *dev, struct ib_qp_cap *cap, 387 int is_user, int has_rq, struct mlx4_ib_qp *qp) 388 { 389 /* Sanity check RQ size before proceeding */ 390 if (cap->max_recv_wr > dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE || 391 cap->max_recv_sge > min(dev->dev->caps.max_sq_sg, dev->dev->caps.max_rq_sg)) 392 return -EINVAL; 393 394 if (!has_rq) { 395 if (cap->max_recv_wr) 396 return -EINVAL; 397 398 qp->rq.wqe_cnt = qp->rq.max_gs = 0; 399 } else { 400 /* HW requires >= 1 RQ entry with >= 1 gather entry */ 401 if (is_user && (!cap->max_recv_wr || !cap->max_recv_sge)) 402 return -EINVAL; 403 404 qp->rq.wqe_cnt = roundup_pow_of_two(max(1U, cap->max_recv_wr)); 405 qp->rq.max_gs = roundup_pow_of_two(max(1U, cap->max_recv_sge)); 406 qp->rq.wqe_shift = ilog2(qp->rq.max_gs * sizeof (struct mlx4_wqe_data_seg)); 407 } 408 409 /* leave userspace return values as they were, so as not to break ABI */ 410 if (is_user) { 411 cap->max_recv_wr = qp->rq.max_post = qp->rq.wqe_cnt; 412 cap->max_recv_sge = qp->rq.max_gs; 413 } else { 414 cap->max_recv_wr = qp->rq.max_post = 415 min(dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE, qp->rq.wqe_cnt); 416 cap->max_recv_sge = min(qp->rq.max_gs, 417 min(dev->dev->caps.max_sq_sg, 418 dev->dev->caps.max_rq_sg)); 419 } 420 421 return 0; 422 } 423 424 static int set_kernel_sq_size(struct mlx4_ib_dev *dev, struct ib_qp_cap *cap, 425 enum mlx4_ib_qp_type type, struct mlx4_ib_qp *qp, 426 bool shrink_wqe) 427 { 428 int s; 429 430 /* Sanity check SQ size before proceeding */ 431 if (cap->max_send_wr > (dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE) || 432 cap->max_send_sge > min(dev->dev->caps.max_sq_sg, dev->dev->caps.max_rq_sg) || 433 cap->max_inline_data + send_wqe_overhead(type, qp->flags) + 434 sizeof (struct mlx4_wqe_inline_seg) > dev->dev->caps.max_sq_desc_sz) 435 return -EINVAL; 436 437 /* 438 * For MLX transport we need 2 extra S/G entries: 439 * one for the header and one for the checksum at the end 440 */ 441 if ((type == MLX4_IB_QPT_SMI || type == MLX4_IB_QPT_GSI || 442 type & (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER)) && 443 cap->max_send_sge + 2 > dev->dev->caps.max_sq_sg) 444 return -EINVAL; 445 446 s = max(cap->max_send_sge * sizeof (struct mlx4_wqe_data_seg), 447 cap->max_inline_data + sizeof (struct mlx4_wqe_inline_seg)) + 448 send_wqe_overhead(type, qp->flags); 449 450 if (s > dev->dev->caps.max_sq_desc_sz) 451 return -EINVAL; 452 453 /* 454 * Hermon supports shrinking WQEs, such that a single work 455 * request can include multiple units of 1 << wqe_shift. This 456 * way, work requests can differ in size, and do not have to 457 * be a power of 2 in size, saving memory and speeding up send 458 * WR posting. Unfortunately, if we do this then the 459 * wqe_index field in CQEs can't be used to look up the WR ID 460 * anymore, so we do this only if selective signaling is off. 461 * 462 * Further, on 32-bit platforms, we can't use vmap() to make 463 * the QP buffer virtually contiguous. Thus we have to use 464 * constant-sized WRs to make sure a WR is always fully within 465 * a single page-sized chunk. 466 * 467 * Finally, we use NOP work requests to pad the end of the 468 * work queue, to avoid wrap-around in the middle of WR. We 469 * set NEC bit to avoid getting completions with error for 470 * these NOP WRs, but since NEC is only supported starting 471 * with firmware 2.2.232, we use constant-sized WRs for older 472 * firmware. 473 * 474 * And, since MLX QPs only support SEND, we use constant-sized 475 * WRs in this case. 476 * 477 * We look for the smallest value of wqe_shift such that the 478 * resulting number of wqes does not exceed device 479 * capabilities. 480 * 481 * We set WQE size to at least 64 bytes, this way stamping 482 * invalidates each WQE. 483 */ 484 if (shrink_wqe && dev->dev->caps.fw_ver >= MLX4_FW_VER_WQE_CTRL_NEC && 485 qp->sq_signal_bits && BITS_PER_LONG == 64 && 486 type != MLX4_IB_QPT_SMI && type != MLX4_IB_QPT_GSI && 487 !(type & (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_PROXY_SMI | 488 MLX4_IB_QPT_PROXY_GSI | MLX4_IB_QPT_TUN_SMI_OWNER))) 489 qp->sq.wqe_shift = ilog2(64); 490 else 491 qp->sq.wqe_shift = order_base_2(s); 492 493 for (;;) { 494 qp->sq_max_wqes_per_wr = DIV_ROUND_UP(s, 1U << qp->sq.wqe_shift); 495 496 /* 497 * We need to leave 2 KB + 1 WR of headroom in the SQ to 498 * allow HW to prefetch. 499 */ 500 qp->sq_spare_wqes = (2048 >> qp->sq.wqe_shift) + qp->sq_max_wqes_per_wr; 501 qp->sq.wqe_cnt = roundup_pow_of_two(cap->max_send_wr * 502 qp->sq_max_wqes_per_wr + 503 qp->sq_spare_wqes); 504 505 if (qp->sq.wqe_cnt <= dev->dev->caps.max_wqes) 506 break; 507 508 if (qp->sq_max_wqes_per_wr <= 1) 509 return -EINVAL; 510 511 ++qp->sq.wqe_shift; 512 } 513 514 qp->sq.max_gs = (min(dev->dev->caps.max_sq_desc_sz, 515 (qp->sq_max_wqes_per_wr << qp->sq.wqe_shift)) - 516 send_wqe_overhead(type, qp->flags)) / 517 sizeof (struct mlx4_wqe_data_seg); 518 519 qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) + 520 (qp->sq.wqe_cnt << qp->sq.wqe_shift); 521 if (qp->rq.wqe_shift > qp->sq.wqe_shift) { 522 qp->rq.offset = 0; 523 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift; 524 } else { 525 qp->rq.offset = qp->sq.wqe_cnt << qp->sq.wqe_shift; 526 qp->sq.offset = 0; 527 } 528 529 cap->max_send_wr = qp->sq.max_post = 530 (qp->sq.wqe_cnt - qp->sq_spare_wqes) / qp->sq_max_wqes_per_wr; 531 cap->max_send_sge = min(qp->sq.max_gs, 532 min(dev->dev->caps.max_sq_sg, 533 dev->dev->caps.max_rq_sg)); 534 /* We don't support inline sends for kernel QPs (yet) */ 535 cap->max_inline_data = 0; 536 537 return 0; 538 } 539 540 static int set_user_sq_size(struct mlx4_ib_dev *dev, 541 struct mlx4_ib_qp *qp, 542 struct mlx4_ib_create_qp *ucmd) 543 { 544 /* Sanity check SQ size before proceeding */ 545 if ((1 << ucmd->log_sq_bb_count) > dev->dev->caps.max_wqes || 546 ucmd->log_sq_stride > 547 order_base_2(dev->dev->caps.max_sq_desc_sz) || 548 ucmd->log_sq_stride < MLX4_IB_MIN_SQ_STRIDE) 549 return -EINVAL; 550 551 qp->sq.wqe_cnt = 1 << ucmd->log_sq_bb_count; 552 qp->sq.wqe_shift = ucmd->log_sq_stride; 553 554 qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) + 555 (qp->sq.wqe_cnt << qp->sq.wqe_shift); 556 557 return 0; 558 } 559 560 static int alloc_proxy_bufs(struct ib_device *dev, struct mlx4_ib_qp *qp) 561 { 562 int i; 563 564 qp->sqp_proxy_rcv = 565 kmalloc_array(qp->rq.wqe_cnt, sizeof(struct mlx4_ib_buf), 566 GFP_KERNEL); 567 if (!qp->sqp_proxy_rcv) 568 return -ENOMEM; 569 for (i = 0; i < qp->rq.wqe_cnt; i++) { 570 qp->sqp_proxy_rcv[i].addr = 571 kmalloc(sizeof (struct mlx4_ib_proxy_sqp_hdr), 572 GFP_KERNEL); 573 if (!qp->sqp_proxy_rcv[i].addr) 574 goto err; 575 qp->sqp_proxy_rcv[i].map = 576 ib_dma_map_single(dev, qp->sqp_proxy_rcv[i].addr, 577 sizeof (struct mlx4_ib_proxy_sqp_hdr), 578 DMA_FROM_DEVICE); 579 if (ib_dma_mapping_error(dev, qp->sqp_proxy_rcv[i].map)) { 580 kfree(qp->sqp_proxy_rcv[i].addr); 581 goto err; 582 } 583 } 584 return 0; 585 586 err: 587 while (i > 0) { 588 --i; 589 ib_dma_unmap_single(dev, qp->sqp_proxy_rcv[i].map, 590 sizeof (struct mlx4_ib_proxy_sqp_hdr), 591 DMA_FROM_DEVICE); 592 kfree(qp->sqp_proxy_rcv[i].addr); 593 } 594 kfree(qp->sqp_proxy_rcv); 595 qp->sqp_proxy_rcv = NULL; 596 return -ENOMEM; 597 } 598 599 static void free_proxy_bufs(struct ib_device *dev, struct mlx4_ib_qp *qp) 600 { 601 int i; 602 603 for (i = 0; i < qp->rq.wqe_cnt; i++) { 604 ib_dma_unmap_single(dev, qp->sqp_proxy_rcv[i].map, 605 sizeof (struct mlx4_ib_proxy_sqp_hdr), 606 DMA_FROM_DEVICE); 607 kfree(qp->sqp_proxy_rcv[i].addr); 608 } 609 kfree(qp->sqp_proxy_rcv); 610 } 611 612 static int qp_has_rq(struct ib_qp_init_attr *attr) 613 { 614 if (attr->qp_type == IB_QPT_XRC_INI || attr->qp_type == IB_QPT_XRC_TGT) 615 return 0; 616 617 return !attr->srq; 618 } 619 620 static int qp0_enabled_vf(struct mlx4_dev *dev, int qpn) 621 { 622 int i; 623 for (i = 0; i < dev->caps.num_ports; i++) { 624 if (qpn == dev->caps.qp0_proxy[i]) 625 return !!dev->caps.qp0_qkey[i]; 626 } 627 return 0; 628 } 629 630 static void mlx4_ib_free_qp_counter(struct mlx4_ib_dev *dev, 631 struct mlx4_ib_qp *qp) 632 { 633 mutex_lock(&dev->counters_table[qp->port - 1].mutex); 634 mlx4_counter_free(dev->dev, qp->counter_index->index); 635 list_del(&qp->counter_index->list); 636 mutex_unlock(&dev->counters_table[qp->port - 1].mutex); 637 638 kfree(qp->counter_index); 639 qp->counter_index = NULL; 640 } 641 642 static int create_qp_common(struct mlx4_ib_dev *dev, struct ib_pd *pd, 643 struct ib_qp_init_attr *init_attr, 644 struct ib_udata *udata, int sqpn, struct mlx4_ib_qp **caller_qp, 645 gfp_t gfp) 646 { 647 int qpn; 648 int err; 649 struct ib_qp_cap backup_cap; 650 struct mlx4_ib_sqp *sqp; 651 struct mlx4_ib_qp *qp; 652 enum mlx4_ib_qp_type qp_type = (enum mlx4_ib_qp_type) init_attr->qp_type; 653 struct mlx4_ib_cq *mcq; 654 unsigned long flags; 655 656 /* When tunneling special qps, we use a plain UD qp */ 657 if (sqpn) { 658 if (mlx4_is_mfunc(dev->dev) && 659 (!mlx4_is_master(dev->dev) || 660 !(init_attr->create_flags & MLX4_IB_SRIOV_SQP))) { 661 if (init_attr->qp_type == IB_QPT_GSI) 662 qp_type = MLX4_IB_QPT_PROXY_GSI; 663 else { 664 if (mlx4_is_master(dev->dev) || 665 qp0_enabled_vf(dev->dev, sqpn)) 666 qp_type = MLX4_IB_QPT_PROXY_SMI_OWNER; 667 else 668 qp_type = MLX4_IB_QPT_PROXY_SMI; 669 } 670 } 671 qpn = sqpn; 672 /* add extra sg entry for tunneling */ 673 init_attr->cap.max_recv_sge++; 674 } else if (init_attr->create_flags & MLX4_IB_SRIOV_TUNNEL_QP) { 675 struct mlx4_ib_qp_tunnel_init_attr *tnl_init = 676 container_of(init_attr, 677 struct mlx4_ib_qp_tunnel_init_attr, init_attr); 678 if ((tnl_init->proxy_qp_type != IB_QPT_SMI && 679 tnl_init->proxy_qp_type != IB_QPT_GSI) || 680 !mlx4_is_master(dev->dev)) 681 return -EINVAL; 682 if (tnl_init->proxy_qp_type == IB_QPT_GSI) 683 qp_type = MLX4_IB_QPT_TUN_GSI; 684 else if (tnl_init->slave == mlx4_master_func_num(dev->dev) || 685 mlx4_vf_smi_enabled(dev->dev, tnl_init->slave, 686 tnl_init->port)) 687 qp_type = MLX4_IB_QPT_TUN_SMI_OWNER; 688 else 689 qp_type = MLX4_IB_QPT_TUN_SMI; 690 /* we are definitely in the PPF here, since we are creating 691 * tunnel QPs. base_tunnel_sqpn is therefore valid. */ 692 qpn = dev->dev->phys_caps.base_tunnel_sqpn + 8 * tnl_init->slave 693 + tnl_init->proxy_qp_type * 2 + tnl_init->port - 1; 694 sqpn = qpn; 695 } 696 697 if (!*caller_qp) { 698 if (qp_type == MLX4_IB_QPT_SMI || qp_type == MLX4_IB_QPT_GSI || 699 (qp_type & (MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_SMI_OWNER | 700 MLX4_IB_QPT_PROXY_GSI | MLX4_IB_QPT_TUN_SMI_OWNER))) { 701 sqp = kzalloc(sizeof (struct mlx4_ib_sqp), gfp); 702 if (!sqp) 703 return -ENOMEM; 704 qp = &sqp->qp; 705 qp->pri.vid = 0xFFFF; 706 qp->alt.vid = 0xFFFF; 707 } else { 708 qp = kzalloc(sizeof (struct mlx4_ib_qp), gfp); 709 if (!qp) 710 return -ENOMEM; 711 qp->pri.vid = 0xFFFF; 712 qp->alt.vid = 0xFFFF; 713 } 714 } else 715 qp = *caller_qp; 716 717 qp->mlx4_ib_qp_type = qp_type; 718 719 mutex_init(&qp->mutex); 720 spin_lock_init(&qp->sq.lock); 721 spin_lock_init(&qp->rq.lock); 722 INIT_LIST_HEAD(&qp->gid_list); 723 INIT_LIST_HEAD(&qp->steering_rules); 724 725 qp->state = IB_QPS_RESET; 726 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR) 727 qp->sq_signal_bits = cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE); 728 729 err = set_rq_size(dev, &init_attr->cap, !!pd->uobject, qp_has_rq(init_attr), qp); 730 if (err) 731 goto err; 732 733 if (pd->uobject) { 734 struct mlx4_ib_create_qp ucmd; 735 736 if (ib_copy_from_udata(&ucmd, udata, sizeof ucmd)) { 737 err = -EFAULT; 738 goto err; 739 } 740 741 qp->sq_no_prefetch = ucmd.sq_no_prefetch; 742 743 err = set_user_sq_size(dev, qp, &ucmd); 744 if (err) 745 goto err; 746 747 qp->umem = ib_umem_get(pd->uobject->context, ucmd.buf_addr, 748 qp->buf_size, 0, 0); 749 if (IS_ERR(qp->umem)) { 750 err = PTR_ERR(qp->umem); 751 goto err; 752 } 753 754 err = mlx4_mtt_init(dev->dev, ib_umem_page_count(qp->umem), 755 qp->umem->page_shift, &qp->mtt); 756 if (err) 757 goto err_buf; 758 759 err = mlx4_ib_umem_write_mtt(dev, &qp->mtt, qp->umem); 760 if (err) 761 goto err_mtt; 762 763 if (qp_has_rq(init_attr)) { 764 err = mlx4_ib_db_map_user(to_mucontext(pd->uobject->context), 765 ucmd.db_addr, &qp->db); 766 if (err) 767 goto err_mtt; 768 } 769 } else { 770 qp->sq_no_prefetch = 0; 771 772 if (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO) 773 qp->flags |= MLX4_IB_QP_LSO; 774 775 if (init_attr->create_flags & IB_QP_CREATE_NETIF_QP) { 776 if (dev->steering_support == 777 MLX4_STEERING_MODE_DEVICE_MANAGED) 778 qp->flags |= MLX4_IB_QP_NETIF; 779 else 780 goto err; 781 } 782 783 memcpy(&backup_cap, &init_attr->cap, sizeof(backup_cap)); 784 err = set_kernel_sq_size(dev, &init_attr->cap, 785 qp_type, qp, true); 786 if (err) 787 goto err; 788 789 if (qp_has_rq(init_attr)) { 790 err = mlx4_db_alloc(dev->dev, &qp->db, 0, gfp); 791 if (err) 792 goto err; 793 794 *qp->db.db = 0; 795 } 796 797 if (mlx4_buf_alloc(dev->dev, qp->buf_size, qp->buf_size, 798 &qp->buf, gfp)) { 799 memcpy(&init_attr->cap, &backup_cap, 800 sizeof(backup_cap)); 801 err = set_kernel_sq_size(dev, &init_attr->cap, qp_type, 802 qp, false); 803 if (err) 804 goto err_db; 805 806 if (mlx4_buf_alloc(dev->dev, qp->buf_size, 807 PAGE_SIZE * 2, &qp->buf, gfp)) { 808 err = -ENOMEM; 809 goto err_db; 810 } 811 } 812 813 err = mlx4_mtt_init(dev->dev, qp->buf.npages, qp->buf.page_shift, 814 &qp->mtt); 815 if (err) 816 goto err_buf; 817 818 err = mlx4_buf_write_mtt(dev->dev, &qp->mtt, &qp->buf, gfp); 819 if (err) 820 goto err_mtt; 821 822 qp->sq.wrid = kmalloc_array(qp->sq.wqe_cnt, sizeof(u64), 823 gfp | __GFP_NOWARN); 824 if (!qp->sq.wrid) 825 qp->sq.wrid = __vmalloc(qp->sq.wqe_cnt * sizeof(u64), 826 gfp, 0 /*PAGE_KERNEL*/); 827 qp->rq.wrid = kmalloc_array(qp->rq.wqe_cnt, sizeof(u64), 828 gfp | __GFP_NOWARN); 829 if (!qp->rq.wrid) 830 qp->rq.wrid = __vmalloc(qp->rq.wqe_cnt * sizeof(u64), 831 gfp, 0 /*PAGE_KERNEL*/); 832 if (!qp->sq.wrid || !qp->rq.wrid) { 833 err = -ENOMEM; 834 goto err_wrid; 835 } 836 } 837 838 if (sqpn) { 839 if (qp->mlx4_ib_qp_type & (MLX4_IB_QPT_PROXY_SMI_OWNER | 840 MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI)) { 841 if (alloc_proxy_bufs(pd->device, qp)) { 842 err = -ENOMEM; 843 goto err_wrid; 844 } 845 } 846 } else { 847 /* Raw packet QPNs may not have bits 6,7 set in their qp_num; 848 * otherwise, the WQE BlueFlame setup flow wrongly causes 849 * VLAN insertion. */ 850 if (init_attr->qp_type == IB_QPT_RAW_PACKET) 851 err = mlx4_qp_reserve_range(dev->dev, 1, 1, &qpn, 852 (init_attr->cap.max_send_wr ? 853 MLX4_RESERVE_ETH_BF_QP : 0) | 854 (init_attr->cap.max_recv_wr ? 855 MLX4_RESERVE_A0_QP : 0)); 856 else 857 if (qp->flags & MLX4_IB_QP_NETIF) 858 err = mlx4_ib_steer_qp_alloc(dev, 1, &qpn); 859 else 860 err = mlx4_qp_reserve_range(dev->dev, 1, 1, 861 &qpn, 0); 862 if (err) 863 goto err_proxy; 864 } 865 866 if (init_attr->create_flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK) 867 qp->flags |= MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK; 868 869 err = mlx4_qp_alloc(dev->dev, qpn, &qp->mqp, gfp); 870 if (err) 871 goto err_qpn; 872 873 if (init_attr->qp_type == IB_QPT_XRC_TGT) 874 qp->mqp.qpn |= (1 << 23); 875 876 /* 877 * Hardware wants QPN written in big-endian order (after 878 * shifting) for send doorbell. Precompute this value to save 879 * a little bit when posting sends. 880 */ 881 qp->doorbell_qpn = swab32(qp->mqp.qpn << 8); 882 883 qp->mqp.event = mlx4_ib_qp_event; 884 if (!*caller_qp) 885 *caller_qp = qp; 886 887 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags); 888 mlx4_ib_lock_cqs(to_mcq(init_attr->send_cq), 889 to_mcq(init_attr->recv_cq)); 890 /* Maintain device to QPs access, needed for further handling 891 * via reset flow 892 */ 893 list_add_tail(&qp->qps_list, &dev->qp_list); 894 /* Maintain CQ to QPs access, needed for further handling 895 * via reset flow 896 */ 897 mcq = to_mcq(init_attr->send_cq); 898 list_add_tail(&qp->cq_send_list, &mcq->send_qp_list); 899 mcq = to_mcq(init_attr->recv_cq); 900 list_add_tail(&qp->cq_recv_list, &mcq->recv_qp_list); 901 mlx4_ib_unlock_cqs(to_mcq(init_attr->send_cq), 902 to_mcq(init_attr->recv_cq)); 903 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags); 904 return 0; 905 906 err_qpn: 907 if (!sqpn) { 908 if (qp->flags & MLX4_IB_QP_NETIF) 909 mlx4_ib_steer_qp_free(dev, qpn, 1); 910 else 911 mlx4_qp_release_range(dev->dev, qpn, 1); 912 } 913 err_proxy: 914 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI) 915 free_proxy_bufs(pd->device, qp); 916 err_wrid: 917 if (pd->uobject) { 918 if (qp_has_rq(init_attr)) 919 mlx4_ib_db_unmap_user(to_mucontext(pd->uobject->context), &qp->db); 920 } else { 921 kvfree(qp->sq.wrid); 922 kvfree(qp->rq.wrid); 923 } 924 925 err_mtt: 926 mlx4_mtt_cleanup(dev->dev, &qp->mtt); 927 928 err_buf: 929 if (pd->uobject) 930 ib_umem_release(qp->umem); 931 else 932 mlx4_buf_free(dev->dev, qp->buf_size, &qp->buf); 933 934 err_db: 935 if (!pd->uobject && qp_has_rq(init_attr)) 936 mlx4_db_free(dev->dev, &qp->db); 937 938 err: 939 if (!*caller_qp) 940 kfree(qp); 941 return err; 942 } 943 944 static enum mlx4_qp_state to_mlx4_state(enum ib_qp_state state) 945 { 946 switch (state) { 947 case IB_QPS_RESET: return MLX4_QP_STATE_RST; 948 case IB_QPS_INIT: return MLX4_QP_STATE_INIT; 949 case IB_QPS_RTR: return MLX4_QP_STATE_RTR; 950 case IB_QPS_RTS: return MLX4_QP_STATE_RTS; 951 case IB_QPS_SQD: return MLX4_QP_STATE_SQD; 952 case IB_QPS_SQE: return MLX4_QP_STATE_SQER; 953 case IB_QPS_ERR: return MLX4_QP_STATE_ERR; 954 default: return -1; 955 } 956 } 957 958 static void mlx4_ib_lock_cqs(struct mlx4_ib_cq *send_cq, struct mlx4_ib_cq *recv_cq) 959 __acquires(&send_cq->lock) __acquires(&recv_cq->lock) 960 { 961 if (send_cq == recv_cq) { 962 spin_lock(&send_cq->lock); 963 __acquire(&recv_cq->lock); 964 } else if (send_cq->mcq.cqn < recv_cq->mcq.cqn) { 965 spin_lock(&send_cq->lock); 966 spin_lock_nested(&recv_cq->lock, SINGLE_DEPTH_NESTING); 967 } else { 968 spin_lock(&recv_cq->lock); 969 spin_lock_nested(&send_cq->lock, SINGLE_DEPTH_NESTING); 970 } 971 } 972 973 static void mlx4_ib_unlock_cqs(struct mlx4_ib_cq *send_cq, struct mlx4_ib_cq *recv_cq) 974 __releases(&send_cq->lock) __releases(&recv_cq->lock) 975 { 976 if (send_cq == recv_cq) { 977 __release(&recv_cq->lock); 978 spin_unlock(&send_cq->lock); 979 } else if (send_cq->mcq.cqn < recv_cq->mcq.cqn) { 980 spin_unlock(&recv_cq->lock); 981 spin_unlock(&send_cq->lock); 982 } else { 983 spin_unlock(&send_cq->lock); 984 spin_unlock(&recv_cq->lock); 985 } 986 } 987 988 static void del_gid_entries(struct mlx4_ib_qp *qp) 989 { 990 struct mlx4_ib_gid_entry *ge, *tmp; 991 992 list_for_each_entry_safe(ge, tmp, &qp->gid_list, list) { 993 list_del(&ge->list); 994 kfree(ge); 995 } 996 } 997 998 static struct mlx4_ib_pd *get_pd(struct mlx4_ib_qp *qp) 999 { 1000 if (qp->ibqp.qp_type == IB_QPT_XRC_TGT) 1001 return to_mpd(to_mxrcd(qp->ibqp.xrcd)->pd); 1002 else 1003 return to_mpd(qp->ibqp.pd); 1004 } 1005 1006 static void get_cqs(struct mlx4_ib_qp *qp, 1007 struct mlx4_ib_cq **send_cq, struct mlx4_ib_cq **recv_cq) 1008 { 1009 switch (qp->ibqp.qp_type) { 1010 case IB_QPT_XRC_TGT: 1011 *send_cq = to_mcq(to_mxrcd(qp->ibqp.xrcd)->cq); 1012 *recv_cq = *send_cq; 1013 break; 1014 case IB_QPT_XRC_INI: 1015 *send_cq = to_mcq(qp->ibqp.send_cq); 1016 *recv_cq = *send_cq; 1017 break; 1018 default: 1019 *send_cq = to_mcq(qp->ibqp.send_cq); 1020 *recv_cq = to_mcq(qp->ibqp.recv_cq); 1021 break; 1022 } 1023 } 1024 1025 static void destroy_qp_common(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp, 1026 struct ib_udata *udata) 1027 { 1028 struct mlx4_ib_cq *send_cq, *recv_cq; 1029 unsigned long flags; 1030 1031 if (qp->state != IB_QPS_RESET) { 1032 if (mlx4_qp_modify(dev->dev, NULL, to_mlx4_state(qp->state), 1033 MLX4_QP_STATE_RST, NULL, 0, 0, &qp->mqp)) 1034 pr_warn("modify QP %06x to RESET failed.\n", 1035 qp->mqp.qpn); 1036 if (qp->pri.smac || (!qp->pri.smac && qp->pri.smac_port)) { 1037 mlx4_unregister_mac(dev->dev, qp->pri.smac_port, qp->pri.smac); 1038 qp->pri.smac = 0; 1039 qp->pri.smac_port = 0; 1040 } 1041 if (qp->alt.smac) { 1042 mlx4_unregister_mac(dev->dev, qp->alt.smac_port, qp->alt.smac); 1043 qp->alt.smac = 0; 1044 } 1045 if (qp->pri.vid < 0x1000) { 1046 mlx4_unregister_vlan(dev->dev, qp->pri.vlan_port, qp->pri.vid); 1047 qp->pri.vid = 0xFFFF; 1048 qp->pri.candidate_vid = 0xFFFF; 1049 qp->pri.update_vid = 0; 1050 } 1051 if (qp->alt.vid < 0x1000) { 1052 mlx4_unregister_vlan(dev->dev, qp->alt.vlan_port, qp->alt.vid); 1053 qp->alt.vid = 0xFFFF; 1054 qp->alt.candidate_vid = 0xFFFF; 1055 qp->alt.update_vid = 0; 1056 } 1057 } 1058 1059 get_cqs(qp, &send_cq, &recv_cq); 1060 1061 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags); 1062 mlx4_ib_lock_cqs(send_cq, recv_cq); 1063 1064 /* del from lists under both locks above to protect reset flow paths */ 1065 list_del(&qp->qps_list); 1066 list_del(&qp->cq_send_list); 1067 list_del(&qp->cq_recv_list); 1068 if (!udata) { 1069 __mlx4_ib_cq_clean(recv_cq, qp->mqp.qpn, 1070 qp->ibqp.srq ? to_msrq(qp->ibqp.srq): NULL); 1071 if (send_cq != recv_cq) 1072 __mlx4_ib_cq_clean(send_cq, qp->mqp.qpn, NULL); 1073 } 1074 1075 mlx4_qp_remove(dev->dev, &qp->mqp); 1076 1077 mlx4_ib_unlock_cqs(send_cq, recv_cq); 1078 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags); 1079 1080 mlx4_qp_free(dev->dev, &qp->mqp); 1081 1082 if (!is_sqp(dev, qp) && !is_tunnel_qp(dev, qp)) { 1083 if (qp->flags & MLX4_IB_QP_NETIF) 1084 mlx4_ib_steer_qp_free(dev, qp->mqp.qpn, 1); 1085 else 1086 mlx4_qp_release_range(dev->dev, qp->mqp.qpn, 1); 1087 } 1088 1089 mlx4_mtt_cleanup(dev->dev, &qp->mtt); 1090 1091 if (udata) { 1092 if (qp->rq.wqe_cnt) { 1093 struct mlx4_ib_ucontext *mcontext = 1094 rdma_udata_to_drv_context( 1095 udata, 1096 struct mlx4_ib_ucontext, 1097 ibucontext); 1098 1099 mlx4_ib_db_unmap_user(mcontext, &qp->db); 1100 } 1101 } else { 1102 kvfree(qp->sq.wrid); 1103 kvfree(qp->rq.wrid); 1104 if (qp->mlx4_ib_qp_type & (MLX4_IB_QPT_PROXY_SMI_OWNER | 1105 MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI)) 1106 free_proxy_bufs(&dev->ib_dev, qp); 1107 mlx4_buf_free(dev->dev, qp->buf_size, &qp->buf); 1108 if (qp->rq.wqe_cnt) 1109 mlx4_db_free(dev->dev, &qp->db); 1110 } 1111 ib_umem_release(qp->umem); 1112 1113 del_gid_entries(qp); 1114 } 1115 1116 static u32 get_sqp_num(struct mlx4_ib_dev *dev, struct ib_qp_init_attr *attr) 1117 { 1118 /* Native or PPF */ 1119 if (!mlx4_is_mfunc(dev->dev) || 1120 (mlx4_is_master(dev->dev) && 1121 attr->create_flags & MLX4_IB_SRIOV_SQP)) { 1122 return dev->dev->phys_caps.base_sqpn + 1123 (attr->qp_type == IB_QPT_SMI ? 0 : 2) + 1124 attr->port_num - 1; 1125 } 1126 /* PF or VF -- creating proxies */ 1127 if (attr->qp_type == IB_QPT_SMI) 1128 return dev->dev->caps.qp0_proxy[attr->port_num - 1]; 1129 else 1130 return dev->dev->caps.qp1_proxy[attr->port_num - 1]; 1131 } 1132 1133 static struct ib_qp *_mlx4_ib_create_qp(struct ib_pd *pd, 1134 struct ib_qp_init_attr *init_attr, 1135 struct ib_udata *udata) 1136 { 1137 struct mlx4_ib_qp *qp = NULL; 1138 int err; 1139 int sup_u_create_flags = MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK; 1140 u16 xrcdn = 0; 1141 gfp_t gfp; 1142 1143 gfp = (init_attr->create_flags & MLX4_IB_QP_CREATE_USE_GFP_NOIO) ? 1144 GFP_NOIO : GFP_KERNEL; 1145 /* 1146 * We only support LSO, vendor flag1, and multicast loopback blocking, 1147 * and only for kernel UD QPs. 1148 */ 1149 if (init_attr->create_flags & ~(MLX4_IB_QP_LSO | 1150 MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK | 1151 MLX4_IB_SRIOV_TUNNEL_QP | 1152 MLX4_IB_SRIOV_SQP | 1153 MLX4_IB_QP_NETIF | 1154 MLX4_IB_QP_CREATE_ROCE_V2_GSI | 1155 MLX4_IB_QP_CREATE_USE_GFP_NOIO)) 1156 return ERR_PTR(-EINVAL); 1157 1158 if (init_attr->create_flags & IB_QP_CREATE_NETIF_QP) { 1159 if (init_attr->qp_type != IB_QPT_UD) 1160 return ERR_PTR(-EINVAL); 1161 } 1162 1163 if (init_attr->create_flags) { 1164 if (udata && init_attr->create_flags & ~(sup_u_create_flags)) 1165 return ERR_PTR(-EINVAL); 1166 1167 if ((init_attr->create_flags & ~(MLX4_IB_SRIOV_SQP | 1168 MLX4_IB_QP_CREATE_USE_GFP_NOIO | 1169 MLX4_IB_QP_CREATE_ROCE_V2_GSI | 1170 MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK) && 1171 init_attr->qp_type != IB_QPT_UD) || 1172 (init_attr->create_flags & MLX4_IB_SRIOV_SQP && 1173 init_attr->qp_type > IB_QPT_GSI) || 1174 (init_attr->create_flags & MLX4_IB_QP_CREATE_ROCE_V2_GSI && 1175 init_attr->qp_type != IB_QPT_GSI)) 1176 return ERR_PTR(-EINVAL); 1177 } 1178 1179 switch (init_attr->qp_type) { 1180 case IB_QPT_XRC_TGT: 1181 pd = to_mxrcd(init_attr->xrcd)->pd; 1182 xrcdn = to_mxrcd(init_attr->xrcd)->xrcdn; 1183 init_attr->send_cq = to_mxrcd(init_attr->xrcd)->cq; 1184 /* fall through */ 1185 case IB_QPT_XRC_INI: 1186 if (!(to_mdev(pd->device)->dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC)) 1187 return ERR_PTR(-ENOSYS); 1188 init_attr->recv_cq = init_attr->send_cq; 1189 /* fall through */ 1190 case IB_QPT_RC: 1191 case IB_QPT_UC: 1192 case IB_QPT_RAW_PACKET: 1193 qp = kzalloc(sizeof *qp, gfp); 1194 if (!qp) 1195 return ERR_PTR(-ENOMEM); 1196 qp->pri.vid = 0xFFFF; 1197 qp->alt.vid = 0xFFFF; 1198 /* fall through */ 1199 case IB_QPT_UD: 1200 { 1201 err = create_qp_common(to_mdev(pd->device), pd, init_attr, 1202 udata, 0, &qp, gfp); 1203 if (err) { 1204 kfree(qp); 1205 return ERR_PTR(err); 1206 } 1207 1208 qp->ibqp.qp_num = qp->mqp.qpn; 1209 qp->xrcdn = xrcdn; 1210 1211 break; 1212 } 1213 case IB_QPT_SMI: 1214 case IB_QPT_GSI: 1215 { 1216 int sqpn; 1217 1218 /* Userspace is not allowed to create special QPs: */ 1219 if (udata) 1220 return ERR_PTR(-EINVAL); 1221 if (init_attr->create_flags & MLX4_IB_QP_CREATE_ROCE_V2_GSI) { 1222 int res = mlx4_qp_reserve_range(to_mdev(pd->device)->dev, 1, 1, &sqpn, 0); 1223 1224 if (res) 1225 return ERR_PTR(res); 1226 } else { 1227 sqpn = get_sqp_num(to_mdev(pd->device), init_attr); 1228 } 1229 1230 err = create_qp_common(to_mdev(pd->device), pd, init_attr, udata, 1231 sqpn, 1232 &qp, gfp); 1233 if (err) 1234 return ERR_PTR(err); 1235 1236 qp->port = init_attr->port_num; 1237 qp->ibqp.qp_num = init_attr->qp_type == IB_QPT_SMI ? 0 : 1238 init_attr->create_flags & MLX4_IB_QP_CREATE_ROCE_V2_GSI ? sqpn : 1; 1239 break; 1240 } 1241 default: 1242 /* Don't support raw QPs */ 1243 return ERR_PTR(-EINVAL); 1244 } 1245 1246 return &qp->ibqp; 1247 } 1248 1249 struct ib_qp *mlx4_ib_create_qp(struct ib_pd *pd, 1250 struct ib_qp_init_attr *init_attr, 1251 struct ib_udata *udata) { 1252 struct ib_device *device = pd ? pd->device : init_attr->xrcd->device; 1253 struct ib_qp *ibqp; 1254 struct mlx4_ib_dev *dev = to_mdev(device); 1255 1256 ibqp = _mlx4_ib_create_qp(pd, init_attr, udata); 1257 1258 if (!IS_ERR(ibqp) && 1259 (init_attr->qp_type == IB_QPT_GSI) && 1260 !(init_attr->create_flags & MLX4_IB_QP_CREATE_ROCE_V2_GSI)) { 1261 struct mlx4_ib_sqp *sqp = to_msqp((to_mqp(ibqp))); 1262 int is_eth = rdma_cap_eth_ah(&dev->ib_dev, init_attr->port_num); 1263 1264 if (is_eth && 1265 dev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ROCE_V1_V2) { 1266 init_attr->create_flags |= MLX4_IB_QP_CREATE_ROCE_V2_GSI; 1267 sqp->roce_v2_gsi = ib_create_qp(pd, init_attr); 1268 1269 if (IS_ERR(sqp->roce_v2_gsi)) { 1270 pr_err("Failed to create GSI QP for RoCEv2 (%ld)\n", PTR_ERR(sqp->roce_v2_gsi)); 1271 sqp->roce_v2_gsi = NULL; 1272 } else { 1273 sqp = to_msqp(to_mqp(sqp->roce_v2_gsi)); 1274 sqp->qp.flags |= MLX4_IB_ROCE_V2_GSI_QP; 1275 } 1276 1277 init_attr->create_flags &= ~MLX4_IB_QP_CREATE_ROCE_V2_GSI; 1278 } 1279 } 1280 return ibqp; 1281 } 1282 1283 static int _mlx4_ib_destroy_qp(struct ib_qp *qp, struct ib_udata *udata) 1284 { 1285 struct mlx4_ib_dev *dev = to_mdev(qp->device); 1286 struct mlx4_ib_qp *mqp = to_mqp(qp); 1287 1288 if (is_qp0(dev, mqp)) 1289 mlx4_CLOSE_PORT(dev->dev, mqp->port); 1290 1291 if (dev->qp1_proxy[mqp->port - 1] == mqp) { 1292 mutex_lock(&dev->qp1_proxy_lock[mqp->port - 1]); 1293 dev->qp1_proxy[mqp->port - 1] = NULL; 1294 mutex_unlock(&dev->qp1_proxy_lock[mqp->port - 1]); 1295 } 1296 1297 if (mqp->counter_index) 1298 mlx4_ib_free_qp_counter(dev, mqp); 1299 1300 destroy_qp_common(dev, mqp, udata); 1301 1302 if (is_sqp(dev, mqp)) 1303 kfree(to_msqp(mqp)); 1304 else 1305 kfree(mqp); 1306 1307 return 0; 1308 } 1309 1310 int mlx4_ib_destroy_qp(struct ib_qp *qp, struct ib_udata *udata) 1311 { 1312 struct mlx4_ib_qp *mqp = to_mqp(qp); 1313 1314 if (mqp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI) { 1315 struct mlx4_ib_sqp *sqp = to_msqp(mqp); 1316 1317 if (sqp->roce_v2_gsi) 1318 ib_destroy_qp(sqp->roce_v2_gsi); 1319 } 1320 1321 return _mlx4_ib_destroy_qp(qp, udata); 1322 } 1323 1324 static int to_mlx4_st(struct mlx4_ib_dev *dev, enum mlx4_ib_qp_type type) 1325 { 1326 switch (type) { 1327 case MLX4_IB_QPT_RC: return MLX4_QP_ST_RC; 1328 case MLX4_IB_QPT_UC: return MLX4_QP_ST_UC; 1329 case MLX4_IB_QPT_UD: return MLX4_QP_ST_UD; 1330 case MLX4_IB_QPT_XRC_INI: 1331 case MLX4_IB_QPT_XRC_TGT: return MLX4_QP_ST_XRC; 1332 case MLX4_IB_QPT_SMI: 1333 case MLX4_IB_QPT_GSI: 1334 case MLX4_IB_QPT_RAW_PACKET: return MLX4_QP_ST_MLX; 1335 1336 case MLX4_IB_QPT_PROXY_SMI_OWNER: 1337 case MLX4_IB_QPT_TUN_SMI_OWNER: return (mlx4_is_mfunc(dev->dev) ? 1338 MLX4_QP_ST_MLX : -1); 1339 case MLX4_IB_QPT_PROXY_SMI: 1340 case MLX4_IB_QPT_TUN_SMI: 1341 case MLX4_IB_QPT_PROXY_GSI: 1342 case MLX4_IB_QPT_TUN_GSI: return (mlx4_is_mfunc(dev->dev) ? 1343 MLX4_QP_ST_UD : -1); 1344 default: return -1; 1345 } 1346 } 1347 1348 static __be32 to_mlx4_access_flags(struct mlx4_ib_qp *qp, const struct ib_qp_attr *attr, 1349 int attr_mask) 1350 { 1351 u8 dest_rd_atomic; 1352 u32 access_flags; 1353 u32 hw_access_flags = 0; 1354 1355 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) 1356 dest_rd_atomic = attr->max_dest_rd_atomic; 1357 else 1358 dest_rd_atomic = qp->resp_depth; 1359 1360 if (attr_mask & IB_QP_ACCESS_FLAGS) 1361 access_flags = attr->qp_access_flags; 1362 else 1363 access_flags = qp->atomic_rd_en; 1364 1365 if (!dest_rd_atomic) 1366 access_flags &= IB_ACCESS_REMOTE_WRITE; 1367 1368 if (access_flags & IB_ACCESS_REMOTE_READ) 1369 hw_access_flags |= MLX4_QP_BIT_RRE; 1370 if (access_flags & IB_ACCESS_REMOTE_ATOMIC) 1371 hw_access_flags |= MLX4_QP_BIT_RAE; 1372 if (access_flags & IB_ACCESS_REMOTE_WRITE) 1373 hw_access_flags |= MLX4_QP_BIT_RWE; 1374 1375 return cpu_to_be32(hw_access_flags); 1376 } 1377 1378 static void store_sqp_attrs(struct mlx4_ib_sqp *sqp, const struct ib_qp_attr *attr, 1379 int attr_mask) 1380 { 1381 if (attr_mask & IB_QP_PKEY_INDEX) 1382 sqp->pkey_index = attr->pkey_index; 1383 if (attr_mask & IB_QP_QKEY) 1384 sqp->qkey = attr->qkey; 1385 if (attr_mask & IB_QP_SQ_PSN) 1386 sqp->send_psn = attr->sq_psn; 1387 } 1388 1389 static void mlx4_set_sched(struct mlx4_qp_path *path, u8 port) 1390 { 1391 path->sched_queue = (path->sched_queue & 0xbf) | ((port - 1) << 6); 1392 } 1393 1394 static int _mlx4_set_path(struct mlx4_ib_dev *dev, const struct rdma_ah_attr *ah, 1395 u64 smac, u16 vlan_tag, struct mlx4_qp_path *path, 1396 struct mlx4_roce_smac_vlan_info *smac_info, u8 port) 1397 { 1398 int vidx; 1399 int smac_index; 1400 int err; 1401 1402 path->grh_mylmc = rdma_ah_get_path_bits(ah) & 0x7f; 1403 path->rlid = cpu_to_be16(rdma_ah_get_dlid(ah)); 1404 if (rdma_ah_get_static_rate(ah)) { 1405 path->static_rate = rdma_ah_get_static_rate(ah) + 1406 MLX4_STAT_RATE_OFFSET; 1407 while (path->static_rate > IB_RATE_2_5_GBPS + MLX4_STAT_RATE_OFFSET && 1408 !(1 << path->static_rate & dev->dev->caps.stat_rate_support)) 1409 --path->static_rate; 1410 } else 1411 path->static_rate = 0; 1412 1413 if (rdma_ah_get_ah_flags(ah) & IB_AH_GRH) { 1414 const struct ib_global_route *grh = rdma_ah_read_grh(ah); 1415 int real_sgid_index = 1416 mlx4_ib_gid_index_to_real_index(dev, grh->sgid_attr); 1417 1418 if (real_sgid_index < 0) 1419 return real_sgid_index; 1420 if (real_sgid_index >= dev->dev->caps.gid_table_len[port]) { 1421 pr_err("sgid_index (%u) too large. max is %d\n", 1422 real_sgid_index, dev->dev->caps.gid_table_len[port] - 1); 1423 return -1; 1424 } 1425 1426 path->grh_mylmc |= 1 << 7; 1427 path->mgid_index = real_sgid_index; 1428 path->hop_limit = grh->hop_limit; 1429 path->tclass_flowlabel = 1430 cpu_to_be32((grh->traffic_class << 20) | 1431 (grh->flow_label)); 1432 memcpy(path->rgid, grh->dgid.raw, 16); 1433 } 1434 1435 if (ah->type == RDMA_AH_ATTR_TYPE_ROCE) { 1436 if (!(rdma_ah_get_ah_flags(ah) & IB_AH_GRH)) 1437 return -1; 1438 1439 path->sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE | 1440 ((port - 1) << 6) | ((rdma_ah_get_sl(ah) & 7) << 3); 1441 1442 path->feup |= MLX4_FEUP_FORCE_ETH_UP; 1443 if (vlan_tag < 0x1000) { 1444 if (smac_info->vid < 0x1000) { 1445 /* both valid vlan ids */ 1446 if (smac_info->vid != vlan_tag) { 1447 /* different VIDs. unreg old and reg new */ 1448 err = mlx4_register_vlan(dev->dev, port, vlan_tag, &vidx); 1449 if (err) 1450 return err; 1451 smac_info->candidate_vid = vlan_tag; 1452 smac_info->candidate_vlan_index = vidx; 1453 smac_info->candidate_vlan_port = port; 1454 smac_info->update_vid = 1; 1455 path->vlan_index = vidx; 1456 } else { 1457 path->vlan_index = smac_info->vlan_index; 1458 } 1459 } else { 1460 /* no current vlan tag in qp */ 1461 err = mlx4_register_vlan(dev->dev, port, vlan_tag, &vidx); 1462 if (err) 1463 return err; 1464 smac_info->candidate_vid = vlan_tag; 1465 smac_info->candidate_vlan_index = vidx; 1466 smac_info->candidate_vlan_port = port; 1467 smac_info->update_vid = 1; 1468 path->vlan_index = vidx; 1469 } 1470 path->feup |= MLX4_FVL_FORCE_ETH_VLAN; 1471 path->fl = 1 << 6; 1472 } else { 1473 /* have current vlan tag. unregister it at modify-qp success */ 1474 if (smac_info->vid < 0x1000) { 1475 smac_info->candidate_vid = 0xFFFF; 1476 smac_info->update_vid = 1; 1477 } 1478 } 1479 1480 /* get smac_index for RoCE use. 1481 * If no smac was yet assigned, register one. 1482 * If one was already assigned, but the new mac differs, 1483 * unregister the old one and register the new one. 1484 */ 1485 if ((!smac_info->smac && !smac_info->smac_port) || 1486 smac_info->smac != smac) { 1487 /* register candidate now, unreg if needed, after success */ 1488 smac_index = mlx4_register_mac(dev->dev, port, smac); 1489 if (smac_index >= 0) { 1490 smac_info->candidate_smac_index = smac_index; 1491 smac_info->candidate_smac = smac; 1492 smac_info->candidate_smac_port = port; 1493 } else { 1494 return -EINVAL; 1495 } 1496 } else { 1497 smac_index = smac_info->smac_index; 1498 } 1499 memcpy(path->dmac, ah->roce.dmac, 6); 1500 path->ackto = MLX4_IB_LINK_TYPE_ETH; 1501 /* put MAC table smac index for IBoE */ 1502 path->grh_mylmc = (u8) (smac_index) | 0x80; 1503 } else { 1504 path->sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE | 1505 ((port - 1) << 6) | ((rdma_ah_get_sl(ah) & 0xf) << 2); 1506 } 1507 1508 return 0; 1509 } 1510 1511 static int mlx4_set_path(struct mlx4_ib_dev *dev, const struct ib_qp_attr *qp, 1512 enum ib_qp_attr_mask qp_attr_mask, 1513 struct mlx4_ib_qp *mqp, 1514 struct mlx4_qp_path *path, u8 port, 1515 u16 vlan_id, u8 *smac) 1516 { 1517 return _mlx4_set_path(dev, &qp->ah_attr, 1518 mlx4_mac_to_u64(smac), 1519 vlan_id, 1520 path, &mqp->pri, port); 1521 } 1522 1523 static int mlx4_set_alt_path(struct mlx4_ib_dev *dev, 1524 const struct ib_qp_attr *qp, 1525 enum ib_qp_attr_mask qp_attr_mask, 1526 struct mlx4_ib_qp *mqp, 1527 struct mlx4_qp_path *path, u8 port) 1528 { 1529 return _mlx4_set_path(dev, &qp->alt_ah_attr, 1530 0, 1531 0xffff, 1532 path, &mqp->alt, port); 1533 } 1534 1535 static void update_mcg_macs(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp) 1536 { 1537 struct mlx4_ib_gid_entry *ge, *tmp; 1538 1539 list_for_each_entry_safe(ge, tmp, &qp->gid_list, list) { 1540 if (!ge->added && mlx4_ib_add_mc(dev, qp, &ge->gid)) { 1541 ge->added = 1; 1542 ge->port = qp->port; 1543 } 1544 } 1545 } 1546 1547 static int handle_eth_ud_smac_index(struct mlx4_ib_dev *dev, 1548 struct mlx4_ib_qp *qp, 1549 struct mlx4_qp_context *context) 1550 { 1551 u64 u64_mac; 1552 int smac_index; 1553 1554 u64_mac = atomic64_read(&dev->iboe.mac[qp->port - 1]); 1555 1556 context->pri_path.sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE | ((qp->port - 1) << 6); 1557 if (!qp->pri.smac && !qp->pri.smac_port) { 1558 smac_index = mlx4_register_mac(dev->dev, qp->port, u64_mac); 1559 if (smac_index >= 0) { 1560 qp->pri.candidate_smac_index = smac_index; 1561 qp->pri.candidate_smac = u64_mac; 1562 qp->pri.candidate_smac_port = qp->port; 1563 context->pri_path.grh_mylmc = 0x80 | (u8) smac_index; 1564 } else { 1565 return -ENOENT; 1566 } 1567 } 1568 return 0; 1569 } 1570 1571 static int create_qp_lb_counter(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp) 1572 { 1573 struct counter_index *new_counter_index; 1574 int err; 1575 u32 tmp_idx; 1576 1577 if (rdma_port_get_link_layer(&dev->ib_dev, qp->port) != 1578 IB_LINK_LAYER_ETHERNET || 1579 !(qp->flags & MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK) || 1580 !(dev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_LB_SRC_CHK)) 1581 return 0; 1582 1583 err = mlx4_counter_alloc(dev->dev, &tmp_idx); 1584 if (err) 1585 return err; 1586 1587 new_counter_index = kmalloc(sizeof(*new_counter_index), GFP_KERNEL); 1588 if (!new_counter_index) { 1589 mlx4_counter_free(dev->dev, tmp_idx); 1590 return -ENOMEM; 1591 } 1592 1593 new_counter_index->index = tmp_idx; 1594 new_counter_index->allocated = 1; 1595 qp->counter_index = new_counter_index; 1596 1597 mutex_lock(&dev->counters_table[qp->port - 1].mutex); 1598 list_add_tail(&new_counter_index->list, 1599 &dev->counters_table[qp->port - 1].counters_list); 1600 mutex_unlock(&dev->counters_table[qp->port - 1].mutex); 1601 1602 return 0; 1603 } 1604 1605 enum { 1606 MLX4_QPC_ROCE_MODE_1 = 0, 1607 MLX4_QPC_ROCE_MODE_2 = 2, 1608 MLX4_QPC_ROCE_MODE_UNDEFINED = 0xff 1609 }; 1610 1611 static u8 gid_type_to_qpc(enum ib_gid_type gid_type) 1612 { 1613 switch (gid_type) { 1614 case IB_GID_TYPE_ROCE: 1615 return MLX4_QPC_ROCE_MODE_1; 1616 case IB_GID_TYPE_ROCE_UDP_ENCAP: 1617 return MLX4_QPC_ROCE_MODE_2; 1618 default: 1619 return MLX4_QPC_ROCE_MODE_UNDEFINED; 1620 } 1621 } 1622 1623 static int __mlx4_ib_modify_qp(struct ib_qp *ibqp, 1624 const struct ib_qp_attr *attr, int attr_mask, 1625 enum ib_qp_state cur_state, 1626 enum ib_qp_state new_state, 1627 struct ib_udata *udata) 1628 { 1629 const struct ib_gid_attr *gid_attr = NULL; 1630 struct mlx4_ib_dev *dev = to_mdev(ibqp->device); 1631 struct mlx4_ib_qp *qp = to_mqp(ibqp); 1632 struct mlx4_ib_pd *pd; 1633 struct mlx4_ib_cq *send_cq, *recv_cq; 1634 struct mlx4_ib_ucontext *ucontext = rdma_udata_to_drv_context( 1635 udata, struct mlx4_ib_ucontext, ibucontext); 1636 struct mlx4_qp_context *context; 1637 enum mlx4_qp_optpar optpar = 0; 1638 int sqd_event; 1639 int steer_qp = 0; 1640 int err = -EINVAL; 1641 int counter_index; 1642 1643 /* APM is not supported under RoCE */ 1644 if (attr_mask & IB_QP_ALT_PATH && 1645 rdma_port_get_link_layer(&dev->ib_dev, qp->port) == 1646 IB_LINK_LAYER_ETHERNET) 1647 return -ENOTSUPP; 1648 1649 context = kzalloc(sizeof *context, GFP_KERNEL); 1650 if (!context) 1651 return -ENOMEM; 1652 1653 context->flags = cpu_to_be32((to_mlx4_state(new_state) << 28) | 1654 (to_mlx4_st(dev, qp->mlx4_ib_qp_type) << 16)); 1655 1656 if (!(attr_mask & IB_QP_PATH_MIG_STATE)) 1657 context->flags |= cpu_to_be32(MLX4_QP_PM_MIGRATED << 11); 1658 else { 1659 optpar |= MLX4_QP_OPTPAR_PM_STATE; 1660 switch (attr->path_mig_state) { 1661 case IB_MIG_MIGRATED: 1662 context->flags |= cpu_to_be32(MLX4_QP_PM_MIGRATED << 11); 1663 break; 1664 case IB_MIG_REARM: 1665 context->flags |= cpu_to_be32(MLX4_QP_PM_REARM << 11); 1666 break; 1667 case IB_MIG_ARMED: 1668 context->flags |= cpu_to_be32(MLX4_QP_PM_ARMED << 11); 1669 break; 1670 } 1671 } 1672 1673 if (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_SMI) 1674 context->mtu_msgmax = (IB_MTU_4096 << 5) | 11; 1675 else if (ibqp->qp_type == IB_QPT_RAW_PACKET) 1676 context->mtu_msgmax = (MLX4_RAW_QP_MTU << 5) | MLX4_RAW_QP_MSGMAX; 1677 else if (ibqp->qp_type == IB_QPT_UD) { 1678 if (qp->flags & MLX4_IB_QP_LSO) 1679 context->mtu_msgmax = (IB_MTU_4096 << 5) | 1680 ilog2(dev->dev->caps.max_gso_sz); 1681 else 1682 context->mtu_msgmax = (IB_MTU_4096 << 5) | 12; 1683 } else if (attr_mask & IB_QP_PATH_MTU) { 1684 if (attr->path_mtu < IB_MTU_256 || attr->path_mtu > IB_MTU_4096) { 1685 pr_err("path MTU (%u) is invalid\n", 1686 attr->path_mtu); 1687 goto out; 1688 } 1689 context->mtu_msgmax = (attr->path_mtu << 5) | 1690 ilog2(dev->dev->caps.max_msg_sz); 1691 } 1692 1693 if (qp->rq.wqe_cnt) 1694 context->rq_size_stride = ilog2(qp->rq.wqe_cnt) << 3; 1695 context->rq_size_stride |= qp->rq.wqe_shift - 4; 1696 1697 if (qp->sq.wqe_cnt) 1698 context->sq_size_stride = ilog2(qp->sq.wqe_cnt) << 3; 1699 context->sq_size_stride |= qp->sq.wqe_shift - 4; 1700 1701 if (new_state == IB_QPS_RESET && qp->counter_index) 1702 mlx4_ib_free_qp_counter(dev, qp); 1703 1704 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) { 1705 context->sq_size_stride |= !!qp->sq_no_prefetch << 7; 1706 context->xrcd = cpu_to_be32((u32) qp->xrcdn); 1707 if (ibqp->qp_type == IB_QPT_RAW_PACKET) 1708 context->param3 |= cpu_to_be32(1 << 30); 1709 } 1710 1711 if (ucontext) 1712 context->usr_page = cpu_to_be32( 1713 mlx4_to_hw_uar_index(dev->dev, ucontext->uar.index)); 1714 else 1715 context->usr_page = cpu_to_be32( 1716 mlx4_to_hw_uar_index(dev->dev, dev->priv_uar.index)); 1717 1718 if (attr_mask & IB_QP_DEST_QPN) 1719 context->remote_qpn = cpu_to_be32(attr->dest_qp_num); 1720 1721 if (attr_mask & IB_QP_PORT) { 1722 if (cur_state == IB_QPS_SQD && new_state == IB_QPS_SQD && 1723 !(attr_mask & IB_QP_AV)) { 1724 mlx4_set_sched(&context->pri_path, attr->port_num); 1725 optpar |= MLX4_QP_OPTPAR_SCHED_QUEUE; 1726 } 1727 } 1728 1729 if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) { 1730 err = create_qp_lb_counter(dev, qp); 1731 if (err) 1732 goto out; 1733 1734 counter_index = 1735 dev->counters_table[qp->port - 1].default_counter; 1736 if (qp->counter_index) 1737 counter_index = qp->counter_index->index; 1738 1739 if (counter_index != -1) { 1740 context->pri_path.counter_index = counter_index; 1741 optpar |= MLX4_QP_OPTPAR_COUNTER_INDEX; 1742 if (qp->counter_index) { 1743 context->pri_path.fl |= 1744 MLX4_FL_ETH_SRC_CHECK_MC_LB; 1745 context->pri_path.vlan_control |= 1746 MLX4_CTRL_ETH_SRC_CHECK_IF_COUNTER; 1747 } 1748 } else 1749 context->pri_path.counter_index = 1750 MLX4_SINK_COUNTER_INDEX(dev->dev); 1751 1752 if (qp->flags & MLX4_IB_QP_NETIF) { 1753 mlx4_ib_steer_qp_reg(dev, qp, 1); 1754 steer_qp = 1; 1755 } 1756 1757 if (ibqp->qp_type == IB_QPT_GSI) { 1758 enum ib_gid_type gid_type = qp->flags & MLX4_IB_ROCE_V2_GSI_QP ? 1759 IB_GID_TYPE_ROCE_UDP_ENCAP : IB_GID_TYPE_ROCE; 1760 u8 qpc_roce_mode = gid_type_to_qpc(gid_type); 1761 1762 context->rlkey_roce_mode |= (qpc_roce_mode << 6); 1763 } 1764 } 1765 1766 if (attr_mask & IB_QP_PKEY_INDEX) { 1767 if (qp->mlx4_ib_qp_type & MLX4_IB_QPT_ANY_SRIOV) 1768 context->pri_path.disable_pkey_check = 0x40; 1769 context->pri_path.pkey_index = attr->pkey_index; 1770 optpar |= MLX4_QP_OPTPAR_PKEY_INDEX; 1771 } 1772 1773 if (attr_mask & IB_QP_AV) { 1774 u8 port_num = mlx4_is_bonded(to_mdev(ibqp->device)->dev) ? 1 : 1775 attr_mask & IB_QP_PORT ? attr->port_num : qp->port; 1776 u16 vlan = 0xffff; 1777 u8 smac[ETH_ALEN]; 1778 int is_eth = rdma_cap_eth_ah(&dev->ib_dev, port_num) && 1779 rdma_ah_get_ah_flags(&attr->ah_attr) & IB_AH_GRH; 1780 1781 if (is_eth) { 1782 gid_attr = attr->ah_attr.grh.sgid_attr; 1783 err = rdma_read_gid_l2_fields(gid_attr, &vlan, 1784 &smac[0]); 1785 if (err) 1786 goto out; 1787 } 1788 1789 if (mlx4_set_path(dev, attr, attr_mask, qp, &context->pri_path, 1790 port_num, vlan, smac)) 1791 goto out; 1792 1793 optpar |= (MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH | 1794 MLX4_QP_OPTPAR_SCHED_QUEUE); 1795 1796 if (is_eth && 1797 (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR)) { 1798 u8 qpc_roce_mode = gid_type_to_qpc(gid_attr->gid_type); 1799 1800 if (qpc_roce_mode == MLX4_QPC_ROCE_MODE_UNDEFINED) { 1801 err = -EINVAL; 1802 goto out; 1803 } 1804 context->rlkey_roce_mode |= (qpc_roce_mode << 6); 1805 } 1806 1807 } 1808 1809 if (attr_mask & IB_QP_TIMEOUT) { 1810 context->pri_path.ackto |= attr->timeout << 3; 1811 optpar |= MLX4_QP_OPTPAR_ACK_TIMEOUT; 1812 } 1813 1814 if (attr_mask & IB_QP_ALT_PATH) { 1815 if (attr->alt_port_num == 0 || 1816 attr->alt_port_num > dev->dev->caps.num_ports) 1817 goto out; 1818 1819 if (attr->alt_pkey_index >= 1820 dev->dev->caps.pkey_table_len[attr->alt_port_num]) 1821 goto out; 1822 1823 if (mlx4_set_alt_path(dev, attr, attr_mask, qp, 1824 &context->alt_path, 1825 attr->alt_port_num)) 1826 goto out; 1827 1828 context->alt_path.pkey_index = attr->alt_pkey_index; 1829 context->alt_path.ackto = attr->alt_timeout << 3; 1830 optpar |= MLX4_QP_OPTPAR_ALT_ADDR_PATH; 1831 } 1832 1833 pd = get_pd(qp); 1834 get_cqs(qp, &send_cq, &recv_cq); 1835 context->pd = cpu_to_be32(pd->pdn); 1836 context->cqn_send = cpu_to_be32(send_cq->mcq.cqn); 1837 context->cqn_recv = cpu_to_be32(recv_cq->mcq.cqn); 1838 context->params1 = cpu_to_be32(MLX4_IB_ACK_REQ_FREQ << 28); 1839 1840 /* Set "fast registration enabled" for all kernel QPs */ 1841 if (!qp->ibqp.uobject) 1842 context->params1 |= cpu_to_be32(1 << 11); 1843 1844 if (attr_mask & IB_QP_RNR_RETRY) { 1845 context->params1 |= cpu_to_be32(attr->rnr_retry << 13); 1846 optpar |= MLX4_QP_OPTPAR_RNR_RETRY; 1847 } 1848 1849 if (attr_mask & IB_QP_RETRY_CNT) { 1850 context->params1 |= cpu_to_be32(attr->retry_cnt << 16); 1851 optpar |= MLX4_QP_OPTPAR_RETRY_COUNT; 1852 } 1853 1854 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) { 1855 if (attr->max_rd_atomic) 1856 context->params1 |= 1857 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21); 1858 optpar |= MLX4_QP_OPTPAR_SRA_MAX; 1859 } 1860 1861 if (attr_mask & IB_QP_SQ_PSN) 1862 context->next_send_psn = cpu_to_be32(attr->sq_psn); 1863 1864 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) { 1865 if (attr->max_dest_rd_atomic) 1866 context->params2 |= 1867 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21); 1868 optpar |= MLX4_QP_OPTPAR_RRA_MAX; 1869 } 1870 1871 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) { 1872 context->params2 |= to_mlx4_access_flags(qp, attr, attr_mask); 1873 optpar |= MLX4_QP_OPTPAR_RWE | MLX4_QP_OPTPAR_RRE | MLX4_QP_OPTPAR_RAE; 1874 } 1875 1876 if (ibqp->srq) 1877 context->params2 |= cpu_to_be32(MLX4_QP_BIT_RIC); 1878 1879 if (attr_mask & IB_QP_MIN_RNR_TIMER) { 1880 context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24); 1881 optpar |= MLX4_QP_OPTPAR_RNR_TIMEOUT; 1882 } 1883 if (attr_mask & IB_QP_RQ_PSN) 1884 context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn); 1885 1886 /* proxy and tunnel qp qkeys will be changed in modify-qp wrappers */ 1887 if (attr_mask & IB_QP_QKEY) { 1888 if (qp->mlx4_ib_qp_type & 1889 (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER)) 1890 context->qkey = cpu_to_be32(IB_QP_SET_QKEY); 1891 else { 1892 if (mlx4_is_mfunc(dev->dev) && 1893 !(qp->mlx4_ib_qp_type & MLX4_IB_QPT_ANY_SRIOV) && 1894 (attr->qkey & MLX4_RESERVED_QKEY_MASK) == 1895 MLX4_RESERVED_QKEY_BASE) { 1896 pr_err("Cannot use reserved QKEY" 1897 " 0x%x (range 0xffff0000..0xffffffff" 1898 " is reserved)\n", attr->qkey); 1899 err = -EINVAL; 1900 goto out; 1901 } 1902 context->qkey = cpu_to_be32(attr->qkey); 1903 } 1904 optpar |= MLX4_QP_OPTPAR_Q_KEY; 1905 } 1906 1907 if (ibqp->srq) 1908 context->srqn = cpu_to_be32(1 << 24 | to_msrq(ibqp->srq)->msrq.srqn); 1909 1910 if (qp->rq.wqe_cnt && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) 1911 context->db_rec_addr = cpu_to_be64(qp->db.dma); 1912 1913 if (cur_state == IB_QPS_INIT && 1914 new_state == IB_QPS_RTR && 1915 (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_SMI || 1916 ibqp->qp_type == IB_QPT_UD || 1917 ibqp->qp_type == IB_QPT_RAW_PACKET)) { 1918 context->pri_path.sched_queue = (qp->port - 1) << 6; 1919 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_SMI || 1920 qp->mlx4_ib_qp_type & 1921 (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER)) { 1922 context->pri_path.sched_queue |= MLX4_IB_DEFAULT_QP0_SCHED_QUEUE; 1923 if (qp->mlx4_ib_qp_type != MLX4_IB_QPT_SMI) 1924 context->pri_path.fl = 0x80; 1925 } else { 1926 if (qp->mlx4_ib_qp_type & MLX4_IB_QPT_ANY_SRIOV) 1927 context->pri_path.fl = 0x80; 1928 context->pri_path.sched_queue |= MLX4_IB_DEFAULT_SCHED_QUEUE; 1929 } 1930 if (rdma_port_get_link_layer(&dev->ib_dev, qp->port) == 1931 IB_LINK_LAYER_ETHERNET) { 1932 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_TUN_GSI || 1933 qp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI) 1934 context->pri_path.feup = 1 << 7; /* don't fsm */ 1935 /* handle smac_index */ 1936 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_UD || 1937 qp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI || 1938 qp->mlx4_ib_qp_type == MLX4_IB_QPT_TUN_GSI) { 1939 err = handle_eth_ud_smac_index(dev, qp, context); 1940 if (err) { 1941 err = -EINVAL; 1942 goto out; 1943 } 1944 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI) 1945 dev->qp1_proxy[qp->port - 1] = qp; 1946 } 1947 } 1948 } 1949 1950 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET) { 1951 context->pri_path.ackto = (context->pri_path.ackto & 0xf8) | 1952 MLX4_IB_LINK_TYPE_ETH; 1953 if (dev->dev->caps.tunnel_offload_mode == MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) { 1954 /* set QP to receive both tunneled & non-tunneled packets */ 1955 if (!(context->flags & cpu_to_be32(1 << MLX4_RSS_QPC_FLAG_OFFSET))) 1956 context->srqn = cpu_to_be32(7 << 28); 1957 } 1958 } 1959 1960 if (ibqp->qp_type == IB_QPT_UD && (new_state == IB_QPS_RTR)) { 1961 int is_eth = rdma_port_get_link_layer( 1962 &dev->ib_dev, qp->port) == 1963 IB_LINK_LAYER_ETHERNET; 1964 if (is_eth) { 1965 context->pri_path.ackto = MLX4_IB_LINK_TYPE_ETH; 1966 optpar |= MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH; 1967 } 1968 } 1969 1970 1971 if (cur_state == IB_QPS_RTS && new_state == IB_QPS_SQD && 1972 attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY && attr->en_sqd_async_notify) 1973 sqd_event = 1; 1974 else 1975 sqd_event = 0; 1976 1977 if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) 1978 context->rlkey_roce_mode |= (1 << 4); 1979 1980 /* 1981 * Before passing a kernel QP to the HW, make sure that the 1982 * ownership bits of the send queue are set and the SQ 1983 * headroom is stamped so that the hardware doesn't start 1984 * processing stale work requests. 1985 */ 1986 if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) { 1987 struct mlx4_wqe_ctrl_seg *ctrl; 1988 int i; 1989 1990 for (i = 0; i < qp->sq.wqe_cnt; ++i) { 1991 ctrl = get_send_wqe(qp, i); 1992 ctrl->owner_opcode = cpu_to_be32(1U << 31); 1993 if (qp->sq_max_wqes_per_wr == 1) 1994 ctrl->fence_size = 1995 1 << (qp->sq.wqe_shift - 4); 1996 1997 stamp_send_wqe(qp, i, 1 << qp->sq.wqe_shift); 1998 } 1999 } 2000 2001 err = mlx4_qp_modify(dev->dev, &qp->mtt, to_mlx4_state(cur_state), 2002 to_mlx4_state(new_state), context, optpar, 2003 sqd_event, &qp->mqp); 2004 if (err) 2005 goto out; 2006 2007 qp->state = new_state; 2008 2009 if (attr_mask & IB_QP_ACCESS_FLAGS) 2010 qp->atomic_rd_en = attr->qp_access_flags; 2011 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) 2012 qp->resp_depth = attr->max_dest_rd_atomic; 2013 if (attr_mask & IB_QP_PORT) { 2014 qp->port = attr->port_num; 2015 update_mcg_macs(dev, qp); 2016 } 2017 if (attr_mask & IB_QP_ALT_PATH) 2018 qp->alt_port = attr->alt_port_num; 2019 2020 if (is_sqp(dev, qp)) 2021 store_sqp_attrs(to_msqp(qp), attr, attr_mask); 2022 2023 /* 2024 * If we moved QP0 to RTR, bring the IB link up; if we moved 2025 * QP0 to RESET or ERROR, bring the link back down. 2026 */ 2027 if (is_qp0(dev, qp)) { 2028 if (cur_state != IB_QPS_RTR && new_state == IB_QPS_RTR) 2029 if (mlx4_INIT_PORT(dev->dev, qp->port)) 2030 pr_warn("INIT_PORT failed for port %d\n", 2031 qp->port); 2032 2033 if (cur_state != IB_QPS_RESET && cur_state != IB_QPS_ERR && 2034 (new_state == IB_QPS_RESET || new_state == IB_QPS_ERR)) 2035 mlx4_CLOSE_PORT(dev->dev, qp->port); 2036 } 2037 2038 /* 2039 * If we moved a kernel QP to RESET, clean up all old CQ 2040 * entries and reinitialize the QP. 2041 */ 2042 if (new_state == IB_QPS_RESET) { 2043 if (!ibqp->uobject) { 2044 mlx4_ib_cq_clean(recv_cq, qp->mqp.qpn, 2045 ibqp->srq ? to_msrq(ibqp->srq) : NULL); 2046 if (send_cq != recv_cq) 2047 mlx4_ib_cq_clean(send_cq, qp->mqp.qpn, NULL); 2048 2049 qp->rq.head = 0; 2050 qp->rq.tail = 0; 2051 qp->sq.head = 0; 2052 qp->sq.tail = 0; 2053 qp->sq_next_wqe = 0; 2054 if (qp->rq.wqe_cnt) 2055 *qp->db.db = 0; 2056 2057 if (qp->flags & MLX4_IB_QP_NETIF) 2058 mlx4_ib_steer_qp_reg(dev, qp, 0); 2059 } 2060 if (qp->pri.smac || (!qp->pri.smac && qp->pri.smac_port)) { 2061 mlx4_unregister_mac(dev->dev, qp->pri.smac_port, qp->pri.smac); 2062 qp->pri.smac = 0; 2063 qp->pri.smac_port = 0; 2064 } 2065 if (qp->alt.smac) { 2066 mlx4_unregister_mac(dev->dev, qp->alt.smac_port, qp->alt.smac); 2067 qp->alt.smac = 0; 2068 } 2069 if (qp->pri.vid < 0x1000) { 2070 mlx4_unregister_vlan(dev->dev, qp->pri.vlan_port, qp->pri.vid); 2071 qp->pri.vid = 0xFFFF; 2072 qp->pri.candidate_vid = 0xFFFF; 2073 qp->pri.update_vid = 0; 2074 } 2075 2076 if (qp->alt.vid < 0x1000) { 2077 mlx4_unregister_vlan(dev->dev, qp->alt.vlan_port, qp->alt.vid); 2078 qp->alt.vid = 0xFFFF; 2079 qp->alt.candidate_vid = 0xFFFF; 2080 qp->alt.update_vid = 0; 2081 } 2082 } 2083 out: 2084 if (err && qp->counter_index) 2085 mlx4_ib_free_qp_counter(dev, qp); 2086 if (err && steer_qp) 2087 mlx4_ib_steer_qp_reg(dev, qp, 0); 2088 kfree(context); 2089 if (qp->pri.candidate_smac || 2090 (!qp->pri.candidate_smac && qp->pri.candidate_smac_port)) { 2091 if (err) { 2092 mlx4_unregister_mac(dev->dev, qp->pri.candidate_smac_port, qp->pri.candidate_smac); 2093 } else { 2094 if (qp->pri.smac || (!qp->pri.smac && qp->pri.smac_port)) 2095 mlx4_unregister_mac(dev->dev, qp->pri.smac_port, qp->pri.smac); 2096 qp->pri.smac = qp->pri.candidate_smac; 2097 qp->pri.smac_index = qp->pri.candidate_smac_index; 2098 qp->pri.smac_port = qp->pri.candidate_smac_port; 2099 } 2100 qp->pri.candidate_smac = 0; 2101 qp->pri.candidate_smac_index = 0; 2102 qp->pri.candidate_smac_port = 0; 2103 } 2104 if (qp->alt.candidate_smac) { 2105 if (err) { 2106 mlx4_unregister_mac(dev->dev, qp->alt.candidate_smac_port, qp->alt.candidate_smac); 2107 } else { 2108 if (qp->alt.smac) 2109 mlx4_unregister_mac(dev->dev, qp->alt.smac_port, qp->alt.smac); 2110 qp->alt.smac = qp->alt.candidate_smac; 2111 qp->alt.smac_index = qp->alt.candidate_smac_index; 2112 qp->alt.smac_port = qp->alt.candidate_smac_port; 2113 } 2114 qp->alt.candidate_smac = 0; 2115 qp->alt.candidate_smac_index = 0; 2116 qp->alt.candidate_smac_port = 0; 2117 } 2118 2119 if (qp->pri.update_vid) { 2120 if (err) { 2121 if (qp->pri.candidate_vid < 0x1000) 2122 mlx4_unregister_vlan(dev->dev, qp->pri.candidate_vlan_port, 2123 qp->pri.candidate_vid); 2124 } else { 2125 if (qp->pri.vid < 0x1000) 2126 mlx4_unregister_vlan(dev->dev, qp->pri.vlan_port, 2127 qp->pri.vid); 2128 qp->pri.vid = qp->pri.candidate_vid; 2129 qp->pri.vlan_port = qp->pri.candidate_vlan_port; 2130 qp->pri.vlan_index = qp->pri.candidate_vlan_index; 2131 } 2132 qp->pri.candidate_vid = 0xFFFF; 2133 qp->pri.update_vid = 0; 2134 } 2135 2136 if (qp->alt.update_vid) { 2137 if (err) { 2138 if (qp->alt.candidate_vid < 0x1000) 2139 mlx4_unregister_vlan(dev->dev, qp->alt.candidate_vlan_port, 2140 qp->alt.candidate_vid); 2141 } else { 2142 if (qp->alt.vid < 0x1000) 2143 mlx4_unregister_vlan(dev->dev, qp->alt.vlan_port, 2144 qp->alt.vid); 2145 qp->alt.vid = qp->alt.candidate_vid; 2146 qp->alt.vlan_port = qp->alt.candidate_vlan_port; 2147 qp->alt.vlan_index = qp->alt.candidate_vlan_index; 2148 } 2149 qp->alt.candidate_vid = 0xFFFF; 2150 qp->alt.update_vid = 0; 2151 } 2152 2153 return err; 2154 } 2155 2156 static int _mlx4_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, 2157 int attr_mask, struct ib_udata *udata) 2158 { 2159 struct mlx4_ib_dev *dev = to_mdev(ibqp->device); 2160 struct mlx4_ib_qp *qp = to_mqp(ibqp); 2161 enum ib_qp_state cur_state, new_state; 2162 int err = -EINVAL; 2163 mutex_lock(&qp->mutex); 2164 2165 cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state; 2166 new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state; 2167 2168 if (!ib_modify_qp_is_ok(cur_state, new_state, ibqp->qp_type, 2169 attr_mask)) { 2170 pr_debug("qpn 0x%x: invalid attribute mask specified " 2171 "for transition %d to %d. qp_type %d," 2172 " attr_mask 0x%x\n", 2173 ibqp->qp_num, cur_state, new_state, 2174 ibqp->qp_type, attr_mask); 2175 goto out; 2176 } 2177 2178 if (mlx4_is_bonded(dev->dev) && (attr_mask & IB_QP_PORT)) { 2179 if ((cur_state == IB_QPS_RESET) && (new_state == IB_QPS_INIT)) { 2180 if ((ibqp->qp_type == IB_QPT_RC) || 2181 (ibqp->qp_type == IB_QPT_UD) || 2182 (ibqp->qp_type == IB_QPT_UC) || 2183 (ibqp->qp_type == IB_QPT_RAW_PACKET) || 2184 (ibqp->qp_type == IB_QPT_XRC_INI)) { 2185 attr->port_num = mlx4_ib_bond_next_port(dev); 2186 } 2187 } else { 2188 /* no sense in changing port_num 2189 * when ports are bonded */ 2190 attr_mask &= ~IB_QP_PORT; 2191 } 2192 } 2193 2194 if ((attr_mask & IB_QP_PORT) && 2195 (attr->port_num == 0 || attr->port_num > dev->num_ports)) { 2196 pr_debug("qpn 0x%x: invalid port number (%d) specified " 2197 "for transition %d to %d. qp_type %d\n", 2198 ibqp->qp_num, attr->port_num, cur_state, 2199 new_state, ibqp->qp_type); 2200 goto out; 2201 } 2202 2203 if ((attr_mask & IB_QP_PORT) && (ibqp->qp_type == IB_QPT_RAW_PACKET) && 2204 (rdma_port_get_link_layer(&dev->ib_dev, attr->port_num) != 2205 IB_LINK_LAYER_ETHERNET)) 2206 goto out; 2207 2208 if (attr_mask & IB_QP_PKEY_INDEX) { 2209 int p = attr_mask & IB_QP_PORT ? attr->port_num : qp->port; 2210 if (attr->pkey_index >= dev->dev->caps.pkey_table_len[p]) { 2211 pr_debug("qpn 0x%x: invalid pkey index (%d) specified " 2212 "for transition %d to %d. qp_type %d\n", 2213 ibqp->qp_num, attr->pkey_index, cur_state, 2214 new_state, ibqp->qp_type); 2215 goto out; 2216 } 2217 } 2218 2219 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC && 2220 attr->max_rd_atomic > dev->dev->caps.max_qp_init_rdma) { 2221 pr_debug("qpn 0x%x: max_rd_atomic (%d) too large. " 2222 "Transition %d to %d. qp_type %d\n", 2223 ibqp->qp_num, attr->max_rd_atomic, cur_state, 2224 new_state, ibqp->qp_type); 2225 goto out; 2226 } 2227 2228 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC && 2229 attr->max_dest_rd_atomic > dev->dev->caps.max_qp_dest_rdma) { 2230 pr_debug("qpn 0x%x: max_dest_rd_atomic (%d) too large. " 2231 "Transition %d to %d. qp_type %d\n", 2232 ibqp->qp_num, attr->max_dest_rd_atomic, cur_state, 2233 new_state, ibqp->qp_type); 2234 goto out; 2235 } 2236 2237 if (cur_state == new_state && cur_state == IB_QPS_RESET) { 2238 err = 0; 2239 goto out; 2240 } 2241 2242 err = __mlx4_ib_modify_qp(ibqp, attr, attr_mask, cur_state, new_state, udata); 2243 2244 if (mlx4_is_bonded(dev->dev) && (attr_mask & IB_QP_PORT)) 2245 attr->port_num = 1; 2246 2247 out: 2248 mutex_unlock(&qp->mutex); 2249 return err; 2250 } 2251 2252 int mlx4_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, 2253 int attr_mask, struct ib_udata *udata) 2254 { 2255 struct mlx4_ib_qp *mqp = to_mqp(ibqp); 2256 int ret; 2257 2258 ret = _mlx4_ib_modify_qp(ibqp, attr, attr_mask, udata); 2259 2260 if (mqp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI) { 2261 struct mlx4_ib_sqp *sqp = to_msqp(mqp); 2262 int err = 0; 2263 2264 if (sqp->roce_v2_gsi) 2265 err = ib_modify_qp(sqp->roce_v2_gsi, attr, attr_mask); 2266 if (err) 2267 pr_err("Failed to modify GSI QP for RoCEv2 (%d)\n", 2268 err); 2269 } 2270 return ret; 2271 } 2272 2273 static int vf_get_qp0_qkey(struct mlx4_dev *dev, int qpn, u32 *qkey) 2274 { 2275 int i; 2276 for (i = 0; i < dev->caps.num_ports; i++) { 2277 if (qpn == dev->caps.qp0_proxy[i] || 2278 qpn == dev->caps.qp0_tunnel[i]) { 2279 *qkey = dev->caps.qp0_qkey[i]; 2280 return 0; 2281 } 2282 } 2283 return -EINVAL; 2284 } 2285 2286 static int build_sriov_qp0_header(struct mlx4_ib_sqp *sqp, 2287 const struct ib_ud_wr *wr, 2288 void *wqe, unsigned *mlx_seg_len) 2289 { 2290 struct mlx4_ib_dev *mdev = to_mdev(sqp->qp.ibqp.device); 2291 struct ib_device *ib_dev = &mdev->ib_dev; 2292 struct mlx4_wqe_mlx_seg *mlx = wqe; 2293 struct mlx4_wqe_inline_seg *inl = wqe + sizeof *mlx; 2294 struct mlx4_ib_ah *ah = to_mah(wr->ah); 2295 u16 pkey; 2296 u32 qkey; 2297 int send_size; 2298 int header_size; 2299 int spc; 2300 int i; 2301 2302 if (wr->wr.opcode != IB_WR_SEND) 2303 return -EINVAL; 2304 2305 send_size = 0; 2306 2307 for (i = 0; i < wr->wr.num_sge; ++i) 2308 send_size += wr->wr.sg_list[i].length; 2309 2310 /* for proxy-qp0 sends, need to add in size of tunnel header */ 2311 /* for tunnel-qp0 sends, tunnel header is already in s/g list */ 2312 if (sqp->qp.mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_SMI_OWNER) 2313 send_size += sizeof (struct mlx4_ib_tunnel_header); 2314 2315 ib_ud_header_init(send_size, 1, 0, 0, 0, 0, 0, 0, &sqp->ud_header); 2316 2317 if (sqp->qp.mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_SMI_OWNER) { 2318 sqp->ud_header.lrh.service_level = 2319 be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 28; 2320 sqp->ud_header.lrh.destination_lid = 2321 cpu_to_be16(ah->av.ib.g_slid & 0x7f); 2322 sqp->ud_header.lrh.source_lid = 2323 cpu_to_be16(ah->av.ib.g_slid & 0x7f); 2324 } 2325 2326 mlx->flags &= cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE); 2327 2328 /* force loopback */ 2329 mlx->flags |= cpu_to_be32(MLX4_WQE_MLX_VL15 | 0x1 | MLX4_WQE_MLX_SLR); 2330 mlx->rlid = sqp->ud_header.lrh.destination_lid; 2331 2332 sqp->ud_header.lrh.virtual_lane = 0; 2333 sqp->ud_header.bth.solicited_event = !!(wr->wr.send_flags & IB_SEND_SOLICITED); 2334 ib_get_cached_pkey(ib_dev, sqp->qp.port, 0, &pkey); 2335 sqp->ud_header.bth.pkey = cpu_to_be16(pkey); 2336 if (sqp->qp.mlx4_ib_qp_type == MLX4_IB_QPT_TUN_SMI_OWNER) 2337 sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->remote_qpn); 2338 else 2339 sqp->ud_header.bth.destination_qpn = 2340 cpu_to_be32(mdev->dev->caps.qp0_tunnel[sqp->qp.port - 1]); 2341 2342 sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1)); 2343 if (mlx4_is_master(mdev->dev)) { 2344 if (mlx4_get_parav_qkey(mdev->dev, sqp->qp.mqp.qpn, &qkey)) 2345 return -EINVAL; 2346 } else { 2347 if (vf_get_qp0_qkey(mdev->dev, sqp->qp.mqp.qpn, &qkey)) 2348 return -EINVAL; 2349 } 2350 sqp->ud_header.deth.qkey = cpu_to_be32(qkey); 2351 sqp->ud_header.deth.source_qpn = cpu_to_be32(sqp->qp.mqp.qpn); 2352 2353 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY; 2354 sqp->ud_header.immediate_present = 0; 2355 2356 header_size = ib_ud_header_pack(&sqp->ud_header, sqp->header_buf); 2357 2358 /* 2359 * Inline data segments may not cross a 64 byte boundary. If 2360 * our UD header is bigger than the space available up to the 2361 * next 64 byte boundary in the WQE, use two inline data 2362 * segments to hold the UD header. 2363 */ 2364 spc = MLX4_INLINE_ALIGN - 2365 ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1)); 2366 if (header_size <= spc) { 2367 inl->byte_count = cpu_to_be32((1U << 31) | header_size); 2368 memcpy(inl + 1, sqp->header_buf, header_size); 2369 i = 1; 2370 } else { 2371 inl->byte_count = cpu_to_be32((1U << 31) | spc); 2372 memcpy(inl + 1, sqp->header_buf, spc); 2373 2374 inl = (void *) (inl + 1) + spc; 2375 memcpy(inl + 1, sqp->header_buf + spc, header_size - spc); 2376 /* 2377 * Need a barrier here to make sure all the data is 2378 * visible before the byte_count field is set. 2379 * Otherwise the HCA prefetcher could grab the 64-byte 2380 * chunk with this inline segment and get a valid (!= 2381 * 0xffffffff) byte count but stale data, and end up 2382 * generating a packet with bad headers. 2383 * 2384 * The first inline segment's byte_count field doesn't 2385 * need a barrier, because it comes after a 2386 * control/MLX segment and therefore is at an offset 2387 * of 16 mod 64. 2388 */ 2389 wmb(); 2390 inl->byte_count = cpu_to_be32((1U << 31) | (header_size - spc)); 2391 i = 2; 2392 } 2393 2394 *mlx_seg_len = 2395 ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + header_size, 16); 2396 return 0; 2397 } 2398 2399 static u8 sl_to_vl(struct mlx4_ib_dev *dev, u8 sl, int port_num) 2400 { 2401 union sl2vl_tbl_to_u64 tmp_vltab; 2402 u8 vl; 2403 2404 if (sl > 15) 2405 return 0xf; 2406 tmp_vltab.sl64 = atomic64_read(&dev->sl2vl[port_num - 1]); 2407 vl = tmp_vltab.sl8[sl >> 1]; 2408 if (sl & 1) 2409 vl &= 0x0f; 2410 else 2411 vl >>= 4; 2412 return vl; 2413 } 2414 2415 static int fill_gid_by_hw_index(struct mlx4_ib_dev *ibdev, u8 port_num, 2416 int index, union ib_gid *gid, 2417 enum ib_gid_type *gid_type) 2418 { 2419 struct mlx4_ib_iboe *iboe = &ibdev->iboe; 2420 struct mlx4_port_gid_table *port_gid_table; 2421 unsigned long flags; 2422 2423 port_gid_table = &iboe->gids[port_num - 1]; 2424 spin_lock_irqsave(&iboe->lock, flags); 2425 memcpy(gid, &port_gid_table->gids[index].gid, sizeof(*gid)); 2426 *gid_type = port_gid_table->gids[index].gid_type; 2427 spin_unlock_irqrestore(&iboe->lock, flags); 2428 if (rdma_is_zero_gid(gid)) 2429 return -ENOENT; 2430 2431 return 0; 2432 } 2433 2434 #define MLX4_ROCEV2_QP1_SPORT 0xC000 2435 static int build_mlx_header(struct mlx4_ib_sqp *sqp, const struct ib_ud_wr *wr, 2436 void *wqe, unsigned *mlx_seg_len) 2437 { 2438 struct ib_device *ib_dev = sqp->qp.ibqp.device; 2439 struct mlx4_ib_dev *ibdev = to_mdev(ib_dev); 2440 struct mlx4_wqe_mlx_seg *mlx = wqe; 2441 struct mlx4_wqe_ctrl_seg *ctrl = wqe; 2442 struct mlx4_wqe_inline_seg *inl = wqe + sizeof *mlx; 2443 struct mlx4_ib_ah *ah = to_mah(wr->ah); 2444 union ib_gid sgid; 2445 u16 pkey; 2446 int send_size; 2447 int header_size; 2448 int spc; 2449 int i; 2450 int err = 0; 2451 u16 vlan = 0xffff; 2452 bool is_eth; 2453 bool is_vlan = false; 2454 bool is_grh; 2455 bool is_udp = false; 2456 int ip_version = 0; 2457 2458 send_size = 0; 2459 for (i = 0; i < wr->wr.num_sge; ++i) 2460 send_size += wr->wr.sg_list[i].length; 2461 2462 is_eth = rdma_port_get_link_layer(sqp->qp.ibqp.device, sqp->qp.port) == IB_LINK_LAYER_ETHERNET; 2463 is_grh = mlx4_ib_ah_grh_present(ah); 2464 if (is_eth) { 2465 enum ib_gid_type gid_type; 2466 if (mlx4_is_mfunc(to_mdev(ib_dev)->dev)) { 2467 /* When multi-function is enabled, the ib_core gid 2468 * indexes don't necessarily match the hw ones, so 2469 * we must use our own cache */ 2470 err = mlx4_get_roce_gid_from_slave(to_mdev(ib_dev)->dev, 2471 be32_to_cpu(ah->av.ib.port_pd) >> 24, 2472 ah->av.ib.gid_index, &sgid.raw[0]); 2473 if (err) 2474 return err; 2475 } else { 2476 err = fill_gid_by_hw_index(ibdev, sqp->qp.port, 2477 ah->av.ib.gid_index, 2478 &sgid, &gid_type); 2479 if (!err) { 2480 is_udp = gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP; 2481 if (is_udp) { 2482 if (ipv6_addr_v4mapped((struct in6_addr *)&sgid)) 2483 ip_version = 4; 2484 else 2485 ip_version = 6; 2486 is_grh = false; 2487 } 2488 } else { 2489 return err; 2490 } 2491 } 2492 if (ah->av.eth.vlan != cpu_to_be16(0xffff)) { 2493 vlan = be16_to_cpu(ah->av.eth.vlan) & 0x0fff; 2494 is_vlan = 1; 2495 } 2496 } 2497 err = ib_ud_header_init(send_size, !is_eth, is_eth, is_vlan, is_grh, 2498 ip_version, is_udp, 0, &sqp->ud_header); 2499 if (err) 2500 return err; 2501 2502 if (!is_eth) { 2503 sqp->ud_header.lrh.service_level = 2504 be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 28; 2505 sqp->ud_header.lrh.destination_lid = ah->av.ib.dlid; 2506 sqp->ud_header.lrh.source_lid = cpu_to_be16(ah->av.ib.g_slid & 0x7f); 2507 } 2508 2509 if (is_grh || (ip_version == 6)) { 2510 sqp->ud_header.grh.traffic_class = 2511 (be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 20) & 0xff; 2512 sqp->ud_header.grh.flow_label = 2513 ah->av.ib.sl_tclass_flowlabel & cpu_to_be32(0xfffff); 2514 sqp->ud_header.grh.hop_limit = ah->av.ib.hop_limit; 2515 if (is_eth) { 2516 memcpy(sqp->ud_header.grh.source_gid.raw, sgid.raw, 16); 2517 } else { 2518 if (mlx4_is_mfunc(to_mdev(ib_dev)->dev)) { 2519 /* When multi-function is enabled, the ib_core gid 2520 * indexes don't necessarily match the hw ones, so 2521 * we must use our own cache 2522 */ 2523 sqp->ud_header.grh.source_gid.global.subnet_prefix = 2524 cpu_to_be64(atomic64_read(&(to_mdev(ib_dev)->sriov. 2525 demux[sqp->qp.port - 1]. 2526 subnet_prefix))); 2527 sqp->ud_header.grh.source_gid.global.interface_id = 2528 to_mdev(ib_dev)->sriov.demux[sqp->qp.port - 1]. 2529 guid_cache[ah->av.ib.gid_index]; 2530 } else { 2531 sqp->ud_header.grh.source_gid = 2532 ah->ibah.sgid_attr->gid; 2533 } 2534 } 2535 memcpy(sqp->ud_header.grh.destination_gid.raw, 2536 ah->av.ib.dgid, 16); 2537 } 2538 2539 if (ip_version == 4) { 2540 sqp->ud_header.ip4.tos = 2541 (be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 20) & 0xff; 2542 sqp->ud_header.ip4.id = 0; 2543 sqp->ud_header.ip4.frag_off = htons(IP_DF); 2544 sqp->ud_header.ip4.ttl = ah->av.eth.hop_limit; 2545 2546 memcpy(&sqp->ud_header.ip4.saddr, 2547 sgid.raw + 12, 4); 2548 memcpy(&sqp->ud_header.ip4.daddr, ah->av.ib.dgid + 12, 4); 2549 sqp->ud_header.ip4.check = ib_ud_ip4_csum(&sqp->ud_header); 2550 } 2551 2552 if (is_udp) { 2553 sqp->ud_header.udp.dport = htons(ROCE_V2_UDP_DPORT); 2554 sqp->ud_header.udp.sport = htons(MLX4_ROCEV2_QP1_SPORT); 2555 sqp->ud_header.udp.csum = 0; 2556 } 2557 2558 mlx->flags &= cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE); 2559 2560 if (!is_eth) { 2561 mlx->flags |= cpu_to_be32((!sqp->qp.ibqp.qp_num ? MLX4_WQE_MLX_VL15 : 0) | 2562 (sqp->ud_header.lrh.destination_lid == 2563 IB_LID_PERMISSIVE ? MLX4_WQE_MLX_SLR : 0) | 2564 (sqp->ud_header.lrh.service_level << 8)); 2565 if (ah->av.ib.port_pd & cpu_to_be32(0x80000000)) 2566 mlx->flags |= cpu_to_be32(0x1); /* force loopback */ 2567 mlx->rlid = sqp->ud_header.lrh.destination_lid; 2568 } 2569 2570 switch (wr->wr.opcode) { 2571 case IB_WR_SEND: 2572 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY; 2573 sqp->ud_header.immediate_present = 0; 2574 break; 2575 case IB_WR_SEND_WITH_IMM: 2576 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE; 2577 sqp->ud_header.immediate_present = 1; 2578 sqp->ud_header.immediate_data = wr->wr.ex.imm_data; 2579 break; 2580 default: 2581 return -EINVAL; 2582 } 2583 2584 if (is_eth) { 2585 struct in6_addr in6; 2586 u16 ether_type; 2587 u16 pcp = (be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 29) << 13; 2588 2589 ether_type = (!is_udp) ? MLX4_IB_IBOE_ETHERTYPE : 2590 (ip_version == 4 ? ETHERTYPE_IP : ETHERTYPE_IPV6); 2591 2592 mlx->sched_prio = cpu_to_be16(pcp); 2593 2594 ether_addr_copy(sqp->ud_header.eth.smac_h, ah->av.eth.s_mac); 2595 memcpy(sqp->ud_header.eth.dmac_h, ah->av.eth.mac, 6); 2596 memcpy(&ctrl->srcrb_flags16[0], ah->av.eth.mac, 2); 2597 memcpy(&ctrl->imm, ah->av.eth.mac + 2, 4); 2598 memcpy(&in6, sgid.raw, sizeof(in6)); 2599 2600 2601 if (!memcmp(sqp->ud_header.eth.smac_h, sqp->ud_header.eth.dmac_h, 6)) 2602 mlx->flags |= cpu_to_be32(MLX4_WQE_CTRL_FORCE_LOOPBACK); 2603 if (!is_vlan) { 2604 sqp->ud_header.eth.type = cpu_to_be16(ether_type); 2605 } else { 2606 sqp->ud_header.vlan.type = cpu_to_be16(ether_type); 2607 sqp->ud_header.vlan.tag = cpu_to_be16(vlan | pcp); 2608 } 2609 } else { 2610 sqp->ud_header.lrh.virtual_lane = !sqp->qp.ibqp.qp_num ? 15 : 2611 sl_to_vl(to_mdev(ib_dev), 2612 sqp->ud_header.lrh.service_level, 2613 sqp->qp.port); 2614 if (sqp->qp.ibqp.qp_num && sqp->ud_header.lrh.virtual_lane == 15) 2615 return -EINVAL; 2616 if (sqp->ud_header.lrh.destination_lid == IB_LID_PERMISSIVE) 2617 sqp->ud_header.lrh.source_lid = IB_LID_PERMISSIVE; 2618 } 2619 sqp->ud_header.bth.solicited_event = !!(wr->wr.send_flags & IB_SEND_SOLICITED); 2620 if (!sqp->qp.ibqp.qp_num) 2621 ib_get_cached_pkey(ib_dev, sqp->qp.port, sqp->pkey_index, &pkey); 2622 else 2623 ib_get_cached_pkey(ib_dev, sqp->qp.port, wr->pkey_index, &pkey); 2624 sqp->ud_header.bth.pkey = cpu_to_be16(pkey); 2625 sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->remote_qpn); 2626 sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1)); 2627 sqp->ud_header.deth.qkey = cpu_to_be32(wr->remote_qkey & 0x80000000 ? 2628 sqp->qkey : wr->remote_qkey); 2629 sqp->ud_header.deth.source_qpn = cpu_to_be32(sqp->qp.ibqp.qp_num); 2630 2631 header_size = ib_ud_header_pack(&sqp->ud_header, sqp->header_buf); 2632 2633 if (0) { 2634 pr_err("built UD header of size %d:\n", header_size); 2635 for (i = 0; i < header_size / 4; ++i) { 2636 if (i % 8 == 0) 2637 pr_err(" [%02x] ", i * 4); 2638 pr_cont(" %08x", 2639 be32_to_cpu(((__be32 *) sqp->header_buf)[i])); 2640 if ((i + 1) % 8 == 0) 2641 pr_cont("\n"); 2642 } 2643 pr_err("\n"); 2644 } 2645 2646 /* 2647 * Inline data segments may not cross a 64 byte boundary. If 2648 * our UD header is bigger than the space available up to the 2649 * next 64 byte boundary in the WQE, use two inline data 2650 * segments to hold the UD header. 2651 */ 2652 spc = MLX4_INLINE_ALIGN - 2653 ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1)); 2654 if (header_size <= spc) { 2655 inl->byte_count = cpu_to_be32(1U << 31 | header_size); 2656 memcpy(inl + 1, sqp->header_buf, header_size); 2657 i = 1; 2658 } else { 2659 inl->byte_count = cpu_to_be32(1U << 31 | spc); 2660 memcpy(inl + 1, sqp->header_buf, spc); 2661 2662 inl = (void *) (inl + 1) + spc; 2663 memcpy(inl + 1, sqp->header_buf + spc, header_size - spc); 2664 /* 2665 * Need a barrier here to make sure all the data is 2666 * visible before the byte_count field is set. 2667 * Otherwise the HCA prefetcher could grab the 64-byte 2668 * chunk with this inline segment and get a valid (!= 2669 * 0xffffffff) byte count but stale data, and end up 2670 * generating a packet with bad headers. 2671 * 2672 * The first inline segment's byte_count field doesn't 2673 * need a barrier, because it comes after a 2674 * control/MLX segment and therefore is at an offset 2675 * of 16 mod 64. 2676 */ 2677 wmb(); 2678 inl->byte_count = cpu_to_be32(1U << 31 | (header_size - spc)); 2679 i = 2; 2680 } 2681 2682 *mlx_seg_len = 2683 ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + header_size, 16); 2684 return 0; 2685 } 2686 2687 static int mlx4_wq_overflow(struct mlx4_ib_wq *wq, int nreq, struct ib_cq *ib_cq) 2688 { 2689 unsigned cur; 2690 struct mlx4_ib_cq *cq; 2691 2692 cur = wq->head - wq->tail; 2693 if (likely(cur + nreq < wq->max_post)) 2694 return 0; 2695 2696 cq = to_mcq(ib_cq); 2697 spin_lock(&cq->lock); 2698 cur = wq->head - wq->tail; 2699 spin_unlock(&cq->lock); 2700 2701 return cur + nreq >= wq->max_post; 2702 } 2703 2704 static __be32 convert_access(int acc) 2705 { 2706 return (acc & IB_ACCESS_REMOTE_ATOMIC ? 2707 cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_ATOMIC) : 0) | 2708 (acc & IB_ACCESS_REMOTE_WRITE ? 2709 cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_WRITE) : 0) | 2710 (acc & IB_ACCESS_REMOTE_READ ? 2711 cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_READ) : 0) | 2712 (acc & IB_ACCESS_LOCAL_WRITE ? cpu_to_be32(MLX4_WQE_FMR_PERM_LOCAL_WRITE) : 0) | 2713 cpu_to_be32(MLX4_WQE_FMR_PERM_LOCAL_READ); 2714 } 2715 2716 static void set_reg_seg(struct mlx4_wqe_fmr_seg *fseg, 2717 const struct ib_reg_wr *wr) 2718 { 2719 struct mlx4_ib_mr *mr = to_mmr(wr->mr); 2720 2721 fseg->flags = convert_access(wr->access); 2722 fseg->mem_key = cpu_to_be32(wr->key); 2723 fseg->buf_list = cpu_to_be64(mr->page_map); 2724 fseg->start_addr = cpu_to_be64(mr->ibmr.iova); 2725 fseg->reg_len = cpu_to_be64(mr->ibmr.length); 2726 fseg->offset = 0; /* XXX -- is this just for ZBVA? */ 2727 fseg->page_size = cpu_to_be32(ilog2(mr->ibmr.page_size)); 2728 fseg->reserved[0] = 0; 2729 fseg->reserved[1] = 0; 2730 } 2731 2732 static void set_local_inv_seg(struct mlx4_wqe_local_inval_seg *iseg, u32 rkey) 2733 { 2734 memset(iseg, 0, sizeof(*iseg)); 2735 iseg->mem_key = cpu_to_be32(rkey); 2736 } 2737 2738 static __always_inline void set_raddr_seg(struct mlx4_wqe_raddr_seg *rseg, 2739 u64 remote_addr, u32 rkey) 2740 { 2741 rseg->raddr = cpu_to_be64(remote_addr); 2742 rseg->rkey = cpu_to_be32(rkey); 2743 rseg->reserved = 0; 2744 } 2745 2746 static void set_atomic_seg(struct mlx4_wqe_atomic_seg *aseg, 2747 const struct ib_atomic_wr *wr) 2748 { 2749 if (wr->wr.opcode == IB_WR_ATOMIC_CMP_AND_SWP) { 2750 aseg->swap_add = cpu_to_be64(wr->swap); 2751 aseg->compare = cpu_to_be64(wr->compare_add); 2752 } else if (wr->wr.opcode == IB_WR_MASKED_ATOMIC_FETCH_AND_ADD) { 2753 aseg->swap_add = cpu_to_be64(wr->compare_add); 2754 aseg->compare = cpu_to_be64(wr->compare_add_mask); 2755 } else { 2756 aseg->swap_add = cpu_to_be64(wr->compare_add); 2757 aseg->compare = 0; 2758 } 2759 2760 } 2761 2762 static void set_masked_atomic_seg(struct mlx4_wqe_masked_atomic_seg *aseg, 2763 const struct ib_atomic_wr *wr) 2764 { 2765 aseg->swap_add = cpu_to_be64(wr->swap); 2766 aseg->swap_add_mask = cpu_to_be64(wr->swap_mask); 2767 aseg->compare = cpu_to_be64(wr->compare_add); 2768 aseg->compare_mask = cpu_to_be64(wr->compare_add_mask); 2769 } 2770 2771 static void set_datagram_seg(struct mlx4_wqe_datagram_seg *dseg, 2772 const struct ib_ud_wr *wr) 2773 { 2774 memcpy(dseg->av, &to_mah(wr->ah)->av, sizeof (struct mlx4_av)); 2775 dseg->dqpn = cpu_to_be32(wr->remote_qpn); 2776 dseg->qkey = cpu_to_be32(wr->remote_qkey); 2777 dseg->vlan = to_mah(wr->ah)->av.eth.vlan; 2778 memcpy(dseg->mac, to_mah(wr->ah)->av.eth.mac, 6); 2779 } 2780 2781 static void set_tunnel_datagram_seg(struct mlx4_ib_dev *dev, 2782 struct mlx4_wqe_datagram_seg *dseg, 2783 const struct ib_ud_wr *wr, 2784 enum mlx4_ib_qp_type qpt) 2785 { 2786 union mlx4_ext_av *av = &to_mah(wr->ah)->av; 2787 struct mlx4_av sqp_av = {0}; 2788 int port = *((u8 *) &av->ib.port_pd) & 0x3; 2789 2790 /* force loopback */ 2791 sqp_av.port_pd = av->ib.port_pd | cpu_to_be32(0x80000000); 2792 sqp_av.g_slid = av->ib.g_slid & 0x7f; /* no GRH */ 2793 sqp_av.sl_tclass_flowlabel = av->ib.sl_tclass_flowlabel & 2794 cpu_to_be32(0xf0000000); 2795 2796 memcpy(dseg->av, &sqp_av, sizeof (struct mlx4_av)); 2797 if (qpt == MLX4_IB_QPT_PROXY_GSI) 2798 dseg->dqpn = cpu_to_be32(dev->dev->caps.qp1_tunnel[port - 1]); 2799 else 2800 dseg->dqpn = cpu_to_be32(dev->dev->caps.qp0_tunnel[port - 1]); 2801 /* Use QKEY from the QP context, which is set by master */ 2802 dseg->qkey = cpu_to_be32(IB_QP_SET_QKEY); 2803 } 2804 2805 static void build_tunnel_header(const struct ib_ud_wr *wr, void *wqe, unsigned *mlx_seg_len) 2806 { 2807 struct mlx4_wqe_inline_seg *inl = wqe; 2808 struct mlx4_ib_tunnel_header hdr; 2809 struct mlx4_ib_ah *ah = to_mah(wr->ah); 2810 int spc; 2811 int i; 2812 2813 memcpy(&hdr.av, &ah->av, sizeof hdr.av); 2814 hdr.remote_qpn = cpu_to_be32(wr->remote_qpn); 2815 hdr.pkey_index = cpu_to_be16(wr->pkey_index); 2816 hdr.qkey = cpu_to_be32(wr->remote_qkey); 2817 memcpy(hdr.mac, ah->av.eth.mac, 6); 2818 hdr.vlan = ah->av.eth.vlan; 2819 2820 spc = MLX4_INLINE_ALIGN - 2821 ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1)); 2822 if (sizeof (hdr) <= spc) { 2823 memcpy(inl + 1, &hdr, sizeof (hdr)); 2824 wmb(); 2825 inl->byte_count = cpu_to_be32((1U << 31) | (u32)sizeof(hdr)); 2826 i = 1; 2827 } else { 2828 memcpy(inl + 1, &hdr, spc); 2829 wmb(); 2830 inl->byte_count = cpu_to_be32((1U << 31) | spc); 2831 2832 inl = (void *) (inl + 1) + spc; 2833 memcpy(inl + 1, (void *) &hdr + spc, sizeof (hdr) - spc); 2834 wmb(); 2835 inl->byte_count = cpu_to_be32((1U << 31) | (u32)(sizeof (hdr) - spc)); 2836 i = 2; 2837 } 2838 2839 *mlx_seg_len = 2840 ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + sizeof (hdr), 16); 2841 } 2842 2843 static void set_mlx_icrc_seg(void *dseg) 2844 { 2845 u32 *t = dseg; 2846 struct mlx4_wqe_inline_seg *iseg = dseg; 2847 2848 t[1] = 0; 2849 2850 /* 2851 * Need a barrier here before writing the byte_count field to 2852 * make sure that all the data is visible before the 2853 * byte_count field is set. Otherwise, if the segment begins 2854 * a new cacheline, the HCA prefetcher could grab the 64-byte 2855 * chunk and get a valid (!= * 0xffffffff) byte count but 2856 * stale data, and end up sending the wrong data. 2857 */ 2858 wmb(); 2859 2860 iseg->byte_count = cpu_to_be32((1U << 31) | 4); 2861 } 2862 2863 static void set_data_seg(struct mlx4_wqe_data_seg *dseg, struct ib_sge *sg) 2864 { 2865 dseg->lkey = cpu_to_be32(sg->lkey); 2866 dseg->addr = cpu_to_be64(sg->addr); 2867 2868 /* 2869 * Need a barrier here before writing the byte_count field to 2870 * make sure that all the data is visible before the 2871 * byte_count field is set. Otherwise, if the segment begins 2872 * a new cacheline, the HCA prefetcher could grab the 64-byte 2873 * chunk and get a valid (!= * 0xffffffff) byte count but 2874 * stale data, and end up sending the wrong data. 2875 */ 2876 wmb(); 2877 2878 dseg->byte_count = cpu_to_be32(sg->length); 2879 } 2880 2881 static void __set_data_seg(struct mlx4_wqe_data_seg *dseg, struct ib_sge *sg) 2882 { 2883 dseg->byte_count = cpu_to_be32(sg->length); 2884 dseg->lkey = cpu_to_be32(sg->lkey); 2885 dseg->addr = cpu_to_be64(sg->addr); 2886 } 2887 2888 static int build_lso_seg(struct mlx4_wqe_lso_seg *wqe, const struct ib_ud_wr *wr, 2889 struct mlx4_ib_qp *qp, unsigned *lso_seg_len, 2890 __be32 *lso_hdr_sz, __be32 *blh) 2891 { 2892 unsigned halign = ALIGN(sizeof *wqe + wr->hlen, 16); 2893 2894 if (unlikely(halign > MLX4_IB_CACHE_LINE_SIZE)) 2895 *blh = cpu_to_be32(1 << 6); 2896 2897 if (unlikely(!(qp->flags & MLX4_IB_QP_LSO) && 2898 wr->wr.num_sge > qp->sq.max_gs - (halign >> 4))) 2899 return -EINVAL; 2900 2901 memcpy(wqe->header, wr->header, wr->hlen); 2902 2903 *lso_hdr_sz = cpu_to_be32(wr->mss << 16 | wr->hlen); 2904 *lso_seg_len = halign; 2905 return 0; 2906 } 2907 2908 static __be32 send_ieth(const struct ib_send_wr *wr) 2909 { 2910 switch (wr->opcode) { 2911 case IB_WR_SEND_WITH_IMM: 2912 case IB_WR_RDMA_WRITE_WITH_IMM: 2913 return wr->ex.imm_data; 2914 2915 case IB_WR_SEND_WITH_INV: 2916 return cpu_to_be32(wr->ex.invalidate_rkey); 2917 2918 default: 2919 return 0; 2920 } 2921 } 2922 2923 static void add_zero_len_inline(void *wqe) 2924 { 2925 struct mlx4_wqe_inline_seg *inl = wqe; 2926 memset(wqe, 0, 16); 2927 inl->byte_count = cpu_to_be32(1U << 31); 2928 } 2929 2930 int mlx4_ib_post_send(struct ib_qp *ibqp, const struct ib_send_wr *wr, 2931 const struct ib_send_wr **bad_wr) 2932 { 2933 struct mlx4_ib_qp *qp = to_mqp(ibqp); 2934 void *wqe; 2935 struct mlx4_wqe_ctrl_seg *ctrl; 2936 struct mlx4_wqe_data_seg *dseg; 2937 unsigned long flags; 2938 int nreq; 2939 int err = 0; 2940 unsigned ind; 2941 int uninitialized_var(stamp); 2942 int uninitialized_var(size); 2943 unsigned uninitialized_var(seglen); 2944 __be32 dummy; 2945 __be32 *lso_wqe; 2946 __be32 lso_hdr_sz = 0; 2947 __be32 blh; 2948 int i; 2949 struct mlx4_ib_dev *mdev = to_mdev(ibqp->device); 2950 2951 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI) { 2952 struct mlx4_ib_sqp *sqp = to_msqp(qp); 2953 2954 if (sqp->roce_v2_gsi) { 2955 struct mlx4_ib_ah *ah = to_mah(ud_wr(wr)->ah); 2956 enum ib_gid_type gid_type; 2957 union ib_gid gid; 2958 2959 if (!fill_gid_by_hw_index(mdev, sqp->qp.port, 2960 ah->av.ib.gid_index, 2961 &gid, &gid_type)) 2962 qp = (gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP) ? 2963 to_mqp(sqp->roce_v2_gsi) : qp; 2964 else 2965 pr_err("Failed to get gid at index %d. RoCEv2 will not work properly\n", 2966 ah->av.ib.gid_index); 2967 } 2968 } 2969 2970 spin_lock_irqsave(&qp->sq.lock, flags); 2971 if (mdev->dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR) { 2972 err = -EIO; 2973 *bad_wr = wr; 2974 nreq = 0; 2975 goto out; 2976 } 2977 2978 ind = qp->sq_next_wqe; 2979 2980 for (nreq = 0; wr; ++nreq, wr = wr->next) { 2981 lso_wqe = &dummy; 2982 blh = 0; 2983 2984 if (mlx4_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) { 2985 err = -ENOMEM; 2986 *bad_wr = wr; 2987 goto out; 2988 } 2989 2990 if (unlikely(wr->num_sge > qp->sq.max_gs)) { 2991 err = -EINVAL; 2992 *bad_wr = wr; 2993 goto out; 2994 } 2995 2996 ctrl = wqe = get_send_wqe(qp, ind & (qp->sq.wqe_cnt - 1)); 2997 qp->sq.wrid[(qp->sq.head + nreq) & (qp->sq.wqe_cnt - 1)] = wr->wr_id; 2998 2999 ctrl->srcrb_flags = 3000 (wr->send_flags & IB_SEND_SIGNALED ? 3001 cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE) : 0) | 3002 (wr->send_flags & IB_SEND_SOLICITED ? 3003 cpu_to_be32(MLX4_WQE_CTRL_SOLICITED) : 0) | 3004 ((wr->send_flags & IB_SEND_IP_CSUM) ? 3005 cpu_to_be32(MLX4_WQE_CTRL_IP_CSUM | 3006 MLX4_WQE_CTRL_TCP_UDP_CSUM) : 0) | 3007 qp->sq_signal_bits; 3008 3009 ctrl->imm = send_ieth(wr); 3010 3011 wqe += sizeof *ctrl; 3012 size = sizeof *ctrl / 16; 3013 3014 switch (qp->mlx4_ib_qp_type) { 3015 case MLX4_IB_QPT_RC: 3016 case MLX4_IB_QPT_UC: 3017 switch (wr->opcode) { 3018 case IB_WR_ATOMIC_CMP_AND_SWP: 3019 case IB_WR_ATOMIC_FETCH_AND_ADD: 3020 case IB_WR_MASKED_ATOMIC_FETCH_AND_ADD: 3021 set_raddr_seg(wqe, atomic_wr(wr)->remote_addr, 3022 atomic_wr(wr)->rkey); 3023 wqe += sizeof (struct mlx4_wqe_raddr_seg); 3024 3025 set_atomic_seg(wqe, atomic_wr(wr)); 3026 wqe += sizeof (struct mlx4_wqe_atomic_seg); 3027 3028 size += (sizeof (struct mlx4_wqe_raddr_seg) + 3029 sizeof (struct mlx4_wqe_atomic_seg)) / 16; 3030 3031 break; 3032 3033 case IB_WR_MASKED_ATOMIC_CMP_AND_SWP: 3034 set_raddr_seg(wqe, atomic_wr(wr)->remote_addr, 3035 atomic_wr(wr)->rkey); 3036 wqe += sizeof (struct mlx4_wqe_raddr_seg); 3037 3038 set_masked_atomic_seg(wqe, atomic_wr(wr)); 3039 wqe += sizeof (struct mlx4_wqe_masked_atomic_seg); 3040 3041 size += (sizeof (struct mlx4_wqe_raddr_seg) + 3042 sizeof (struct mlx4_wqe_masked_atomic_seg)) / 16; 3043 3044 break; 3045 3046 case IB_WR_RDMA_READ: 3047 case IB_WR_RDMA_WRITE: 3048 case IB_WR_RDMA_WRITE_WITH_IMM: 3049 set_raddr_seg(wqe, rdma_wr(wr)->remote_addr, 3050 rdma_wr(wr)->rkey); 3051 wqe += sizeof (struct mlx4_wqe_raddr_seg); 3052 size += sizeof (struct mlx4_wqe_raddr_seg) / 16; 3053 break; 3054 3055 case IB_WR_LOCAL_INV: 3056 ctrl->srcrb_flags |= 3057 cpu_to_be32(MLX4_WQE_CTRL_STRONG_ORDER); 3058 set_local_inv_seg(wqe, wr->ex.invalidate_rkey); 3059 wqe += sizeof (struct mlx4_wqe_local_inval_seg); 3060 size += sizeof (struct mlx4_wqe_local_inval_seg) / 16; 3061 break; 3062 3063 case IB_WR_REG_MR: 3064 ctrl->srcrb_flags |= 3065 cpu_to_be32(MLX4_WQE_CTRL_STRONG_ORDER); 3066 set_reg_seg(wqe, reg_wr(wr)); 3067 wqe += sizeof(struct mlx4_wqe_fmr_seg); 3068 size += sizeof(struct mlx4_wqe_fmr_seg) / 16; 3069 break; 3070 3071 default: 3072 /* No extra segments required for sends */ 3073 break; 3074 } 3075 break; 3076 3077 case MLX4_IB_QPT_TUN_SMI_OWNER: 3078 err = build_sriov_qp0_header(to_msqp(qp), ud_wr(wr), 3079 ctrl, &seglen); 3080 if (unlikely(err)) { 3081 *bad_wr = wr; 3082 goto out; 3083 } 3084 wqe += seglen; 3085 size += seglen / 16; 3086 break; 3087 case MLX4_IB_QPT_TUN_SMI: 3088 case MLX4_IB_QPT_TUN_GSI: 3089 /* this is a UD qp used in MAD responses to slaves. */ 3090 set_datagram_seg(wqe, ud_wr(wr)); 3091 /* set the forced-loopback bit in the data seg av */ 3092 *(__be32 *) wqe |= cpu_to_be32(0x80000000); 3093 wqe += sizeof (struct mlx4_wqe_datagram_seg); 3094 size += sizeof (struct mlx4_wqe_datagram_seg) / 16; 3095 break; 3096 case MLX4_IB_QPT_UD: 3097 set_datagram_seg(wqe, ud_wr(wr)); 3098 wqe += sizeof (struct mlx4_wqe_datagram_seg); 3099 size += sizeof (struct mlx4_wqe_datagram_seg) / 16; 3100 3101 if (wr->opcode == IB_WR_LSO) { 3102 err = build_lso_seg(wqe, ud_wr(wr), qp, &seglen, 3103 &lso_hdr_sz, &blh); 3104 if (unlikely(err)) { 3105 *bad_wr = wr; 3106 goto out; 3107 } 3108 lso_wqe = (__be32 *) wqe; 3109 wqe += seglen; 3110 size += seglen / 16; 3111 } 3112 break; 3113 3114 case MLX4_IB_QPT_PROXY_SMI_OWNER: 3115 err = build_sriov_qp0_header(to_msqp(qp), ud_wr(wr), 3116 ctrl, &seglen); 3117 if (unlikely(err)) { 3118 *bad_wr = wr; 3119 goto out; 3120 } 3121 wqe += seglen; 3122 size += seglen / 16; 3123 /* to start tunnel header on a cache-line boundary */ 3124 add_zero_len_inline(wqe); 3125 wqe += 16; 3126 size++; 3127 build_tunnel_header(ud_wr(wr), wqe, &seglen); 3128 wqe += seglen; 3129 size += seglen / 16; 3130 break; 3131 case MLX4_IB_QPT_PROXY_SMI: 3132 case MLX4_IB_QPT_PROXY_GSI: 3133 /* If we are tunneling special qps, this is a UD qp. 3134 * In this case we first add a UD segment targeting 3135 * the tunnel qp, and then add a header with address 3136 * information */ 3137 set_tunnel_datagram_seg(to_mdev(ibqp->device), wqe, 3138 ud_wr(wr), 3139 qp->mlx4_ib_qp_type); 3140 wqe += sizeof (struct mlx4_wqe_datagram_seg); 3141 size += sizeof (struct mlx4_wqe_datagram_seg) / 16; 3142 build_tunnel_header(ud_wr(wr), wqe, &seglen); 3143 wqe += seglen; 3144 size += seglen / 16; 3145 break; 3146 3147 case MLX4_IB_QPT_SMI: 3148 case MLX4_IB_QPT_GSI: 3149 err = build_mlx_header(to_msqp(qp), ud_wr(wr), ctrl, 3150 &seglen); 3151 if (unlikely(err)) { 3152 *bad_wr = wr; 3153 goto out; 3154 } 3155 wqe += seglen; 3156 size += seglen / 16; 3157 break; 3158 3159 default: 3160 break; 3161 } 3162 3163 /* 3164 * Write data segments in reverse order, so as to 3165 * overwrite cacheline stamp last within each 3166 * cacheline. This avoids issues with WQE 3167 * prefetching. 3168 */ 3169 3170 dseg = wqe; 3171 dseg += wr->num_sge - 1; 3172 size += wr->num_sge * (sizeof (struct mlx4_wqe_data_seg) / 16); 3173 3174 /* Add one more inline data segment for ICRC for MLX sends */ 3175 if (unlikely(qp->mlx4_ib_qp_type == MLX4_IB_QPT_SMI || 3176 qp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI || 3177 qp->mlx4_ib_qp_type & 3178 (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER))) { 3179 set_mlx_icrc_seg(dseg + 1); 3180 size += sizeof (struct mlx4_wqe_data_seg) / 16; 3181 } 3182 3183 for (i = wr->num_sge - 1; i >= 0; --i, --dseg) 3184 set_data_seg(dseg, wr->sg_list + i); 3185 3186 /* 3187 * Possibly overwrite stamping in cacheline with LSO 3188 * segment only after making sure all data segments 3189 * are written. 3190 */ 3191 wmb(); 3192 *lso_wqe = lso_hdr_sz; 3193 3194 ctrl->fence_size = (wr->send_flags & IB_SEND_FENCE ? 3195 MLX4_WQE_CTRL_FENCE : 0) | size; 3196 3197 /* 3198 * Make sure descriptor is fully written before 3199 * setting ownership bit (because HW can start 3200 * executing as soon as we do). 3201 */ 3202 wmb(); 3203 3204 if (wr->opcode < 0 || wr->opcode >= ARRAY_SIZE(mlx4_ib_opcode)) { 3205 *bad_wr = wr; 3206 err = -EINVAL; 3207 goto out; 3208 } 3209 3210 ctrl->owner_opcode = mlx4_ib_opcode[wr->opcode] | 3211 (ind & qp->sq.wqe_cnt ? cpu_to_be32(1U << 31) : 0) | blh; 3212 3213 stamp = ind + qp->sq_spare_wqes; 3214 ind += DIV_ROUND_UP(size * 16, 1U << qp->sq.wqe_shift); 3215 3216 /* 3217 * We can improve latency by not stamping the last 3218 * send queue WQE until after ringing the doorbell, so 3219 * only stamp here if there are still more WQEs to post. 3220 * 3221 * Same optimization applies to padding with NOP wqe 3222 * in case of WQE shrinking (used to prevent wrap-around 3223 * in the middle of WR). 3224 */ 3225 if (wr->next) { 3226 stamp_send_wqe(qp, stamp, size * 16); 3227 ind = pad_wraparound(qp, ind); 3228 } 3229 } 3230 3231 out: 3232 if (likely(nreq)) { 3233 qp->sq.head += nreq; 3234 3235 /* 3236 * Make sure that descriptors are written before 3237 * doorbell record. 3238 */ 3239 wmb(); 3240 3241 writel(qp->doorbell_qpn, 3242 to_mdev(ibqp->device)->uar_map + MLX4_SEND_DOORBELL); 3243 3244 /* 3245 * Make sure doorbells don't leak out of SQ spinlock 3246 * and reach the HCA out of order. 3247 */ 3248 mmiowb(); 3249 3250 stamp_send_wqe(qp, stamp, size * 16); 3251 3252 ind = pad_wraparound(qp, ind); 3253 qp->sq_next_wqe = ind; 3254 } 3255 3256 spin_unlock_irqrestore(&qp->sq.lock, flags); 3257 3258 return err; 3259 } 3260 3261 int mlx4_ib_post_recv(struct ib_qp *ibqp, const struct ib_recv_wr *wr, 3262 const struct ib_recv_wr **bad_wr) 3263 { 3264 struct mlx4_ib_qp *qp = to_mqp(ibqp); 3265 struct mlx4_wqe_data_seg *scat; 3266 unsigned long flags; 3267 int err = 0; 3268 int nreq; 3269 int ind; 3270 int max_gs; 3271 int i; 3272 struct mlx4_ib_dev *mdev = to_mdev(ibqp->device); 3273 3274 max_gs = qp->rq.max_gs; 3275 spin_lock_irqsave(&qp->rq.lock, flags); 3276 3277 if (mdev->dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR) { 3278 err = -EIO; 3279 *bad_wr = wr; 3280 nreq = 0; 3281 goto out; 3282 } 3283 3284 ind = qp->rq.head & (qp->rq.wqe_cnt - 1); 3285 3286 for (nreq = 0; wr; ++nreq, wr = wr->next) { 3287 if (mlx4_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) { 3288 err = -ENOMEM; 3289 *bad_wr = wr; 3290 goto out; 3291 } 3292 3293 if (unlikely(wr->num_sge > qp->rq.max_gs)) { 3294 err = -EINVAL; 3295 *bad_wr = wr; 3296 goto out; 3297 } 3298 3299 scat = get_recv_wqe(qp, ind); 3300 3301 if (qp->mlx4_ib_qp_type & (MLX4_IB_QPT_PROXY_SMI_OWNER | 3302 MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI)) { 3303 ib_dma_sync_single_for_device(ibqp->device, 3304 qp->sqp_proxy_rcv[ind].map, 3305 sizeof (struct mlx4_ib_proxy_sqp_hdr), 3306 DMA_FROM_DEVICE); 3307 scat->byte_count = 3308 cpu_to_be32(sizeof (struct mlx4_ib_proxy_sqp_hdr)); 3309 /* use dma lkey from upper layer entry */ 3310 scat->lkey = cpu_to_be32(wr->sg_list->lkey); 3311 scat->addr = cpu_to_be64(qp->sqp_proxy_rcv[ind].map); 3312 scat++; 3313 max_gs--; 3314 } 3315 3316 for (i = 0; i < wr->num_sge; ++i) 3317 __set_data_seg(scat + i, wr->sg_list + i); 3318 3319 if (i < max_gs) { 3320 scat[i].byte_count = 0; 3321 scat[i].lkey = cpu_to_be32(MLX4_INVALID_LKEY); 3322 scat[i].addr = 0; 3323 } 3324 3325 qp->rq.wrid[ind] = wr->wr_id; 3326 3327 ind = (ind + 1) & (qp->rq.wqe_cnt - 1); 3328 } 3329 3330 out: 3331 if (likely(nreq)) { 3332 qp->rq.head += nreq; 3333 3334 /* 3335 * Make sure that descriptors are written before 3336 * doorbell record. 3337 */ 3338 wmb(); 3339 3340 *qp->db.db = cpu_to_be32(qp->rq.head & 0xffff); 3341 } 3342 3343 spin_unlock_irqrestore(&qp->rq.lock, flags); 3344 3345 return err; 3346 } 3347 3348 static inline enum ib_qp_state to_ib_qp_state(enum mlx4_qp_state mlx4_state) 3349 { 3350 switch (mlx4_state) { 3351 case MLX4_QP_STATE_RST: return IB_QPS_RESET; 3352 case MLX4_QP_STATE_INIT: return IB_QPS_INIT; 3353 case MLX4_QP_STATE_RTR: return IB_QPS_RTR; 3354 case MLX4_QP_STATE_RTS: return IB_QPS_RTS; 3355 case MLX4_QP_STATE_SQ_DRAINING: 3356 case MLX4_QP_STATE_SQD: return IB_QPS_SQD; 3357 case MLX4_QP_STATE_SQER: return IB_QPS_SQE; 3358 case MLX4_QP_STATE_ERR: return IB_QPS_ERR; 3359 default: return -1; 3360 } 3361 } 3362 3363 static inline enum ib_mig_state to_ib_mig_state(int mlx4_mig_state) 3364 { 3365 switch (mlx4_mig_state) { 3366 case MLX4_QP_PM_ARMED: return IB_MIG_ARMED; 3367 case MLX4_QP_PM_REARM: return IB_MIG_REARM; 3368 case MLX4_QP_PM_MIGRATED: return IB_MIG_MIGRATED; 3369 default: return -1; 3370 } 3371 } 3372 3373 static int to_ib_qp_access_flags(int mlx4_flags) 3374 { 3375 int ib_flags = 0; 3376 3377 if (mlx4_flags & MLX4_QP_BIT_RRE) 3378 ib_flags |= IB_ACCESS_REMOTE_READ; 3379 if (mlx4_flags & MLX4_QP_BIT_RWE) 3380 ib_flags |= IB_ACCESS_REMOTE_WRITE; 3381 if (mlx4_flags & MLX4_QP_BIT_RAE) 3382 ib_flags |= IB_ACCESS_REMOTE_ATOMIC; 3383 3384 return ib_flags; 3385 } 3386 3387 static void to_rdma_ah_attr(struct mlx4_ib_dev *ibdev, 3388 struct rdma_ah_attr *ah_attr, 3389 struct mlx4_qp_path *path) 3390 { 3391 struct mlx4_dev *dev = ibdev->dev; 3392 u8 port_num = path->sched_queue & 0x40 ? 2 : 1; 3393 3394 memset(ah_attr, 0, sizeof *ah_attr); 3395 ah_attr->type = rdma_ah_find_type(&ibdev->ib_dev, port_num); 3396 if (port_num == 0 || port_num > dev->caps.num_ports) 3397 return; 3398 3399 if (ah_attr->type == RDMA_AH_ATTR_TYPE_ROCE) 3400 rdma_ah_set_sl(ah_attr, ((path->sched_queue >> 3) & 0x7) | 3401 ((path->sched_queue & 4) << 1)); 3402 else 3403 rdma_ah_set_sl(ah_attr, (path->sched_queue >> 2) & 0xf); 3404 rdma_ah_set_port_num(ah_attr, port_num); 3405 3406 rdma_ah_set_dlid(ah_attr, be16_to_cpu(path->rlid)); 3407 rdma_ah_set_path_bits(ah_attr, path->grh_mylmc & 0x7f); 3408 rdma_ah_set_static_rate(ah_attr, 3409 path->static_rate ? path->static_rate - 5 : 0); 3410 if (path->grh_mylmc & (1 << 7)) { 3411 rdma_ah_set_grh(ah_attr, NULL, 3412 be32_to_cpu(path->tclass_flowlabel) & 0xfffff, 3413 path->mgid_index, 3414 path->hop_limit, 3415 (be32_to_cpu(path->tclass_flowlabel) 3416 >> 20) & 0xff); 3417 rdma_ah_set_dgid_raw(ah_attr, path->rgid); 3418 } 3419 } 3420 3421 int mlx4_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask, 3422 struct ib_qp_init_attr *qp_init_attr) 3423 { 3424 struct mlx4_ib_dev *dev = to_mdev(ibqp->device); 3425 struct mlx4_ib_qp *qp = to_mqp(ibqp); 3426 struct mlx4_qp_context context; 3427 int mlx4_state; 3428 int err = 0; 3429 3430 mutex_lock(&qp->mutex); 3431 3432 if (qp->state == IB_QPS_RESET) { 3433 qp_attr->qp_state = IB_QPS_RESET; 3434 goto done; 3435 } 3436 3437 err = mlx4_qp_query(dev->dev, &qp->mqp, &context); 3438 if (err) { 3439 err = -EINVAL; 3440 goto out; 3441 } 3442 3443 mlx4_state = be32_to_cpu(context.flags) >> 28; 3444 3445 qp->state = to_ib_qp_state(mlx4_state); 3446 qp_attr->qp_state = qp->state; 3447 qp_attr->path_mtu = context.mtu_msgmax >> 5; 3448 qp_attr->path_mig_state = 3449 to_ib_mig_state((be32_to_cpu(context.flags) >> 11) & 0x3); 3450 qp_attr->qkey = be32_to_cpu(context.qkey); 3451 qp_attr->rq_psn = be32_to_cpu(context.rnr_nextrecvpsn) & 0xffffff; 3452 qp_attr->sq_psn = be32_to_cpu(context.next_send_psn) & 0xffffff; 3453 qp_attr->dest_qp_num = be32_to_cpu(context.remote_qpn) & 0xffffff; 3454 qp_attr->qp_access_flags = 3455 to_ib_qp_access_flags(be32_to_cpu(context.params2)); 3456 3457 if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC) { 3458 to_rdma_ah_attr(dev, &qp_attr->ah_attr, &context.pri_path); 3459 to_rdma_ah_attr(dev, &qp_attr->alt_ah_attr, &context.alt_path); 3460 qp_attr->alt_pkey_index = context.alt_path.pkey_index & 0x7f; 3461 qp_attr->alt_port_num = 3462 rdma_ah_get_port_num(&qp_attr->alt_ah_attr); 3463 } 3464 3465 qp_attr->pkey_index = context.pri_path.pkey_index & 0x7f; 3466 if (qp_attr->qp_state == IB_QPS_INIT) 3467 qp_attr->port_num = qp->port; 3468 else 3469 qp_attr->port_num = context.pri_path.sched_queue & 0x40 ? 2 : 1; 3470 3471 /* qp_attr->en_sqd_async_notify is only applicable in modify qp */ 3472 qp_attr->sq_draining = mlx4_state == MLX4_QP_STATE_SQ_DRAINING; 3473 3474 qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context.params1) >> 21) & 0x7); 3475 3476 qp_attr->max_dest_rd_atomic = 3477 1 << ((be32_to_cpu(context.params2) >> 21) & 0x7); 3478 qp_attr->min_rnr_timer = 3479 (be32_to_cpu(context.rnr_nextrecvpsn) >> 24) & 0x1f; 3480 qp_attr->timeout = context.pri_path.ackto >> 3; 3481 qp_attr->retry_cnt = (be32_to_cpu(context.params1) >> 16) & 0x7; 3482 qp_attr->rnr_retry = (be32_to_cpu(context.params1) >> 13) & 0x7; 3483 qp_attr->alt_timeout = context.alt_path.ackto >> 3; 3484 3485 done: 3486 qp_attr->cur_qp_state = qp_attr->qp_state; 3487 qp_attr->cap.max_recv_wr = qp->rq.wqe_cnt; 3488 qp_attr->cap.max_recv_sge = qp->rq.max_gs; 3489 3490 if (!ibqp->uobject) { 3491 qp_attr->cap.max_send_wr = qp->sq.wqe_cnt; 3492 qp_attr->cap.max_send_sge = qp->sq.max_gs; 3493 } else { 3494 qp_attr->cap.max_send_wr = 0; 3495 qp_attr->cap.max_send_sge = 0; 3496 } 3497 3498 /* 3499 * We don't support inline sends for kernel QPs (yet), and we 3500 * don't know what userspace's value should be. 3501 */ 3502 qp_attr->cap.max_inline_data = 0; 3503 3504 qp_init_attr->cap = qp_attr->cap; 3505 3506 qp_init_attr->create_flags = 0; 3507 if (qp->flags & MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK) 3508 qp_init_attr->create_flags |= IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK; 3509 3510 if (qp->flags & MLX4_IB_QP_LSO) 3511 qp_init_attr->create_flags |= IB_QP_CREATE_IPOIB_UD_LSO; 3512 3513 if (qp->flags & MLX4_IB_QP_NETIF) 3514 qp_init_attr->create_flags |= IB_QP_CREATE_NETIF_QP; 3515 3516 qp_init_attr->sq_sig_type = 3517 qp->sq_signal_bits == cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE) ? 3518 IB_SIGNAL_ALL_WR : IB_SIGNAL_REQ_WR; 3519 3520 out: 3521 mutex_unlock(&qp->mutex); 3522 return err; 3523 } 3524 3525