1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (C) 2007-2009 Semihalf, Rafal Jaworowski <raj@semihalf.com>
5 * Copyright (C) 2006 Semihalf, Marian Balakowicz <m8@semihalf.com>
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
20 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
22 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
23 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
24 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
25 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
26 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Some hw specific parts of this pmap were derived or influenced
29 * by NetBSD's ibm4xx pmap module. More generic code is shared with
30 * a few other pmap modules from the FreeBSD tree.
31 */
32
33 /*
34 * VM layout notes:
35 *
36 * Kernel and user threads run within one common virtual address space
37 * defined by AS=0.
38 *
39 * 32-bit pmap:
40 * Virtual address space layout:
41 * -----------------------------
42 * 0x0000_0000 - 0x7fff_ffff : user process
43 * 0x8000_0000 - 0xbfff_ffff : pmap_mapdev()-ed area (PCI/PCIE etc.)
44 * 0xc000_0000 - 0xc0ff_ffff : kernel reserved
45 * 0xc000_0000 - data_end : kernel code+data, env, metadata etc.
46 * 0xc100_0000 - 0xffff_ffff : KVA
47 * 0xc100_0000 - 0xc100_3fff : reserved for page zero/copy
48 * 0xc100_4000 - 0xc200_3fff : reserved for ptbl bufs
49 * 0xc200_4000 - 0xc200_8fff : guard page + kstack0
50 * 0xc200_9000 - 0xfeef_ffff : actual free KVA space
51 *
52 * 64-bit pmap:
53 * Virtual address space layout:
54 * -----------------------------
55 * 0x0000_0000_0000_0000 - 0xbfff_ffff_ffff_ffff : user process
56 * 0x0000_0000_0000_0000 - 0x8fff_ffff_ffff_ffff : text, data, heap, maps, libraries
57 * 0x9000_0000_0000_0000 - 0xafff_ffff_ffff_ffff : mmio region
58 * 0xb000_0000_0000_0000 - 0xbfff_ffff_ffff_ffff : stack
59 * 0xc000_0000_0000_0000 - 0xcfff_ffff_ffff_ffff : kernel reserved
60 * 0xc000_0000_0000_0000 - endkernel-1 : kernel code & data
61 * endkernel - msgbufp-1 : flat device tree
62 * msgbufp - kernel_pdir-1 : message buffer
63 * kernel_pdir - kernel_pp2d-1 : kernel page directory
64 * kernel_pp2d - . : kernel pointers to page directory
65 * pmap_zero_copy_min - crashdumpmap-1 : reserved for page zero/copy
66 * crashdumpmap - ptbl_buf_pool_vabase-1 : reserved for ptbl bufs
67 * ptbl_buf_pool_vabase - virtual_avail-1 : user page directories and page tables
68 * virtual_avail - 0xcfff_ffff_ffff_ffff : actual free KVA space
69 * 0xd000_0000_0000_0000 - 0xdfff_ffff_ffff_ffff : coprocessor region
70 * 0xe000_0000_0000_0000 - 0xefff_ffff_ffff_ffff : mmio region
71 * 0xf000_0000_0000_0000 - 0xffff_ffff_ffff_ffff : direct map
72 * 0xf000_0000_0000_0000 - +Maxmem : physmem map
73 * - 0xffff_ffff_ffff_ffff : device direct map
74 */
75
76 #include <sys/cdefs.h>
77 #include "opt_ddb.h"
78 #include "opt_kstack_pages.h"
79
80 #include <sys/param.h>
81 #include <sys/conf.h>
82 #include <sys/malloc.h>
83 #include <sys/ktr.h>
84 #include <sys/proc.h>
85 #include <sys/user.h>
86 #include <sys/queue.h>
87 #include <sys/systm.h>
88 #include <sys/kernel.h>
89 #include <sys/kerneldump.h>
90 #include <sys/limits.h>
91 #include <sys/linker.h>
92 #include <sys/msgbuf.h>
93 #include <sys/lock.h>
94 #include <sys/mutex.h>
95 #include <sys/rwlock.h>
96 #include <sys/sched.h>
97 #include <sys/smp.h>
98 #include <sys/vmmeter.h>
99
100 #include <vm/vm.h>
101 #include <vm/vm_param.h>
102 #include <vm/vm_page.h>
103 #include <vm/vm_kern.h>
104 #include <vm/vm_pageout.h>
105 #include <vm/vm_extern.h>
106 #include <vm/vm_object.h>
107 #include <vm/vm_map.h>
108 #include <vm/vm_pager.h>
109 #include <vm/vm_phys.h>
110 #include <vm/vm_pagequeue.h>
111 #include <vm/vm_radix.h>
112 #include <vm/vm_dumpset.h>
113 #include <vm/uma.h>
114
115 #include <machine/_inttypes.h>
116 #include <machine/cpu.h>
117 #include <machine/pcb.h>
118 #include <machine/platform.h>
119
120 #include <machine/tlb.h>
121 #include <machine/spr.h>
122 #include <machine/md_var.h>
123 #include <machine/mmuvar.h>
124 #include <machine/pmap.h>
125 #include <machine/pte.h>
126
127 #include <ddb/ddb.h>
128
129 #define SPARSE_MAPDEV
130
131 /* Use power-of-two mappings in mmu_booke_mapdev(), to save entries. */
132 #define POW2_MAPPINGS
133
134 #ifdef DEBUG
135 #define debugf(fmt, args...) printf(fmt, ##args)
136 #define __debug_used
137 #else
138 #define debugf(fmt, args...)
139 #define __debug_used __unused
140 #endif
141
142 #ifdef __powerpc64__
143 #define PRI0ptrX "016lx"
144 #else
145 #define PRI0ptrX "08x"
146 #endif
147
148 #define TODO panic("%s: not implemented", __func__);
149
150 extern unsigned char _etext[];
151 extern unsigned char _end[];
152
153 extern uint32_t *bootinfo;
154
155 vm_paddr_t kernload;
156 vm_offset_t kernstart;
157 vm_size_t kernsize;
158
159 /* Message buffer and tables. */
160 static vm_offset_t data_start;
161 static vm_size_t data_end;
162
163 /* Phys/avail memory regions. */
164 static struct mem_region *availmem_regions;
165 static int availmem_regions_sz;
166 static struct mem_region *physmem_regions;
167 static int physmem_regions_sz;
168
169 #ifndef __powerpc64__
170 /* Reserved KVA space and mutex for mmu_booke_zero_page. */
171 static vm_offset_t zero_page_va;
172 static struct mtx zero_page_mutex;
173
174 /* Reserved KVA space and mutex for mmu_booke_copy_page. */
175 static vm_offset_t copy_page_src_va;
176 static vm_offset_t copy_page_dst_va;
177 static struct mtx copy_page_mutex;
178 #endif
179
180 static struct mtx tlbivax_mutex;
181 static bool mmuv2;
182
183 /**************************************************************************/
184 /* PMAP */
185 /**************************************************************************/
186
187 static int mmu_booke_enter_locked(pmap_t, vm_offset_t, vm_page_t,
188 vm_prot_t, u_int flags, int8_t psind);
189
190 unsigned int kptbl_min; /* Index of the first kernel ptbl. */
191 static uma_zone_t ptbl_root_zone;
192
193 /*
194 * If user pmap is processed with mmu_booke_remove and the resident count
195 * drops to 0, there are no more pages to remove, so we need not continue.
196 */
197 #define PMAP_REMOVE_DONE(pmap) \
198 ((pmap) != kernel_pmap && (pmap)->pm_stats.resident_count == 0)
199
200 #if defined(COMPAT_FREEBSD32) || !defined(__powerpc64__)
201 extern int elf32_nxstack;
202 #endif
203
204 /**************************************************************************/
205 /* TLB and TID handling */
206 /**************************************************************************/
207
208 /* Translation ID busy table (dynamically allocated) */
209 static __inline void tid_set_busy(int cpu, int tid, pmap_t pmap);
210 static volatile pmap_t *tidbusy;
211 uint32_t tid_max;
212
213 /*
214 * TLB0 capabilities (entry, way numbers etc.). These can vary between e500
215 * core revisions and should be read from h/w registers during early config.
216 */
217 uint32_t tlb0_entries;
218 uint32_t tlb0_ways;
219 uint32_t tlb0_entries_per_way;
220 uint32_t tlb1_entries;
221
222 #define TLB0_ENTRIES (tlb0_entries)
223 #define TLB0_WAYS (tlb0_ways)
224 #define TLB0_ENTRIES_PER_WAY (tlb0_entries_per_way)
225
226 #define TLB1_ENTRIES (tlb1_entries)
227
228 static tlbtid_t tid_alloc(struct pmap *);
229
230 #ifdef DDB
231 #ifdef __powerpc64__
232 static void tlb_print_entry(int, uint32_t, uint64_t, uint32_t, uint32_t);
233 #else
234 static void tlb_print_entry(int, uint32_t, uint32_t, uint32_t, uint32_t);
235 #endif
236 #endif
237
238 static void tlb1_read_entry(tlb_entry_t *, unsigned int);
239 static void tlb1_write_entry(tlb_entry_t *, unsigned int);
240 static int tlb1_iomapped(int, vm_paddr_t, vm_size_t, vm_offset_t *);
241 static vm_size_t tlb1_mapin_region(vm_offset_t, vm_paddr_t, vm_size_t, int);
242
243 static __inline uint32_t tlb_calc_wimg(vm_paddr_t pa, vm_memattr_t ma);
244
245 static vm_size_t tsize2size(unsigned int);
246 static unsigned int size2tsize(vm_size_t);
247
248 static void set_mas4_defaults(void);
249
250 static inline void tlb0_flush_entry(vm_offset_t);
251 static inline unsigned int tlb0_tableidx(vm_offset_t, unsigned int);
252
253 /**************************************************************************/
254 /* Page table management */
255 /**************************************************************************/
256
257 static struct rwlock_padalign pvh_global_lock;
258
259 /* Data for the pv entry allocation mechanism */
260 static uma_zone_t pvzone;
261 static int pv_entry_count = 0, pv_entry_max = 0, pv_entry_high_water = 0;
262
263 #define PV_ENTRY_ZONE_MIN 2048 /* min pv entries in uma zone */
264
265 #ifndef PMAP_SHPGPERPROC
266 #define PMAP_SHPGPERPROC 200
267 #endif
268
269 static vm_paddr_t pte_vatopa(pmap_t, vm_offset_t);
270 static int pte_enter(pmap_t, vm_page_t, vm_offset_t, uint32_t, bool);
271 static int pte_remove(pmap_t, vm_offset_t, uint8_t);
272 static pte_t *pte_find(pmap_t, vm_offset_t);
273 static void kernel_pte_alloc(vm_offset_t, vm_offset_t);
274
275 static pv_entry_t pv_alloc(void);
276 static void pv_free(pv_entry_t);
277 static void pv_insert(pmap_t, vm_offset_t, vm_page_t);
278 static void pv_remove(pmap_t, vm_offset_t, vm_page_t);
279
280 static void booke_pmap_init_qpages(void);
281
282 static inline void tlb_miss_lock(void);
283 static inline void tlb_miss_unlock(void);
284
285 #ifdef SMP
286 extern tlb_entry_t __boot_tlb1[];
287 void pmap_bootstrap_ap(volatile uint32_t *);
288 #endif
289
290 /*
291 * Kernel MMU interface
292 */
293 static void mmu_booke_clear_modify(vm_page_t);
294 static void mmu_booke_copy(pmap_t, pmap_t, vm_offset_t,
295 vm_size_t, vm_offset_t);
296 static void mmu_booke_copy_page(vm_page_t, vm_page_t);
297 static void mmu_booke_copy_pages(vm_page_t *,
298 vm_offset_t, vm_page_t *, vm_offset_t, int);
299 static int mmu_booke_enter(pmap_t, vm_offset_t, vm_page_t,
300 vm_prot_t, u_int flags, int8_t psind);
301 static void mmu_booke_enter_object(pmap_t, vm_offset_t, vm_offset_t,
302 vm_page_t, vm_prot_t);
303 static void mmu_booke_enter_quick(pmap_t, vm_offset_t, vm_page_t,
304 vm_prot_t);
305 static vm_paddr_t mmu_booke_extract(pmap_t, vm_offset_t);
306 static vm_page_t mmu_booke_extract_and_hold(pmap_t, vm_offset_t,
307 vm_prot_t);
308 static void mmu_booke_init(void);
309 static bool mmu_booke_is_modified(vm_page_t);
310 static bool mmu_booke_is_prefaultable(pmap_t, vm_offset_t);
311 static bool mmu_booke_is_referenced(vm_page_t);
312 static int mmu_booke_ts_referenced(vm_page_t);
313 static void *mmu_booke_map(vm_offset_t *, vm_paddr_t, vm_paddr_t,
314 int);
315 static int mmu_booke_mincore(pmap_t, vm_offset_t,
316 vm_paddr_t *);
317 static void mmu_booke_object_init_pt(pmap_t, vm_offset_t,
318 vm_object_t, vm_pindex_t, vm_size_t);
319 static bool mmu_booke_page_exists_quick(pmap_t, vm_page_t);
320 static void mmu_booke_page_init(vm_page_t);
321 static int mmu_booke_page_wired_mappings(vm_page_t);
322 static int mmu_booke_pinit(pmap_t);
323 static void mmu_booke_pinit0(pmap_t);
324 static void mmu_booke_protect(pmap_t, vm_offset_t, vm_offset_t,
325 vm_prot_t);
326 static void mmu_booke_qenter(void *, vm_page_t *, int);
327 static void mmu_booke_qremove(void *, int);
328 static void mmu_booke_release(pmap_t);
329 static void mmu_booke_remove(pmap_t, vm_offset_t, vm_offset_t);
330 static void mmu_booke_remove_all(vm_page_t);
331 static void mmu_booke_remove_write(vm_page_t);
332 static void mmu_booke_unwire(pmap_t, vm_offset_t, vm_offset_t);
333 static void mmu_booke_zero_page(vm_page_t);
334 static void mmu_booke_zero_page_area(vm_page_t, int, int);
335 static void mmu_booke_activate(struct thread *);
336 static void mmu_booke_deactivate(struct thread *);
337 static void mmu_booke_bootstrap(vm_offset_t, vm_offset_t);
338 static void *mmu_booke_mapdev(vm_paddr_t, vm_size_t);
339 static void *mmu_booke_mapdev_attr(vm_paddr_t, vm_size_t, vm_memattr_t);
340 static void mmu_booke_unmapdev(void *, vm_size_t);
341 static vm_paddr_t mmu_booke_kextract(vm_offset_t);
342 static void mmu_booke_kenter(vm_offset_t, vm_paddr_t);
343 static void mmu_booke_kenter_attr(vm_offset_t, vm_paddr_t, vm_memattr_t);
344 static void mmu_booke_kremove(vm_offset_t);
345 static int mmu_booke_dev_direct_mapped(vm_paddr_t, vm_size_t);
346 static void mmu_booke_sync_icache(pmap_t, vm_offset_t,
347 vm_size_t);
348 static void mmu_booke_dumpsys_map(vm_paddr_t pa, size_t,
349 void **);
350 static void mmu_booke_dumpsys_unmap(vm_paddr_t pa, size_t,
351 void *);
352 static void mmu_booke_scan_init(void);
353 static void *mmu_booke_quick_enter_page(vm_page_t m);
354 static void mmu_booke_quick_remove_page(void *addr);
355 static int mmu_booke_change_attr(void *addr,
356 vm_size_t sz, vm_memattr_t mode);
357 static int mmu_booke_decode_kernel_ptr(vm_offset_t addr,
358 int *is_user, vm_offset_t *decoded_addr);
359 static void mmu_booke_page_array_startup(long);
360 static bool mmu_booke_page_is_mapped(vm_page_t m);
361 static bool mmu_booke_ps_enabled(pmap_t pmap);
362 #ifdef __powerpc64__
363 static int mmu_booke_growkernel(vm_offset_t);
364 #endif
365
366 static struct pmap_funcs mmu_booke_methods = {
367 /* pmap dispatcher interface */
368 .clear_modify = mmu_booke_clear_modify,
369 .copy = mmu_booke_copy,
370 .copy_page = mmu_booke_copy_page,
371 .copy_pages = mmu_booke_copy_pages,
372 .enter = mmu_booke_enter,
373 .enter_object = mmu_booke_enter_object,
374 .enter_quick = mmu_booke_enter_quick,
375 .extract = mmu_booke_extract,
376 .extract_and_hold = mmu_booke_extract_and_hold,
377 .init = mmu_booke_init,
378 .is_modified = mmu_booke_is_modified,
379 .is_prefaultable = mmu_booke_is_prefaultable,
380 .is_referenced = mmu_booke_is_referenced,
381 .ts_referenced = mmu_booke_ts_referenced,
382 .map = mmu_booke_map,
383 .mincore = mmu_booke_mincore,
384 .object_init_pt = mmu_booke_object_init_pt,
385 .page_exists_quick = mmu_booke_page_exists_quick,
386 .page_init = mmu_booke_page_init,
387 .page_wired_mappings = mmu_booke_page_wired_mappings,
388 .pinit = mmu_booke_pinit,
389 .pinit0 = mmu_booke_pinit0,
390 .protect = mmu_booke_protect,
391 .qenter = mmu_booke_qenter,
392 .qremove = mmu_booke_qremove,
393 .release = mmu_booke_release,
394 .remove = mmu_booke_remove,
395 .remove_all = mmu_booke_remove_all,
396 .remove_write = mmu_booke_remove_write,
397 .sync_icache = mmu_booke_sync_icache,
398 .unwire = mmu_booke_unwire,
399 .zero_page = mmu_booke_zero_page,
400 .zero_page_area = mmu_booke_zero_page_area,
401 .activate = mmu_booke_activate,
402 .deactivate = mmu_booke_deactivate,
403 .quick_enter_page = mmu_booke_quick_enter_page,
404 .quick_remove_page = mmu_booke_quick_remove_page,
405 .page_array_startup = mmu_booke_page_array_startup,
406 .page_is_mapped = mmu_booke_page_is_mapped,
407 .ps_enabled = mmu_booke_ps_enabled,
408 #ifdef __powerpc64__
409 .growkernel_nopanic = mmu_booke_growkernel,
410 #endif
411
412 /* Internal interfaces */
413 .bootstrap = mmu_booke_bootstrap,
414 .dev_direct_mapped = mmu_booke_dev_direct_mapped,
415 .mapdev = mmu_booke_mapdev,
416 .mapdev_attr = mmu_booke_mapdev_attr,
417 .kenter = mmu_booke_kenter,
418 .kenter_attr = mmu_booke_kenter_attr,
419 .kextract = mmu_booke_kextract,
420 .kremove = mmu_booke_kremove,
421 .unmapdev = mmu_booke_unmapdev,
422 .change_attr = mmu_booke_change_attr,
423 .decode_kernel_ptr = mmu_booke_decode_kernel_ptr,
424
425 /* dumpsys() support */
426 .dumpsys_map_chunk = mmu_booke_dumpsys_map,
427 .dumpsys_unmap_chunk = mmu_booke_dumpsys_unmap,
428 .dumpsys_pa_init = mmu_booke_scan_init,
429 };
430
431 MMU_DEF(booke_mmu, MMU_TYPE_BOOKE, mmu_booke_methods);
432
433 #ifdef __powerpc64__
434 #include "pmap_64.c"
435 #else
436 #include "pmap_32.c"
437 #endif
438
439 static vm_offset_t tlb1_map_base = VM_MAPDEV_BASE;
440
441 static __inline uint32_t
tlb_calc_wimg(vm_paddr_t pa,vm_memattr_t ma)442 tlb_calc_wimg(vm_paddr_t pa, vm_memattr_t ma)
443 {
444 uint32_t attrib;
445 int i;
446
447 if (ma != VM_MEMATTR_DEFAULT) {
448 switch (ma) {
449 case VM_MEMATTR_UNCACHEABLE:
450 return (MAS2_I | MAS2_G);
451 case VM_MEMATTR_WRITE_COMBINING:
452 case VM_MEMATTR_WRITE_BACK:
453 case VM_MEMATTR_PREFETCHABLE:
454 return (MAS2_I);
455 case VM_MEMATTR_WRITE_THROUGH:
456 return (MAS2_W | MAS2_M);
457 case VM_MEMATTR_CACHEABLE:
458 return (MAS2_M);
459 }
460 }
461
462 /*
463 * Assume the page is cache inhibited and access is guarded unless
464 * it's in our available memory array.
465 */
466 attrib = _TLB_ENTRY_IO;
467 for (i = 0; i < physmem_regions_sz; i++) {
468 if ((pa >= physmem_regions[i].mr_start) &&
469 (pa < (physmem_regions[i].mr_start +
470 physmem_regions[i].mr_size))) {
471 attrib = _TLB_ENTRY_MEM;
472 break;
473 }
474 }
475
476 return (attrib);
477 }
478
479 static inline void
tlb_miss_lock(void)480 tlb_miss_lock(void)
481 {
482 #ifdef SMP
483 struct pcpu *pc;
484
485 if (!smp_started)
486 return;
487
488 STAILQ_FOREACH(pc, &cpuhead, pc_allcpu) {
489 if (pc != pcpup) {
490 CTR3(KTR_PMAP, "%s: tlb miss LOCK of CPU=%d, "
491 "tlb_lock=%p", __func__, pc->pc_cpuid, pc->pc_booke.tlb_lock);
492
493 KASSERT((pc->pc_cpuid != PCPU_GET(cpuid)),
494 ("tlb_miss_lock: tried to lock self"));
495
496 tlb_lock(pc->pc_booke.tlb_lock);
497
498 CTR1(KTR_PMAP, "%s: locked", __func__);
499 }
500 }
501 #endif
502 }
503
504 static inline void
tlb_miss_unlock(void)505 tlb_miss_unlock(void)
506 {
507 #ifdef SMP
508 struct pcpu *pc;
509
510 if (!smp_started)
511 return;
512
513 STAILQ_FOREACH(pc, &cpuhead, pc_allcpu) {
514 if (pc != pcpup) {
515 CTR2(KTR_PMAP, "%s: tlb miss UNLOCK of CPU=%d",
516 __func__, pc->pc_cpuid);
517
518 tlb_unlock(pc->pc_booke.tlb_lock);
519
520 CTR1(KTR_PMAP, "%s: unlocked", __func__);
521 }
522 }
523 #endif
524 }
525
526 /* Return number of entries in TLB0. */
527 static __inline void
tlb0_get_tlbconf(void)528 tlb0_get_tlbconf(void)
529 {
530 uint32_t tlb0_cfg;
531
532 tlb0_cfg = mfspr(SPR_TLB0CFG);
533 tlb0_entries = tlb0_cfg & TLBCFG_NENTRY_MASK;
534 tlb0_ways = (tlb0_cfg & TLBCFG_ASSOC_MASK) >> TLBCFG_ASSOC_SHIFT;
535 tlb0_entries_per_way = tlb0_entries / tlb0_ways;
536 }
537
538 /* Return number of entries in TLB1. */
539 static __inline void
tlb1_get_tlbconf(void)540 tlb1_get_tlbconf(void)
541 {
542 uint32_t tlb1_cfg;
543
544 tlb1_cfg = mfspr(SPR_TLB1CFG);
545 tlb1_entries = tlb1_cfg & TLBCFG_NENTRY_MASK;
546 }
547
548 /**************************************************************************/
549 /* Page table related */
550 /**************************************************************************/
551
552 /* Allocate pv_entry structure. */
553 pv_entry_t
pv_alloc(void)554 pv_alloc(void)
555 {
556 pv_entry_t pv;
557
558 pv_entry_count++;
559 if (pv_entry_count > pv_entry_high_water)
560 pagedaemon_wakeup(0); /* XXX powerpc NUMA */
561 pv = uma_zalloc(pvzone, M_NOWAIT);
562
563 return (pv);
564 }
565
566 /* Free pv_entry structure. */
567 static __inline void
pv_free(pv_entry_t pve)568 pv_free(pv_entry_t pve)
569 {
570
571 pv_entry_count--;
572 uma_zfree(pvzone, pve);
573 }
574
575 /* Allocate and initialize pv_entry structure. */
576 static void
pv_insert(pmap_t pmap,vm_offset_t va,vm_page_t m)577 pv_insert(pmap_t pmap, vm_offset_t va, vm_page_t m)
578 {
579 pv_entry_t pve;
580
581 //int su = (pmap == kernel_pmap);
582 //debugf("pv_insert: s (su = %d pmap = 0x%08x va = 0x%08x m = 0x%08x)\n", su,
583 // (u_int32_t)pmap, va, (u_int32_t)m);
584
585 pve = pv_alloc();
586 if (pve == NULL)
587 panic("pv_insert: no pv entries!");
588
589 pve->pv_pmap = pmap;
590 pve->pv_va = va;
591
592 /* add to pv_list */
593 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
594 rw_assert(&pvh_global_lock, RA_WLOCKED);
595
596 TAILQ_INSERT_TAIL(&m->md.pv_list, pve, pv_link);
597
598 //debugf("pv_insert: e\n");
599 }
600
601 /* Destroy pv entry. */
602 static void
pv_remove(pmap_t pmap,vm_offset_t va,vm_page_t m)603 pv_remove(pmap_t pmap, vm_offset_t va, vm_page_t m)
604 {
605 pv_entry_t pve;
606
607 //int su = (pmap == kernel_pmap);
608 //debugf("pv_remove: s (su = %d pmap = 0x%08x va = 0x%08x)\n", su, (u_int32_t)pmap, va);
609
610 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
611 rw_assert(&pvh_global_lock, RA_WLOCKED);
612
613 /* find pv entry */
614 TAILQ_FOREACH(pve, &m->md.pv_list, pv_link) {
615 if ((pmap == pve->pv_pmap) && (va == pve->pv_va)) {
616 /* remove from pv_list */
617 TAILQ_REMOVE(&m->md.pv_list, pve, pv_link);
618 if (TAILQ_EMPTY(&m->md.pv_list))
619 vm_page_aflag_clear(m, PGA_WRITEABLE);
620
621 /* free pv entry struct */
622 pv_free(pve);
623 break;
624 }
625 }
626
627 //debugf("pv_remove: e\n");
628 }
629
630 /**************************************************************************/
631 /* PMAP related */
632 /**************************************************************************/
633
634 /*
635 * This is called during booke_init, before the system is really initialized.
636 */
637 static void
mmu_booke_bootstrap(vm_offset_t start,vm_offset_t kernelend)638 mmu_booke_bootstrap(vm_offset_t start, vm_offset_t kernelend)
639 {
640 vm_paddr_t phys_kernelend;
641 struct mem_region *mp, *mp1;
642 int cnt, i, j;
643 vm_paddr_t s, e, sz;
644 vm_paddr_t physsz, hwphyssz;
645 u_int phys_avail_count __debug_used;
646 vm_size_t kstack0_sz;
647 vm_paddr_t kstack0_phys;
648 vm_offset_t kstack0;
649 uint32_t tid_bits;
650 void *dpcpu;
651
652 debugf("mmu_booke_bootstrap: entered\n");
653
654 if ((mfspr(SPR_MMUCFG) & MMUCFG_MAVN_M) > 0)
655 mmuv2 = true;
656
657 /* Set interesting system properties */
658 #ifdef __powerpc64__
659 hw_direct_map = 1;
660 #else
661 hw_direct_map = 0;
662 #endif
663 #if defined(COMPAT_FREEBSD32) || !defined(__powerpc64__)
664 elf32_nxstack = 1;
665 #endif
666
667 /* Initialize invalidation mutex */
668 mtx_init(&tlbivax_mutex, "tlbivax", NULL, MTX_SPIN);
669
670 /* Read TLB0 size and associativity. */
671 tlb0_get_tlbconf();
672
673 /*
674 * Calculate the max TID from the hardware. Allow overriding with a
675 * tunable. The tunable should be a power of 2.
676 */
677 tid_bits = ((mfspr(SPR_MMUCFG) & MMUCFG_PIDSIZE_M) >> MMUCFG_PIDSIZE_S);
678 TUNABLE_INT_FETCH("machdep.tid_max", &tid_max);
679 if (tid_max <= 0)
680 tid_max = INT_MAX;
681 else
682 tid_max = 1 << ilog2(tid_max);
683 tid_max = min((1 << tid_bits), tid_max) - 1;
684
685 /*
686 * Align kernel start and end address (kernel image).
687 * Note that kernel end does not necessarily relate to kernsize.
688 * kernsize is the size of the kernel that is actually mapped.
689 */
690 data_start = round_page(kernelend);
691 data_end = data_start;
692
693 tidbusy = (void *)data_end;
694 printf("tidbusy at %p\n", tidbusy);
695 printf("tidmax = %d\n", tid_max);
696 data_end += round_page(sizeof(pmap_t) * MAXCPU * (tid_max + 1));
697
698 /* Allocate the dynamic per-cpu area. */
699 dpcpu = (void *)data_end;
700 data_end += DPCPU_SIZE;
701
702 /* Allocate space for the message buffer. */
703 msgbufp = (struct msgbuf *)data_end;
704 data_end += msgbufsize;
705 debugf(" msgbufp at 0x%"PRI0ptrX" end = 0x%"PRI0ptrX"\n",
706 (uintptr_t)msgbufp, data_end);
707
708 data_end = round_page(data_end);
709
710 /* Retrieve phys/avail mem regions */
711 mem_regions(&physmem_regions, &physmem_regions_sz,
712 &availmem_regions, &availmem_regions_sz);
713
714 if (PHYS_AVAIL_ENTRIES < availmem_regions_sz)
715 panic("mmu_booke_bootstrap: phys_avail too small");
716
717 vm_page_array = (vm_page_t)data_end;
718 /*
719 * Get a rough idea (upper bound) on the size of the page array. The
720 * vm_page_array will not handle any more pages than we have in the
721 * avail_regions array, and most likely much less.
722 */
723 sz = 0;
724 for (mp = availmem_regions; mp->mr_size; mp++) {
725 sz += mp->mr_size;
726 }
727 sz = (round_page(sz) / (PAGE_SIZE + sizeof(struct vm_page)));
728 data_end += round_page(sz * sizeof(struct vm_page));
729
730 /*
731 * Reserve kernel page-table pages last, so their reservation size can
732 * be computed from the final bootstrap data_end (on 64-bit, only leaf
733 * ptbls covering [VM_MIN_KERNEL_ADDRESS, data_end + slack] are
734 * pre-allocated; the rest are added on demand by pmap_growkernel()).
735 */
736 data_end = round_page(mmu_booke_alloc_kernel_pgtables(data_end));
737
738 /* Pre-round up to 1MB. This wastes some space, but saves TLB entries */
739 data_end = roundup2(data_end, 1 << 20);
740
741 debugf(" data_end: 0x%"PRI0ptrX"\n", data_end);
742 debugf(" kernstart: %#zx\n", kernstart);
743 debugf(" kernsize: %#zx\n", kernsize);
744
745 if (data_end - kernstart > kernsize) {
746 kernsize += tlb1_mapin_region(kernstart + kernsize,
747 kernload + kernsize, (data_end - kernstart) - kernsize,
748 _TLB_ENTRY_MEM);
749 }
750 data_end = kernstart + kernsize;
751 debugf(" updated data_end: 0x%"PRI0ptrX"\n", data_end);
752
753 /*
754 * Clear the structures - note we can only do it safely after the
755 * possible additional TLB1 translations are in place (above) so that
756 * all range up to the currently calculated 'data_end' is covered.
757 */
758 bzero((void *)data_start, data_end - data_start);
759 dpcpu_init(dpcpu, 0);
760
761 /*******************************************************/
762 /* Set the start and end of kva. */
763 /*******************************************************/
764 virtual_avail = round_page(data_end);
765 virtual_end = VM_MAX_KERNEL_ADDRESS;
766
767 #ifndef __powerpc64__
768 /* Allocate KVA space for page zero/copy operations. */
769 zero_page_va = virtual_avail;
770 virtual_avail += PAGE_SIZE;
771 copy_page_src_va = virtual_avail;
772 virtual_avail += PAGE_SIZE;
773 copy_page_dst_va = virtual_avail;
774 virtual_avail += PAGE_SIZE;
775 debugf("zero_page_va = 0x%"PRI0ptrX"\n", zero_page_va);
776 debugf("copy_page_src_va = 0x%"PRI0ptrX"\n", copy_page_src_va);
777 debugf("copy_page_dst_va = 0x%"PRI0ptrX"\n", copy_page_dst_va);
778
779 /* Initialize page zero/copy mutexes. */
780 mtx_init(&zero_page_mutex, "mmu_booke_zero_page", NULL, MTX_DEF);
781 mtx_init(©_page_mutex, "mmu_booke_copy_page", NULL, MTX_DEF);
782
783 /* Allocate KVA space for ptbl bufs. */
784 ptbl_buf_pool_vabase = virtual_avail;
785 virtual_avail += PTBL_BUFS * PTBL_PAGES * PAGE_SIZE;
786 debugf("ptbl_buf_pool_vabase = 0x%"PRI0ptrX" end = 0x%"PRI0ptrX"\n",
787 ptbl_buf_pool_vabase, virtual_avail);
788 #endif
789 #ifdef __powerpc64__
790 /* Allocate KVA space for crashdumpmap. */
791 crashdumpmap = (caddr_t)virtual_avail;
792 virtual_avail += MAXDUMPPGS * PAGE_SIZE;
793 #endif
794
795 /* Calculate corresponding physical addresses for the kernel region. */
796 phys_kernelend = kernload + kernsize;
797 debugf("kernel image and allocated data:\n");
798 debugf(" kernload = 0x%09jx\n", (uintmax_t)kernload);
799 debugf(" kernstart = 0x%"PRI0ptrX"\n", kernstart);
800 debugf(" kernsize = 0x%"PRI0ptrX"\n", kernsize);
801
802 /*
803 * Remove kernel physical address range from avail regions list. Page
804 * align all regions. Non-page aligned memory isn't very interesting
805 * to us. Also, sort the entries for ascending addresses.
806 */
807
808 sz = 0;
809 cnt = availmem_regions_sz;
810 debugf("processing avail regions:\n");
811 for (mp = availmem_regions; mp->mr_size; mp++) {
812 s = mp->mr_start;
813 e = mp->mr_start + mp->mr_size;
814 debugf(" %09jx-%09jx -> ", (uintmax_t)s, (uintmax_t)e);
815 /* Check whether this region holds all of the kernel. */
816 if (s < kernload && e > phys_kernelend) {
817 availmem_regions[cnt].mr_start = phys_kernelend;
818 availmem_regions[cnt++].mr_size = e - phys_kernelend;
819 e = kernload;
820 }
821 /* Look whether this regions starts within the kernel. */
822 if (s >= kernload && s < phys_kernelend) {
823 if (e <= phys_kernelend)
824 goto empty;
825 s = phys_kernelend;
826 }
827 /* Now look whether this region ends within the kernel. */
828 if (e > kernload && e <= phys_kernelend) {
829 if (s >= kernload)
830 goto empty;
831 e = kernload;
832 }
833 /* Now page align the start and size of the region. */
834 s = round_page(s);
835 e = trunc_page(e);
836 if (e < s)
837 e = s;
838 sz = e - s;
839 debugf("%09jx-%09jx = %jx\n",
840 (uintmax_t)s, (uintmax_t)e, (uintmax_t)sz);
841
842 /* Check whether some memory is left here. */
843 if (sz == 0) {
844 empty:
845 memmove(mp, mp + 1,
846 (cnt - (mp - availmem_regions)) * sizeof(*mp));
847 cnt--;
848 mp--;
849 continue;
850 }
851
852 /* Do an insertion sort. */
853 for (mp1 = availmem_regions; mp1 < mp; mp1++)
854 if (s < mp1->mr_start)
855 break;
856 if (mp1 < mp) {
857 memmove(mp1 + 1, mp1, (char *)mp - (char *)mp1);
858 mp1->mr_start = s;
859 mp1->mr_size = sz;
860 } else {
861 mp->mr_start = s;
862 mp->mr_size = sz;
863 }
864 }
865 availmem_regions_sz = cnt;
866
867 /*******************************************************/
868 /* Steal physical memory for kernel stack from the end */
869 /* of the first avail region */
870 /*******************************************************/
871 kstack0_sz = kstack_pages * PAGE_SIZE;
872 kstack0_phys = availmem_regions[0].mr_start +
873 availmem_regions[0].mr_size;
874 kstack0_phys -= kstack0_sz;
875 availmem_regions[0].mr_size -= kstack0_sz;
876
877 /*******************************************************/
878 /* Fill in phys_avail table, based on availmem_regions */
879 /*******************************************************/
880 phys_avail_count = 0;
881 physsz = 0;
882 hwphyssz = 0;
883 TUNABLE_ULONG_FETCH("hw.physmem", (u_long *) &hwphyssz);
884
885 debugf("fill in phys_avail:\n");
886 for (i = 0, j = 0; i < availmem_regions_sz; i++, j += 2) {
887 debugf(" region: 0x%jx - 0x%jx (0x%jx)\n",
888 (uintmax_t)availmem_regions[i].mr_start,
889 (uintmax_t)availmem_regions[i].mr_start +
890 availmem_regions[i].mr_size,
891 (uintmax_t)availmem_regions[i].mr_size);
892
893 if (hwphyssz != 0 &&
894 (physsz + availmem_regions[i].mr_size) >= hwphyssz) {
895 debugf(" hw.physmem adjust\n");
896 if (physsz < hwphyssz) {
897 phys_avail[j] = availmem_regions[i].mr_start;
898 phys_avail[j + 1] =
899 availmem_regions[i].mr_start +
900 hwphyssz - physsz;
901 physsz = hwphyssz;
902 phys_avail_count++;
903 dump_avail[j] = phys_avail[j];
904 dump_avail[j + 1] = phys_avail[j + 1];
905 }
906 break;
907 }
908
909 phys_avail[j] = availmem_regions[i].mr_start;
910 phys_avail[j + 1] = availmem_regions[i].mr_start +
911 availmem_regions[i].mr_size;
912 phys_avail_count++;
913 physsz += availmem_regions[i].mr_size;
914 dump_avail[j] = phys_avail[j];
915 dump_avail[j + 1] = phys_avail[j + 1];
916 }
917 physmem = btoc(physsz);
918
919 /* Calculate the last available physical address. */
920 for (i = 0; phys_avail[i + 2] != 0; i += 2)
921 ;
922 Maxmem = powerpc_btop(phys_avail[i + 1]);
923
924 debugf("Maxmem = 0x%08lx\n", Maxmem);
925 debugf("phys_avail_count = %d\n", phys_avail_count);
926 debugf("physsz = 0x%09jx physmem = %jd (0x%09jx)\n",
927 (uintmax_t)physsz, (uintmax_t)physmem, (uintmax_t)physmem);
928
929 #ifdef __powerpc64__
930 /*
931 * Map the physical memory contiguously in TLB1.
932 * Round so it fits into a single mapping.
933 */
934 tlb1_mapin_region(DMAP_BASE_ADDRESS, 0,
935 phys_avail[i + 1], _TLB_ENTRY_MEM);
936 #endif
937
938 /*******************************************************/
939 /* Initialize (statically allocated) kernel pmap. */
940 /*******************************************************/
941 mtx_init(&kernel_pmap->pm_mtx, "kernel pmap", NULL, MTX_DEF);
942
943 debugf("kernel_pmap = 0x%"PRI0ptrX"\n", (uintptr_t)kernel_pmap);
944 kernel_pte_alloc(virtual_avail, kernstart);
945 for (i = 0; i < MAXCPU; i++) {
946 kernel_pmap->pm_tid[i] = TID_KERNEL;
947
948 /* Initialize each CPU's tidbusy entry 0 with kernel_pmap */
949 tid_set_busy(i, TID_KERNEL, kernel_pmap);
950 }
951
952 /* Mark kernel_pmap active on all CPUs */
953 CPU_FILL(&kernel_pmap->pm_active);
954
955 /*
956 * Initialize the global pv list lock.
957 */
958 rw_init(&pvh_global_lock, "pmap pv global");
959
960 /*******************************************************/
961 /* Final setup */
962 /*******************************************************/
963
964 /* Enter kstack0 into kernel map, provide guard page */
965 kstack0 = virtual_avail + KSTACK_GUARD_PAGES * PAGE_SIZE;
966 thread0.td_kstack = (char *)kstack0;
967 thread0.td_kstack_pages = kstack_pages;
968
969 debugf("kstack_sz = 0x%08jx\n", (uintmax_t)kstack0_sz);
970 debugf("kstack0_phys at 0x%09jx - 0x%09jx\n",
971 (uintmax_t)kstack0_phys, (uintmax_t)kstack0_phys + kstack0_sz);
972 debugf("kstack0 at 0x%"PRI0ptrX" - 0x%"PRI0ptrX"\n",
973 kstack0, kstack0 + kstack0_sz);
974
975 virtual_avail += KSTACK_GUARD_PAGES * PAGE_SIZE + kstack0_sz;
976 for (i = 0; i < kstack_pages; i++) {
977 mmu_booke_kenter(kstack0, kstack0_phys);
978 kstack0 += PAGE_SIZE;
979 kstack0_phys += PAGE_SIZE;
980 }
981
982 pmap_bootstrapped = 1;
983
984 debugf("virtual_avail = %"PRI0ptrX"\n", virtual_avail);
985 debugf("virtual_end = %"PRI0ptrX"\n", virtual_end);
986
987 debugf("mmu_booke_bootstrap: exit\n");
988 }
989
990 #ifdef SMP
991 void
tlb1_ap_prep(void)992 tlb1_ap_prep(void)
993 {
994 tlb_entry_t *e, tmp;
995 unsigned int i;
996
997 /* Prepare TLB1 image for AP processors */
998 e = __boot_tlb1;
999 for (i = 0; i < TLB1_ENTRIES; i++) {
1000 tlb1_read_entry(&tmp, i);
1001
1002 if ((tmp.mas1 & MAS1_VALID) && (tmp.mas2 & _TLB_ENTRY_SHARED))
1003 memcpy(e++, &tmp, sizeof(tmp));
1004 }
1005 }
1006
1007 void
pmap_bootstrap_ap(volatile uint32_t * trcp __unused)1008 pmap_bootstrap_ap(volatile uint32_t *trcp __unused)
1009 {
1010 int i;
1011
1012 /*
1013 * Finish TLB1 configuration: the BSP already set up its TLB1 and we
1014 * have the snapshot of its contents in the s/w __boot_tlb1[] table
1015 * created by tlb1_ap_prep(), so use these values directly to
1016 * (re)program AP's TLB1 hardware.
1017 *
1018 * Start at index 1 because index 0 has the kernel map.
1019 */
1020 for (i = 1; i < TLB1_ENTRIES; i++) {
1021 if (__boot_tlb1[i].mas1 & MAS1_VALID)
1022 tlb1_write_entry(&__boot_tlb1[i], i);
1023 }
1024
1025 set_mas4_defaults();
1026 }
1027 #endif
1028
1029 static void
booke_pmap_init_qpages(void)1030 booke_pmap_init_qpages(void)
1031 {
1032 struct pcpu *pc;
1033 int i;
1034
1035 CPU_FOREACH(i) {
1036 pc = pcpu_find(i);
1037 pc->pc_qmap_addr = kva_alloc(PAGE_SIZE);
1038 if (pc->pc_qmap_addr == NULL)
1039 panic("pmap_init_qpages: unable to allocate KVA");
1040 }
1041 }
1042
1043 SYSINIT(qpages_init, SI_SUB_CPU, SI_ORDER_ANY, booke_pmap_init_qpages, NULL);
1044
1045 /*
1046 * Get the physical page address for the given pmap/virtual address.
1047 */
1048 static vm_paddr_t
mmu_booke_extract(pmap_t pmap,vm_offset_t va)1049 mmu_booke_extract(pmap_t pmap, vm_offset_t va)
1050 {
1051 vm_paddr_t pa;
1052
1053 PMAP_LOCK(pmap);
1054 pa = pte_vatopa(pmap, va);
1055 PMAP_UNLOCK(pmap);
1056
1057 return (pa);
1058 }
1059
1060 /*
1061 * Extract the physical page address associated with the given
1062 * kernel virtual address.
1063 */
1064 static vm_paddr_t
mmu_booke_kextract(vm_offset_t va)1065 mmu_booke_kextract(vm_offset_t va)
1066 {
1067 tlb_entry_t e;
1068 vm_paddr_t p = 0;
1069 int i;
1070
1071 #ifdef __powerpc64__
1072 if (va >= DMAP_BASE_ADDRESS && va <= DMAP_MAX_ADDRESS)
1073 return (DMAP_TO_PHYS(va));
1074 #endif
1075
1076 if (va >= VM_MIN_KERNEL_ADDRESS && va <= VM_MAX_KERNEL_ADDRESS)
1077 p = pte_vatopa(kernel_pmap, va);
1078
1079 if (p == 0) {
1080 /* Check TLB1 mappings */
1081 for (i = 0; i < TLB1_ENTRIES; i++) {
1082 tlb1_read_entry(&e, i);
1083 if (!(e.mas1 & MAS1_VALID))
1084 continue;
1085 if (va >= e.virt && va < e.virt + e.size)
1086 return (e.phys + (va - e.virt));
1087 }
1088 }
1089
1090 return (p);
1091 }
1092
1093 /*
1094 * Initialize the pmap module.
1095 *
1096 * Called by vm_mem_init(), to initialize any structures that the pmap system
1097 * needs to map virtual memory.
1098 */
1099 static void
mmu_booke_init(void)1100 mmu_booke_init(void)
1101 {
1102 int shpgperproc = PMAP_SHPGPERPROC;
1103
1104 /*
1105 * Initialize the address space (zone) for the pv entries. Set a
1106 * high water mark so that the system can recover from excessive
1107 * numbers of pv entries.
1108 */
1109 pvzone = uma_zcreate("PV ENTRY", sizeof(struct pv_entry), NULL, NULL,
1110 NULL, NULL, UMA_ALIGN_PTR, UMA_ZONE_VM | UMA_ZONE_NOFREE);
1111
1112 TUNABLE_INT_FETCH("vm.pmap.shpgperproc", &shpgperproc);
1113 pv_entry_max = shpgperproc * maxproc + vm_cnt.v_page_count;
1114
1115 TUNABLE_INT_FETCH("vm.pmap.pv_entry_max", &pv_entry_max);
1116 pv_entry_high_water = 9 * (pv_entry_max / 10);
1117
1118 uma_zone_reserve_kva(pvzone, pv_entry_max);
1119
1120 /* Pre-fill pvzone with initial number of pv entries. */
1121 uma_prealloc(pvzone, PV_ENTRY_ZONE_MIN);
1122
1123 /* Create a UMA zone for page table roots. */
1124 ptbl_root_zone = uma_zcreate("pmap root", PMAP_ROOT_SIZE,
1125 NULL, NULL, NULL, NULL, UMA_ALIGN_CACHE, UMA_ZONE_VM);
1126
1127 /* Initialize ptbl allocation. */
1128 ptbl_init();
1129 }
1130
1131 /*
1132 * Map a list of wired pages into kernel virtual address space. This is
1133 * intended for temporary mappings which do not need page modification or
1134 * references recorded. Existing mappings in the region are overwritten.
1135 */
1136 static void
mmu_booke_qenter(void * sva,vm_page_t * m,int count)1137 mmu_booke_qenter(void *sva, vm_page_t *m, int count)
1138 {
1139 vm_offset_t va;
1140
1141 va = (vm_offset_t)sva;
1142 while (count-- > 0) {
1143 mmu_booke_kenter(va, VM_PAGE_TO_PHYS(*m));
1144 va += PAGE_SIZE;
1145 m++;
1146 }
1147 }
1148
1149 /*
1150 * Remove page mappings from kernel virtual address space. Intended for
1151 * temporary mappings entered by mmu_booke_qenter.
1152 */
1153 static void
mmu_booke_qremove(void * sva,int count)1154 mmu_booke_qremove(void *sva, int count)
1155 {
1156 vm_offset_t va;
1157
1158 va = (vm_offset_t)sva;
1159 while (count-- > 0) {
1160 mmu_booke_kremove(va);
1161 va += PAGE_SIZE;
1162 }
1163 }
1164
1165 /*
1166 * Map a wired page into kernel virtual address space.
1167 */
1168 static void
mmu_booke_kenter(vm_offset_t va,vm_paddr_t pa)1169 mmu_booke_kenter(vm_offset_t va, vm_paddr_t pa)
1170 {
1171
1172 mmu_booke_kenter_attr(va, pa, VM_MEMATTR_DEFAULT);
1173 }
1174
1175 static void
mmu_booke_kenter_attr(vm_offset_t va,vm_paddr_t pa,vm_memattr_t ma)1176 mmu_booke_kenter_attr(vm_offset_t va, vm_paddr_t pa, vm_memattr_t ma)
1177 {
1178 uint32_t flags;
1179 pte_t *pte;
1180
1181 KASSERT(((va >= VM_MIN_KERNEL_ADDRESS) &&
1182 (va <= VM_MAX_KERNEL_ADDRESS)), ("mmu_booke_kenter: invalid va"));
1183
1184 flags = PTE_SR | PTE_SW | PTE_SX | PTE_WIRED | PTE_VALID;
1185 flags |= tlb_calc_wimg(pa, ma) << PTE_MAS2_SHIFT;
1186 flags |= PTE_PS_4KB;
1187
1188 pte = pte_find(kernel_pmap, va);
1189 KASSERT((pte != NULL), ("mmu_booke_kenter: invalid va. NULL PTE"));
1190
1191 mtx_lock_spin(&tlbivax_mutex);
1192 tlb_miss_lock();
1193
1194 if (PTE_ISVALID(pte)) {
1195 CTR1(KTR_PMAP, "%s: replacing entry!", __func__);
1196
1197 /* Flush entry from TLB0 */
1198 tlb0_flush_entry(va);
1199 }
1200
1201 *pte = PTE_RPN_FROM_PA(pa) | flags;
1202
1203 //debugf("mmu_booke_kenter: pdir_idx = %d ptbl_idx = %d va=0x%08x "
1204 // "pa=0x%08x rpn=0x%08x flags=0x%08x\n",
1205 // pdir_idx, ptbl_idx, va, pa, pte->rpn, pte->flags);
1206
1207 /* Flush the real memory from the instruction cache. */
1208 if ((flags & (PTE_I | PTE_G)) == 0)
1209 __syncicache((void *)va, PAGE_SIZE);
1210
1211 tlb_miss_unlock();
1212 mtx_unlock_spin(&tlbivax_mutex);
1213 }
1214
1215 /*
1216 * Remove a page from kernel page table.
1217 */
1218 static void
mmu_booke_kremove(vm_offset_t va)1219 mmu_booke_kremove(vm_offset_t va)
1220 {
1221 pte_t *pte;
1222
1223 CTR2(KTR_PMAP,"%s: s (va = 0x%"PRI0ptrX")\n", __func__, va);
1224
1225 KASSERT(((va >= VM_MIN_KERNEL_ADDRESS) &&
1226 (va <= VM_MAX_KERNEL_ADDRESS)),
1227 ("mmu_booke_kremove: invalid va"));
1228
1229 pte = pte_find(kernel_pmap, va);
1230
1231 if (pte == NULL || !PTE_ISVALID(pte)) {
1232 CTR1(KTR_PMAP, "%s: invalid pte", __func__);
1233
1234 return;
1235 }
1236
1237 mtx_lock_spin(&tlbivax_mutex);
1238 tlb_miss_lock();
1239
1240 /* Invalidate entry in TLB0, update PTE. */
1241 tlb0_flush_entry(va);
1242 *pte = 0;
1243
1244 tlb_miss_unlock();
1245 mtx_unlock_spin(&tlbivax_mutex);
1246 }
1247
1248 /*
1249 * Figure out where a given kernel pointer (usually in a fault) points
1250 * to from the VM's perspective, potentially remapping into userland's
1251 * address space.
1252 */
1253 static int
mmu_booke_decode_kernel_ptr(vm_offset_t addr,int * is_user,vm_offset_t * decoded_addr)1254 mmu_booke_decode_kernel_ptr(vm_offset_t addr, int *is_user,
1255 vm_offset_t *decoded_addr)
1256 {
1257
1258 if (trunc_page(addr) <= VM_MAXUSER_ADDRESS)
1259 *is_user = 1;
1260 else
1261 *is_user = 0;
1262
1263 *decoded_addr = addr;
1264 return (0);
1265 }
1266
1267 static bool
mmu_booke_page_is_mapped(vm_page_t m)1268 mmu_booke_page_is_mapped(vm_page_t m)
1269 {
1270
1271 return (!TAILQ_EMPTY(&(m)->md.pv_list));
1272 }
1273
1274 static bool
mmu_booke_ps_enabled(pmap_t pmap __unused)1275 mmu_booke_ps_enabled(pmap_t pmap __unused)
1276 {
1277 return (false);
1278 }
1279
1280 /*
1281 * Initialize pmap associated with process 0.
1282 */
1283 static void
mmu_booke_pinit0(pmap_t pmap)1284 mmu_booke_pinit0(pmap_t pmap)
1285 {
1286
1287 PMAP_LOCK_INIT(pmap);
1288 mmu_booke_pinit(pmap);
1289 PCPU_SET(curpmap, pmap);
1290 }
1291
1292 /*
1293 * Insert the given physical page at the specified virtual address in the
1294 * target physical map with the protection requested. If specified the page
1295 * will be wired down.
1296 */
1297 static int
mmu_booke_enter(pmap_t pmap,vm_offset_t va,vm_page_t m,vm_prot_t prot,u_int flags,int8_t psind)1298 mmu_booke_enter(pmap_t pmap, vm_offset_t va, vm_page_t m,
1299 vm_prot_t prot, u_int flags, int8_t psind)
1300 {
1301 int error;
1302
1303 rw_wlock(&pvh_global_lock);
1304 PMAP_LOCK(pmap);
1305 error = mmu_booke_enter_locked(pmap, va, m, prot, flags, psind);
1306 PMAP_UNLOCK(pmap);
1307 rw_wunlock(&pvh_global_lock);
1308 return (error);
1309 }
1310
1311 static int
mmu_booke_enter_locked(pmap_t pmap,vm_offset_t va,vm_page_t m,vm_prot_t prot,u_int pmap_flags,int8_t psind __unused)1312 mmu_booke_enter_locked(pmap_t pmap, vm_offset_t va, vm_page_t m,
1313 vm_prot_t prot, u_int pmap_flags, int8_t psind __unused)
1314 {
1315 pte_t *pte;
1316 vm_paddr_t pa;
1317 pte_t flags;
1318 int error, su, sync;
1319
1320 pa = VM_PAGE_TO_PHYS(m);
1321 su = (pmap == kernel_pmap);
1322 sync = 0;
1323
1324 //debugf("mmu_booke_enter_locked: s (pmap=0x%08x su=%d tid=%d m=0x%08x va=0x%08x "
1325 // "pa=0x%08x prot=0x%08x flags=%#x)\n",
1326 // (u_int32_t)pmap, su, pmap->pm_tid,
1327 // (u_int32_t)m, va, pa, prot, flags);
1328
1329 if (su) {
1330 KASSERT(((va >= virtual_avail) &&
1331 (va <= VM_MAX_KERNEL_ADDRESS)),
1332 ("mmu_booke_enter_locked: kernel pmap, non kernel va"));
1333 } else {
1334 KASSERT((va <= VM_MAXUSER_ADDRESS),
1335 ("mmu_booke_enter_locked: user pmap, non user va"));
1336 }
1337 if ((m->oflags & VPO_UNMANAGED) == 0) {
1338 if ((pmap_flags & PMAP_ENTER_QUICK_LOCKED) == 0)
1339 VM_PAGE_OBJECT_BUSY_ASSERT(m);
1340 else
1341 VM_OBJECT_ASSERT_LOCKED(m->object);
1342 }
1343
1344 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1345
1346 /*
1347 * If there is an existing mapping, and the physical address has not
1348 * changed, must be protection or wiring change.
1349 */
1350 if (((pte = pte_find(pmap, va)) != NULL) &&
1351 (PTE_ISVALID(pte)) && (PTE_PA(pte) == pa)) {
1352
1353 /*
1354 * Before actually updating pte->flags we calculate and
1355 * prepare its new value in a helper var.
1356 */
1357 flags = *pte;
1358 flags &= ~(PTE_UW | PTE_UX | PTE_SW | PTE_SX | PTE_MODIFIED);
1359
1360 /* Wiring change, just update stats. */
1361 if ((pmap_flags & PMAP_ENTER_WIRED) != 0) {
1362 if (!PTE_ISWIRED(pte)) {
1363 flags |= PTE_WIRED;
1364 pmap->pm_stats.wired_count++;
1365 }
1366 } else {
1367 if (PTE_ISWIRED(pte)) {
1368 flags &= ~PTE_WIRED;
1369 pmap->pm_stats.wired_count--;
1370 }
1371 }
1372
1373 if (prot & VM_PROT_WRITE) {
1374 /* Add write permissions. */
1375 flags |= PTE_SW;
1376 if (!su)
1377 flags |= PTE_UW;
1378
1379 if ((flags & PTE_MANAGED) != 0)
1380 vm_page_aflag_set(m, PGA_WRITEABLE);
1381 } else {
1382 /* Handle modified pages, sense modify status. */
1383
1384 /*
1385 * The PTE_MODIFIED flag could be set by underlying
1386 * TLB misses since we last read it (above), possibly
1387 * other CPUs could update it so we check in the PTE
1388 * directly rather than rely on that saved local flags
1389 * copy.
1390 */
1391 if (PTE_ISMODIFIED(pte))
1392 vm_page_dirty(m);
1393 }
1394
1395 if (prot & VM_PROT_EXECUTE) {
1396 flags |= PTE_SX;
1397 if (!su)
1398 flags |= PTE_UX;
1399
1400 /*
1401 * Check existing flags for execute permissions: if we
1402 * are turning execute permissions on, icache should
1403 * be flushed.
1404 */
1405 if ((*pte & (PTE_UX | PTE_SX)) == 0)
1406 sync++;
1407 }
1408
1409 flags &= ~PTE_REFERENCED;
1410
1411 /*
1412 * The new flags value is all calculated -- only now actually
1413 * update the PTE.
1414 */
1415 mtx_lock_spin(&tlbivax_mutex);
1416 tlb_miss_lock();
1417
1418 tlb0_flush_entry(va);
1419 *pte &= ~PTE_FLAGS_MASK;
1420 *pte |= flags;
1421
1422 tlb_miss_unlock();
1423 mtx_unlock_spin(&tlbivax_mutex);
1424
1425 } else {
1426 /*
1427 * If there is an existing mapping, but it's for a different
1428 * physical address, pte_enter() will delete the old mapping.
1429 */
1430 //if ((pte != NULL) && PTE_ISVALID(pte))
1431 // debugf("mmu_booke_enter_locked: replace\n");
1432 //else
1433 // debugf("mmu_booke_enter_locked: new\n");
1434
1435 /* Now set up the flags and install the new mapping. */
1436 flags = (PTE_SR | PTE_VALID);
1437 flags |= PTE_M;
1438
1439 if (!su)
1440 flags |= PTE_UR;
1441
1442 if (prot & VM_PROT_WRITE) {
1443 flags |= PTE_SW;
1444 if (!su)
1445 flags |= PTE_UW;
1446
1447 if ((m->oflags & VPO_UNMANAGED) == 0)
1448 vm_page_aflag_set(m, PGA_WRITEABLE);
1449 }
1450
1451 if (prot & VM_PROT_EXECUTE) {
1452 flags |= PTE_SX;
1453 if (!su)
1454 flags |= PTE_UX;
1455 }
1456
1457 /* If its wired update stats. */
1458 if ((pmap_flags & PMAP_ENTER_WIRED) != 0)
1459 flags |= PTE_WIRED;
1460
1461 error = pte_enter(pmap, m, va, flags,
1462 (pmap_flags & PMAP_ENTER_NOSLEEP) != 0);
1463 if (error != 0)
1464 return (KERN_RESOURCE_SHORTAGE);
1465
1466 if ((flags & PMAP_ENTER_WIRED) != 0)
1467 pmap->pm_stats.wired_count++;
1468
1469 /* Flush the real memory from the instruction cache. */
1470 if (prot & VM_PROT_EXECUTE)
1471 sync++;
1472 }
1473
1474 if (sync && (su || pmap == PCPU_GET(curpmap))) {
1475 __syncicache((void *)va, PAGE_SIZE);
1476 sync = 0;
1477 }
1478
1479 return (KERN_SUCCESS);
1480 }
1481
1482 /*
1483 * Maps a sequence of resident pages belonging to the same object.
1484 * The sequence begins with the given page m_start. This page is
1485 * mapped at the given virtual address start. Each subsequent page is
1486 * mapped at a virtual address that is offset from start by the same
1487 * amount as the page is offset from m_start within the object. The
1488 * last page in the sequence is the page with the largest offset from
1489 * m_start that can be mapped at a virtual address less than the given
1490 * virtual address end. Not every virtual page between start and end
1491 * is mapped; only those for which a resident page exists with the
1492 * corresponding offset from m_start are mapped.
1493 */
1494 static void
mmu_booke_enter_object(pmap_t pmap,vm_offset_t start,vm_offset_t end,vm_page_t m_start,vm_prot_t prot)1495 mmu_booke_enter_object(pmap_t pmap, vm_offset_t start,
1496 vm_offset_t end, vm_page_t m_start, vm_prot_t prot)
1497 {
1498 struct pctrie_iter pages;
1499 vm_offset_t va;
1500 vm_page_t m;
1501
1502 VM_OBJECT_ASSERT_LOCKED(m_start->object);
1503
1504 vm_page_iter_limit_init(&pages, m_start->object,
1505 m_start->pindex + atop(end - start));
1506 m = vm_radix_iter_lookup(&pages, m_start->pindex);
1507 rw_wlock(&pvh_global_lock);
1508 PMAP_LOCK(pmap);
1509 while (m != NULL) {
1510 va = start + ptoa(m->pindex - m_start->pindex);
1511 mmu_booke_enter_locked(pmap, va, m,
1512 prot & (VM_PROT_READ | VM_PROT_EXECUTE),
1513 PMAP_ENTER_NOSLEEP | PMAP_ENTER_QUICK_LOCKED, 0);
1514 m = vm_radix_iter_step(&pages);
1515 }
1516 PMAP_UNLOCK(pmap);
1517 rw_wunlock(&pvh_global_lock);
1518 }
1519
1520 static void
mmu_booke_enter_quick(pmap_t pmap,vm_offset_t va,vm_page_t m,vm_prot_t prot)1521 mmu_booke_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m,
1522 vm_prot_t prot)
1523 {
1524
1525 rw_wlock(&pvh_global_lock);
1526 PMAP_LOCK(pmap);
1527 mmu_booke_enter_locked(pmap, va, m,
1528 prot & (VM_PROT_READ | VM_PROT_EXECUTE), PMAP_ENTER_NOSLEEP |
1529 PMAP_ENTER_QUICK_LOCKED, 0);
1530 PMAP_UNLOCK(pmap);
1531 rw_wunlock(&pvh_global_lock);
1532 }
1533
1534 /*
1535 * Remove the given range of addresses from the specified map.
1536 *
1537 * It is assumed that the start and end are properly rounded to the page size.
1538 */
1539 static void
mmu_booke_remove(pmap_t pmap,vm_offset_t va,vm_offset_t endva)1540 mmu_booke_remove(pmap_t pmap, vm_offset_t va, vm_offset_t endva)
1541 {
1542 pte_t *pte;
1543 uint8_t hold_flag;
1544
1545 int su = (pmap == kernel_pmap);
1546
1547 //debugf("mmu_booke_remove: s (su = %d pmap=0x%08x tid=%d va=0x%08x endva=0x%08x)\n",
1548 // su, (u_int32_t)pmap, pmap->pm_tid, va, endva);
1549
1550 if (su) {
1551 KASSERT(((va >= virtual_avail) &&
1552 (va <= VM_MAX_KERNEL_ADDRESS)),
1553 ("mmu_booke_remove: kernel pmap, non kernel va"));
1554 } else {
1555 KASSERT((va <= VM_MAXUSER_ADDRESS),
1556 ("mmu_booke_remove: user pmap, non user va"));
1557 }
1558
1559 if (PMAP_REMOVE_DONE(pmap)) {
1560 //debugf("mmu_booke_remove: e (empty)\n");
1561 return;
1562 }
1563
1564 hold_flag = PTBL_HOLD_FLAG(pmap);
1565 //debugf("mmu_booke_remove: hold_flag = %d\n", hold_flag);
1566
1567 rw_wlock(&pvh_global_lock);
1568 PMAP_LOCK(pmap);
1569 for (; va < endva; va += PAGE_SIZE) {
1570 pte = pte_find_next(pmap, &va);
1571 if ((pte == NULL) || !PTE_ISVALID(pte))
1572 break;
1573 if (va >= endva)
1574 break;
1575 pte_remove(pmap, va, hold_flag);
1576 }
1577 PMAP_UNLOCK(pmap);
1578 rw_wunlock(&pvh_global_lock);
1579
1580 //debugf("mmu_booke_remove: e\n");
1581 }
1582
1583 /*
1584 * Remove physical page from all pmaps in which it resides.
1585 */
1586 static void
mmu_booke_remove_all(vm_page_t m)1587 mmu_booke_remove_all(vm_page_t m)
1588 {
1589 pv_entry_t pv, pvn;
1590 uint8_t hold_flag;
1591
1592 rw_wlock(&pvh_global_lock);
1593 TAILQ_FOREACH_SAFE(pv, &m->md.pv_list, pv_link, pvn) {
1594 PMAP_LOCK(pv->pv_pmap);
1595 hold_flag = PTBL_HOLD_FLAG(pv->pv_pmap);
1596 pte_remove(pv->pv_pmap, pv->pv_va, hold_flag);
1597 PMAP_UNLOCK(pv->pv_pmap);
1598 }
1599 vm_page_aflag_clear(m, PGA_WRITEABLE);
1600 rw_wunlock(&pvh_global_lock);
1601 }
1602
1603 /*
1604 * Map a range of physical addresses into kernel virtual address space.
1605 */
1606 static void *
mmu_booke_map(vm_offset_t * virt,vm_paddr_t pa_start,vm_paddr_t pa_end,int prot)1607 mmu_booke_map(vm_offset_t *virt, vm_paddr_t pa_start,
1608 vm_paddr_t pa_end, int prot)
1609 {
1610 vm_offset_t sva = *virt;
1611 vm_offset_t va = sva;
1612
1613 #ifdef __powerpc64__
1614 /* XXX: Handle memory not starting at 0x0. */
1615 if (pa_end < ctob(Maxmem))
1616 return (PHYS_TO_DMAP(pa_start));
1617 #endif
1618
1619 while (pa_start < pa_end) {
1620 mmu_booke_kenter(va, pa_start);
1621 va += PAGE_SIZE;
1622 pa_start += PAGE_SIZE;
1623 }
1624 *virt = va;
1625
1626 return ((void *)sva);
1627 }
1628
1629 /*
1630 * The pmap must be activated before it's address space can be accessed in any
1631 * way.
1632 */
1633 static void
mmu_booke_activate(struct thread * td)1634 mmu_booke_activate(struct thread *td)
1635 {
1636 pmap_t pmap;
1637 u_int cpuid;
1638
1639 pmap = &td->td_proc->p_vmspace->vm_pmap;
1640
1641 CTR5(KTR_PMAP, "%s: s (td = %p, proc = '%s', id = %d, pmap = 0x%"PRI0ptrX")",
1642 __func__, td, td->td_proc->p_comm, td->td_proc->p_pid, pmap);
1643
1644 KASSERT((pmap != kernel_pmap), ("mmu_booke_activate: kernel_pmap!"));
1645
1646 sched_pin();
1647
1648 cpuid = PCPU_GET(cpuid);
1649 CPU_SET_ATOMIC(cpuid, &pmap->pm_active);
1650 PCPU_SET(curpmap, pmap);
1651
1652 if (pmap->pm_tid[cpuid] == TID_NONE)
1653 tid_alloc(pmap);
1654
1655 /* Load PID0 register with pmap tid value. */
1656 mtspr(SPR_PID0, pmap->pm_tid[cpuid]);
1657 __asm __volatile("isync");
1658
1659 mtspr(SPR_DBCR0, td->td_pcb->pcb_cpu.booke.dbcr0);
1660
1661 sched_unpin();
1662
1663 CTR3(KTR_PMAP, "%s: e (tid = %d for '%s')", __func__,
1664 pmap->pm_tid[PCPU_GET(cpuid)], td->td_proc->p_comm);
1665 }
1666
1667 /*
1668 * Deactivate the specified process's address space.
1669 */
1670 static void
mmu_booke_deactivate(struct thread * td)1671 mmu_booke_deactivate(struct thread *td)
1672 {
1673 pmap_t pmap;
1674
1675 pmap = &td->td_proc->p_vmspace->vm_pmap;
1676
1677 CTR5(KTR_PMAP, "%s: td=%p, proc = '%s', id = %d, pmap = 0x%"PRI0ptrX,
1678 __func__, td, td->td_proc->p_comm, td->td_proc->p_pid, pmap);
1679
1680 td->td_pcb->pcb_cpu.booke.dbcr0 = mfspr(SPR_DBCR0);
1681
1682 CPU_CLR_ATOMIC(PCPU_GET(cpuid), &pmap->pm_active);
1683 PCPU_SET(curpmap, NULL);
1684 }
1685
1686 /*
1687 * Copy the range specified by src_addr/len
1688 * from the source map to the range dst_addr/len
1689 * in the destination map.
1690 *
1691 * This routine is only advisory and need not do anything.
1692 */
1693 static void
mmu_booke_copy(pmap_t dst_pmap,pmap_t src_pmap,vm_offset_t dst_addr,vm_size_t len,vm_offset_t src_addr)1694 mmu_booke_copy(pmap_t dst_pmap, pmap_t src_pmap,
1695 vm_offset_t dst_addr, vm_size_t len, vm_offset_t src_addr)
1696 {
1697
1698 }
1699
1700 /*
1701 * Set the physical protection on the specified range of this map as requested.
1702 */
1703 static void
mmu_booke_protect(pmap_t pmap,vm_offset_t sva,vm_offset_t eva,vm_prot_t prot)1704 mmu_booke_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
1705 vm_prot_t prot)
1706 {
1707 vm_offset_t va;
1708 vm_page_t m;
1709 pte_t *pte;
1710
1711 if ((prot & VM_PROT_READ) == VM_PROT_NONE) {
1712 mmu_booke_remove(pmap, sva, eva);
1713 return;
1714 }
1715
1716 if (prot & VM_PROT_WRITE)
1717 return;
1718
1719 PMAP_LOCK(pmap);
1720 for (va = sva; va < eva; va += PAGE_SIZE) {
1721 if ((pte = pte_find(pmap, va)) != NULL) {
1722 if (PTE_ISVALID(pte)) {
1723 m = PHYS_TO_VM_PAGE(PTE_PA(pte));
1724
1725 mtx_lock_spin(&tlbivax_mutex);
1726 tlb_miss_lock();
1727
1728 /* Handle modified pages. */
1729 if (PTE_ISMODIFIED(pte) && PTE_ISMANAGED(pte))
1730 vm_page_dirty(m);
1731
1732 tlb0_flush_entry(va);
1733 *pte &= ~(PTE_UW | PTE_SW | PTE_MODIFIED);
1734
1735 tlb_miss_unlock();
1736 mtx_unlock_spin(&tlbivax_mutex);
1737 }
1738 }
1739 }
1740 PMAP_UNLOCK(pmap);
1741 }
1742
1743 /*
1744 * Clear the write and modified bits in each of the given page's mappings.
1745 */
1746 static void
mmu_booke_remove_write(vm_page_t m)1747 mmu_booke_remove_write(vm_page_t m)
1748 {
1749 pv_entry_t pv;
1750 pte_t *pte;
1751
1752 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1753 ("mmu_booke_remove_write: page %p is not managed", m));
1754 vm_page_assert_busied(m);
1755
1756 if (!pmap_page_is_write_mapped(m))
1757 return;
1758 rw_wlock(&pvh_global_lock);
1759 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) {
1760 PMAP_LOCK(pv->pv_pmap);
1761 if ((pte = pte_find(pv->pv_pmap, pv->pv_va)) != NULL) {
1762 if (PTE_ISVALID(pte)) {
1763 m = PHYS_TO_VM_PAGE(PTE_PA(pte));
1764
1765 mtx_lock_spin(&tlbivax_mutex);
1766 tlb_miss_lock();
1767
1768 /* Handle modified pages. */
1769 if (PTE_ISMODIFIED(pte))
1770 vm_page_dirty(m);
1771
1772 /* Flush mapping from TLB0. */
1773 *pte &= ~(PTE_UW | PTE_SW | PTE_MODIFIED);
1774
1775 tlb_miss_unlock();
1776 mtx_unlock_spin(&tlbivax_mutex);
1777 }
1778 }
1779 PMAP_UNLOCK(pv->pv_pmap);
1780 }
1781 vm_page_aflag_clear(m, PGA_WRITEABLE);
1782 rw_wunlock(&pvh_global_lock);
1783 }
1784
1785 /*
1786 * Atomically extract and hold the physical page with the given
1787 * pmap and virtual address pair if that mapping permits the given
1788 * protection.
1789 */
1790 static vm_page_t
mmu_booke_extract_and_hold(pmap_t pmap,vm_offset_t va,vm_prot_t prot)1791 mmu_booke_extract_and_hold(pmap_t pmap, vm_offset_t va,
1792 vm_prot_t prot)
1793 {
1794 pte_t *pte;
1795 vm_page_t m;
1796 uint32_t pte_wbit;
1797
1798 m = NULL;
1799 PMAP_LOCK(pmap);
1800 pte = pte_find(pmap, va);
1801 if ((pte != NULL) && PTE_ISVALID(pte)) {
1802 if (pmap == kernel_pmap)
1803 pte_wbit = PTE_SW;
1804 else
1805 pte_wbit = PTE_UW;
1806
1807 if ((*pte & pte_wbit) != 0 || (prot & VM_PROT_WRITE) == 0) {
1808 m = PHYS_TO_VM_PAGE(PTE_PA(pte));
1809 if (!vm_page_wire_mapped(m))
1810 m = NULL;
1811 }
1812 }
1813 PMAP_UNLOCK(pmap);
1814 return (m);
1815 }
1816
1817 /*
1818 * Initialize a vm_page's machine-dependent fields.
1819 */
1820 static void
mmu_booke_page_init(vm_page_t m)1821 mmu_booke_page_init(vm_page_t m)
1822 {
1823
1824 m->md.pv_tracked = 0;
1825 TAILQ_INIT(&m->md.pv_list);
1826 }
1827
1828 /*
1829 * Return whether or not the specified physical page was modified
1830 * in any of physical maps.
1831 */
1832 static bool
mmu_booke_is_modified(vm_page_t m)1833 mmu_booke_is_modified(vm_page_t m)
1834 {
1835 pte_t *pte;
1836 pv_entry_t pv;
1837 bool rv;
1838
1839 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1840 ("mmu_booke_is_modified: page %p is not managed", m));
1841 rv = false;
1842
1843 /*
1844 * If the page is not busied then this check is racy.
1845 */
1846 if (!pmap_page_is_write_mapped(m))
1847 return (false);
1848
1849 rw_wlock(&pvh_global_lock);
1850 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) {
1851 PMAP_LOCK(pv->pv_pmap);
1852 if ((pte = pte_find(pv->pv_pmap, pv->pv_va)) != NULL &&
1853 PTE_ISVALID(pte)) {
1854 if (PTE_ISMODIFIED(pte))
1855 rv = true;
1856 }
1857 PMAP_UNLOCK(pv->pv_pmap);
1858 if (rv)
1859 break;
1860 }
1861 rw_wunlock(&pvh_global_lock);
1862 return (rv);
1863 }
1864
1865 /*
1866 * Return whether or not the specified virtual address is eligible
1867 * for prefault.
1868 */
1869 static bool
mmu_booke_is_prefaultable(pmap_t pmap,vm_offset_t addr)1870 mmu_booke_is_prefaultable(pmap_t pmap, vm_offset_t addr)
1871 {
1872
1873 return (false);
1874 }
1875
1876 /*
1877 * Return whether or not the specified physical page was referenced
1878 * in any physical maps.
1879 */
1880 static bool
mmu_booke_is_referenced(vm_page_t m)1881 mmu_booke_is_referenced(vm_page_t m)
1882 {
1883 pte_t *pte;
1884 pv_entry_t pv;
1885 bool rv;
1886
1887 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1888 ("mmu_booke_is_referenced: page %p is not managed", m));
1889 rv = false;
1890 rw_wlock(&pvh_global_lock);
1891 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) {
1892 PMAP_LOCK(pv->pv_pmap);
1893 if ((pte = pte_find(pv->pv_pmap, pv->pv_va)) != NULL &&
1894 PTE_ISVALID(pte)) {
1895 if (PTE_ISREFERENCED(pte))
1896 rv = true;
1897 }
1898 PMAP_UNLOCK(pv->pv_pmap);
1899 if (rv)
1900 break;
1901 }
1902 rw_wunlock(&pvh_global_lock);
1903 return (rv);
1904 }
1905
1906 /*
1907 * Clear the modify bits on the specified physical page.
1908 */
1909 static void
mmu_booke_clear_modify(vm_page_t m)1910 mmu_booke_clear_modify(vm_page_t m)
1911 {
1912 pte_t *pte;
1913 pv_entry_t pv;
1914
1915 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1916 ("mmu_booke_clear_modify: page %p is not managed", m));
1917 vm_page_assert_busied(m);
1918
1919 if (!pmap_page_is_write_mapped(m))
1920 return;
1921
1922 rw_wlock(&pvh_global_lock);
1923 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) {
1924 PMAP_LOCK(pv->pv_pmap);
1925 if ((pte = pte_find(pv->pv_pmap, pv->pv_va)) != NULL &&
1926 PTE_ISVALID(pte)) {
1927 mtx_lock_spin(&tlbivax_mutex);
1928 tlb_miss_lock();
1929
1930 if (*pte & (PTE_SW | PTE_UW | PTE_MODIFIED)) {
1931 tlb0_flush_entry(pv->pv_va);
1932 *pte &= ~(PTE_SW | PTE_UW | PTE_MODIFIED |
1933 PTE_REFERENCED);
1934 }
1935
1936 tlb_miss_unlock();
1937 mtx_unlock_spin(&tlbivax_mutex);
1938 }
1939 PMAP_UNLOCK(pv->pv_pmap);
1940 }
1941 rw_wunlock(&pvh_global_lock);
1942 }
1943
1944 /*
1945 * Return a count of reference bits for a page, clearing those bits.
1946 * It is not necessary for every reference bit to be cleared, but it
1947 * is necessary that 0 only be returned when there are truly no
1948 * reference bits set.
1949 *
1950 * As an optimization, update the page's dirty field if a modified bit is
1951 * found while counting reference bits. This opportunistic update can be
1952 * performed at low cost and can eliminate the need for some future calls
1953 * to pmap_is_modified(). However, since this function stops after
1954 * finding PMAP_TS_REFERENCED_MAX reference bits, it may not detect some
1955 * dirty pages. Those dirty pages will only be detected by a future call
1956 * to pmap_is_modified().
1957 */
1958 static int
mmu_booke_ts_referenced(vm_page_t m)1959 mmu_booke_ts_referenced(vm_page_t m)
1960 {
1961 pte_t *pte;
1962 pv_entry_t pv;
1963 int count;
1964
1965 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1966 ("mmu_booke_ts_referenced: page %p is not managed", m));
1967 count = 0;
1968 rw_wlock(&pvh_global_lock);
1969 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) {
1970 PMAP_LOCK(pv->pv_pmap);
1971 if ((pte = pte_find(pv->pv_pmap, pv->pv_va)) != NULL &&
1972 PTE_ISVALID(pte)) {
1973 if (PTE_ISMODIFIED(pte))
1974 vm_page_dirty(m);
1975 if (PTE_ISREFERENCED(pte)) {
1976 mtx_lock_spin(&tlbivax_mutex);
1977 tlb_miss_lock();
1978
1979 tlb0_flush_entry(pv->pv_va);
1980 *pte &= ~PTE_REFERENCED;
1981
1982 tlb_miss_unlock();
1983 mtx_unlock_spin(&tlbivax_mutex);
1984
1985 if (++count >= PMAP_TS_REFERENCED_MAX) {
1986 PMAP_UNLOCK(pv->pv_pmap);
1987 break;
1988 }
1989 }
1990 }
1991 PMAP_UNLOCK(pv->pv_pmap);
1992 }
1993 rw_wunlock(&pvh_global_lock);
1994 return (count);
1995 }
1996
1997 /*
1998 * Clear the wired attribute from the mappings for the specified range of
1999 * addresses in the given pmap. Every valid mapping within that range must
2000 * have the wired attribute set. In contrast, invalid mappings cannot have
2001 * the wired attribute set, so they are ignored.
2002 *
2003 * The wired attribute of the page table entry is not a hardware feature, so
2004 * there is no need to invalidate any TLB entries.
2005 */
2006 static void
mmu_booke_unwire(pmap_t pmap,vm_offset_t sva,vm_offset_t eva)2007 mmu_booke_unwire(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
2008 {
2009 vm_offset_t va;
2010 pte_t *pte;
2011
2012 PMAP_LOCK(pmap);
2013 for (va = sva; va < eva; va += PAGE_SIZE) {
2014 if ((pte = pte_find(pmap, va)) != NULL &&
2015 PTE_ISVALID(pte)) {
2016 if (!PTE_ISWIRED(pte))
2017 panic("mmu_booke_unwire: pte %p isn't wired",
2018 pte);
2019 *pte &= ~PTE_WIRED;
2020 pmap->pm_stats.wired_count--;
2021 }
2022 }
2023 PMAP_UNLOCK(pmap);
2024
2025 }
2026
2027 /*
2028 * Return true if the pmap's pv is one of the first 16 pvs linked to from this
2029 * page. This count may be changed upwards or downwards in the future; it is
2030 * only necessary that true be returned for a small subset of pmaps for proper
2031 * page aging.
2032 */
2033 static bool
mmu_booke_page_exists_quick(pmap_t pmap,vm_page_t m)2034 mmu_booke_page_exists_quick(pmap_t pmap, vm_page_t m)
2035 {
2036 pv_entry_t pv;
2037 int loops;
2038 bool rv;
2039
2040 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2041 ("mmu_booke_page_exists_quick: page %p is not managed", m));
2042 loops = 0;
2043 rv = false;
2044 rw_wlock(&pvh_global_lock);
2045 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) {
2046 if (pv->pv_pmap == pmap) {
2047 rv = true;
2048 break;
2049 }
2050 if (++loops >= 16)
2051 break;
2052 }
2053 rw_wunlock(&pvh_global_lock);
2054 return (rv);
2055 }
2056
2057 /*
2058 * Return the number of managed mappings to the given physical page that are
2059 * wired.
2060 */
2061 static int
mmu_booke_page_wired_mappings(vm_page_t m)2062 mmu_booke_page_wired_mappings(vm_page_t m)
2063 {
2064 pv_entry_t pv;
2065 pte_t *pte;
2066 int count = 0;
2067
2068 if ((m->oflags & VPO_UNMANAGED) != 0)
2069 return (count);
2070 rw_wlock(&pvh_global_lock);
2071 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) {
2072 PMAP_LOCK(pv->pv_pmap);
2073 if ((pte = pte_find(pv->pv_pmap, pv->pv_va)) != NULL)
2074 if (PTE_ISVALID(pte) && PTE_ISWIRED(pte))
2075 count++;
2076 PMAP_UNLOCK(pv->pv_pmap);
2077 }
2078 rw_wunlock(&pvh_global_lock);
2079 return (count);
2080 }
2081
2082 static int
mmu_booke_dev_direct_mapped(vm_paddr_t pa,vm_size_t size)2083 mmu_booke_dev_direct_mapped(vm_paddr_t pa, vm_size_t size)
2084 {
2085 int i;
2086 vm_offset_t va;
2087
2088 /*
2089 * This currently does not work for entries that
2090 * overlap TLB1 entries.
2091 */
2092 for (i = 0; i < TLB1_ENTRIES; i ++) {
2093 if (tlb1_iomapped(i, pa, size, &va) == 0)
2094 return (0);
2095 }
2096
2097 return (EFAULT);
2098 }
2099
2100 void
mmu_booke_dumpsys_map(vm_paddr_t pa,size_t sz,void ** va)2101 mmu_booke_dumpsys_map(vm_paddr_t pa, size_t sz, void **va)
2102 {
2103 vm_paddr_t ppa;
2104 vm_offset_t ofs;
2105 vm_size_t gran;
2106
2107 /* Minidumps are based on virtual memory addresses. */
2108 if (do_minidump) {
2109 *va = (void *)(vm_offset_t)pa;
2110 return;
2111 }
2112
2113 /* Raw physical memory dumps don't have a virtual address. */
2114 /* We always map a 256MB page at 256M. */
2115 gran = 256 * 1024 * 1024;
2116 ppa = rounddown2(pa, gran);
2117 ofs = pa - ppa;
2118 *va = (void *)gran;
2119 tlb1_set_entry((vm_offset_t)va, ppa, gran, _TLB_ENTRY_IO);
2120
2121 if (sz > (gran - ofs))
2122 tlb1_set_entry((vm_offset_t)(va + gran), ppa + gran, gran,
2123 _TLB_ENTRY_IO);
2124 }
2125
2126 void
mmu_booke_dumpsys_unmap(vm_paddr_t pa,size_t sz,void * va)2127 mmu_booke_dumpsys_unmap(vm_paddr_t pa, size_t sz, void *va)
2128 {
2129 vm_paddr_t ppa;
2130 vm_offset_t ofs;
2131 vm_size_t gran;
2132 tlb_entry_t e;
2133 int i;
2134
2135 /* Minidumps are based on virtual memory addresses. */
2136 /* Nothing to do... */
2137 if (do_minidump)
2138 return;
2139
2140 for (i = 0; i < TLB1_ENTRIES; i++) {
2141 tlb1_read_entry(&e, i);
2142 if (!(e.mas1 & MAS1_VALID))
2143 break;
2144 }
2145
2146 /* Raw physical memory dumps don't have a virtual address. */
2147 i--;
2148 e.mas1 = 0;
2149 e.mas2 = 0;
2150 e.mas3 = 0;
2151 tlb1_write_entry(&e, i);
2152
2153 gran = 256 * 1024 * 1024;
2154 ppa = rounddown2(pa, gran);
2155 ofs = pa - ppa;
2156 if (sz > (gran - ofs)) {
2157 i--;
2158 e.mas1 = 0;
2159 e.mas2 = 0;
2160 e.mas3 = 0;
2161 tlb1_write_entry(&e, i);
2162 }
2163 }
2164
2165 extern struct dump_pa dump_map[PHYS_AVAIL_SZ + 1];
2166
2167 void
mmu_booke_scan_init(void)2168 mmu_booke_scan_init(void)
2169 {
2170 vm_offset_t va;
2171 pte_t *pte;
2172 int i;
2173
2174 if (!do_minidump) {
2175 /* Initialize phys. segments for dumpsys(). */
2176 memset(&dump_map, 0, sizeof(dump_map));
2177 mem_regions(&physmem_regions, &physmem_regions_sz, &availmem_regions,
2178 &availmem_regions_sz);
2179 for (i = 0; i < physmem_regions_sz; i++) {
2180 dump_map[i].pa_start = physmem_regions[i].mr_start;
2181 dump_map[i].pa_size = physmem_regions[i].mr_size;
2182 }
2183 return;
2184 }
2185
2186 /* Virtual segments for minidumps: */
2187 memset(&dump_map, 0, sizeof(dump_map));
2188
2189 /* 1st: kernel .data and .bss. */
2190 dump_map[0].pa_start = trunc_page((uintptr_t)_etext);
2191 dump_map[0].pa_size =
2192 round_page((uintptr_t)_end) - dump_map[0].pa_start;
2193
2194 /* 2nd: msgbuf and tables (see pmap_bootstrap()). */
2195 dump_map[1].pa_start = data_start;
2196 dump_map[1].pa_size = data_end - data_start;
2197
2198 /* 3rd: kernel VM. */
2199 va = dump_map[1].pa_start + dump_map[1].pa_size;
2200 /* Find start of next chunk (from va). */
2201 while (va < virtual_end) {
2202 /* Don't dump the buffer cache. */
2203 if (va >= kmi.buffer_sva && va < kmi.buffer_eva) {
2204 va = kmi.buffer_eva;
2205 continue;
2206 }
2207 pte = pte_find(kernel_pmap, va);
2208 if (pte != NULL && PTE_ISVALID(pte))
2209 break;
2210 va += PAGE_SIZE;
2211 }
2212 if (va < virtual_end) {
2213 dump_map[2].pa_start = va;
2214 va += PAGE_SIZE;
2215 /* Find last page in chunk. */
2216 while (va < virtual_end) {
2217 /* Don't run into the buffer cache. */
2218 if (va == kmi.buffer_sva)
2219 break;
2220 pte = pte_find(kernel_pmap, va);
2221 if (pte == NULL || !PTE_ISVALID(pte))
2222 break;
2223 va += PAGE_SIZE;
2224 }
2225 dump_map[2].pa_size = va - dump_map[2].pa_start;
2226 }
2227 }
2228
2229 /*
2230 * Map a set of physical memory pages into the kernel virtual address space.
2231 * Return a pointer to where it is mapped. This routine is intended to be used
2232 * for mapping device memory, NOT real memory.
2233 */
2234 static void *
mmu_booke_mapdev(vm_paddr_t pa,vm_size_t size)2235 mmu_booke_mapdev(vm_paddr_t pa, vm_size_t size)
2236 {
2237
2238 return (mmu_booke_mapdev_attr(pa, size, VM_MEMATTR_DEFAULT));
2239 }
2240
2241 static int
tlb1_find_pa(vm_paddr_t pa,tlb_entry_t * e)2242 tlb1_find_pa(vm_paddr_t pa, tlb_entry_t *e)
2243 {
2244 int i;
2245
2246 for (i = 0; i < TLB1_ENTRIES; i++) {
2247 tlb1_read_entry(e, i);
2248 if ((e->mas1 & MAS1_VALID) == 0)
2249 continue;
2250 if (e->phys == pa)
2251 return (i);
2252 }
2253 return (-1);
2254 }
2255
2256 static void *
mmu_booke_mapdev_attr(vm_paddr_t pa,vm_size_t size,vm_memattr_t ma)2257 mmu_booke_mapdev_attr(vm_paddr_t pa, vm_size_t size, vm_memattr_t ma)
2258 {
2259 tlb_entry_t e;
2260 vm_paddr_t tmppa;
2261 #ifndef __powerpc64__
2262 uintptr_t tmpva;
2263 #endif
2264 uintptr_t va, retva;
2265 vm_size_t sz;
2266 int i;
2267 int wimge;
2268
2269 /*
2270 * Check if this is premapped in TLB1.
2271 */
2272 sz = size;
2273 tmppa = pa;
2274 va = ~0;
2275 wimge = tlb_calc_wimg(pa, ma);
2276 for (i = 0; i < TLB1_ENTRIES; i++) {
2277 tlb1_read_entry(&e, i);
2278 if (!(e.mas1 & MAS1_VALID))
2279 continue;
2280 if (wimge != (e.mas2 & (MAS2_WIMGE_MASK & ~_TLB_ENTRY_SHARED)))
2281 continue;
2282 if (tmppa >= e.phys && tmppa < e.phys + e.size) {
2283 va = e.virt + (pa - e.phys);
2284 tmppa = e.phys + e.size;
2285 sz -= MIN(sz, e.size - (pa - e.phys));
2286 while (sz > 0 && (i = tlb1_find_pa(tmppa, &e)) != -1) {
2287 if (wimge != (e.mas2 & (MAS2_WIMGE_MASK & ~_TLB_ENTRY_SHARED)))
2288 break;
2289 sz -= MIN(sz, e.size);
2290 tmppa = e.phys + e.size;
2291 }
2292 if (sz != 0)
2293 break;
2294 return ((void *)va);
2295 }
2296 }
2297
2298 size = roundup(size, PAGE_SIZE);
2299
2300 #ifdef __powerpc64__
2301 KASSERT(pa < VM_MAPDEV_PA_MAX,
2302 ("Unsupported physical address! %lx", pa));
2303 va = VM_MAPDEV_BASE + pa;
2304 retva = va;
2305 #ifdef POW2_MAPPINGS
2306 /*
2307 * Align the mapping to a power of 2 size, taking into account that we
2308 * may need to increase the size multiple times to satisfy the size and
2309 * alignment requirements.
2310 *
2311 * This works in the general case because it's very rare (near never?)
2312 * to have different access properties (WIMG) within a single
2313 * power-of-two region. If a design does call for that, POW2_MAPPINGS
2314 * can be undefined, and exact mappings will be used instead.
2315 */
2316 sz = size;
2317 size = roundup2(size, 1 << ilog2(size));
2318 while (rounddown2(va, size) + size < va + sz)
2319 size <<= 1;
2320 va = rounddown2(va, size);
2321 pa = rounddown2(pa, size);
2322 #endif
2323 #else
2324 /*
2325 * The device mapping area is between VM_MAXUSER_ADDRESS and
2326 * VM_MIN_KERNEL_ADDRESS. This gives 1GB of device addressing.
2327 */
2328 #ifdef SPARSE_MAPDEV
2329 /*
2330 * With a sparse mapdev, align to the largest starting region. This
2331 * could feasibly be optimized for a 'best-fit' alignment, but that
2332 * calculation could be very costly.
2333 * Align to the smaller of:
2334 * - first set bit in overlap of (pa & size mask)
2335 * - largest size envelope
2336 *
2337 * It's possible the device mapping may start at a PA that's not larger
2338 * than the size mask, so we need to offset in to maximize the TLB entry
2339 * range and minimize the number of used TLB entries.
2340 */
2341 do {
2342 tmpva = tlb1_map_base;
2343 sz = ffsl((~((1 << flsl(size-1)) - 1)) & pa);
2344 sz = sz ? min(roundup(sz + 3, 4), flsl(size) - 1) : flsl(size) - 1;
2345 va = roundup(tlb1_map_base, 1 << sz) | (((1 << sz) - 1) & pa);
2346 } while (!atomic_cmpset_int(&tlb1_map_base, tmpva, va + size));
2347 #endif
2348 va = atomic_fetchadd_int(&tlb1_map_base, size);
2349 retva = va;
2350 #endif
2351
2352 if (tlb1_mapin_region(va, pa, size, tlb_calc_wimg(pa, ma)) != size)
2353 return (NULL);
2354
2355 return ((void *)retva);
2356 }
2357
2358 /*
2359 * 'Unmap' a range mapped by mmu_booke_mapdev().
2360 */
2361 static void
mmu_booke_unmapdev(void * p,vm_size_t size)2362 mmu_booke_unmapdev(void *p, vm_size_t size)
2363 {
2364 #ifdef SUPPORTS_SHRINKING_TLB1
2365 void *base;
2366 vm_offset_t offset, va;
2367
2368 /*
2369 * Unmap only if this is inside kernel virtual space.
2370 */
2371 va = (vm_offset_t)p;
2372 if ((va >= VM_MIN_KERNEL_ADDRESS) && (va <= VM_MAX_KERNEL_ADDRESS)) {
2373 base = trunc_page(va);
2374 offset = va & PAGE_MASK;
2375 size = roundup(offset + size, PAGE_SIZE);
2376 mmu_booke_qremove(base, atop(size));
2377 kva_free((vm_offset_t)base, size);
2378 }
2379 #endif
2380 }
2381
2382 /*
2383 * mmu_booke_object_init_pt preloads the ptes for a given object into the
2384 * specified pmap. This eliminates the blast of soft faults on process startup
2385 * and immediately after an mmap.
2386 */
2387 static void
mmu_booke_object_init_pt(pmap_t pmap,vm_offset_t addr,vm_object_t object,vm_pindex_t pindex,vm_size_t size)2388 mmu_booke_object_init_pt(pmap_t pmap, vm_offset_t addr,
2389 vm_object_t object, vm_pindex_t pindex, vm_size_t size)
2390 {
2391
2392 VM_OBJECT_ASSERT_WLOCKED(object);
2393 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG,
2394 ("mmu_booke_object_init_pt: non-device object"));
2395 }
2396
2397 /*
2398 * Perform the pmap work for mincore.
2399 */
2400 static int
mmu_booke_mincore(pmap_t pmap,vm_offset_t addr,vm_paddr_t * pap)2401 mmu_booke_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *pap)
2402 {
2403
2404 /* XXX: this should be implemented at some point */
2405 return (0);
2406 }
2407
2408 static int
mmu_booke_change_attr(void * sva,vm_size_t sz,vm_memattr_t mode)2409 mmu_booke_change_attr(void *sva, vm_size_t sz, vm_memattr_t mode)
2410 {
2411 vm_offset_t addr, va;
2412 pte_t *pte;
2413 int i, j;
2414 tlb_entry_t e;
2415
2416 addr = (vm_offset_t)sva;
2417 addr = trunc_page(addr);
2418
2419 /* Only allow changes to mapped kernel addresses. This includes:
2420 * - KVA
2421 * - DMAP (powerpc64)
2422 * - Device mappings
2423 */
2424 if (addr <= VM_MAXUSER_ADDRESS ||
2425 #ifdef __powerpc64__
2426 (addr >= tlb1_map_base && addr < DMAP_BASE_ADDRESS) ||
2427 (addr > DMAP_MAX_ADDRESS && addr < VM_MIN_KERNEL_ADDRESS) ||
2428 #else
2429 (addr >= tlb1_map_base && addr < VM_MIN_KERNEL_ADDRESS) ||
2430 #endif
2431 (addr > VM_MAX_KERNEL_ADDRESS))
2432 return (EINVAL);
2433
2434 /* Check TLB1 mappings */
2435 for (i = 0; i < TLB1_ENTRIES; i++) {
2436 tlb1_read_entry(&e, i);
2437 if (!(e.mas1 & MAS1_VALID))
2438 continue;
2439 if (addr >= e.virt && addr < e.virt + e.size)
2440 break;
2441 }
2442 if (i < TLB1_ENTRIES) {
2443 /* Only allow full mappings to be modified for now. */
2444 /* Validate the range. */
2445 for (j = i, va = addr; va < addr + sz; va += e.size, j++) {
2446 tlb1_read_entry(&e, j);
2447 if (va != e.virt || (sz - (va - addr) < e.size))
2448 return (EINVAL);
2449 }
2450 for (va = addr; va < addr + sz; va += e.size, i++) {
2451 tlb1_read_entry(&e, i);
2452 e.mas2 &= ~MAS2_WIMGE_MASK;
2453 e.mas2 |= tlb_calc_wimg(e.phys, mode);
2454
2455 /*
2456 * Write it out to the TLB. Should really re-sync with other
2457 * cores.
2458 */
2459 tlb1_write_entry(&e, i);
2460 }
2461 return (0);
2462 }
2463
2464 /* Not in TLB1, try through pmap */
2465 /* First validate the range. */
2466 for (va = addr; va < addr + sz; va += PAGE_SIZE) {
2467 pte = pte_find(kernel_pmap, va);
2468 if (pte == NULL || !PTE_ISVALID(pte))
2469 return (EINVAL);
2470 }
2471
2472 mtx_lock_spin(&tlbivax_mutex);
2473 tlb_miss_lock();
2474 for (va = addr; va < addr + sz; va += PAGE_SIZE) {
2475 pte = pte_find(kernel_pmap, va);
2476 *pte &= ~(PTE_MAS2_MASK << PTE_MAS2_SHIFT);
2477 *pte |= tlb_calc_wimg(PTE_PA(pte), mode) << PTE_MAS2_SHIFT;
2478 tlb0_flush_entry(va);
2479 }
2480 tlb_miss_unlock();
2481 mtx_unlock_spin(&tlbivax_mutex);
2482
2483 return (0);
2484 }
2485
2486 static void
mmu_booke_page_array_startup(long pages)2487 mmu_booke_page_array_startup(long pages)
2488 {
2489 vm_page_array_size = pages;
2490 }
2491
2492 /**************************************************************************/
2493 /* TID handling */
2494 /**************************************************************************/
2495
2496 static __inline void
tid_set_busy(int cpu,int tid,pmap_t pmap)2497 tid_set_busy(int cpu, int tid, pmap_t pmap)
2498 {
2499 volatile pmap_t *pm = &tidbusy[cpu * (tid_max + 1) + tid];
2500
2501 if (pmap == NULL) {
2502 if (*pm != NULL)
2503 (*pm)->pm_tid[cpu] = TID_NONE;
2504 } else
2505 pmap->pm_tid[cpu] = tid;
2506 *pm = pmap;
2507 }
2508
2509 static __inline pmap_t
tid_get_busy(int cpu,int tid)2510 tid_get_busy(int cpu, int tid)
2511 {
2512 return (tidbusy[cpu * (tid_max + 1) + tid]);
2513 }
2514
2515 /*
2516 * Allocate a TID. If necessary, steal one from someone else.
2517 * The new TID is flushed from the TLB before returning.
2518 */
2519 static tlbtid_t
tid_alloc(pmap_t pmap)2520 tid_alloc(pmap_t pmap)
2521 {
2522 tlbtid_t tid;
2523 int thiscpu;
2524
2525 KASSERT((pmap != kernel_pmap), ("tid_alloc: kernel pmap"));
2526
2527 CTR2(KTR_PMAP, "%s: s (pmap = %p)", __func__, pmap);
2528
2529 thiscpu = PCPU_GET(cpuid);
2530
2531 tid = PCPU_GET(booke.tid_next);
2532 /* tid_max is always a power-of-2-minus-1, so check for overflow. */
2533 if ((tid & ~tid_max) != 0)
2534 tid = TID_MIN;
2535 PCPU_SET(booke.tid_next, tid + 1);
2536
2537 /* If we are stealing TID then clear the relevant pmap's field */
2538 if (tid_get_busy(thiscpu, tid) != NULL) {
2539 CTR2(KTR_PMAP, "%s: warning: stealing tid %d", __func__, tid);
2540
2541 tid_set_busy(thiscpu, tid, NULL);
2542
2543 /* Flush all entries from TLB0 matching this TID. */
2544 tid_flush(tid);
2545 }
2546
2547 tid_set_busy(thiscpu, tid, pmap);
2548 pmap->pm_tid[thiscpu] = tid;
2549 __asm __volatile("msync; isync");
2550
2551 CTR3(KTR_PMAP, "%s: e (%02d next = %02d)", __func__, tid,
2552 PCPU_GET(booke.tid_next));
2553
2554 return (tid);
2555 }
2556
2557 /**************************************************************************/
2558 /* TLB0 handling */
2559 /**************************************************************************/
2560
2561 /* Convert TLB0 va and way number to tlb0[] table index. */
2562 static inline unsigned int
tlb0_tableidx(vm_offset_t va,unsigned int way)2563 tlb0_tableidx(vm_offset_t va, unsigned int way)
2564 {
2565 unsigned int idx;
2566
2567 idx = (way * TLB0_ENTRIES_PER_WAY);
2568 idx += (va & MAS2_TLB0_ENTRY_IDX_MASK) >> MAS2_TLB0_ENTRY_IDX_SHIFT;
2569 return (idx);
2570 }
2571
2572 /*
2573 * Invalidate TLB0 entry.
2574 */
2575 static inline void
tlb0_flush_entry(vm_offset_t va)2576 tlb0_flush_entry(vm_offset_t va)
2577 {
2578
2579 CTR2(KTR_PMAP, "%s: s va=0x%08x", __func__, va);
2580
2581 mtx_assert(&tlbivax_mutex, MA_OWNED);
2582
2583 __asm __volatile("tlbivax 0, %0" :: "r"(va & MAS2_EPN_MASK));
2584 __asm __volatile("isync; msync");
2585 __asm __volatile("tlbsync; msync");
2586
2587 CTR1(KTR_PMAP, "%s: e", __func__);
2588 }
2589
2590 /**************************************************************************/
2591 /* TLB1 handling */
2592 /**************************************************************************/
2593
2594 /*
2595 * TLB1 mapping notes:
2596 *
2597 * TLB1[0] Kernel text and data.
2598 * TLB1[1-15] Additional kernel text and data mappings (if required), PCI
2599 * windows, other devices mappings.
2600 */
2601
2602 /*
2603 * Read an entry from given TLB1 slot.
2604 */
2605 void
tlb1_read_entry(tlb_entry_t * entry,unsigned int slot)2606 tlb1_read_entry(tlb_entry_t *entry, unsigned int slot)
2607 {
2608 register_t msr;
2609 uint32_t mas0;
2610
2611 KASSERT((entry != NULL), ("%s(): Entry is NULL!", __func__));
2612
2613 msr = mfmsr();
2614 __asm __volatile("wrteei 0");
2615
2616 mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(slot);
2617 mtspr(SPR_MAS0, mas0);
2618 __asm __volatile("isync; tlbre");
2619
2620 entry->mas1 = mfspr(SPR_MAS1);
2621 entry->mas2 = mfspr(SPR_MAS2);
2622 entry->mas3 = mfspr(SPR_MAS3);
2623
2624 switch ((mfpvr() >> 16) & 0xFFFF) {
2625 case FSL_E500v2:
2626 case FSL_E500mc:
2627 case FSL_E5500:
2628 case FSL_E6500:
2629 entry->mas7 = mfspr(SPR_MAS7);
2630 break;
2631 default:
2632 entry->mas7 = 0;
2633 break;
2634 }
2635 __asm __volatile("wrtee %0" :: "r"(msr));
2636
2637 entry->virt = entry->mas2 & MAS2_EPN_MASK;
2638 entry->phys = ((vm_paddr_t)(entry->mas7 & MAS7_RPN) << 32) |
2639 (entry->mas3 & MAS3_RPN);
2640 entry->size =
2641 tsize2size((entry->mas1 & MAS1_TSIZE_MASK) >> MAS1_TSIZE_SHIFT);
2642 }
2643
2644 struct tlbwrite_args {
2645 tlb_entry_t *e;
2646 unsigned int idx;
2647 };
2648
2649 static uint32_t
tlb1_find_free(void)2650 tlb1_find_free(void)
2651 {
2652 tlb_entry_t e;
2653 int i;
2654
2655 for (i = 0; i < TLB1_ENTRIES; i++) {
2656 tlb1_read_entry(&e, i);
2657 if ((e.mas1 & MAS1_VALID) == 0)
2658 return (i);
2659 }
2660 return (-1);
2661 }
2662
2663 static void
tlb1_purge_va_range(vm_offset_t va,vm_size_t size)2664 tlb1_purge_va_range(vm_offset_t va, vm_size_t size)
2665 {
2666 tlb_entry_t e;
2667 int i;
2668
2669 for (i = 0; i < TLB1_ENTRIES; i++) {
2670 tlb1_read_entry(&e, i);
2671 if ((e.mas1 & MAS1_VALID) == 0)
2672 continue;
2673 if ((e.mas2 & MAS2_EPN_MASK) >= va &&
2674 (e.mas2 & MAS2_EPN_MASK) < va + size) {
2675 mtspr(SPR_MAS1, e.mas1 & ~MAS1_VALID);
2676 __asm __volatile("isync; tlbwe; isync; msync");
2677 }
2678 }
2679 }
2680
2681 static void
tlb1_write_entry_int(void * arg)2682 tlb1_write_entry_int(void *arg)
2683 {
2684 struct tlbwrite_args *args = arg;
2685 uint32_t idx, mas0;
2686
2687 idx = args->idx;
2688 if (idx == -1) {
2689 tlb1_purge_va_range(args->e->virt, args->e->size);
2690 idx = tlb1_find_free();
2691 if (idx == -1)
2692 panic("No free TLB1 entries!\n");
2693 }
2694 /* Select entry */
2695 mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(idx);
2696
2697 mtspr(SPR_MAS0, mas0);
2698 mtspr(SPR_MAS1, args->e->mas1);
2699 mtspr(SPR_MAS2, args->e->mas2);
2700 mtspr(SPR_MAS3, args->e->mas3);
2701 switch ((mfpvr() >> 16) & 0xFFFF) {
2702 case FSL_E500mc:
2703 case FSL_E5500:
2704 case FSL_E6500:
2705 mtspr(SPR_MAS8, 0);
2706 /* FALLTHROUGH */
2707 case FSL_E500v2:
2708 mtspr(SPR_MAS7, args->e->mas7);
2709 break;
2710 default:
2711 break;
2712 }
2713
2714 __asm __volatile("isync; tlbwe; isync; msync");
2715
2716 }
2717
2718 static void
tlb1_write_entry_sync(void * arg)2719 tlb1_write_entry_sync(void *arg)
2720 {
2721 /* Empty synchronization point for smp_rendezvous(). */
2722 }
2723
2724 /*
2725 * Write given entry to TLB1 hardware.
2726 */
2727 static void
tlb1_write_entry(tlb_entry_t * e,unsigned int idx)2728 tlb1_write_entry(tlb_entry_t *e, unsigned int idx)
2729 {
2730 struct tlbwrite_args args;
2731
2732 args.e = e;
2733 args.idx = idx;
2734
2735 #ifdef SMP
2736 if ((e->mas2 & _TLB_ENTRY_SHARED) && smp_started) {
2737 mb();
2738 smp_rendezvous(tlb1_write_entry_sync,
2739 tlb1_write_entry_int,
2740 tlb1_write_entry_sync, &args);
2741 } else
2742 #endif
2743 {
2744 register_t msr;
2745
2746 msr = mfmsr();
2747 __asm __volatile("wrteei 0");
2748 tlb1_write_entry_int(&args);
2749 __asm __volatile("wrtee %0" :: "r"(msr));
2750 }
2751 }
2752
2753 /*
2754 * Convert TLB TSIZE value to mapped region size.
2755 */
2756 static vm_size_t
tsize2size(unsigned int tsize)2757 tsize2size(unsigned int tsize)
2758 {
2759
2760 /*
2761 * size = 4^tsize KB
2762 * size = 4^tsize * 2^10 = 2^(2 * tsize - 10)
2763 */
2764
2765 return ((1UL << tsize) * 1024);
2766 }
2767
2768 /*
2769 * Convert region size (must be power of 4) to TLB TSIZE value.
2770 */
2771 static unsigned int
size2tsize(vm_size_t size)2772 size2tsize(vm_size_t size)
2773 {
2774
2775 return (ilog2(size) - 10);
2776 }
2777
2778 /*
2779 * Register permanent kernel mapping in TLB1.
2780 *
2781 * Entries are created starting from index 0 (current free entry is
2782 * kept in tlb1_idx) and are not supposed to be invalidated.
2783 */
2784 int
tlb1_set_entry(vm_offset_t va,vm_paddr_t pa,vm_size_t size,uint32_t flags)2785 tlb1_set_entry(vm_offset_t va, vm_paddr_t pa, vm_size_t size,
2786 uint32_t flags)
2787 {
2788 tlb_entry_t e;
2789 uint32_t ts, tid;
2790 int tsize, index;
2791
2792 /* First try to update an existing entry. */
2793 for (index = 0; index < TLB1_ENTRIES; index++) {
2794 tlb1_read_entry(&e, index);
2795 /* Check if we're just updating the flags, and update them. */
2796 if (e.phys == pa && e.virt == va && e.size == size) {
2797 e.mas2 = (va & MAS2_EPN_MASK) | flags;
2798 tlb1_write_entry(&e, index);
2799 return (0);
2800 }
2801 }
2802
2803 /* Convert size to TSIZE */
2804 tsize = size2tsize(size);
2805
2806 tid = (TID_KERNEL << MAS1_TID_SHIFT) & MAS1_TID_MASK;
2807 /* XXX TS is hard coded to 0 for now as we only use single address space */
2808 ts = (0 << MAS1_TS_SHIFT) & MAS1_TS_MASK;
2809
2810 e.phys = pa;
2811 e.virt = va;
2812 e.size = size;
2813 e.mas1 = MAS1_VALID | MAS1_IPROT | ts | tid;
2814 e.mas1 |= ((tsize << MAS1_TSIZE_SHIFT) & MAS1_TSIZE_MASK);
2815 e.mas2 = (va & MAS2_EPN_MASK) | flags;
2816
2817 /* Set supervisor RWX permission bits */
2818 e.mas3 = (pa & MAS3_RPN) | MAS3_SR | MAS3_SW | MAS3_SX;
2819 e.mas7 = (pa >> 32) & MAS7_RPN;
2820
2821 tlb1_write_entry(&e, -1);
2822
2823 return (0);
2824 }
2825
2826 /*
2827 * Map in contiguous RAM region into the TLB1.
2828 */
2829 static vm_size_t
tlb1_mapin_region(vm_offset_t va,vm_paddr_t pa,vm_size_t size,int wimge)2830 tlb1_mapin_region(vm_offset_t va, vm_paddr_t pa, vm_size_t size, int wimge)
2831 {
2832 vm_offset_t base;
2833 vm_size_t mapped, sz, ssize;
2834 int shift;
2835
2836 mapped = 0;
2837 base = va;
2838 ssize = size;
2839
2840 if (mmuv2)
2841 shift = 1;
2842 else
2843 shift = 2;
2844
2845 while (size > 0) {
2846 sz = 1UL << (ilog2(size) & ~(shift - 1));
2847 /* Align size to PA */
2848 if (pa % sz != 0) {
2849 do {
2850 sz >>= shift;
2851 } while (pa % sz != 0);
2852 }
2853 /* Now align from there to VA */
2854 if (va % sz != 0) {
2855 do {
2856 sz >>= shift;
2857 } while (va % sz != 0);
2858 }
2859 #ifdef __powerpc64__
2860 /*
2861 * Clamp TLB1 entries to 4G.
2862 *
2863 * While the e6500 supports up to 1TB mappings, the e5500
2864 * only supports up to 4G mappings. (0b1011)
2865 *
2866 * If any e6500 machines capable of supporting a very
2867 * large amount of memory appear in the future, we can
2868 * revisit this.
2869 *
2870 * For now, though, since we have plenty of space in TLB1,
2871 * always avoid creating entries larger than 4GB.
2872 */
2873 if (!mmuv2)
2874 sz = MIN(sz, 1UL << 32);
2875 #endif
2876 if (bootverbose)
2877 printf("Wiring VA=%p to PA=%jx (size=%lx)\n",
2878 (void *)va, (uintmax_t)pa, (long)sz);
2879 if (tlb1_set_entry(va, pa, sz,
2880 _TLB_ENTRY_SHARED | wimge) < 0)
2881 return (mapped);
2882 size -= sz;
2883 pa += sz;
2884 va += sz;
2885 }
2886
2887 mapped = (va - base);
2888 if (bootverbose)
2889 printf("mapped size 0x%"PRIxPTR" (wasted space 0x%"PRIxPTR")\n",
2890 mapped, mapped - ssize);
2891
2892 return (mapped);
2893 }
2894
2895 /*
2896 * TLB1 initialization routine, to be called after the very first
2897 * assembler level setup done in locore.S.
2898 */
2899 void
tlb1_init(void)2900 tlb1_init(void)
2901 {
2902 vm_offset_t mas2;
2903 uint32_t mas0, mas1, mas3, mas7;
2904 uint32_t tsz;
2905
2906 tlb1_get_tlbconf();
2907
2908 mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(0);
2909 mtspr(SPR_MAS0, mas0);
2910 __asm __volatile("isync; tlbre");
2911
2912 mas1 = mfspr(SPR_MAS1);
2913 mas2 = mfspr(SPR_MAS2);
2914 mas3 = mfspr(SPR_MAS3);
2915 mas7 = mfspr(SPR_MAS7);
2916
2917 kernload = ((vm_paddr_t)(mas7 & MAS7_RPN) << 32) |
2918 (mas3 & MAS3_RPN);
2919
2920 tsz = (mas1 & MAS1_TSIZE_MASK) >> MAS1_TSIZE_SHIFT;
2921 kernsize += (tsz > 0) ? tsize2size(tsz) : 0;
2922 kernstart = trunc_page(mas2);
2923
2924 /* Setup TLB miss defaults */
2925 set_mas4_defaults();
2926 }
2927
2928 /*
2929 * pmap_early_io_unmap() should be used in short conjunction with
2930 * pmap_early_io_map(), as in the following snippet:
2931 *
2932 * x = pmap_early_io_map(...);
2933 * <do something with x>
2934 * pmap_early_io_unmap(x, size);
2935 *
2936 * And avoiding more allocations between.
2937 */
2938 void
pmap_early_io_unmap(vm_offset_t va,vm_size_t size)2939 pmap_early_io_unmap(vm_offset_t va, vm_size_t size)
2940 {
2941 int i;
2942 tlb_entry_t e;
2943 vm_size_t isize;
2944
2945 size = roundup(size, PAGE_SIZE);
2946 isize = size;
2947 for (i = 0; i < TLB1_ENTRIES && size > 0; i++) {
2948 tlb1_read_entry(&e, i);
2949 if (!(e.mas1 & MAS1_VALID))
2950 continue;
2951 if (va <= e.virt && (va + isize) >= (e.virt + e.size)) {
2952 size -= e.size;
2953 e.mas1 &= ~MAS1_VALID;
2954 tlb1_write_entry(&e, i);
2955 }
2956 }
2957 if (tlb1_map_base == va + isize)
2958 tlb1_map_base -= isize;
2959 }
2960
2961 vm_offset_t
pmap_early_io_map(vm_paddr_t pa,vm_size_t size)2962 pmap_early_io_map(vm_paddr_t pa, vm_size_t size)
2963 {
2964 vm_paddr_t pa_base;
2965 vm_offset_t va, sz;
2966 int i;
2967 tlb_entry_t e;
2968
2969 KASSERT(!pmap_bootstrapped, ("Do not use after PMAP is up!"));
2970
2971 for (i = 0; i < TLB1_ENTRIES; i++) {
2972 tlb1_read_entry(&e, i);
2973 if (!(e.mas1 & MAS1_VALID))
2974 continue;
2975 if (pa >= e.phys && (pa + size) <=
2976 (e.phys + e.size))
2977 return (e.virt + (pa - e.phys));
2978 }
2979
2980 pa_base = rounddown(pa, PAGE_SIZE);
2981 size = roundup(size + (pa - pa_base), PAGE_SIZE);
2982 tlb1_map_base = roundup2(tlb1_map_base, 1 << (ilog2(size) & ~1));
2983 va = tlb1_map_base + (pa - pa_base);
2984
2985 do {
2986 sz = 1 << (ilog2(size) & ~1);
2987 tlb1_set_entry(tlb1_map_base, pa_base, sz,
2988 _TLB_ENTRY_SHARED | _TLB_ENTRY_IO);
2989 size -= sz;
2990 pa_base += sz;
2991 tlb1_map_base += sz;
2992 } while (size > 0);
2993
2994 return (va);
2995 }
2996
2997 void
pmap_track_page(pmap_t pmap,vm_offset_t va)2998 pmap_track_page(pmap_t pmap, vm_offset_t va)
2999 {
3000 vm_paddr_t pa;
3001 vm_page_t page;
3002 struct pv_entry *pve;
3003
3004 va = trunc_page(va);
3005 pa = pmap_kextract(va);
3006 page = PHYS_TO_VM_PAGE(pa);
3007
3008 rw_wlock(&pvh_global_lock);
3009 PMAP_LOCK(pmap);
3010
3011 TAILQ_FOREACH(pve, &page->md.pv_list, pv_link) {
3012 if ((pmap == pve->pv_pmap) && (va == pve->pv_va)) {
3013 goto out;
3014 }
3015 }
3016 page->md.pv_tracked = true;
3017 pv_insert(pmap, va, page);
3018 out:
3019 PMAP_UNLOCK(pmap);
3020 rw_wunlock(&pvh_global_lock);
3021 }
3022
3023 /*
3024 * Setup MAS4 defaults.
3025 * These values are loaded to MAS0-2 on a TLB miss.
3026 */
3027 static void
set_mas4_defaults(void)3028 set_mas4_defaults(void)
3029 {
3030 uint32_t mas4;
3031
3032 /* Defaults: TLB0, PID0, TSIZED=4K */
3033 mas4 = MAS4_TLBSELD0;
3034 mas4 |= (TLB_SIZE_4K << MAS4_TSIZED_SHIFT) & MAS4_TSIZED_MASK;
3035 #ifdef SMP
3036 mas4 |= MAS4_MD;
3037 #endif
3038 mtspr(SPR_MAS4, mas4);
3039 __asm __volatile("isync");
3040 }
3041
3042 /*
3043 * Return 0 if the physical IO range is encompassed by one of the
3044 * the TLB1 entries, otherwise return related error code.
3045 */
3046 static int
tlb1_iomapped(int i,vm_paddr_t pa,vm_size_t size,vm_offset_t * va)3047 tlb1_iomapped(int i, vm_paddr_t pa, vm_size_t size, vm_offset_t *va)
3048 {
3049 uint32_t prot;
3050 vm_paddr_t pa_start;
3051 vm_paddr_t pa_end;
3052 unsigned int entry_tsize;
3053 vm_size_t entry_size;
3054 tlb_entry_t e;
3055
3056 *va = (vm_offset_t)NULL;
3057
3058 tlb1_read_entry(&e, i);
3059 /* Skip invalid entries */
3060 if (!(e.mas1 & MAS1_VALID))
3061 return (EINVAL);
3062
3063 /*
3064 * The entry must be cache-inhibited, guarded, and r/w
3065 * so it can function as an i/o page
3066 */
3067 prot = e.mas2 & (MAS2_I | MAS2_G);
3068 if (prot != (MAS2_I | MAS2_G))
3069 return (EPERM);
3070
3071 prot = e.mas3 & (MAS3_SR | MAS3_SW);
3072 if (prot != (MAS3_SR | MAS3_SW))
3073 return (EPERM);
3074
3075 /* The address should be within the entry range. */
3076 entry_tsize = (e.mas1 & MAS1_TSIZE_MASK) >> MAS1_TSIZE_SHIFT;
3077 KASSERT((entry_tsize), ("tlb1_iomapped: invalid entry tsize"));
3078
3079 entry_size = tsize2size(entry_tsize);
3080 pa_start = (((vm_paddr_t)e.mas7 & MAS7_RPN) << 32) |
3081 (e.mas3 & MAS3_RPN);
3082 pa_end = pa_start + entry_size;
3083
3084 if ((pa < pa_start) || ((pa + size) > pa_end))
3085 return (ERANGE);
3086
3087 /* Return virtual address of this mapping. */
3088 *va = (e.mas2 & MAS2_EPN_MASK) + (pa - pa_start);
3089 return (0);
3090 }
3091
3092 #ifdef DDB
3093 /* Print out contents of the MAS registers for each TLB0 entry */
3094 static void
3095 #ifdef __powerpc64__
tlb_print_entry(int i,uint32_t mas1,uint64_t mas2,uint32_t mas3,uint32_t mas7)3096 tlb_print_entry(int i, uint32_t mas1, uint64_t mas2, uint32_t mas3,
3097 #else
3098 tlb_print_entry(int i, uint32_t mas1, uint32_t mas2, uint32_t mas3,
3099 #endif
3100 uint32_t mas7)
3101 {
3102 int as;
3103 char desc[3];
3104 tlbtid_t tid;
3105 vm_size_t size;
3106 unsigned int tsize;
3107
3108 desc[2] = '\0';
3109 if (mas1 & MAS1_VALID)
3110 desc[0] = 'V';
3111 else
3112 desc[0] = ' ';
3113
3114 if (mas1 & MAS1_IPROT)
3115 desc[1] = 'P';
3116 else
3117 desc[1] = ' ';
3118
3119 as = (mas1 & MAS1_TS_MASK) ? 1 : 0;
3120 tid = MAS1_GETTID(mas1);
3121
3122 tsize = (mas1 & MAS1_TSIZE_MASK) >> MAS1_TSIZE_SHIFT;
3123 size = 0;
3124 if (tsize)
3125 size = tsize2size(tsize);
3126
3127 printf("%3d: (%s) [AS=%d] "
3128 "sz = 0x%jx tsz = %d tid = %d mas1 = 0x%08x "
3129 "mas2(va) = 0x%"PRI0ptrX" mas3(pa) = 0x%08x mas7 = 0x%08x\n",
3130 i, desc, as, (uintmax_t)size, tsize, tid, mas1, mas2, mas3, mas7);
3131 }
3132
DB_SHOW_COMMAND(tlb0,tlb0_print_tlbentries)3133 DB_SHOW_COMMAND(tlb0, tlb0_print_tlbentries)
3134 {
3135 uint32_t mas0, mas1, mas3, mas7;
3136 #ifdef __powerpc64__
3137 uint64_t mas2;
3138 #else
3139 uint32_t mas2;
3140 #endif
3141 int entryidx, way, idx;
3142
3143 printf("TLB0 entries:\n");
3144 for (way = 0; way < TLB0_WAYS; way ++)
3145 for (entryidx = 0; entryidx < TLB0_ENTRIES_PER_WAY; entryidx++) {
3146 mas0 = MAS0_TLBSEL(0) | MAS0_ESEL(way);
3147 mtspr(SPR_MAS0, mas0);
3148
3149 mas2 = entryidx << MAS2_TLB0_ENTRY_IDX_SHIFT;
3150 mtspr(SPR_MAS2, mas2);
3151
3152 __asm __volatile("isync; tlbre");
3153
3154 mas1 = mfspr(SPR_MAS1);
3155 mas2 = mfspr(SPR_MAS2);
3156 mas3 = mfspr(SPR_MAS3);
3157 mas7 = mfspr(SPR_MAS7);
3158
3159 idx = tlb0_tableidx(mas2, way);
3160 tlb_print_entry(idx, mas1, mas2, mas3, mas7);
3161 }
3162 }
3163
3164 /*
3165 * Print out contents of the MAS registers for each TLB1 entry
3166 */
DB_SHOW_COMMAND(tlb1,tlb1_print_tlbentries)3167 DB_SHOW_COMMAND(tlb1, tlb1_print_tlbentries)
3168 {
3169 uint32_t mas0, mas1, mas3, mas7;
3170 #ifdef __powerpc64__
3171 uint64_t mas2;
3172 #else
3173 uint32_t mas2;
3174 #endif
3175 int i;
3176
3177 printf("TLB1 entries:\n");
3178 for (i = 0; i < TLB1_ENTRIES; i++) {
3179 mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(i);
3180 mtspr(SPR_MAS0, mas0);
3181
3182 __asm __volatile("isync; tlbre");
3183
3184 mas1 = mfspr(SPR_MAS1);
3185 mas2 = mfspr(SPR_MAS2);
3186 mas3 = mfspr(SPR_MAS3);
3187 mas7 = mfspr(SPR_MAS7);
3188
3189 tlb_print_entry(i, mas1, mas2, mas3, mas7);
3190 }
3191 }
3192 #endif
3193