1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2016-2022 NVIDIA Corporation
4 *
5 * Author: Thierry Reding <treding@nvidia.com>
6 * Dipen Patel <dpatel@nvidia.com>
7 */
8
9 #include <linux/gpio/driver.h>
10 #include <linux/hte.h>
11 #include <linux/interrupt.h>
12 #include <linux/irq.h>
13 #include <linux/module.h>
14 #include <linux/of.h>
15 #include <linux/platform_device.h>
16 #include <linux/property.h>
17 #include <linux/seq_file.h>
18
19 #include <dt-bindings/gpio/tegra186-gpio.h>
20 #include <dt-bindings/gpio/tegra194-gpio.h>
21 #include <dt-bindings/gpio/tegra234-gpio.h>
22 #include <dt-bindings/gpio/tegra241-gpio.h>
23
24 /* security registers */
25 #define TEGRA186_GPIO_CTL_SCR 0x0c
26 #define TEGRA186_GPIO_CTL_SCR_SEC_WEN BIT(28)
27 #define TEGRA186_GPIO_CTL_SCR_SEC_REN BIT(27)
28
29 #define TEGRA186_GPIO_INT_ROUTE_MAPPING(p, x) (0x14 + (p) * 0x20 + (x) * 4)
30
31 #define TEGRA186_GPIO_VM 0x00
32 #define TEGRA186_GPIO_VM_RW_MASK 0x03
33 #define TEGRA186_GPIO_SCR 0x04
34 #define TEGRA186_GPIO_SCR_PIN_SIZE 0x08
35 #define TEGRA186_GPIO_SCR_PORT_SIZE 0x40
36 #define TEGRA186_GPIO_SCR_SEC_WEN BIT(28)
37 #define TEGRA186_GPIO_SCR_SEC_REN BIT(27)
38 #define TEGRA186_GPIO_SCR_SEC_G1W BIT(9)
39 #define TEGRA186_GPIO_SCR_SEC_G1R BIT(1)
40
41 /* control registers */
42 #define TEGRA186_GPIO_ENABLE_CONFIG 0x00
43 #define TEGRA186_GPIO_ENABLE_CONFIG_ENABLE BIT(0)
44 #define TEGRA186_GPIO_ENABLE_CONFIG_OUT BIT(1)
45 #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_NONE (0x0 << 2)
46 #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_LEVEL (0x1 << 2)
47 #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE (0x2 << 2)
48 #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_DOUBLE_EDGE (0x3 << 2)
49 #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_MASK (0x3 << 2)
50 #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL BIT(4)
51 #define TEGRA186_GPIO_ENABLE_CONFIG_DEBOUNCE BIT(5)
52 #define TEGRA186_GPIO_ENABLE_CONFIG_INTERRUPT BIT(6)
53 #define TEGRA186_GPIO_ENABLE_CONFIG_TIMESTAMP_FUNC BIT(7)
54
55 #define TEGRA186_GPIO_DEBOUNCE_CONTROL 0x04
56 #define TEGRA186_GPIO_DEBOUNCE_CONTROL_THRESHOLD(x) ((x) & 0xff)
57
58 #define TEGRA186_GPIO_INPUT 0x08
59 #define TEGRA186_GPIO_INPUT_HIGH BIT(0)
60
61 #define TEGRA186_GPIO_OUTPUT_CONTROL 0x0c
62 #define TEGRA186_GPIO_OUTPUT_CONTROL_FLOATED BIT(0)
63
64 #define TEGRA186_GPIO_OUTPUT_VALUE 0x10
65 #define TEGRA186_GPIO_OUTPUT_VALUE_HIGH BIT(0)
66
67 #define TEGRA186_GPIO_INTERRUPT_CLEAR 0x14
68
69 #define TEGRA186_GPIO_INTERRUPT_STATUS(x) (0x100 + (x) * 4)
70
71 struct tegra_gpio_port {
72 const char *name;
73 unsigned int bank;
74 unsigned int port;
75 unsigned int pins;
76 };
77
78 struct tegra186_pin_range {
79 unsigned int offset;
80 const char *group;
81 };
82
83 struct tegra_gpio_soc {
84 const struct tegra_gpio_port *ports;
85 unsigned int num_ports;
86 const char *name;
87 unsigned int instance;
88
89 unsigned int num_irqs_per_bank;
90
91 const struct tegra186_pin_range *pin_ranges;
92 unsigned int num_pin_ranges;
93 const char *pinmux;
94 bool has_gte;
95 bool has_vm_support;
96 };
97
98 struct tegra_gpio {
99 struct gpio_chip gpio;
100 unsigned int num_irq;
101 unsigned int *irq;
102
103 const struct tegra_gpio_soc *soc;
104 unsigned int num_irqs_per_bank;
105 unsigned int num_banks;
106
107 void __iomem *secure;
108 void __iomem *base;
109 };
110
111 static const struct tegra_gpio_port *
tegra186_gpio_get_port(struct tegra_gpio * gpio,unsigned int * pin)112 tegra186_gpio_get_port(struct tegra_gpio *gpio, unsigned int *pin)
113 {
114 unsigned int start = 0, i;
115
116 for (i = 0; i < gpio->soc->num_ports; i++) {
117 const struct tegra_gpio_port *port = &gpio->soc->ports[i];
118
119 if (*pin >= start && *pin < start + port->pins) {
120 *pin -= start;
121 return port;
122 }
123
124 start += port->pins;
125 }
126
127 return NULL;
128 }
129
tegra186_gpio_get_base(struct tegra_gpio * gpio,unsigned int pin)130 static void __iomem *tegra186_gpio_get_base(struct tegra_gpio *gpio,
131 unsigned int pin)
132 {
133 const struct tegra_gpio_port *port;
134 unsigned int offset;
135
136 port = tegra186_gpio_get_port(gpio, &pin);
137 if (!port)
138 return NULL;
139
140 offset = port->bank * 0x1000 + port->port * 0x200;
141
142 return gpio->base + offset + pin * 0x20;
143 }
144
tegra186_gpio_get_secure_base(struct tegra_gpio * gpio,unsigned int pin)145 static void __iomem *tegra186_gpio_get_secure_base(struct tegra_gpio *gpio,
146 unsigned int pin)
147 {
148 const struct tegra_gpio_port *port;
149 unsigned int offset;
150
151 port = tegra186_gpio_get_port(gpio, &pin);
152 if (!port)
153 return NULL;
154
155 offset = port->bank * 0x1000 + port->port * TEGRA186_GPIO_SCR_PORT_SIZE;
156
157 return gpio->secure + offset + pin * TEGRA186_GPIO_SCR_PIN_SIZE;
158 }
159
tegra186_gpio_is_accessible(struct tegra_gpio * gpio,unsigned int pin)160 static inline bool tegra186_gpio_is_accessible(struct tegra_gpio *gpio, unsigned int pin)
161 {
162 void __iomem *secure;
163 u32 value;
164
165 secure = tegra186_gpio_get_secure_base(gpio, pin);
166
167 if (gpio->soc->has_vm_support) {
168 value = readl(secure + TEGRA186_GPIO_VM);
169 if ((value & TEGRA186_GPIO_VM_RW_MASK) != TEGRA186_GPIO_VM_RW_MASK)
170 return false;
171 }
172
173 value = __raw_readl(secure + TEGRA186_GPIO_SCR);
174
175 /*
176 * When SCR_SEC_[R|W]EN is unset, then we have full read/write access to all the
177 * registers for given GPIO pin.
178 * When SCR_SEC[R|W]EN is set, then there is need to further check the accompanying
179 * SCR_SEC_G1[R|W] bit to determine read/write access to all the registers for given
180 * GPIO pin.
181 */
182
183 if (((value & TEGRA186_GPIO_SCR_SEC_REN) == 0 ||
184 ((value & TEGRA186_GPIO_SCR_SEC_REN) && (value & TEGRA186_GPIO_SCR_SEC_G1R))) &&
185 ((value & TEGRA186_GPIO_SCR_SEC_WEN) == 0 ||
186 ((value & TEGRA186_GPIO_SCR_SEC_WEN) && (value & TEGRA186_GPIO_SCR_SEC_G1W))))
187 return true;
188
189 return false;
190 }
191
tegra186_init_valid_mask(struct gpio_chip * chip,unsigned long * valid_mask,unsigned int ngpios)192 static int tegra186_init_valid_mask(struct gpio_chip *chip,
193 unsigned long *valid_mask, unsigned int ngpios)
194 {
195 struct tegra_gpio *gpio = gpiochip_get_data(chip);
196 unsigned int j;
197
198 for (j = 0; j < ngpios; j++) {
199 if (!tegra186_gpio_is_accessible(gpio, j))
200 clear_bit(j, valid_mask);
201 }
202 return 0;
203 }
204
tegra186_gpio_set(struct gpio_chip * chip,unsigned int offset,int level)205 static int tegra186_gpio_set(struct gpio_chip *chip, unsigned int offset,
206 int level)
207 {
208 struct tegra_gpio *gpio = gpiochip_get_data(chip);
209 void __iomem *base;
210 u32 value;
211
212 base = tegra186_gpio_get_base(gpio, offset);
213 if (WARN_ON(base == NULL))
214 return -ENODEV;
215
216 value = readl(base + TEGRA186_GPIO_OUTPUT_VALUE);
217 if (level == 0)
218 value &= ~TEGRA186_GPIO_OUTPUT_VALUE_HIGH;
219 else
220 value |= TEGRA186_GPIO_OUTPUT_VALUE_HIGH;
221
222 writel(value, base + TEGRA186_GPIO_OUTPUT_VALUE);
223
224 return 0;
225 }
226
tegra186_gpio_get_direction(struct gpio_chip * chip,unsigned int offset)227 static int tegra186_gpio_get_direction(struct gpio_chip *chip,
228 unsigned int offset)
229 {
230 struct tegra_gpio *gpio = gpiochip_get_data(chip);
231 void __iomem *base;
232 u32 value;
233
234 base = tegra186_gpio_get_base(gpio, offset);
235 if (WARN_ON(base == NULL))
236 return -ENODEV;
237
238 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
239 if (value & TEGRA186_GPIO_ENABLE_CONFIG_OUT)
240 return GPIO_LINE_DIRECTION_OUT;
241
242 return GPIO_LINE_DIRECTION_IN;
243 }
244
tegra186_gpio_direction_input(struct gpio_chip * chip,unsigned int offset)245 static int tegra186_gpio_direction_input(struct gpio_chip *chip,
246 unsigned int offset)
247 {
248 struct tegra_gpio *gpio = gpiochip_get_data(chip);
249 void __iomem *base;
250 u32 value;
251
252 base = tegra186_gpio_get_base(gpio, offset);
253 if (WARN_ON(base == NULL))
254 return -ENODEV;
255
256 value = readl(base + TEGRA186_GPIO_OUTPUT_CONTROL);
257 value |= TEGRA186_GPIO_OUTPUT_CONTROL_FLOATED;
258 writel(value, base + TEGRA186_GPIO_OUTPUT_CONTROL);
259
260 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
261 value |= TEGRA186_GPIO_ENABLE_CONFIG_ENABLE;
262 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_OUT;
263 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG);
264
265 return 0;
266 }
267
tegra186_gpio_direction_output(struct gpio_chip * chip,unsigned int offset,int level)268 static int tegra186_gpio_direction_output(struct gpio_chip *chip,
269 unsigned int offset, int level)
270 {
271 struct tegra_gpio *gpio = gpiochip_get_data(chip);
272 void __iomem *base;
273 u32 value;
274 int ret;
275
276 /* configure output level first */
277 ret = tegra186_gpio_set(chip, offset, level);
278 if (ret)
279 return ret;
280
281 base = tegra186_gpio_get_base(gpio, offset);
282 if (WARN_ON(base == NULL))
283 return -EINVAL;
284
285 /* set the direction */
286 value = readl(base + TEGRA186_GPIO_OUTPUT_CONTROL);
287 value &= ~TEGRA186_GPIO_OUTPUT_CONTROL_FLOATED;
288 writel(value, base + TEGRA186_GPIO_OUTPUT_CONTROL);
289
290 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
291 value |= TEGRA186_GPIO_ENABLE_CONFIG_ENABLE;
292 value |= TEGRA186_GPIO_ENABLE_CONFIG_OUT;
293 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG);
294
295 return 0;
296 }
297
298 #define HTE_BOTH_EDGES (HTE_RISING_EDGE_TS | HTE_FALLING_EDGE_TS)
299
tegra186_gpio_en_hw_ts(struct gpio_chip * gc,u32 offset,unsigned long flags)300 static int tegra186_gpio_en_hw_ts(struct gpio_chip *gc, u32 offset,
301 unsigned long flags)
302 {
303 struct tegra_gpio *gpio;
304 void __iomem *base;
305 int value;
306
307 if (!gc)
308 return -EINVAL;
309
310 gpio = gpiochip_get_data(gc);
311 if (!gpio)
312 return -ENODEV;
313
314 base = tegra186_gpio_get_base(gpio, offset);
315 if (WARN_ON(base == NULL))
316 return -EINVAL;
317
318 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
319 value |= TEGRA186_GPIO_ENABLE_CONFIG_TIMESTAMP_FUNC;
320
321 if (flags == HTE_BOTH_EDGES) {
322 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_DOUBLE_EDGE;
323 } else if (flags == HTE_RISING_EDGE_TS) {
324 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE;
325 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL;
326 } else if (flags == HTE_FALLING_EDGE_TS) {
327 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE;
328 }
329
330 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG);
331
332 return 0;
333 }
334
tegra186_gpio_dis_hw_ts(struct gpio_chip * gc,u32 offset,unsigned long flags)335 static int tegra186_gpio_dis_hw_ts(struct gpio_chip *gc, u32 offset,
336 unsigned long flags)
337 {
338 struct tegra_gpio *gpio;
339 void __iomem *base;
340 int value;
341
342 if (!gc)
343 return -EINVAL;
344
345 gpio = gpiochip_get_data(gc);
346 if (!gpio)
347 return -ENODEV;
348
349 base = tegra186_gpio_get_base(gpio, offset);
350 if (WARN_ON(base == NULL))
351 return -EINVAL;
352
353 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
354 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_TIMESTAMP_FUNC;
355 if (flags == HTE_BOTH_EDGES) {
356 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_DOUBLE_EDGE;
357 } else if (flags == HTE_RISING_EDGE_TS) {
358 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE;
359 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL;
360 } else if (flags == HTE_FALLING_EDGE_TS) {
361 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE;
362 }
363 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG);
364
365 return 0;
366 }
367
tegra186_gpio_get(struct gpio_chip * chip,unsigned int offset)368 static int tegra186_gpio_get(struct gpio_chip *chip, unsigned int offset)
369 {
370 struct tegra_gpio *gpio = gpiochip_get_data(chip);
371 void __iomem *base;
372 u32 value;
373
374 base = tegra186_gpio_get_base(gpio, offset);
375 if (WARN_ON(base == NULL))
376 return -ENODEV;
377
378 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
379 if (value & TEGRA186_GPIO_ENABLE_CONFIG_OUT)
380 value = readl(base + TEGRA186_GPIO_OUTPUT_VALUE);
381 else
382 value = readl(base + TEGRA186_GPIO_INPUT);
383
384 return value & BIT(0);
385 }
386
tegra186_gpio_set_config(struct gpio_chip * chip,unsigned int offset,unsigned long config)387 static int tegra186_gpio_set_config(struct gpio_chip *chip,
388 unsigned int offset,
389 unsigned long config)
390 {
391 struct tegra_gpio *gpio = gpiochip_get_data(chip);
392 u32 debounce, value;
393 void __iomem *base;
394
395 base = tegra186_gpio_get_base(gpio, offset);
396 if (base == NULL)
397 return -ENXIO;
398
399 if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE)
400 return -ENOTSUPP;
401
402 debounce = pinconf_to_config_argument(config);
403
404 /*
405 * The Tegra186 GPIO controller supports a maximum of 255 ms debounce
406 * time.
407 */
408 if (debounce > 255000)
409 return -EINVAL;
410
411 debounce = DIV_ROUND_UP(debounce, USEC_PER_MSEC);
412
413 value = TEGRA186_GPIO_DEBOUNCE_CONTROL_THRESHOLD(debounce);
414 writel(value, base + TEGRA186_GPIO_DEBOUNCE_CONTROL);
415
416 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
417 value |= TEGRA186_GPIO_ENABLE_CONFIG_DEBOUNCE;
418 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG);
419
420 return 0;
421 }
422
tegra186_gpio_add_pin_ranges(struct gpio_chip * chip)423 static int tegra186_gpio_add_pin_ranges(struct gpio_chip *chip)
424 {
425 struct tegra_gpio *gpio = gpiochip_get_data(chip);
426 struct pinctrl_dev *pctldev;
427 struct device_node *np;
428 unsigned int i, j;
429 int err;
430
431 if (!gpio->soc->pinmux || gpio->soc->num_pin_ranges == 0)
432 return 0;
433
434 np = of_find_compatible_node(NULL, NULL, gpio->soc->pinmux);
435 if (!np)
436 return -ENODEV;
437
438 pctldev = of_pinctrl_get(np);
439 of_node_put(np);
440 if (!pctldev)
441 return -EPROBE_DEFER;
442
443 for (i = 0; i < gpio->soc->num_pin_ranges; i++) {
444 unsigned int pin = gpio->soc->pin_ranges[i].offset, port;
445 const char *group = gpio->soc->pin_ranges[i].group;
446
447 port = pin / 8;
448 pin = pin % 8;
449
450 if (port >= gpio->soc->num_ports) {
451 dev_warn(chip->parent, "invalid port %u for %s\n",
452 port, group);
453 continue;
454 }
455
456 for (j = 0; j < port; j++)
457 pin += gpio->soc->ports[j].pins;
458
459 err = gpiochip_add_pingroup_range(chip, pctldev, pin, group);
460 if (err < 0)
461 return err;
462 }
463
464 return 0;
465 }
466
tegra186_gpio_of_xlate(struct gpio_chip * chip,const struct of_phandle_args * spec,u32 * flags)467 static int tegra186_gpio_of_xlate(struct gpio_chip *chip,
468 const struct of_phandle_args *spec,
469 u32 *flags)
470 {
471 struct tegra_gpio *gpio = gpiochip_get_data(chip);
472 unsigned int port, pin, i, offset = 0;
473
474 if (WARN_ON(chip->of_gpio_n_cells < 2))
475 return -EINVAL;
476
477 if (WARN_ON(spec->args_count < chip->of_gpio_n_cells))
478 return -EINVAL;
479
480 port = spec->args[0] / 8;
481 pin = spec->args[0] % 8;
482
483 if (port >= gpio->soc->num_ports) {
484 dev_err(chip->parent, "invalid port number: %u\n", port);
485 return -EINVAL;
486 }
487
488 for (i = 0; i < port; i++)
489 offset += gpio->soc->ports[i].pins;
490
491 if (flags)
492 *flags = spec->args[1];
493
494 return offset + pin;
495 }
496
497 #define to_tegra_gpio(x) container_of((x), struct tegra_gpio, gpio)
498
tegra186_irq_ack(struct irq_data * data)499 static void tegra186_irq_ack(struct irq_data *data)
500 {
501 struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
502 struct tegra_gpio *gpio = to_tegra_gpio(gc);
503 void __iomem *base;
504
505 base = tegra186_gpio_get_base(gpio, data->hwirq);
506 if (WARN_ON(base == NULL))
507 return;
508
509 writel(1, base + TEGRA186_GPIO_INTERRUPT_CLEAR);
510 }
511
tegra186_irq_mask(struct irq_data * data)512 static void tegra186_irq_mask(struct irq_data *data)
513 {
514 struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
515 struct tegra_gpio *gpio = to_tegra_gpio(gc);
516 void __iomem *base;
517 u32 value;
518
519 base = tegra186_gpio_get_base(gpio, data->hwirq);
520 if (WARN_ON(base == NULL))
521 return;
522
523 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
524 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_INTERRUPT;
525 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG);
526
527 gpiochip_disable_irq(&gpio->gpio, data->hwirq);
528 }
529
tegra186_irq_unmask(struct irq_data * data)530 static void tegra186_irq_unmask(struct irq_data *data)
531 {
532 struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
533 struct tegra_gpio *gpio = to_tegra_gpio(gc);
534 void __iomem *base;
535 u32 value;
536
537 base = tegra186_gpio_get_base(gpio, data->hwirq);
538 if (WARN_ON(base == NULL))
539 return;
540
541 gpiochip_enable_irq(&gpio->gpio, data->hwirq);
542
543 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
544 value |= TEGRA186_GPIO_ENABLE_CONFIG_INTERRUPT;
545 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG);
546 }
547
tegra186_irq_set_type(struct irq_data * data,unsigned int type)548 static int tegra186_irq_set_type(struct irq_data *data, unsigned int type)
549 {
550 struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
551 struct tegra_gpio *gpio = to_tegra_gpio(gc);
552 void __iomem *base;
553 u32 value;
554
555 base = tegra186_gpio_get_base(gpio, data->hwirq);
556 if (WARN_ON(base == NULL))
557 return -ENODEV;
558
559 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
560 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_MASK;
561 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL;
562
563 switch (type & IRQ_TYPE_SENSE_MASK) {
564 case IRQ_TYPE_NONE:
565 break;
566
567 case IRQ_TYPE_EDGE_RISING:
568 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE;
569 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL;
570 break;
571
572 case IRQ_TYPE_EDGE_FALLING:
573 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE;
574 break;
575
576 case IRQ_TYPE_EDGE_BOTH:
577 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_DOUBLE_EDGE;
578 break;
579
580 case IRQ_TYPE_LEVEL_HIGH:
581 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_LEVEL;
582 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL;
583 break;
584
585 case IRQ_TYPE_LEVEL_LOW:
586 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_LEVEL;
587 break;
588
589 default:
590 return -EINVAL;
591 }
592
593 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG);
594
595 if ((type & IRQ_TYPE_EDGE_BOTH) == 0)
596 irq_set_handler_locked(data, handle_level_irq);
597 else
598 irq_set_handler_locked(data, handle_edge_irq);
599
600 if (data->parent_data)
601 return irq_chip_set_type_parent(data, type);
602
603 return 0;
604 }
605
tegra186_irq_set_wake(struct irq_data * data,unsigned int on)606 static int tegra186_irq_set_wake(struct irq_data *data, unsigned int on)
607 {
608 if (data->parent_data)
609 return irq_chip_set_wake_parent(data, on);
610
611 return 0;
612 }
613
tegra186_irq_print_chip(struct irq_data * data,struct seq_file * p)614 static void tegra186_irq_print_chip(struct irq_data *data, struct seq_file *p)
615 {
616 struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
617
618 seq_puts(p, dev_name(gc->parent));
619 }
620
621 static const struct irq_chip tegra186_gpio_irq_chip = {
622 .irq_ack = tegra186_irq_ack,
623 .irq_mask = tegra186_irq_mask,
624 .irq_unmask = tegra186_irq_unmask,
625 .irq_set_type = tegra186_irq_set_type,
626 .irq_set_wake = tegra186_irq_set_wake,
627 .irq_print_chip = tegra186_irq_print_chip,
628 .flags = IRQCHIP_IMMUTABLE,
629 GPIOCHIP_IRQ_RESOURCE_HELPERS,
630 };
631
tegra186_gpio_irq(struct irq_desc * desc)632 static void tegra186_gpio_irq(struct irq_desc *desc)
633 {
634 struct tegra_gpio *gpio = irq_desc_get_handler_data(desc);
635 struct irq_domain *domain = gpio->gpio.irq.domain;
636 struct irq_chip *chip = irq_desc_get_chip(desc);
637 unsigned int parent = irq_desc_get_irq(desc);
638 unsigned int i, j, offset = 0;
639
640 chained_irq_enter(chip, desc);
641
642 for (i = 0; i < gpio->soc->num_ports; i++) {
643 const struct tegra_gpio_port *port = &gpio->soc->ports[i];
644 unsigned int pin;
645 unsigned long value;
646 void __iomem *base;
647
648 base = gpio->base + port->bank * 0x1000 + port->port * 0x200;
649
650 /* skip ports that are not associated with this bank */
651 for (j = 0; j < gpio->num_irqs_per_bank; j++) {
652 if (parent == gpio->irq[port->bank * gpio->num_irqs_per_bank + j])
653 break;
654 }
655
656 if (j == gpio->num_irqs_per_bank)
657 goto skip;
658
659 value = readl(base + TEGRA186_GPIO_INTERRUPT_STATUS(1));
660
661 for_each_set_bit(pin, &value, port->pins) {
662 int ret = generic_handle_domain_irq(domain, offset + pin);
663 WARN_RATELIMIT(ret, "hwirq = %d", offset + pin);
664 }
665
666 skip:
667 offset += port->pins;
668 }
669
670 chained_irq_exit(chip, desc);
671 }
672
tegra186_gpio_irq_domain_translate(struct irq_domain * domain,struct irq_fwspec * fwspec,unsigned long * hwirq,unsigned int * type)673 static int tegra186_gpio_irq_domain_translate(struct irq_domain *domain,
674 struct irq_fwspec *fwspec,
675 unsigned long *hwirq,
676 unsigned int *type)
677 {
678 struct tegra_gpio *gpio = gpiochip_get_data(domain->host_data);
679 unsigned int port, pin, i, offset = 0;
680
681 if (WARN_ON(gpio->gpio.of_gpio_n_cells < 2))
682 return -EINVAL;
683
684 if (WARN_ON(fwspec->param_count < gpio->gpio.of_gpio_n_cells))
685 return -EINVAL;
686
687 port = fwspec->param[0] / 8;
688 pin = fwspec->param[0] % 8;
689
690 if (port >= gpio->soc->num_ports)
691 return -EINVAL;
692
693 for (i = 0; i < port; i++)
694 offset += gpio->soc->ports[i].pins;
695
696 *type = fwspec->param[1] & IRQ_TYPE_SENSE_MASK;
697 *hwirq = offset + pin;
698
699 return 0;
700 }
701
tegra186_gpio_populate_parent_fwspec(struct gpio_chip * chip,union gpio_irq_fwspec * gfwspec,unsigned int parent_hwirq,unsigned int parent_type)702 static int tegra186_gpio_populate_parent_fwspec(struct gpio_chip *chip,
703 union gpio_irq_fwspec *gfwspec,
704 unsigned int parent_hwirq,
705 unsigned int parent_type)
706 {
707 struct tegra_gpio *gpio = gpiochip_get_data(chip);
708 struct irq_fwspec *fwspec = &gfwspec->fwspec;
709
710 fwspec->fwnode = chip->irq.parent_domain->fwnode;
711 fwspec->param_count = 3;
712 fwspec->param[0] = gpio->soc->instance;
713 fwspec->param[1] = parent_hwirq;
714 fwspec->param[2] = parent_type;
715
716 return 0;
717 }
718
tegra186_gpio_child_to_parent_hwirq(struct gpio_chip * chip,unsigned int hwirq,unsigned int type,unsigned int * parent_hwirq,unsigned int * parent_type)719 static int tegra186_gpio_child_to_parent_hwirq(struct gpio_chip *chip,
720 unsigned int hwirq,
721 unsigned int type,
722 unsigned int *parent_hwirq,
723 unsigned int *parent_type)
724 {
725 *parent_hwirq = chip->irq.child_offset_to_irq(chip, hwirq);
726 *parent_type = type;
727
728 return 0;
729 }
730
tegra186_gpio_child_offset_to_irq(struct gpio_chip * chip,unsigned int offset)731 static unsigned int tegra186_gpio_child_offset_to_irq(struct gpio_chip *chip,
732 unsigned int offset)
733 {
734 struct tegra_gpio *gpio = gpiochip_get_data(chip);
735 unsigned int i;
736
737 for (i = 0; i < gpio->soc->num_ports; i++) {
738 if (offset < gpio->soc->ports[i].pins)
739 break;
740
741 offset -= gpio->soc->ports[i].pins;
742 }
743
744 return offset + i * 8;
745 }
746
747 static const struct of_device_id tegra186_pmc_of_match[] = {
748 { .compatible = "nvidia,tegra186-pmc" },
749 { .compatible = "nvidia,tegra194-pmc" },
750 { .compatible = "nvidia,tegra234-pmc" },
751 { /* sentinel */ }
752 };
753
tegra186_gpio_init_route_mapping(struct tegra_gpio * gpio)754 static void tegra186_gpio_init_route_mapping(struct tegra_gpio *gpio)
755 {
756 struct device *dev = gpio->gpio.parent;
757 unsigned int i;
758 u32 value;
759
760 for (i = 0; i < gpio->soc->num_ports; i++) {
761 const struct tegra_gpio_port *port = &gpio->soc->ports[i];
762 unsigned int offset, p = port->port;
763 void __iomem *base;
764
765 base = gpio->secure + port->bank * 0x1000 + 0x800;
766
767 value = readl(base + TEGRA186_GPIO_CTL_SCR);
768
769 /*
770 * For controllers that haven't been locked down yet, make
771 * sure to program the default interrupt route mapping.
772 */
773 if ((value & TEGRA186_GPIO_CTL_SCR_SEC_REN) == 0 &&
774 (value & TEGRA186_GPIO_CTL_SCR_SEC_WEN) == 0) {
775 /*
776 * On Tegra194 and later, each pin can be routed to one or more
777 * interrupts.
778 */
779 dev_dbg(dev, "programming default interrupt routing for port %s\n",
780 port->name);
781
782 offset = TEGRA186_GPIO_INT_ROUTE_MAPPING(p, 0);
783
784 /*
785 * By default we only want to route GPIO pins to IRQ 0. This works
786 * only under the assumption that we're running as the host kernel
787 * and hence all GPIO pins are owned by Linux.
788 *
789 * For cases where Linux is the guest OS, the hypervisor will have
790 * to configure the interrupt routing and pass only the valid
791 * interrupts via device tree.
792 */
793 value = readl(base + offset);
794 value = BIT(port->pins) - 1;
795 writel(value, base + offset);
796 }
797 }
798 }
799
tegra186_gpio_irqs_per_bank(struct tegra_gpio * gpio)800 static unsigned int tegra186_gpio_irqs_per_bank(struct tegra_gpio *gpio)
801 {
802 struct device *dev = gpio->gpio.parent;
803
804 if (gpio->num_irq > gpio->num_banks) {
805 if (gpio->num_irq % gpio->num_banks != 0)
806 goto error;
807 }
808
809 if (gpio->num_irq < gpio->num_banks)
810 goto error;
811
812 gpio->num_irqs_per_bank = gpio->num_irq / gpio->num_banks;
813
814 if (gpio->num_irqs_per_bank > gpio->soc->num_irqs_per_bank)
815 goto error;
816
817 return 0;
818
819 error:
820 dev_err(dev, "invalid number of interrupts (%u) for %u banks\n",
821 gpio->num_irq, gpio->num_banks);
822 return -EINVAL;
823 }
824
tegra186_gpio_probe(struct platform_device * pdev)825 static int tegra186_gpio_probe(struct platform_device *pdev)
826 {
827 unsigned int i, j, offset;
828 struct gpio_irq_chip *irq;
829 struct tegra_gpio *gpio;
830 struct device_node *np;
831 struct resource *res;
832 char **names;
833 int err;
834
835 gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);
836 if (!gpio)
837 return -ENOMEM;
838
839 gpio->soc = device_get_match_data(&pdev->dev);
840 gpio->gpio.label = gpio->soc->name;
841 gpio->gpio.parent = &pdev->dev;
842
843 /* count the number of banks in the controller */
844 for (i = 0; i < gpio->soc->num_ports; i++)
845 if (gpio->soc->ports[i].bank > gpio->num_banks)
846 gpio->num_banks = gpio->soc->ports[i].bank;
847
848 gpio->num_banks++;
849
850 /* get register apertures */
851 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "security");
852 if (!res)
853 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
854 gpio->secure = devm_ioremap_resource(&pdev->dev, res);
855 if (IS_ERR(gpio->secure))
856 return PTR_ERR(gpio->secure);
857
858 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "gpio");
859 if (!res)
860 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
861 gpio->base = devm_ioremap_resource(&pdev->dev, res);
862 if (IS_ERR(gpio->base))
863 return PTR_ERR(gpio->base);
864
865 err = platform_irq_count(pdev);
866 if (err < 0)
867 return err;
868
869 gpio->num_irq = err;
870
871 err = tegra186_gpio_irqs_per_bank(gpio);
872 if (err < 0)
873 return err;
874
875 gpio->irq = devm_kcalloc(&pdev->dev, gpio->num_irq, sizeof(*gpio->irq),
876 GFP_KERNEL);
877 if (!gpio->irq)
878 return -ENOMEM;
879
880 for (i = 0; i < gpio->num_irq; i++) {
881 err = platform_get_irq(pdev, i);
882 if (err < 0)
883 return err;
884
885 gpio->irq[i] = err;
886 }
887
888 gpio->gpio.request = gpiochip_generic_request;
889 gpio->gpio.free = gpiochip_generic_free;
890 gpio->gpio.get_direction = tegra186_gpio_get_direction;
891 gpio->gpio.direction_input = tegra186_gpio_direction_input;
892 gpio->gpio.direction_output = tegra186_gpio_direction_output;
893 gpio->gpio.get = tegra186_gpio_get;
894 gpio->gpio.set_rv = tegra186_gpio_set;
895 gpio->gpio.set_config = tegra186_gpio_set_config;
896 gpio->gpio.add_pin_ranges = tegra186_gpio_add_pin_ranges;
897 gpio->gpio.init_valid_mask = tegra186_init_valid_mask;
898 if (gpio->soc->has_gte) {
899 gpio->gpio.en_hw_timestamp = tegra186_gpio_en_hw_ts;
900 gpio->gpio.dis_hw_timestamp = tegra186_gpio_dis_hw_ts;
901 }
902
903 gpio->gpio.base = -1;
904
905 for (i = 0; i < gpio->soc->num_ports; i++)
906 gpio->gpio.ngpio += gpio->soc->ports[i].pins;
907
908 names = devm_kcalloc(gpio->gpio.parent, gpio->gpio.ngpio,
909 sizeof(*names), GFP_KERNEL);
910 if (!names)
911 return -ENOMEM;
912
913 for (i = 0, offset = 0; i < gpio->soc->num_ports; i++) {
914 const struct tegra_gpio_port *port = &gpio->soc->ports[i];
915 char *name;
916
917 for (j = 0; j < port->pins; j++) {
918 name = devm_kasprintf(gpio->gpio.parent, GFP_KERNEL,
919 "P%s.%02x", port->name, j);
920 if (!name)
921 return -ENOMEM;
922
923 names[offset + j] = name;
924 }
925
926 offset += port->pins;
927 }
928
929 gpio->gpio.names = (const char * const *)names;
930
931 #if defined(CONFIG_OF_GPIO)
932 gpio->gpio.of_gpio_n_cells = 2;
933 gpio->gpio.of_xlate = tegra186_gpio_of_xlate;
934 #endif /* CONFIG_OF_GPIO */
935
936 irq = &gpio->gpio.irq;
937 gpio_irq_chip_set_chip(irq, &tegra186_gpio_irq_chip);
938 irq->fwnode = dev_fwnode(&pdev->dev);
939 irq->child_to_parent_hwirq = tegra186_gpio_child_to_parent_hwirq;
940 irq->populate_parent_alloc_arg = tegra186_gpio_populate_parent_fwspec;
941 irq->child_offset_to_irq = tegra186_gpio_child_offset_to_irq;
942 irq->child_irq_domain_ops.translate = tegra186_gpio_irq_domain_translate;
943 irq->handler = handle_simple_irq;
944 irq->default_type = IRQ_TYPE_NONE;
945 irq->parent_handler = tegra186_gpio_irq;
946 irq->parent_handler_data = gpio;
947 irq->num_parents = gpio->num_irq;
948
949 /*
950 * To simplify things, use a single interrupt per bank for now. Some
951 * chips support up to 8 interrupts per bank, which can be useful to
952 * distribute the load and decrease the processing latency for GPIOs
953 * but it also requires a more complicated interrupt routing than we
954 * currently program.
955 */
956 if (gpio->num_irqs_per_bank > 1) {
957 irq->parents = devm_kcalloc(&pdev->dev, gpio->num_banks,
958 sizeof(*irq->parents), GFP_KERNEL);
959 if (!irq->parents)
960 return -ENOMEM;
961
962 for (i = 0; i < gpio->num_banks; i++)
963 irq->parents[i] = gpio->irq[i * gpio->num_irqs_per_bank];
964
965 irq->num_parents = gpio->num_banks;
966 } else {
967 irq->num_parents = gpio->num_irq;
968 irq->parents = gpio->irq;
969 }
970
971 if (gpio->soc->num_irqs_per_bank > 1)
972 tegra186_gpio_init_route_mapping(gpio);
973
974 np = of_find_matching_node(NULL, tegra186_pmc_of_match);
975 if (np) {
976 if (of_device_is_available(np)) {
977 irq->parent_domain = irq_find_host(np);
978 of_node_put(np);
979
980 if (!irq->parent_domain)
981 return -EPROBE_DEFER;
982 } else {
983 of_node_put(np);
984 }
985 }
986
987 irq->map = devm_kcalloc(&pdev->dev, gpio->gpio.ngpio,
988 sizeof(*irq->map), GFP_KERNEL);
989 if (!irq->map)
990 return -ENOMEM;
991
992 for (i = 0, offset = 0; i < gpio->soc->num_ports; i++) {
993 const struct tegra_gpio_port *port = &gpio->soc->ports[i];
994
995 for (j = 0; j < port->pins; j++)
996 irq->map[offset + j] = irq->parents[port->bank];
997
998 offset += port->pins;
999 }
1000
1001 return devm_gpiochip_add_data(&pdev->dev, &gpio->gpio, gpio);
1002 }
1003
1004 #define TEGRA186_MAIN_GPIO_PORT(_name, _bank, _port, _pins) \
1005 [TEGRA186_MAIN_GPIO_PORT_##_name] = { \
1006 .name = #_name, \
1007 .bank = _bank, \
1008 .port = _port, \
1009 .pins = _pins, \
1010 }
1011
1012 static const struct tegra_gpio_port tegra186_main_ports[] = {
1013 TEGRA186_MAIN_GPIO_PORT( A, 2, 0, 7),
1014 TEGRA186_MAIN_GPIO_PORT( B, 3, 0, 7),
1015 TEGRA186_MAIN_GPIO_PORT( C, 3, 1, 7),
1016 TEGRA186_MAIN_GPIO_PORT( D, 3, 2, 6),
1017 TEGRA186_MAIN_GPIO_PORT( E, 2, 1, 8),
1018 TEGRA186_MAIN_GPIO_PORT( F, 2, 2, 6),
1019 TEGRA186_MAIN_GPIO_PORT( G, 4, 1, 6),
1020 TEGRA186_MAIN_GPIO_PORT( H, 1, 0, 7),
1021 TEGRA186_MAIN_GPIO_PORT( I, 0, 4, 8),
1022 TEGRA186_MAIN_GPIO_PORT( J, 5, 0, 8),
1023 TEGRA186_MAIN_GPIO_PORT( K, 5, 1, 1),
1024 TEGRA186_MAIN_GPIO_PORT( L, 1, 1, 8),
1025 TEGRA186_MAIN_GPIO_PORT( M, 5, 3, 6),
1026 TEGRA186_MAIN_GPIO_PORT( N, 0, 0, 7),
1027 TEGRA186_MAIN_GPIO_PORT( O, 0, 1, 4),
1028 TEGRA186_MAIN_GPIO_PORT( P, 4, 0, 7),
1029 TEGRA186_MAIN_GPIO_PORT( Q, 0, 2, 6),
1030 TEGRA186_MAIN_GPIO_PORT( R, 0, 5, 6),
1031 TEGRA186_MAIN_GPIO_PORT( T, 0, 3, 4),
1032 TEGRA186_MAIN_GPIO_PORT( X, 1, 2, 8),
1033 TEGRA186_MAIN_GPIO_PORT( Y, 1, 3, 7),
1034 TEGRA186_MAIN_GPIO_PORT(BB, 2, 3, 2),
1035 TEGRA186_MAIN_GPIO_PORT(CC, 5, 2, 4),
1036 };
1037
1038 static const struct tegra_gpio_soc tegra186_main_soc = {
1039 .num_ports = ARRAY_SIZE(tegra186_main_ports),
1040 .ports = tegra186_main_ports,
1041 .name = "tegra186-gpio",
1042 .instance = 0,
1043 .num_irqs_per_bank = 1,
1044 .has_vm_support = false,
1045 };
1046
1047 #define TEGRA186_AON_GPIO_PORT(_name, _bank, _port, _pins) \
1048 [TEGRA186_AON_GPIO_PORT_##_name] = { \
1049 .name = #_name, \
1050 .bank = _bank, \
1051 .port = _port, \
1052 .pins = _pins, \
1053 }
1054
1055 static const struct tegra_gpio_port tegra186_aon_ports[] = {
1056 TEGRA186_AON_GPIO_PORT( S, 0, 1, 5),
1057 TEGRA186_AON_GPIO_PORT( U, 0, 2, 6),
1058 TEGRA186_AON_GPIO_PORT( V, 0, 4, 8),
1059 TEGRA186_AON_GPIO_PORT( W, 0, 5, 8),
1060 TEGRA186_AON_GPIO_PORT( Z, 0, 7, 4),
1061 TEGRA186_AON_GPIO_PORT(AA, 0, 6, 8),
1062 TEGRA186_AON_GPIO_PORT(EE, 0, 3, 3),
1063 TEGRA186_AON_GPIO_PORT(FF, 0, 0, 5),
1064 };
1065
1066 static const struct tegra_gpio_soc tegra186_aon_soc = {
1067 .num_ports = ARRAY_SIZE(tegra186_aon_ports),
1068 .ports = tegra186_aon_ports,
1069 .name = "tegra186-gpio-aon",
1070 .instance = 1,
1071 .num_irqs_per_bank = 1,
1072 .has_vm_support = false,
1073 };
1074
1075 #define TEGRA194_MAIN_GPIO_PORT(_name, _bank, _port, _pins) \
1076 [TEGRA194_MAIN_GPIO_PORT_##_name] = { \
1077 .name = #_name, \
1078 .bank = _bank, \
1079 .port = _port, \
1080 .pins = _pins, \
1081 }
1082
1083 static const struct tegra_gpio_port tegra194_main_ports[] = {
1084 TEGRA194_MAIN_GPIO_PORT( A, 1, 2, 8),
1085 TEGRA194_MAIN_GPIO_PORT( B, 4, 7, 2),
1086 TEGRA194_MAIN_GPIO_PORT( C, 4, 3, 8),
1087 TEGRA194_MAIN_GPIO_PORT( D, 4, 4, 4),
1088 TEGRA194_MAIN_GPIO_PORT( E, 4, 5, 8),
1089 TEGRA194_MAIN_GPIO_PORT( F, 4, 6, 6),
1090 TEGRA194_MAIN_GPIO_PORT( G, 4, 0, 8),
1091 TEGRA194_MAIN_GPIO_PORT( H, 4, 1, 8),
1092 TEGRA194_MAIN_GPIO_PORT( I, 4, 2, 5),
1093 TEGRA194_MAIN_GPIO_PORT( J, 5, 1, 6),
1094 TEGRA194_MAIN_GPIO_PORT( K, 3, 0, 8),
1095 TEGRA194_MAIN_GPIO_PORT( L, 3, 1, 4),
1096 TEGRA194_MAIN_GPIO_PORT( M, 2, 3, 8),
1097 TEGRA194_MAIN_GPIO_PORT( N, 2, 4, 3),
1098 TEGRA194_MAIN_GPIO_PORT( O, 5, 0, 6),
1099 TEGRA194_MAIN_GPIO_PORT( P, 2, 5, 8),
1100 TEGRA194_MAIN_GPIO_PORT( Q, 2, 6, 8),
1101 TEGRA194_MAIN_GPIO_PORT( R, 2, 7, 6),
1102 TEGRA194_MAIN_GPIO_PORT( S, 3, 3, 8),
1103 TEGRA194_MAIN_GPIO_PORT( T, 3, 4, 8),
1104 TEGRA194_MAIN_GPIO_PORT( U, 3, 5, 1),
1105 TEGRA194_MAIN_GPIO_PORT( V, 1, 0, 8),
1106 TEGRA194_MAIN_GPIO_PORT( W, 1, 1, 2),
1107 TEGRA194_MAIN_GPIO_PORT( X, 2, 0, 8),
1108 TEGRA194_MAIN_GPIO_PORT( Y, 2, 1, 8),
1109 TEGRA194_MAIN_GPIO_PORT( Z, 2, 2, 8),
1110 TEGRA194_MAIN_GPIO_PORT(FF, 3, 2, 2),
1111 TEGRA194_MAIN_GPIO_PORT(GG, 0, 0, 2)
1112 };
1113
1114 static const struct tegra186_pin_range tegra194_main_pin_ranges[] = {
1115 { TEGRA194_MAIN_GPIO(GG, 0), "pex_l5_clkreq_n_pgg0" },
1116 { TEGRA194_MAIN_GPIO(GG, 1), "pex_l5_rst_n_pgg1" },
1117 };
1118
1119 static const struct tegra_gpio_soc tegra194_main_soc = {
1120 .num_ports = ARRAY_SIZE(tegra194_main_ports),
1121 .ports = tegra194_main_ports,
1122 .name = "tegra194-gpio",
1123 .instance = 0,
1124 .num_irqs_per_bank = 8,
1125 .num_pin_ranges = ARRAY_SIZE(tegra194_main_pin_ranges),
1126 .pin_ranges = tegra194_main_pin_ranges,
1127 .pinmux = "nvidia,tegra194-pinmux",
1128 .has_vm_support = true,
1129 };
1130
1131 #define TEGRA194_AON_GPIO_PORT(_name, _bank, _port, _pins) \
1132 [TEGRA194_AON_GPIO_PORT_##_name] = { \
1133 .name = #_name, \
1134 .bank = _bank, \
1135 .port = _port, \
1136 .pins = _pins, \
1137 }
1138
1139 static const struct tegra_gpio_port tegra194_aon_ports[] = {
1140 TEGRA194_AON_GPIO_PORT(AA, 0, 3, 8),
1141 TEGRA194_AON_GPIO_PORT(BB, 0, 4, 4),
1142 TEGRA194_AON_GPIO_PORT(CC, 0, 1, 8),
1143 TEGRA194_AON_GPIO_PORT(DD, 0, 2, 3),
1144 TEGRA194_AON_GPIO_PORT(EE, 0, 0, 7)
1145 };
1146
1147 static const struct tegra_gpio_soc tegra194_aon_soc = {
1148 .num_ports = ARRAY_SIZE(tegra194_aon_ports),
1149 .ports = tegra194_aon_ports,
1150 .name = "tegra194-gpio-aon",
1151 .instance = 1,
1152 .num_irqs_per_bank = 8,
1153 .has_gte = true,
1154 .has_vm_support = false,
1155 };
1156
1157 #define TEGRA234_MAIN_GPIO_PORT(_name, _bank, _port, _pins) \
1158 [TEGRA234_MAIN_GPIO_PORT_##_name] = { \
1159 .name = #_name, \
1160 .bank = _bank, \
1161 .port = _port, \
1162 .pins = _pins, \
1163 }
1164
1165 static const struct tegra_gpio_port tegra234_main_ports[] = {
1166 TEGRA234_MAIN_GPIO_PORT( A, 0, 0, 8),
1167 TEGRA234_MAIN_GPIO_PORT( B, 0, 3, 1),
1168 TEGRA234_MAIN_GPIO_PORT( C, 5, 1, 8),
1169 TEGRA234_MAIN_GPIO_PORT( D, 5, 2, 4),
1170 TEGRA234_MAIN_GPIO_PORT( E, 5, 3, 8),
1171 TEGRA234_MAIN_GPIO_PORT( F, 5, 4, 6),
1172 TEGRA234_MAIN_GPIO_PORT( G, 4, 0, 8),
1173 TEGRA234_MAIN_GPIO_PORT( H, 4, 1, 8),
1174 TEGRA234_MAIN_GPIO_PORT( I, 4, 2, 7),
1175 TEGRA234_MAIN_GPIO_PORT( J, 5, 0, 6),
1176 TEGRA234_MAIN_GPIO_PORT( K, 3, 0, 8),
1177 TEGRA234_MAIN_GPIO_PORT( L, 3, 1, 4),
1178 TEGRA234_MAIN_GPIO_PORT( M, 2, 0, 8),
1179 TEGRA234_MAIN_GPIO_PORT( N, 2, 1, 8),
1180 TEGRA234_MAIN_GPIO_PORT( P, 2, 2, 8),
1181 TEGRA234_MAIN_GPIO_PORT( Q, 2, 3, 8),
1182 TEGRA234_MAIN_GPIO_PORT( R, 2, 4, 6),
1183 TEGRA234_MAIN_GPIO_PORT( X, 1, 0, 8),
1184 TEGRA234_MAIN_GPIO_PORT( Y, 1, 1, 8),
1185 TEGRA234_MAIN_GPIO_PORT( Z, 1, 2, 8),
1186 TEGRA234_MAIN_GPIO_PORT(AC, 0, 1, 8),
1187 TEGRA234_MAIN_GPIO_PORT(AD, 0, 2, 4),
1188 TEGRA234_MAIN_GPIO_PORT(AE, 3, 3, 2),
1189 TEGRA234_MAIN_GPIO_PORT(AF, 3, 4, 4),
1190 TEGRA234_MAIN_GPIO_PORT(AG, 3, 2, 8),
1191 };
1192
1193 static const struct tegra_gpio_soc tegra234_main_soc = {
1194 .num_ports = ARRAY_SIZE(tegra234_main_ports),
1195 .ports = tegra234_main_ports,
1196 .name = "tegra234-gpio",
1197 .instance = 0,
1198 .num_irqs_per_bank = 8,
1199 .has_vm_support = true,
1200 };
1201
1202 #define TEGRA234_AON_GPIO_PORT(_name, _bank, _port, _pins) \
1203 [TEGRA234_AON_GPIO_PORT_##_name] = { \
1204 .name = #_name, \
1205 .bank = _bank, \
1206 .port = _port, \
1207 .pins = _pins, \
1208 }
1209
1210 static const struct tegra_gpio_port tegra234_aon_ports[] = {
1211 TEGRA234_AON_GPIO_PORT(AA, 0, 4, 8),
1212 TEGRA234_AON_GPIO_PORT(BB, 0, 5, 4),
1213 TEGRA234_AON_GPIO_PORT(CC, 0, 2, 8),
1214 TEGRA234_AON_GPIO_PORT(DD, 0, 3, 3),
1215 TEGRA234_AON_GPIO_PORT(EE, 0, 0, 8),
1216 TEGRA234_AON_GPIO_PORT(GG, 0, 1, 1),
1217 };
1218
1219 static const struct tegra_gpio_soc tegra234_aon_soc = {
1220 .num_ports = ARRAY_SIZE(tegra234_aon_ports),
1221 .ports = tegra234_aon_ports,
1222 .name = "tegra234-gpio-aon",
1223 .instance = 1,
1224 .num_irqs_per_bank = 8,
1225 .has_gte = true,
1226 .has_vm_support = false,
1227 };
1228
1229 #define TEGRA241_MAIN_GPIO_PORT(_name, _bank, _port, _pins) \
1230 [TEGRA241_MAIN_GPIO_PORT_##_name] = { \
1231 .name = #_name, \
1232 .bank = _bank, \
1233 .port = _port, \
1234 .pins = _pins, \
1235 }
1236
1237 static const struct tegra_gpio_port tegra241_main_ports[] = {
1238 TEGRA241_MAIN_GPIO_PORT(A, 0, 0, 8),
1239 TEGRA241_MAIN_GPIO_PORT(B, 0, 1, 8),
1240 TEGRA241_MAIN_GPIO_PORT(C, 0, 2, 2),
1241 TEGRA241_MAIN_GPIO_PORT(D, 0, 3, 6),
1242 TEGRA241_MAIN_GPIO_PORT(E, 0, 4, 8),
1243 TEGRA241_MAIN_GPIO_PORT(F, 1, 0, 8),
1244 TEGRA241_MAIN_GPIO_PORT(G, 1, 1, 8),
1245 TEGRA241_MAIN_GPIO_PORT(H, 1, 2, 8),
1246 TEGRA241_MAIN_GPIO_PORT(J, 1, 3, 8),
1247 TEGRA241_MAIN_GPIO_PORT(K, 1, 4, 4),
1248 TEGRA241_MAIN_GPIO_PORT(L, 1, 5, 6),
1249 };
1250
1251 static const struct tegra_gpio_soc tegra241_main_soc = {
1252 .num_ports = ARRAY_SIZE(tegra241_main_ports),
1253 .ports = tegra241_main_ports,
1254 .name = "tegra241-gpio",
1255 .instance = 0,
1256 .num_irqs_per_bank = 8,
1257 .has_vm_support = false,
1258 };
1259
1260 #define TEGRA241_AON_GPIO_PORT(_name, _bank, _port, _pins) \
1261 [TEGRA241_AON_GPIO_PORT_##_name] = { \
1262 .name = #_name, \
1263 .bank = _bank, \
1264 .port = _port, \
1265 .pins = _pins, \
1266 }
1267
1268 static const struct tegra_gpio_port tegra241_aon_ports[] = {
1269 TEGRA241_AON_GPIO_PORT(AA, 0, 0, 8),
1270 TEGRA241_AON_GPIO_PORT(BB, 0, 0, 4),
1271 };
1272
1273 static const struct tegra_gpio_soc tegra241_aon_soc = {
1274 .num_ports = ARRAY_SIZE(tegra241_aon_ports),
1275 .ports = tegra241_aon_ports,
1276 .name = "tegra241-gpio-aon",
1277 .instance = 1,
1278 .num_irqs_per_bank = 8,
1279 .has_vm_support = false,
1280 };
1281
1282 static const struct of_device_id tegra186_gpio_of_match[] = {
1283 {
1284 .compatible = "nvidia,tegra186-gpio",
1285 .data = &tegra186_main_soc
1286 }, {
1287 .compatible = "nvidia,tegra186-gpio-aon",
1288 .data = &tegra186_aon_soc
1289 }, {
1290 .compatible = "nvidia,tegra194-gpio",
1291 .data = &tegra194_main_soc
1292 }, {
1293 .compatible = "nvidia,tegra194-gpio-aon",
1294 .data = &tegra194_aon_soc
1295 }, {
1296 .compatible = "nvidia,tegra234-gpio",
1297 .data = &tegra234_main_soc
1298 }, {
1299 .compatible = "nvidia,tegra234-gpio-aon",
1300 .data = &tegra234_aon_soc
1301 }, {
1302 /* sentinel */
1303 }
1304 };
1305 MODULE_DEVICE_TABLE(of, tegra186_gpio_of_match);
1306
1307 static const struct acpi_device_id tegra186_gpio_acpi_match[] = {
1308 { .id = "NVDA0108", .driver_data = (kernel_ulong_t)&tegra186_main_soc },
1309 { .id = "NVDA0208", .driver_data = (kernel_ulong_t)&tegra186_aon_soc },
1310 { .id = "NVDA0308", .driver_data = (kernel_ulong_t)&tegra194_main_soc },
1311 { .id = "NVDA0408", .driver_data = (kernel_ulong_t)&tegra194_aon_soc },
1312 { .id = "NVDA0508", .driver_data = (kernel_ulong_t)&tegra241_main_soc },
1313 { .id = "NVDA0608", .driver_data = (kernel_ulong_t)&tegra241_aon_soc },
1314 {}
1315 };
1316 MODULE_DEVICE_TABLE(acpi, tegra186_gpio_acpi_match);
1317
1318 static struct platform_driver tegra186_gpio_driver = {
1319 .driver = {
1320 .name = "tegra186-gpio",
1321 .of_match_table = tegra186_gpio_of_match,
1322 .acpi_match_table = tegra186_gpio_acpi_match,
1323 },
1324 .probe = tegra186_gpio_probe,
1325 };
1326 module_platform_driver(tegra186_gpio_driver);
1327
1328 MODULE_DESCRIPTION("NVIDIA Tegra186 GPIO controller driver");
1329 MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>");
1330 MODULE_LICENSE("GPL v2");
1331