1 /* 2 * This file and its contents are supplied under the terms of the 3 * Common Development and Distribution License ("CDDL"), version 1.0. 4 * You may only use this file in accordance with the terms of version 5 * 1.0 of the CDDL. 6 * 7 * A full copy of the text of the CDDL should have accompanied this 8 * source. A copy of the CDDL is also available via the Internet at 9 * http://www.illumos.org/license/CDDL. 10 */ 11 12 /* 13 * Copyright 2015 OmniTI Computer Consulting, Inc. All rights reserved. 14 * Copyright 2019 Joyent, Inc. 15 * Copyright 2017 Tegile Systems, Inc. All rights reserved. 16 * Copyright 2020 Ryan Zezeski 17 * Copyright 2026 RackTop Systems, Inc. 18 */ 19 20 /* 21 * Please see i40e_main.c for an introduction to the device driver, its layout, 22 * and more. 23 */ 24 25 #ifndef _I40E_SW_H 26 #define _I40E_SW_H 27 28 #ifdef __cplusplus 29 extern "C" { 30 #endif 31 32 #include <sys/types.h> 33 #include <sys/conf.h> 34 #include <sys/debug.h> 35 #include <sys/stropts.h> 36 #include <sys/stream.h> 37 #include <sys/strsun.h> 38 #include <sys/strlog.h> 39 #include <sys/kmem.h> 40 #include <sys/stat.h> 41 #include <sys/kstat.h> 42 #include <sys/modctl.h> 43 #include <sys/errno.h> 44 #include <sys/dlpi.h> 45 #include <sys/mac_provider.h> 46 #include <sys/mac_ether.h> 47 #include <sys/vlan.h> 48 #include <sys/ddi.h> 49 #include <sys/sunddi.h> 50 #include <sys/pci.h> 51 #include <sys/pcie.h> 52 #include <sys/sdt.h> 53 #include <sys/ethernet.h> 54 #include <sys/pattr.h> 55 #include <sys/strsubr.h> 56 #include <sys/netlb.h> 57 #include <sys/random.h> 58 #include <inet/common.h> 59 #include <inet/tcp.h> 60 #include <inet/ip.h> 61 #include <inet/mi.h> 62 #include <inet/nd.h> 63 #include <netinet/udp.h> 64 #include <netinet/sctp.h> 65 #include <sys/bitmap.h> 66 #include <sys/cpuvar.h> 67 #include <sys/ddifm.h> 68 #include <sys/fm/protocol.h> 69 #include <sys/fm/util.h> 70 #include <sys/disp.h> 71 #include <sys/fm/io/ddi.h> 72 #include <sys/list.h> 73 #include <sys/debug.h> 74 #include <sys/sdt.h> 75 #include <sys/ddi_ufm.h> 76 #include "i40e_type.h" 77 #include "i40e_osdep.h" 78 #include "i40e_prototype.h" 79 #include "i40e_xregs.h" 80 81 #define I40E_MODULE_NAME "i40e" 82 83 #define I40E_ADAPTER_REGSET 1 84 85 /* 86 * Configuration constants. Note that the hardware defines a minimum bound of 32 87 * descriptors and requires that the programming of the descriptor lengths be 88 * aligned in units of 32 descriptors. 89 */ 90 #define I40E_MIN_TX_RING_SIZE 64 91 #define I40E_MAX_TX_RING_SIZE 4096 92 #define I40E_DEF_TX_RING_SIZE 1024 93 94 /* 95 * Place an artificial limit on the max number of groups. The X710 96 * series supports up to 384 VSIs to be partitioned across PFs as the 97 * driver sees fit. But until we support more interrupts this seems 98 * like a good place to start. 99 */ 100 #define I40E_MIN_NUM_RX_GROUPS 1 101 #define I40E_MAX_NUM_RX_GROUPS 32 102 #define I40E_DEF_NUM_RX_GROUPS 16 103 104 #define I40E_MIN_RX_RING_SIZE 64 105 #define I40E_MAX_RX_RING_SIZE 4096 106 #define I40E_DEF_RX_RING_SIZE 1024 107 108 #define I40E_DESC_ALIGN 32 109 110 /* 111 * Sizes used for asynchronous processing of the adminq. We allocate a fixed 112 * size buffer for each instance of the device during attach time, rather than 113 * allocating and freeing one during interrupt processing. 114 * 115 * We also define the descriptor size of the admin queue here. 116 */ 117 #define I40E_ADMINQ_BUFSZ 4096 118 #define I40E_MAX_ADMINQ_SIZE 1024 119 #define I40E_DEF_ADMINQ_SIZE 256 120 121 /* 122 * Note, while the min and maximum values are based upon the sizing of the ring 123 * itself, the default is taken from ixgbe without much thought. It's basically 124 * been cargo culted. See i40e_transceiver.c for a bit more information. 125 */ 126 #define I40E_MIN_RX_LIMIT_PER_INTR 16 127 #define I40E_MAX_RX_LIMIT_PER_INTR 4096 128 #define I40E_DEF_RX_LIMIT_PER_INTR 256 129 130 /* 131 * Valid MTU ranges. Note that the XL710's maximum payload is actually 9728. 132 * However, we need to adjust for the ETHERFCSL (4 bytes) and the Ethernet VLAN 133 * header size (18 bytes) to get the actual maximum frame we can use. If 134 * different adapters end up with different sizes, we should make this value a 135 * bit more dynamic. 136 */ 137 #define I40E_MAX_MTU 9706 138 #define I40E_MIN_MTU ETHERMIN 139 #define I40E_DEF_MTU ETHERMTU 140 141 /* 142 * This is somewhat buried, but in section 8.4.2.2.1 of the I40E datasheet 143 * (revision 3.9), the table that lists the Segmentation Parameters (it's 144 * formatted a bit poorly) in the MSS / TARGET_VSI row, it states that the 145 * MSS value should be no smaller than 64. Real world experience shows using 146 * a smaller number will stop the ring from processing packets. 147 */ 148 #define I40E_MIN_MSS 64 149 150 /* 151 * Interrupt throttling related values. Interrupt throttling values are defined 152 * in two microsecond increments. Note that a value of zero basically says do no 153 * ITR activity. A helpful way to think about these is that setting the ITR to a 154 * value will allow a certain number of interrupts per second. 155 * 156 * Our default values for RX allow 20k interrupts per second while our default 157 * values for TX allow for 5k interrupts per second. For other class interrupts, 158 * we limit ourselves to a rate of 2k/s. 159 */ 160 #define I40E_MIN_ITR 0x0000 161 #define I40E_MAX_ITR 0x0FF0 162 #define I40E_DEF_RX_ITR 0x0019 163 #define I40E_DEF_TX_ITR 0x0064 164 #define I40E_DEF_OTHER_ITR 0x00FA 165 166 /* 167 * Indexes into the three ITR registers that we have. 168 */ 169 typedef enum i40e_itr_index { 170 I40E_ITR_INDEX_RX = 0x0, 171 I40E_ITR_INDEX_TX = 0x1, 172 I40E_ITR_INDEX_OTHER = 0x2, 173 I40E_ITR_INDEX_NONE = 0x3 174 } i40e_itr_index_t; 175 176 /* 177 * The hardware claims to support LSO up to 256 KB, but due to the limitations 178 * imposed by the IP header for non-jumbo frames, we cap it at 64 KB. 179 */ 180 #define I40E_LSO_MAXLEN (64 * 1024) 181 182 #define I40E_CYCLIC_PERIOD NANOSEC /* 1 second */ 183 #define I40E_DRAIN_RX_WAIT (500 * MILLISEC) /* In us */ 184 185 /* 186 * All the other queue types for are defined by the common code. However, this 187 * is the constant to indicate that it's terminated. 188 */ 189 #define I40E_QUEUE_TYPE_EOL 0x7FF 190 191 /* 192 * See the comments in i40e_transceiver.c as to the purpose of this value and 193 * how it's used to ensure that the IP header is eventually aligned when it's 194 * received by the OS. 195 */ 196 #define I40E_BUF_IPHDR_ALIGNMENT 2 197 198 /* 199 * The XL710 controller has a total of eight buffers available for the 200 * transmission of any single frame. This is defined in 8.4.1 - Transmit 201 * Packet in System Memory. 202 */ 203 #define I40E_TX_MAX_COOKIE 8 204 205 /* 206 * An LSO frame can be as large as 64KB, so we allow a DMA bind to span more 207 * cookies than a non-LSO frame. The key here to is to select a value such 208 * that once the HW has chunked up the LSO frame into MSS-sized segments that no 209 * single segment spans more than 8 cookies (see comments for 210 * I40E_TX_MAX_COOKIE) 211 */ 212 #define I40E_TX_LSO_MAX_COOKIE 32 213 214 /* 215 * Sizing to determine the amount of available descriptors at which we'll 216 * consider ourselves blocked. Also, when we have these available, we'll then 217 * consider ourselves available to transmit to MAC again. Strictly speaking, the 218 * MAX is based on the ring size. The default sizing is based on ixgbe. 219 */ 220 #define I40E_MIN_TX_BLOCK_THRESH I40E_TX_MAX_COOKIE 221 #define I40E_DEF_TX_BLOCK_THRESH I40E_MIN_TX_BLOCK_THRESH 222 223 /* 224 * Sizing for DMA thresholds. These are used to indicate whether or not we 225 * should perform a bcopy or a DMA binding of a given message block. The range 226 * allows for setting things such that we'll always do a bcopy (a high value) or 227 * always perform a DMA binding (a low value). 228 */ 229 #define I40E_MIN_RX_DMA_THRESH 0 230 #define I40E_DEF_RX_DMA_THRESH 256 231 #define I40E_MAX_RX_DMA_THRESH INT32_MAX 232 233 #define I40E_MIN_TX_DMA_THRESH 0 234 #define I40E_DEF_TX_DMA_THRESH 256 235 #define I40E_MAX_TX_DMA_THRESH INT32_MAX 236 237 /* 238 * The max size of each individual tx buffer is 16KB - 1. 239 * See table 8-17 240 */ 241 #define I40E_MAX_TX_BUFSZ 0x0000000000003FFFull 242 243 /* 244 * Resource sizing counts. There are various aspects of hardware where we may 245 * have some variable number of elements that we need to handle. Such as the 246 * hardware capabilities and switch capacities. We cannot know a priori how many 247 * elements to do, so instead we take a starting guess and then will grow it up 248 * to an upper bound on a number of elements, to limit memory consumption in 249 * case of a hardware bug. 250 */ 251 #define I40E_HW_CAP_DEFAULT 40 252 #define I40E_SWITCH_CAP_DEFAULT 25 253 254 /* 255 * Host Memory Context related constants. 256 */ 257 #define I40E_HMC_RX_CTX_UNIT 128 258 #define I40E_HMC_RX_DBUFF_MIN 1024 259 #define I40E_HMC_RX_DBUFF_MAX (16 * 1024 - 128) 260 #define I40E_HMC_RX_DTYPE_NOSPLIT 0 261 #define I40E_HMC_RX_DSIZE_32BYTE 1 262 #define I40E_HMC_RX_CRCSTRIP_ENABLE 1 263 #define I40E_HMC_RX_FC_DISABLE 0 264 #define I40E_HMC_RX_L2TAGORDER 1 265 #define I40E_HMC_RX_HDRSPLIT_DISABLE 0 266 #define I40E_HMC_RX_INVLAN_DONTSTRIP 0 267 #define I40E_HMC_RX_TPH_DISABLE 0 268 #define I40E_HMC_RX_LOWRXQ_NOINTR 0 269 #define I40E_HMC_RX_PREFENA 1 270 271 #define I40E_HMC_TX_CTX_UNIT 128 272 #define I40E_HMC_TX_NEW_CONTEXT 1 273 #define I40E_HMC_TX_FC_DISABLE 0 274 #define I40E_HMC_TX_TS_DISABLE 0 275 #define I40E_HMC_TX_FD_DISABLE 0 276 #define I40E_HMC_TX_ALT_VLAN_DISABLE 0 277 #define I40E_HMC_TX_WB_ENABLE 1 278 #define I40E_HMC_TX_TPH_DISABLE 0 279 280 /* 281 * This defines the error mask that we care about from rx descriptors. Currently 282 * we're only concerned with the general errors and oversize errors. 283 */ 284 #define I40E_RX_ERR_BITS ((1 << I40E_RX_DESC_ERROR_RXE_SHIFT) | \ 285 (1 << I40E_RX_DESC_ERROR_OVERSIZE_SHIFT)) 286 287 /* 288 * Property sizing macros for firmware versions, etc. They need to be large 289 * enough to hold 32-bit quantities transformed to strings as %d.%d or %x. 290 */ 291 #define I40E_DDI_PROP_LEN 64 292 293 #define I40E_GROUP_NOMSIX 1 294 #define I40E_TRQPAIR_NOMSIX 1 295 296 /* 297 * It seems reasonable to cast this to void because the only reason that we 298 * should be getting a DDI_FAILURE is due to the fact that we specify addresses 299 * out of range. Because we specify no offset or address, it shouldn't happen. 300 */ 301 #ifdef DEBUG 302 #define I40E_DMA_SYNC(handle, flag) ASSERT0(ddi_dma_sync( \ 303 (handle)->dmab_dma_handle, 0, 0, \ 304 (flag))) 305 #else /* !DEBUG */ 306 #define I40E_DMA_SYNC(handle, flag) ((void) ddi_dma_sync( \ 307 (handle)->dmab_dma_handle, 0, 0, \ 308 (flag))) 309 #endif /* DEBUG */ 310 311 /* 312 * Constants related to ring startup and teardown. These refer to the amount of 313 * time that we're willing to wait for a ring to spin up and spin down. 314 */ 315 #define I40E_RING_WAIT_NTRIES 10 316 #define I40E_RING_WAIT_PAUSE 10 /* ms */ 317 #define I40E_RING_ENABLE_GAP 50 /* ms */ 318 319 /* 320 * Printed Board Assembly (PBA) length. These are derived from Table 6-2. 321 */ 322 #define I40E_PBANUM_LENGTH 12 323 #define I40E_PBANUM_STRLEN 13 324 325 /* 326 * Define the maximum number of queues for a traffic class. These values come 327 * from the 'Number and offset of queue pairs per TCs' section of the 'Add VSI 328 * Command Buffer' table. For the 710 controller family this is table 7-62 329 * (r2.5) and for the 722 this is table 38-216 (r2.0). 330 */ 331 #define I40E_710_MAX_TC_QUEUES 64 332 #define I40E_722_MAX_TC_QUEUES 128 333 334 /* 335 * Define the size of the HLUT table size. The HLUT table can either be 128 or 336 * 512 bytes. We always set the table size to be 512 bytes in i40e_chip_start(). 337 * Note, this should not be confused with the common code's macro 338 * I40E_HASH_LUT_SIZE_512 which is the bit pattern needed to tell the card to 339 * use a 512 byte HLUT. 340 */ 341 #define I40E_HLUT_TABLE_SIZE 512 342 343 /* 344 * Bit flags for attach_progress 345 */ 346 typedef enum i40e_attach_state { 347 I40E_ATTACH_PCI_CONFIG = 0x0001, /* PCI config setup */ 348 I40E_ATTACH_REGS_MAP = 0x0002, /* Registers mapped */ 349 I40E_ATTACH_PROPS = 0x0004, /* Properties initialized */ 350 I40E_ATTACH_ALLOC_INTR = 0x0008, /* Interrupts allocated */ 351 I40E_ATTACH_ALLOC_RINGSLOCKS = 0x0010, /* Rings & locks allocated */ 352 I40E_ATTACH_ADD_INTR = 0x0020, /* Intr handlers added */ 353 I40E_ATTACH_COMMON_CODE = 0x0040, /* Intel code initialized */ 354 I40E_ATTACH_INIT = 0x0080, /* Device initialized */ 355 I40E_ATTACH_STATS = 0x0200, /* Kstats created */ 356 I40E_ATTACH_MAC = 0x0800, /* MAC registered */ 357 I40E_ATTACH_ENABLE_INTR = 0x1000, /* DDI interrupts enabled */ 358 I40E_ATTACH_FM_INIT = 0x2000, /* FMA initialized */ 359 I40E_ATTACH_LINK_TIMER = 0x4000, /* link check timer */ 360 I40E_ATTACH_UFM_INIT = 0x8000, /* DDI UFM initialized */ 361 } i40e_attach_state_t; 362 363 364 /* 365 * State flags that what's going on in in the device. Some of these state flags 366 * indicate some aspirational work that needs to happen in the driver. 367 * 368 * I40E_UNKNOWN: The device has yet to be started. 369 * I40E_INITIALIZED: The device has been fully attached. 370 * I40E_STARTED: The device has come out of the GLDV3 start routine. 371 * I40E_SUSPENDED: The device is suspended and I/O among other things 372 * should not occur. This happens because of an actual 373 * DDI_SUSPEND or interrupt adjustments. 374 * I40E_STALL: The tx stall detection logic has found a stall. 375 * I40E_OVERTEMP: The device has encountered a temperature alarm. 376 * I40E_INTR_ADJUST: Our interrupts are being manipulated and therefore we 377 * shouldn't be manipulating their state. 378 * I40E_ERROR: We've detected an FM error and degraded the device. 379 */ 380 typedef enum i40e_state { 381 I40E_UNKNOWN = 0x00, 382 I40E_INITIALIZED = 0x01, 383 I40E_STARTED = 0x02, 384 I40E_SUSPENDED = 0x04, 385 I40E_STALL = 0x08, 386 I40E_OVERTEMP = 0x20, 387 I40E_INTR_ADJUST = 0x40, 388 I40E_ERROR = 0x80 389 } i40e_state_t; 390 391 392 /* 393 * Definitions for common Intel things that we use and some slightly more usable 394 * names. 395 */ 396 typedef struct i40e_hw i40e_hw_t; 397 typedef struct i40e_aqc_switch_resource_alloc_element_resp i40e_switch_rsrc_t; 398 399 /* 400 * Handles and addresses of DMA buffers. 401 */ 402 typedef struct i40e_dma_buffer { 403 caddr_t dmab_address; /* Virtual address */ 404 uint64_t dmab_dma_address; /* DMA (Hardware) address */ 405 ddi_acc_handle_t dmab_acc_handle; /* Data access handle */ 406 ddi_dma_handle_t dmab_dma_handle; /* DMA handle */ 407 size_t dmab_size; /* Buffer size */ 408 size_t dmab_len; /* Data length in the buffer */ 409 } i40e_dma_buffer_t; 410 411 /* 412 * RX Control Block 413 */ 414 typedef struct i40e_rx_control_block { 415 mblk_t *rcb_mp; 416 uint32_t rcb_ref; 417 i40e_dma_buffer_t rcb_dma; 418 frtn_t rcb_free_rtn; 419 struct i40e_rx_data *rcb_rxd; 420 } i40e_rx_control_block_t; 421 422 typedef enum { 423 I40E_TX_NONE, 424 I40E_TX_COPY, 425 I40E_TX_DMA, 426 I40E_TX_DESC, 427 } i40e_tx_type_t; 428 429 typedef struct i40e_tx_desc i40e_tx_desc_t; 430 typedef struct i40e_tx_context_desc i40e_tx_context_desc_t; 431 typedef union i40e_32byte_rx_desc i40e_rx_desc_t; 432 433 struct i40e_dma_bind_info { 434 caddr_t dbi_paddr; 435 size_t dbi_len; 436 }; 437 438 typedef struct i40e_tx_control_block { 439 struct i40e_tx_control_block *tcb_next; 440 mblk_t *tcb_mp; 441 i40e_tx_type_t tcb_type; 442 ddi_dma_handle_t tcb_dma_handle; 443 ddi_dma_handle_t tcb_lso_dma_handle; 444 i40e_dma_buffer_t tcb_dma; 445 struct i40e_dma_bind_info *tcb_bind_info; 446 uint_t tcb_bind_ncookies; 447 boolean_t tcb_used_lso; 448 } i40e_tx_control_block_t; 449 450 /* 451 * Receive ring data (used below). 452 */ 453 typedef struct i40e_rx_data { 454 struct i40e *rxd_i40e; 455 456 /* 457 * RX descriptor ring definitions 458 */ 459 i40e_dma_buffer_t rxd_desc_area; /* DMA buffer of rx desc ring */ 460 i40e_rx_desc_t *rxd_desc_ring; /* Rx desc ring */ 461 uint32_t rxd_desc_next; /* Index of next rx desc */ 462 463 /* 464 * RX control block list definitions 465 */ 466 kmutex_t rxd_free_lock; /* Lock to protect free data */ 467 i40e_rx_control_block_t *rxd_rcb_area; /* Array of control blocks */ 468 i40e_rx_control_block_t **rxd_work_list; /* Work list of rcbs */ 469 i40e_rx_control_block_t **rxd_free_list; /* Free list of rcbs */ 470 uint32_t rxd_rcb_free; /* Number of free rcbs */ 471 472 /* 473 * RX software ring settings 474 */ 475 uint32_t rxd_ring_size; /* Rx descriptor ring size */ 476 uint32_t rxd_free_list_size; /* Rx free list size */ 477 478 /* 479 * RX outstanding data. This is used to keep track of outstanding loaned 480 * descriptors after we've shut down receiving information. Note these 481 * are protected by the i40e_t`i40e_rx_pending_lock. 482 */ 483 uint32_t rxd_rcb_pending; 484 boolean_t rxd_shutdown; 485 } i40e_rx_data_t; 486 487 /* 488 * Structures for unicast and multicast addresses. Note that we keep the VSI id 489 * around for unicast addresses, since they may belong to different VSIs. 490 * However, since all multicast addresses belong to the default VSI, we don't 491 * duplicate that information. 492 */ 493 typedef struct i40e_uaddr { 494 uint8_t iua_mac[ETHERADDRL]; 495 int iua_vsi; 496 } i40e_uaddr_t; 497 498 typedef struct i40e_maddr { 499 uint8_t ima_mac[ETHERADDRL]; 500 } i40e_maddr_t; 501 502 /* 503 * Collection of RX statistics on a given queue. 504 */ 505 typedef struct i40e_rxq_stat { 506 /* 507 * The i40e hardware does not maintain statistics on a per-ring basis, 508 * only on a per-PF and per-VSI level. As such, to satisfy the GLDv3, we 509 * need to maintain our own stats for packets and bytes. 510 */ 511 kstat_named_t irxs_bytes; /* Bytes in on queue */ 512 kstat_named_t irxs_packets; /* Packets in on queue */ 513 514 /* 515 * The following set of stats cover non-checksum data path issues. 516 */ 517 kstat_named_t irxs_rx_desc_error; /* Error bit set on desc */ 518 kstat_named_t irxs_rx_copy_nomem; /* allocb failure for copy */ 519 kstat_named_t irxs_rx_intr_limit; /* Hit i40e_rx_limit_per_intr */ 520 kstat_named_t irxs_rx_bind_norcb; /* No replacement rcb free */ 521 kstat_named_t irxs_rx_bind_nomp; /* No mblk_t in bind rcb */ 522 523 /* 524 * The following set of statistics covers rx checksum related activity. 525 * These are all primarily set in i40e_rx_hcksum. If rx checksum 526 * activity is disabled, then these should all be zero. 527 */ 528 kstat_named_t irxs_hck_v4hdrok; /* Valid IPv4 Header */ 529 kstat_named_t irxs_hck_l4hdrok; /* Valid L4 Header */ 530 kstat_named_t irxs_hck_unknown; /* !pinfo.known */ 531 kstat_named_t irxs_hck_nol3l4p; /* Missing L3L4P bit in desc */ 532 kstat_named_t irxs_hck_iperr; /* IPE error bit set */ 533 kstat_named_t irxs_hck_eiperr; /* EIPE error bit set */ 534 kstat_named_t irxs_hck_l4err; /* L4E error bit set */ 535 kstat_named_t irxs_hck_v6skip; /* IPv6 case hw fails on */ 536 kstat_named_t irxs_hck_set; /* Total times we set cksum */ 537 kstat_named_t irxs_hck_miss; /* Times with zero cksum bits */ 538 } i40e_rxq_stat_t; 539 540 /* 541 * Collection of TX Statistics on a given queue 542 */ 543 typedef struct i40e_txq_stat { 544 kstat_named_t itxs_bytes; /* Bytes out on queue */ 545 kstat_named_t itxs_packets; /* Packets out on queue */ 546 kstat_named_t itxs_descriptors; /* Descriptors issued */ 547 kstat_named_t itxs_recycled; /* Descriptors reclaimed */ 548 kstat_named_t itxs_force_copy; /* non-TSO force copy */ 549 kstat_named_t itxs_tso_force_copy; /* TSO force copy */ 550 /* 551 * Various failure conditions. 552 */ 553 kstat_named_t itxs_hck_nol2info; /* Missing l2 info */ 554 kstat_named_t itxs_hck_nol3info; /* Missing l3 info */ 555 kstat_named_t itxs_hck_nol4info; /* Missing l4 info */ 556 kstat_named_t itxs_hck_badl3; /* Not IPv4/IPv6 */ 557 kstat_named_t itxs_hck_badl4; /* Bad L4 Paylaod */ 558 kstat_named_t itxs_lso_nohck; /* Missing offloads for LSO */ 559 kstat_named_t itxs_bind_fails; /* DMA bind failures */ 560 kstat_named_t itxs_tx_short; /* Tx chain too short */ 561 562 kstat_named_t itxs_err_notcb; /* No tcb's available */ 563 kstat_named_t itxs_err_nodescs; /* No tcb's available */ 564 kstat_named_t itxs_err_context; /* Total context failures */ 565 566 kstat_named_t itxs_num_unblocked; /* Number of MAC unblocks */ 567 kstat_named_t itxs_bad_mss; /* Given an unsupported MSS */ 568 } i40e_txq_stat_t; 569 570 /* 571 * An instance of an XL710 transmit/receive queue pair. This currently 572 * represents a combination of both a transmit and receive ring, though they 573 * should really be split apart into separate logical structures. Unfortunately, 574 * during initial work we mistakenly joined them together. 575 */ 576 typedef struct i40e_trqpair { 577 struct i40e *itrq_i40e; 578 579 /* interrupt control structures */ 580 kmutex_t itrq_intr_lock; 581 kcondvar_t itrq_intr_cv; 582 boolean_t itrq_intr_busy; /* Busy processing interrupt */ 583 boolean_t itrq_intr_quiesce; /* Interrupt quiesced */ 584 585 hrtime_t irtq_time_stopped; /* Time when ring was stopped */ 586 587 /* Receive-side structures. */ 588 kmutex_t itrq_rx_lock; 589 mac_ring_handle_t itrq_macrxring; /* Receive ring handle. */ 590 i40e_rx_data_t *itrq_rxdata; /* Receive ring rx data. */ 591 uint64_t itrq_rxgen; /* Generation number for mac/GLDv3. */ 592 uint32_t itrq_index; /* Queue index in the PF */ 593 uint32_t itrq_rx_intrvec; /* Receive interrupt vector. */ 594 boolean_t itrq_intr_poll; /* True when polling */ 595 596 /* Receive-side stats. */ 597 i40e_rxq_stat_t itrq_rxstat; 598 kstat_t *itrq_rxkstat; 599 600 /* Transmit-side structures. */ 601 kmutex_t itrq_tx_lock; 602 kcondvar_t itrq_tx_cv; 603 uint_t itrq_tx_active; /* No. of active i40e_ring_tx()'s */ 604 boolean_t itrq_tx_quiesce; /* Tx is quiesced */ 605 mac_ring_handle_t itrq_mactxring; /* Transmit ring handle. */ 606 uint32_t itrq_tx_intrvec; /* Transmit interrupt vector. */ 607 boolean_t itrq_tx_blocked; /* Does MAC think we're blocked? */ 608 609 /* 610 * TX data sizing 611 */ 612 uint32_t itrq_tx_ring_size; 613 uint32_t itrq_tx_free_list_size; 614 615 /* 616 * TX descriptor ring data 617 */ 618 i40e_dma_buffer_t itrq_desc_area; /* DMA buffer of tx desc ring */ 619 i40e_tx_desc_t *itrq_desc_ring; /* TX Desc ring */ 620 volatile uint32_t *itrq_desc_wbhead; /* TX write-back index */ 621 uint32_t itrq_desc_head; /* Last index hw freed */ 622 uint32_t itrq_desc_tail; /* Index of next free desc */ 623 uint32_t itrq_desc_free; /* Number of free descriptors */ 624 625 /* 626 * TX control block (tcb) data 627 */ 628 kmutex_t itrq_tcb_lock; 629 i40e_tx_control_block_t *itrq_tcb_area; /* Array of control blocks */ 630 i40e_tx_control_block_t **itrq_tcb_work_list; /* In use tcb */ 631 i40e_tx_control_block_t **itrq_tcb_free_list; /* Available tcb */ 632 uint32_t itrq_tcb_free; /* Count of free tcb */ 633 634 /* Transmit-side stats. */ 635 i40e_txq_stat_t itrq_txstat; 636 kstat_t *itrq_txkstat; 637 638 } i40e_trqpair_t; 639 640 /* 641 * VSI statistics. 642 * 643 * This mirrors the i40e_eth_stats structure but transforms it into a kstat. 644 * Note that the stock statistic structure also includes entries for tx 645 * discards. However, this is not actually implemented for the VSI (see Table 646 * 7-221), hence why we don't include the member which would always have a value 647 * of zero. This choice was made to minimize confusion to someone looking at 648 * these, as a value of zero does not necessarily equate to the fact that it's 649 * not implemented. 650 */ 651 typedef struct i40e_vsi_stats { 652 uint64_t ivs_rx_bytes; /* gorc */ 653 uint64_t ivs_rx_unicast; /* uprc */ 654 uint64_t ivs_rx_multicast; /* mprc */ 655 uint64_t ivs_rx_broadcast; /* bprc */ 656 uint64_t ivs_rx_discards; /* rdpc */ 657 uint64_t ivs_rx_unknown_protocol; /* rupp */ 658 uint64_t ivs_tx_bytes; /* gotc */ 659 uint64_t ivs_tx_unicast; /* uptc */ 660 uint64_t ivs_tx_multicast; /* mptc */ 661 uint64_t ivs_tx_broadcast; /* bptc */ 662 uint64_t ivs_tx_errors; /* tepc */ 663 } i40e_vsi_stats_t; 664 665 typedef struct i40e_vsi_kstats { 666 kstat_named_t ivk_rx_bytes; 667 kstat_named_t ivk_rx_unicast; 668 kstat_named_t ivk_rx_multicast; 669 kstat_named_t ivk_rx_broadcast; 670 kstat_named_t ivk_rx_discards; 671 kstat_named_t ivk_rx_unknown_protocol; 672 kstat_named_t ivk_tx_bytes; 673 kstat_named_t ivk_tx_unicast; 674 kstat_named_t ivk_tx_multicast; 675 kstat_named_t ivk_tx_broadcast; 676 kstat_named_t ivk_tx_errors; 677 } i40e_vsi_kstats_t; 678 679 /* 680 * For pf statistics, we opt not to use the standard statistics as defined by 681 * the Intel common code. This also currently combines statistics that are 682 * global across the entire device. 683 */ 684 typedef struct i40e_pf_stats { 685 uint64_t ips_rx_bytes; /* gorc */ 686 uint64_t ips_rx_unicast; /* uprc */ 687 uint64_t ips_rx_multicast; /* mprc */ 688 uint64_t ips_rx_broadcast; /* bprc */ 689 uint64_t ips_tx_bytes; /* gotc */ 690 uint64_t ips_tx_unicast; /* uptc */ 691 uint64_t ips_tx_multicast; /* mptc */ 692 uint64_t ips_tx_broadcast; /* bptc */ 693 694 uint64_t ips_rx_size_64; /* prc64 */ 695 uint64_t ips_rx_size_127; /* prc127 */ 696 uint64_t ips_rx_size_255; /* prc255 */ 697 uint64_t ips_rx_size_511; /* prc511 */ 698 uint64_t ips_rx_size_1023; /* prc1023 */ 699 uint64_t ips_rx_size_1522; /* prc1522 */ 700 uint64_t ips_rx_size_9522; /* prc9522 */ 701 702 uint64_t ips_tx_size_64; /* ptc64 */ 703 uint64_t ips_tx_size_127; /* ptc127 */ 704 uint64_t ips_tx_size_255; /* ptc255 */ 705 uint64_t ips_tx_size_511; /* ptc511 */ 706 uint64_t ips_tx_size_1023; /* ptc1023 */ 707 uint64_t ips_tx_size_1522; /* ptc1522 */ 708 uint64_t ips_tx_size_9522; /* ptc9522 */ 709 710 uint64_t ips_link_xon_rx; /* lxonrxc */ 711 uint64_t ips_link_xoff_rx; /* lxoffrxc */ 712 uint64_t ips_link_xon_tx; /* lxontxc */ 713 uint64_t ips_link_xoff_tx; /* lxofftxc */ 714 uint64_t ips_priority_xon_rx[8]; /* pxonrxc[8] */ 715 uint64_t ips_priority_xoff_rx[8]; /* pxoffrxc[8] */ 716 uint64_t ips_priority_xon_tx[8]; /* pxontxc[8] */ 717 uint64_t ips_priority_xoff_tx[8]; /* pxofftxc[8] */ 718 uint64_t ips_priority_xon_2_xoff[8]; /* rxon2offcnt[8] */ 719 720 uint64_t ips_crc_errors; /* crcerrs */ 721 uint64_t ips_illegal_bytes; /* illerrc */ 722 uint64_t ips_mac_local_faults; /* mlfc */ 723 uint64_t ips_mac_remote_faults; /* mrfc */ 724 uint64_t ips_rx_length_errors; /* rlec */ 725 uint64_t ips_rx_undersize; /* ruc */ 726 uint64_t ips_rx_fragments; /* rfc */ 727 uint64_t ips_rx_oversize; /* roc */ 728 uint64_t ips_rx_jabber; /* rjc */ 729 uint64_t ips_rx_discards; /* rdpc */ 730 uint64_t ips_rx_vm_discards; /* ldpc */ 731 uint64_t ips_rx_short_discards; /* mspdc */ 732 uint64_t ips_tx_dropped_link_down; /* tdold */ 733 uint64_t ips_rx_unknown_protocol; /* rupp */ 734 uint64_t ips_rx_err1; /* rxerr1 */ 735 uint64_t ips_rx_err2; /* rxerr2 */ 736 } i40e_pf_stats_t; 737 738 typedef struct i40e_pf_kstats { 739 kstat_named_t ipk_rx_bytes; /* gorc */ 740 kstat_named_t ipk_rx_unicast; /* uprc */ 741 kstat_named_t ipk_rx_multicast; /* mprc */ 742 kstat_named_t ipk_rx_broadcast; /* bprc */ 743 kstat_named_t ipk_tx_bytes; /* gotc */ 744 kstat_named_t ipk_tx_unicast; /* uptc */ 745 kstat_named_t ipk_tx_multicast; /* mptc */ 746 kstat_named_t ipk_tx_broadcast; /* bptc */ 747 748 kstat_named_t ipk_rx_size_64; /* prc64 */ 749 kstat_named_t ipk_rx_size_127; /* prc127 */ 750 kstat_named_t ipk_rx_size_255; /* prc255 */ 751 kstat_named_t ipk_rx_size_511; /* prc511 */ 752 kstat_named_t ipk_rx_size_1023; /* prc1023 */ 753 kstat_named_t ipk_rx_size_1522; /* prc1522 */ 754 kstat_named_t ipk_rx_size_9522; /* prc9522 */ 755 756 kstat_named_t ipk_tx_size_64; /* ptc64 */ 757 kstat_named_t ipk_tx_size_127; /* ptc127 */ 758 kstat_named_t ipk_tx_size_255; /* ptc255 */ 759 kstat_named_t ipk_tx_size_511; /* ptc511 */ 760 kstat_named_t ipk_tx_size_1023; /* ptc1023 */ 761 kstat_named_t ipk_tx_size_1522; /* ptc1522 */ 762 kstat_named_t ipk_tx_size_9522; /* ptc9522 */ 763 764 kstat_named_t ipk_link_xon_rx; /* lxonrxc */ 765 kstat_named_t ipk_link_xoff_rx; /* lxoffrxc */ 766 kstat_named_t ipk_link_xon_tx; /* lxontxc */ 767 kstat_named_t ipk_link_xoff_tx; /* lxofftxc */ 768 kstat_named_t ipk_priority_xon_rx[8]; /* pxonrxc[8] */ 769 kstat_named_t ipk_priority_xoff_rx[8]; /* pxoffrxc[8] */ 770 kstat_named_t ipk_priority_xon_tx[8]; /* pxontxc[8] */ 771 kstat_named_t ipk_priority_xoff_tx[8]; /* pxofftxc[8] */ 772 kstat_named_t ipk_priority_xon_2_xoff[8]; /* rxon2offcnt[8] */ 773 774 kstat_named_t ipk_crc_errors; /* crcerrs */ 775 kstat_named_t ipk_illegal_bytes; /* illerrc */ 776 kstat_named_t ipk_mac_local_faults; /* mlfc */ 777 kstat_named_t ipk_mac_remote_faults; /* mrfc */ 778 kstat_named_t ipk_rx_length_errors; /* rlec */ 779 kstat_named_t ipk_rx_undersize; /* ruc */ 780 kstat_named_t ipk_rx_fragments; /* rfc */ 781 kstat_named_t ipk_rx_oversize; /* roc */ 782 kstat_named_t ipk_rx_jabber; /* rjc */ 783 kstat_named_t ipk_rx_discards; /* rdpc */ 784 kstat_named_t ipk_rx_vm_discards; /* ldpc */ 785 kstat_named_t ipk_rx_short_discards; /* mspdc */ 786 kstat_named_t ipk_tx_dropped_link_down; /* tdold */ 787 kstat_named_t ipk_rx_unknown_protocol; /* rupp */ 788 kstat_named_t ipk_rx_err1; /* rxerr1 */ 789 kstat_named_t ipk_rx_err2; /* rxerr2 */ 790 } i40e_pf_kstats_t; 791 792 /* 793 * Resources that are pooled and specific to a given i40e_t. 794 */ 795 typedef struct i40e_func_rsrc { 796 uint_t ifr_nrx_queue; 797 uint_t ifr_nrx_queue_used; 798 uint_t ifr_ntx_queue; 799 uint_t ifr_trx_queue_used; 800 uint_t ifr_nvsis; 801 uint_t ifr_nvsis_used; 802 uint_t ifr_nmacfilt; 803 uint_t ifr_nmacfilt_used; 804 uint_t ifr_nmcastfilt; 805 uint_t ifr_nmcastfilt_used; 806 } i40e_func_rsrc_t; 807 808 typedef struct i40e_vsi { 809 uint16_t iv_seid; 810 uint16_t iv_number; 811 kstat_t *iv_kstats; 812 i40e_vsi_stats_t iv_stats; 813 uint16_t iv_stats_id; 814 } i40e_vsi_t; 815 816 /* 817 * While irg_index and irg_grp_hdl aren't used anywhere, they are 818 * still useful for debugging. 819 */ 820 typedef struct i40e_rx_group { 821 uint32_t irg_index; /* index in i40e_rx_groups[] */ 822 uint16_t irg_vsi_seid; /* SEID of VSI for this group */ 823 mac_group_handle_t irg_grp_hdl; /* handle to mac_group_t */ 824 struct i40e *irg_i40e; /* ref to i40e_t */ 825 } i40e_rx_group_t; 826 827 /* 828 * Main i40e per-instance state. 829 */ 830 typedef struct i40e { 831 list_node_t i40e_glink; /* Global list link */ 832 list_node_t i40e_dlink; /* Device list link */ 833 kmutex_t i40e_general_lock; /* General device lock */ 834 835 /* 836 * General Data and management 837 */ 838 dev_info_t *i40e_dip; 839 int i40e_instance; 840 int i40e_fm_capabilities; 841 uint_t i40e_state; 842 i40e_attach_state_t i40e_attach_progress; 843 mac_handle_t i40e_mac_hdl; 844 ddi_periodic_t i40e_periodic_id; 845 846 /* 847 * Pointers to common code data structures and memory for the common 848 * code. 849 */ 850 struct i40e_hw i40e_hw_space; 851 struct i40e_osdep i40e_osdep_space; 852 struct i40e_aq_get_phy_abilities_resp i40e_phy; 853 void *i40e_aqbuf; 854 855 #define I40E_DEF_VSI_IDX 0 856 #define I40E_DEF_VSI(i40e) ((i40e)->i40e_vsis[I40E_DEF_VSI_IDX]) 857 #define I40E_DEF_VSI_SEID(i40e) (I40E_DEF_VSI(i40e).iv_seid) 858 859 /* 860 * Device state, switch information, and resources. 861 */ 862 i40e_vsi_t i40e_vsis[I40E_MAX_NUM_RX_GROUPS]; 863 uint16_t i40e_mac_seid; /* SEID of physical MAC */ 864 uint16_t i40e_veb_seid; /* switch atop MAC (SEID) */ 865 uint16_t i40e_vsi_avail; /* VSIs avail to this PF */ 866 uint16_t i40e_vsi_used; /* VSIs used by this PF */ 867 struct i40e_device *i40e_device; 868 i40e_func_rsrc_t i40e_resources; 869 uint16_t i40e_switch_rsrc_alloc; 870 uint16_t i40e_switch_rsrc_actual; 871 i40e_switch_rsrc_t *i40e_switch_rsrcs; 872 i40e_uaddr_t *i40e_uaddrs; 873 i40e_maddr_t *i40e_maddrs; 874 int i40e_mcast_promisc_count; 875 boolean_t i40e_promisc_on; 876 link_state_t i40e_link_state; 877 uint32_t i40e_link_speed; /* In Mbps */ 878 link_duplex_t i40e_link_duplex; 879 link_fec_t i40e_fec_requested; 880 uint_t i40e_sdu; 881 uint_t i40e_frame_max; 882 883 /* 884 * Transmit and receive information, tunables, and MAC info. 885 */ 886 i40e_trqpair_t *i40e_trqpairs; 887 boolean_t i40e_mr_enable; 888 uint_t i40e_num_trqpairs; /* total TRQPs (per PF) */ 889 uint_t i40e_num_trqpairs_per_vsi; /* TRQPs per VSI */ 890 uint_t i40e_other_itr; 891 892 i40e_rx_group_t *i40e_rx_groups; 893 uint_t i40e_num_rx_groups; 894 int i40e_num_rx_descs; 895 uint32_t i40e_rx_ring_size; 896 uint32_t i40e_rx_buf_size; 897 boolean_t i40e_rx_hcksum_enable; 898 uint32_t i40e_rx_dma_min; 899 uint32_t i40e_rx_limit_per_intr; 900 uint_t i40e_rx_itr; 901 902 int i40e_num_tx_descs; 903 uint32_t i40e_tx_ring_size; 904 uint32_t i40e_tx_buf_size; 905 uint32_t i40e_tx_block_thresh; 906 boolean_t i40e_tx_hcksum_enable; 907 boolean_t i40e_tx_lso_enable; 908 uint32_t i40e_tx_dma_min; 909 uint_t i40e_tx_itr; 910 911 /* 912 * Interrupt state 913 */ 914 uint_t i40e_intr_pri; 915 uint_t i40e_intr_force; 916 uint_t i40e_intr_type; 917 int i40e_intr_cap; 918 uint32_t i40e_intr_count; 919 uint32_t i40e_intr_count_max; 920 uint32_t i40e_intr_count_min; 921 size_t i40e_intr_size; 922 ddi_intr_handle_t *i40e_intr_handles; 923 ddi_cb_handle_t i40e_callback_handle; 924 925 /* 926 * DMA attributes. See i40e_transceiver.c for why we have copies of them 927 * in the i40e_t. 928 */ 929 ddi_dma_attr_t i40e_static_dma_attr; 930 ddi_dma_attr_t i40e_txbind_dma_attr; 931 ddi_dma_attr_t i40e_txbind_lso_dma_attr; 932 ddi_device_acc_attr_t i40e_desc_acc_attr; 933 ddi_device_acc_attr_t i40e_buf_acc_attr; 934 935 /* 936 * The following two fields are used to protect and keep track of 937 * outstanding, loaned buffers to MAC. If we have these, we can't 938 * detach as we have active DMA memory outstanding. 939 */ 940 kmutex_t i40e_rx_pending_lock; 941 kcondvar_t i40e_rx_pending_cv; 942 uint32_t i40e_rx_pending; 943 944 /* 945 * PF statistics and VSI statistics. 946 */ 947 kmutex_t i40e_stat_lock; 948 kstat_t *i40e_pf_kstat; 949 i40e_pf_stats_t i40e_pf_stat; 950 951 /* 952 * Misc. stats and counters that should maybe one day be kstats. 953 */ 954 uint64_t i40e_s_link_status_errs; 955 uint32_t i40e_s_link_status_lasterr; 956 957 /* 958 * LED information. Note this state is only modified in 959 * i40e_gld_set_led() which is protected by MAC's serializer lock. 960 */ 961 uint32_t i40e_led_status; 962 boolean_t i40e_led_saved; 963 964 /* DDI UFM handle */ 965 ddi_ufm_handle_t *i40e_ufmh; 966 } i40e_t; 967 968 /* 969 * The i40e_device represents a PCI device which encapsulates multiple physical 970 * functions which are represented as an i40e_t. This is used to track the use 971 * of pooled resources throughout all of the various devices. 972 */ 973 typedef struct i40e_device { 974 list_node_t id_link; 975 dev_info_t *id_parent; 976 uint_t id_pci_bus; 977 uint_t id_pci_device; 978 uint_t id_nfuncs; /* Total number of functions */ 979 uint_t id_nreg; /* Total number present */ 980 list_t id_i40e_list; /* List of i40e_t's registered */ 981 i40e_switch_rsrc_t *id_rsrcs; /* Switch resources for this PF */ 982 uint_t id_rsrcs_alloc; /* Total allocated resources */ 983 uint_t id_rsrcs_act; /* Actual number of resources */ 984 } i40e_device_t; 985 986 /* Values for the interrupt forcing on the NIC. */ 987 #define I40E_INTR_NONE 0 988 #define I40E_INTR_MSIX 1 989 #define I40E_INTR_MSI 2 990 #define I40E_INTR_LEGACY 3 991 992 /* Hint that we don't want to do any polling... */ 993 #define I40E_POLL_NULL -1 994 995 /* 996 * Logging functions. 997 */ 998 /*PRINTFLIKE2*/ 999 extern void i40e_error(i40e_t *, const char *, ...) __KPRINTFLIKE(2); 1000 /*PRINTFLIKE2*/ 1001 extern void i40e_notice(i40e_t *, const char *, ...) __KPRINTFLIKE(2); 1002 /*PRINTFLIKE2*/ 1003 extern void i40e_log(i40e_t *, const char *, ...) __KPRINTFLIKE(2); 1004 1005 /* 1006 * General link handling functions. 1007 */ 1008 extern void i40e_link_check(i40e_t *); 1009 extern void i40e_update_mtu(i40e_t *); 1010 1011 /* 1012 * FMA functions. 1013 */ 1014 extern int i40e_check_acc_handle(ddi_acc_handle_t); 1015 extern int i40e_check_dma_handle(ddi_dma_handle_t); 1016 extern void i40e_fm_ereport(i40e_t *, char *); 1017 1018 /* 1019 * Interrupt handlers and interrupt handler setup. 1020 */ 1021 extern void i40e_intr_chip_init(i40e_t *); 1022 extern void i40e_intr_chip_fini(i40e_t *); 1023 extern uint_t i40e_intr_msix(void *, void *); 1024 extern uint_t i40e_intr_msi(void *, void *); 1025 extern uint_t i40e_intr_legacy(void *, void *); 1026 extern void i40e_intr_io_enable_all(i40e_t *); 1027 extern void i40e_intr_io_disable_all(i40e_t *); 1028 extern void i40e_intr_io_clear_cause(i40e_t *); 1029 extern void i40e_intr_rx_queue_disable(i40e_trqpair_t *); 1030 extern void i40e_intr_rx_queue_enable(i40e_trqpair_t *); 1031 extern void i40e_intr_set_itr(i40e_t *, i40e_itr_index_t, uint_t); 1032 extern void i40e_intr_quiesce(i40e_trqpair_t *); 1033 1034 /* 1035 * Receive-side functions 1036 */ 1037 extern mblk_t *i40e_ring_rx(i40e_trqpair_t *, int); 1038 extern mblk_t *i40e_ring_rx_poll(void *, int); 1039 extern void i40e_rx_recycle(caddr_t); 1040 extern boolean_t i40e_ring_tx_quiesce(i40e_trqpair_t *); 1041 1042 /* 1043 * Transmit-side functions 1044 */ 1045 mblk_t *i40e_ring_tx(void *, mblk_t *); 1046 extern void i40e_tx_recycle_ring(i40e_trqpair_t *); 1047 extern void i40e_tx_cleanup_ring(i40e_trqpair_t *); 1048 1049 /* 1050 * Statistics functions. 1051 */ 1052 extern boolean_t i40e_stats_init(i40e_t *); 1053 extern void i40e_stats_fini(i40e_t *); 1054 extern boolean_t i40e_stat_vsi_init(i40e_t *, uint_t); 1055 extern void i40e_stat_vsi_fini(i40e_t *, uint_t); 1056 extern boolean_t i40e_stats_trqpair_init(i40e_trqpair_t *); 1057 extern void i40e_stats_trqpair_fini(i40e_trqpair_t *); 1058 extern int i40e_m_stat(void *, uint_t, uint64_t *); 1059 extern int i40e_rx_ring_stat(mac_ring_driver_t, uint_t, uint64_t *); 1060 extern int i40e_tx_ring_stat(mac_ring_driver_t, uint_t, uint64_t *); 1061 extern mac_ether_media_t i40e_link_to_media(i40e_t *); 1062 1063 /* 1064 * MAC/GLDv3 functions, and functions called by MAC/GLDv3 support code. 1065 */ 1066 extern boolean_t i40e_register_mac(i40e_t *); 1067 extern boolean_t i40e_start(i40e_t *); 1068 extern void i40e_stop(i40e_t *); 1069 extern int i40e_setup_ring(i40e_trqpair_t *); 1070 extern boolean_t i40e_shutdown_ring(i40e_trqpair_t *); 1071 1072 /* 1073 * DMA & buffer functions and attributes 1074 */ 1075 extern void i40e_init_dma_attrs(i40e_t *, boolean_t); 1076 extern boolean_t i40e_alloc_ring_mem(i40e_trqpair_t *); 1077 extern void i40e_free_ring_mem(i40e_trqpair_t *, boolean_t); 1078 1079 #ifdef __cplusplus 1080 } 1081 #endif 1082 1083 #endif /* _I40E_SW_H */ 1084