1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /*
3 * Copyright (C) 2003-2014, 2018-2021, 2023-2025 Intel Corporation
4 * Copyright (C) 2013-2015 Intel Mobile Communications GmbH
5 * Copyright (C) 2016-2017 Intel Deutschland GmbH
6 */
7 #include <linux/etherdevice.h>
8 #include <linux/ieee80211.h>
9 #include <linux/dmapool.h>
10 #include <linux/slab.h>
11 #include <linux/sched.h>
12 #include <linux/tcp.h>
13 #ifdef CONFIG_INET
14 #include <net/ip6_checksum.h>
15 #include <net/tso.h>
16 #endif
17 #if defined(__FreeBSD__)
18 #include <net/mac80211.h>
19 #endif
20
21 #include "fw/api/commands.h"
22 #include "fw/api/datapath.h"
23 #include "fw/api/debug.h"
24 #include "iwl-fh.h"
25 #include "iwl-debug.h"
26 #include "iwl-csr.h"
27 #include "iwl-prph.h"
28 #include "iwl-io.h"
29 #include "iwl-scd.h"
30 #include "iwl-op-mode.h"
31 #include "internal.h"
32 #include "fw/api/tx.h"
33 #include "fw/dbg.h"
34 #include "pcie/utils.h"
35
36 /*************** DMA-QUEUE-GENERAL-FUNCTIONS *****
37 * DMA services
38 *
39 * Theory of operation
40 *
41 * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer
42 * of buffer descriptors, each of which points to one or more data buffers for
43 * the device to read from or fill. Driver and device exchange status of each
44 * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty
45 * entries in each circular buffer, to protect against confusing empty and full
46 * queue states.
47 *
48 * The device reads or writes the data in the queues via the device's several
49 * DMA/FIFO channels. Each queue is mapped to a single DMA channel.
50 *
51 * For Tx queue, there are low mark and high mark limits. If, after queuing
52 * the packet for Tx, free space become < low mark, Tx queue stopped. When
53 * reclaiming packets (on 'tx done IRQ), if free space become > high mark,
54 * Tx queue resumed.
55 *
56 ***************************************************/
57
58
iwl_pcie_alloc_dma_ptr(struct iwl_trans * trans,struct iwl_dma_ptr * ptr,size_t size)59 int iwl_pcie_alloc_dma_ptr(struct iwl_trans *trans,
60 struct iwl_dma_ptr *ptr, size_t size)
61 {
62 if (WARN_ON(ptr->addr))
63 return -EINVAL;
64
65 ptr->addr = dma_alloc_coherent(trans->dev, size,
66 &ptr->dma, GFP_KERNEL);
67 if (!ptr->addr)
68 return -ENOMEM;
69 ptr->size = size;
70 return 0;
71 }
72
iwl_pcie_free_dma_ptr(struct iwl_trans * trans,struct iwl_dma_ptr * ptr)73 void iwl_pcie_free_dma_ptr(struct iwl_trans *trans, struct iwl_dma_ptr *ptr)
74 {
75 if (unlikely(!ptr->addr))
76 return;
77
78 dma_free_coherent(trans->dev, ptr->size, ptr->addr, ptr->dma);
79 memset(ptr, 0, sizeof(*ptr));
80 }
81
82 /*
83 * iwl_pcie_txq_inc_wr_ptr - Send new write index to hardware
84 */
iwl_pcie_txq_inc_wr_ptr(struct iwl_trans * trans,struct iwl_txq * txq)85 static void iwl_pcie_txq_inc_wr_ptr(struct iwl_trans *trans,
86 struct iwl_txq *txq)
87 {
88 u32 reg = 0;
89 int txq_id = txq->id;
90
91 lockdep_assert_held(&txq->lock);
92
93 /*
94 * explicitly wake up the NIC if:
95 * 1. shadow registers aren't enabled
96 * 2. NIC is woken up for CMD regardless of shadow outside this function
97 * 3. there is a chance that the NIC is asleep
98 */
99 if (!trans->mac_cfg->base->shadow_reg_enable &&
100 txq_id != trans->conf.cmd_queue &&
101 test_bit(STATUS_TPOWER_PMI, &trans->status)) {
102 /*
103 * wake up nic if it's powered down ...
104 * uCode will wake up, and interrupt us again, so next
105 * time we'll skip this part.
106 */
107 reg = iwl_read32(trans, CSR_UCODE_DRV_GP1);
108
109 if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
110 IWL_DEBUG_INFO(trans, "Tx queue %d requesting wakeup, GP1 = 0x%x\n",
111 txq_id, reg);
112 iwl_set_bit(trans, CSR_GP_CNTRL,
113 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
114 txq->need_update = true;
115 return;
116 }
117 }
118
119 /*
120 * if not in power-save mode, uCode will never sleep when we're
121 * trying to tx (during RFKILL, we're not trying to tx).
122 */
123 IWL_DEBUG_TX(trans, "Q:%d WR: 0x%x\n", txq_id, txq->write_ptr);
124 if (!txq->block)
125 iwl_write32(trans, HBUS_TARG_WRPTR,
126 txq->write_ptr | (txq_id << 8));
127 }
128
iwl_pcie_txq_check_wrptrs(struct iwl_trans * trans)129 void iwl_pcie_txq_check_wrptrs(struct iwl_trans *trans)
130 {
131 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
132 int i;
133
134 for (i = 0; i < trans->mac_cfg->base->num_of_queues; i++) {
135 struct iwl_txq *txq = trans_pcie->txqs.txq[i];
136
137 if (!test_bit(i, trans_pcie->txqs.queue_used))
138 continue;
139
140 spin_lock_bh(&txq->lock);
141 if (txq->need_update) {
142 iwl_pcie_txq_inc_wr_ptr(trans, txq);
143 txq->need_update = false;
144 }
145 spin_unlock_bh(&txq->lock);
146 }
147 }
148
iwl_pcie_gen1_tfd_set_tb(struct iwl_tfd * tfd,u8 idx,dma_addr_t addr,u16 len)149 static inline void iwl_pcie_gen1_tfd_set_tb(struct iwl_tfd *tfd,
150 u8 idx, dma_addr_t addr, u16 len)
151 {
152 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
153 u16 hi_n_len = len << 4;
154
155 put_unaligned_le32(addr, &tb->lo);
156 hi_n_len |= iwl_get_dma_hi_addr(addr);
157
158 tb->hi_n_len = cpu_to_le16(hi_n_len);
159
160 tfd->num_tbs = idx + 1;
161 }
162
iwl_txq_gen1_tfd_get_num_tbs(struct iwl_tfd * tfd)163 static inline u8 iwl_txq_gen1_tfd_get_num_tbs(struct iwl_tfd *tfd)
164 {
165 return tfd->num_tbs & 0x1f;
166 }
167
iwl_pcie_txq_build_tfd(struct iwl_trans * trans,struct iwl_txq * txq,dma_addr_t addr,u16 len,bool reset)168 static int iwl_pcie_txq_build_tfd(struct iwl_trans *trans, struct iwl_txq *txq,
169 dma_addr_t addr, u16 len, bool reset)
170 {
171 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
172 void *tfd;
173 u32 num_tbs;
174
175 tfd = (u8 *)txq->tfds + trans_pcie->txqs.tfd.size * txq->write_ptr;
176
177 if (reset)
178 memset(tfd, 0, trans_pcie->txqs.tfd.size);
179
180 num_tbs = iwl_txq_gen1_tfd_get_num_tbs(tfd);
181
182 /* Each TFD can point to a maximum max_tbs Tx buffers */
183 if (num_tbs >= trans_pcie->txqs.tfd.max_tbs) {
184 IWL_ERR(trans, "Error can not send more than %d chunks\n",
185 trans_pcie->txqs.tfd.max_tbs);
186 return -EINVAL;
187 }
188
189 if (WARN(addr & ~IWL_TX_DMA_MASK,
190 "Unaligned address = %llx\n", (unsigned long long)addr))
191 return -EINVAL;
192
193 iwl_pcie_gen1_tfd_set_tb(tfd, num_tbs, addr, len);
194
195 return num_tbs;
196 }
197
iwl_pcie_clear_cmd_in_flight(struct iwl_trans * trans)198 static void iwl_pcie_clear_cmd_in_flight(struct iwl_trans *trans)
199 {
200 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
201
202 if (!trans->mac_cfg->base->apmg_wake_up_wa)
203 return;
204
205 spin_lock(&trans_pcie->reg_lock);
206
207 if (WARN_ON(!trans_pcie->cmd_hold_nic_awake)) {
208 spin_unlock(&trans_pcie->reg_lock);
209 return;
210 }
211
212 trans_pcie->cmd_hold_nic_awake = false;
213 iwl_trans_clear_bit(trans, CSR_GP_CNTRL,
214 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
215 spin_unlock(&trans_pcie->reg_lock);
216 }
217
iwl_pcie_free_and_unmap_tso_page(struct iwl_trans * trans,struct page * page)218 static void iwl_pcie_free_and_unmap_tso_page(struct iwl_trans *trans,
219 struct page *page)
220 {
221 struct iwl_tso_page_info *info = IWL_TSO_PAGE_INFO(page_address(page));
222
223 /* Decrease internal use count and unmap/free page if needed */
224 if (refcount_dec_and_test(&info->use_count)) {
225 dma_unmap_page(trans->dev, info->dma_addr, PAGE_SIZE,
226 DMA_TO_DEVICE);
227
228 __free_page(page);
229 }
230 }
231
iwl_pcie_free_tso_pages(struct iwl_trans * trans,struct sk_buff * skb,struct iwl_cmd_meta * cmd_meta)232 void iwl_pcie_free_tso_pages(struct iwl_trans *trans, struct sk_buff *skb,
233 struct iwl_cmd_meta *cmd_meta)
234 {
235 struct page **page_ptr;
236 struct page *next;
237
238 page_ptr = (void *)((u8 *)skb->cb + trans->conf.cb_data_offs);
239 next = *page_ptr;
240 *page_ptr = NULL;
241
242 while (next) {
243 struct iwl_tso_page_info *info;
244 struct page *tmp = next;
245
246 info = IWL_TSO_PAGE_INFO(page_address(next));
247 next = info->next;
248
249 /* Unmap the scatter gather list that is on the last page */
250 if (!next && cmd_meta->sg_offset) {
251 struct sg_table *sgt;
252
253 sgt = (void *)((u8 *)page_address(tmp) +
254 cmd_meta->sg_offset);
255
256 dma_unmap_sgtable(trans->dev, sgt, DMA_TO_DEVICE, 0);
257 }
258
259 iwl_pcie_free_and_unmap_tso_page(trans, tmp);
260 }
261 }
262
263 static inline dma_addr_t
iwl_txq_gen1_tfd_tb_get_addr(struct iwl_tfd * tfd,u8 idx)264 iwl_txq_gen1_tfd_tb_get_addr(struct iwl_tfd *tfd, u8 idx)
265 {
266 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
267 dma_addr_t addr;
268 dma_addr_t hi_len;
269
270 addr = get_unaligned_le32(&tb->lo);
271
272 if (sizeof(dma_addr_t) <= sizeof(u32))
273 return addr;
274
275 hi_len = le16_to_cpu(tb->hi_n_len) & 0xF;
276
277 /*
278 * shift by 16 twice to avoid warnings on 32-bit
279 * (where this code never runs anyway due to the
280 * if statement above)
281 */
282 return addr | ((hi_len << 16) << 16);
283 }
284
iwl_txq_set_tfd_invalid_gen1(struct iwl_trans * trans,struct iwl_tfd * tfd)285 static void iwl_txq_set_tfd_invalid_gen1(struct iwl_trans *trans,
286 struct iwl_tfd *tfd)
287 {
288 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
289
290 tfd->num_tbs = 0;
291
292 iwl_pcie_gen1_tfd_set_tb(tfd, 0, trans_pcie->invalid_tx_cmd.dma,
293 trans_pcie->invalid_tx_cmd.size);
294 }
295
iwl_txq_gen1_tfd_unmap(struct iwl_trans * trans,struct iwl_cmd_meta * meta,struct iwl_txq * txq,int index)296 static void iwl_txq_gen1_tfd_unmap(struct iwl_trans *trans,
297 struct iwl_cmd_meta *meta,
298 struct iwl_txq *txq, int index)
299 {
300 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
301 int i, num_tbs;
302 struct iwl_tfd *tfd = iwl_txq_get_tfd(trans, txq, index);
303
304 /* Sanity check on number of chunks */
305 num_tbs = iwl_txq_gen1_tfd_get_num_tbs(tfd);
306
307 if (num_tbs > trans_pcie->txqs.tfd.max_tbs) {
308 IWL_ERR(trans, "Too many chunks: %i\n", num_tbs);
309 /* @todo issue fatal error, it is quite serious situation */
310 return;
311 }
312
313 /* TB1 is mapped directly, the rest is the TSO page and SG list. */
314 if (meta->sg_offset)
315 num_tbs = 2;
316
317 /* first TB is never freed - it's the bidirectional DMA data */
318
319 for (i = 1; i < num_tbs; i++) {
320 if (meta->tbs & BIT(i))
321 dma_unmap_page(trans->dev,
322 iwl_txq_gen1_tfd_tb_get_addr(tfd, i),
323 iwl_txq_gen1_tfd_tb_get_len(trans,
324 tfd, i),
325 DMA_TO_DEVICE);
326 else
327 dma_unmap_single(trans->dev,
328 iwl_txq_gen1_tfd_tb_get_addr(tfd, i),
329 iwl_txq_gen1_tfd_tb_get_len(trans,
330 tfd, i),
331 DMA_TO_DEVICE);
332 }
333
334 meta->tbs = 0;
335
336 iwl_txq_set_tfd_invalid_gen1(trans, tfd);
337 }
338
339 /**
340 * iwl_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
341 * @trans: transport private data
342 * @txq: tx queue
343 * @read_ptr: the TXQ read_ptr to free
344 *
345 * Does NOT advance any TFD circular buffer read/write indexes
346 * Does NOT free the TFD itself (which is within circular buffer)
347 */
iwl_txq_free_tfd(struct iwl_trans * trans,struct iwl_txq * txq,int read_ptr)348 static void iwl_txq_free_tfd(struct iwl_trans *trans, struct iwl_txq *txq,
349 int read_ptr)
350 {
351 /* rd_ptr is bounded by TFD_QUEUE_SIZE_MAX and
352 * idx is bounded by n_window
353 */
354 int idx = iwl_txq_get_cmd_index(txq, read_ptr);
355 struct sk_buff *skb;
356
357 lockdep_assert_held(&txq->reclaim_lock);
358
359 if (!txq->entries)
360 return;
361
362 /* We have only q->n_window txq->entries, but we use
363 * TFD_QUEUE_SIZE_MAX tfds
364 */
365 if (trans->mac_cfg->gen2)
366 iwl_txq_gen2_tfd_unmap(trans, &txq->entries[idx].meta,
367 iwl_txq_get_tfd(trans, txq, read_ptr));
368 else
369 iwl_txq_gen1_tfd_unmap(trans, &txq->entries[idx].meta,
370 txq, read_ptr);
371
372 /* free SKB */
373 skb = txq->entries[idx].skb;
374
375 /* Can be called from irqs-disabled context
376 * If skb is not NULL, it means that the whole queue is being
377 * freed and that the queue is not empty - free the skb
378 */
379 if (skb) {
380 iwl_op_mode_free_skb(trans->op_mode, skb);
381 txq->entries[idx].skb = NULL;
382 }
383 }
384
385 /*
386 * iwl_pcie_txq_unmap - Unmap any remaining DMA mappings and free skb's
387 */
iwl_pcie_txq_unmap(struct iwl_trans * trans,int txq_id)388 static void iwl_pcie_txq_unmap(struct iwl_trans *trans, int txq_id)
389 {
390 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
391 struct iwl_txq *txq = trans_pcie->txqs.txq[txq_id];
392
393 if (!txq) {
394 IWL_ERR(trans, "Trying to free a queue that wasn't allocated?\n");
395 return;
396 }
397
398 spin_lock_bh(&txq->reclaim_lock);
399 spin_lock(&txq->lock);
400 while (txq->write_ptr != txq->read_ptr) {
401 IWL_DEBUG_TX_REPLY(trans, "Q %d Free %d\n",
402 txq_id, txq->read_ptr);
403
404 if (txq_id != trans->conf.cmd_queue) {
405 struct sk_buff *skb = txq->entries[txq->read_ptr].skb;
406 struct iwl_cmd_meta *cmd_meta =
407 &txq->entries[txq->read_ptr].meta;
408
409 if (WARN_ON_ONCE(!skb))
410 continue;
411
412 iwl_pcie_free_tso_pages(trans, skb, cmd_meta);
413 }
414 iwl_txq_free_tfd(trans, txq, txq->read_ptr);
415 txq->read_ptr = iwl_txq_inc_wrap(trans, txq->read_ptr);
416
417 if (txq->read_ptr == txq->write_ptr &&
418 txq_id == trans->conf.cmd_queue)
419 iwl_pcie_clear_cmd_in_flight(trans);
420 }
421
422 while (!skb_queue_empty(&txq->overflow_q)) {
423 struct sk_buff *skb = __skb_dequeue(&txq->overflow_q);
424
425 iwl_op_mode_free_skb(trans->op_mode, skb);
426 }
427
428 spin_unlock(&txq->lock);
429 spin_unlock_bh(&txq->reclaim_lock);
430
431 /* just in case - this queue may have been stopped */
432 iwl_trans_pcie_wake_queue(trans, txq);
433 }
434
435 /*
436 * iwl_pcie_txq_free - Deallocate DMA queue.
437 * @txq: Transmit queue to deallocate.
438 *
439 * Empty queue by removing and destroying all BD's.
440 * Free all buffers.
441 * 0-fill, but do not free "txq" descriptor structure.
442 */
iwl_pcie_txq_free(struct iwl_trans * trans,int txq_id)443 static void iwl_pcie_txq_free(struct iwl_trans *trans, int txq_id)
444 {
445 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
446 struct iwl_txq *txq = trans_pcie->txqs.txq[txq_id];
447 struct device *dev = trans->dev;
448 int i;
449
450 if (WARN_ON(!txq))
451 return;
452
453 iwl_pcie_txq_unmap(trans, txq_id);
454
455 /* De-alloc array of command/tx buffers */
456 if (txq_id == trans->conf.cmd_queue)
457 for (i = 0; i < txq->n_window; i++) {
458 kfree_sensitive(txq->entries[i].cmd);
459 kfree_sensitive(txq->entries[i].free_buf);
460 }
461
462 /* De-alloc circular buffer of TFDs */
463 if (txq->tfds) {
464 dma_free_coherent(dev,
465 trans_pcie->txqs.tfd.size *
466 trans->mac_cfg->base->max_tfd_queue_size,
467 txq->tfds, txq->dma_addr);
468 txq->dma_addr = 0;
469 txq->tfds = NULL;
470
471 dma_free_coherent(dev,
472 sizeof(*txq->first_tb_bufs) * txq->n_window,
473 txq->first_tb_bufs, txq->first_tb_dma);
474 }
475
476 kfree(txq->entries);
477 txq->entries = NULL;
478
479 timer_delete_sync(&txq->stuck_timer);
480
481 /* 0-fill queue descriptor structure */
482 memset(txq, 0, sizeof(*txq));
483 }
484
iwl_pcie_tx_start(struct iwl_trans * trans)485 void iwl_pcie_tx_start(struct iwl_trans *trans)
486 {
487 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
488 int nq = trans->mac_cfg->base->num_of_queues;
489 int chan;
490 u32 reg_val;
491 int clear_dwords = (SCD_TRANS_TBL_OFFSET_QUEUE(nq) -
492 SCD_CONTEXT_MEM_LOWER_BOUND) / sizeof(u32);
493
494 /* make sure all queue are not stopped/used */
495 memset(trans_pcie->txqs.queue_stopped, 0,
496 sizeof(trans_pcie->txqs.queue_stopped));
497 memset(trans_pcie->txqs.queue_used, 0,
498 sizeof(trans_pcie->txqs.queue_used));
499
500 trans_pcie->scd_base_addr =
501 iwl_read_prph(trans, SCD_SRAM_BASE_ADDR);
502
503 /* reset context data, TX status and translation data */
504 iwl_trans_write_mem(trans, trans_pcie->scd_base_addr +
505 SCD_CONTEXT_MEM_LOWER_BOUND,
506 NULL, clear_dwords);
507
508 iwl_write_prph(trans, SCD_DRAM_BASE_ADDR,
509 trans_pcie->txqs.scd_bc_tbls.dma >> 10);
510
511 /* The chain extension of the SCD doesn't work well. This feature is
512 * enabled by default by the HW, so we need to disable it manually.
513 */
514 if (trans->mac_cfg->base->scd_chain_ext_wa)
515 iwl_write_prph(trans, SCD_CHAINEXT_EN, 0);
516
517 iwl_trans_ac_txq_enable(trans, trans->conf.cmd_queue,
518 trans->conf.cmd_fifo,
519 IWL_DEF_WD_TIMEOUT);
520
521 /* Activate all Tx DMA/FIFO channels */
522 iwl_scd_activate_fifos(trans);
523
524 /* Enable DMA channel */
525 for (chan = 0; chan < FH_TCSR_CHNL_NUM; chan++)
526 iwl_write_direct32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(chan),
527 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
528 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE);
529
530 /* Update FH chicken bits */
531 reg_val = iwl_read_direct32(trans, FH_TX_CHICKEN_BITS_REG);
532 iwl_write_direct32(trans, FH_TX_CHICKEN_BITS_REG,
533 reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN);
534
535 /* Enable L1-Active */
536 if (trans->mac_cfg->device_family < IWL_DEVICE_FAMILY_8000)
537 iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG,
538 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
539 }
540
iwl_trans_pcie_tx_reset(struct iwl_trans * trans)541 void iwl_trans_pcie_tx_reset(struct iwl_trans *trans)
542 {
543 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
544 int txq_id;
545
546 /*
547 * we should never get here in gen2 trans mode return early to avoid
548 * having invalid accesses
549 */
550 if (WARN_ON_ONCE(trans->mac_cfg->gen2))
551 return;
552
553 for (txq_id = 0; txq_id < trans->mac_cfg->base->num_of_queues;
554 txq_id++) {
555 struct iwl_txq *txq = trans_pcie->txqs.txq[txq_id];
556 if (trans->mac_cfg->gen2)
557 iwl_write_direct64(trans,
558 FH_MEM_CBBC_QUEUE(trans, txq_id),
559 txq->dma_addr);
560 else
561 iwl_write_direct32(trans,
562 FH_MEM_CBBC_QUEUE(trans, txq_id),
563 txq->dma_addr >> 8);
564 iwl_pcie_txq_unmap(trans, txq_id);
565 txq->read_ptr = 0;
566 txq->write_ptr = 0;
567 }
568
569 /* Tell NIC where to find the "keep warm" buffer */
570 iwl_write_direct32(trans, FH_KW_MEM_ADDR_REG,
571 trans_pcie->kw.dma >> 4);
572
573 /*
574 * Send 0 as the scd_base_addr since the device may have be reset
575 * while we were in WoWLAN in which case SCD_SRAM_BASE_ADDR will
576 * contain garbage.
577 */
578 iwl_pcie_tx_start(trans);
579 }
580
iwl_pcie_tx_stop_fh(struct iwl_trans * trans)581 static void iwl_pcie_tx_stop_fh(struct iwl_trans *trans)
582 {
583 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
584 int ch, ret;
585 u32 mask = 0;
586
587 spin_lock_bh(&trans_pcie->irq_lock);
588
589 if (!iwl_trans_grab_nic_access(trans))
590 goto out;
591
592 /* Stop each Tx DMA channel */
593 for (ch = 0; ch < FH_TCSR_CHNL_NUM; ch++) {
594 iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(ch), 0x0);
595 mask |= FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch);
596 }
597
598 /* Wait for DMA channels to be idle */
599 ret = iwl_poll_bits(trans, FH_TSSR_TX_STATUS_REG, mask, 5000);
600 if (ret)
601 IWL_ERR(trans,
602 "Failing on timeout while stopping DMA channel %d [0x%08x]\n",
603 ch, iwl_read32(trans, FH_TSSR_TX_STATUS_REG));
604
605 iwl_trans_release_nic_access(trans);
606
607 out:
608 spin_unlock_bh(&trans_pcie->irq_lock);
609 }
610
611 /*
612 * iwl_pcie_tx_stop - Stop all Tx DMA channels
613 */
iwl_pcie_tx_stop(struct iwl_trans * trans)614 int iwl_pcie_tx_stop(struct iwl_trans *trans)
615 {
616 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
617 int txq_id;
618
619 /* Turn off all Tx DMA fifos */
620 iwl_scd_deactivate_fifos(trans);
621
622 /* Turn off all Tx DMA channels */
623 iwl_pcie_tx_stop_fh(trans);
624
625 /*
626 * This function can be called before the op_mode disabled the
627 * queues. This happens when we have an rfkill interrupt.
628 * Since we stop Tx altogether - mark the queues as stopped.
629 */
630 memset(trans_pcie->txqs.queue_stopped, 0,
631 sizeof(trans_pcie->txqs.queue_stopped));
632 memset(trans_pcie->txqs.queue_used, 0,
633 sizeof(trans_pcie->txqs.queue_used));
634
635 /* This can happen: start_hw, stop_device */
636 if (!trans_pcie->txq_memory)
637 return 0;
638
639 /* Unmap DMA from host system and free skb's */
640 for (txq_id = 0; txq_id < trans->mac_cfg->base->num_of_queues;
641 txq_id++)
642 iwl_pcie_txq_unmap(trans, txq_id);
643
644 return 0;
645 }
646
647 /*
648 * iwl_trans_tx_free - Free TXQ Context
649 *
650 * Destroy all TX DMA queues and structures
651 */
iwl_pcie_tx_free(struct iwl_trans * trans)652 void iwl_pcie_tx_free(struct iwl_trans *trans)
653 {
654 int txq_id;
655 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
656
657 memset(trans_pcie->txqs.queue_used, 0,
658 sizeof(trans_pcie->txqs.queue_used));
659
660 /* Tx queues */
661 if (trans_pcie->txq_memory) {
662 for (txq_id = 0;
663 txq_id < trans->mac_cfg->base->num_of_queues;
664 txq_id++) {
665 iwl_pcie_txq_free(trans, txq_id);
666 trans_pcie->txqs.txq[txq_id] = NULL;
667 }
668 }
669
670 kfree(trans_pcie->txq_memory);
671 trans_pcie->txq_memory = NULL;
672
673 iwl_pcie_free_dma_ptr(trans, &trans_pcie->kw);
674
675 iwl_pcie_free_dma_ptr(trans, &trans_pcie->txqs.scd_bc_tbls);
676 }
677
iwl_txq_log_scd_error(struct iwl_trans * trans,struct iwl_txq * txq)678 void iwl_txq_log_scd_error(struct iwl_trans *trans, struct iwl_txq *txq)
679 {
680 u32 txq_id = txq->id;
681 u32 status;
682 bool active;
683 u8 fifo;
684
685 if (trans->mac_cfg->gen2) {
686 IWL_ERR(trans, "Queue %d is stuck %d %d\n", txq_id,
687 txq->read_ptr, txq->write_ptr);
688 /* TODO: access new SCD registers and dump them */
689 return;
690 }
691
692 status = iwl_read_prph(trans, SCD_QUEUE_STATUS_BITS(txq_id));
693 fifo = (status >> SCD_QUEUE_STTS_REG_POS_TXF) & 0x7;
694 active = !!(status & BIT(SCD_QUEUE_STTS_REG_POS_ACTIVE));
695
696 IWL_ERR(trans,
697 "Queue %d is %sactive on fifo %d and stuck for %u ms. SW [%d, %d] HW [%d, %d] FH TRB=0x0%x\n",
698 txq_id, active ? "" : "in", fifo,
699 jiffies_to_msecs(txq->wd_timeout),
700 txq->read_ptr, txq->write_ptr,
701 iwl_read_prph(trans, SCD_QUEUE_RDPTR(txq_id)) &
702 (trans->mac_cfg->base->max_tfd_queue_size - 1),
703 iwl_read_prph(trans, SCD_QUEUE_WRPTR(txq_id)) &
704 (trans->mac_cfg->base->max_tfd_queue_size - 1),
705 iwl_read_direct32(trans, FH_TX_TRB_REG(fifo)));
706 }
707
iwl_txq_stuck_timer(struct timer_list * t)708 static void iwl_txq_stuck_timer(struct timer_list *t)
709 {
710 struct iwl_txq *txq = timer_container_of(txq, t, stuck_timer);
711 struct iwl_trans *trans = txq->trans;
712
713 spin_lock(&txq->lock);
714 /* check if triggered erroneously */
715 if (txq->read_ptr == txq->write_ptr) {
716 spin_unlock(&txq->lock);
717 return;
718 }
719 spin_unlock(&txq->lock);
720
721 iwl_txq_log_scd_error(trans, txq);
722
723 iwl_force_nmi(trans);
724 }
725
iwl_pcie_txq_alloc(struct iwl_trans * trans,struct iwl_txq * txq,int slots_num,bool cmd_queue)726 int iwl_pcie_txq_alloc(struct iwl_trans *trans, struct iwl_txq *txq,
727 int slots_num, bool cmd_queue)
728 {
729 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
730 size_t num_entries = trans->mac_cfg->gen2 ?
731 slots_num : trans->mac_cfg->base->max_tfd_queue_size;
732 size_t tfd_sz;
733 size_t tb0_buf_sz;
734 int i;
735
736 if (WARN_ONCE(slots_num <= 0, "Invalid slots num:%d\n", slots_num))
737 return -EINVAL;
738
739 if (WARN_ON(txq->entries || txq->tfds))
740 return -EINVAL;
741
742 tfd_sz = trans_pcie->txqs.tfd.size * num_entries;
743
744 timer_setup(&txq->stuck_timer, iwl_txq_stuck_timer, 0);
745 txq->trans = trans;
746
747 txq->n_window = slots_num;
748
749 txq->entries = kzalloc_objs(struct iwl_pcie_txq_entry, slots_num);
750
751 if (!txq->entries)
752 goto error;
753
754 if (cmd_queue)
755 for (i = 0; i < slots_num; i++) {
756 txq->entries[i].cmd =
757 kmalloc_obj(struct iwl_device_cmd);
758 if (!txq->entries[i].cmd)
759 goto error;
760 }
761
762 /* Circular buffer of transmit frame descriptors (TFDs),
763 * shared with device
764 */
765 txq->tfds = dma_alloc_coherent(trans->dev, tfd_sz,
766 &txq->dma_addr, GFP_KERNEL);
767 if (!txq->tfds)
768 goto error;
769
770 BUILD_BUG_ON(sizeof(*txq->first_tb_bufs) != IWL_FIRST_TB_SIZE_ALIGN);
771
772 tb0_buf_sz = sizeof(*txq->first_tb_bufs) * slots_num;
773
774 txq->first_tb_bufs = dma_alloc_coherent(trans->dev, tb0_buf_sz,
775 &txq->first_tb_dma,
776 GFP_KERNEL);
777 if (!txq->first_tb_bufs)
778 goto err_free_tfds;
779
780 for (i = 0; i < num_entries; i++) {
781 void *tfd = iwl_txq_get_tfd(trans, txq, i);
782
783 if (trans->mac_cfg->gen2)
784 iwl_txq_set_tfd_invalid_gen2(trans, tfd);
785 else
786 iwl_txq_set_tfd_invalid_gen1(trans, tfd);
787 }
788
789 return 0;
790 err_free_tfds:
791 dma_free_coherent(trans->dev, tfd_sz, txq->tfds, txq->dma_addr);
792 txq->tfds = NULL;
793 error:
794 if (txq->entries && cmd_queue)
795 for (i = 0; i < slots_num; i++)
796 kfree(txq->entries[i].cmd);
797 kfree(txq->entries);
798 txq->entries = NULL;
799
800 return -ENOMEM;
801 }
802
803 #define BC_TABLE_SIZE (sizeof(struct iwl_bc_tbl_entry) * TFD_QUEUE_BC_SIZE)
804
805 /*
806 * iwl_pcie_tx_alloc - allocate TX context
807 * Allocate all Tx DMA structures and initialize them
808 */
iwl_pcie_tx_alloc(struct iwl_trans * trans)809 static int iwl_pcie_tx_alloc(struct iwl_trans *trans)
810 {
811 int ret;
812 int txq_id, slots_num;
813 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
814 u16 bc_tbls_size = trans->mac_cfg->base->num_of_queues;
815
816 if (WARN_ON(trans->mac_cfg->device_family >= IWL_DEVICE_FAMILY_AX210))
817 return -EINVAL;
818
819 bc_tbls_size *= BC_TABLE_SIZE;
820
821 /*It is not allowed to alloc twice, so warn when this happens.
822 * We cannot rely on the previous allocation, so free and fail */
823 if (WARN_ON(trans_pcie->txq_memory)) {
824 ret = -EINVAL;
825 goto error;
826 }
827
828 ret = iwl_pcie_alloc_dma_ptr(trans, &trans_pcie->txqs.scd_bc_tbls,
829 bc_tbls_size);
830 if (ret) {
831 IWL_ERR(trans, "Scheduler BC Table allocation failed\n");
832 goto error;
833 }
834
835 /* Alloc keep-warm buffer */
836 ret = iwl_pcie_alloc_dma_ptr(trans, &trans_pcie->kw, IWL_KW_SIZE);
837 if (ret) {
838 IWL_ERR(trans, "Keep Warm allocation failed\n");
839 goto error;
840 }
841
842 trans_pcie->txq_memory =
843 kzalloc_objs(struct iwl_txq,
844 trans->mac_cfg->base->num_of_queues);
845 if (!trans_pcie->txq_memory) {
846 IWL_ERR(trans, "Not enough memory for txq\n");
847 ret = -ENOMEM;
848 goto error;
849 }
850
851 /* Alloc and init all Tx queues, including the command queue (#4/#9) */
852 for (txq_id = 0; txq_id < trans->mac_cfg->base->num_of_queues;
853 txq_id++) {
854 bool cmd_queue = (txq_id == trans->conf.cmd_queue);
855
856 if (cmd_queue)
857 slots_num = max_t(u32, IWL_CMD_QUEUE_SIZE,
858 trans->mac_cfg->base->min_txq_size);
859 else
860 slots_num = max_t(u32, IWL_DEFAULT_QUEUE_SIZE,
861 trans->mac_cfg->base->min_ba_txq_size);
862 trans_pcie->txqs.txq[txq_id] = &trans_pcie->txq_memory[txq_id];
863 ret = iwl_pcie_txq_alloc(trans, trans_pcie->txqs.txq[txq_id],
864 slots_num, cmd_queue);
865 if (ret) {
866 IWL_ERR(trans, "Tx %d queue alloc failed\n", txq_id);
867 goto error;
868 }
869 trans_pcie->txqs.txq[txq_id]->id = txq_id;
870 }
871
872 return 0;
873
874 error:
875 iwl_pcie_tx_free(trans);
876
877 return ret;
878 }
879
880 /*
881 * iwl_queue_init - Initialize queue's high/low-water and read/write indexes
882 */
iwl_queue_init(struct iwl_txq * q,int slots_num)883 static int iwl_queue_init(struct iwl_txq *q, int slots_num)
884 {
885 q->n_window = slots_num;
886
887 /* slots_num must be power-of-two size, otherwise
888 * iwl_txq_get_cmd_index is broken.
889 */
890 if (WARN_ON(!is_power_of_2(slots_num)))
891 return -EINVAL;
892
893 q->low_mark = q->n_window / 4;
894 if (q->low_mark < 4)
895 q->low_mark = 4;
896
897 q->high_mark = q->n_window / 8;
898 if (q->high_mark < 2)
899 q->high_mark = 2;
900
901 q->write_ptr = 0;
902 q->read_ptr = 0;
903
904 return 0;
905 }
906
iwl_txq_init(struct iwl_trans * trans,struct iwl_txq * txq,int slots_num,bool cmd_queue)907 int iwl_txq_init(struct iwl_trans *trans, struct iwl_txq *txq,
908 int slots_num, bool cmd_queue)
909 {
910 u32 tfd_queue_max_size =
911 trans->mac_cfg->base->max_tfd_queue_size;
912 int ret;
913
914 txq->need_update = false;
915
916 /* max_tfd_queue_size must be power-of-two size, otherwise
917 * iwl_txq_inc_wrap and iwl_txq_dec_wrap are broken.
918 */
919 if (WARN_ONCE(tfd_queue_max_size & (tfd_queue_max_size - 1),
920 "Max tfd queue size must be a power of two, but is %d",
921 tfd_queue_max_size))
922 return -EINVAL;
923
924 /* Initialize queue's high/low-water marks, and head/tail indexes */
925 ret = iwl_queue_init(txq, slots_num);
926 if (ret)
927 return ret;
928
929 spin_lock_init(&txq->lock);
930 spin_lock_init(&txq->reclaim_lock);
931
932 if (cmd_queue) {
933 #if defined(__linux__)
934 static struct lock_class_key iwl_txq_cmd_queue_lock_class;
935
936 lockdep_set_class(&txq->lock, &iwl_txq_cmd_queue_lock_class);
937 #endif
938 }
939
940 __skb_queue_head_init(&txq->overflow_q);
941
942 return 0;
943 }
944
iwl_pcie_tx_init(struct iwl_trans * trans)945 int iwl_pcie_tx_init(struct iwl_trans *trans)
946 {
947 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
948 int ret;
949 int txq_id, slots_num;
950 bool alloc = false;
951
952 if (!trans_pcie->txq_memory) {
953 ret = iwl_pcie_tx_alloc(trans);
954 if (ret)
955 goto error;
956 alloc = true;
957 }
958
959 spin_lock_bh(&trans_pcie->irq_lock);
960
961 /* Turn off all Tx DMA fifos */
962 iwl_scd_deactivate_fifos(trans);
963
964 /* Tell NIC where to find the "keep warm" buffer */
965 iwl_write_direct32(trans, FH_KW_MEM_ADDR_REG,
966 trans_pcie->kw.dma >> 4);
967
968 spin_unlock_bh(&trans_pcie->irq_lock);
969
970 /* Alloc and init all Tx queues, including the command queue (#4/#9) */
971 for (txq_id = 0; txq_id < trans->mac_cfg->base->num_of_queues;
972 txq_id++) {
973 bool cmd_queue = (txq_id == trans->conf.cmd_queue);
974
975 if (cmd_queue)
976 slots_num = max_t(u32, IWL_CMD_QUEUE_SIZE,
977 trans->mac_cfg->base->min_txq_size);
978 else
979 slots_num = max_t(u32, IWL_DEFAULT_QUEUE_SIZE,
980 trans->mac_cfg->base->min_ba_txq_size);
981 ret = iwl_txq_init(trans, trans_pcie->txqs.txq[txq_id], slots_num,
982 cmd_queue);
983 if (ret) {
984 IWL_ERR(trans, "Tx %d queue init failed\n", txq_id);
985 goto error;
986 }
987
988 /*
989 * Tell nic where to find circular buffer of TFDs for a
990 * given Tx queue, and enable the DMA channel used for that
991 * queue.
992 * Circular buffer (TFD queue in DRAM) physical base address
993 */
994 iwl_write_direct32(trans, FH_MEM_CBBC_QUEUE(trans, txq_id),
995 trans_pcie->txqs.txq[txq_id]->dma_addr >> 8);
996 }
997
998 iwl_set_bits_prph(trans, SCD_GP_CTRL, SCD_GP_CTRL_AUTO_ACTIVE_MODE);
999 if (trans->mac_cfg->base->num_of_queues > 20)
1000 iwl_set_bits_prph(trans, SCD_GP_CTRL,
1001 SCD_GP_CTRL_ENABLE_31_QUEUES);
1002
1003 return 0;
1004 error:
1005 /*Upon error, free only if we allocated something */
1006 if (alloc)
1007 iwl_pcie_tx_free(trans);
1008 return ret;
1009 }
1010
iwl_pcie_set_cmd_in_flight(struct iwl_trans * trans,const struct iwl_host_cmd * cmd)1011 static int iwl_pcie_set_cmd_in_flight(struct iwl_trans *trans,
1012 const struct iwl_host_cmd *cmd)
1013 {
1014 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1015
1016 /* Make sure the NIC is still alive in the bus */
1017 if (test_bit(STATUS_TRANS_DEAD, &trans->status))
1018 return -ENODEV;
1019
1020 if (!trans->mac_cfg->base->apmg_wake_up_wa)
1021 return 0;
1022
1023 /*
1024 * wake up the NIC to make sure that the firmware will see the host
1025 * command - we will let the NIC sleep once all the host commands
1026 * returned. This needs to be done only on NICs that have
1027 * apmg_wake_up_wa set (see above.)
1028 */
1029 if (!_iwl_trans_pcie_grab_nic_access(trans, false))
1030 return -EIO;
1031
1032 /*
1033 * In iwl_trans_grab_nic_access(), we've acquired the reg_lock.
1034 * There, we also returned immediately if cmd_hold_nic_awake is
1035 * already true, so it's OK to unconditionally set it to true.
1036 */
1037 trans_pcie->cmd_hold_nic_awake = true;
1038 spin_unlock(&trans_pcie->reg_lock);
1039
1040 return 0;
1041 }
1042
iwl_txq_progress(struct iwl_txq * txq)1043 static void iwl_txq_progress(struct iwl_txq *txq)
1044 {
1045 lockdep_assert_held(&txq->lock);
1046
1047 if (!txq->wd_timeout)
1048 return;
1049
1050 /*
1051 * station is asleep and we send data - that must
1052 * be uAPSD or PS-Poll. Don't rearm the timer.
1053 */
1054 if (txq->frozen)
1055 return;
1056
1057 /*
1058 * if empty delete timer, otherwise move timer forward
1059 * since we're making progress on this queue
1060 */
1061 if (txq->read_ptr == txq->write_ptr)
1062 timer_delete(&txq->stuck_timer);
1063 else
1064 mod_timer(&txq->stuck_timer, jiffies + txq->wd_timeout);
1065 }
1066
iwl_txq_used(const struct iwl_txq * q,int i,int read_ptr,int write_ptr)1067 static inline bool iwl_txq_used(const struct iwl_txq *q, int i,
1068 int read_ptr, int write_ptr)
1069 {
1070 int index = iwl_txq_get_cmd_index(q, i);
1071 int r = iwl_txq_get_cmd_index(q, read_ptr);
1072 int w = iwl_txq_get_cmd_index(q, write_ptr);
1073
1074 return w >= r ?
1075 (index >= r && index < w) :
1076 !(index < r && index >= w);
1077 }
1078
1079 /*
1080 * iwl_pcie_cmdq_reclaim - Reclaim TX command queue entries already Tx'd
1081 *
1082 * When FW advances 'R' index, all entries between old and new 'R' index
1083 * need to be reclaimed. As result, some free space forms. If there is
1084 * enough free space (> low mark), wake the stack that feeds us.
1085 */
iwl_pcie_cmdq_reclaim(struct iwl_trans * trans,int txq_id,int idx)1086 static void iwl_pcie_cmdq_reclaim(struct iwl_trans *trans, int txq_id, int idx)
1087 {
1088 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1089 struct iwl_txq *txq = trans_pcie->txqs.txq[txq_id];
1090 int nfreed = 0;
1091 u16 r;
1092
1093 lockdep_assert_held(&txq->lock);
1094
1095 idx = iwl_txq_get_cmd_index(txq, idx);
1096 r = iwl_txq_get_cmd_index(txq, txq->read_ptr);
1097
1098 if (idx >= trans->mac_cfg->base->max_tfd_queue_size ||
1099 (!iwl_txq_used(txq, idx, txq->read_ptr, txq->write_ptr))) {
1100 WARN_ONCE(test_bit(txq_id, trans_pcie->txqs.queue_used),
1101 "%s: Read index for DMA queue txq id (%d), index %d is out of range [0-%d] %d %d.\n",
1102 __func__, txq_id, idx,
1103 trans->mac_cfg->base->max_tfd_queue_size,
1104 txq->write_ptr, txq->read_ptr);
1105 return;
1106 }
1107
1108 for (idx = iwl_txq_inc_wrap(trans, idx); r != idx;
1109 r = iwl_txq_inc_wrap(trans, r)) {
1110 txq->read_ptr = iwl_txq_inc_wrap(trans, txq->read_ptr);
1111
1112 if (nfreed++ > 0) {
1113 IWL_ERR(trans, "HCMD skipped: index (%d) %d %d\n",
1114 idx, txq->write_ptr, r);
1115 iwl_force_nmi(trans);
1116 }
1117 }
1118
1119 if (txq->read_ptr == txq->write_ptr)
1120 iwl_pcie_clear_cmd_in_flight(trans);
1121
1122 iwl_txq_progress(txq);
1123 }
1124
iwl_pcie_txq_set_ratid_map(struct iwl_trans * trans,u16 ra_tid,u16 txq_id)1125 static int iwl_pcie_txq_set_ratid_map(struct iwl_trans *trans, u16 ra_tid,
1126 u16 txq_id)
1127 {
1128 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1129 u32 tbl_dw_addr;
1130 u32 tbl_dw;
1131 u16 scd_q2ratid;
1132
1133 scd_q2ratid = ra_tid & SCD_QUEUE_RA_TID_MAP_RATID_MSK;
1134
1135 tbl_dw_addr = trans_pcie->scd_base_addr +
1136 SCD_TRANS_TBL_OFFSET_QUEUE(txq_id);
1137
1138 tbl_dw = iwl_trans_read_mem32(trans, tbl_dw_addr);
1139
1140 if (txq_id & 0x1)
1141 tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF);
1142 else
1143 tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000);
1144
1145 iwl_trans_write_mem32(trans, tbl_dw_addr, tbl_dw);
1146
1147 return 0;
1148 }
1149
1150 /* Receiver address (actually, Rx station's index into station table),
1151 * combined with Traffic ID (QOS priority), in format used by Tx Scheduler */
1152 #define BUILD_RAxTID(sta_id, tid) (((sta_id) << 4) + (tid))
1153
iwl_trans_pcie_txq_enable(struct iwl_trans * trans,int txq_id,u16 ssn,const struct iwl_trans_txq_scd_cfg * cfg,unsigned int wdg_timeout)1154 bool iwl_trans_pcie_txq_enable(struct iwl_trans *trans, int txq_id, u16 ssn,
1155 const struct iwl_trans_txq_scd_cfg *cfg,
1156 unsigned int wdg_timeout)
1157 {
1158 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1159 struct iwl_txq *txq = trans_pcie->txqs.txq[txq_id];
1160 int fifo = -1;
1161 bool scd_bug = false;
1162
1163 if (test_and_set_bit(txq_id, trans_pcie->txqs.queue_used))
1164 WARN_ONCE(1, "queue %d already used - expect issues", txq_id);
1165
1166 txq->wd_timeout = msecs_to_jiffies(wdg_timeout);
1167
1168 if (cfg) {
1169 fifo = cfg->fifo;
1170
1171 /* Disable the scheduler prior configuring the cmd queue */
1172 if (txq_id == trans->conf.cmd_queue &&
1173 trans->conf.scd_set_active)
1174 iwl_scd_enable_set_active(trans, 0);
1175
1176 /* Stop this Tx queue before configuring it */
1177 iwl_scd_txq_set_inactive(trans, txq_id);
1178
1179 /* Set this queue as a chain-building queue unless it is CMD */
1180 if (txq_id != trans->conf.cmd_queue)
1181 iwl_scd_txq_set_chain(trans, txq_id);
1182
1183 if (cfg->aggregate) {
1184 u16 ra_tid = BUILD_RAxTID(cfg->sta_id, cfg->tid);
1185
1186 /* Map receiver-address / traffic-ID to this queue */
1187 iwl_pcie_txq_set_ratid_map(trans, ra_tid, txq_id);
1188
1189 /* enable aggregations for the queue */
1190 iwl_scd_txq_enable_agg(trans, txq_id);
1191 txq->ampdu = true;
1192 } else {
1193 /*
1194 * disable aggregations for the queue, this will also
1195 * make the ra_tid mapping configuration irrelevant
1196 * since it is now a non-AGG queue.
1197 */
1198 iwl_scd_txq_disable_agg(trans, txq_id);
1199
1200 ssn = txq->read_ptr;
1201 }
1202 } else {
1203 /*
1204 * If we need to move the SCD write pointer by steps of
1205 * 0x40, 0x80 or 0xc0, it gets stuck. Avoids this and let
1206 * the op_mode know by returning true later.
1207 * Do this only in case cfg is NULL since this trick can
1208 * be done only if we have DQA enabled which is true for mvm
1209 * only. And mvm never sets a cfg pointer.
1210 * This is really ugly, but this is the easiest way out for
1211 * this sad hardware issue.
1212 * This bug has been fixed on devices 9000 and up.
1213 */
1214 scd_bug = !trans->mac_cfg->mq_rx_supported &&
1215 !((ssn - txq->write_ptr) & 0x3f) &&
1216 (ssn != txq->write_ptr);
1217 if (scd_bug)
1218 ssn++;
1219 }
1220
1221 /* Place first TFD at index corresponding to start sequence number.
1222 * Assumes that ssn_idx is valid (!= 0xFFF) */
1223 txq->read_ptr = (ssn & 0xff);
1224 txq->write_ptr = (ssn & 0xff);
1225 iwl_write_direct32(trans, HBUS_TARG_WRPTR,
1226 (ssn & 0xff) | (txq_id << 8));
1227
1228 if (cfg) {
1229 u8 frame_limit = cfg->frame_limit;
1230
1231 iwl_write_prph(trans, SCD_QUEUE_RDPTR(txq_id), ssn);
1232
1233 /* Set up Tx window size and frame limit for this queue */
1234 iwl_trans_write_mem32(trans, trans_pcie->scd_base_addr +
1235 SCD_CONTEXT_QUEUE_OFFSET(txq_id), 0);
1236 iwl_trans_write_mem32(trans,
1237 trans_pcie->scd_base_addr +
1238 SCD_CONTEXT_QUEUE_OFFSET(txq_id) + sizeof(u32),
1239 SCD_QUEUE_CTX_REG2_VAL(WIN_SIZE, frame_limit) |
1240 SCD_QUEUE_CTX_REG2_VAL(FRAME_LIMIT, frame_limit));
1241
1242 /* Set up status area in SRAM, map to Tx DMA/FIFO, activate */
1243 iwl_write_prph(trans, SCD_QUEUE_STATUS_BITS(txq_id),
1244 (1 << SCD_QUEUE_STTS_REG_POS_ACTIVE) |
1245 (cfg->fifo << SCD_QUEUE_STTS_REG_POS_TXF) |
1246 (1 << SCD_QUEUE_STTS_REG_POS_WSL) |
1247 SCD_QUEUE_STTS_REG_MSK);
1248
1249 /* enable the scheduler for this queue (only) */
1250 if (txq_id == trans->conf.cmd_queue &&
1251 trans->conf.scd_set_active)
1252 iwl_scd_enable_set_active(trans, BIT(txq_id));
1253
1254 IWL_DEBUG_TX_QUEUES(trans,
1255 "Activate queue %d on FIFO %d WrPtr: %d\n",
1256 txq_id, fifo, ssn & 0xff);
1257 } else {
1258 IWL_DEBUG_TX_QUEUES(trans,
1259 "Activate queue %d WrPtr: %d\n",
1260 txq_id, ssn & 0xff);
1261 }
1262
1263 return scd_bug;
1264 }
1265
iwl_trans_pcie_txq_set_shared_mode(struct iwl_trans * trans,u32 txq_id,bool shared_mode)1266 void iwl_trans_pcie_txq_set_shared_mode(struct iwl_trans *trans, u32 txq_id,
1267 bool shared_mode)
1268 {
1269 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1270 struct iwl_txq *txq = trans_pcie->txqs.txq[txq_id];
1271
1272 txq->ampdu = !shared_mode;
1273 }
1274
iwl_trans_pcie_txq_disable(struct iwl_trans * trans,int txq_id,bool configure_scd)1275 void iwl_trans_pcie_txq_disable(struct iwl_trans *trans, int txq_id,
1276 bool configure_scd)
1277 {
1278 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1279 u32 stts_addr = trans_pcie->scd_base_addr +
1280 SCD_TX_STTS_QUEUE_OFFSET(txq_id);
1281 static const u32 zero_val[4] = {};
1282
1283 trans_pcie->txqs.txq[txq_id]->frozen_expiry_remainder = 0;
1284 trans_pcie->txqs.txq[txq_id]->frozen = false;
1285
1286 /*
1287 * Upon HW Rfkill - we stop the device, and then stop the queues
1288 * in the op_mode. Just for the sake of the simplicity of the op_mode,
1289 * allow the op_mode to call txq_disable after it already called
1290 * stop_device.
1291 */
1292 if (!test_and_clear_bit(txq_id, trans_pcie->txqs.queue_used)) {
1293 WARN_ONCE(test_bit(STATUS_DEVICE_ENABLED, &trans->status),
1294 "queue %d not used", txq_id);
1295 return;
1296 }
1297
1298 if (configure_scd) {
1299 iwl_scd_txq_set_inactive(trans, txq_id);
1300
1301 iwl_trans_write_mem(trans, stts_addr, (const void *)zero_val,
1302 ARRAY_SIZE(zero_val));
1303 }
1304
1305 iwl_pcie_txq_unmap(trans, txq_id);
1306 trans_pcie->txqs.txq[txq_id]->ampdu = false;
1307
1308 IWL_DEBUG_TX_QUEUES(trans, "Deactivate queue %d\n", txq_id);
1309 }
1310
1311 /*************** HOST COMMAND QUEUE FUNCTIONS *****/
1312
iwl_trans_pcie_block_txq_ptrs(struct iwl_trans * trans,bool block)1313 static void iwl_trans_pcie_block_txq_ptrs(struct iwl_trans *trans, bool block)
1314 {
1315 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1316 int i;
1317
1318 for (i = 0; i < trans->mac_cfg->base->num_of_queues; i++) {
1319 struct iwl_txq *txq = trans_pcie->txqs.txq[i];
1320
1321 if (i == trans->conf.cmd_queue)
1322 continue;
1323
1324 /* we skip the command queue (obviously) so it's OK to nest */
1325 spin_lock_nested(&txq->lock, 1);
1326
1327 if (!block && !(WARN_ON_ONCE(!txq->block))) {
1328 txq->block--;
1329 if (!txq->block) {
1330 iwl_write32(trans, HBUS_TARG_WRPTR,
1331 txq->write_ptr | (i << 8));
1332 }
1333 } else if (block) {
1334 txq->block++;
1335 }
1336
1337 spin_unlock(&txq->lock);
1338 }
1339 }
1340
1341 /*
1342 * iwl_pcie_enqueue_hcmd - enqueue a uCode command
1343 * @priv: device private data point
1344 * @cmd: a pointer to the ucode command structure
1345 *
1346 * The function returns < 0 values to indicate the operation
1347 * failed. On success, it returns the index (>= 0) of command in the
1348 * command queue.
1349 */
iwl_pcie_enqueue_hcmd(struct iwl_trans * trans,struct iwl_host_cmd * cmd)1350 int iwl_pcie_enqueue_hcmd(struct iwl_trans *trans,
1351 struct iwl_host_cmd *cmd)
1352 {
1353 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1354 struct iwl_txq *txq = trans_pcie->txqs.txq[trans->conf.cmd_queue];
1355 struct iwl_device_cmd *out_cmd;
1356 struct iwl_cmd_meta *out_meta;
1357 void *dup_buf = NULL;
1358 dma_addr_t phys_addr;
1359 int idx;
1360 u16 copy_size, cmd_size, tb0_size;
1361 bool had_nocopy = false;
1362 u8 group_id = iwl_cmd_groupid(cmd->id);
1363 int i, ret;
1364 u32 cmd_pos;
1365 const u8 *cmddata[IWL_MAX_CMD_TBS_PER_TFD];
1366 u16 cmdlen[IWL_MAX_CMD_TBS_PER_TFD];
1367 unsigned long flags;
1368
1369 if (WARN(!trans->conf.wide_cmd_header &&
1370 group_id > IWL_ALWAYS_LONG_GROUP,
1371 "unsupported wide command %#x\n", cmd->id))
1372 return -EINVAL;
1373
1374 if (group_id != 0) {
1375 copy_size = sizeof(struct iwl_cmd_header_wide);
1376 cmd_size = sizeof(struct iwl_cmd_header_wide);
1377 } else {
1378 copy_size = sizeof(struct iwl_cmd_header);
1379 cmd_size = sizeof(struct iwl_cmd_header);
1380 }
1381
1382 /* need one for the header if the first is NOCOPY */
1383 BUILD_BUG_ON(IWL_MAX_CMD_TBS_PER_TFD > IWL_NUM_OF_TBS - 1);
1384
1385 for (i = 0; i < IWL_MAX_CMD_TBS_PER_TFD; i++) {
1386 cmddata[i] = cmd->data[i];
1387 cmdlen[i] = cmd->len[i];
1388
1389 if (!cmd->len[i])
1390 continue;
1391
1392 /* need at least IWL_FIRST_TB_SIZE copied */
1393 if (copy_size < IWL_FIRST_TB_SIZE) {
1394 int copy = IWL_FIRST_TB_SIZE - copy_size;
1395
1396 if (copy > cmdlen[i])
1397 copy = cmdlen[i];
1398 cmdlen[i] -= copy;
1399 cmddata[i] += copy;
1400 copy_size += copy;
1401 }
1402
1403 if (cmd->dataflags[i] & IWL_HCMD_DFL_NOCOPY) {
1404 had_nocopy = true;
1405 if (WARN_ON(cmd->dataflags[i] & IWL_HCMD_DFL_DUP)) {
1406 idx = -EINVAL;
1407 goto free_dup_buf;
1408 }
1409 } else if (cmd->dataflags[i] & IWL_HCMD_DFL_DUP) {
1410 /*
1411 * This is also a chunk that isn't copied
1412 * to the static buffer so set had_nocopy.
1413 */
1414 had_nocopy = true;
1415
1416 /* only allowed once */
1417 if (WARN_ON(dup_buf)) {
1418 idx = -EINVAL;
1419 goto free_dup_buf;
1420 }
1421
1422 dup_buf = kmemdup(cmddata[i], cmdlen[i],
1423 GFP_ATOMIC);
1424 if (!dup_buf)
1425 return -ENOMEM;
1426 } else {
1427 /* NOCOPY must not be followed by normal! */
1428 if (WARN_ON(had_nocopy)) {
1429 idx = -EINVAL;
1430 goto free_dup_buf;
1431 }
1432 copy_size += cmdlen[i];
1433 }
1434 cmd_size += cmd->len[i];
1435 }
1436
1437 /*
1438 * If any of the command structures end up being larger than
1439 * the TFD_MAX_PAYLOAD_SIZE and they aren't dynamically
1440 * allocated into separate TFDs, then we will need to
1441 * increase the size of the buffers.
1442 */
1443 if (WARN(copy_size > TFD_MAX_PAYLOAD_SIZE,
1444 "Command %s (%#x) is too large (%d bytes)\n",
1445 iwl_get_cmd_string(trans, cmd->id),
1446 cmd->id, copy_size)) {
1447 idx = -EINVAL;
1448 goto free_dup_buf;
1449 }
1450
1451 spin_lock_irqsave(&txq->lock, flags);
1452
1453 if (iwl_txq_space(trans, txq) < ((cmd->flags & CMD_ASYNC) ? 2 : 1)) {
1454 spin_unlock_irqrestore(&txq->lock, flags);
1455
1456 IWL_ERR(trans, "No space in command queue\n");
1457 iwl_op_mode_nic_error(trans->op_mode,
1458 IWL_ERR_TYPE_CMD_QUEUE_FULL);
1459 iwl_trans_schedule_reset(trans, IWL_ERR_TYPE_CMD_QUEUE_FULL);
1460 idx = -ENOSPC;
1461 goto free_dup_buf;
1462 }
1463
1464 idx = iwl_txq_get_cmd_index(txq, txq->write_ptr);
1465 out_cmd = txq->entries[idx].cmd;
1466 out_meta = &txq->entries[idx].meta;
1467
1468 /* re-initialize, this also marks the SG list as unused */
1469 memset(out_meta, 0, sizeof(*out_meta));
1470 if (cmd->flags & CMD_WANT_SKB)
1471 out_meta->source = cmd;
1472
1473 /* set up the header */
1474 if (group_id != 0) {
1475 out_cmd->hdr_wide.cmd = iwl_cmd_opcode(cmd->id);
1476 out_cmd->hdr_wide.group_id = group_id;
1477 out_cmd->hdr_wide.version = iwl_cmd_version(cmd->id);
1478 out_cmd->hdr_wide.length =
1479 cpu_to_le16(cmd_size -
1480 sizeof(struct iwl_cmd_header_wide));
1481 out_cmd->hdr_wide.reserved = 0;
1482 out_cmd->hdr_wide.sequence =
1483 cpu_to_le16(QUEUE_TO_SEQ(trans->conf.cmd_queue) |
1484 INDEX_TO_SEQ(txq->write_ptr));
1485
1486 cmd_pos = sizeof(struct iwl_cmd_header_wide);
1487 copy_size = sizeof(struct iwl_cmd_header_wide);
1488 } else {
1489 out_cmd->hdr.cmd = iwl_cmd_opcode(cmd->id);
1490 out_cmd->hdr.sequence =
1491 cpu_to_le16(QUEUE_TO_SEQ(trans->conf.cmd_queue) |
1492 INDEX_TO_SEQ(txq->write_ptr));
1493 out_cmd->hdr.group_id = 0;
1494
1495 cmd_pos = sizeof(struct iwl_cmd_header);
1496 copy_size = sizeof(struct iwl_cmd_header);
1497 }
1498
1499 /* and copy the data that needs to be copied */
1500 for (i = 0; i < IWL_MAX_CMD_TBS_PER_TFD; i++) {
1501 int copy;
1502
1503 if (!cmd->len[i])
1504 continue;
1505
1506 /* copy everything if not nocopy/dup */
1507 if (!(cmd->dataflags[i] & (IWL_HCMD_DFL_NOCOPY |
1508 IWL_HCMD_DFL_DUP))) {
1509 copy = cmd->len[i];
1510
1511 memcpy((u8 *)out_cmd + cmd_pos, cmd->data[i], copy);
1512 cmd_pos += copy;
1513 copy_size += copy;
1514 continue;
1515 }
1516
1517 /*
1518 * Otherwise we need at least IWL_FIRST_TB_SIZE copied
1519 * in total (for bi-directional DMA), but copy up to what
1520 * we can fit into the payload for debug dump purposes.
1521 */
1522 copy = min_t(int, TFD_MAX_PAYLOAD_SIZE - cmd_pos, cmd->len[i]);
1523
1524 memcpy((u8 *)out_cmd + cmd_pos, cmd->data[i], copy);
1525 cmd_pos += copy;
1526
1527 /* However, treat copy_size the proper way, we need it below */
1528 if (copy_size < IWL_FIRST_TB_SIZE) {
1529 copy = IWL_FIRST_TB_SIZE - copy_size;
1530
1531 if (copy > cmd->len[i])
1532 copy = cmd->len[i];
1533 copy_size += copy;
1534 }
1535 }
1536
1537 IWL_DEBUG_HC(trans,
1538 "Sending command %s (%.2x.%.2x), seq: 0x%04X, %d bytes at %d[%d]:%d\n",
1539 iwl_get_cmd_string(trans, cmd->id),
1540 group_id, out_cmd->hdr.cmd,
1541 le16_to_cpu(out_cmd->hdr.sequence),
1542 cmd_size, txq->write_ptr, idx, trans->conf.cmd_queue);
1543
1544 /* start the TFD with the minimum copy bytes */
1545 tb0_size = min_t(int, copy_size, IWL_FIRST_TB_SIZE);
1546 memcpy(&txq->first_tb_bufs[idx], &out_cmd->hdr, tb0_size);
1547 iwl_pcie_txq_build_tfd(trans, txq,
1548 iwl_txq_get_first_tb_dma(txq, idx),
1549 tb0_size, true);
1550
1551 /* map first command fragment, if any remains */
1552 if (copy_size > tb0_size) {
1553 phys_addr = dma_map_single(trans->dev,
1554 ((u8 *)&out_cmd->hdr) + tb0_size,
1555 copy_size - tb0_size,
1556 DMA_TO_DEVICE);
1557 if (dma_mapping_error(trans->dev, phys_addr)) {
1558 iwl_txq_gen1_tfd_unmap(trans, out_meta, txq,
1559 txq->write_ptr);
1560 idx = -ENOMEM;
1561 goto out;
1562 }
1563
1564 iwl_pcie_txq_build_tfd(trans, txq, phys_addr,
1565 copy_size - tb0_size, false);
1566 }
1567
1568 /* map the remaining (adjusted) nocopy/dup fragments */
1569 for (i = 0; i < IWL_MAX_CMD_TBS_PER_TFD; i++) {
1570 void *data = (void *)(uintptr_t)cmddata[i];
1571
1572 if (!cmdlen[i])
1573 continue;
1574 if (!(cmd->dataflags[i] & (IWL_HCMD_DFL_NOCOPY |
1575 IWL_HCMD_DFL_DUP)))
1576 continue;
1577 if (cmd->dataflags[i] & IWL_HCMD_DFL_DUP)
1578 data = dup_buf;
1579 phys_addr = dma_map_single(trans->dev, data,
1580 cmdlen[i], DMA_TO_DEVICE);
1581 if (dma_mapping_error(trans->dev, phys_addr)) {
1582 iwl_txq_gen1_tfd_unmap(trans, out_meta, txq,
1583 txq->write_ptr);
1584 idx = -ENOMEM;
1585 goto out;
1586 }
1587
1588 iwl_pcie_txq_build_tfd(trans, txq, phys_addr, cmdlen[i], false);
1589 }
1590
1591 BUILD_BUG_ON(IWL_TFH_NUM_TBS > sizeof(out_meta->tbs) * BITS_PER_BYTE);
1592 out_meta->flags = cmd->flags;
1593 if (WARN_ON_ONCE(txq->entries[idx].free_buf))
1594 kfree_sensitive(txq->entries[idx].free_buf);
1595 txq->entries[idx].free_buf = dup_buf;
1596
1597 trace_iwlwifi_dev_hcmd(trans->dev, cmd, cmd_size, &out_cmd->hdr_wide);
1598
1599 /* start timer if queue currently empty */
1600 if (txq->read_ptr == txq->write_ptr && txq->wd_timeout)
1601 mod_timer(&txq->stuck_timer, jiffies + txq->wd_timeout);
1602
1603 ret = iwl_pcie_set_cmd_in_flight(trans, cmd);
1604 if (ret < 0) {
1605 idx = ret;
1606 goto out;
1607 }
1608
1609 if (cmd->flags & CMD_BLOCK_TXQS)
1610 iwl_trans_pcie_block_txq_ptrs(trans, true);
1611
1612 /* Increment and update queue's write index */
1613 txq->write_ptr = iwl_txq_inc_wrap(trans, txq->write_ptr);
1614 iwl_pcie_txq_inc_wr_ptr(trans, txq);
1615
1616 out:
1617 spin_unlock_irqrestore(&txq->lock, flags);
1618 free_dup_buf:
1619 if (idx < 0)
1620 kfree(dup_buf);
1621 return idx;
1622 }
1623
1624 /*
1625 * iwl_pcie_hcmd_complete - Pull unused buffers off the queue and reclaim them
1626 * @rxb: Rx buffer to reclaim
1627 */
iwl_pcie_hcmd_complete(struct iwl_trans * trans,struct iwl_rx_cmd_buffer * rxb)1628 void iwl_pcie_hcmd_complete(struct iwl_trans *trans,
1629 struct iwl_rx_cmd_buffer *rxb)
1630 {
1631 struct iwl_rx_packet *pkt = rxb_addr(rxb);
1632 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
1633 u8 group_id;
1634 u32 cmd_id;
1635 int txq_id = SEQ_TO_QUEUE(sequence);
1636 int index = SEQ_TO_INDEX(sequence);
1637 int cmd_index;
1638 struct iwl_device_cmd *cmd;
1639 struct iwl_cmd_meta *meta;
1640 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1641 struct iwl_txq *txq = trans_pcie->txqs.txq[trans->conf.cmd_queue];
1642
1643 /* If a Tx command is being handled and it isn't in the actual
1644 * command queue then there a command routing bug has been introduced
1645 * in the queue management code. */
1646 if (IWL_FW_CHECK(trans, txq_id != trans->conf.cmd_queue,
1647 "wrong command queue %d (should be %d), sequence 0x%X readp=%d writep=%d pkt=%*phN\n",
1648 txq_id, trans->conf.cmd_queue, sequence, txq->read_ptr,
1649 txq->write_ptr, 32, pkt))
1650 return;
1651
1652 spin_lock_bh(&txq->lock);
1653
1654 cmd_index = iwl_txq_get_cmd_index(txq, index);
1655 cmd = txq->entries[cmd_index].cmd;
1656 meta = &txq->entries[cmd_index].meta;
1657 group_id = cmd->hdr.group_id;
1658 cmd_id = WIDE_ID(group_id, cmd->hdr.cmd);
1659
1660 if (trans->mac_cfg->gen2)
1661 iwl_txq_gen2_tfd_unmap(trans, meta,
1662 iwl_txq_get_tfd(trans, txq, index));
1663 else
1664 iwl_txq_gen1_tfd_unmap(trans, meta, txq, index);
1665
1666 /* Input error checking is done when commands are added to queue. */
1667 if (meta->flags & CMD_WANT_SKB) {
1668 struct page *p = rxb_steal_page(rxb);
1669
1670 meta->source->resp_pkt = pkt;
1671 #if defined(__linux__)
1672 meta->source->_rx_page_addr = (unsigned long)page_address(p);
1673 #elif defined(__FreeBSD__)
1674 meta->source->_page = p;
1675 #endif
1676 meta->source->_rx_page_order = trans_pcie->rx_page_order;
1677 }
1678
1679 if (meta->flags & CMD_BLOCK_TXQS)
1680 iwl_trans_pcie_block_txq_ptrs(trans, false);
1681
1682 iwl_pcie_cmdq_reclaim(trans, txq_id, index);
1683
1684 if (!(meta->flags & CMD_ASYNC)) {
1685 if (!test_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status)) {
1686 IWL_WARN(trans,
1687 "HCMD_ACTIVE already clear for command %s\n",
1688 iwl_get_cmd_string(trans, cmd_id));
1689 }
1690 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
1691 IWL_DEBUG_INFO(trans, "Clearing HCMD_ACTIVE for command %s\n",
1692 iwl_get_cmd_string(trans, cmd_id));
1693 wake_up(&trans_pcie->wait_command_queue);
1694 }
1695
1696 meta->flags = 0;
1697
1698 spin_unlock_bh(&txq->lock);
1699 }
1700
iwl_fill_data_tbs(struct iwl_trans * trans,struct sk_buff * skb,struct iwl_txq * txq,u8 hdr_len,struct iwl_cmd_meta * out_meta)1701 static int iwl_fill_data_tbs(struct iwl_trans *trans, struct sk_buff *skb,
1702 struct iwl_txq *txq, u8 hdr_len,
1703 struct iwl_cmd_meta *out_meta)
1704 {
1705 u16 head_tb_len;
1706 int i;
1707
1708 /*
1709 * Set up TFD's third entry to point directly to remainder
1710 * of skb's head, if any
1711 */
1712 head_tb_len = skb_headlen(skb) - hdr_len;
1713
1714 if (head_tb_len > 0) {
1715 dma_addr_t tb_phys = dma_map_single(trans->dev,
1716 skb->data + hdr_len,
1717 head_tb_len, DMA_TO_DEVICE);
1718 if (unlikely(dma_mapping_error(trans->dev, tb_phys)))
1719 return -EINVAL;
1720 trace_iwlwifi_dev_tx_tb(trans->dev, skb, skb->data + hdr_len,
1721 tb_phys, head_tb_len);
1722 iwl_pcie_txq_build_tfd(trans, txq, tb_phys, head_tb_len, false);
1723 }
1724
1725 /* set up the remaining entries to point to the data */
1726 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1727 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1728 dma_addr_t tb_phys;
1729 int tb_idx;
1730
1731 if (!skb_frag_size(frag))
1732 continue;
1733
1734 tb_phys = skb_frag_dma_map(trans->dev, frag, 0,
1735 skb_frag_size(frag), DMA_TO_DEVICE);
1736
1737 if (unlikely(dma_mapping_error(trans->dev, tb_phys)))
1738 return -EINVAL;
1739 trace_iwlwifi_dev_tx_tb(trans->dev, skb, skb_frag_address(frag),
1740 tb_phys, skb_frag_size(frag));
1741 tb_idx = iwl_pcie_txq_build_tfd(trans, txq, tb_phys,
1742 skb_frag_size(frag), false);
1743 if (tb_idx < 0)
1744 return tb_idx;
1745
1746 out_meta->tbs |= BIT(tb_idx);
1747 }
1748
1749 return 0;
1750 }
1751
1752 #ifdef CONFIG_INET
iwl_pcie_get_page_hdr(struct iwl_trans * trans,size_t len,struct sk_buff * skb)1753 static void *iwl_pcie_get_page_hdr(struct iwl_trans *trans,
1754 size_t len, struct sk_buff *skb)
1755 {
1756 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1757 struct iwl_tso_hdr_page *p = this_cpu_ptr(trans_pcie->txqs.tso_hdr_page);
1758 struct iwl_tso_page_info *info;
1759 struct page **page_ptr;
1760 dma_addr_t phys;
1761 void *ret;
1762
1763 page_ptr = (void *)((u8 *)skb->cb + trans->conf.cb_data_offs);
1764
1765 if (WARN_ON(*page_ptr))
1766 return NULL;
1767
1768 if (!p->page)
1769 goto alloc;
1770
1771 /*
1772 * Check if there's enough room on this page
1773 *
1774 * Note that we put a page chaining pointer *last* in the
1775 * page - we need it somewhere, and if it's there then we
1776 * avoid DMA mapping the last bits of the page which may
1777 * trigger the 32-bit boundary hardware bug.
1778 *
1779 * (see also get_workaround_page() in tx-gen2.c)
1780 */
1781 if (((unsigned long)p->pos & ~PAGE_MASK) + len < IWL_TSO_PAGE_DATA_SIZE) {
1782 info = IWL_TSO_PAGE_INFO(page_address(p->page));
1783 goto out;
1784 }
1785
1786 /* We don't have enough room on this page, get a new one. */
1787 iwl_pcie_free_and_unmap_tso_page(trans, p->page);
1788
1789 alloc:
1790 p->page = alloc_page(GFP_ATOMIC);
1791 if (!p->page)
1792 return NULL;
1793 p->pos = page_address(p->page);
1794
1795 info = IWL_TSO_PAGE_INFO(page_address(p->page));
1796
1797 /* set the chaining pointer to NULL */
1798 info->next = NULL;
1799
1800 /* Create a DMA mapping for the page */
1801 phys = dma_map_page_attrs(trans->dev, p->page, 0, PAGE_SIZE,
1802 DMA_TO_DEVICE, DMA_ATTR_SKIP_CPU_SYNC);
1803 if (unlikely(dma_mapping_error(trans->dev, phys))) {
1804 __free_page(p->page);
1805 p->page = NULL;
1806
1807 return NULL;
1808 }
1809
1810 /* Store physical address and set use count */
1811 info->dma_addr = phys;
1812 refcount_set(&info->use_count, 1);
1813 out:
1814 *page_ptr = p->page;
1815 /* Return an internal reference for the caller */
1816 refcount_inc(&info->use_count);
1817 ret = p->pos;
1818 p->pos += len;
1819
1820 return ret;
1821 }
1822
1823 /**
1824 * iwl_pcie_get_sgt_tb_phys - Find TB address in mapped SG list
1825 * @sgt: scatter gather table
1826 * @offset: Offset into the mapped memory (i.e. SKB payload data)
1827 * @len: Length of the area
1828 *
1829 * Find the DMA address that corresponds to the SKB payload data at the
1830 * position given by @offset.
1831 *
1832 * Returns: Address for TB entry
1833 */
iwl_pcie_get_sgt_tb_phys(struct sg_table * sgt,unsigned int offset,unsigned int len)1834 dma_addr_t iwl_pcie_get_sgt_tb_phys(struct sg_table *sgt, unsigned int offset,
1835 unsigned int len)
1836 {
1837 struct scatterlist *sg;
1838 unsigned int sg_offset = 0;
1839 int i;
1840
1841 /*
1842 * Search the mapped DMA areas in the SG for the area that contains the
1843 * data at offset with the given length.
1844 */
1845 for_each_sgtable_dma_sg(sgt, sg, i) {
1846 if (offset >= sg_offset &&
1847 offset + len <= sg_offset + sg_dma_len(sg))
1848 return sg_dma_address(sg) + offset - sg_offset;
1849
1850 sg_offset += sg_dma_len(sg);
1851 }
1852
1853 WARN_ON_ONCE(1);
1854
1855 return DMA_MAPPING_ERROR;
1856 }
1857
1858 /**
1859 * iwl_pcie_prep_tso - Prepare TSO page and SKB for sending
1860 * @trans: transport private data
1861 * @skb: the SKB to map
1862 * @cmd_meta: command meta to store the scatter list information for unmapping
1863 * @hdr: output argument for TSO headers
1864 * @hdr_room: requested length for TSO headers
1865 * @offset: offset into the data from which mapping should start
1866 *
1867 * Allocate space for a scatter gather list and TSO headers and map the SKB
1868 * using the scatter gather list. The SKB is unmapped again when the page is
1869 * free'ed again at the end of the operation.
1870 *
1871 * Returns: newly allocated and mapped scatter gather table with list
1872 */
iwl_pcie_prep_tso(struct iwl_trans * trans,struct sk_buff * skb,struct iwl_cmd_meta * cmd_meta,u8 ** hdr,unsigned int hdr_room,unsigned int offset)1873 struct sg_table *iwl_pcie_prep_tso(struct iwl_trans *trans, struct sk_buff *skb,
1874 struct iwl_cmd_meta *cmd_meta,
1875 u8 **hdr, unsigned int hdr_room,
1876 unsigned int offset)
1877 {
1878 struct sg_table *sgt;
1879 unsigned int n_segments = skb_shinfo(skb)->nr_frags + 1;
1880 int orig_nents;
1881
1882 if (WARN_ON_ONCE(skb_has_frag_list(skb)))
1883 return NULL;
1884
1885 *hdr = iwl_pcie_get_page_hdr(trans,
1886 hdr_room + __alignof__(struct sg_table) +
1887 sizeof(struct sg_table) +
1888 n_segments * sizeof(struct scatterlist),
1889 skb);
1890 if (!*hdr)
1891 return NULL;
1892
1893 sgt = (void *)PTR_ALIGN(*hdr + hdr_room, __alignof__(struct sg_table));
1894 sgt->sgl = (void *)(sgt + 1);
1895
1896 sg_init_table(sgt->sgl, n_segments);
1897
1898 /* Only map the data, not the header (it is copied to the TSO page) */
1899 orig_nents = skb_to_sgvec(skb, sgt->sgl, offset, skb->len - offset);
1900 if (WARN_ON_ONCE(orig_nents <= 0))
1901 return NULL;
1902
1903 sgt->orig_nents = orig_nents;
1904
1905 /* And map the entire SKB */
1906 if (dma_map_sgtable(trans->dev, sgt, DMA_TO_DEVICE, 0) < 0)
1907 return NULL;
1908
1909 /* Store non-zero (i.e. valid) offset for unmapping */
1910 cmd_meta->sg_offset = (unsigned long) sgt & ~PAGE_MASK;
1911
1912 return sgt;
1913 }
1914
iwl_fill_data_tbs_amsdu(struct iwl_trans * trans,struct sk_buff * skb,struct iwl_txq * txq,u8 hdr_len,struct iwl_cmd_meta * out_meta,struct iwl_device_tx_cmd * dev_cmd,u16 tb1_len)1915 static int iwl_fill_data_tbs_amsdu(struct iwl_trans *trans, struct sk_buff *skb,
1916 struct iwl_txq *txq, u8 hdr_len,
1917 struct iwl_cmd_meta *out_meta,
1918 struct iwl_device_tx_cmd *dev_cmd,
1919 u16 tb1_len)
1920 {
1921 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1922 struct iwl_tx_cmd_v6 *tx_cmd = (void *)dev_cmd->payload;
1923 struct ieee80211_hdr *hdr = (void *)skb->data;
1924 unsigned int snap_ip_tcp_hdrlen, ip_hdrlen, total_len, hdr_room;
1925 unsigned int mss = skb_shinfo(skb)->gso_size;
1926 unsigned int data_offset = 0;
1927 u16 length, iv_len, amsdu_pad;
1928 dma_addr_t start_hdr_phys;
1929 u8 *start_hdr, *pos_hdr;
1930 struct sg_table *sgt;
1931 struct tso_t tso;
1932
1933 /* if the packet is protected, then it must be CCMP or GCMP */
1934 BUILD_BUG_ON(IEEE80211_CCMP_HDR_LEN != IEEE80211_GCMP_HDR_LEN);
1935 iv_len = ieee80211_has_protected(hdr->frame_control) ?
1936 IEEE80211_CCMP_HDR_LEN : 0;
1937
1938 trace_iwlwifi_dev_tx(trans->dev, skb,
1939 iwl_txq_get_tfd(trans, txq, txq->write_ptr),
1940 trans_pcie->txqs.tfd.size,
1941 &dev_cmd->hdr, IWL_FIRST_TB_SIZE + tb1_len, 0);
1942
1943 ip_hdrlen = skb_network_header_len(skb);
1944 snap_ip_tcp_hdrlen = 8 + ip_hdrlen + tcp_hdrlen(skb);
1945 total_len = skb->len - snap_ip_tcp_hdrlen - hdr_len - iv_len;
1946 amsdu_pad = 0;
1947
1948 /* total amount of header we may need for this A-MSDU */
1949 hdr_room = DIV_ROUND_UP(total_len, mss) *
1950 (3 + snap_ip_tcp_hdrlen + sizeof(struct ethhdr)) + iv_len;
1951
1952 /* Our device supports 9 segments at most, it will fit in 1 page */
1953 sgt = iwl_pcie_prep_tso(trans, skb, out_meta, &start_hdr, hdr_room,
1954 snap_ip_tcp_hdrlen + hdr_len + iv_len);
1955 if (!sgt)
1956 return -ENOMEM;
1957
1958 start_hdr_phys = iwl_pcie_get_tso_page_phys(start_hdr);
1959 pos_hdr = start_hdr;
1960 memcpy(pos_hdr, skb->data + hdr_len, iv_len);
1961 pos_hdr += iv_len;
1962
1963 /*
1964 * Pull the ieee80211 header + IV to be able to use TSO core,
1965 * we will restore it for the tx_status flow.
1966 */
1967 skb_pull(skb, hdr_len + iv_len);
1968
1969 /*
1970 * Remove the length of all the headers that we don't actually
1971 * have in the MPDU by themselves, but that we duplicate into
1972 * all the different MSDUs inside the A-MSDU.
1973 */
1974 le16_add_cpu(&tx_cmd->params.len, -snap_ip_tcp_hdrlen);
1975
1976 tso_start(skb, &tso);
1977
1978 while (total_len) {
1979 /* this is the data left for this subframe */
1980 unsigned int data_left =
1981 min_t(unsigned int, mss, total_len);
1982 unsigned int hdr_tb_len;
1983 dma_addr_t hdr_tb_phys;
1984 u8 *subf_hdrs_start = pos_hdr;
1985
1986 total_len -= data_left;
1987
1988 memset(pos_hdr, 0, amsdu_pad);
1989 pos_hdr += amsdu_pad;
1990 amsdu_pad = (4 - (sizeof(struct ethhdr) + snap_ip_tcp_hdrlen +
1991 data_left)) & 0x3;
1992 ether_addr_copy(pos_hdr, ieee80211_get_DA(hdr));
1993 pos_hdr += ETH_ALEN;
1994 ether_addr_copy(pos_hdr, ieee80211_get_SA(hdr));
1995 pos_hdr += ETH_ALEN;
1996
1997 length = snap_ip_tcp_hdrlen + data_left;
1998 *((__be16 *)pos_hdr) = cpu_to_be16(length);
1999 pos_hdr += sizeof(length);
2000
2001 /*
2002 * This will copy the SNAP as well which will be considered
2003 * as MAC header.
2004 */
2005 tso_build_hdr(skb, pos_hdr, &tso, data_left, !total_len);
2006
2007 pos_hdr += snap_ip_tcp_hdrlen;
2008
2009 hdr_tb_len = pos_hdr - start_hdr;
2010 hdr_tb_phys = iwl_pcie_get_tso_page_phys(start_hdr);
2011
2012 iwl_pcie_txq_build_tfd(trans, txq, hdr_tb_phys,
2013 hdr_tb_len, false);
2014 trace_iwlwifi_dev_tx_tb(trans->dev, skb, start_hdr,
2015 hdr_tb_phys, hdr_tb_len);
2016 /* add this subframe's headers' length to the tx_cmd */
2017 le16_add_cpu(&tx_cmd->params.len, pos_hdr - subf_hdrs_start);
2018
2019 /* prepare the start_hdr for the next subframe */
2020 start_hdr = pos_hdr;
2021
2022 /* put the payload */
2023 while (data_left) {
2024 unsigned int size = min_t(unsigned int, tso.size,
2025 data_left);
2026 dma_addr_t tb_phys;
2027
2028 tb_phys = iwl_pcie_get_sgt_tb_phys(sgt, data_offset, size);
2029 /* Not a real mapping error, use direct comparison */
2030 if (unlikely(tb_phys == DMA_MAPPING_ERROR))
2031 return -EINVAL;
2032
2033 iwl_pcie_txq_build_tfd(trans, txq, tb_phys,
2034 size, false);
2035 trace_iwlwifi_dev_tx_tb(trans->dev, skb, tso.data,
2036 tb_phys, size);
2037
2038 data_left -= size;
2039 data_offset += size;
2040 tso_build_data(skb, &tso, size);
2041 }
2042 }
2043
2044 dma_sync_single_for_device(trans->dev, start_hdr_phys, hdr_room,
2045 DMA_TO_DEVICE);
2046
2047 /* re -add the WiFi header and IV */
2048 skb_push(skb, hdr_len + iv_len);
2049
2050 return 0;
2051 }
2052 #else /* CONFIG_INET */
iwl_fill_data_tbs_amsdu(struct iwl_trans * trans,struct sk_buff * skb,struct iwl_txq * txq,u8 hdr_len,struct iwl_cmd_meta * out_meta,struct iwl_device_tx_cmd * dev_cmd,u16 tb1_len)2053 static int iwl_fill_data_tbs_amsdu(struct iwl_trans *trans, struct sk_buff *skb,
2054 struct iwl_txq *txq, u8 hdr_len,
2055 struct iwl_cmd_meta *out_meta,
2056 struct iwl_device_tx_cmd *dev_cmd,
2057 u16 tb1_len)
2058 {
2059 /* No A-MSDU without CONFIG_INET */
2060 WARN_ON(1);
2061
2062 return -1;
2063 }
2064 #endif /* CONFIG_INET */
2065
2066 #define IWL_TX_CRC_SIZE 4
2067 #define IWL_TX_DELIMITER_SIZE 4
2068
2069 /*
2070 * iwl_txq_gen1_update_byte_cnt_tbl - Set up entry in Tx byte-count array
2071 */
iwl_txq_gen1_update_byte_cnt_tbl(struct iwl_trans * trans,struct iwl_txq * txq,u16 byte_cnt,int num_tbs)2072 static void iwl_txq_gen1_update_byte_cnt_tbl(struct iwl_trans *trans,
2073 struct iwl_txq *txq, u16 byte_cnt,
2074 int num_tbs)
2075 {
2076 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2077 struct iwl_bc_tbl_entry *scd_bc_tbl;
2078 int write_ptr = txq->write_ptr;
2079 int txq_id = txq->id;
2080 u8 sec_ctl = 0;
2081 u16 len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE;
2082 __le16 bc_ent;
2083 struct iwl_device_tx_cmd *dev_cmd = txq->entries[txq->write_ptr].cmd;
2084 struct iwl_tx_cmd_v6 *tx_cmd = (void *)dev_cmd->payload;
2085 u8 sta_id = tx_cmd->params.sta_id;
2086
2087 scd_bc_tbl = trans_pcie->txqs.scd_bc_tbls.addr;
2088
2089 sec_ctl = tx_cmd->params.sec_ctl;
2090
2091 switch (sec_ctl & TX_CMD_SEC_MSK) {
2092 case TX_CMD_SEC_CCM:
2093 len += IEEE80211_CCMP_MIC_LEN;
2094 break;
2095 case TX_CMD_SEC_TKIP:
2096 len += IEEE80211_TKIP_ICV_LEN;
2097 break;
2098 case TX_CMD_SEC_WEP:
2099 len += IEEE80211_WEP_IV_LEN + IEEE80211_WEP_ICV_LEN;
2100 break;
2101 }
2102
2103 if (trans->mac_cfg->device_family >= IWL_DEVICE_FAMILY_7000 &&
2104 trans->mac_cfg->device_family < IWL_DEVICE_FAMILY_AX210)
2105 len = DIV_ROUND_UP(len, 4);
2106
2107 if (WARN_ON(len > 0xFFF || write_ptr >= TFD_QUEUE_SIZE_MAX))
2108 return;
2109
2110 bc_ent = cpu_to_le16(len | (sta_id << 12));
2111
2112 scd_bc_tbl[txq_id * TFD_QUEUE_BC_SIZE + write_ptr].tfd_offset = bc_ent;
2113
2114 if (write_ptr < TFD_QUEUE_SIZE_BC_DUP)
2115 scd_bc_tbl[txq_id * TFD_QUEUE_BC_SIZE + TFD_QUEUE_SIZE_MAX + write_ptr].tfd_offset =
2116 bc_ent;
2117 }
2118
iwl_trans_pcie_tx(struct iwl_trans * trans,struct sk_buff * skb,struct iwl_device_tx_cmd * dev_cmd,int txq_id)2119 int iwl_trans_pcie_tx(struct iwl_trans *trans, struct sk_buff *skb,
2120 struct iwl_device_tx_cmd *dev_cmd, int txq_id)
2121 {
2122 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2123 struct ieee80211_hdr *hdr;
2124 struct iwl_tx_cmd_v6 *tx_cmd = (struct iwl_tx_cmd_v6 *)dev_cmd->payload;
2125 struct iwl_cmd_meta *out_meta;
2126 struct iwl_txq *txq;
2127 dma_addr_t tb0_phys, tb1_phys, scratch_phys;
2128 void *tb1_addr;
2129 void *tfd;
2130 u16 len, tb1_len;
2131 bool wait_write_ptr;
2132 __le16 fc;
2133 u8 hdr_len;
2134 u16 wifi_seq;
2135 bool amsdu;
2136
2137 txq = trans_pcie->txqs.txq[txq_id];
2138
2139 if (WARN_ONCE(!test_bit(txq_id, trans_pcie->txqs.queue_used),
2140 "TX on unused queue %d\n", txq_id))
2141 return -EINVAL;
2142
2143 if (skb_is_nonlinear(skb) &&
2144 skb_shinfo(skb)->nr_frags > IWL_TRANS_PCIE_MAX_FRAGS(trans_pcie) &&
2145 __skb_linearize(skb))
2146 return -ENOMEM;
2147
2148 /* mac80211 always puts the full header into the SKB's head,
2149 * so there's no need to check if it's readable there
2150 */
2151 hdr = (struct ieee80211_hdr *)skb->data;
2152 fc = hdr->frame_control;
2153 hdr_len = ieee80211_hdrlen(fc);
2154
2155 spin_lock(&txq->lock);
2156
2157 if (iwl_txq_space(trans, txq) < txq->high_mark) {
2158 iwl_txq_stop(trans, txq);
2159
2160 /* don't put the packet on the ring, if there is no room */
2161 if (unlikely(iwl_txq_space(trans, txq) < 3)) {
2162 struct iwl_device_tx_cmd **dev_cmd_ptr;
2163
2164 dev_cmd_ptr = (void *)((u8 *)skb->cb +
2165 trans->conf.cb_data_offs +
2166 sizeof(void *));
2167
2168 *dev_cmd_ptr = dev_cmd;
2169 __skb_queue_tail(&txq->overflow_q, skb);
2170
2171 spin_unlock(&txq->lock);
2172 return 0;
2173 }
2174 }
2175
2176 /* In AGG mode, the index in the ring must correspond to the WiFi
2177 * sequence number. This is a HW requirements to help the SCD to parse
2178 * the BA.
2179 * Check here that the packets are in the right place on the ring.
2180 */
2181 wifi_seq = IEEE80211_SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl));
2182 WARN_ONCE(txq->ampdu &&
2183 (wifi_seq & 0xff) != txq->write_ptr,
2184 "Q: %d WiFi Seq %d tfdNum %d",
2185 txq_id, wifi_seq, txq->write_ptr);
2186
2187 /* Set up driver data for this TFD */
2188 txq->entries[txq->write_ptr].skb = skb;
2189 txq->entries[txq->write_ptr].cmd = dev_cmd;
2190
2191 dev_cmd->hdr.sequence =
2192 cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) |
2193 INDEX_TO_SEQ(txq->write_ptr)));
2194
2195 tb0_phys = iwl_txq_get_first_tb_dma(txq, txq->write_ptr);
2196 scratch_phys = tb0_phys + sizeof(struct iwl_cmd_header) +
2197 offsetof(struct iwl_tx_cmd_v6_params, scratch);
2198
2199 tx_cmd->params.dram_lsb_ptr = cpu_to_le32(scratch_phys);
2200 tx_cmd->params.dram_msb_ptr = iwl_get_dma_hi_addr(scratch_phys);
2201
2202 /* Set up first empty entry in queue's array of Tx/cmd buffers */
2203 out_meta = &txq->entries[txq->write_ptr].meta;
2204 memset(out_meta, 0, sizeof(*out_meta));
2205
2206 /*
2207 * The second TB (tb1) points to the remainder of the TX command
2208 * and the 802.11 header - dword aligned size
2209 * (This calculation modifies the TX command, so do it before the
2210 * setup of the first TB)
2211 */
2212 len = sizeof(struct iwl_tx_cmd_v6) + sizeof(struct iwl_cmd_header) +
2213 hdr_len - IWL_FIRST_TB_SIZE;
2214 /* do not align A-MSDU to dword as the subframe header aligns it */
2215 amsdu = ieee80211_is_data_qos(fc) &&
2216 (*ieee80211_get_qos_ctl(hdr) &
2217 IEEE80211_QOS_CTL_A_MSDU_PRESENT);
2218 if (!amsdu) {
2219 tb1_len = ALIGN(len, 4);
2220 /* Tell NIC about any 2-byte padding after MAC header */
2221 if (tb1_len != len)
2222 tx_cmd->params.tx_flags |= cpu_to_le32(TX_CMD_FLG_MH_PAD);
2223 } else {
2224 tb1_len = len;
2225 }
2226
2227 /*
2228 * The first TB points to bi-directional DMA data, we'll
2229 * memcpy the data into it later.
2230 */
2231 iwl_pcie_txq_build_tfd(trans, txq, tb0_phys,
2232 IWL_FIRST_TB_SIZE, true);
2233
2234 /* there must be data left over for TB1 or this code must be changed */
2235 BUILD_BUG_ON(sizeof(struct iwl_tx_cmd_v6) < IWL_FIRST_TB_SIZE);
2236 BUILD_BUG_ON(sizeof(struct iwl_cmd_header) +
2237 offsetofend(struct iwl_tx_cmd_v6_params, scratch) >
2238 IWL_FIRST_TB_SIZE);
2239
2240 /* map the data for TB1 */
2241 tb1_addr = ((u8 *)&dev_cmd->hdr) + IWL_FIRST_TB_SIZE;
2242 tb1_phys = dma_map_single(trans->dev, tb1_addr, tb1_len, DMA_TO_DEVICE);
2243 if (unlikely(dma_mapping_error(trans->dev, tb1_phys)))
2244 goto out_err;
2245 iwl_pcie_txq_build_tfd(trans, txq, tb1_phys, tb1_len, false);
2246
2247 trace_iwlwifi_dev_tx(trans->dev, skb,
2248 iwl_txq_get_tfd(trans, txq, txq->write_ptr),
2249 trans_pcie->txqs.tfd.size,
2250 &dev_cmd->hdr, IWL_FIRST_TB_SIZE + tb1_len,
2251 hdr_len);
2252
2253 /*
2254 * If gso_size wasn't set, don't give the frame "amsdu treatment"
2255 * (adding subframes, etc.).
2256 * This can happen in some testing flows when the amsdu was already
2257 * pre-built, and we just need to send the resulting skb.
2258 */
2259 if (amsdu && skb_shinfo(skb)->gso_size) {
2260 if (unlikely(iwl_fill_data_tbs_amsdu(trans, skb, txq, hdr_len,
2261 out_meta, dev_cmd,
2262 tb1_len)))
2263 goto out_err;
2264 } else {
2265 struct sk_buff *frag;
2266
2267 if (unlikely(iwl_fill_data_tbs(trans, skb, txq, hdr_len,
2268 out_meta)))
2269 goto out_err;
2270
2271 skb_walk_frags(skb, frag) {
2272 if (unlikely(iwl_fill_data_tbs(trans, frag, txq, 0,
2273 out_meta)))
2274 goto out_err;
2275 }
2276 }
2277
2278 /* building the A-MSDU might have changed this data, so memcpy it now */
2279 memcpy(&txq->first_tb_bufs[txq->write_ptr], dev_cmd, IWL_FIRST_TB_SIZE);
2280
2281 tfd = iwl_txq_get_tfd(trans, txq, txq->write_ptr);
2282 /* Set up entry for this TFD in Tx byte-count array */
2283 iwl_txq_gen1_update_byte_cnt_tbl(trans, txq, le16_to_cpu(tx_cmd->params.len),
2284 iwl_txq_gen1_tfd_get_num_tbs(tfd));
2285
2286 wait_write_ptr = ieee80211_has_morefrags(fc);
2287
2288 /* start timer if queue currently empty */
2289 if (txq->read_ptr == txq->write_ptr && txq->wd_timeout) {
2290 /*
2291 * If the TXQ is active, then set the timer, if not,
2292 * set the timer in remainder so that the timer will
2293 * be armed with the right value when the station will
2294 * wake up.
2295 */
2296 if (!txq->frozen)
2297 mod_timer(&txq->stuck_timer,
2298 jiffies + txq->wd_timeout);
2299 else
2300 txq->frozen_expiry_remainder = txq->wd_timeout;
2301 }
2302
2303 /* Tell device the write index *just past* this latest filled TFD */
2304 txq->write_ptr = iwl_txq_inc_wrap(trans, txq->write_ptr);
2305 if (!wait_write_ptr)
2306 iwl_pcie_txq_inc_wr_ptr(trans, txq);
2307
2308 /*
2309 * At this point the frame is "transmitted" successfully
2310 * and we will get a TX status notification eventually.
2311 */
2312 spin_unlock(&txq->lock);
2313 return 0;
2314 out_err:
2315 iwl_txq_gen1_tfd_unmap(trans, out_meta, txq, txq->write_ptr);
2316 spin_unlock(&txq->lock);
2317 return -1;
2318 }
2319
iwl_txq_gen1_inval_byte_cnt_tbl(struct iwl_trans * trans,struct iwl_txq * txq,int read_ptr)2320 static void iwl_txq_gen1_inval_byte_cnt_tbl(struct iwl_trans *trans,
2321 struct iwl_txq *txq,
2322 int read_ptr)
2323 {
2324 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2325 struct iwl_bc_tbl_entry *scd_bc_tbl = trans_pcie->txqs.scd_bc_tbls.addr;
2326 int txq_id = txq->id;
2327 u8 sta_id = 0;
2328 __le16 bc_ent;
2329 struct iwl_device_tx_cmd *dev_cmd = txq->entries[read_ptr].cmd;
2330 struct iwl_tx_cmd_v6 *tx_cmd = (void *)dev_cmd->payload;
2331
2332 WARN_ON(read_ptr >= TFD_QUEUE_SIZE_MAX);
2333
2334 if (txq_id != trans->conf.cmd_queue)
2335 sta_id = tx_cmd->params.sta_id;
2336
2337 bc_ent = cpu_to_le16(1 | (sta_id << 12));
2338
2339 scd_bc_tbl[txq_id * TFD_QUEUE_BC_SIZE + read_ptr].tfd_offset = bc_ent;
2340
2341 if (read_ptr < TFD_QUEUE_SIZE_BC_DUP)
2342 scd_bc_tbl[txq_id * TFD_QUEUE_BC_SIZE + TFD_QUEUE_SIZE_MAX + read_ptr].tfd_offset =
2343 bc_ent;
2344 }
2345
2346 /* Frees buffers until index _not_ inclusive */
iwl_pcie_reclaim(struct iwl_trans * trans,int txq_id,int ssn,struct sk_buff_head * skbs,bool is_flush)2347 void iwl_pcie_reclaim(struct iwl_trans *trans, int txq_id, int ssn,
2348 struct sk_buff_head *skbs, bool is_flush)
2349 {
2350 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2351 struct iwl_txq *txq = trans_pcie->txqs.txq[txq_id];
2352 int tfd_num, read_ptr, last_to_free;
2353 int txq_read_ptr, txq_write_ptr;
2354
2355 /* This function is not meant to release cmd queue*/
2356 if (WARN_ON(txq_id == trans->conf.cmd_queue))
2357 return;
2358
2359 if (WARN_ON(!txq))
2360 return;
2361
2362 tfd_num = iwl_txq_get_cmd_index(txq, ssn);
2363
2364 spin_lock_bh(&txq->reclaim_lock);
2365
2366 spin_lock(&txq->lock);
2367 txq_read_ptr = txq->read_ptr;
2368 txq_write_ptr = txq->write_ptr;
2369 spin_unlock(&txq->lock);
2370
2371 /* There is nothing to do if we are flushing an empty queue */
2372 if (is_flush && txq_write_ptr == txq_read_ptr)
2373 goto out;
2374
2375 read_ptr = iwl_txq_get_cmd_index(txq, txq_read_ptr);
2376
2377 if (!test_bit(txq_id, trans_pcie->txqs.queue_used)) {
2378 IWL_DEBUG_TX_QUEUES(trans, "Q %d inactive - ignoring idx %d\n",
2379 txq_id, ssn);
2380 goto out;
2381 }
2382
2383 if (read_ptr == tfd_num)
2384 goto out;
2385
2386 IWL_DEBUG_TX_REPLY(trans, "[Q %d] %d (%d) -> %d (%d)\n",
2387 txq_id, read_ptr, txq_read_ptr, tfd_num, ssn);
2388
2389 /* Since we free until index _not_ inclusive, the one before index is
2390 * the last we will free. This one must be used
2391 */
2392 last_to_free = iwl_txq_dec_wrap(trans, tfd_num);
2393
2394 if (!iwl_txq_used(txq, last_to_free, txq_read_ptr, txq_write_ptr)) {
2395 IWL_ERR(trans,
2396 "%s: Read index for txq id (%d), last_to_free %d is out of range [0-%d] %d %d.\n",
2397 __func__, txq_id, last_to_free,
2398 trans->mac_cfg->base->max_tfd_queue_size,
2399 txq_write_ptr, txq_read_ptr);
2400
2401 iwl_op_mode_time_point(trans->op_mode,
2402 IWL_FW_INI_TIME_POINT_FAKE_TX,
2403 NULL);
2404 goto out;
2405 }
2406
2407 if (WARN_ON(!skb_queue_empty(skbs)))
2408 goto out;
2409
2410 for (;
2411 read_ptr != tfd_num;
2412 txq_read_ptr = iwl_txq_inc_wrap(trans, txq_read_ptr),
2413 read_ptr = iwl_txq_get_cmd_index(txq, txq_read_ptr)) {
2414 struct iwl_cmd_meta *cmd_meta = &txq->entries[read_ptr].meta;
2415 struct sk_buff *skb = txq->entries[read_ptr].skb;
2416
2417 if (WARN_ONCE(!skb, "no SKB at %d (%d) on queue %d\n",
2418 read_ptr, txq_read_ptr, txq_id))
2419 continue;
2420
2421 iwl_pcie_free_tso_pages(trans, skb, cmd_meta);
2422
2423 __skb_queue_tail(skbs, skb);
2424
2425 txq->entries[read_ptr].skb = NULL;
2426
2427 if (!trans->mac_cfg->gen2)
2428 iwl_txq_gen1_inval_byte_cnt_tbl(trans, txq,
2429 txq_read_ptr);
2430
2431 iwl_txq_free_tfd(trans, txq, txq_read_ptr);
2432 }
2433
2434 spin_lock(&txq->lock);
2435 txq->read_ptr = txq_read_ptr;
2436
2437 iwl_txq_progress(txq);
2438
2439 if (iwl_txq_space(trans, txq) > txq->low_mark &&
2440 test_bit(txq_id, trans_pcie->txqs.queue_stopped)) {
2441 struct sk_buff_head overflow_skbs;
2442 struct sk_buff *skb;
2443
2444 __skb_queue_head_init(&overflow_skbs);
2445 skb_queue_splice_init(&txq->overflow_q,
2446 is_flush ? skbs : &overflow_skbs);
2447
2448 /*
2449 * We are going to transmit from the overflow queue.
2450 * Remember this state so that wait_for_txq_empty will know we
2451 * are adding more packets to the TFD queue. It cannot rely on
2452 * the state of &txq->overflow_q, as we just emptied it, but
2453 * haven't TXed the content yet.
2454 */
2455 txq->overflow_tx = true;
2456
2457 /*
2458 * This is tricky: we are in reclaim path and are holding
2459 * reclaim_lock, so noone will try to access the txq data
2460 * from that path. We stopped tx, so we can't have tx as well.
2461 * Bottom line, we can unlock and re-lock later.
2462 */
2463 spin_unlock(&txq->lock);
2464
2465 while ((skb = __skb_dequeue(&overflow_skbs))) {
2466 struct iwl_device_tx_cmd *dev_cmd_ptr;
2467
2468 dev_cmd_ptr = *(void **)((u8 *)skb->cb +
2469 trans->conf.cb_data_offs +
2470 sizeof(void *));
2471
2472 /*
2473 * Note that we can very well be overflowing again.
2474 * In that case, iwl_txq_space will be small again
2475 * and we won't wake mac80211's queue.
2476 */
2477 iwl_trans_tx(trans, skb, dev_cmd_ptr, txq_id);
2478 }
2479
2480 if (iwl_txq_space(trans, txq) > txq->low_mark)
2481 iwl_trans_pcie_wake_queue(trans, txq);
2482
2483 spin_lock(&txq->lock);
2484 txq->overflow_tx = false;
2485 }
2486
2487 spin_unlock(&txq->lock);
2488 out:
2489 spin_unlock_bh(&txq->reclaim_lock);
2490 }
2491
2492 /* Set wr_ptr of specific device and txq */
iwl_pcie_set_q_ptrs(struct iwl_trans * trans,int txq_id,int ptr)2493 void iwl_pcie_set_q_ptrs(struct iwl_trans *trans, int txq_id, int ptr)
2494 {
2495 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2496 struct iwl_txq *txq = trans_pcie->txqs.txq[txq_id];
2497
2498 spin_lock_bh(&txq->lock);
2499
2500 txq->write_ptr = ptr;
2501 txq->read_ptr = txq->write_ptr;
2502
2503 spin_unlock_bh(&txq->lock);
2504 }
2505
iwl_pcie_freeze_txq_timer(struct iwl_trans * trans,unsigned long txqs,bool freeze)2506 void iwl_pcie_freeze_txq_timer(struct iwl_trans *trans,
2507 unsigned long txqs, bool freeze)
2508 {
2509 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2510 int queue;
2511
2512 for_each_set_bit(queue, &txqs, BITS_PER_LONG) {
2513 struct iwl_txq *txq = trans_pcie->txqs.txq[queue];
2514 unsigned long now;
2515
2516 spin_lock_bh(&txq->lock);
2517
2518 now = jiffies;
2519
2520 if (txq->frozen == freeze)
2521 goto next_queue;
2522
2523 IWL_DEBUG_TX_QUEUES(trans, "%s TXQ %d\n",
2524 freeze ? "Freezing" : "Waking", queue);
2525
2526 txq->frozen = freeze;
2527
2528 if (txq->read_ptr == txq->write_ptr)
2529 goto next_queue;
2530
2531 if (freeze) {
2532 if (unlikely(time_after(now,
2533 txq->stuck_timer.expires))) {
2534 /*
2535 * The timer should have fired, maybe it is
2536 * spinning right now on the lock.
2537 */
2538 goto next_queue;
2539 }
2540 /* remember how long until the timer fires */
2541 txq->frozen_expiry_remainder =
2542 txq->stuck_timer.expires - now;
2543 timer_delete(&txq->stuck_timer);
2544 goto next_queue;
2545 }
2546
2547 /*
2548 * Wake a non-empty queue -> arm timer with the
2549 * remainder before it froze
2550 */
2551 mod_timer(&txq->stuck_timer,
2552 now + txq->frozen_expiry_remainder);
2553
2554 next_queue:
2555 spin_unlock_bh(&txq->lock);
2556 }
2557 }
2558
2559 #define HOST_COMPLETE_TIMEOUT (2 * HZ)
2560
iwl_trans_pcie_send_hcmd_sync(struct iwl_trans * trans,struct iwl_host_cmd * cmd,const char * cmd_str)2561 static int iwl_trans_pcie_send_hcmd_sync(struct iwl_trans *trans,
2562 struct iwl_host_cmd *cmd,
2563 const char *cmd_str)
2564 {
2565 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2566 struct iwl_txq *txq = trans_pcie->txqs.txq[trans->conf.cmd_queue];
2567 int cmd_idx;
2568 int ret;
2569
2570 IWL_DEBUG_INFO(trans, "Attempting to send sync command %s\n", cmd_str);
2571
2572 if (WARN(test_and_set_bit(STATUS_SYNC_HCMD_ACTIVE,
2573 &trans->status),
2574 "Command %s: a command is already active!\n", cmd_str))
2575 return -EIO;
2576
2577 IWL_DEBUG_INFO(trans, "Setting HCMD_ACTIVE for command %s\n", cmd_str);
2578
2579 if (trans->mac_cfg->gen2)
2580 cmd_idx = iwl_pcie_gen2_enqueue_hcmd(trans, cmd);
2581 else
2582 cmd_idx = iwl_pcie_enqueue_hcmd(trans, cmd);
2583
2584 if (cmd_idx < 0) {
2585 ret = cmd_idx;
2586 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
2587 IWL_ERR(trans, "Error sending %s: enqueue_hcmd failed: %d\n",
2588 cmd_str, ret);
2589 return ret;
2590 }
2591
2592 ret = wait_event_timeout(trans_pcie->wait_command_queue,
2593 !test_bit(STATUS_SYNC_HCMD_ACTIVE,
2594 &trans->status),
2595 HOST_COMPLETE_TIMEOUT);
2596 if (!ret) {
2597 IWL_ERR(trans, "Error sending %s: time out after %dms.\n",
2598 cmd_str, jiffies_to_msecs(HOST_COMPLETE_TIMEOUT));
2599
2600 IWL_ERR(trans, "Current CMD queue read_ptr %d write_ptr %d\n",
2601 txq->read_ptr, txq->write_ptr);
2602
2603 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
2604 IWL_DEBUG_INFO(trans, "Clearing HCMD_ACTIVE for command %s\n",
2605 cmd_str);
2606 ret = -ETIMEDOUT;
2607
2608 iwl_trans_pcie_sync_nmi(trans);
2609 goto cancel;
2610 }
2611
2612 if (test_bit(STATUS_FW_ERROR, &trans->status)) {
2613 if (trans->suppress_cmd_error_once) {
2614 trans->suppress_cmd_error_once = false;
2615 } else {
2616 IWL_ERR(trans, "FW error in SYNC CMD %s\n", cmd_str);
2617 dump_stack();
2618 }
2619 ret = -EIO;
2620 goto cancel;
2621 }
2622
2623 if (!(cmd->flags & CMD_SEND_IN_RFKILL) &&
2624 test_bit(STATUS_RFKILL_OPMODE, &trans->status)) {
2625 IWL_DEBUG_RF_KILL(trans, "RFKILL in SYNC CMD... no rsp\n");
2626 ret = -ERFKILL;
2627 goto cancel;
2628 }
2629
2630 if ((cmd->flags & CMD_WANT_SKB) && !cmd->resp_pkt) {
2631 IWL_ERR(trans, "Error: Response NULL in '%s'\n", cmd_str);
2632 ret = -EIO;
2633 goto cancel;
2634 }
2635
2636 return 0;
2637
2638 cancel:
2639 if (cmd->flags & CMD_WANT_SKB) {
2640 /*
2641 * Cancel the CMD_WANT_SKB flag for the cmd in the
2642 * TX cmd queue. Otherwise in case the cmd comes
2643 * in later, it will possibly set an invalid
2644 * address (cmd->meta.source).
2645 */
2646 txq->entries[cmd_idx].meta.flags &= ~CMD_WANT_SKB;
2647 }
2648
2649 if (cmd->resp_pkt) {
2650 iwl_free_resp(cmd);
2651 cmd->resp_pkt = NULL;
2652 }
2653
2654 return ret;
2655 }
2656
iwl_trans_pcie_send_hcmd(struct iwl_trans * trans,struct iwl_host_cmd * cmd)2657 int iwl_trans_pcie_send_hcmd(struct iwl_trans *trans,
2658 struct iwl_host_cmd *cmd)
2659 {
2660 const char *cmd_str = iwl_get_cmd_string(trans, cmd->id);
2661
2662 /* Make sure the NIC is still alive in the bus */
2663 if (test_bit(STATUS_TRANS_DEAD, &trans->status))
2664 return -ENODEV;
2665
2666 if (!(cmd->flags & CMD_SEND_IN_RFKILL) &&
2667 test_bit(STATUS_RFKILL_OPMODE, &trans->status)) {
2668 IWL_DEBUG_RF_KILL(trans, "Dropping CMD 0x%x: RF KILL\n",
2669 cmd->id);
2670 return -ERFKILL;
2671 }
2672
2673 if (cmd->flags & CMD_ASYNC) {
2674 int ret;
2675
2676 IWL_DEBUG_INFO(trans, "Sending async command %s\n", cmd_str);
2677
2678 /* An asynchronous command can not expect an SKB to be set. */
2679 if (WARN_ON(cmd->flags & CMD_WANT_SKB))
2680 return -EINVAL;
2681
2682 if (trans->mac_cfg->gen2)
2683 ret = iwl_pcie_gen2_enqueue_hcmd(trans, cmd);
2684 else
2685 ret = iwl_pcie_enqueue_hcmd(trans, cmd);
2686
2687 if (ret < 0) {
2688 IWL_ERR(trans,
2689 "Error sending %s: enqueue_hcmd failed: %d\n",
2690 iwl_get_cmd_string(trans, cmd->id), ret);
2691 return ret;
2692 }
2693 return 0;
2694 }
2695
2696 return iwl_trans_pcie_send_hcmd_sync(trans, cmd, cmd_str);
2697 }
2698