1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * (C) 2018 MediaTek Inc. 4 * Copyright (C) 2022 BayLibre SAS 5 * Authors: Fabien Parent <fparent@baylibre.com> 6 * Bernhard Rosenkränzer <bero@baylibre.com> 7 * Alexandre Mergnat <amergnat@baylibre.com> 8 */ 9 10#include <dt-bindings/clock/mediatek,mt8365-clk.h> 11#include <dt-bindings/interrupt-controller/arm-gic.h> 12#include <dt-bindings/interrupt-controller/irq.h> 13#include <dt-bindings/memory/mediatek,mt8365-larb-port.h> 14#include <dt-bindings/phy/phy.h> 15#include <dt-bindings/power/mediatek,mt8365-power.h> 16 17/ { 18 compatible = "mediatek,mt8365"; 19 interrupt-parent = <&sysirq>; 20 #address-cells = <2>; 21 #size-cells = <2>; 22 23 aliases { 24 aal0 = &aal0; 25 ccorr0 = &ccorr0; 26 color0 = &color0; 27 dither0 = &dither0; 28 dpi0 = &dpi0; 29 dsi0 = &dsi0; 30 gamma0 = &gamma0; 31 ovl0 = &ovl0; 32 rdma0 = &rdma0; 33 rdma1 = &rdma1; 34 }; 35 36 cpus { 37 #address-cells = <1>; 38 #size-cells = <0>; 39 40 cluster0_opp: opp-table-0 { 41 compatible = "operating-points-v2"; 42 opp-shared; 43 44 opp-850000000 { 45 opp-hz = /bits/ 64 <850000000>; 46 opp-microvolt = <650000>; 47 }; 48 49 opp-918000000 { 50 opp-hz = /bits/ 64 <918000000>; 51 opp-microvolt = <668750>; 52 }; 53 54 opp-987000000 { 55 opp-hz = /bits/ 64 <987000000>; 56 opp-microvolt = <687500>; 57 }; 58 59 opp-1056000000 { 60 opp-hz = /bits/ 64 <1056000000>; 61 opp-microvolt = <706250>; 62 }; 63 64 opp-1125000000 { 65 opp-hz = /bits/ 64 <1125000000>; 66 opp-microvolt = <725000>; 67 }; 68 69 opp-1216000000 { 70 opp-hz = /bits/ 64 <1216000000>; 71 opp-microvolt = <750000>; 72 }; 73 74 opp-1308000000 { 75 opp-hz = /bits/ 64 <1308000000>; 76 opp-microvolt = <775000>; 77 }; 78 79 opp-1400000000 { 80 opp-hz = /bits/ 64 <1400000000>; 81 opp-microvolt = <800000>; 82 }; 83 84 opp-1466000000 { 85 opp-hz = /bits/ 64 <1466000000>; 86 opp-microvolt = <825000>; 87 }; 88 89 opp-1533000000 { 90 opp-hz = /bits/ 64 <1533000000>; 91 opp-microvolt = <850000>; 92 }; 93 94 opp-1633000000 { 95 opp-hz = /bits/ 64 <1633000000>; 96 opp-microvolt = <887500>; 97 }; 98 99 opp-1700000000 { 100 opp-hz = /bits/ 64 <1700000000>; 101 opp-microvolt = <912500>; 102 }; 103 104 opp-1767000000 { 105 opp-hz = /bits/ 64 <1767000000>; 106 opp-microvolt = <937500>; 107 }; 108 109 opp-1834000000 { 110 opp-hz = /bits/ 64 <1834000000>; 111 opp-microvolt = <962500>; 112 }; 113 114 opp-1917000000 { 115 opp-hz = /bits/ 64 <1917000000>; 116 opp-microvolt = <993750>; 117 }; 118 119 opp-2001000000 { 120 opp-hz = /bits/ 64 <2001000000>; 121 opp-microvolt = <1025000>; 122 }; 123 }; 124 125 cpu-map { 126 cluster0 { 127 core0 { 128 cpu = <&cpu0>; 129 }; 130 core1 { 131 cpu = <&cpu1>; 132 }; 133 core2 { 134 cpu = <&cpu2>; 135 }; 136 core3 { 137 cpu = <&cpu3>; 138 }; 139 }; 140 }; 141 142 cpu0: cpu@0 { 143 device_type = "cpu"; 144 compatible = "arm,cortex-a53"; 145 reg = <0x0>; 146 #cooling-cells = <2>; 147 enable-method = "psci"; 148 cpu-idle-states = <&CPU_MCDI &CLUSTER_MCDI &CLUSTER_DPIDLE>; 149 i-cache-size = <0x8000>; 150 i-cache-line-size = <64>; 151 i-cache-sets = <256>; 152 d-cache-size = <0x8000>; 153 d-cache-line-size = <64>; 154 d-cache-sets = <256>; 155 next-level-cache = <&l2>; 156 clocks = <&mcucfg CLK_MCU_BUS_SEL>, 157 <&apmixedsys CLK_APMIXED_MAINPLL>; 158 clock-names = "cpu", "intermediate"; 159 operating-points-v2 = <&cluster0_opp>; 160 }; 161 162 cpu1: cpu@1 { 163 device_type = "cpu"; 164 compatible = "arm,cortex-a53"; 165 reg = <0x1>; 166 #cooling-cells = <2>; 167 enable-method = "psci"; 168 cpu-idle-states = <&CPU_MCDI &CLUSTER_MCDI &CLUSTER_DPIDLE>; 169 i-cache-size = <0x8000>; 170 i-cache-line-size = <64>; 171 i-cache-sets = <256>; 172 d-cache-size = <0x8000>; 173 d-cache-line-size = <64>; 174 d-cache-sets = <256>; 175 next-level-cache = <&l2>; 176 clocks = <&mcucfg CLK_MCU_BUS_SEL>, 177 <&apmixedsys CLK_APMIXED_MAINPLL>; 178 clock-names = "cpu", "intermediate", "armpll"; 179 operating-points-v2 = <&cluster0_opp>; 180 }; 181 182 cpu2: cpu@2 { 183 device_type = "cpu"; 184 compatible = "arm,cortex-a53"; 185 reg = <0x2>; 186 #cooling-cells = <2>; 187 enable-method = "psci"; 188 cpu-idle-states = <&CPU_MCDI &CLUSTER_MCDI &CLUSTER_DPIDLE>; 189 i-cache-size = <0x8000>; 190 i-cache-line-size = <64>; 191 i-cache-sets = <256>; 192 d-cache-size = <0x8000>; 193 d-cache-line-size = <64>; 194 d-cache-sets = <256>; 195 next-level-cache = <&l2>; 196 clocks = <&mcucfg CLK_MCU_BUS_SEL>, 197 <&apmixedsys CLK_APMIXED_MAINPLL>; 198 clock-names = "cpu", "intermediate", "armpll"; 199 operating-points-v2 = <&cluster0_opp>; 200 }; 201 202 cpu3: cpu@3 { 203 device_type = "cpu"; 204 compatible = "arm,cortex-a53"; 205 reg = <0x3>; 206 #cooling-cells = <2>; 207 enable-method = "psci"; 208 cpu-idle-states = <&CPU_MCDI &CLUSTER_MCDI &CLUSTER_DPIDLE>; 209 i-cache-size = <0x8000>; 210 i-cache-line-size = <64>; 211 i-cache-sets = <256>; 212 d-cache-size = <0x8000>; 213 d-cache-line-size = <64>; 214 d-cache-sets = <256>; 215 next-level-cache = <&l2>; 216 clocks = <&mcucfg CLK_MCU_BUS_SEL>, 217 <&apmixedsys CLK_APMIXED_MAINPLL>; 218 clock-names = "cpu", "intermediate", "armpll"; 219 operating-points-v2 = <&cluster0_opp>; 220 }; 221 222 idle-states { 223 entry-method = "psci"; 224 225 CPU_MCDI: cpu-mcdi { 226 compatible = "arm,idle-state"; 227 local-timer-stop; 228 arm,psci-suspend-param = <0x00010001>; 229 entry-latency-us = <300>; 230 exit-latency-us = <200>; 231 min-residency-us = <1000>; 232 }; 233 234 CLUSTER_MCDI: cluster-mcdi { 235 compatible = "arm,idle-state"; 236 local-timer-stop; 237 arm,psci-suspend-param = <0x01010001>; 238 entry-latency-us = <350>; 239 exit-latency-us = <250>; 240 min-residency-us = <1200>; 241 }; 242 243 CLUSTER_DPIDLE: cluster-dpidle { 244 compatible = "arm,idle-state"; 245 local-timer-stop; 246 arm,psci-suspend-param = <0x01010004>; 247 entry-latency-us = <300>; 248 exit-latency-us = <800>; 249 min-residency-us = <3300>; 250 }; 251 }; 252 253 l2: l2-cache { 254 compatible = "cache"; 255 cache-level = <2>; 256 cache-size = <0x80000>; 257 cache-line-size = <64>; 258 cache-sets = <512>; 259 cache-unified; 260 }; 261 }; 262 263 clk26m: oscillator { 264 compatible = "fixed-clock"; 265 #clock-cells = <0>; 266 clock-frequency = <26000000>; 267 clock-output-names = "clk26m"; 268 }; 269 270 gpu_opp_table: opp-table-gpu { 271 compatible = "operating-points-v2"; 272 opp-shared; 273 274 opp-450000000 { 275 opp-hz = /bits/ 64 <450000000>; 276 opp-microvolt = <650000>; 277 }; 278 279 opp-560000000 { 280 opp-hz = /bits/ 64 <560000000>; 281 opp-microvolt = <700000>; 282 }; 283 284 opp-800000000 { 285 opp-hz = /bits/ 64 <800000000>; 286 opp-microvolt = <800000>; 287 }; 288 }; 289 290 psci { 291 compatible = "arm,psci-1.0"; 292 method = "smc"; 293 }; 294 295 soc { 296 #address-cells = <2>; 297 #size-cells = <2>; 298 compatible = "simple-bus"; 299 ranges; 300 301 gic: interrupt-controller@c000000 { 302 compatible = "arm,gic-v3"; 303 #interrupt-cells = <3>; 304 interrupt-parent = <&gic>; 305 interrupt-controller; 306 reg = <0 0x0c000000 0 0x10000>, /* GICD */ 307 <0 0x0c080000 0 0x80000>, /* GICR */ 308 <0 0x0c400000 0 0x2000>, /* GICC */ 309 <0 0x0c410000 0 0x1000>, /* GICH */ 310 <0 0x0c420000 0 0x2000>; /* GICV */ 311 312 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 313 }; 314 315 mfgcfg: syscon@13000000 { 316 compatible = "mediatek,mt8365-mfgcfg", "syscon"; 317 reg = <0 0x13000000 0 0x1000>; 318 #clock-cells = <1>; 319 }; 320 321 gpu: gpu@13040000 { 322 compatible = "mediatek,mt8365-mali", "arm,mali-bifrost"; 323 reg = <0 0x13040000 0 0x4000>; 324 325 clocks = <&mfgcfg CLK_MFG_BG3D>; 326 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_LOW>, 327 <GIC_SPI 202 IRQ_TYPE_LEVEL_LOW>, 328 <GIC_SPI 201 IRQ_TYPE_LEVEL_LOW>, 329 <GIC_SPI 204 IRQ_TYPE_LEVEL_LOW>; 330 interrupt-names = "job", "mmu", "gpu", "event"; 331 operating-points-v2 = <&gpu_opp_table>; 332 power-domains = <&spm MT8365_POWER_DOMAIN_MFG>; 333 status = "disabled"; 334 }; 335 336 topckgen: syscon@10000000 { 337 compatible = "mediatek,mt8365-topckgen", "syscon"; 338 reg = <0 0x10000000 0 0x1000>; 339 #clock-cells = <1>; 340 }; 341 342 infracfg: syscon@10001000 { 343 compatible = "mediatek,mt8365-infracfg", "syscon"; 344 reg = <0 0x10001000 0 0x1000>; 345 #clock-cells = <1>; 346 }; 347 348 pericfg: syscon@10003000 { 349 compatible = "mediatek,mt8365-pericfg", "syscon"; 350 reg = <0 0x10003000 0 0x1000>; 351 #clock-cells = <1>; 352 }; 353 354 syscfg_pctl: syscfg-pctl@10005000 { 355 compatible = "mediatek,mt8365-syscfg", "syscon"; 356 reg = <0 0x10005000 0 0x1000>; 357 }; 358 359 scpsys: syscon@10006000 { 360 compatible = "mediatek,mt8365-scpsys", "syscon", "simple-mfd"; 361 reg = <0 0x10006000 0 0x1000>; 362 363 /* System Power Manager */ 364 spm: power-controller { 365 compatible = "mediatek,mt8365-power-controller"; 366 #address-cells = <1>; 367 #size-cells = <0>; 368 #power-domain-cells = <1>; 369 370 /* power domains of the SoC */ 371 power-domain@MT8365_POWER_DOMAIN_MM { 372 reg = <MT8365_POWER_DOMAIN_MM>; 373 clocks = <&topckgen CLK_TOP_MM_SEL>, 374 <&mmsys CLK_MM_MM_SMI_COMMON>, 375 <&mmsys CLK_MM_MM_SMI_COMM0>, 376 <&mmsys CLK_MM_MM_SMI_COMM1>, 377 <&mmsys CLK_MM_MM_SMI_LARB0>; 378 clock-names = "mm", "mm-0", "mm-1", 379 "mm-2", "mm-3"; 380 #power-domain-cells = <0>; 381 mediatek,infracfg = <&infracfg>; 382 mediatek,infracfg-nao = <&infracfg_nao>; 383 #address-cells = <1>; 384 #size-cells = <0>; 385 386 power-domain@MT8365_POWER_DOMAIN_CAM { 387 reg = <MT8365_POWER_DOMAIN_CAM>; 388 clocks = <&camsys CLK_CAM_LARB2>, 389 <&camsys CLK_CAM_SENIF>, 390 <&camsys CLK_CAMSV0>, 391 <&camsys CLK_CAMSV1>, 392 <&camsys CLK_CAM_FDVT>, 393 <&camsys CLK_CAM_WPE>; 394 clock-names = "cam-0", "cam-1", 395 "cam-2", "cam-3", 396 "cam-4", "cam-5"; 397 #power-domain-cells = <0>; 398 mediatek,infracfg = <&infracfg>; 399 mediatek,smi = <&smi_common>; 400 }; 401 402 power-domain@MT8365_POWER_DOMAIN_VDEC { 403 reg = <MT8365_POWER_DOMAIN_VDEC>; 404 #power-domain-cells = <0>; 405 mediatek,smi = <&smi_common>; 406 }; 407 408 power-domain@MT8365_POWER_DOMAIN_VENC { 409 reg = <MT8365_POWER_DOMAIN_VENC>; 410 #power-domain-cells = <0>; 411 mediatek,smi = <&smi_common>; 412 }; 413 414 power-domain@MT8365_POWER_DOMAIN_APU { 415 reg = <MT8365_POWER_DOMAIN_APU>; 416 clocks = <&infracfg CLK_IFR_APU_AXI>, 417 <&apu CLK_APU_IPU_CK>, 418 <&apu CLK_APU_AXI>, 419 <&apu CLK_APU_JTAG>, 420 <&apu CLK_APU_IF_CK>, 421 <&apu CLK_APU_EDMA>, 422 <&apu CLK_APU_AHB>; 423 clock-names = "apu", "apu-0", 424 "apu-1", "apu-2", 425 "apu-3", "apu-4", 426 "apu-5"; 427 #power-domain-cells = <0>; 428 mediatek,infracfg = <&infracfg>; 429 mediatek,smi = <&smi_common>; 430 }; 431 }; 432 433 power-domain@MT8365_POWER_DOMAIN_CONN { 434 reg = <MT8365_POWER_DOMAIN_CONN>; 435 clocks = <&topckgen CLK_TOP_CONN_32K>, 436 <&topckgen CLK_TOP_CONN_26M>; 437 clock-names = "conn", "conn1"; 438 #power-domain-cells = <0>; 439 mediatek,infracfg = <&infracfg>; 440 }; 441 442 mfg: power-domain@MT8365_POWER_DOMAIN_MFG { 443 reg = <MT8365_POWER_DOMAIN_MFG>; 444 clocks = <&topckgen CLK_TOP_MFG_SEL>; 445 clock-names = "mfg"; 446 #power-domain-cells = <0>; 447 mediatek,infracfg = <&infracfg>; 448 }; 449 450 power-domain@MT8365_POWER_DOMAIN_AUDIO { 451 reg = <MT8365_POWER_DOMAIN_AUDIO>; 452 clocks = <&topckgen CLK_TOP_AUD_INTBUS_SEL>, 453 <&infracfg CLK_IFR_AUDIO>, 454 <&infracfg CLK_IFR_AUD_26M_BK>; 455 clock-names = "audio", "audio1", "audio2"; 456 #power-domain-cells = <0>; 457 mediatek,infracfg = <&infracfg>; 458 }; 459 460 power-domain@MT8365_POWER_DOMAIN_DSP { 461 reg = <MT8365_POWER_DOMAIN_DSP>; 462 clocks = <&topckgen CLK_TOP_DSP_SEL>, 463 <&topckgen CLK_TOP_DSP_26M>; 464 clock-names = "dsp", "dsp1"; 465 #power-domain-cells = <0>; 466 mediatek,infracfg = <&infracfg>; 467 }; 468 }; 469 }; 470 471 watchdog: watchdog@10007000 { 472 compatible = "mediatek,mt8365-wdt", "mediatek,mt6589-wdt"; 473 reg = <0 0x10007000 0 0x100>; 474 #reset-cells = <1>; 475 }; 476 477 pio: pinctrl@1000b000 { 478 compatible = "mediatek,mt8365-pinctrl"; 479 reg = <0 0x1000b000 0 0x1000>; 480 mediatek,pctl-regmap = <&syscfg_pctl>; 481 gpio-controller; 482 #gpio-cells = <2>; 483 interrupt-controller; 484 #interrupt-cells = <2>; 485 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 486 }; 487 488 apmixedsys: syscon@1000c000 { 489 compatible = "mediatek,mt8365-apmixedsys", "syscon"; 490 reg = <0 0x1000c000 0 0x1000>; 491 #clock-cells = <1>; 492 }; 493 494 pwrap: pwrap@1000d000 { 495 compatible = "mediatek,mt8365-pwrap"; 496 reg = <0 0x1000d000 0 0x1000>; 497 reg-names = "pwrap"; 498 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 499 clocks = <&infracfg CLK_IFR_PWRAP_SPI>, 500 <&infracfg CLK_IFR_PMIC_AP>, 501 <&infracfg CLK_IFR_PWRAP_SYS>, 502 <&infracfg CLK_IFR_PWRAP_TMR>; 503 clock-names = "spi", "wrap", "sys", "tmr"; 504 }; 505 506 keypad: keypad@10010000 { 507 compatible = "mediatek,mt8365-keypad", 508 "mediatek,mt6779-keypad"; 509 reg = <0 0x10010000 0 0x1000>; 510 wakeup-source; 511 interrupts = <GIC_SPI 124 IRQ_TYPE_EDGE_FALLING>; 512 clocks = <&clk26m>; 513 clock-names = "kpd"; 514 status = "disabled"; 515 }; 516 517 mcucfg: syscon@10200000 { 518 compatible = "mediatek,mt8365-mcucfg", "syscon"; 519 reg = <0 0x10200000 0 0x2000>; 520 #clock-cells = <1>; 521 }; 522 523 sysirq: interrupt-controller@10200a80 { 524 compatible = "mediatek,mt8365-sysirq", "mediatek,mt6577-sysirq"; 525 interrupt-controller; 526 #interrupt-cells = <3>; 527 interrupt-parent = <&gic>; 528 reg = <0 0x10200a80 0 0x20>; 529 }; 530 531 iommu: iommu@10205000 { 532 compatible = "mediatek,mt8365-m4u"; 533 reg = <0 0x10205000 0 0x1000>; 534 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_LOW>; 535 mediatek,larbs = <&larb0>, <&larb1>, <&larb2>, <&larb3>; 536 #iommu-cells = <1>; 537 }; 538 539 infracfg_nao: syscon@1020e000 { 540 compatible = "mediatek,mt8365-infracfg-nao", "syscon"; 541 reg = <0 0x1020e000 0 0x1000>; 542 }; 543 544 rng: rng@1020f000 { 545 compatible = "mediatek,mt8365-rng", "mediatek,mt7623-rng"; 546 reg = <0 0x1020f000 0 0x100>; 547 clocks = <&infracfg CLK_IFR_TRNG>; 548 clock-names = "rng"; 549 }; 550 551 apdma: dma-controller@11000280 { 552 compatible = "mediatek,mt8365-uart-dma", "mediatek,mt6577-uart-dma"; 553 reg = <0 0x11000280 0 0x80>, 554 <0 0x11000300 0 0x80>, 555 <0 0x11000380 0 0x80>, 556 <0 0x11000400 0 0x80>, 557 <0 0x11000580 0 0x80>, 558 <0 0x11000600 0 0x80>; 559 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_LOW>, 560 <GIC_SPI 46 IRQ_TYPE_LEVEL_LOW>, 561 <GIC_SPI 47 IRQ_TYPE_LEVEL_LOW>, 562 <GIC_SPI 48 IRQ_TYPE_LEVEL_LOW>, 563 <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>, 564 <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>; 565 dma-requests = <6>; 566 clocks = <&infracfg CLK_IFR_AP_DMA>; 567 clock-names = "apdma"; 568 #dma-cells = <1>; 569 }; 570 571 uart0: serial@11002000 { 572 compatible = "mediatek,mt8365-uart", "mediatek,mt6577-uart"; 573 reg = <0 0x11002000 0 0x1000>; 574 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_LOW>; 575 clocks = <&clk26m>, <&infracfg CLK_IFR_UART0>; 576 clock-names = "baud", "bus"; 577 dmas = <&apdma 0>, <&apdma 1>; 578 dma-names = "tx", "rx"; 579 status = "disabled"; 580 }; 581 582 uart1: serial@11003000 { 583 compatible = "mediatek,mt8365-uart", "mediatek,mt6577-uart"; 584 reg = <0 0x11003000 0 0x1000>; 585 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_LOW>; 586 clocks = <&clk26m>, <&infracfg CLK_IFR_UART1>; 587 clock-names = "baud", "bus"; 588 dmas = <&apdma 2>, <&apdma 3>; 589 dma-names = "tx", "rx"; 590 status = "disabled"; 591 }; 592 593 uart2: serial@11004000 { 594 compatible = "mediatek,mt8365-uart", "mediatek,mt6577-uart"; 595 reg = <0 0x11004000 0 0x1000>; 596 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_LOW>; 597 clocks = <&clk26m>, <&infracfg CLK_IFR_UART2>; 598 clock-names = "baud", "bus"; 599 dmas = <&apdma 4>, <&apdma 5>; 600 dma-names = "tx", "rx"; 601 status = "disabled"; 602 }; 603 604 pwm: pwm@11006000 { 605 compatible = "mediatek,mt8365-pwm"; 606 reg = <0 0x11006000 0 0x1000>; 607 #pwm-cells = <2>; 608 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_LOW>; 609 clocks = <&infracfg CLK_IFR_PWM_HCLK>, 610 <&infracfg CLK_IFR_PWM>, 611 <&infracfg CLK_IFR_PWM1>, 612 <&infracfg CLK_IFR_PWM2>, 613 <&infracfg CLK_IFR_PWM3>; 614 clock-names = "top", "main", "pwm1", "pwm2", "pwm3"; 615 }; 616 617 i2c0: i2c@11007000 { 618 compatible = "mediatek,mt8365-i2c", "mediatek,mt8168-i2c"; 619 reg = <0 0x11007000 0 0xa0>, <0 0x11000080 0 0x80>; 620 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_LOW>; 621 clock-div = <1>; 622 clocks = <&infracfg CLK_IFR_I2C0_AXI>, <&infracfg CLK_IFR_AP_DMA>; 623 clock-names = "main", "dma"; 624 #address-cells = <1>; 625 #size-cells = <0>; 626 status = "disabled"; 627 }; 628 629 i2c1: i2c@11008000 { 630 compatible = "mediatek,mt8365-i2c", "mediatek,mt8168-i2c"; 631 reg = <0 0x11008000 0 0xa0>, <0 0x11000100 0 0x80>; 632 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_LOW>; 633 clock-div = <1>; 634 clocks = <&infracfg CLK_IFR_I2C1_AXI>, <&infracfg CLK_IFR_AP_DMA>; 635 clock-names = "main", "dma"; 636 #address-cells = <1>; 637 #size-cells = <0>; 638 status = "disabled"; 639 }; 640 641 i2c2: i2c@11009000 { 642 compatible = "mediatek,mt8365-i2c", "mediatek,mt8168-i2c"; 643 reg = <0 0x11009000 0 0xa0>, <0 0x11000180 0 0x80>; 644 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_LOW>; 645 clock-div = <1>; 646 clocks = <&infracfg CLK_IFR_I2C2_AXI>, <&infracfg CLK_IFR_AP_DMA>; 647 clock-names = "main", "dma"; 648 #address-cells = <1>; 649 #size-cells = <0>; 650 status = "disabled"; 651 }; 652 653 spi: spi@1100a000 { 654 compatible = "mediatek,mt8365-spi", "mediatek,mt7622-spi"; 655 reg = <0 0x1100a000 0 0x100>; 656 #address-cells = <1>; 657 #size-cells = <0>; 658 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_LOW>; 659 clocks = <&topckgen CLK_TOP_UNIVPLL2_D4>, 660 <&topckgen CLK_TOP_SPI_SEL>, 661 <&infracfg CLK_IFR_SPI0>; 662 clock-names = "parent-clk", "sel-clk", "spi-clk"; 663 status = "disabled"; 664 }; 665 666 disp_pwm: pwm@1100e000 { 667 compatible = "mediatek,mt8365-disp-pwm", "mediatek,mt8183-disp-pwm"; 668 reg = <0 0x1100e000 0 0x1000>; 669 clock-names = "main", "mm"; 670 clocks = <&topckgen CLK_TOP_DISP_PWM_SEL>, <&infracfg CLK_IFR_DISP_PWM>; 671 power-domains = <&spm MT8365_POWER_DOMAIN_MM>; 672 #pwm-cells = <2>; 673 }; 674 675 i2c3: i2c@1100f000 { 676 compatible = "mediatek,mt8365-i2c", "mediatek,mt8168-i2c"; 677 reg = <0 0x1100f000 0 0xa0>, <0 0x11000200 0 0x80>; 678 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_LOW>; 679 clock-div = <1>; 680 clocks = <&infracfg CLK_IFR_I2C3_AXI>, <&infracfg CLK_IFR_AP_DMA>; 681 clock-names = "main", "dma"; 682 #address-cells = <1>; 683 #size-cells = <0>; 684 status = "disabled"; 685 }; 686 687 ssusb: usb@11201000 { 688 compatible = "mediatek,mt8365-mtu3", "mediatek,mtu3"; 689 reg = <0 0x11201000 0 0x2e00>, <0 0x11203e00 0 0x0100>; 690 reg-names = "mac", "ippc"; 691 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_LOW>; 692 phys = <&u2port0 PHY_TYPE_USB2>, 693 <&u2port1 PHY_TYPE_USB2>; 694 clocks = <&topckgen CLK_TOP_SSUSB_TOP_CK_EN>, 695 <&infracfg CLK_IFR_SSUSB_REF>, 696 <&infracfg CLK_IFR_SSUSB_SYS>, 697 <&infracfg CLK_IFR_ICUSB>; 698 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck"; 699 #address-cells = <2>; 700 #size-cells = <2>; 701 ranges; 702 status = "disabled"; 703 704 usb_host: usb@11200000 { 705 compatible = "mediatek,mt8365-xhci", "mediatek,mtk-xhci"; 706 reg = <0 0x11200000 0 0x1000>; 707 reg-names = "mac"; 708 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_LOW>; 709 clocks = <&topckgen CLK_TOP_SSUSB_TOP_CK_EN>, 710 <&infracfg CLK_IFR_SSUSB_REF>, 711 <&infracfg CLK_IFR_SSUSB_SYS>, 712 <&infracfg CLK_IFR_ICUSB>, 713 <&infracfg CLK_IFR_SSUSB_XHCI>; 714 clock-names = "sys_ck", "ref_ck", "mcu_ck", 715 "dma_ck", "xhci_ck"; 716 status = "disabled"; 717 }; 718 }; 719 720 mmc0: mmc@11230000 { 721 compatible = "mediatek,mt8365-mmc", "mediatek,mt8183-mmc"; 722 reg = <0 0x11230000 0 0x1000>, 723 <0 0x11cd0000 0 0x1000>; 724 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_LOW>; 725 clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>, 726 <&infracfg CLK_IFR_MSDC0_HCLK>, 727 <&infracfg CLK_IFR_MSDC0_SRC>; 728 clock-names = "source", "hclk", "source_cg"; 729 status = "disabled"; 730 }; 731 732 mmc1: mmc@11240000 { 733 compatible = "mediatek,mt8365-mmc", "mediatek,mt8183-mmc"; 734 reg = <0 0x11240000 0 0x1000>, 735 <0 0x11c90000 0 0x1000>; 736 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_LOW>; 737 clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>, 738 <&infracfg CLK_IFR_MSDC1_HCLK>, 739 <&infracfg CLK_IFR_MSDC1_SRC>; 740 clock-names = "source", "hclk", "source_cg"; 741 status = "disabled"; 742 }; 743 744 mmc2: mmc@11250000 { 745 compatible = "mediatek,mt8365-mmc", "mediatek,mt8183-mmc"; 746 reg = <0 0x11250000 0 0x1000>, 747 <0 0x11c60000 0 0x1000>; 748 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_LOW>; 749 clocks = <&topckgen CLK_TOP_MSDC50_2_SEL>, 750 <&infracfg CLK_IFR_MSDC2_HCLK>, 751 <&infracfg CLK_IFR_MSDC2_SRC>, 752 <&infracfg CLK_IFR_MSDC2_BK>, 753 <&infracfg CLK_IFR_AP_MSDC0>; 754 clock-names = "source", "hclk", "source_cg", 755 "bus_clk", "sys_cg"; 756 status = "disabled"; 757 }; 758 759 ethernet: ethernet@112a0000 { 760 compatible = "mediatek,mt8365-eth"; 761 reg = <0 0x112a0000 0 0x1000>; 762 mediatek,pericfg = <&infracfg>; 763 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 764 clocks = <&topckgen CLK_TOP_ETH_SEL>, 765 <&infracfg CLK_IFR_NIC_AXI>, 766 <&infracfg CLK_IFR_NIC_SLV_AXI>; 767 clock-names = "core", "reg", "trans"; 768 status = "disabled"; 769 }; 770 771 mipi_tx0: dsi-phy@11c00000 { 772 compatible = "mediatek,mt8365-mipi-tx", "mediatek,mt8183-mipi-tx"; 773 reg = <0 0x11c00000 0 0x800>; 774 clock-output-names = "mipi_tx0_pll"; 775 clocks = <&clk26m>; 776 #clock-cells = <0>; 777 #phy-cells = <0>; 778 }; 779 780 u3phy: t-phy@11cc0000 { 781 compatible = "mediatek,mt8365-tphy", "mediatek,generic-tphy-v2"; 782 #address-cells = <1>; 783 #size-cells = <1>; 784 ranges = <0 0 0x11cc0000 0x9000>; 785 786 u2port0: usb-phy@0 { 787 reg = <0x0 0x400>; 788 clocks = <&topckgen CLK_TOP_SSUSB_PHY_CK_EN>, 789 <&topckgen CLK_TOP_USB20_48M_EN>; 790 clock-names = "ref", "da_ref"; 791 #phy-cells = <1>; 792 }; 793 794 u2port1: usb-phy@1000 { 795 reg = <0x1000 0x400>; 796 clocks = <&topckgen CLK_TOP_SSUSB_PHY_CK_EN>, 797 <&topckgen CLK_TOP_USB20_48M_EN>; 798 clock-names = "ref", "da_ref"; 799 #phy-cells = <1>; 800 }; 801 }; 802 803 mmsys: syscon@14000000 { 804 compatible = "mediatek,mt8365-mmsys", "syscon"; 805 reg = <0 0x14000000 0 0x1000>; 806 #clock-cells = <1>; 807 port { 808 #address-cells = <1>; 809 #size-cells = <0>; 810 811 mmsys_main: endpoint@0 { 812 reg = <0>; 813 remote-endpoint = <&ovl0_in>; 814 }; 815 mmsys_ext: endpoint@1 { 816 reg = <1>; 817 remote-endpoint = <&rdma1_in>; 818 }; 819 }; 820 }; 821 822 mutex: mutex@14001000 { 823 compatible = "mediatek,mt8365-disp-mutex"; 824 reg = <0 0x14001000 0 0x1000>; 825 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_LOW>; 826 power-domains = <&spm MT8365_POWER_DOMAIN_MM>; 827 }; 828 829 smi_common: smi@14002000 { 830 compatible = "mediatek,mt8365-smi-common"; 831 reg = <0 0x14002000 0 0x1000>; 832 clocks = <&mmsys CLK_MM_MM_SMI_COMMON>, 833 <&mmsys CLK_MM_MM_SMI_COMMON>, 834 <&mmsys CLK_MM_MM_SMI_COMM0>, 835 <&mmsys CLK_MM_MM_SMI_COMM1>; 836 clock-names = "apb", "smi", "gals0", "gals1"; 837 power-domains = <&spm MT8365_POWER_DOMAIN_MM>; 838 }; 839 840 larb0: larb@14003000 { 841 compatible = "mediatek,mt8365-smi-larb", 842 "mediatek,mt8186-smi-larb"; 843 reg = <0 0x14003000 0 0x1000>; 844 mediatek,smi = <&smi_common>; 845 clocks = <&mmsys CLK_MM_MM_SMI_LARB0>, 846 <&mmsys CLK_MM_MM_SMI_LARB0>; 847 clock-names = "apb", "smi"; 848 power-domains = <&spm MT8365_POWER_DOMAIN_MM>; 849 mediatek,larb-id = <0>; 850 }; 851 852 ovl0: ovl@1400b000 { 853 compatible = "mediatek,mt8365-disp-ovl", "mediatek,mt8192-disp-ovl"; 854 reg = <0 0x1400b000 0 0x1000>; 855 clocks = <&mmsys CLK_MM_MM_DISP_OVL0>; 856 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_LOW>; 857 iommus = <&iommu M4U_PORT_DISP_OVL0>; 858 power-domains = <&spm MT8365_POWER_DOMAIN_MM>; 859 ports { 860 #address-cells = <1>; 861 #size-cells = <0>; 862 863 port@0 { 864 #address-cells = <1>; 865 #size-cells = <0>; 866 reg = <0>; 867 ovl0_in: endpoint@0 { 868 reg = <0>; 869 remote-endpoint = <&mmsys_main>; 870 }; 871 }; 872 873 port@1 { 874 #address-cells = <1>; 875 #size-cells = <0>; 876 reg = <1>; 877 ovl0_out: endpoint@0 { 878 reg = <0>; 879 remote-endpoint = <&rdma0_in>; 880 }; 881 }; 882 }; 883 }; 884 885 rdma0: rdma@1400d000 { 886 compatible = "mediatek,mt8365-disp-rdma", "mediatek,mt8183-disp-rdma"; 887 reg = <0 0x1400d000 0 0x1000>; 888 clocks = <&mmsys CLK_MM_MM_DISP_RDMA0>; 889 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_LOW>; 890 iommus = <&iommu M4U_PORT_DISP_RDMA0>; 891 mediatek,rdma-fifo-size = <5120>; 892 power-domains = <&spm MT8365_POWER_DOMAIN_MM>; 893 ports { 894 #address-cells = <1>; 895 #size-cells = <0>; 896 897 port@0 { 898 #address-cells = <1>; 899 #size-cells = <0>; 900 reg = <0>; 901 rdma0_in: endpoint@0 { 902 reg = <0>; 903 remote-endpoint = <&ovl0_out>; 904 }; 905 }; 906 907 port@1 { 908 #address-cells = <1>; 909 #size-cells = <0>; 910 reg = <1>; 911 rdma0_out: endpoint@0 { 912 reg = <0>; 913 remote-endpoint = <&color0_in>; 914 }; 915 }; 916 }; 917 }; 918 919 color0: color@1400f000 { 920 compatible = "mediatek,mt8365-disp-color", "mediatek,mt8173-disp-color"; 921 reg = <0 0x1400f000 0 0x1000>; 922 clocks = <&mmsys CLK_MM_MM_DISP_COLOR0>; 923 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_LOW>; 924 power-domains = <&spm MT8365_POWER_DOMAIN_MM>; 925 ports { 926 #address-cells = <1>; 927 #size-cells = <0>; 928 929 port@0 { 930 #address-cells = <1>; 931 #size-cells = <0>; 932 reg = <0>; 933 color0_in: endpoint@0 { 934 reg = <0>; 935 remote-endpoint = <&rdma0_out>; 936 }; 937 }; 938 939 port@1 { 940 #address-cells = <1>; 941 #size-cells = <0>; 942 reg = <1>; 943 color0_out: endpoint@0 { 944 reg = <0>; 945 remote-endpoint = <&ccorr0_in>; 946 }; 947 }; 948 }; 949 }; 950 951 ccorr0: ccorr@14010000 { 952 compatible = "mediatek,mt8365-disp-ccorr", "mediatek,mt8183-disp-ccorr"; 953 reg = <0 0x14010000 0 0x1000>; 954 clocks = <&mmsys CLK_MM_MM_DISP_CCORR0>; 955 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_LOW>; 956 power-domains = <&spm MT8365_POWER_DOMAIN_MM>; 957 ports { 958 #address-cells = <1>; 959 #size-cells = <0>; 960 961 port@0 { 962 #address-cells = <1>; 963 #size-cells = <0>; 964 reg = <0>; 965 ccorr0_in: endpoint@0 { 966 reg = <0>; 967 remote-endpoint = <&color0_out>; 968 }; 969 }; 970 971 port@1 { 972 #address-cells = <1>; 973 #size-cells = <0>; 974 reg = <1>; 975 ccorr0_out: endpoint@0 { 976 reg = <0>; 977 remote-endpoint = <&aal0_in>; 978 }; 979 }; 980 }; 981 }; 982 983 aal0: aal@14011000 { 984 compatible = "mediatek,mt8365-disp-aal", "mediatek,mt8183-disp-aal"; 985 reg = <0 0x14011000 0 0x1000>; 986 clocks = <&mmsys CLK_MM_MM_DISP_AAL0>; 987 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_LOW>; 988 power-domains = <&spm MT8365_POWER_DOMAIN_MM>; 989 ports { 990 #address-cells = <1>; 991 #size-cells = <0>; 992 993 port@0 { 994 #address-cells = <1>; 995 #size-cells = <0>; 996 reg = <0>; 997 aal0_in: endpoint@0 { 998 reg = <0>; 999 remote-endpoint = <&ccorr0_out>; 1000 }; 1001 }; 1002 1003 port@1 { 1004 #address-cells = <1>; 1005 #size-cells = <0>; 1006 reg = <1>; 1007 aal0_out: endpoint@0 { 1008 reg = <0>; 1009 remote-endpoint = <&gamma0_in>; 1010 }; 1011 }; 1012 }; 1013 }; 1014 1015 gamma0: gamma@14012000 { 1016 compatible = "mediatek,mt8365-disp-gamma", "mediatek,mt8183-disp-gamma"; 1017 reg = <0 0x14012000 0 0x1000>; 1018 clocks = <&mmsys CLK_MM_MM_DISP_GAMMA0>; 1019 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_LOW>; 1020 power-domains = <&spm MT8365_POWER_DOMAIN_MM>; 1021 ports { 1022 #address-cells = <1>; 1023 #size-cells = <0>; 1024 1025 port@0 { 1026 #address-cells = <1>; 1027 #size-cells = <0>; 1028 reg = <0>; 1029 gamma0_in: endpoint@0 { 1030 reg = <0>; 1031 remote-endpoint = <&aal0_out>; 1032 }; 1033 }; 1034 1035 port@1 { 1036 #address-cells = <1>; 1037 #size-cells = <0>; 1038 reg = <1>; 1039 gamma0_out: endpoint@0 { 1040 reg = <0>; 1041 remote-endpoint = <&dither0_in>; 1042 }; 1043 }; 1044 }; 1045 }; 1046 1047 dither0: dither@14013000 { 1048 compatible = "mediatek,mt8365-disp-dither", "mediatek,mt8183-disp-dither"; 1049 reg = <0 0x14013000 0 0x1000>; 1050 clocks = <&mmsys CLK_MM_MM_DISP_DITHER0>; 1051 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_LOW>; 1052 power-domains = <&spm MT8365_POWER_DOMAIN_MM>; 1053 ports { 1054 #address-cells = <1>; 1055 #size-cells = <0>; 1056 1057 port@0 { 1058 #address-cells = <1>; 1059 #size-cells = <0>; 1060 reg = <0>; 1061 dither0_in: endpoint@0 { 1062 reg = <0>; 1063 remote-endpoint = <&gamma0_out>; 1064 }; 1065 }; 1066 1067 port@1 { 1068 #address-cells = <1>; 1069 #size-cells = <0>; 1070 reg = <1>; 1071 dither0_out: endpoint@0 { 1072 reg = <0>; 1073 }; 1074 }; 1075 }; 1076 }; 1077 1078 dsi0: dsi@14014000 { 1079 compatible = "mediatek,mt8365-dsi", "mediatek,mt8183-dsi"; 1080 reg = <0 0x14014000 0 0x1000>; 1081 clock-names = "engine", "digital", "hs"; 1082 clocks = <&mmsys CLK_MM_MM_DSI0>, 1083 <&mmsys CLK_MM_DSI0_DIG_DSI>, 1084 <&mipi_tx0>; 1085 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_LOW>; 1086 phy-names = "dphy"; 1087 phys = <&mipi_tx0>; 1088 power-domains = <&spm MT8365_POWER_DOMAIN_MM>; 1089 }; 1090 1091 rdma1: rdma@14016000 { 1092 compatible = "mediatek,mt8365-disp-rdma", "mediatek,mt8183-disp-rdma"; 1093 reg = <0 0x14016000 0 0x1000>; 1094 clocks = <&mmsys CLK_MM_MM_DISP_RDMA1>; 1095 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>; 1096 iommus = <&iommu M4U_PORT_DISP_RDMA1>; 1097 mediatek,rdma-fifo-size = <2048>; 1098 power-domains = <&spm MT8365_POWER_DOMAIN_MM>; 1099 ports { 1100 #address-cells = <1>; 1101 #size-cells = <0>; 1102 1103 port@0 { 1104 #address-cells = <1>; 1105 #size-cells = <0>; 1106 reg = <0>; 1107 rdma1_in: endpoint@1 { 1108 reg = <1>; 1109 remote-endpoint = <&mmsys_ext>; 1110 }; 1111 }; 1112 1113 port@1 { 1114 #address-cells = <1>; 1115 #size-cells = <0>; 1116 reg = <1>; 1117 rdma1_out: endpoint@1 { 1118 reg = <1>; 1119 }; 1120 }; 1121 }; 1122 }; 1123 1124 dpi0: dpi@14018000 { 1125 compatible = "mediatek,mt8365-dpi", "mediatek,mt8192-dpi"; 1126 reg = <0 0x14018000 0 0x1000>; 1127 clocks = <&mmsys CLK_MM_DPI0_DPI0>, 1128 <&mmsys CLK_MM_MM_DPI0>, 1129 <&apmixedsys CLK_APMIXED_LVDSPLL>; 1130 clock-names = "pixel", "engine", "pll"; 1131 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_LOW>; 1132 power-domains = <&spm MT8365_POWER_DOMAIN_MM>; 1133 status = "disabled"; 1134 }; 1135 1136 camsys: syscon@15000000 { 1137 compatible = "mediatek,mt8365-imgsys", "syscon"; 1138 reg = <0 0x15000000 0 0x1000>; 1139 #clock-cells = <1>; 1140 }; 1141 1142 larb2: larb@15001000 { 1143 compatible = "mediatek,mt8365-smi-larb", 1144 "mediatek,mt8186-smi-larb"; 1145 reg = <0 0x15001000 0 0x1000>; 1146 mediatek,smi = <&smi_common>; 1147 clocks = <&mmsys CLK_MM_MM_SMI_IMG>, 1148 <&camsys CLK_CAM_LARB2>; 1149 clock-names = "apb", "smi"; 1150 power-domains = <&spm MT8365_POWER_DOMAIN_CAM>; 1151 mediatek,larb-id = <2>; 1152 }; 1153 1154 vdecsys: syscon@16000000 { 1155 compatible = "mediatek,mt8365-vdecsys", "syscon"; 1156 reg = <0 0x16000000 0 0x1000>; 1157 #clock-cells = <1>; 1158 }; 1159 1160 larb3: larb@16010000 { 1161 compatible = "mediatek,mt8365-smi-larb", 1162 "mediatek,mt8186-smi-larb"; 1163 reg = <0 0x16010000 0 0x1000>; 1164 mediatek,smi = <&smi_common>; 1165 clocks = <&vdecsys CLK_VDEC_LARB1>, 1166 <&vdecsys CLK_VDEC_LARB1>; 1167 clock-names = "apb", "smi"; 1168 power-domains = <&spm MT8365_POWER_DOMAIN_VDEC>; 1169 mediatek,larb-id = <3>; 1170 }; 1171 1172 vencsys: syscon@17000000 { 1173 compatible = "mediatek,mt8365-vencsys", "syscon"; 1174 reg = <0 0x17000000 0 0x1000>; 1175 #clock-cells = <1>; 1176 }; 1177 1178 larb1: larb@17010000 { 1179 compatible = "mediatek,mt8365-smi-larb", 1180 "mediatek,mt8186-smi-larb"; 1181 reg = <0 0x17010000 0 0x1000>; 1182 mediatek,smi = <&smi_common>; 1183 clocks = <&vencsys CLK_VENC>, <&vencsys CLK_VENC>; 1184 clock-names = "apb", "smi"; 1185 power-domains = <&spm MT8365_POWER_DOMAIN_VENC>; 1186 mediatek,larb-id = <1>; 1187 }; 1188 1189 apu: syscon@19020000 { 1190 compatible = "mediatek,mt8365-apu", "syscon"; 1191 reg = <0 0x19020000 0 0x1000>; 1192 #clock-cells = <1>; 1193 }; 1194 1195 afe: audio-controller@11220000 { 1196 compatible = "mediatek,mt8365-afe-pcm"; 1197 reg = <0 0x11220000 0 0x1000>; 1198 #sound-dai-cells = <0>; 1199 clocks = <&clk26m>, 1200 <&topckgen CLK_TOP_AUDIO_SEL>, 1201 <&topckgen CLK_TOP_AUD_I2S0_M>, 1202 <&topckgen CLK_TOP_AUD_I2S1_M>, 1203 <&topckgen CLK_TOP_AUD_I2S2_M>, 1204 <&topckgen CLK_TOP_AUD_I2S3_M>, 1205 <&topckgen CLK_TOP_AUD_ENGEN1_SEL>, 1206 <&topckgen CLK_TOP_AUD_ENGEN2_SEL>, 1207 <&topckgen CLK_TOP_AUD_1_SEL>, 1208 <&topckgen CLK_TOP_AUD_2_SEL>, 1209 <&topckgen CLK_TOP_APLL_I2S0_SEL>, 1210 <&topckgen CLK_TOP_APLL_I2S1_SEL>, 1211 <&topckgen CLK_TOP_APLL_I2S2_SEL>, 1212 <&topckgen CLK_TOP_APLL_I2S3_SEL>; 1213 clock-names = "top_clk26m_clk", 1214 "top_audio_sel", 1215 "audio_i2s0_m", 1216 "audio_i2s1_m", 1217 "audio_i2s2_m", 1218 "audio_i2s3_m", 1219 "engen1", 1220 "engen2", 1221 "aud1", 1222 "aud2", 1223 "i2s0_m_sel", 1224 "i2s1_m_sel", 1225 "i2s2_m_sel", 1226 "i2s3_m_sel"; 1227 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_LOW>; 1228 power-domains = <&spm MT8365_POWER_DOMAIN_AUDIO>; 1229 status = "disabled"; 1230 }; 1231 }; 1232 1233 timer { 1234 compatible = "arm,armv8-timer"; 1235 interrupt-parent = <&gic>; 1236 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 1237 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 1238 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 1239 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 1240 }; 1241 1242 system_clk: dummy13m { 1243 compatible = "fixed-clock"; 1244 clock-frequency = <13000000>; 1245 #clock-cells = <0>; 1246 }; 1247 1248 systimer: timer@10017000 { 1249 compatible = "mediatek,mt8365-systimer", "mediatek,mt6765-timer"; 1250 reg = <0 0x10017000 0 0x100>; 1251 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 1252 clocks = <&system_clk>; 1253 clock-names = "clk13m"; 1254 }; 1255}; 1256