1 /*
2 * Copyright (c) 2007 Cisco Systems, Inc. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #include <rdma/ib_mad.h>
34 #include <rdma/ib_smi.h>
35 #include <rdma/ib_sa.h>
36 #include <rdma/ib_cache.h>
37
38 #include <linux/random.h>
39 #include <dev/mlx4/cmd.h>
40 #include <dev/mlx4/driver.h>
41 #include <linux/gfp.h>
42 #include <rdma/ib_pma.h>
43
44 #include "mlx4_ib.h"
45
46 enum {
47 MLX4_IB_VENDOR_CLASS1 = 0x9,
48 MLX4_IB_VENDOR_CLASS2 = 0xa
49 };
50
51 #define MLX4_TUN_SEND_WRID_SHIFT 34
52 #define MLX4_TUN_QPN_SHIFT 32
53 #define MLX4_TUN_WRID_RECV (((u64) 1) << MLX4_TUN_SEND_WRID_SHIFT)
54 #define MLX4_TUN_SET_WRID_QPN(a) (((u64) ((a) & 0x3)) << MLX4_TUN_QPN_SHIFT)
55
56 #define MLX4_TUN_IS_RECV(a) (((a) >> MLX4_TUN_SEND_WRID_SHIFT) & 0x1)
57 #define MLX4_TUN_WRID_QPN(a) (((a) >> MLX4_TUN_QPN_SHIFT) & 0x3)
58
59 /* Port mgmt change event handling */
60
61 #define GET_BLK_PTR_FROM_EQE(eqe) be32_to_cpu(eqe->event.port_mgmt_change.params.tbl_change_info.block_ptr)
62 #define GET_MASK_FROM_EQE(eqe) be32_to_cpu(eqe->event.port_mgmt_change.params.tbl_change_info.tbl_entries_mask)
63 #define NUM_IDX_IN_PKEY_TBL_BLK 32
64 #define GUID_TBL_ENTRY_SIZE 8 /* size in bytes */
65 #define GUID_TBL_BLK_NUM_ENTRIES 8
66 #define GUID_TBL_BLK_SIZE (GUID_TBL_ENTRY_SIZE * GUID_TBL_BLK_NUM_ENTRIES)
67
68 struct mlx4_mad_rcv_buf {
69 struct ib_grh grh;
70 u8 payload[256];
71 } __packed;
72
73 struct mlx4_mad_snd_buf {
74 u8 payload[256];
75 } __packed;
76
77 struct mlx4_tunnel_mad {
78 struct ib_grh grh;
79 struct mlx4_ib_tunnel_header hdr;
80 struct ib_mad mad;
81 } __packed;
82
83 struct mlx4_rcv_tunnel_mad {
84 struct mlx4_rcv_tunnel_hdr hdr;
85 struct ib_grh grh;
86 struct ib_mad mad;
87 } __packed;
88
89 static void handle_client_rereg_event(struct mlx4_ib_dev *dev, u8 port_num);
90 static void handle_lid_change_event(struct mlx4_ib_dev *dev, u8 port_num);
91 static void __propagate_pkey_ev(struct mlx4_ib_dev *dev, int port_num,
92 int block, u32 change_bitmap);
93
mlx4_ib_gen_node_guid(void)94 __be64 mlx4_ib_gen_node_guid(void)
95 {
96 #define NODE_GUID_HI ((u64) (((u64)IB_OPENIB_OUI) << 40))
97 return cpu_to_be64(NODE_GUID_HI | random());
98 }
99
mlx4_ib_get_new_demux_tid(struct mlx4_ib_demux_ctx * ctx)100 __be64 mlx4_ib_get_new_demux_tid(struct mlx4_ib_demux_ctx *ctx)
101 {
102 return cpu_to_be64(atomic_inc_return(&ctx->tid)) |
103 cpu_to_be64(0xff00000000000000LL);
104 }
105
mlx4_MAD_IFC(struct mlx4_ib_dev * dev,int mad_ifc_flags,int port,const struct ib_wc * in_wc,const struct ib_grh * in_grh,const void * in_mad,void * response_mad)106 int mlx4_MAD_IFC(struct mlx4_ib_dev *dev, int mad_ifc_flags,
107 int port, const struct ib_wc *in_wc,
108 const struct ib_grh *in_grh,
109 const void *in_mad, void *response_mad)
110 {
111 struct mlx4_cmd_mailbox *inmailbox, *outmailbox;
112 void *inbox;
113 int err;
114 u32 in_modifier = port;
115 u8 op_modifier = 0;
116
117 inmailbox = mlx4_alloc_cmd_mailbox(dev->dev);
118 if (IS_ERR(inmailbox))
119 return PTR_ERR(inmailbox);
120 inbox = inmailbox->buf;
121
122 outmailbox = mlx4_alloc_cmd_mailbox(dev->dev);
123 if (IS_ERR(outmailbox)) {
124 mlx4_free_cmd_mailbox(dev->dev, inmailbox);
125 return PTR_ERR(outmailbox);
126 }
127
128 memcpy(inbox, in_mad, 256);
129
130 /*
131 * Key check traps can't be generated unless we have in_wc to
132 * tell us where to send the trap.
133 */
134 if ((mad_ifc_flags & MLX4_MAD_IFC_IGNORE_MKEY) || !in_wc)
135 op_modifier |= 0x1;
136 if ((mad_ifc_flags & MLX4_MAD_IFC_IGNORE_BKEY) || !in_wc)
137 op_modifier |= 0x2;
138 if (mlx4_is_mfunc(dev->dev) &&
139 (mad_ifc_flags & MLX4_MAD_IFC_NET_VIEW || in_wc))
140 op_modifier |= 0x8;
141
142 if (in_wc) {
143 struct {
144 __be32 my_qpn;
145 u32 reserved1;
146 __be32 rqpn;
147 u8 sl;
148 u8 g_path;
149 u16 reserved2[2];
150 __be16 pkey;
151 u32 reserved3[11];
152 u8 grh[40];
153 } *ext_info;
154
155 memset(inbox + 256, 0, 256);
156 ext_info = inbox + 256;
157
158 ext_info->my_qpn = cpu_to_be32(in_wc->qp->qp_num);
159 ext_info->rqpn = cpu_to_be32(in_wc->src_qp);
160 ext_info->sl = in_wc->sl << 4;
161 ext_info->g_path = in_wc->dlid_path_bits |
162 (in_wc->wc_flags & IB_WC_GRH ? 0x80 : 0);
163 ext_info->pkey = cpu_to_be16(in_wc->pkey_index);
164
165 if (in_grh)
166 memcpy(ext_info->grh, in_grh, 40);
167
168 op_modifier |= 0x4;
169
170 in_modifier |= ib_lid_cpu16(in_wc->slid) << 16;
171 }
172
173 err = mlx4_cmd_box(dev->dev, inmailbox->dma, outmailbox->dma, in_modifier,
174 mlx4_is_master(dev->dev) ? (op_modifier & ~0x8) : op_modifier,
175 MLX4_CMD_MAD_IFC, MLX4_CMD_TIME_CLASS_C,
176 (op_modifier & 0x8) ? MLX4_CMD_NATIVE : MLX4_CMD_WRAPPED);
177
178 if (!err)
179 memcpy(response_mad, outmailbox->buf, 256);
180
181 mlx4_free_cmd_mailbox(dev->dev, inmailbox);
182 mlx4_free_cmd_mailbox(dev->dev, outmailbox);
183
184 return err;
185 }
186
update_sm_ah(struct mlx4_ib_dev * dev,u8 port_num,u16 lid,u8 sl)187 static void update_sm_ah(struct mlx4_ib_dev *dev, u8 port_num, u16 lid, u8 sl)
188 {
189 struct ib_ah *new_ah;
190 struct rdma_ah_attr ah_attr;
191 unsigned long flags;
192
193 if (!dev->send_agent[port_num - 1][0])
194 return;
195
196 memset(&ah_attr, 0, sizeof ah_attr);
197 ah_attr.type = rdma_ah_find_type(&dev->ib_dev, port_num);
198 rdma_ah_set_dlid(&ah_attr, lid);
199 rdma_ah_set_sl(&ah_attr, sl);
200 rdma_ah_set_port_num(&ah_attr, port_num);
201
202 new_ah = rdma_create_ah(dev->send_agent[port_num - 1][0]->qp->pd,
203 &ah_attr, 0);
204 if (IS_ERR(new_ah))
205 return;
206
207 spin_lock_irqsave(&dev->sm_lock, flags);
208 if (dev->sm_ah[port_num - 1])
209 rdma_destroy_ah(dev->sm_ah[port_num - 1], 0);
210 dev->sm_ah[port_num - 1] = new_ah;
211 spin_unlock_irqrestore(&dev->sm_lock, flags);
212 }
213
214 /*
215 * Snoop SM MADs for port info, GUID info, and P_Key table sets, so we can
216 * synthesize LID change, Client-Rereg, GID change, and P_Key change events.
217 */
smp_snoop(struct ib_device * ibdev,u8 port_num,const struct ib_mad * mad,u16 prev_lid)218 static void smp_snoop(struct ib_device *ibdev, u8 port_num, const struct ib_mad *mad,
219 u16 prev_lid)
220 {
221 struct ib_port_info *pinfo;
222 u16 lid;
223 __be16 *base;
224 u32 bn, pkey_change_bitmap;
225 int i;
226
227
228 struct mlx4_ib_dev *dev = to_mdev(ibdev);
229 if ((mad->mad_hdr.mgmt_class == IB_MGMT_CLASS_SUBN_LID_ROUTED ||
230 mad->mad_hdr.mgmt_class == IB_MGMT_CLASS_SUBN_DIRECTED_ROUTE) &&
231 mad->mad_hdr.method == IB_MGMT_METHOD_SET)
232 switch (mad->mad_hdr.attr_id) {
233 case IB_SMP_ATTR_PORT_INFO:
234 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_PORT_MNG_CHG_EV)
235 return;
236 pinfo = (struct ib_port_info *) ((struct ib_smp *) mad)->data;
237 lid = be16_to_cpu(pinfo->lid);
238
239 update_sm_ah(dev, port_num,
240 be16_to_cpu(pinfo->sm_lid),
241 pinfo->neighbormtu_mastersmsl & 0xf);
242
243 if (pinfo->clientrereg_resv_subnetto & 0x80)
244 handle_client_rereg_event(dev, port_num);
245
246 if (prev_lid != lid)
247 handle_lid_change_event(dev, port_num);
248 break;
249
250 case IB_SMP_ATTR_PKEY_TABLE:
251 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_PORT_MNG_CHG_EV)
252 return;
253 if (!mlx4_is_mfunc(dev->dev)) {
254 mlx4_ib_dispatch_event(dev, port_num,
255 IB_EVENT_PKEY_CHANGE);
256 break;
257 }
258
259 /* at this point, we are running in the master.
260 * Slaves do not receive SMPs.
261 */
262 bn = be32_to_cpu(((struct ib_smp *)mad)->attr_mod) & 0xFFFF;
263 base = (__be16 *) &(((struct ib_smp *)mad)->data[0]);
264 pkey_change_bitmap = 0;
265 for (i = 0; i < 32; i++) {
266 pr_debug("PKEY[%d] = x%x\n",
267 i + bn*32, be16_to_cpu(base[i]));
268 if (be16_to_cpu(base[i]) !=
269 dev->pkeys.phys_pkey_cache[port_num - 1][i + bn*32]) {
270 pkey_change_bitmap |= (1 << i);
271 dev->pkeys.phys_pkey_cache[port_num - 1][i + bn*32] =
272 be16_to_cpu(base[i]);
273 }
274 }
275 pr_debug("PKEY Change event: port=%d, "
276 "block=0x%x, change_bitmap=0x%x\n",
277 port_num, bn, pkey_change_bitmap);
278
279 if (pkey_change_bitmap) {
280 mlx4_ib_dispatch_event(dev, port_num,
281 IB_EVENT_PKEY_CHANGE);
282 if (!dev->sriov.is_going_down)
283 __propagate_pkey_ev(dev, port_num, bn,
284 pkey_change_bitmap);
285 }
286 break;
287
288 case IB_SMP_ATTR_GUID_INFO:
289 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_PORT_MNG_CHG_EV)
290 return;
291 /* paravirtualized master's guid is guid 0 -- does not change */
292 if (!mlx4_is_master(dev->dev))
293 mlx4_ib_dispatch_event(dev, port_num,
294 IB_EVENT_GID_CHANGE);
295 /*if master, notify relevant slaves*/
296 if (mlx4_is_master(dev->dev) &&
297 !dev->sriov.is_going_down) {
298 bn = be32_to_cpu(((struct ib_smp *)mad)->attr_mod);
299 mlx4_ib_update_cache_on_guid_change(dev, bn, port_num,
300 (u8 *)(&((struct ib_smp *)mad)->data));
301 mlx4_ib_notify_slaves_on_guid_change(dev, bn, port_num,
302 (u8 *)(&((struct ib_smp *)mad)->data));
303 }
304 break;
305
306 case IB_SMP_ATTR_SL_TO_VL_TABLE:
307 /* cache sl to vl mapping changes for use in
308 * filling QP1 LRH VL field when sending packets
309 */
310 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_PORT_MNG_CHG_EV &&
311 dev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_SL_TO_VL_CHANGE_EVENT)
312 return;
313 if (!mlx4_is_slave(dev->dev)) {
314 union sl2vl_tbl_to_u64 sl2vl64;
315 int jj;
316
317 for (jj = 0; jj < 8; jj++) {
318 sl2vl64.sl8[jj] = ((struct ib_smp *)mad)->data[jj];
319 pr_debug("sl2vl[%d] = %02x\n", jj, sl2vl64.sl8[jj]);
320 }
321 atomic64_set(&dev->sl2vl[port_num - 1], sl2vl64.sl64);
322 }
323 break;
324
325 default:
326 break;
327 }
328 }
329
__propagate_pkey_ev(struct mlx4_ib_dev * dev,int port_num,int block,u32 change_bitmap)330 static void __propagate_pkey_ev(struct mlx4_ib_dev *dev, int port_num,
331 int block, u32 change_bitmap)
332 {
333 int i, ix, slave, err;
334 int have_event = 0;
335
336 for (slave = 0; slave < dev->dev->caps.sqp_demux; slave++) {
337 if (slave == mlx4_master_func_num(dev->dev))
338 continue;
339 if (!mlx4_is_slave_active(dev->dev, slave))
340 continue;
341
342 have_event = 0;
343 for (i = 0; i < 32; i++) {
344 if (!(change_bitmap & (1 << i)))
345 continue;
346 for (ix = 0;
347 ix < dev->dev->caps.pkey_table_len[port_num]; ix++) {
348 if (dev->pkeys.virt2phys_pkey[slave][port_num - 1]
349 [ix] == i + 32 * block) {
350 err = mlx4_gen_pkey_eqe(dev->dev, slave, port_num);
351 pr_debug("propagate_pkey_ev: slave %d,"
352 " port %d, ix %d (%d)\n",
353 slave, port_num, ix, err);
354 have_event = 1;
355 break;
356 }
357 }
358 if (have_event)
359 break;
360 }
361 }
362 }
363
node_desc_override(struct ib_device * dev,struct ib_mad * mad)364 static void node_desc_override(struct ib_device *dev,
365 struct ib_mad *mad)
366 {
367 unsigned long flags;
368
369 if ((mad->mad_hdr.mgmt_class == IB_MGMT_CLASS_SUBN_LID_ROUTED ||
370 mad->mad_hdr.mgmt_class == IB_MGMT_CLASS_SUBN_DIRECTED_ROUTE) &&
371 mad->mad_hdr.method == IB_MGMT_METHOD_GET_RESP &&
372 mad->mad_hdr.attr_id == IB_SMP_ATTR_NODE_DESC) {
373 spin_lock_irqsave(&to_mdev(dev)->sm_lock, flags);
374 memcpy(((struct ib_smp *) mad)->data, dev->node_desc,
375 IB_DEVICE_NODE_DESC_MAX);
376 spin_unlock_irqrestore(&to_mdev(dev)->sm_lock, flags);
377 }
378 }
379
forward_trap(struct mlx4_ib_dev * dev,u8 port_num,const struct ib_mad * mad)380 static void forward_trap(struct mlx4_ib_dev *dev, u8 port_num, const struct ib_mad *mad)
381 {
382 int qpn = mad->mad_hdr.mgmt_class != IB_MGMT_CLASS_SUBN_LID_ROUTED;
383 struct ib_mad_send_buf *send_buf;
384 struct ib_mad_agent *agent = dev->send_agent[port_num - 1][qpn];
385 int ret;
386 unsigned long flags;
387
388 if (agent) {
389 send_buf = ib_create_send_mad(agent, qpn, 0, 0, IB_MGMT_MAD_HDR,
390 IB_MGMT_MAD_DATA, GFP_ATOMIC,
391 IB_MGMT_BASE_VERSION);
392 if (IS_ERR(send_buf))
393 return;
394 /*
395 * We rely here on the fact that MLX QPs don't use the
396 * address handle after the send is posted (this is
397 * wrong following the IB spec strictly, but we know
398 * it's OK for our devices).
399 */
400 spin_lock_irqsave(&dev->sm_lock, flags);
401 memcpy(send_buf->mad, mad, sizeof *mad);
402 if ((send_buf->ah = dev->sm_ah[port_num - 1]))
403 ret = ib_post_send_mad(send_buf, NULL);
404 else
405 ret = -EINVAL;
406 spin_unlock_irqrestore(&dev->sm_lock, flags);
407
408 if (ret)
409 ib_free_send_mad(send_buf);
410 }
411 }
412
mlx4_ib_demux_sa_handler(struct ib_device * ibdev,int port,int slave,struct ib_sa_mad * sa_mad)413 static int mlx4_ib_demux_sa_handler(struct ib_device *ibdev, int port, int slave,
414 struct ib_sa_mad *sa_mad)
415 {
416 int ret = 0;
417
418 /* dispatch to different sa handlers */
419 switch (be16_to_cpu(sa_mad->mad_hdr.attr_id)) {
420 case IB_SA_ATTR_MC_MEMBER_REC:
421 ret = mlx4_ib_mcg_demux_handler(ibdev, port, slave, sa_mad);
422 break;
423 default:
424 break;
425 }
426 return ret;
427 }
428
mlx4_ib_find_real_gid(struct ib_device * ibdev,u8 port,__be64 guid)429 int mlx4_ib_find_real_gid(struct ib_device *ibdev, u8 port, __be64 guid)
430 {
431 struct mlx4_ib_dev *dev = to_mdev(ibdev);
432 int i;
433
434 for (i = 0; i < dev->dev->caps.sqp_demux; i++) {
435 if (dev->sriov.demux[port - 1].guid_cache[i] == guid)
436 return i;
437 }
438 return -1;
439 }
440
441
find_slave_port_pkey_ix(struct mlx4_ib_dev * dev,int slave,u8 port,u16 pkey,u16 * ix)442 static int find_slave_port_pkey_ix(struct mlx4_ib_dev *dev, int slave,
443 u8 port, u16 pkey, u16 *ix)
444 {
445 int i, ret;
446 u8 unassigned_pkey_ix, pkey_ix, partial_ix = 0xFF;
447 u16 slot_pkey;
448
449 if (slave == mlx4_master_func_num(dev->dev))
450 return ib_find_cached_pkey(&dev->ib_dev, port, pkey, ix);
451
452 unassigned_pkey_ix = dev->dev->phys_caps.pkey_phys_table_len[port] - 1;
453
454 for (i = 0; i < dev->dev->caps.pkey_table_len[port]; i++) {
455 if (dev->pkeys.virt2phys_pkey[slave][port - 1][i] == unassigned_pkey_ix)
456 continue;
457
458 pkey_ix = dev->pkeys.virt2phys_pkey[slave][port - 1][i];
459
460 ret = ib_get_cached_pkey(&dev->ib_dev, port, pkey_ix, &slot_pkey);
461 if (ret)
462 continue;
463 if ((slot_pkey & 0x7FFF) == (pkey & 0x7FFF)) {
464 if (slot_pkey & 0x8000) {
465 *ix = (u16) pkey_ix;
466 return 0;
467 } else {
468 /* take first partial pkey index found */
469 if (partial_ix == 0xFF)
470 partial_ix = pkey_ix;
471 }
472 }
473 }
474
475 if (partial_ix < 0xFF) {
476 *ix = (u16) partial_ix;
477 return 0;
478 }
479
480 return -EINVAL;
481 }
482
get_gids_from_l3_hdr(struct ib_grh * grh,union ib_gid * sgid,union ib_gid * dgid)483 static int get_gids_from_l3_hdr(struct ib_grh *grh, union ib_gid *sgid,
484 union ib_gid *dgid)
485 {
486 int version = ib_get_rdma_header_version((const union rdma_network_hdr *)grh);
487 enum rdma_network_type net_type;
488
489 if (version == 4)
490 net_type = RDMA_NETWORK_IPV4;
491 else if (version == 6)
492 net_type = RDMA_NETWORK_IPV6;
493 else
494 return -EINVAL;
495
496 return ib_get_gids_from_rdma_hdr((union rdma_network_hdr *)grh, net_type,
497 sgid, dgid);
498 }
499
mlx4_ib_send_to_slave(struct mlx4_ib_dev * dev,int slave,u8 port,enum ib_qp_type dest_qpt,struct ib_wc * wc,struct ib_grh * grh,struct ib_mad * mad)500 int mlx4_ib_send_to_slave(struct mlx4_ib_dev *dev, int slave, u8 port,
501 enum ib_qp_type dest_qpt, struct ib_wc *wc,
502 struct ib_grh *grh, struct ib_mad *mad)
503 {
504 struct ib_sge list;
505 struct ib_ud_wr wr;
506 const struct ib_send_wr *bad_wr;
507 struct mlx4_ib_demux_pv_ctx *tun_ctx;
508 struct mlx4_ib_demux_pv_qp *tun_qp;
509 struct mlx4_rcv_tunnel_mad *tun_mad;
510 struct rdma_ah_attr attr;
511 struct ib_ah *ah;
512 struct ib_qp *src_qp = NULL;
513 unsigned tun_tx_ix = 0;
514 int dqpn;
515 int ret = 0;
516 u16 tun_pkey_ix;
517 u16 cached_pkey;
518 u8 is_eth = dev->dev->caps.port_type[port] == MLX4_PORT_TYPE_ETH;
519
520 if (dest_qpt > IB_QPT_GSI)
521 return -EINVAL;
522
523 tun_ctx = dev->sriov.demux[port-1].tun[slave];
524
525 /* check if proxy qp created */
526 if (!tun_ctx || tun_ctx->state != DEMUX_PV_STATE_ACTIVE)
527 return -EAGAIN;
528
529 if (!dest_qpt)
530 tun_qp = &tun_ctx->qp[0];
531 else
532 tun_qp = &tun_ctx->qp[1];
533
534 /* compute P_Key index to put in tunnel header for slave */
535 if (dest_qpt) {
536 u16 pkey_ix;
537 ret = ib_get_cached_pkey(&dev->ib_dev, port, wc->pkey_index, &cached_pkey);
538 if (ret)
539 return -EINVAL;
540
541 ret = find_slave_port_pkey_ix(dev, slave, port, cached_pkey, &pkey_ix);
542 if (ret)
543 return -EINVAL;
544 tun_pkey_ix = pkey_ix;
545 } else
546 tun_pkey_ix = dev->pkeys.virt2phys_pkey[slave][port - 1][0];
547
548 dqpn = dev->dev->phys_caps.base_proxy_sqpn + 8 * slave + port + (dest_qpt * 2) - 1;
549
550 /* get tunnel tx data buf for slave */
551 src_qp = tun_qp->qp;
552
553 /* create ah. Just need an empty one with the port num for the post send.
554 * The driver will set the force loopback bit in post_send */
555 memset(&attr, 0, sizeof attr);
556 attr.type = rdma_ah_find_type(&dev->ib_dev, port);
557
558 rdma_ah_set_port_num(&attr, port);
559 if (is_eth) {
560 union ib_gid sgid;
561 union ib_gid dgid;
562
563 if (get_gids_from_l3_hdr(grh, &sgid, &dgid))
564 return -EINVAL;
565 attr.ah_flags = IB_AH_GRH;
566 rdma_ah_set_grh(&attr, &dgid, 0, 0, 0, 0);
567 }
568 ah = rdma_create_ah(tun_ctx->pd, &attr, 0);
569 if (IS_ERR(ah))
570 return -ENOMEM;
571
572 /* allocate tunnel tx buf after pass failure returns */
573 spin_lock(&tun_qp->tx_lock);
574 if (tun_qp->tx_ix_head - tun_qp->tx_ix_tail >=
575 (MLX4_NUM_TUNNEL_BUFS - 1))
576 ret = -EAGAIN;
577 else
578 tun_tx_ix = (++tun_qp->tx_ix_head) & (MLX4_NUM_TUNNEL_BUFS - 1);
579 spin_unlock(&tun_qp->tx_lock);
580 if (ret)
581 goto end;
582
583 tun_mad = (struct mlx4_rcv_tunnel_mad *) (tun_qp->tx_ring[tun_tx_ix].buf.addr);
584 if (tun_qp->tx_ring[tun_tx_ix].ah)
585 rdma_destroy_ah(tun_qp->tx_ring[tun_tx_ix].ah, 0);
586 tun_qp->tx_ring[tun_tx_ix].ah = ah;
587 ib_dma_sync_single_for_cpu(&dev->ib_dev,
588 tun_qp->tx_ring[tun_tx_ix].buf.map,
589 sizeof (struct mlx4_rcv_tunnel_mad),
590 DMA_TO_DEVICE);
591
592 /* copy over to tunnel buffer */
593 if (grh)
594 memcpy(&tun_mad->grh, grh, sizeof *grh);
595 memcpy(&tun_mad->mad, mad, sizeof *mad);
596
597 /* adjust tunnel data */
598 tun_mad->hdr.pkey_index = cpu_to_be16(tun_pkey_ix);
599 tun_mad->hdr.flags_src_qp = cpu_to_be32(wc->src_qp & 0xFFFFFF);
600 tun_mad->hdr.g_ml_path = (grh && (wc->wc_flags & IB_WC_GRH)) ? 0x80 : 0;
601
602 if (is_eth) {
603 u16 vlan = 0;
604 if (mlx4_get_slave_default_vlan(dev->dev, port, slave, &vlan,
605 NULL)) {
606 /* VST mode */
607 if (vlan != wc->vlan_id) {
608 /* Packet vlan is not the VST-assigned vlan.
609 * Drop the packet.
610 */
611 ret = -EPERM;
612 goto out;
613 } else {
614 /* Remove the vlan tag before forwarding
615 * the packet to the VF.
616 */
617 vlan = 0xffff;
618 }
619 } else {
620 vlan = wc->vlan_id;
621 }
622
623 tun_mad->hdr.sl_vid = cpu_to_be16(vlan);
624 memcpy((char *)&tun_mad->hdr.mac_31_0, &(wc->smac[0]), 4);
625 memcpy((char *)&tun_mad->hdr.slid_mac_47_32, &(wc->smac[4]), 2);
626 } else {
627 tun_mad->hdr.sl_vid = cpu_to_be16(((u16)(wc->sl)) << 12);
628 tun_mad->hdr.slid_mac_47_32 = ib_lid_be16(wc->slid);
629 }
630
631 ib_dma_sync_single_for_device(&dev->ib_dev,
632 tun_qp->tx_ring[tun_tx_ix].buf.map,
633 sizeof (struct mlx4_rcv_tunnel_mad),
634 DMA_TO_DEVICE);
635
636 list.addr = tun_qp->tx_ring[tun_tx_ix].buf.map;
637 list.length = sizeof (struct mlx4_rcv_tunnel_mad);
638 list.lkey = tun_ctx->pd->local_dma_lkey;
639
640 wr.ah = ah;
641 wr.port_num = port;
642 wr.remote_qkey = IB_QP_SET_QKEY;
643 wr.remote_qpn = dqpn;
644 wr.wr.next = NULL;
645 wr.wr.wr_id = ((u64) tun_tx_ix) | MLX4_TUN_SET_WRID_QPN(dest_qpt);
646 wr.wr.sg_list = &list;
647 wr.wr.num_sge = 1;
648 wr.wr.opcode = IB_WR_SEND;
649 wr.wr.send_flags = IB_SEND_SIGNALED;
650
651 ret = ib_post_send(src_qp, &wr.wr, &bad_wr);
652 if (!ret)
653 return 0;
654 out:
655 spin_lock(&tun_qp->tx_lock);
656 tun_qp->tx_ix_tail++;
657 spin_unlock(&tun_qp->tx_lock);
658 tun_qp->tx_ring[tun_tx_ix].ah = NULL;
659 end:
660 rdma_destroy_ah(ah, 0);
661 return ret;
662 }
663
mlx4_ib_demux_mad(struct ib_device * ibdev,u8 port,struct ib_wc * wc,struct ib_grh * grh,struct ib_mad * mad)664 static int mlx4_ib_demux_mad(struct ib_device *ibdev, u8 port,
665 struct ib_wc *wc, struct ib_grh *grh,
666 struct ib_mad *mad)
667 {
668 struct mlx4_ib_dev *dev = to_mdev(ibdev);
669 int err, other_port;
670 int slave = -1;
671 u8 *slave_id;
672 int is_eth = 0;
673
674 if (rdma_port_get_link_layer(ibdev, port) == IB_LINK_LAYER_INFINIBAND)
675 is_eth = 0;
676 else
677 is_eth = 1;
678
679 if (is_eth) {
680 if (!(wc->wc_flags & IB_WC_GRH)) {
681 mlx4_ib_warn(ibdev, "RoCE grh not present.\n");
682 return -EINVAL;
683 }
684 if (mad->mad_hdr.mgmt_class != IB_MGMT_CLASS_CM) {
685 mlx4_ib_warn(ibdev, "RoCE mgmt class is not CM\n");
686 return -EINVAL;
687 }
688 err = mlx4_get_slave_from_roce_gid(dev->dev, port, grh->dgid.raw, &slave);
689 if (err && mlx4_is_mf_bonded(dev->dev)) {
690 other_port = (port == 1) ? 2 : 1;
691 err = mlx4_get_slave_from_roce_gid(dev->dev, other_port, grh->dgid.raw, &slave);
692 if (!err) {
693 port = other_port;
694 pr_debug("resolved slave %d from gid %pI6 wire port %d other %d\n",
695 slave, grh->dgid.raw, port, other_port);
696 }
697 }
698 if (err) {
699 mlx4_ib_warn(ibdev, "failed matching grh\n");
700 return -ENOENT;
701 }
702 if (slave >= dev->dev->caps.sqp_demux) {
703 mlx4_ib_warn(ibdev, "slave id: %d is bigger than allowed:%d\n",
704 slave, dev->dev->caps.sqp_demux);
705 return -ENOENT;
706 }
707
708 if (mlx4_ib_demux_cm_handler(ibdev, port, NULL, mad))
709 return 0;
710
711 err = mlx4_ib_send_to_slave(dev, slave, port, wc->qp->qp_type, wc, grh, mad);
712 if (err)
713 pr_debug("failed sending to slave %d via tunnel qp (%d)\n",
714 slave, err);
715 return 0;
716 }
717
718 /* Initially assume that this mad is for us */
719 slave = mlx4_master_func_num(dev->dev);
720
721 /* See if the slave id is encoded in a response mad */
722 if (mad->mad_hdr.method & 0x80) {
723 slave_id = (u8 *) &mad->mad_hdr.tid;
724 slave = *slave_id;
725 if (slave != 255) /*255 indicates the dom0*/
726 *slave_id = 0; /* remap tid */
727 }
728
729 /* If a grh is present, we demux according to it */
730 if (wc->wc_flags & IB_WC_GRH) {
731 slave = mlx4_ib_find_real_gid(ibdev, port, grh->dgid.global.interface_id);
732 if (slave < 0) {
733 mlx4_ib_warn(ibdev, "failed matching grh\n");
734 return -ENOENT;
735 }
736 }
737 /* Class-specific handling */
738 switch (mad->mad_hdr.mgmt_class) {
739 case IB_MGMT_CLASS_SUBN_LID_ROUTED:
740 case IB_MGMT_CLASS_SUBN_DIRECTED_ROUTE:
741 /* 255 indicates the dom0 */
742 if (slave != 255 && slave != mlx4_master_func_num(dev->dev)) {
743 if (!mlx4_vf_smi_enabled(dev->dev, slave, port))
744 return -EPERM;
745 /* for a VF. drop unsolicited MADs */
746 if (!(mad->mad_hdr.method & IB_MGMT_METHOD_RESP)) {
747 mlx4_ib_warn(ibdev, "demux QP0. rejecting unsolicited mad for slave %d class 0x%x, method 0x%x\n",
748 slave, mad->mad_hdr.mgmt_class,
749 mad->mad_hdr.method);
750 return -EINVAL;
751 }
752 }
753 break;
754 case IB_MGMT_CLASS_SUBN_ADM:
755 if (mlx4_ib_demux_sa_handler(ibdev, port, slave,
756 (struct ib_sa_mad *) mad))
757 return 0;
758 break;
759 case IB_MGMT_CLASS_CM:
760 if (mlx4_ib_demux_cm_handler(ibdev, port, &slave, mad))
761 return 0;
762 break;
763 case IB_MGMT_CLASS_DEVICE_MGMT:
764 if (mad->mad_hdr.method != IB_MGMT_METHOD_GET_RESP)
765 return 0;
766 break;
767 default:
768 /* Drop unsupported classes for slaves in tunnel mode */
769 if (slave != mlx4_master_func_num(dev->dev)) {
770 pr_debug("dropping unsupported ingress mad from class:%d "
771 "for slave:%d\n", mad->mad_hdr.mgmt_class, slave);
772 return 0;
773 }
774 }
775 /*make sure that no slave==255 was not handled yet.*/
776 if (slave >= dev->dev->caps.sqp_demux) {
777 mlx4_ib_warn(ibdev, "slave id: %d is bigger than allowed:%d\n",
778 slave, dev->dev->caps.sqp_demux);
779 return -ENOENT;
780 }
781
782 err = mlx4_ib_send_to_slave(dev, slave, port, wc->qp->qp_type, wc, grh, mad);
783 if (err)
784 pr_debug("failed sending to slave %d via tunnel qp (%d)\n",
785 slave, err);
786 return 0;
787 }
788
ib_process_mad(struct ib_device * ibdev,int mad_flags,u8 port_num,const struct ib_wc * in_wc,const struct ib_grh * in_grh,const struct ib_mad * in_mad,struct ib_mad * out_mad)789 static int ib_process_mad(struct ib_device *ibdev, int mad_flags, u8 port_num,
790 const struct ib_wc *in_wc, const struct ib_grh *in_grh,
791 const struct ib_mad *in_mad, struct ib_mad *out_mad)
792 {
793 u16 slid, prev_lid = 0;
794 int err;
795 struct ib_port_attr pattr;
796
797 if (in_wc && in_wc->qp->qp_num) {
798 pr_debug("received MAD: slid:%d sqpn:%d "
799 "dlid_bits:%d dqpn:%d wc_flags:0x%x, cls %x, mtd %x, atr %x\n",
800 ib_lid_cpu16(in_wc->slid), in_wc->src_qp,
801 in_wc->dlid_path_bits,
802 in_wc->qp->qp_num,
803 in_wc->wc_flags,
804 in_mad->mad_hdr.mgmt_class, in_mad->mad_hdr.method,
805 be16_to_cpu(in_mad->mad_hdr.attr_id));
806 if (in_wc->wc_flags & IB_WC_GRH) {
807 pr_debug("sgid_hi:0x%016llx sgid_lo:0x%016llx\n",
808 (unsigned long long)be64_to_cpu(in_grh->sgid.global.subnet_prefix),
809 (unsigned long long)be64_to_cpu(in_grh->sgid.global.interface_id));
810 pr_debug("dgid_hi:0x%016llx dgid_lo:0x%016llx\n",
811 (unsigned long long)be64_to_cpu(in_grh->dgid.global.subnet_prefix),
812 (unsigned long long)be64_to_cpu(in_grh->dgid.global.interface_id));
813 }
814 }
815
816 slid = in_wc ? ib_lid_cpu16(in_wc->slid) : be16_to_cpu(IB_LID_PERMISSIVE);
817
818 if (in_mad->mad_hdr.method == IB_MGMT_METHOD_TRAP && slid == 0) {
819 forward_trap(to_mdev(ibdev), port_num, in_mad);
820 return IB_MAD_RESULT_SUCCESS | IB_MAD_RESULT_CONSUMED;
821 }
822
823 if (in_mad->mad_hdr.mgmt_class == IB_MGMT_CLASS_SUBN_LID_ROUTED ||
824 in_mad->mad_hdr.mgmt_class == IB_MGMT_CLASS_SUBN_DIRECTED_ROUTE) {
825 if (in_mad->mad_hdr.method != IB_MGMT_METHOD_GET &&
826 in_mad->mad_hdr.method != IB_MGMT_METHOD_SET &&
827 in_mad->mad_hdr.method != IB_MGMT_METHOD_TRAP_REPRESS)
828 return IB_MAD_RESULT_SUCCESS;
829
830 /*
831 * Don't process SMInfo queries -- the SMA can't handle them.
832 */
833 if (in_mad->mad_hdr.attr_id == IB_SMP_ATTR_SM_INFO)
834 return IB_MAD_RESULT_SUCCESS;
835 } else if (in_mad->mad_hdr.mgmt_class == IB_MGMT_CLASS_PERF_MGMT ||
836 in_mad->mad_hdr.mgmt_class == MLX4_IB_VENDOR_CLASS1 ||
837 in_mad->mad_hdr.mgmt_class == MLX4_IB_VENDOR_CLASS2 ||
838 in_mad->mad_hdr.mgmt_class == IB_MGMT_CLASS_CONG_MGMT) {
839 if (in_mad->mad_hdr.method != IB_MGMT_METHOD_GET &&
840 in_mad->mad_hdr.method != IB_MGMT_METHOD_SET)
841 return IB_MAD_RESULT_SUCCESS;
842 } else
843 return IB_MAD_RESULT_SUCCESS;
844
845 if ((in_mad->mad_hdr.mgmt_class == IB_MGMT_CLASS_SUBN_LID_ROUTED ||
846 in_mad->mad_hdr.mgmt_class == IB_MGMT_CLASS_SUBN_DIRECTED_ROUTE) &&
847 in_mad->mad_hdr.method == IB_MGMT_METHOD_SET &&
848 in_mad->mad_hdr.attr_id == IB_SMP_ATTR_PORT_INFO &&
849 !ib_query_port(ibdev, port_num, &pattr))
850 prev_lid = ib_lid_cpu16(pattr.lid);
851
852 err = mlx4_MAD_IFC(to_mdev(ibdev),
853 (mad_flags & IB_MAD_IGNORE_MKEY ? MLX4_MAD_IFC_IGNORE_MKEY : 0) |
854 (mad_flags & IB_MAD_IGNORE_BKEY ? MLX4_MAD_IFC_IGNORE_BKEY : 0) |
855 MLX4_MAD_IFC_NET_VIEW,
856 port_num, in_wc, in_grh, in_mad, out_mad);
857 if (err)
858 return IB_MAD_RESULT_FAILURE;
859
860 if (!out_mad->mad_hdr.status) {
861 smp_snoop(ibdev, port_num, in_mad, prev_lid);
862 /* slaves get node desc from FW */
863 if (!mlx4_is_slave(to_mdev(ibdev)->dev))
864 node_desc_override(ibdev, out_mad);
865 }
866
867 /* set return bit in status of directed route responses */
868 if (in_mad->mad_hdr.mgmt_class == IB_MGMT_CLASS_SUBN_DIRECTED_ROUTE)
869 out_mad->mad_hdr.status |= cpu_to_be16(1 << 15);
870
871 if (in_mad->mad_hdr.method == IB_MGMT_METHOD_TRAP_REPRESS)
872 /* no response for trap repress */
873 return IB_MAD_RESULT_SUCCESS | IB_MAD_RESULT_CONSUMED;
874
875 return IB_MAD_RESULT_SUCCESS | IB_MAD_RESULT_REPLY;
876 }
877
edit_counter(struct mlx4_counter * cnt,void * counters,__be16 attr_id)878 static void edit_counter(struct mlx4_counter *cnt, void *counters,
879 __be16 attr_id)
880 {
881 switch (attr_id) {
882 case IB_PMA_PORT_COUNTERS:
883 {
884 struct ib_pma_portcounters *pma_cnt =
885 (struct ib_pma_portcounters *)counters;
886
887 ASSIGN_32BIT_COUNTER(pma_cnt->port_xmit_data,
888 (be64_to_cpu(cnt->tx_bytes) >> 2));
889 ASSIGN_32BIT_COUNTER(pma_cnt->port_rcv_data,
890 (be64_to_cpu(cnt->rx_bytes) >> 2));
891 ASSIGN_32BIT_COUNTER(pma_cnt->port_xmit_packets,
892 be64_to_cpu(cnt->tx_frames));
893 ASSIGN_32BIT_COUNTER(pma_cnt->port_rcv_packets,
894 be64_to_cpu(cnt->rx_frames));
895 break;
896 }
897 case IB_PMA_PORT_COUNTERS_EXT:
898 {
899 struct ib_pma_portcounters_ext *pma_cnt_ext =
900 (struct ib_pma_portcounters_ext *)counters;
901
902 pma_cnt_ext->port_xmit_data =
903 cpu_to_be64(be64_to_cpu(cnt->tx_bytes) >> 2);
904 pma_cnt_ext->port_rcv_data =
905 cpu_to_be64(be64_to_cpu(cnt->rx_bytes) >> 2);
906 pma_cnt_ext->port_xmit_packets = cnt->tx_frames;
907 pma_cnt_ext->port_rcv_packets = cnt->rx_frames;
908 break;
909 }
910 default:
911 break;
912 }
913 }
914
iboe_process_mad_port_info(void * out_mad)915 static int iboe_process_mad_port_info(void *out_mad)
916 {
917 struct ib_class_port_info cpi = {};
918
919 cpi.capability_mask = IB_PMA_CLASS_CAP_EXT_WIDTH;
920 memcpy(out_mad, &cpi, sizeof(cpi));
921 return IB_MAD_RESULT_SUCCESS | IB_MAD_RESULT_REPLY;
922 }
923
iboe_process_mad(struct ib_device * ibdev,int mad_flags,u8 port_num,const struct ib_wc * in_wc,const struct ib_grh * in_grh,const struct ib_mad * in_mad,struct ib_mad * out_mad)924 static int iboe_process_mad(struct ib_device *ibdev, int mad_flags, u8 port_num,
925 const struct ib_wc *in_wc, const struct ib_grh *in_grh,
926 const struct ib_mad *in_mad, struct ib_mad *out_mad)
927 {
928 struct mlx4_counter counter_stats;
929 struct mlx4_ib_dev *dev = to_mdev(ibdev);
930 struct counter_index *tmp_counter;
931 int err = IB_MAD_RESULT_FAILURE, stats_avail = 0;
932
933 if (in_mad->mad_hdr.mgmt_class != IB_MGMT_CLASS_PERF_MGMT)
934 return -EINVAL;
935
936 if (in_mad->mad_hdr.attr_id == IB_PMA_CLASS_PORT_INFO)
937 return iboe_process_mad_port_info((void *)(out_mad->data + 40));
938
939 memset(&counter_stats, 0, sizeof(counter_stats));
940 mutex_lock(&dev->counters_table[port_num - 1].mutex);
941 list_for_each_entry(tmp_counter,
942 &dev->counters_table[port_num - 1].counters_list,
943 list) {
944 err = mlx4_get_counter_stats(dev->dev,
945 tmp_counter->index,
946 &counter_stats, 0);
947 if (err) {
948 err = IB_MAD_RESULT_FAILURE;
949 stats_avail = 0;
950 break;
951 }
952 stats_avail = 1;
953 }
954 mutex_unlock(&dev->counters_table[port_num - 1].mutex);
955 if (stats_avail) {
956 memset(out_mad->data, 0, sizeof out_mad->data);
957 switch (counter_stats.counter_mode & 0xf) {
958 case 0:
959 edit_counter(&counter_stats,
960 (void *)(out_mad->data + 40),
961 in_mad->mad_hdr.attr_id);
962 err = IB_MAD_RESULT_SUCCESS | IB_MAD_RESULT_REPLY;
963 break;
964 default:
965 err = IB_MAD_RESULT_FAILURE;
966 }
967 }
968
969 return err;
970 }
971
mlx4_ib_process_mad(struct ib_device * ibdev,int mad_flags,u8 port_num,const struct ib_wc * in_wc,const struct ib_grh * in_grh,const struct ib_mad_hdr * in,size_t in_mad_size,struct ib_mad_hdr * out,size_t * out_mad_size,u16 * out_mad_pkey_index)972 int mlx4_ib_process_mad(struct ib_device *ibdev, int mad_flags, u8 port_num,
973 const struct ib_wc *in_wc, const struct ib_grh *in_grh,
974 const struct ib_mad_hdr *in, size_t in_mad_size,
975 struct ib_mad_hdr *out, size_t *out_mad_size,
976 u16 *out_mad_pkey_index)
977 {
978 struct mlx4_ib_dev *dev = to_mdev(ibdev);
979 const struct ib_mad *in_mad = (const struct ib_mad *)in;
980 struct ib_mad *out_mad = (struct ib_mad *)out;
981 enum rdma_link_layer link = rdma_port_get_link_layer(ibdev, port_num);
982
983 if (WARN_ON_ONCE(in_mad_size != sizeof(*in_mad) ||
984 *out_mad_size != sizeof(*out_mad)))
985 return IB_MAD_RESULT_FAILURE;
986
987 /* iboe_process_mad() which uses the HCA flow-counters to implement IB PMA
988 * queries, should be called only by VFs and for that specific purpose
989 */
990 if (link == IB_LINK_LAYER_INFINIBAND) {
991 if (mlx4_is_slave(dev->dev) &&
992 (in_mad->mad_hdr.mgmt_class == IB_MGMT_CLASS_PERF_MGMT &&
993 (in_mad->mad_hdr.attr_id == IB_PMA_PORT_COUNTERS ||
994 in_mad->mad_hdr.attr_id == IB_PMA_PORT_COUNTERS_EXT ||
995 in_mad->mad_hdr.attr_id == IB_PMA_CLASS_PORT_INFO)))
996 return iboe_process_mad(ibdev, mad_flags, port_num, in_wc,
997 in_grh, in_mad, out_mad);
998
999 return ib_process_mad(ibdev, mad_flags, port_num, in_wc,
1000 in_grh, in_mad, out_mad);
1001 }
1002
1003 if (link == IB_LINK_LAYER_ETHERNET)
1004 return iboe_process_mad(ibdev, mad_flags, port_num, in_wc,
1005 in_grh, in_mad, out_mad);
1006
1007 return -EINVAL;
1008 }
1009
send_handler(struct ib_mad_agent * agent,struct ib_mad_send_wc * mad_send_wc)1010 static void send_handler(struct ib_mad_agent *agent,
1011 struct ib_mad_send_wc *mad_send_wc)
1012 {
1013 if (mad_send_wc->send_buf->context[0])
1014 rdma_destroy_ah(mad_send_wc->send_buf->context[0], 0);
1015 ib_free_send_mad(mad_send_wc->send_buf);
1016 }
1017
mlx4_ib_mad_init(struct mlx4_ib_dev * dev)1018 int mlx4_ib_mad_init(struct mlx4_ib_dev *dev)
1019 {
1020 struct ib_mad_agent *agent;
1021 int p, q;
1022 int ret;
1023 enum rdma_link_layer ll;
1024
1025 for (p = 0; p < dev->num_ports; ++p) {
1026 ll = rdma_port_get_link_layer(&dev->ib_dev, p + 1);
1027 for (q = 0; q <= 1; ++q) {
1028 if (ll == IB_LINK_LAYER_INFINIBAND) {
1029 agent = ib_register_mad_agent(&dev->ib_dev, p + 1,
1030 q ? IB_QPT_GSI : IB_QPT_SMI,
1031 NULL, 0, send_handler,
1032 NULL, NULL, 0);
1033 if (IS_ERR(agent)) {
1034 ret = PTR_ERR(agent);
1035 goto err;
1036 }
1037 dev->send_agent[p][q] = agent;
1038 } else
1039 dev->send_agent[p][q] = NULL;
1040 }
1041 }
1042
1043 return 0;
1044
1045 err:
1046 for (p = 0; p < dev->num_ports; ++p)
1047 for (q = 0; q <= 1; ++q)
1048 if (dev->send_agent[p][q])
1049 ib_unregister_mad_agent(dev->send_agent[p][q]);
1050
1051 return ret;
1052 }
1053
mlx4_ib_mad_cleanup(struct mlx4_ib_dev * dev)1054 void mlx4_ib_mad_cleanup(struct mlx4_ib_dev *dev)
1055 {
1056 struct ib_mad_agent *agent;
1057 int p, q;
1058
1059 for (p = 0; p < dev->num_ports; ++p) {
1060 for (q = 0; q <= 1; ++q) {
1061 agent = dev->send_agent[p][q];
1062 if (agent) {
1063 dev->send_agent[p][q] = NULL;
1064 ib_unregister_mad_agent(agent);
1065 }
1066 }
1067
1068 if (dev->sm_ah[p])
1069 rdma_destroy_ah(dev->sm_ah[p], 0);
1070 }
1071 }
1072
handle_lid_change_event(struct mlx4_ib_dev * dev,u8 port_num)1073 static void handle_lid_change_event(struct mlx4_ib_dev *dev, u8 port_num)
1074 {
1075 mlx4_ib_dispatch_event(dev, port_num, IB_EVENT_LID_CHANGE);
1076
1077 if (mlx4_is_master(dev->dev) && !dev->sriov.is_going_down)
1078 mlx4_gen_slaves_port_mgt_ev(dev->dev, port_num,
1079 MLX4_EQ_PORT_INFO_LID_CHANGE_MASK);
1080 }
1081
handle_client_rereg_event(struct mlx4_ib_dev * dev,u8 port_num)1082 static void handle_client_rereg_event(struct mlx4_ib_dev *dev, u8 port_num)
1083 {
1084 /* re-configure the alias-guid and mcg's */
1085 if (mlx4_is_master(dev->dev)) {
1086 mlx4_ib_invalidate_all_guid_record(dev, port_num);
1087
1088 if (!dev->sriov.is_going_down) {
1089 mlx4_ib_mcg_port_cleanup(&dev->sriov.demux[port_num - 1], 0);
1090 mlx4_gen_slaves_port_mgt_ev(dev->dev, port_num,
1091 MLX4_EQ_PORT_INFO_CLIENT_REREG_MASK);
1092 }
1093 }
1094
1095 /* Update the sl to vl table from inside client rereg
1096 * only if in secure-host mode (snooping is not possible)
1097 * and the sl-to-vl change event is not generated by FW.
1098 */
1099 if (!mlx4_is_slave(dev->dev) &&
1100 dev->dev->flags & MLX4_FLAG_SECURE_HOST &&
1101 !(dev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_SL_TO_VL_CHANGE_EVENT)) {
1102 if (mlx4_is_master(dev->dev))
1103 /* already in work queue from mlx4_ib_event queueing
1104 * mlx4_handle_port_mgmt_change_event, which calls
1105 * this procedure. Therefore, call sl2vl_update directly.
1106 */
1107 mlx4_ib_sl2vl_update(dev, port_num);
1108 else
1109 mlx4_sched_ib_sl2vl_update_work(dev, port_num);
1110 }
1111 mlx4_ib_dispatch_event(dev, port_num, IB_EVENT_CLIENT_REREGISTER);
1112 }
1113
propagate_pkey_ev(struct mlx4_ib_dev * dev,int port_num,struct mlx4_eqe * eqe)1114 static void propagate_pkey_ev(struct mlx4_ib_dev *dev, int port_num,
1115 struct mlx4_eqe *eqe)
1116 {
1117 __propagate_pkey_ev(dev, port_num, GET_BLK_PTR_FROM_EQE(eqe),
1118 GET_MASK_FROM_EQE(eqe));
1119 }
1120
handle_slaves_guid_change(struct mlx4_ib_dev * dev,u8 port_num,u32 guid_tbl_blk_num,u32 change_bitmap)1121 static void handle_slaves_guid_change(struct mlx4_ib_dev *dev, u8 port_num,
1122 u32 guid_tbl_blk_num, u32 change_bitmap)
1123 {
1124 struct ib_smp *in_mad = NULL;
1125 struct ib_smp *out_mad = NULL;
1126 u16 i;
1127
1128 if (!mlx4_is_mfunc(dev->dev) || !mlx4_is_master(dev->dev))
1129 return;
1130
1131 in_mad = kmalloc(sizeof *in_mad, GFP_KERNEL);
1132 out_mad = kmalloc(sizeof *out_mad, GFP_KERNEL);
1133 if (!in_mad || !out_mad) {
1134 mlx4_ib_warn(&dev->ib_dev, "failed to allocate memory for guid info mads\n");
1135 goto out;
1136 }
1137
1138 guid_tbl_blk_num *= 4;
1139
1140 for (i = 0; i < 4; i++) {
1141 if (change_bitmap && (!((change_bitmap >> (8 * i)) & 0xff)))
1142 continue;
1143 memset(in_mad, 0, sizeof *in_mad);
1144 memset(out_mad, 0, sizeof *out_mad);
1145
1146 in_mad->base_version = 1;
1147 in_mad->mgmt_class = IB_MGMT_CLASS_SUBN_LID_ROUTED;
1148 in_mad->class_version = 1;
1149 in_mad->method = IB_MGMT_METHOD_GET;
1150 in_mad->attr_id = IB_SMP_ATTR_GUID_INFO;
1151 in_mad->attr_mod = cpu_to_be32(guid_tbl_blk_num + i);
1152
1153 if (mlx4_MAD_IFC(dev,
1154 MLX4_MAD_IFC_IGNORE_KEYS | MLX4_MAD_IFC_NET_VIEW,
1155 port_num, NULL, NULL, in_mad, out_mad)) {
1156 mlx4_ib_warn(&dev->ib_dev, "Failed in get GUID INFO MAD_IFC\n");
1157 goto out;
1158 }
1159
1160 mlx4_ib_update_cache_on_guid_change(dev, guid_tbl_blk_num + i,
1161 port_num,
1162 (u8 *)(&((struct ib_smp *)out_mad)->data));
1163 mlx4_ib_notify_slaves_on_guid_change(dev, guid_tbl_blk_num + i,
1164 port_num,
1165 (u8 *)(&((struct ib_smp *)out_mad)->data));
1166 }
1167
1168 out:
1169 kfree(in_mad);
1170 kfree(out_mad);
1171 return;
1172 }
1173
handle_port_mgmt_change_event(struct work_struct * work)1174 void handle_port_mgmt_change_event(struct work_struct *work)
1175 {
1176 struct ib_event_work *ew = container_of(work, struct ib_event_work, work);
1177 struct mlx4_ib_dev *dev = ew->ib_dev;
1178 struct mlx4_eqe *eqe = &(ew->ib_eqe);
1179 u8 port = eqe->event.port_mgmt_change.port;
1180 u32 changed_attr;
1181 u32 tbl_block;
1182 u32 change_bitmap;
1183
1184 switch (eqe->subtype) {
1185 case MLX4_DEV_PMC_SUBTYPE_PORT_INFO:
1186 changed_attr = be32_to_cpu(eqe->event.port_mgmt_change.params.port_info.changed_attr);
1187
1188 /* Update the SM ah - This should be done before handling
1189 the other changed attributes so that MADs can be sent to the SM */
1190 if (changed_attr & MSTR_SM_CHANGE_MASK) {
1191 u16 lid = be16_to_cpu(eqe->event.port_mgmt_change.params.port_info.mstr_sm_lid);
1192 u8 sl = eqe->event.port_mgmt_change.params.port_info.mstr_sm_sl & 0xf;
1193 update_sm_ah(dev, port, lid, sl);
1194 }
1195
1196 /* Check if it is a lid change event */
1197 if (changed_attr & MLX4_EQ_PORT_INFO_LID_CHANGE_MASK)
1198 handle_lid_change_event(dev, port);
1199
1200 /* Generate GUID changed event */
1201 if (changed_attr & MLX4_EQ_PORT_INFO_GID_PFX_CHANGE_MASK) {
1202 if (mlx4_is_master(dev->dev)) {
1203 union ib_gid gid;
1204 int err = 0;
1205
1206 if (!eqe->event.port_mgmt_change.params.port_info.gid_prefix)
1207 err = __mlx4_ib_query_gid(&dev->ib_dev, port, 0, &gid, 1);
1208 else
1209 gid.global.subnet_prefix =
1210 eqe->event.port_mgmt_change.params.port_info.gid_prefix;
1211 if (err) {
1212 pr_warn("Could not change QP1 subnet prefix for port %d: query_gid error (%d)\n",
1213 port, err);
1214 } else {
1215 pr_debug("Changing QP1 subnet prefix for port %d. old=0x%llx. new=0x%llx\n",
1216 port,
1217 (long long)atomic64_read(&dev->sriov.demux[port - 1].subnet_prefix),
1218 (long long)be64_to_cpu(gid.global.subnet_prefix));
1219 atomic64_set(&dev->sriov.demux[port - 1].subnet_prefix,
1220 be64_to_cpu(gid.global.subnet_prefix));
1221 }
1222 }
1223 mlx4_ib_dispatch_event(dev, port, IB_EVENT_GID_CHANGE);
1224 /*if master, notify all slaves*/
1225 if (mlx4_is_master(dev->dev))
1226 mlx4_gen_slaves_port_mgt_ev(dev->dev, port,
1227 MLX4_EQ_PORT_INFO_GID_PFX_CHANGE_MASK);
1228 }
1229
1230 if (changed_attr & MLX4_EQ_PORT_INFO_CLIENT_REREG_MASK)
1231 handle_client_rereg_event(dev, port);
1232 break;
1233
1234 case MLX4_DEV_PMC_SUBTYPE_PKEY_TABLE:
1235 mlx4_ib_dispatch_event(dev, port, IB_EVENT_PKEY_CHANGE);
1236 if (mlx4_is_master(dev->dev) && !dev->sriov.is_going_down)
1237 propagate_pkey_ev(dev, port, eqe);
1238 break;
1239 case MLX4_DEV_PMC_SUBTYPE_GUID_INFO:
1240 /* paravirtualized master's guid is guid 0 -- does not change */
1241 if (!mlx4_is_master(dev->dev))
1242 mlx4_ib_dispatch_event(dev, port, IB_EVENT_GID_CHANGE);
1243 /*if master, notify relevant slaves*/
1244 else if (!dev->sriov.is_going_down) {
1245 tbl_block = GET_BLK_PTR_FROM_EQE(eqe);
1246 change_bitmap = GET_MASK_FROM_EQE(eqe);
1247 handle_slaves_guid_change(dev, port, tbl_block, change_bitmap);
1248 }
1249 break;
1250
1251 case MLX4_DEV_PMC_SUBTYPE_SL_TO_VL_MAP:
1252 /* cache sl to vl mapping changes for use in
1253 * filling QP1 LRH VL field when sending packets
1254 */
1255 if (!mlx4_is_slave(dev->dev)) {
1256 union sl2vl_tbl_to_u64 sl2vl64;
1257 int jj;
1258
1259 for (jj = 0; jj < 8; jj++) {
1260 sl2vl64.sl8[jj] =
1261 eqe->event.port_mgmt_change.params.sl2vl_tbl_change_info.sl2vl_table[jj];
1262 pr_debug("sl2vl[%d] = %02x\n", jj, sl2vl64.sl8[jj]);
1263 }
1264 atomic64_set(&dev->sl2vl[port - 1], sl2vl64.sl64);
1265 }
1266 break;
1267 default:
1268 pr_warn("Unsupported subtype 0x%x for "
1269 "Port Management Change event\n", eqe->subtype);
1270 }
1271
1272 kfree(ew);
1273 }
1274
mlx4_ib_dispatch_event(struct mlx4_ib_dev * dev,u8 port_num,enum ib_event_type type)1275 void mlx4_ib_dispatch_event(struct mlx4_ib_dev *dev, u8 port_num,
1276 enum ib_event_type type)
1277 {
1278 struct ib_event event;
1279
1280 event.device = &dev->ib_dev;
1281 event.element.port_num = port_num;
1282 event.event = type;
1283
1284 ib_dispatch_event(&event);
1285 }
1286
mlx4_ib_tunnel_comp_handler(struct ib_cq * cq,void * arg)1287 static void mlx4_ib_tunnel_comp_handler(struct ib_cq *cq, void *arg)
1288 {
1289 unsigned long flags;
1290 struct mlx4_ib_demux_pv_ctx *ctx = cq->cq_context;
1291 struct mlx4_ib_dev *dev = to_mdev(ctx->ib_dev);
1292 spin_lock_irqsave(&dev->sriov.going_down_lock, flags);
1293 if (!dev->sriov.is_going_down && ctx->state == DEMUX_PV_STATE_ACTIVE)
1294 queue_work(ctx->wq, &ctx->work);
1295 spin_unlock_irqrestore(&dev->sriov.going_down_lock, flags);
1296 }
1297
mlx4_ib_post_pv_qp_buf(struct mlx4_ib_demux_pv_ctx * ctx,struct mlx4_ib_demux_pv_qp * tun_qp,int index)1298 static int mlx4_ib_post_pv_qp_buf(struct mlx4_ib_demux_pv_ctx *ctx,
1299 struct mlx4_ib_demux_pv_qp *tun_qp,
1300 int index)
1301 {
1302 struct ib_sge sg_list;
1303 struct ib_recv_wr recv_wr;
1304 const struct ib_recv_wr *bad_recv_wr;
1305 int size;
1306
1307 size = (tun_qp->qp->qp_type == IB_QPT_UD) ?
1308 sizeof (struct mlx4_tunnel_mad) : sizeof (struct mlx4_mad_rcv_buf);
1309
1310 sg_list.addr = tun_qp->ring[index].map;
1311 sg_list.length = size;
1312 sg_list.lkey = ctx->pd->local_dma_lkey;
1313
1314 recv_wr.next = NULL;
1315 recv_wr.sg_list = &sg_list;
1316 recv_wr.num_sge = 1;
1317 recv_wr.wr_id = (u64) index | MLX4_TUN_WRID_RECV |
1318 MLX4_TUN_SET_WRID_QPN(tun_qp->proxy_qpt);
1319 ib_dma_sync_single_for_device(ctx->ib_dev, tun_qp->ring[index].map,
1320 size, DMA_FROM_DEVICE);
1321 return ib_post_recv(tun_qp->qp, &recv_wr, &bad_recv_wr);
1322 }
1323
mlx4_ib_multiplex_sa_handler(struct ib_device * ibdev,int port,int slave,struct ib_sa_mad * sa_mad)1324 static int mlx4_ib_multiplex_sa_handler(struct ib_device *ibdev, int port,
1325 int slave, struct ib_sa_mad *sa_mad)
1326 {
1327 int ret = 0;
1328
1329 /* dispatch to different sa handlers */
1330 switch (be16_to_cpu(sa_mad->mad_hdr.attr_id)) {
1331 case IB_SA_ATTR_MC_MEMBER_REC:
1332 ret = mlx4_ib_mcg_multiplex_handler(ibdev, port, slave, sa_mad);
1333 break;
1334 default:
1335 break;
1336 }
1337 return ret;
1338 }
1339
is_proxy_qp0(struct mlx4_ib_dev * dev,int qpn,int slave)1340 static int is_proxy_qp0(struct mlx4_ib_dev *dev, int qpn, int slave)
1341 {
1342 int proxy_start = dev->dev->phys_caps.base_proxy_sqpn + 8 * slave;
1343
1344 return (qpn >= proxy_start && qpn <= proxy_start + 1);
1345 }
1346
1347
mlx4_ib_send_to_wire(struct mlx4_ib_dev * dev,int slave,u8 port,enum ib_qp_type dest_qpt,u16 pkey_index,u32 remote_qpn,u32 qkey,struct rdma_ah_attr * attr,u8 * s_mac,u16 vlan_id,struct ib_mad * mad)1348 int mlx4_ib_send_to_wire(struct mlx4_ib_dev *dev, int slave, u8 port,
1349 enum ib_qp_type dest_qpt, u16 pkey_index,
1350 u32 remote_qpn, u32 qkey, struct rdma_ah_attr *attr,
1351 u8 *s_mac, u16 vlan_id, struct ib_mad *mad)
1352 {
1353 struct ib_sge list;
1354 struct ib_ud_wr wr;
1355 const struct ib_send_wr *bad_wr;
1356 struct mlx4_ib_demux_pv_ctx *sqp_ctx;
1357 struct mlx4_ib_demux_pv_qp *sqp;
1358 struct mlx4_mad_snd_buf *sqp_mad;
1359 struct ib_ah *ah;
1360 struct ib_qp *send_qp = NULL;
1361 unsigned wire_tx_ix = 0;
1362 u16 wire_pkey_ix;
1363 int src_qpnum;
1364 int ret;
1365
1366 sqp_ctx = dev->sriov.sqps[port-1];
1367
1368 /* check if proxy qp created */
1369 if (!sqp_ctx || sqp_ctx->state != DEMUX_PV_STATE_ACTIVE)
1370 return -EAGAIN;
1371
1372 if (dest_qpt == IB_QPT_SMI) {
1373 src_qpnum = 0;
1374 sqp = &sqp_ctx->qp[0];
1375 wire_pkey_ix = dev->pkeys.virt2phys_pkey[slave][port - 1][0];
1376 } else {
1377 src_qpnum = 1;
1378 sqp = &sqp_ctx->qp[1];
1379 wire_pkey_ix = dev->pkeys.virt2phys_pkey[slave][port - 1][pkey_index];
1380 }
1381
1382 send_qp = sqp->qp;
1383
1384 ah = rdma_zalloc_drv_obj(sqp_ctx->pd->device, ib_ah);
1385 if (!ah)
1386 return -ENOMEM;
1387
1388 ah->device = sqp_ctx->pd->device;
1389 ah->pd = sqp_ctx->pd;
1390
1391 /* create ah */
1392 ret = mlx4_ib_create_ah_slave(ah, attr,
1393 attr->grh.sgid_index,
1394 s_mac, vlan_id);
1395 if (ret)
1396 goto out;
1397
1398 spin_lock(&sqp->tx_lock);
1399 if (sqp->tx_ix_head - sqp->tx_ix_tail >=
1400 (MLX4_NUM_TUNNEL_BUFS - 1))
1401 ret = -EAGAIN;
1402 else
1403 wire_tx_ix = (++sqp->tx_ix_head) & (MLX4_NUM_TUNNEL_BUFS - 1);
1404 spin_unlock(&sqp->tx_lock);
1405 if (ret)
1406 goto out;
1407
1408 sqp_mad = (struct mlx4_mad_snd_buf *) (sqp->tx_ring[wire_tx_ix].buf.addr);
1409 kfree(sqp->tx_ring[wire_tx_ix].ah);
1410 sqp->tx_ring[wire_tx_ix].ah = ah;
1411 ib_dma_sync_single_for_cpu(&dev->ib_dev,
1412 sqp->tx_ring[wire_tx_ix].buf.map,
1413 sizeof (struct mlx4_mad_snd_buf),
1414 DMA_TO_DEVICE);
1415
1416 memcpy(&sqp_mad->payload, mad, sizeof *mad);
1417
1418 ib_dma_sync_single_for_device(&dev->ib_dev,
1419 sqp->tx_ring[wire_tx_ix].buf.map,
1420 sizeof (struct mlx4_mad_snd_buf),
1421 DMA_TO_DEVICE);
1422
1423 list.addr = sqp->tx_ring[wire_tx_ix].buf.map;
1424 list.length = sizeof (struct mlx4_mad_snd_buf);
1425 list.lkey = sqp_ctx->pd->local_dma_lkey;
1426
1427 wr.ah = ah;
1428 wr.port_num = port;
1429 wr.pkey_index = wire_pkey_ix;
1430 wr.remote_qkey = qkey;
1431 wr.remote_qpn = remote_qpn;
1432 wr.wr.next = NULL;
1433 wr.wr.wr_id = ((u64) wire_tx_ix) | MLX4_TUN_SET_WRID_QPN(src_qpnum);
1434 wr.wr.sg_list = &list;
1435 wr.wr.num_sge = 1;
1436 wr.wr.opcode = IB_WR_SEND;
1437 wr.wr.send_flags = IB_SEND_SIGNALED;
1438
1439 ret = ib_post_send(send_qp, &wr.wr, &bad_wr);
1440 if (!ret)
1441 return 0;
1442
1443 spin_lock(&sqp->tx_lock);
1444 sqp->tx_ix_tail++;
1445 spin_unlock(&sqp->tx_lock);
1446 sqp->tx_ring[wire_tx_ix].ah = NULL;
1447 out:
1448 kfree(ah);
1449 return ret;
1450 }
1451
get_slave_base_gid_ix(struct mlx4_ib_dev * dev,int slave,int port)1452 static int get_slave_base_gid_ix(struct mlx4_ib_dev *dev, int slave, int port)
1453 {
1454 if (rdma_port_get_link_layer(&dev->ib_dev, port) == IB_LINK_LAYER_INFINIBAND)
1455 return slave;
1456 return mlx4_get_base_gid_ix(dev->dev, slave, port);
1457 }
1458
fill_in_real_sgid_index(struct mlx4_ib_dev * dev,int slave,int port,struct rdma_ah_attr * ah_attr)1459 static void fill_in_real_sgid_index(struct mlx4_ib_dev *dev, int slave, int port,
1460 struct rdma_ah_attr *ah_attr)
1461 {
1462 struct ib_global_route *grh = rdma_ah_retrieve_grh(ah_attr);
1463 if (rdma_port_get_link_layer(&dev->ib_dev, port) == IB_LINK_LAYER_INFINIBAND)
1464 grh->sgid_index = slave;
1465 else
1466 grh->sgid_index += get_slave_base_gid_ix(dev, slave, port);
1467 }
1468
mlx4_ib_multiplex_mad(struct mlx4_ib_demux_pv_ctx * ctx,struct ib_wc * wc)1469 static void mlx4_ib_multiplex_mad(struct mlx4_ib_demux_pv_ctx *ctx, struct ib_wc *wc)
1470 {
1471 struct mlx4_ib_dev *dev = to_mdev(ctx->ib_dev);
1472 struct mlx4_ib_demux_pv_qp *tun_qp = &ctx->qp[MLX4_TUN_WRID_QPN(wc->wr_id)];
1473 int wr_ix = wc->wr_id & (MLX4_NUM_TUNNEL_BUFS - 1);
1474 struct mlx4_tunnel_mad *tunnel = tun_qp->ring[wr_ix].addr;
1475 struct mlx4_ib_ah ah;
1476 struct rdma_ah_attr ah_attr;
1477 u8 *slave_id;
1478 int slave;
1479 int port;
1480 u16 vlan_id;
1481 u8 qos;
1482 u8 *dmac;
1483
1484 /* Get slave that sent this packet */
1485 if (wc->src_qp < dev->dev->phys_caps.base_proxy_sqpn ||
1486 wc->src_qp >= dev->dev->phys_caps.base_proxy_sqpn + 8 * MLX4_MFUNC_MAX ||
1487 (wc->src_qp & 0x1) != ctx->port - 1 ||
1488 wc->src_qp & 0x4) {
1489 mlx4_ib_warn(ctx->ib_dev, "can't multiplex bad sqp:%d\n", wc->src_qp);
1490 return;
1491 }
1492 slave = ((wc->src_qp & ~0x7) - dev->dev->phys_caps.base_proxy_sqpn) / 8;
1493 if (slave != ctx->slave) {
1494 mlx4_ib_warn(ctx->ib_dev, "can't multiplex bad sqp:%d: "
1495 "belongs to another slave\n", wc->src_qp);
1496 return;
1497 }
1498
1499 /* Map transaction ID */
1500 ib_dma_sync_single_for_cpu(ctx->ib_dev, tun_qp->ring[wr_ix].map,
1501 sizeof (struct mlx4_tunnel_mad),
1502 DMA_FROM_DEVICE);
1503 switch (tunnel->mad.mad_hdr.method) {
1504 case IB_MGMT_METHOD_SET:
1505 case IB_MGMT_METHOD_GET:
1506 case IB_MGMT_METHOD_REPORT:
1507 case IB_SA_METHOD_GET_TABLE:
1508 case IB_SA_METHOD_DELETE:
1509 case IB_SA_METHOD_GET_MULTI:
1510 case IB_SA_METHOD_GET_TRACE_TBL:
1511 slave_id = (u8 *) &tunnel->mad.mad_hdr.tid;
1512 if (*slave_id) {
1513 mlx4_ib_warn(ctx->ib_dev, "egress mad has non-null tid msb:%d "
1514 "class:%d slave:%d\n", *slave_id,
1515 tunnel->mad.mad_hdr.mgmt_class, slave);
1516 return;
1517 } else
1518 *slave_id = slave;
1519 default:
1520 /* nothing */;
1521 }
1522
1523 /* Class-specific handling */
1524 switch (tunnel->mad.mad_hdr.mgmt_class) {
1525 case IB_MGMT_CLASS_SUBN_LID_ROUTED:
1526 case IB_MGMT_CLASS_SUBN_DIRECTED_ROUTE:
1527 if (slave != mlx4_master_func_num(dev->dev) &&
1528 !mlx4_vf_smi_enabled(dev->dev, slave, ctx->port))
1529 return;
1530 break;
1531 case IB_MGMT_CLASS_SUBN_ADM:
1532 if (mlx4_ib_multiplex_sa_handler(ctx->ib_dev, ctx->port, slave,
1533 (struct ib_sa_mad *) &tunnel->mad))
1534 return;
1535 break;
1536 case IB_MGMT_CLASS_CM:
1537 if (mlx4_ib_multiplex_cm_handler(ctx->ib_dev, ctx->port, slave,
1538 (struct ib_mad *) &tunnel->mad))
1539 return;
1540 break;
1541 case IB_MGMT_CLASS_DEVICE_MGMT:
1542 if (tunnel->mad.mad_hdr.method != IB_MGMT_METHOD_GET &&
1543 tunnel->mad.mad_hdr.method != IB_MGMT_METHOD_SET)
1544 return;
1545 break;
1546 default:
1547 /* Drop unsupported classes for slaves in tunnel mode */
1548 if (slave != mlx4_master_func_num(dev->dev)) {
1549 mlx4_ib_warn(ctx->ib_dev, "dropping unsupported egress mad from class:%d "
1550 "for slave:%d\n", tunnel->mad.mad_hdr.mgmt_class, slave);
1551 return;
1552 }
1553 }
1554
1555 /* We are using standard ib_core services to send the mad, so generate a
1556 * stadard address handle by decoding the tunnelled mlx4_ah fields */
1557 memcpy(&ah.av, &tunnel->hdr.av, sizeof (struct mlx4_av));
1558 ah.ibah.device = ctx->ib_dev;
1559
1560 port = be32_to_cpu(ah.av.ib.port_pd) >> 24;
1561 port = mlx4_slave_convert_port(dev->dev, slave, port);
1562 if (port < 0)
1563 return;
1564 ah.av.ib.port_pd = cpu_to_be32(port << 24 | (be32_to_cpu(ah.av.ib.port_pd) & 0xffffff));
1565 ah.ibah.type = rdma_ah_find_type(&dev->ib_dev, port);
1566
1567 mlx4_ib_query_ah(&ah.ibah, &ah_attr);
1568 if (rdma_ah_get_ah_flags(&ah_attr) & IB_AH_GRH)
1569 fill_in_real_sgid_index(dev, slave, ctx->port, &ah_attr);
1570
1571 dmac = rdma_ah_retrieve_dmac(&ah_attr);
1572 if (dmac)
1573 memcpy(dmac, tunnel->hdr.mac, ETH_ALEN);
1574 vlan_id = be16_to_cpu(tunnel->hdr.vlan);
1575 /* if slave have default vlan use it */
1576 if (mlx4_get_slave_default_vlan(dev->dev, ctx->port, slave,
1577 &vlan_id, &qos))
1578 rdma_ah_set_sl(&ah_attr, qos);
1579
1580 mlx4_ib_send_to_wire(dev, slave, ctx->port,
1581 is_proxy_qp0(dev, wc->src_qp, slave) ?
1582 IB_QPT_SMI : IB_QPT_GSI,
1583 be16_to_cpu(tunnel->hdr.pkey_index),
1584 be32_to_cpu(tunnel->hdr.remote_qpn),
1585 be32_to_cpu(tunnel->hdr.qkey),
1586 &ah_attr, wc->smac, vlan_id, &tunnel->mad);
1587 }
1588
mlx4_ib_alloc_pv_bufs(struct mlx4_ib_demux_pv_ctx * ctx,enum ib_qp_type qp_type,int is_tun)1589 static int mlx4_ib_alloc_pv_bufs(struct mlx4_ib_demux_pv_ctx *ctx,
1590 enum ib_qp_type qp_type, int is_tun)
1591 {
1592 int i;
1593 struct mlx4_ib_demux_pv_qp *tun_qp;
1594 int rx_buf_size, tx_buf_size;
1595
1596 if (qp_type > IB_QPT_GSI)
1597 return -EINVAL;
1598
1599 tun_qp = &ctx->qp[qp_type];
1600
1601 tun_qp->ring = kcalloc(MLX4_NUM_TUNNEL_BUFS,
1602 sizeof(struct mlx4_ib_buf),
1603 GFP_KERNEL);
1604 if (!tun_qp->ring)
1605 return -ENOMEM;
1606
1607 tun_qp->tx_ring = kcalloc(MLX4_NUM_TUNNEL_BUFS,
1608 sizeof (struct mlx4_ib_tun_tx_buf),
1609 GFP_KERNEL);
1610 if (!tun_qp->tx_ring) {
1611 kfree(tun_qp->ring);
1612 tun_qp->ring = NULL;
1613 return -ENOMEM;
1614 }
1615
1616 if (is_tun) {
1617 rx_buf_size = sizeof (struct mlx4_tunnel_mad);
1618 tx_buf_size = sizeof (struct mlx4_rcv_tunnel_mad);
1619 } else {
1620 rx_buf_size = sizeof (struct mlx4_mad_rcv_buf);
1621 tx_buf_size = sizeof (struct mlx4_mad_snd_buf);
1622 }
1623
1624 for (i = 0; i < MLX4_NUM_TUNNEL_BUFS; i++) {
1625 tun_qp->ring[i].addr = kmalloc(rx_buf_size, GFP_KERNEL);
1626 if (!tun_qp->ring[i].addr)
1627 goto err;
1628 tun_qp->ring[i].map = ib_dma_map_single(ctx->ib_dev,
1629 tun_qp->ring[i].addr,
1630 rx_buf_size,
1631 DMA_FROM_DEVICE);
1632 if (ib_dma_mapping_error(ctx->ib_dev, tun_qp->ring[i].map)) {
1633 kfree(tun_qp->ring[i].addr);
1634 goto err;
1635 }
1636 }
1637
1638 for (i = 0; i < MLX4_NUM_TUNNEL_BUFS; i++) {
1639 tun_qp->tx_ring[i].buf.addr =
1640 kmalloc(tx_buf_size, GFP_KERNEL);
1641 if (!tun_qp->tx_ring[i].buf.addr)
1642 goto tx_err;
1643 tun_qp->tx_ring[i].buf.map =
1644 ib_dma_map_single(ctx->ib_dev,
1645 tun_qp->tx_ring[i].buf.addr,
1646 tx_buf_size,
1647 DMA_TO_DEVICE);
1648 if (ib_dma_mapping_error(ctx->ib_dev,
1649 tun_qp->tx_ring[i].buf.map)) {
1650 kfree(tun_qp->tx_ring[i].buf.addr);
1651 goto tx_err;
1652 }
1653 tun_qp->tx_ring[i].ah = NULL;
1654 }
1655 spin_lock_init(&tun_qp->tx_lock);
1656 tun_qp->tx_ix_head = 0;
1657 tun_qp->tx_ix_tail = 0;
1658 tun_qp->proxy_qpt = qp_type;
1659
1660 return 0;
1661
1662 tx_err:
1663 while (i > 0) {
1664 --i;
1665 ib_dma_unmap_single(ctx->ib_dev, tun_qp->tx_ring[i].buf.map,
1666 tx_buf_size, DMA_TO_DEVICE);
1667 kfree(tun_qp->tx_ring[i].buf.addr);
1668 }
1669 kfree(tun_qp->tx_ring);
1670 tun_qp->tx_ring = NULL;
1671 i = MLX4_NUM_TUNNEL_BUFS;
1672 err:
1673 while (i > 0) {
1674 --i;
1675 ib_dma_unmap_single(ctx->ib_dev, tun_qp->ring[i].map,
1676 rx_buf_size, DMA_FROM_DEVICE);
1677 kfree(tun_qp->ring[i].addr);
1678 }
1679 kfree(tun_qp->ring);
1680 tun_qp->ring = NULL;
1681 return -ENOMEM;
1682 }
1683
mlx4_ib_free_pv_qp_bufs(struct mlx4_ib_demux_pv_ctx * ctx,enum ib_qp_type qp_type,int is_tun)1684 static void mlx4_ib_free_pv_qp_bufs(struct mlx4_ib_demux_pv_ctx *ctx,
1685 enum ib_qp_type qp_type, int is_tun)
1686 {
1687 int i;
1688 struct mlx4_ib_demux_pv_qp *tun_qp;
1689 int rx_buf_size, tx_buf_size;
1690
1691 if (qp_type > IB_QPT_GSI)
1692 return;
1693
1694 tun_qp = &ctx->qp[qp_type];
1695 if (is_tun) {
1696 rx_buf_size = sizeof (struct mlx4_tunnel_mad);
1697 tx_buf_size = sizeof (struct mlx4_rcv_tunnel_mad);
1698 } else {
1699 rx_buf_size = sizeof (struct mlx4_mad_rcv_buf);
1700 tx_buf_size = sizeof (struct mlx4_mad_snd_buf);
1701 }
1702
1703
1704 for (i = 0; i < MLX4_NUM_TUNNEL_BUFS; i++) {
1705 ib_dma_unmap_single(ctx->ib_dev, tun_qp->ring[i].map,
1706 rx_buf_size, DMA_FROM_DEVICE);
1707 kfree(tun_qp->ring[i].addr);
1708 }
1709
1710 for (i = 0; i < MLX4_NUM_TUNNEL_BUFS; i++) {
1711 ib_dma_unmap_single(ctx->ib_dev, tun_qp->tx_ring[i].buf.map,
1712 tx_buf_size, DMA_TO_DEVICE);
1713 kfree(tun_qp->tx_ring[i].buf.addr);
1714 if (tun_qp->tx_ring[i].ah)
1715 rdma_destroy_ah(tun_qp->tx_ring[i].ah, 0);
1716 }
1717 kfree(tun_qp->tx_ring);
1718 kfree(tun_qp->ring);
1719 }
1720
mlx4_ib_tunnel_comp_worker(struct work_struct * work)1721 static void mlx4_ib_tunnel_comp_worker(struct work_struct *work)
1722 {
1723 struct mlx4_ib_demux_pv_ctx *ctx;
1724 struct mlx4_ib_demux_pv_qp *tun_qp;
1725 struct ib_wc wc;
1726 int ret;
1727 ctx = container_of(work, struct mlx4_ib_demux_pv_ctx, work);
1728 ib_req_notify_cq(ctx->cq, IB_CQ_NEXT_COMP);
1729
1730 while (ib_poll_cq(ctx->cq, 1, &wc) == 1) {
1731 tun_qp = &ctx->qp[MLX4_TUN_WRID_QPN(wc.wr_id)];
1732 if (wc.status == IB_WC_SUCCESS) {
1733 switch (wc.opcode) {
1734 case IB_WC_RECV:
1735 mlx4_ib_multiplex_mad(ctx, &wc);
1736 ret = mlx4_ib_post_pv_qp_buf(ctx, tun_qp,
1737 wc.wr_id &
1738 (MLX4_NUM_TUNNEL_BUFS - 1));
1739 if (ret)
1740 pr_err("Failed reposting tunnel "
1741 "buf:%lld\n", (unsigned long long)wc.wr_id);
1742 break;
1743 case IB_WC_SEND:
1744 pr_debug("received tunnel send completion:"
1745 "wrid=0x%llx, status=0x%x\n",
1746 (unsigned long long)wc.wr_id, wc.status);
1747 rdma_destroy_ah(tun_qp->tx_ring[wc.wr_id &
1748 (MLX4_NUM_TUNNEL_BUFS - 1)].ah, 0);
1749 tun_qp->tx_ring[wc.wr_id & (MLX4_NUM_TUNNEL_BUFS - 1)].ah
1750 = NULL;
1751 spin_lock(&tun_qp->tx_lock);
1752 tun_qp->tx_ix_tail++;
1753 spin_unlock(&tun_qp->tx_lock);
1754
1755 break;
1756 default:
1757 break;
1758 }
1759 } else {
1760 pr_debug("mlx4_ib: completion error in tunnel: %d."
1761 " status = %d, wrid = 0x%llx\n",
1762 ctx->slave, wc.status, (unsigned long long)wc.wr_id);
1763 if (!MLX4_TUN_IS_RECV(wc.wr_id)) {
1764 rdma_destroy_ah(tun_qp->tx_ring[wc.wr_id &
1765 (MLX4_NUM_TUNNEL_BUFS - 1)].ah, 0);
1766 tun_qp->tx_ring[wc.wr_id & (MLX4_NUM_TUNNEL_BUFS - 1)].ah
1767 = NULL;
1768 spin_lock(&tun_qp->tx_lock);
1769 tun_qp->tx_ix_tail++;
1770 spin_unlock(&tun_qp->tx_lock);
1771 }
1772 }
1773 }
1774 }
1775
pv_qp_event_handler(struct ib_event * event,void * qp_context)1776 static void pv_qp_event_handler(struct ib_event *event, void *qp_context)
1777 {
1778 struct mlx4_ib_demux_pv_ctx *sqp = qp_context;
1779
1780 /* It's worse than that! He's dead, Jim! */
1781 pr_err("Fatal error (%d) on a MAD QP on port %d\n",
1782 event->event, sqp->port);
1783 }
1784
create_pv_sqp(struct mlx4_ib_demux_pv_ctx * ctx,enum ib_qp_type qp_type,int create_tun)1785 static int create_pv_sqp(struct mlx4_ib_demux_pv_ctx *ctx,
1786 enum ib_qp_type qp_type, int create_tun)
1787 {
1788 int i, ret;
1789 struct mlx4_ib_demux_pv_qp *tun_qp;
1790 struct mlx4_ib_qp_tunnel_init_attr qp_init_attr;
1791 struct ib_qp_attr attr;
1792 int qp_attr_mask_INIT;
1793
1794 if (qp_type > IB_QPT_GSI)
1795 return -EINVAL;
1796
1797 tun_qp = &ctx->qp[qp_type];
1798
1799 memset(&qp_init_attr, 0, sizeof qp_init_attr);
1800 qp_init_attr.init_attr.send_cq = ctx->cq;
1801 qp_init_attr.init_attr.recv_cq = ctx->cq;
1802 qp_init_attr.init_attr.sq_sig_type = IB_SIGNAL_ALL_WR;
1803 qp_init_attr.init_attr.cap.max_send_wr = MLX4_NUM_TUNNEL_BUFS;
1804 qp_init_attr.init_attr.cap.max_recv_wr = MLX4_NUM_TUNNEL_BUFS;
1805 qp_init_attr.init_attr.cap.max_send_sge = 1;
1806 qp_init_attr.init_attr.cap.max_recv_sge = 1;
1807 if (create_tun) {
1808 qp_init_attr.init_attr.qp_type = IB_QPT_UD;
1809 qp_init_attr.init_attr.create_flags =
1810 (enum ib_qp_create_flags)MLX4_IB_SRIOV_TUNNEL_QP;
1811 qp_init_attr.port = ctx->port;
1812 qp_init_attr.slave = ctx->slave;
1813 qp_init_attr.proxy_qp_type = qp_type;
1814 qp_attr_mask_INIT = IB_QP_STATE | IB_QP_PKEY_INDEX |
1815 IB_QP_QKEY | IB_QP_PORT;
1816 } else {
1817 qp_init_attr.init_attr.qp_type = qp_type;
1818 qp_init_attr.init_attr.create_flags =
1819 (enum ib_qp_create_flags)MLX4_IB_SRIOV_SQP;
1820 qp_attr_mask_INIT = IB_QP_STATE | IB_QP_PKEY_INDEX | IB_QP_QKEY;
1821 }
1822 qp_init_attr.init_attr.port_num = ctx->port;
1823 qp_init_attr.init_attr.qp_context = ctx;
1824 qp_init_attr.init_attr.event_handler = pv_qp_event_handler;
1825 tun_qp->qp = ib_create_qp(ctx->pd, &qp_init_attr.init_attr);
1826 if (IS_ERR(tun_qp->qp)) {
1827 ret = PTR_ERR(tun_qp->qp);
1828 tun_qp->qp = NULL;
1829 pr_err("Couldn't create %s QP (%d)\n",
1830 create_tun ? "tunnel" : "special", ret);
1831 return ret;
1832 }
1833
1834 memset(&attr, 0, sizeof attr);
1835 attr.qp_state = IB_QPS_INIT;
1836 ret = 0;
1837 if (create_tun)
1838 ret = find_slave_port_pkey_ix(to_mdev(ctx->ib_dev), ctx->slave,
1839 ctx->port, IB_DEFAULT_PKEY_FULL,
1840 &attr.pkey_index);
1841 if (ret || !create_tun)
1842 attr.pkey_index =
1843 to_mdev(ctx->ib_dev)->pkeys.virt2phys_pkey[ctx->slave][ctx->port - 1][0];
1844 attr.qkey = IB_QP1_QKEY;
1845 attr.port_num = ctx->port;
1846 ret = ib_modify_qp(tun_qp->qp, &attr, qp_attr_mask_INIT);
1847 if (ret) {
1848 pr_err("Couldn't change %s qp state to INIT (%d)\n",
1849 create_tun ? "tunnel" : "special", ret);
1850 goto err_qp;
1851 }
1852 attr.qp_state = IB_QPS_RTR;
1853 ret = ib_modify_qp(tun_qp->qp, &attr, IB_QP_STATE);
1854 if (ret) {
1855 pr_err("Couldn't change %s qp state to RTR (%d)\n",
1856 create_tun ? "tunnel" : "special", ret);
1857 goto err_qp;
1858 }
1859 attr.qp_state = IB_QPS_RTS;
1860 attr.sq_psn = 0;
1861 ret = ib_modify_qp(tun_qp->qp, &attr, IB_QP_STATE | IB_QP_SQ_PSN);
1862 if (ret) {
1863 pr_err("Couldn't change %s qp state to RTS (%d)\n",
1864 create_tun ? "tunnel" : "special", ret);
1865 goto err_qp;
1866 }
1867
1868 for (i = 0; i < MLX4_NUM_TUNNEL_BUFS; i++) {
1869 ret = mlx4_ib_post_pv_qp_buf(ctx, tun_qp, i);
1870 if (ret) {
1871 pr_err(" mlx4_ib_post_pv_buf error"
1872 " (err = %d, i = %d)\n", ret, i);
1873 goto err_qp;
1874 }
1875 }
1876 return 0;
1877
1878 err_qp:
1879 ib_destroy_qp(tun_qp->qp);
1880 tun_qp->qp = NULL;
1881 return ret;
1882 }
1883
1884 /*
1885 * IB MAD completion callback for real SQPs
1886 */
mlx4_ib_sqp_comp_worker(struct work_struct * work)1887 static void mlx4_ib_sqp_comp_worker(struct work_struct *work)
1888 {
1889 struct mlx4_ib_demux_pv_ctx *ctx;
1890 struct mlx4_ib_demux_pv_qp *sqp;
1891 struct ib_wc wc;
1892 struct ib_grh *grh;
1893 struct ib_mad *mad;
1894
1895 ctx = container_of(work, struct mlx4_ib_demux_pv_ctx, work);
1896 ib_req_notify_cq(ctx->cq, IB_CQ_NEXT_COMP);
1897
1898 while (mlx4_ib_poll_cq(ctx->cq, 1, &wc) == 1) {
1899 sqp = &ctx->qp[MLX4_TUN_WRID_QPN(wc.wr_id)];
1900 if (wc.status == IB_WC_SUCCESS) {
1901 switch (wc.opcode) {
1902 case IB_WC_SEND:
1903 kfree(sqp->tx_ring[wc.wr_id &
1904 (MLX4_NUM_TUNNEL_BUFS - 1)].ah);
1905 sqp->tx_ring[wc.wr_id & (MLX4_NUM_TUNNEL_BUFS - 1)].ah
1906 = NULL;
1907 spin_lock(&sqp->tx_lock);
1908 sqp->tx_ix_tail++;
1909 spin_unlock(&sqp->tx_lock);
1910 break;
1911 case IB_WC_RECV:
1912 mad = (struct ib_mad *) &(((struct mlx4_mad_rcv_buf *)
1913 (sqp->ring[wc.wr_id &
1914 (MLX4_NUM_TUNNEL_BUFS - 1)].addr))->payload);
1915 grh = &(((struct mlx4_mad_rcv_buf *)
1916 (sqp->ring[wc.wr_id &
1917 (MLX4_NUM_TUNNEL_BUFS - 1)].addr))->grh);
1918 mlx4_ib_demux_mad(ctx->ib_dev, ctx->port, &wc, grh, mad);
1919 if (mlx4_ib_post_pv_qp_buf(ctx, sqp, wc.wr_id &
1920 (MLX4_NUM_TUNNEL_BUFS - 1)))
1921 pr_err("Failed reposting SQP "
1922 "buf:%lld\n", (unsigned long long)wc.wr_id);
1923 break;
1924 default:
1925 BUG_ON(1);
1926 break;
1927 }
1928 } else {
1929 pr_debug("mlx4_ib: completion error in tunnel: %d."
1930 " status = %d, wrid = 0x%llx\n",
1931 ctx->slave, wc.status, (unsigned long long)wc.wr_id);
1932 if (!MLX4_TUN_IS_RECV(wc.wr_id)) {
1933 kfree(sqp->tx_ring[wc.wr_id &
1934 (MLX4_NUM_TUNNEL_BUFS - 1)].ah);
1935 sqp->tx_ring[wc.wr_id & (MLX4_NUM_TUNNEL_BUFS - 1)].ah
1936 = NULL;
1937 spin_lock(&sqp->tx_lock);
1938 sqp->tx_ix_tail++;
1939 spin_unlock(&sqp->tx_lock);
1940 }
1941 }
1942 }
1943 }
1944
alloc_pv_object(struct mlx4_ib_dev * dev,int slave,int port,struct mlx4_ib_demux_pv_ctx ** ret_ctx)1945 static int alloc_pv_object(struct mlx4_ib_dev *dev, int slave, int port,
1946 struct mlx4_ib_demux_pv_ctx **ret_ctx)
1947 {
1948 struct mlx4_ib_demux_pv_ctx *ctx;
1949
1950 *ret_ctx = NULL;
1951 ctx = kzalloc(sizeof (struct mlx4_ib_demux_pv_ctx), GFP_KERNEL);
1952 if (!ctx) {
1953 pr_err("failed allocating pv resource context "
1954 "for port %d, slave %d\n", port, slave);
1955 return -ENOMEM;
1956 }
1957
1958 ctx->ib_dev = &dev->ib_dev;
1959 ctx->port = port;
1960 ctx->slave = slave;
1961 *ret_ctx = ctx;
1962 return 0;
1963 }
1964
free_pv_object(struct mlx4_ib_dev * dev,int slave,int port)1965 static void free_pv_object(struct mlx4_ib_dev *dev, int slave, int port)
1966 {
1967 if (dev->sriov.demux[port - 1].tun[slave]) {
1968 kfree(dev->sriov.demux[port - 1].tun[slave]);
1969 dev->sriov.demux[port - 1].tun[slave] = NULL;
1970 }
1971 }
1972
create_pv_resources(struct ib_device * ibdev,int slave,int port,int create_tun,struct mlx4_ib_demux_pv_ctx * ctx)1973 static int create_pv_resources(struct ib_device *ibdev, int slave, int port,
1974 int create_tun, struct mlx4_ib_demux_pv_ctx *ctx)
1975 {
1976 int ret, cq_size;
1977 struct ib_cq_init_attr cq_attr = {};
1978
1979 if (ctx->state != DEMUX_PV_STATE_DOWN)
1980 return -EEXIST;
1981
1982 ctx->state = DEMUX_PV_STATE_STARTING;
1983 /* have QP0 only if link layer is IB */
1984 if (rdma_port_get_link_layer(ibdev, ctx->port) ==
1985 IB_LINK_LAYER_INFINIBAND)
1986 ctx->has_smi = 1;
1987
1988 if (ctx->has_smi) {
1989 ret = mlx4_ib_alloc_pv_bufs(ctx, IB_QPT_SMI, create_tun);
1990 if (ret) {
1991 pr_err("Failed allocating qp0 tunnel bufs (%d)\n", ret);
1992 goto err_out;
1993 }
1994 }
1995
1996 ret = mlx4_ib_alloc_pv_bufs(ctx, IB_QPT_GSI, create_tun);
1997 if (ret) {
1998 pr_err("Failed allocating qp1 tunnel bufs (%d)\n", ret);
1999 goto err_out_qp0;
2000 }
2001
2002 cq_size = 2 * MLX4_NUM_TUNNEL_BUFS;
2003 if (ctx->has_smi)
2004 cq_size *= 2;
2005
2006 cq_attr.cqe = cq_size;
2007 ctx->cq = ib_create_cq(ctx->ib_dev, mlx4_ib_tunnel_comp_handler,
2008 NULL, ctx, &cq_attr);
2009 if (IS_ERR(ctx->cq)) {
2010 ret = PTR_ERR(ctx->cq);
2011 pr_err("Couldn't create tunnel CQ (%d)\n", ret);
2012 goto err_buf;
2013 }
2014
2015 ctx->pd = ib_alloc_pd(ctx->ib_dev, 0);
2016 if (IS_ERR(ctx->pd)) {
2017 ret = PTR_ERR(ctx->pd);
2018 pr_err("Couldn't create tunnel PD (%d)\n", ret);
2019 goto err_cq;
2020 }
2021
2022 if (ctx->has_smi) {
2023 ret = create_pv_sqp(ctx, IB_QPT_SMI, create_tun);
2024 if (ret) {
2025 pr_err("Couldn't create %s QP0 (%d)\n",
2026 create_tun ? "tunnel for" : "", ret);
2027 goto err_pd;
2028 }
2029 }
2030
2031 ret = create_pv_sqp(ctx, IB_QPT_GSI, create_tun);
2032 if (ret) {
2033 pr_err("Couldn't create %s QP1 (%d)\n",
2034 create_tun ? "tunnel for" : "", ret);
2035 goto err_qp0;
2036 }
2037
2038 if (create_tun)
2039 INIT_WORK(&ctx->work, mlx4_ib_tunnel_comp_worker);
2040 else
2041 INIT_WORK(&ctx->work, mlx4_ib_sqp_comp_worker);
2042
2043 ctx->wq = to_mdev(ibdev)->sriov.demux[port - 1].wq;
2044
2045 ret = ib_req_notify_cq(ctx->cq, IB_CQ_NEXT_COMP);
2046 if (ret) {
2047 pr_err("Couldn't arm tunnel cq (%d)\n", ret);
2048 goto err_wq;
2049 }
2050 ctx->state = DEMUX_PV_STATE_ACTIVE;
2051 return 0;
2052
2053 err_wq:
2054 ctx->wq = NULL;
2055 ib_destroy_qp(ctx->qp[1].qp);
2056 ctx->qp[1].qp = NULL;
2057
2058
2059 err_qp0:
2060 if (ctx->has_smi)
2061 ib_destroy_qp(ctx->qp[0].qp);
2062 ctx->qp[0].qp = NULL;
2063
2064 err_pd:
2065 ib_dealloc_pd(ctx->pd);
2066 ctx->pd = NULL;
2067
2068 err_cq:
2069 ib_destroy_cq(ctx->cq);
2070 ctx->cq = NULL;
2071
2072 err_buf:
2073 mlx4_ib_free_pv_qp_bufs(ctx, IB_QPT_GSI, create_tun);
2074
2075 err_out_qp0:
2076 if (ctx->has_smi)
2077 mlx4_ib_free_pv_qp_bufs(ctx, IB_QPT_SMI, create_tun);
2078 err_out:
2079 ctx->state = DEMUX_PV_STATE_DOWN;
2080 return ret;
2081 }
2082
destroy_pv_resources(struct mlx4_ib_dev * dev,int slave,int port,struct mlx4_ib_demux_pv_ctx * ctx,int flush)2083 static void destroy_pv_resources(struct mlx4_ib_dev *dev, int slave, int port,
2084 struct mlx4_ib_demux_pv_ctx *ctx, int flush)
2085 {
2086 if (!ctx)
2087 return;
2088 if (ctx->state > DEMUX_PV_STATE_DOWN) {
2089 ctx->state = DEMUX_PV_STATE_DOWNING;
2090 if (flush)
2091 flush_workqueue(ctx->wq);
2092 if (ctx->has_smi) {
2093 ib_destroy_qp(ctx->qp[0].qp);
2094 ctx->qp[0].qp = NULL;
2095 mlx4_ib_free_pv_qp_bufs(ctx, IB_QPT_SMI, 1);
2096 }
2097 ib_destroy_qp(ctx->qp[1].qp);
2098 ctx->qp[1].qp = NULL;
2099 mlx4_ib_free_pv_qp_bufs(ctx, IB_QPT_GSI, 1);
2100 ib_dealloc_pd(ctx->pd);
2101 ctx->pd = NULL;
2102 ib_destroy_cq(ctx->cq);
2103 ctx->cq = NULL;
2104 ctx->state = DEMUX_PV_STATE_DOWN;
2105 }
2106 }
2107
mlx4_ib_tunnels_update(struct mlx4_ib_dev * dev,int slave,int port,int do_init)2108 static int mlx4_ib_tunnels_update(struct mlx4_ib_dev *dev, int slave,
2109 int port, int do_init)
2110 {
2111 int ret = 0;
2112
2113 if (!do_init) {
2114 clean_vf_mcast(&dev->sriov.demux[port - 1], slave);
2115 /* for master, destroy real sqp resources */
2116 if (slave == mlx4_master_func_num(dev->dev))
2117 destroy_pv_resources(dev, slave, port,
2118 dev->sriov.sqps[port - 1], 1);
2119 /* destroy the tunnel qp resources */
2120 destroy_pv_resources(dev, slave, port,
2121 dev->sriov.demux[port - 1].tun[slave], 1);
2122 return 0;
2123 }
2124
2125 /* create the tunnel qp resources */
2126 ret = create_pv_resources(&dev->ib_dev, slave, port, 1,
2127 dev->sriov.demux[port - 1].tun[slave]);
2128
2129 /* for master, create the real sqp resources */
2130 if (!ret && slave == mlx4_master_func_num(dev->dev))
2131 ret = create_pv_resources(&dev->ib_dev, slave, port, 0,
2132 dev->sriov.sqps[port - 1]);
2133 return ret;
2134 }
2135
mlx4_ib_tunnels_update_work(struct work_struct * work)2136 void mlx4_ib_tunnels_update_work(struct work_struct *work)
2137 {
2138 struct mlx4_ib_demux_work *dmxw;
2139
2140 dmxw = container_of(work, struct mlx4_ib_demux_work, work);
2141 mlx4_ib_tunnels_update(dmxw->dev, dmxw->slave, (int) dmxw->port,
2142 dmxw->do_init);
2143 kfree(dmxw);
2144 return;
2145 }
2146
mlx4_ib_alloc_demux_ctx(struct mlx4_ib_dev * dev,struct mlx4_ib_demux_ctx * ctx,int port)2147 static int mlx4_ib_alloc_demux_ctx(struct mlx4_ib_dev *dev,
2148 struct mlx4_ib_demux_ctx *ctx,
2149 int port)
2150 {
2151 char name[12];
2152 int ret = 0;
2153 int i;
2154
2155 ctx->tun = kcalloc(dev->dev->caps.sqp_demux,
2156 sizeof (struct mlx4_ib_demux_pv_ctx *), GFP_KERNEL);
2157 if (!ctx->tun)
2158 return -ENOMEM;
2159
2160 ctx->dev = dev;
2161 ctx->port = port;
2162 ctx->ib_dev = &dev->ib_dev;
2163
2164 for (i = 0;
2165 i < min(dev->dev->caps.sqp_demux,
2166 (u16)(dev->dev->persist->num_vfs + 1));
2167 i++) {
2168 struct mlx4_active_ports actv_ports =
2169 mlx4_get_active_ports(dev->dev, i);
2170
2171 if (!test_bit(port - 1, actv_ports.ports))
2172 continue;
2173
2174 ret = alloc_pv_object(dev, i, port, &ctx->tun[i]);
2175 if (ret) {
2176 ret = -ENOMEM;
2177 goto err_mcg;
2178 }
2179 }
2180
2181 ret = mlx4_ib_mcg_port_init(ctx);
2182 if (ret) {
2183 pr_err("Failed initializing mcg para-virt (%d)\n", ret);
2184 goto err_mcg;
2185 }
2186
2187 snprintf(name, sizeof name, "mlx4_ibt%d", port);
2188 ctx->wq = alloc_ordered_workqueue(name, WQ_MEM_RECLAIM);
2189 if (!ctx->wq) {
2190 pr_err("Failed to create tunnelling WQ for port %d\n", port);
2191 ret = -ENOMEM;
2192 goto err_wq;
2193 }
2194
2195 snprintf(name, sizeof name, "mlx4_ibud%d", port);
2196 ctx->ud_wq = alloc_ordered_workqueue(name, WQ_MEM_RECLAIM);
2197 if (!ctx->ud_wq) {
2198 pr_err("Failed to create up/down WQ for port %d\n", port);
2199 ret = -ENOMEM;
2200 goto err_udwq;
2201 }
2202
2203 return 0;
2204
2205 err_udwq:
2206 destroy_workqueue(ctx->wq);
2207 ctx->wq = NULL;
2208
2209 err_wq:
2210 mlx4_ib_mcg_port_cleanup(ctx, 1);
2211 err_mcg:
2212 for (i = 0; i < dev->dev->caps.sqp_demux; i++)
2213 free_pv_object(dev, i, port);
2214 kfree(ctx->tun);
2215 ctx->tun = NULL;
2216 return ret;
2217 }
2218
mlx4_ib_free_sqp_ctx(struct mlx4_ib_demux_pv_ctx * sqp_ctx)2219 static void mlx4_ib_free_sqp_ctx(struct mlx4_ib_demux_pv_ctx *sqp_ctx)
2220 {
2221 if (sqp_ctx->state > DEMUX_PV_STATE_DOWN) {
2222 sqp_ctx->state = DEMUX_PV_STATE_DOWNING;
2223 flush_workqueue(sqp_ctx->wq);
2224 if (sqp_ctx->has_smi) {
2225 ib_destroy_qp(sqp_ctx->qp[0].qp);
2226 sqp_ctx->qp[0].qp = NULL;
2227 mlx4_ib_free_pv_qp_bufs(sqp_ctx, IB_QPT_SMI, 0);
2228 }
2229 ib_destroy_qp(sqp_ctx->qp[1].qp);
2230 sqp_ctx->qp[1].qp = NULL;
2231 mlx4_ib_free_pv_qp_bufs(sqp_ctx, IB_QPT_GSI, 0);
2232 ib_dealloc_pd(sqp_ctx->pd);
2233 sqp_ctx->pd = NULL;
2234 ib_destroy_cq(sqp_ctx->cq);
2235 sqp_ctx->cq = NULL;
2236 sqp_ctx->state = DEMUX_PV_STATE_DOWN;
2237 }
2238 }
2239
mlx4_ib_free_demux_ctx(struct mlx4_ib_demux_ctx * ctx)2240 static void mlx4_ib_free_demux_ctx(struct mlx4_ib_demux_ctx *ctx)
2241 {
2242 int i;
2243 if (ctx) {
2244 struct mlx4_ib_dev *dev = to_mdev(ctx->ib_dev);
2245 mlx4_ib_mcg_port_cleanup(ctx, 1);
2246 for (i = 0; i < dev->dev->caps.sqp_demux; i++) {
2247 if (!ctx->tun[i])
2248 continue;
2249 if (ctx->tun[i]->state > DEMUX_PV_STATE_DOWN)
2250 ctx->tun[i]->state = DEMUX_PV_STATE_DOWNING;
2251 }
2252 flush_workqueue(ctx->wq);
2253 for (i = 0; i < dev->dev->caps.sqp_demux; i++) {
2254 destroy_pv_resources(dev, i, ctx->port, ctx->tun[i], 0);
2255 free_pv_object(dev, i, ctx->port);
2256 }
2257 kfree(ctx->tun);
2258 destroy_workqueue(ctx->ud_wq);
2259 destroy_workqueue(ctx->wq);
2260 }
2261 }
2262
mlx4_ib_master_tunnels(struct mlx4_ib_dev * dev,int do_init)2263 static void mlx4_ib_master_tunnels(struct mlx4_ib_dev *dev, int do_init)
2264 {
2265 int i;
2266
2267 if (!mlx4_is_master(dev->dev))
2268 return;
2269 /* initialize or tear down tunnel QPs for the master */
2270 for (i = 0; i < dev->dev->caps.num_ports; i++)
2271 mlx4_ib_tunnels_update(dev, mlx4_master_func_num(dev->dev), i + 1, do_init);
2272 return;
2273 }
2274
mlx4_ib_init_sriov(struct mlx4_ib_dev * dev)2275 int mlx4_ib_init_sriov(struct mlx4_ib_dev *dev)
2276 {
2277 int i = 0;
2278 int err;
2279
2280 if (!mlx4_is_mfunc(dev->dev))
2281 return 0;
2282
2283 dev->sriov.is_going_down = 0;
2284 spin_lock_init(&dev->sriov.going_down_lock);
2285 mlx4_ib_cm_paravirt_init(dev);
2286
2287 mlx4_ib_warn(&dev->ib_dev, "multi-function enabled\n");
2288
2289 if (mlx4_is_slave(dev->dev)) {
2290 mlx4_ib_warn(&dev->ib_dev, "operating in qp1 tunnel mode\n");
2291 return 0;
2292 }
2293
2294 for (i = 0; i < dev->dev->caps.sqp_demux; i++) {
2295 if (i == mlx4_master_func_num(dev->dev))
2296 mlx4_put_slave_node_guid(dev->dev, i, dev->ib_dev.node_guid);
2297 else
2298 mlx4_put_slave_node_guid(dev->dev, i, mlx4_ib_gen_node_guid());
2299 }
2300
2301 err = mlx4_ib_init_alias_guid_service(dev);
2302 if (err) {
2303 mlx4_ib_warn(&dev->ib_dev, "Failed init alias guid process.\n");
2304 goto paravirt_err;
2305 }
2306 err = mlx4_ib_device_register_sysfs(dev);
2307 if (err) {
2308 mlx4_ib_warn(&dev->ib_dev, "Failed to register sysfs\n");
2309 goto sysfs_err;
2310 }
2311
2312 mlx4_ib_warn(&dev->ib_dev, "initializing demux service for %d qp1 clients\n",
2313 dev->dev->caps.sqp_demux);
2314 for (i = 0; i < dev->num_ports; i++) {
2315 union ib_gid gid;
2316 err = __mlx4_ib_query_gid(&dev->ib_dev, i + 1, 0, &gid, 1);
2317 if (err)
2318 goto demux_err;
2319 dev->sriov.demux[i].guid_cache[0] = gid.global.interface_id;
2320 atomic64_set(&dev->sriov.demux[i].subnet_prefix,
2321 be64_to_cpu(gid.global.subnet_prefix));
2322 err = alloc_pv_object(dev, mlx4_master_func_num(dev->dev), i + 1,
2323 &dev->sriov.sqps[i]);
2324 if (err)
2325 goto demux_err;
2326 err = mlx4_ib_alloc_demux_ctx(dev, &dev->sriov.demux[i], i + 1);
2327 if (err)
2328 goto free_pv;
2329 }
2330 mlx4_ib_master_tunnels(dev, 1);
2331 return 0;
2332
2333 free_pv:
2334 free_pv_object(dev, mlx4_master_func_num(dev->dev), i + 1);
2335 demux_err:
2336 while (--i >= 0) {
2337 free_pv_object(dev, mlx4_master_func_num(dev->dev), i + 1);
2338 mlx4_ib_free_demux_ctx(&dev->sriov.demux[i]);
2339 }
2340 mlx4_ib_device_unregister_sysfs(dev);
2341
2342 sysfs_err:
2343 mlx4_ib_destroy_alias_guid_service(dev);
2344
2345 paravirt_err:
2346 mlx4_ib_cm_paravirt_clean(dev, -1);
2347
2348 return err;
2349 }
2350
mlx4_ib_close_sriov(struct mlx4_ib_dev * dev)2351 void mlx4_ib_close_sriov(struct mlx4_ib_dev *dev)
2352 {
2353 int i;
2354 unsigned long flags;
2355
2356 if (!mlx4_is_mfunc(dev->dev))
2357 return;
2358
2359 spin_lock_irqsave(&dev->sriov.going_down_lock, flags);
2360 dev->sriov.is_going_down = 1;
2361 spin_unlock_irqrestore(&dev->sriov.going_down_lock, flags);
2362 if (mlx4_is_master(dev->dev)) {
2363 for (i = 0; i < dev->num_ports; i++) {
2364 flush_workqueue(dev->sriov.demux[i].ud_wq);
2365 mlx4_ib_free_sqp_ctx(dev->sriov.sqps[i]);
2366 kfree(dev->sriov.sqps[i]);
2367 dev->sriov.sqps[i] = NULL;
2368 mlx4_ib_free_demux_ctx(&dev->sriov.demux[i]);
2369 }
2370
2371 mlx4_ib_cm_paravirt_clean(dev, -1);
2372 mlx4_ib_destroy_alias_guid_service(dev);
2373 mlx4_ib_device_unregister_sysfs(dev);
2374 }
2375 }
2376