1 // SPDX-License-Identifier: MIT
2 /*
3 * Copyright 2024 Advanced Micro Devices, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 */
24
25 #include <linux/devcoredump.h>
26 #include <linux/utsname.h>
27 #include <drm/drm_exec.h>
28 #include "amdgpu_dev_coredump.h"
29 #include "atom.h"
30
31 #ifndef CONFIG_DEV_COREDUMP
amdgpu_coredump(struct amdgpu_device * adev,bool skip_vram_check,bool vram_lost,struct amdgpu_job * job)32 void amdgpu_coredump(struct amdgpu_device *adev, bool skip_vram_check,
33 bool vram_lost, struct amdgpu_job *job)
34 {
35 }
amdgpu_coredump_init(struct amdgpu_device * adev)36 void amdgpu_coredump_init(struct amdgpu_device *adev)
37 {
38 }
amdgpu_coredump_fini(struct amdgpu_device * adev)39 void amdgpu_coredump_fini(struct amdgpu_device *adev)
40 {
41 }
42 #else
43
44 #define AMDGPU_CORE_DUMP_SIZE_MAX (256 * 1024 * 1024)
45
46 const char *hw_ip_names[MAX_HWIP] = {
47 [GC_HWIP] = "GC",
48 [HDP_HWIP] = "HDP",
49 [SDMA0_HWIP] = "SDMA0",
50 [SDMA1_HWIP] = "SDMA1",
51 [SDMA2_HWIP] = "SDMA2",
52 [SDMA3_HWIP] = "SDMA3",
53 [SDMA4_HWIP] = "SDMA4",
54 [SDMA5_HWIP] = "SDMA5",
55 [SDMA6_HWIP] = "SDMA6",
56 [SDMA7_HWIP] = "SDMA7",
57 [LSDMA_HWIP] = "LSDMA",
58 [MMHUB_HWIP] = "MMHUB",
59 [ATHUB_HWIP] = "ATHUB",
60 [NBIO_HWIP] = "NBIO",
61 [MP0_HWIP] = "MP0",
62 [MP1_HWIP] = "MP1",
63 [UVD_HWIP] = "UVD/JPEG/VCN",
64 [VCN1_HWIP] = "VCN1",
65 [VCE_HWIP] = "VCE",
66 [VPE_HWIP] = "VPE",
67 [UMSCH_HWIP] = "UMSCH",
68 [DF_HWIP] = "DF",
69 [DCE_HWIP] = "DCE",
70 [OSSSYS_HWIP] = "OSSSYS",
71 [SMUIO_HWIP] = "SMUIO",
72 [PWR_HWIP] = "PWR",
73 [NBIF_HWIP] = "NBIF",
74 [THM_HWIP] = "THM",
75 [CLK_HWIP] = "CLK",
76 [UMC_HWIP] = "UMC",
77 [RSMU_HWIP] = "RSMU",
78 [XGMI_HWIP] = "XGMI",
79 [DCI_HWIP] = "DCI",
80 [PCIE_HWIP] = "PCIE",
81 };
82
amdgpu_devcoredump_fw_info(struct amdgpu_device * adev,struct drm_printer * p)83 static void amdgpu_devcoredump_fw_info(struct amdgpu_device *adev,
84 struct drm_printer *p)
85 {
86 uint32_t version;
87 uint32_t feature;
88 uint8_t smu_program, smu_major, smu_minor, smu_debug;
89 struct atom_context *ctx = adev->mode_info.atom_context;
90
91 drm_printf(p, "VCE feature version: %u, fw version: 0x%08x\n",
92 adev->vce.fb_version, adev->vce.fw_version);
93 drm_printf(p, "UVD feature version: %u, fw version: 0x%08x\n", 0,
94 adev->uvd.fw_version);
95 drm_printf(p, "GMC feature version: %u, fw version: 0x%08x\n", 0,
96 adev->gmc.fw_version);
97 drm_printf(p, "ME feature version: %u, fw version: 0x%08x\n",
98 adev->gfx.me_feature_version, adev->gfx.me_fw_version);
99 drm_printf(p, "PFP feature version: %u, fw version: 0x%08x\n",
100 adev->gfx.pfp_feature_version, adev->gfx.pfp_fw_version);
101 drm_printf(p, "CE feature version: %u, fw version: 0x%08x\n",
102 adev->gfx.ce_feature_version, adev->gfx.ce_fw_version);
103 drm_printf(p, "RLC feature version: %u, fw version: 0x%08x\n",
104 adev->gfx.rlc_feature_version, adev->gfx.rlc_fw_version);
105
106 drm_printf(p, "RLC SRLC feature version: %u, fw version: 0x%08x\n",
107 adev->gfx.rlc_srlc_feature_version,
108 adev->gfx.rlc_srlc_fw_version);
109 drm_printf(p, "RLC SRLG feature version: %u, fw version: 0x%08x\n",
110 adev->gfx.rlc_srlg_feature_version,
111 adev->gfx.rlc_srlg_fw_version);
112 drm_printf(p, "RLC SRLS feature version: %u, fw version: 0x%08x\n",
113 adev->gfx.rlc_srls_feature_version,
114 adev->gfx.rlc_srls_fw_version);
115 drm_printf(p, "RLCP feature version: %u, fw version: 0x%08x\n",
116 adev->gfx.rlcp_ucode_feature_version,
117 adev->gfx.rlcp_ucode_version);
118 drm_printf(p, "RLCV feature version: %u, fw version: 0x%08x\n",
119 adev->gfx.rlcv_ucode_feature_version,
120 adev->gfx.rlcv_ucode_version);
121 drm_printf(p, "MEC feature version: %u, fw version: 0x%08x\n",
122 adev->gfx.mec_feature_version, adev->gfx.mec_fw_version);
123
124 if (adev->gfx.mec2_fw)
125 drm_printf(p, "MEC2 feature version: %u, fw version: 0x%08x\n",
126 adev->gfx.mec2_feature_version,
127 adev->gfx.mec2_fw_version);
128
129 drm_printf(p, "IMU feature version: %u, fw version: 0x%08x\n", 0,
130 adev->gfx.imu_fw_version);
131 drm_printf(p, "PSP SOS feature version: %u, fw version: 0x%08x\n",
132 adev->psp.sos.feature_version, adev->psp.sos.fw_version);
133 drm_printf(p, "PSP ASD feature version: %u, fw version: 0x%08x\n",
134 adev->psp.asd_context.bin_desc.feature_version,
135 adev->psp.asd_context.bin_desc.fw_version);
136
137 drm_printf(p, "TA XGMI feature version: 0x%08x, fw version: 0x%08x\n",
138 adev->psp.xgmi_context.context.bin_desc.feature_version,
139 adev->psp.xgmi_context.context.bin_desc.fw_version);
140 drm_printf(p, "TA RAS feature version: 0x%08x, fw version: 0x%08x\n",
141 adev->psp.ras_context.context.bin_desc.feature_version,
142 adev->psp.ras_context.context.bin_desc.fw_version);
143 drm_printf(p, "TA HDCP feature version: 0x%08x, fw version: 0x%08x\n",
144 adev->psp.hdcp_context.context.bin_desc.feature_version,
145 adev->psp.hdcp_context.context.bin_desc.fw_version);
146 drm_printf(p, "TA DTM feature version: 0x%08x, fw version: 0x%08x\n",
147 adev->psp.dtm_context.context.bin_desc.feature_version,
148 adev->psp.dtm_context.context.bin_desc.fw_version);
149 drm_printf(p, "TA RAP feature version: 0x%08x, fw version: 0x%08x\n",
150 adev->psp.rap_context.context.bin_desc.feature_version,
151 adev->psp.rap_context.context.bin_desc.fw_version);
152 drm_printf(p,
153 "TA SECURE DISPLAY feature version: 0x%08x, fw version: 0x%08x\n",
154 adev->psp.securedisplay_context.context.bin_desc.feature_version,
155 adev->psp.securedisplay_context.context.bin_desc.fw_version);
156
157 /* SMC firmware */
158 version = adev->pm.fw_version;
159
160 smu_program = (version >> 24) & 0xff;
161 smu_major = (version >> 16) & 0xff;
162 smu_minor = (version >> 8) & 0xff;
163 smu_debug = (version >> 0) & 0xff;
164 drm_printf(p,
165 "SMC feature version: %u, program: %d, fw version: 0x%08x (%d.%d.%d)\n",
166 0, smu_program, version, smu_major, smu_minor, smu_debug);
167
168 /* SDMA firmware */
169 for (int i = 0; i < adev->sdma.num_instances; i++) {
170 drm_printf(p,
171 "SDMA%d feature version: %u, firmware version: 0x%08x\n",
172 i, adev->sdma.instance[i].feature_version,
173 adev->sdma.instance[i].fw_version);
174 }
175
176 drm_printf(p, "VCN feature version: %u, fw version: 0x%08x\n", 0,
177 adev->vcn.fw_version);
178 drm_printf(p, "DMCU feature version: %u, fw version: 0x%08x\n", 0,
179 adev->dm.dmcu_fw_version);
180 drm_printf(p, "DMCUB feature version: %u, fw version: 0x%08x\n", 0,
181 adev->dm.dmcub_fw_version);
182 drm_printf(p, "PSP TOC feature version: %u, fw version: 0x%08x\n",
183 adev->psp.toc.feature_version, adev->psp.toc.fw_version);
184
185 version = adev->mes.kiq_version & AMDGPU_MES_VERSION_MASK;
186 feature = (adev->mes.kiq_version & AMDGPU_MES_FEAT_VERSION_MASK) >>
187 AMDGPU_MES_FEAT_VERSION_SHIFT;
188 drm_printf(p, "MES_KIQ feature version: %u, fw version: 0x%08x\n",
189 feature, version);
190
191 version = adev->mes.sched_version & AMDGPU_MES_VERSION_MASK;
192 feature = (adev->mes.sched_version & AMDGPU_MES_FEAT_VERSION_MASK) >>
193 AMDGPU_MES_FEAT_VERSION_SHIFT;
194 drm_printf(p, "MES feature version: %u, fw version: 0x%08x\n", feature,
195 version);
196
197 drm_printf(p, "VPE feature version: %u, fw version: 0x%08x\n",
198 adev->vpe.feature_version, adev->vpe.fw_version);
199
200 if (adev->bios) {
201 drm_printf(p, "\nVBIOS Information\n");
202 drm_printf(p, "vbios name : %s\n", ctx->name);
203 drm_printf(p, "vbios pn : %s\n", ctx->vbios_pn);
204 drm_printf(p, "vbios version : %d\n", ctx->version);
205 drm_printf(p, "vbios ver_str : %s\n", ctx->vbios_ver_str);
206 drm_printf(p, "vbios date : %s\n", ctx->date);
207 }else {
208 drm_printf(p, "\nVBIOS Information: NA\n");
209 }
210 }
211
212 static void
amdgpu_devcoredump_print_ibs(struct drm_printer * p,struct amdgpu_coredump_info * coredump,bool sizing_pass)213 amdgpu_devcoredump_print_ibs(struct drm_printer *p,
214 struct amdgpu_coredump_info *coredump,
215 bool sizing_pass)
216 {
217 struct amdgpu_device *adev = coredump->adev;
218 struct amdgpu_bo_va_mapping *mapping;
219 struct amdgpu_bo *abo;
220 struct drm_exec exec;
221 struct amdgpu_vm *vm;
222 u32 *ib_content;
223 u64 va_start, offset;
224 u8 *kptr;
225 u32 off;
226 int r;
227
228 /*
229 * On the sizing pass there is no VM to look up and no BO to lock; the
230 * size estimate doesn't depend on whether the IB BOs are reachable.
231 * Just emit the per-IB headers (the content is not written anywhere).
232 */
233 if (sizing_pass) {
234 for (int i = 0; i < coredump->num_ibs; i++) {
235 drm_printf(p, "\nIB #%d 0x%llx %d dw\n", i,
236 coredump->ibs[i].gpu_addr,
237 coredump->ibs[i].ib_size_dw);
238
239 for (int j = 0; j < coredump->ibs[i].ib_size_dw; j++)
240 drm_printf(p, "0xffffffff\n");
241 }
242 return;
243 }
244
245 /*
246 * Lock the VM root PD and every IB BO together in a single drm_exec
247 * ticket. Reserving the IB BOs one by one while the root PD is held
248 * would be a recursive reservation_ww_class_mutex acquire without a
249 * ww_acquire_ctx, which trips lockdep and self-deadlocks for IB BOs
250 * that share their dma_resv with the root PD (always-valid BOs).
251 */
252 drm_exec_init(&exec, DRM_EXEC_IGNORE_DUPLICATES, 1 + coredump->num_ibs);
253 drm_exec_until_all_locked(&exec) {
254 vm = amdgpu_vm_lock_by_pasid(adev, coredump->pasid, &exec);
255 if (!vm)
256 goto unlock;
257
258 for (int i = 0; i < coredump->num_ibs; i++) {
259 u64 pfn = (coredump->ibs[i].gpu_addr &
260 AMDGPU_GMC_HOLE_MASK) / AMDGPU_GPU_PAGE_SIZE;
261
262 mapping = amdgpu_vm_bo_lookup_mapping(vm, pfn);
263 if (!mapping)
264 continue;
265
266 abo = mapping->bo_va->base.bo;
267 r = drm_exec_lock_obj(&exec, &abo->tbo.base);
268 drm_exec_retry_on_contention(&exec);
269 if (r)
270 goto unlock;
271 }
272 }
273
274 for (int i = 0; i < coredump->num_ibs; i++) {
275 bool emit_content = false;
276
277 ib_content = kvmalloc_array(coredump->ibs[i].ib_size_dw, 4,
278 GFP_KERNEL);
279 if (!ib_content)
280 continue;
281
282 va_start = coredump->ibs[i].gpu_addr & AMDGPU_GMC_HOLE_MASK;
283 mapping = amdgpu_vm_bo_lookup_mapping(vm,
284 va_start / AMDGPU_GPU_PAGE_SIZE);
285 if (!mapping)
286 goto output_ib_content;
287
288 abo = mapping->bo_va->base.bo;
289 offset = va_start - mapping->start * AMDGPU_GPU_PAGE_SIZE;
290
291 if (abo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS) {
292 struct amdgpu_res_cursor cursor;
293
294 off = 0;
295
296 if (abo->tbo.resource->mem_type != TTM_PL_VRAM)
297 goto output_ib_content;
298
299 amdgpu_res_first(abo->tbo.resource, offset,
300 coredump->ibs[i].ib_size_dw * 4, &cursor);
301 while (cursor.remaining) {
302 amdgpu_device_mm_access(adev, cursor.start / 4,
303 &ib_content[off], cursor.size / 4,
304 false);
305 off += cursor.size;
306 amdgpu_res_next(&cursor, cursor.size);
307 }
308 emit_content = true;
309 } else {
310 r = ttm_bo_kmap(&abo->tbo, 0, PFN_UP(abo->tbo.base.size),
311 &abo->kmap);
312 if (r)
313 goto output_ib_content;
314
315 kptr = amdgpu_bo_kptr(abo);
316 kptr += offset;
317 memcpy(ib_content, kptr, coredump->ibs[i].ib_size_dw * 4);
318
319 amdgpu_bo_kunmap(abo);
320 emit_content = true;
321 }
322
323 output_ib_content:
324 drm_printf(p, "\nIB #%d 0x%llx %d dw\n", i,
325 coredump->ibs[i].gpu_addr, coredump->ibs[i].ib_size_dw);
326 if (emit_content) {
327 for (int j = 0; j < coredump->ibs[i].ib_size_dw; j++)
328 drm_printf(p, "0x%08x\n", ib_content[j]);
329 }
330 kvfree(ib_content);
331 }
332
333 unlock:
334 drm_exec_fini(&exec);
335 }
336
337 static ssize_t
amdgpu_devcoredump_format(char * buffer,size_t count,struct amdgpu_coredump_info * coredump)338 amdgpu_devcoredump_format(char *buffer, size_t count, struct amdgpu_coredump_info *coredump)
339 {
340 struct drm_printer p;
341 struct drm_print_iterator iter;
342 struct amdgpu_vm_fault_info *fault_info;
343 struct amdgpu_ip_block *ip_block;
344 struct amdgpu_ring *ring;
345 int ver, i, j;
346 u32 ring_idx;
347 bool sizing_pass;
348
349 sizing_pass = buffer == NULL;
350 iter.data = buffer;
351 iter.start = 0;
352 iter.offset = 0;
353 iter.remain = count;
354
355 p = drm_coredump_printer(&iter);
356
357 drm_printf(&p, "**** AMDGPU Device Coredump ****\n");
358 drm_printf(&p, "version: " AMDGPU_COREDUMP_VERSION "\n");
359 drm_printf(&p, "kernel: %s\n", init_utsname()->release);
360 drm_printf(&p, "module: " KBUILD_MODNAME "\n");
361 drm_printf(&p, "time: %ptSp\n", &coredump->reset_time);
362 drm_printf(&p, "pasid: %u\n", coredump->pasid);
363 drm_printf(&p, "vmid: %u\n", coredump->vmid);
364
365 if (coredump->reset_task_info.task.pid)
366 drm_printf(&p, "process_name: %s TGID: %d thread: %s PID: %d\n",
367 coredump->reset_task_info.process_name,
368 coredump->reset_task_info.tgid,
369 coredump->reset_task_info.task.comm,
370 coredump->reset_task_info.task.pid);
371
372 /* SOC Information */
373 drm_printf(&p, "\nSOC Information\n");
374 drm_printf(&p, "SOC Device id: %d\n", coredump->adev->pdev->device);
375 drm_printf(&p, "SOC PCI Revision id: %d\n", coredump->adev->pdev->revision);
376 drm_printf(&p, "SOC Family: %d\n", coredump->adev->family);
377 drm_printf(&p, "SOC Revision id: %d\n", coredump->adev->rev_id);
378 drm_printf(&p, "SOC External Revision id: %d\n", coredump->adev->external_rev_id);
379
380 /* Memory Information */
381 drm_printf(&p, "\nSOC Memory Information\n");
382 drm_printf(&p, "real vram size: %llu\n", coredump->adev->gmc.real_vram_size);
383 drm_printf(&p, "visible vram size: %llu\n", coredump->adev->gmc.visible_vram_size);
384 drm_printf(&p, "gtt size: %llu\n", coredump->adev->mman.gtt_mgr.manager.size);
385
386 /* GDS Config */
387 drm_printf(&p, "\nGDS Config\n");
388 drm_printf(&p, "gds: total size: %d\n", coredump->adev->gds.gds_size);
389 drm_printf(&p, "gds: compute partition size: %d\n", coredump->adev->gds.gds_size);
390 drm_printf(&p, "gds: gws per compute partition: %d\n", coredump->adev->gds.gws_size);
391 drm_printf(&p, "gds: os per compute partition: %d\n", coredump->adev->gds.oa_size);
392
393 /* HWIP Version Information */
394 drm_printf(&p, "\nHW IP Version Information\n");
395 for (int i = 1; i < MAX_HWIP; i++) {
396 for (int j = 0; j < HWIP_MAX_INSTANCE; j++) {
397 ver = coredump->adev->ip_versions[i][j];
398 if (ver)
399 drm_printf(&p, "HWIP: %s[%d][%d]: v%d.%d.%d.%d.%d\n",
400 hw_ip_names[i], i, j,
401 IP_VERSION_MAJ(ver),
402 IP_VERSION_MIN(ver),
403 IP_VERSION_REV(ver),
404 IP_VERSION_VARIANT(ver),
405 IP_VERSION_SUBREV(ver));
406 }
407 }
408
409 amdgpu_discovery_dump(coredump->adev, &p);
410
411 /* IP firmware information */
412 drm_printf(&p, "\nIP Firmwares\n");
413 amdgpu_devcoredump_fw_info(coredump->adev, &p);
414
415 if (coredump->ring) {
416 drm_printf(&p, "\nRing timed out details\n");
417 drm_printf(&p, "IP Type: %d Ring Name: %s\n",
418 coredump->ring->funcs->type,
419 coredump->ring->name);
420 }
421
422 /* Add page fault information */
423 fault_info = &coredump->adev->vm_manager.fault_info;
424 drm_printf(&p, "\n[%s] Page fault observed\n",
425 fault_info->vmhub ? "mmhub" : "gfxhub");
426 drm_printf(&p, "Faulty page starting at address: 0x%016llx\n", fault_info->addr);
427 drm_printf(&p, "Protection fault status register: 0x%x\n\n", fault_info->status);
428
429 /* dump the ip state for each ip */
430 drm_printf(&p, "IP Dump\n");
431 for (int i = 0; i < coredump->adev->num_ip_blocks; i++) {
432 ip_block = &coredump->adev->ip_blocks[i];
433 if (ip_block->version->funcs->print_ip_state) {
434 drm_printf(&p, "IP: %s\n", ip_block->version->funcs->name);
435 ip_block->version->funcs->print_ip_state(ip_block, &p);
436 drm_printf(&p, "\n");
437 }
438 }
439
440 /* Add ring buffer information */
441 drm_printf(&p, "Ring buffer information\n");
442 if (coredump->num_rings) {
443 for (i = 0; i < coredump->num_rings; i++) {
444 ring_idx = coredump->rings[i].ring_index;
445 ring = coredump->adev->rings[ring_idx];
446
447 drm_printf(&p, "ring name: %s\n", ring->name);
448 drm_printf(&p, "Rptr: 0x%llx Wptr: 0x%llx RB mask: %x\n",
449 coredump->rings[i].rptr,
450 coredump->rings[i].wptr,
451 ring->buf_mask);
452 drm_printf(&p, "Ring size in dwords: %d\n",
453 ring->ring_size / 4);
454
455 if (!coredump->rings[i].ring_dw) {
456 drm_printf(&p, "Ring contents unavailable\n");
457 continue;
458 }
459
460 drm_printf(&p, "Ring contents\n");
461 drm_printf(&p, "Offset \t Value\n");
462
463 for (j = 0; j < ring->ring_size; j += 4)
464 drm_printf(&p, "0x%x \t 0x%x\n", j,
465 coredump->rings[i].ring_dw[j / 4]);
466 }
467 }
468
469 if (coredump->skip_vram_check)
470 drm_printf(&p, "VRAM lost check is skipped!\n");
471 else if (coredump->reset_vram_lost)
472 drm_printf(&p, "VRAM is lost due to GPU reset!\n");
473
474 if (coredump->num_ibs)
475 amdgpu_devcoredump_print_ibs(&p, coredump, sizing_pass);
476
477 return count - iter.remain;
478 }
479
480 static ssize_t
amdgpu_devcoredump_read(char * buffer,loff_t offset,size_t count,void * data,size_t datalen)481 amdgpu_devcoredump_read(char *buffer, loff_t offset, size_t count,
482 void *data, size_t datalen)
483 {
484 struct amdgpu_coredump_info *coredump = data;
485 ssize_t byte_copied;
486
487 if (!coredump)
488 return -ENODEV;
489
490 if (!coredump->formatted)
491 return -ENODEV;
492
493 if (offset >= coredump->formatted_size)
494 return 0;
495
496 byte_copied = count < coredump->formatted_size - offset ? count :
497 coredump->formatted_size - offset;
498 memcpy(buffer, coredump->formatted + offset, byte_copied);
499
500 return byte_copied;
501 }
502
amdgpu_devcoredump_free(void * data)503 static void amdgpu_devcoredump_free(void *data)
504 {
505 struct amdgpu_coredump_info *coredump = data;
506 u32 i;
507
508 kvfree(coredump->formatted);
509 for (i = 0; i < coredump->num_rings; i++)
510 kvfree(coredump->rings[i].ring_dw);
511 kvfree(coredump->rings);
512 kvfree(data);
513 }
514
amdgpu_devcoredump_deferred_work(struct work_struct * work)515 static void amdgpu_devcoredump_deferred_work(struct work_struct *work)
516 {
517 struct amdgpu_device *adev = container_of(work, typeof(*adev), coredump_work);
518 struct amdgpu_coredump_info *coredump = adev->coredump;
519
520 if (!coredump)
521 goto end;
522
523 /* Do a one-time preparation of the coredump output because
524 * repeatingly calling drm_coredump_printer is very slow.
525 */
526 coredump->formatted_size = amdgpu_devcoredump_format(
527 NULL, AMDGPU_CORE_DUMP_SIZE_MAX, coredump);
528 coredump->formatted = kvzalloc(coredump->formatted_size, GFP_KERNEL);
529 if (!coredump->formatted) {
530 amdgpu_devcoredump_free(coredump);
531 goto end;
532 }
533
534 amdgpu_devcoredump_format(coredump->formatted, coredump->formatted_size, coredump);
535
536 /* If there's an existing coredump for this device, the free function will be
537 * called immediately so coredump might be invalid after the call to dev_coredumpm.
538 */
539 dev_coredumpm(coredump->adev->dev, THIS_MODULE, coredump, 0, GFP_NOWAIT,
540 amdgpu_devcoredump_read, amdgpu_devcoredump_free);
541
542 end:
543 adev->coredump = NULL;
544 }
545
amdgpu_coredump(struct amdgpu_device * adev,bool skip_vram_check,bool vram_lost,struct amdgpu_job * job)546 void amdgpu_coredump(struct amdgpu_device *adev, bool skip_vram_check,
547 bool vram_lost, struct amdgpu_job *job)
548 {
549 struct drm_device *dev = adev_to_drm(adev);
550 struct amdgpu_coredump_info *coredump;
551 size_t size = sizeof(*coredump);
552 struct drm_sched_job *s_job;
553 u64 ring_count;
554 struct amdgpu_ring *ring;
555 int i, idx;
556
557 /* No need to generate a new coredump if there's one in progress already. */
558 if (work_busy(&adev->coredump_work))
559 return;
560
561 if (job && job->pasid)
562 size += sizeof(struct amdgpu_coredump_ib_info) * job->num_ibs;
563
564 coredump = kvzalloc(size, GFP_NOWAIT);
565 if (!coredump)
566 return;
567
568 coredump->skip_vram_check = skip_vram_check;
569 coredump->reset_vram_lost = vram_lost;
570
571 if (job && job->pasid) {
572 struct amdgpu_task_info *ti;
573
574 ti = amdgpu_vm_get_task_info_pasid(adev, job->pasid);
575 if (ti) {
576 coredump->reset_task_info = *ti;
577 amdgpu_vm_put_task_info(ti);
578 }
579 coredump->pasid = job->pasid;
580 coredump->vmid = job->vmid;
581 coredump->num_ibs = job->num_ibs;
582 for (i = 0; i < job->num_ibs; ++i) {
583 coredump->ibs[i].gpu_addr = job->ibs[i].gpu_addr;
584 coredump->ibs[i].ib_size_dw = job->ibs[i].length_dw;
585 }
586 }
587
588 if (job) {
589 s_job = &job->base;
590 coredump->ring = to_amdgpu_ring(s_job->sched);
591 }
592
593 /* Dump ring content if memory allocation succeeds. */
594 ring_count = 0;
595 for (i = 0; i < adev->num_rings; i++) {
596 ring = adev->rings[i];
597
598 /* Only dump rings with unsignalled fences. */
599 if (atomic_read(&ring->fence_drv.last_seq) == ring->fence_drv.sync_seq &&
600 coredump->ring != ring)
601 continue;
602
603 ring_count++;
604 }
605 if (ring_count)
606 coredump->rings = kvcalloc(ring_count,
607 sizeof(struct amdgpu_coredump_ring),
608 GFP_NOWAIT);
609 if (coredump->rings) {
610 for (i = 0, idx = 0; i < adev->num_rings && idx < ring_count; i++) {
611 struct amdgpu_coredump_ring *cdump_ring;
612
613 ring = adev->rings[i];
614
615 if (atomic_read(&ring->fence_drv.last_seq) == ring->fence_drv.sync_seq &&
616 coredump->ring != ring)
617 continue;
618
619 cdump_ring = &coredump->rings[idx];
620
621 cdump_ring->ring_dw = kvzalloc(ring->ring_size, GFP_NOWAIT);
622 if (cdump_ring->ring_dw)
623 memcpy(cdump_ring->ring_dw, ring->ring, ring->ring_size);
624
625 cdump_ring->ring_index = ring->idx;
626 cdump_ring->rptr = amdgpu_ring_get_rptr(ring);
627 cdump_ring->wptr = amdgpu_ring_get_wptr(ring);
628 idx++;
629 }
630 coredump->num_rings = idx;
631 }
632
633 coredump->adev = adev;
634
635 ktime_get_ts64(&coredump->reset_time);
636
637 /* Update the current coredump pointer (no lock needed, this function can only be called
638 * from a single thread)
639 */
640 adev->coredump = coredump;
641 /* Kick off coredump formatting to a worker thread. */
642 queue_work(system_dfl_wq, &adev->coredump_work);
643
644 drm_info(dev, "AMDGPU device coredump file has been created\n");
645 drm_info(dev, "Check your /sys/class/drm/card%d/device/devcoredump/data\n",
646 dev->primary->index);
647 }
648
amdgpu_coredump_init(struct amdgpu_device * adev)649 void amdgpu_coredump_init(struct amdgpu_device *adev)
650 {
651 INIT_WORK(&adev->coredump_work, amdgpu_devcoredump_deferred_work);
652 }
653
amdgpu_coredump_fini(struct amdgpu_device * adev)654 void amdgpu_coredump_fini(struct amdgpu_device *adev)
655 {
656 /* Finish deferred coredump formatting before HW/IP teardown. */
657 flush_work(&adev->coredump_work);
658 }
659 #endif
660