1 /* 2 * Copyright 2013 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/module.h> 25 #include <linux/pci.h> 26 27 #include "amdgpu.h" 28 #include "amdgpu_pm.h" 29 #include "amdgpu_dpm.h" 30 #include "amdgpu_atombios.h" 31 #include "amdgpu_dpm_internal.h" 32 #include "amd_pcie.h" 33 #include "atom.h" 34 #include "gfx_v6_0.h" 35 #include "r600_dpm.h" 36 #include "sid.h" 37 #include "si_dpm.h" 38 #include "../include/pptable.h" 39 #include <linux/math64.h> 40 #include <linux/seq_file.h> 41 #include <linux/firmware.h> 42 #include <legacy_dpm.h> 43 44 #include "bif/bif_3_0_d.h" 45 #include "bif/bif_3_0_sh_mask.h" 46 47 #include "dce/dce_6_0_d.h" 48 #include "dce/dce_6_0_sh_mask.h" 49 50 #include "gca/gfx_6_0_d.h" 51 #include "gca/gfx_6_0_sh_mask.h" 52 53 #include"gmc/gmc_6_0_d.h" 54 #include"gmc/gmc_6_0_sh_mask.h" 55 56 #include "smu/smu_6_0_d.h" 57 #include "smu/smu_6_0_sh_mask.h" 58 59 #define MC_CG_ARB_FREQ_F0 0x0a 60 #define MC_CG_ARB_FREQ_F1 0x0b 61 #define MC_CG_ARB_FREQ_F2 0x0c 62 #define MC_CG_ARB_FREQ_F3 0x0d 63 64 #define SMC_RAM_END 0x20000 65 66 #define SCLK_MIN_DEEPSLEEP_FREQ 1350 67 68 69 /* sizeof(ATOM_PPLIB_EXTENDEDHEADER) */ 70 #define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V2 12 71 #define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V3 14 72 #define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V4 16 73 #define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V5 18 74 #define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V6 20 75 #define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V7 22 76 77 #define BIOS_SCRATCH_4 0x5cd 78 79 MODULE_FIRMWARE("amdgpu/tahiti_smc.bin"); 80 MODULE_FIRMWARE("amdgpu/pitcairn_smc.bin"); 81 MODULE_FIRMWARE("amdgpu/pitcairn_k_smc.bin"); 82 MODULE_FIRMWARE("amdgpu/verde_smc.bin"); 83 MODULE_FIRMWARE("amdgpu/verde_k_smc.bin"); 84 MODULE_FIRMWARE("amdgpu/oland_smc.bin"); 85 MODULE_FIRMWARE("amdgpu/oland_k_smc.bin"); 86 MODULE_FIRMWARE("amdgpu/hainan_smc.bin"); 87 MODULE_FIRMWARE("amdgpu/hainan_k_smc.bin"); 88 MODULE_FIRMWARE("amdgpu/banks_k_2_smc.bin"); 89 90 static const struct amd_pm_funcs si_dpm_funcs; 91 92 union power_info { 93 struct _ATOM_POWERPLAY_INFO info; 94 struct _ATOM_POWERPLAY_INFO_V2 info_2; 95 struct _ATOM_POWERPLAY_INFO_V3 info_3; 96 struct _ATOM_PPLIB_POWERPLAYTABLE pplib; 97 struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2; 98 struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3; 99 struct _ATOM_PPLIB_POWERPLAYTABLE4 pplib4; 100 struct _ATOM_PPLIB_POWERPLAYTABLE5 pplib5; 101 }; 102 103 union fan_info { 104 struct _ATOM_PPLIB_FANTABLE fan; 105 struct _ATOM_PPLIB_FANTABLE2 fan2; 106 struct _ATOM_PPLIB_FANTABLE3 fan3; 107 }; 108 109 union pplib_clock_info { 110 struct _ATOM_PPLIB_R600_CLOCK_INFO r600; 111 struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780; 112 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen; 113 struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo; 114 struct _ATOM_PPLIB_SI_CLOCK_INFO si; 115 }; 116 117 enum si_dpm_auto_throttle_src { 118 SI_DPM_AUTO_THROTTLE_SRC_THERMAL, 119 SI_DPM_AUTO_THROTTLE_SRC_EXTERNAL 120 }; 121 122 enum si_dpm_event_src { 123 SI_DPM_EVENT_SRC_ANALOG = 0, 124 SI_DPM_EVENT_SRC_EXTERNAL = 1, 125 SI_DPM_EVENT_SRC_DIGITAL = 2, 126 SI_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3, 127 SI_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4 128 }; 129 130 static const u32 r600_utc[R600_PM_NUMBER_OF_TC] = 131 { 132 R600_UTC_DFLT_00, 133 R600_UTC_DFLT_01, 134 R600_UTC_DFLT_02, 135 R600_UTC_DFLT_03, 136 R600_UTC_DFLT_04, 137 R600_UTC_DFLT_05, 138 R600_UTC_DFLT_06, 139 R600_UTC_DFLT_07, 140 R600_UTC_DFLT_08, 141 R600_UTC_DFLT_09, 142 R600_UTC_DFLT_10, 143 R600_UTC_DFLT_11, 144 R600_UTC_DFLT_12, 145 R600_UTC_DFLT_13, 146 R600_UTC_DFLT_14, 147 }; 148 149 static const u32 r600_dtc[R600_PM_NUMBER_OF_TC] = 150 { 151 R600_DTC_DFLT_00, 152 R600_DTC_DFLT_01, 153 R600_DTC_DFLT_02, 154 R600_DTC_DFLT_03, 155 R600_DTC_DFLT_04, 156 R600_DTC_DFLT_05, 157 R600_DTC_DFLT_06, 158 R600_DTC_DFLT_07, 159 R600_DTC_DFLT_08, 160 R600_DTC_DFLT_09, 161 R600_DTC_DFLT_10, 162 R600_DTC_DFLT_11, 163 R600_DTC_DFLT_12, 164 R600_DTC_DFLT_13, 165 R600_DTC_DFLT_14, 166 }; 167 168 static const struct si_cac_config_reg cac_weights_tahiti[] = 169 { 170 { 0x0, 0x0000ffff, 0, 0xc, SISLANDS_CACCONFIG_CGIND }, 171 { 0x0, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 172 { 0x1, 0x0000ffff, 0, 0x101, SISLANDS_CACCONFIG_CGIND }, 173 { 0x1, 0xffff0000, 16, 0xc, SISLANDS_CACCONFIG_CGIND }, 174 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 175 { 0x3, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 176 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 177 { 0x4, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 178 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 179 { 0x5, 0x0000ffff, 0, 0x8fc, SISLANDS_CACCONFIG_CGIND }, 180 { 0x5, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 181 { 0x6, 0x0000ffff, 0, 0x95, SISLANDS_CACCONFIG_CGIND }, 182 { 0x6, 0xffff0000, 16, 0x34e, SISLANDS_CACCONFIG_CGIND }, 183 { 0x18f, 0x0000ffff, 0, 0x1a1, SISLANDS_CACCONFIG_CGIND }, 184 { 0x7, 0x0000ffff, 0, 0xda, SISLANDS_CACCONFIG_CGIND }, 185 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 186 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 187 { 0x8, 0xffff0000, 16, 0x46, SISLANDS_CACCONFIG_CGIND }, 188 { 0x9, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 189 { 0xa, 0x0000ffff, 0, 0x208, SISLANDS_CACCONFIG_CGIND }, 190 { 0xb, 0x0000ffff, 0, 0xe7, SISLANDS_CACCONFIG_CGIND }, 191 { 0xb, 0xffff0000, 16, 0x948, SISLANDS_CACCONFIG_CGIND }, 192 { 0xc, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 193 { 0xd, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 194 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 195 { 0xe, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 196 { 0xf, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 197 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 198 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 199 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 200 { 0x11, 0x0000ffff, 0, 0x167, SISLANDS_CACCONFIG_CGIND }, 201 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 202 { 0x12, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 203 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 204 { 0x13, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 205 { 0x14, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 206 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 207 { 0x15, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND }, 208 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 209 { 0x16, 0x0000ffff, 0, 0x31, SISLANDS_CACCONFIG_CGIND }, 210 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 211 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 212 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 213 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 214 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 215 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 216 { 0x1a, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 217 { 0x1a, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 218 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 219 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 220 { 0x1c, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 221 { 0x1c, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 222 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 223 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 224 { 0x1e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 225 { 0x1e, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 226 { 0x1f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 227 { 0x1f, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 228 { 0x20, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 229 { 0x6d, 0x0000ffff, 0, 0x18e, SISLANDS_CACCONFIG_CGIND }, 230 { 0xFFFFFFFF } 231 }; 232 233 static const struct si_cac_config_reg lcac_tahiti[] = 234 { 235 { 0x143, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND }, 236 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 237 { 0x146, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND }, 238 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 239 { 0x149, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND }, 240 { 0x149, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 241 { 0x14c, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND }, 242 { 0x14c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 243 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 244 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 245 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 246 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 247 { 0x9e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 248 { 0x9e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 249 { 0x101, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 250 { 0x101, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 251 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 252 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 253 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 254 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 255 { 0x10a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 256 { 0x10a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 257 { 0x10d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 258 { 0x10d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 259 { 0x8c, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 260 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 261 { 0x8f, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 262 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 263 { 0x92, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 264 { 0x92, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 265 { 0x95, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 266 { 0x95, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 267 { 0x14f, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 268 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 269 { 0x152, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 270 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 271 { 0x155, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 272 { 0x155, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 273 { 0x158, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 274 { 0x158, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 275 { 0x110, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 276 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 277 { 0x113, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 278 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 279 { 0x116, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 280 { 0x116, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 281 { 0x119, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 282 { 0x119, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 283 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 284 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 285 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 286 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 287 { 0x122, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 288 { 0x122, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 289 { 0x125, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 290 { 0x125, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 291 { 0x128, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 292 { 0x128, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 293 { 0x12b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 294 { 0x12b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 295 { 0x15b, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 296 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 297 { 0x15e, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 298 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 299 { 0x161, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 300 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 301 { 0x164, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 302 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 303 { 0x167, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 304 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 305 { 0x16a, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 306 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 307 { 0x16d, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 308 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 309 { 0x170, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 310 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 311 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 312 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 313 { 0x176, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 314 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 315 { 0x179, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 316 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 317 { 0x17c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 318 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 319 { 0x17f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 320 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 321 { 0xFFFFFFFF } 322 323 }; 324 325 static const struct si_cac_config_reg cac_override_tahiti[] = 326 { 327 { 0xFFFFFFFF } 328 }; 329 330 static const struct si_powertune_data powertune_data_tahiti = 331 { 332 ((1 << 16) | 27027), 333 6, 334 0, 335 4, 336 95, 337 { 338 0UL, 339 0UL, 340 4521550UL, 341 309631529UL, 342 -1270850L, 343 4513710L, 344 40 345 }, 346 595000000UL, 347 12, 348 { 349 0, 350 0, 351 0, 352 0, 353 0, 354 0, 355 0, 356 0 357 }, 358 true 359 }; 360 361 static const struct si_dte_data dte_data_tahiti = 362 { 363 { 1159409, 0, 0, 0, 0 }, 364 { 777, 0, 0, 0, 0 }, 365 2, 366 54000, 367 127000, 368 25, 369 2, 370 10, 371 13, 372 { 27, 31, 35, 39, 43, 47, 54, 61, 67, 74, 81, 88, 95, 0, 0, 0 }, 373 { 240888759, 221057860, 235370597, 162287531, 158510299, 131423027, 116673180, 103067515, 87941937, 76209048, 68209175, 64090048, 58301890, 0, 0, 0 }, 374 { 12024, 11189, 11451, 8411, 7939, 6666, 5681, 4905, 4241, 3720, 3354, 3122, 2890, 0, 0, 0 }, 375 85, 376 false 377 }; 378 379 static const struct si_dte_data dte_data_tahiti_pro = 380 { 381 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 382 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 383 5, 384 45000, 385 100, 386 0xA, 387 1, 388 0, 389 0x10, 390 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 391 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 392 { 0x7D0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 393 90, 394 true 395 }; 396 397 static const struct si_dte_data dte_data_new_zealand = 398 { 399 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0 }, 400 { 0x29B, 0x3E9, 0x537, 0x7D2, 0 }, 401 0x5, 402 0xAFC8, 403 0x69, 404 0x32, 405 1, 406 0, 407 0x10, 408 { 0x82, 0xA0, 0xB4, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE }, 409 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 410 { 0xDAC, 0x1388, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685 }, 411 85, 412 true 413 }; 414 415 static const struct si_dte_data dte_data_aruba_pro = 416 { 417 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 418 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 419 5, 420 45000, 421 100, 422 0xA, 423 1, 424 0, 425 0x10, 426 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 427 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 428 { 0x1000, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 429 90, 430 true 431 }; 432 433 static const struct si_dte_data dte_data_malta = 434 { 435 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 436 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 437 5, 438 45000, 439 100, 440 0xA, 441 1, 442 0, 443 0x10, 444 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 445 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 446 { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 447 90, 448 true 449 }; 450 451 static const struct si_cac_config_reg cac_weights_pitcairn[] = 452 { 453 { 0x0, 0x0000ffff, 0, 0x8a, SISLANDS_CACCONFIG_CGIND }, 454 { 0x0, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 455 { 0x1, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 456 { 0x1, 0xffff0000, 16, 0x24d, SISLANDS_CACCONFIG_CGIND }, 457 { 0x2, 0x0000ffff, 0, 0x19, SISLANDS_CACCONFIG_CGIND }, 458 { 0x3, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 459 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 460 { 0x4, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND }, 461 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 462 { 0x5, 0x0000ffff, 0, 0xc11, SISLANDS_CACCONFIG_CGIND }, 463 { 0x5, 0xffff0000, 16, 0x7f3, SISLANDS_CACCONFIG_CGIND }, 464 { 0x6, 0x0000ffff, 0, 0x403, SISLANDS_CACCONFIG_CGIND }, 465 { 0x6, 0xffff0000, 16, 0x367, SISLANDS_CACCONFIG_CGIND }, 466 { 0x18f, 0x0000ffff, 0, 0x4c9, SISLANDS_CACCONFIG_CGIND }, 467 { 0x7, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 468 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 469 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 470 { 0x8, 0xffff0000, 16, 0x45d, SISLANDS_CACCONFIG_CGIND }, 471 { 0x9, 0x0000ffff, 0, 0x36d, SISLANDS_CACCONFIG_CGIND }, 472 { 0xa, 0x0000ffff, 0, 0x534, SISLANDS_CACCONFIG_CGIND }, 473 { 0xb, 0x0000ffff, 0, 0x5da, SISLANDS_CACCONFIG_CGIND }, 474 { 0xb, 0xffff0000, 16, 0x880, SISLANDS_CACCONFIG_CGIND }, 475 { 0xc, 0x0000ffff, 0, 0x201, SISLANDS_CACCONFIG_CGIND }, 476 { 0xd, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 477 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 478 { 0xe, 0x0000ffff, 0, 0x9f, SISLANDS_CACCONFIG_CGIND }, 479 { 0xf, 0x0000ffff, 0, 0x1f, SISLANDS_CACCONFIG_CGIND }, 480 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 481 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 482 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 483 { 0x11, 0x0000ffff, 0, 0x5de, SISLANDS_CACCONFIG_CGIND }, 484 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 485 { 0x12, 0x0000ffff, 0, 0x7b, SISLANDS_CACCONFIG_CGIND }, 486 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 487 { 0x13, 0xffff0000, 16, 0x13, SISLANDS_CACCONFIG_CGIND }, 488 { 0x14, 0x0000ffff, 0, 0xf9, SISLANDS_CACCONFIG_CGIND }, 489 { 0x15, 0x0000ffff, 0, 0x66, SISLANDS_CACCONFIG_CGIND }, 490 { 0x15, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 491 { 0x4e, 0x0000ffff, 0, 0x13, SISLANDS_CACCONFIG_CGIND }, 492 { 0x16, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 493 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 494 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 495 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 496 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 497 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 498 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 499 { 0x1a, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 500 { 0x1a, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 501 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 502 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 503 { 0x1c, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 504 { 0x1c, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 505 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 506 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 507 { 0x1e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 508 { 0x1e, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 509 { 0x1f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 510 { 0x1f, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 511 { 0x20, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 512 { 0x6d, 0x0000ffff, 0, 0x186, SISLANDS_CACCONFIG_CGIND }, 513 { 0xFFFFFFFF } 514 }; 515 516 static const struct si_cac_config_reg lcac_pitcairn[] = 517 { 518 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 519 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 520 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 521 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 522 { 0x110, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 523 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 524 { 0x14f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 525 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 526 { 0x8c, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 527 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 528 { 0x143, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 529 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 530 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 531 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 532 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 533 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 534 { 0x113, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 535 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 536 { 0x152, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 537 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 538 { 0x8f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 539 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 540 { 0x146, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 541 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 542 { 0x9e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 543 { 0x9e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 544 { 0x10a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 545 { 0x10a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 546 { 0x116, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 547 { 0x116, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 548 { 0x155, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 549 { 0x155, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 550 { 0x92, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 551 { 0x92, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 552 { 0x149, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 553 { 0x149, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 554 { 0x101, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 555 { 0x101, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 556 { 0x10d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 557 { 0x10d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 558 { 0x119, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 559 { 0x119, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 560 { 0x158, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 561 { 0x158, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 562 { 0x95, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 563 { 0x95, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 564 { 0x14c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 565 { 0x14c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 566 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 567 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 568 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 569 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 570 { 0x122, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 571 { 0x122, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 572 { 0x125, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 573 { 0x125, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 574 { 0x128, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 575 { 0x128, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 576 { 0x12b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 577 { 0x12b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 578 { 0x164, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 579 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 580 { 0x167, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 581 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 582 { 0x16a, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 583 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 584 { 0x15e, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 585 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 586 { 0x161, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 587 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 588 { 0x15b, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 589 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 590 { 0x16d, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 591 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 592 { 0x170, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 593 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 594 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 595 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 596 { 0x176, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 597 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 598 { 0x179, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 599 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 600 { 0x17c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 601 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 602 { 0x17f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 603 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 604 { 0xFFFFFFFF } 605 }; 606 607 static const struct si_cac_config_reg cac_override_pitcairn[] = 608 { 609 { 0xFFFFFFFF } 610 }; 611 612 static const struct si_powertune_data powertune_data_pitcairn = 613 { 614 ((1 << 16) | 27027), 615 5, 616 0, 617 6, 618 100, 619 { 620 51600000UL, 621 1800000UL, 622 7194395UL, 623 309631529UL, 624 -1270850L, 625 4513710L, 626 100 627 }, 628 117830498UL, 629 12, 630 { 631 0, 632 0, 633 0, 634 0, 635 0, 636 0, 637 0, 638 0 639 }, 640 true 641 }; 642 643 static const struct si_dte_data dte_data_pitcairn = 644 { 645 { 0, 0, 0, 0, 0 }, 646 { 0, 0, 0, 0, 0 }, 647 0, 648 0, 649 0, 650 0, 651 0, 652 0, 653 0, 654 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 655 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 656 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 657 0, 658 false 659 }; 660 661 static const struct si_dte_data dte_data_curacao_xt = 662 { 663 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 664 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 665 5, 666 45000, 667 100, 668 0xA, 669 1, 670 0, 671 0x10, 672 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 673 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 674 { 0x1D17, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 675 90, 676 true 677 }; 678 679 static const struct si_dte_data dte_data_curacao_pro = 680 { 681 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 682 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 683 5, 684 45000, 685 100, 686 0xA, 687 1, 688 0, 689 0x10, 690 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 691 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 692 { 0x1D17, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 693 90, 694 true 695 }; 696 697 static const struct si_dte_data dte_data_neptune_xt = 698 { 699 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 700 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 701 5, 702 45000, 703 100, 704 0xA, 705 1, 706 0, 707 0x10, 708 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 709 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 710 { 0x3A2F, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 711 90, 712 true 713 }; 714 715 static const struct si_cac_config_reg cac_weights_chelsea_pro[] = 716 { 717 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 718 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 719 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 720 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 721 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 722 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 723 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 724 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 725 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 726 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 727 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 728 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 729 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 730 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 731 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 732 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 733 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 734 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 735 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 736 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 737 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 738 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 739 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 740 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 741 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 742 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 743 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 744 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 745 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 746 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 747 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 748 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 749 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 750 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 751 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 752 { 0x14, 0x0000ffff, 0, 0x2BD, SISLANDS_CACCONFIG_CGIND }, 753 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 754 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 755 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 756 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 757 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 758 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 759 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 760 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 761 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 762 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 763 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 764 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 765 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 766 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 767 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 768 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 769 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 770 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 771 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 772 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 773 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 774 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 775 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 776 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 777 { 0xFFFFFFFF } 778 }; 779 780 static const struct si_cac_config_reg cac_weights_chelsea_xt[] = 781 { 782 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 783 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 784 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 785 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 786 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 787 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 788 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 789 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 790 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 791 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 792 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 793 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 794 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 795 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 796 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 797 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 798 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 799 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 800 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 801 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 802 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 803 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 804 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 805 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 806 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 807 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 808 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 809 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 810 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 811 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 812 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 813 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 814 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 815 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 816 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 817 { 0x14, 0x0000ffff, 0, 0x30A, SISLANDS_CACCONFIG_CGIND }, 818 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 819 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 820 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 821 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 822 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 823 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 824 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 825 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 826 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 827 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 828 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 829 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 830 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 831 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 832 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 833 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 834 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 835 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 836 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 837 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 838 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 839 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 840 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 841 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 842 { 0xFFFFFFFF } 843 }; 844 845 static const struct si_cac_config_reg cac_weights_heathrow[] = 846 { 847 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 848 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 849 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 850 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 851 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 852 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 853 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 854 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 855 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 856 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 857 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 858 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 859 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 860 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 861 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 862 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 863 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 864 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 865 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 866 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 867 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 868 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 869 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 870 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 871 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 872 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 873 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 874 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 875 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 876 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 877 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 878 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 879 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 880 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 881 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 882 { 0x14, 0x0000ffff, 0, 0x362, SISLANDS_CACCONFIG_CGIND }, 883 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 884 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 885 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 886 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 887 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 888 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 889 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 890 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 891 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 892 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 893 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 894 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 895 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 896 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 897 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 898 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 899 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 900 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 901 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 902 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 903 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 904 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 905 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 906 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 907 { 0xFFFFFFFF } 908 }; 909 910 static const struct si_cac_config_reg cac_weights_cape_verde_pro[] = 911 { 912 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 913 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 914 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 915 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 916 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 917 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 918 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 919 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 920 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 921 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 922 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 923 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 924 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 925 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 926 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 927 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 928 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 929 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 930 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 931 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 932 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 933 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 934 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 935 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 936 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 937 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 938 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 939 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 940 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 941 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 942 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 943 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 944 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 945 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 946 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 947 { 0x14, 0x0000ffff, 0, 0x315, SISLANDS_CACCONFIG_CGIND }, 948 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 949 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 950 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 951 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 952 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 953 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 954 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 955 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 956 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 957 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 958 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 959 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 960 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 961 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 962 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 963 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 964 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 965 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 966 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 967 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 968 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 969 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 970 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 971 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 972 { 0xFFFFFFFF } 973 }; 974 975 static const struct si_cac_config_reg cac_weights_cape_verde[] = 976 { 977 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 978 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 979 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 980 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 981 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 982 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 983 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 984 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 985 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 986 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 987 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 988 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 989 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 990 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 991 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 992 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 993 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 994 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 995 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 996 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 997 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 998 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 999 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 1000 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 1001 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 1002 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1003 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 1004 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1005 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1006 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 1007 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1008 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 1009 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 1010 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 1011 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 1012 { 0x14, 0x0000ffff, 0, 0x3BA, SISLANDS_CACCONFIG_CGIND }, 1013 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1014 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 1015 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1016 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 1017 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 1018 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1019 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1020 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1021 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1022 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1023 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1024 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1025 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1026 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1027 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1028 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1029 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1030 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1031 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1032 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1033 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1034 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1035 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1036 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 1037 { 0xFFFFFFFF } 1038 }; 1039 1040 static const struct si_cac_config_reg lcac_cape_verde[] = 1041 { 1042 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1043 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1044 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1045 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1046 { 0x110, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 1047 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1048 { 0x14f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 1049 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1050 { 0x8c, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 1051 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1052 { 0x143, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1053 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1054 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1055 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1056 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1057 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1058 { 0x113, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 1059 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1060 { 0x152, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 1061 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1062 { 0x8f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1063 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1064 { 0x146, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1065 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1066 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1067 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1068 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1069 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1070 { 0x164, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1071 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1072 { 0x167, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1073 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1074 { 0x16a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1075 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1076 { 0x15e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1077 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1078 { 0x161, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1079 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1080 { 0x15b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1081 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1082 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1083 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1084 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1085 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1086 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1087 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1088 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1089 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1090 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1091 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1092 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1093 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1094 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1095 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1096 { 0xFFFFFFFF } 1097 }; 1098 1099 static const struct si_cac_config_reg cac_override_cape_verde[] = 1100 { 1101 { 0xFFFFFFFF } 1102 }; 1103 1104 static const struct si_powertune_data powertune_data_cape_verde = 1105 { 1106 ((1 << 16) | 0x6993), 1107 5, 1108 0, 1109 7, 1110 105, 1111 { 1112 0UL, 1113 0UL, 1114 7194395UL, 1115 309631529UL, 1116 -1270850L, 1117 4513710L, 1118 100 1119 }, 1120 117830498UL, 1121 12, 1122 { 1123 0, 1124 0, 1125 0, 1126 0, 1127 0, 1128 0, 1129 0, 1130 0 1131 }, 1132 true 1133 }; 1134 1135 static const struct si_dte_data dte_data_cape_verde = 1136 { 1137 { 0, 0, 0, 0, 0 }, 1138 { 0, 0, 0, 0, 0 }, 1139 0, 1140 0, 1141 0, 1142 0, 1143 0, 1144 0, 1145 0, 1146 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1147 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1148 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1149 0, 1150 false 1151 }; 1152 1153 static const struct si_dte_data dte_data_venus_xtx = 1154 { 1155 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 1156 { 0x71C, 0xAAB, 0xE39, 0x11C7, 0x0 }, 1157 5, 1158 55000, 1159 0x69, 1160 0xA, 1161 1, 1162 0, 1163 0x3, 1164 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1165 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1166 { 0xD6D8, 0x88B8, 0x1555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1167 90, 1168 true 1169 }; 1170 1171 static const struct si_dte_data dte_data_venus_xt = 1172 { 1173 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 1174 { 0xBDA, 0x11C7, 0x17B4, 0x1DA1, 0x0 }, 1175 5, 1176 55000, 1177 0x69, 1178 0xA, 1179 1, 1180 0, 1181 0x3, 1182 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1183 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1184 { 0xAFC8, 0x88B8, 0x238E, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1185 90, 1186 true 1187 }; 1188 1189 static const struct si_dte_data dte_data_venus_pro = 1190 { 1191 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 1192 { 0x11C7, 0x1AAB, 0x238E, 0x2C72, 0x0 }, 1193 5, 1194 55000, 1195 0x69, 1196 0xA, 1197 1, 1198 0, 1199 0x3, 1200 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1201 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1202 { 0x88B8, 0x88B8, 0x3555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1203 90, 1204 true 1205 }; 1206 1207 static const struct si_cac_config_reg cac_weights_oland[] = 1208 { 1209 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 1210 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 1211 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 1212 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 1213 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1214 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 1215 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 1216 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 1217 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 1218 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 1219 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 1220 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 1221 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 1222 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 1223 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 1224 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 1225 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 1226 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 1227 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 1228 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 1229 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 1230 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 1231 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 1232 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 1233 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 1234 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1235 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 1236 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1237 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1238 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 1239 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1240 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 1241 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 1242 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 1243 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 1244 { 0x14, 0x0000ffff, 0, 0x3BA, SISLANDS_CACCONFIG_CGIND }, 1245 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1246 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 1247 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1248 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 1249 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 1250 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1251 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1252 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1253 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1254 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1255 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1256 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1257 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1258 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1259 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1260 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1261 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1262 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1263 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1264 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1265 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1266 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1267 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1268 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 1269 { 0xFFFFFFFF } 1270 }; 1271 1272 static const struct si_cac_config_reg cac_weights_mars_pro[] = 1273 { 1274 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND }, 1275 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1276 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND }, 1277 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND }, 1278 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1279 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1280 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1281 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1282 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND }, 1283 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND }, 1284 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND }, 1285 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND }, 1286 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND }, 1287 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND }, 1288 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND }, 1289 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND }, 1290 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND }, 1291 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND }, 1292 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND }, 1293 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND }, 1294 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND }, 1295 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND }, 1296 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND }, 1297 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1298 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND }, 1299 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND }, 1300 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 1301 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND }, 1302 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1303 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 1304 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND }, 1305 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1306 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND }, 1307 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND }, 1308 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND }, 1309 { 0x14, 0x0000ffff, 0, 0x2, SISLANDS_CACCONFIG_CGIND }, 1310 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1311 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 1312 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1313 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND }, 1314 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND }, 1315 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1316 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1317 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1318 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1319 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1320 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND }, 1321 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1322 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1323 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1324 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND }, 1325 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND }, 1326 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1327 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1328 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1329 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1330 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1331 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1332 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1333 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND }, 1334 { 0xFFFFFFFF } 1335 }; 1336 1337 static const struct si_cac_config_reg cac_weights_mars_xt[] = 1338 { 1339 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND }, 1340 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1341 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND }, 1342 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND }, 1343 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1344 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1345 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1346 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1347 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND }, 1348 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND }, 1349 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND }, 1350 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND }, 1351 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND }, 1352 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND }, 1353 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND }, 1354 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND }, 1355 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND }, 1356 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND }, 1357 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND }, 1358 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND }, 1359 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND }, 1360 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND }, 1361 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND }, 1362 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1363 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND }, 1364 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND }, 1365 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 1366 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND }, 1367 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1368 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 1369 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND }, 1370 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1371 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND }, 1372 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND }, 1373 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND }, 1374 { 0x14, 0x0000ffff, 0, 0x60, SISLANDS_CACCONFIG_CGIND }, 1375 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1376 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 1377 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1378 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND }, 1379 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND }, 1380 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1381 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1382 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1383 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1384 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1385 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND }, 1386 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1387 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1388 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1389 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND }, 1390 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND }, 1391 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1392 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1393 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1394 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1395 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1396 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1397 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1398 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND }, 1399 { 0xFFFFFFFF } 1400 }; 1401 1402 static const struct si_cac_config_reg cac_weights_oland_pro[] = 1403 { 1404 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND }, 1405 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1406 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND }, 1407 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND }, 1408 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1409 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1410 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1411 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1412 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND }, 1413 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND }, 1414 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND }, 1415 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND }, 1416 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND }, 1417 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND }, 1418 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND }, 1419 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND }, 1420 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND }, 1421 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND }, 1422 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND }, 1423 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND }, 1424 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND }, 1425 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND }, 1426 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND }, 1427 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1428 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND }, 1429 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND }, 1430 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 1431 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND }, 1432 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1433 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 1434 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND }, 1435 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1436 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND }, 1437 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND }, 1438 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND }, 1439 { 0x14, 0x0000ffff, 0, 0x90, SISLANDS_CACCONFIG_CGIND }, 1440 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1441 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 1442 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1443 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND }, 1444 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND }, 1445 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1446 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1447 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1448 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1449 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1450 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND }, 1451 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1452 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1453 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1454 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND }, 1455 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND }, 1456 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1457 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1458 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1459 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1460 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1461 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1462 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1463 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND }, 1464 { 0xFFFFFFFF } 1465 }; 1466 1467 static const struct si_cac_config_reg cac_weights_oland_xt[] = 1468 { 1469 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND }, 1470 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1471 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND }, 1472 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND }, 1473 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1474 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1475 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1476 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1477 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND }, 1478 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND }, 1479 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND }, 1480 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND }, 1481 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND }, 1482 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND }, 1483 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND }, 1484 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND }, 1485 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND }, 1486 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND }, 1487 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND }, 1488 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND }, 1489 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND }, 1490 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND }, 1491 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND }, 1492 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1493 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND }, 1494 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND }, 1495 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 1496 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND }, 1497 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1498 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 1499 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND }, 1500 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1501 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND }, 1502 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND }, 1503 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND }, 1504 { 0x14, 0x0000ffff, 0, 0x120, SISLANDS_CACCONFIG_CGIND }, 1505 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1506 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 1507 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1508 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND }, 1509 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND }, 1510 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1511 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1512 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1513 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1514 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1515 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND }, 1516 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1517 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1518 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1519 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND }, 1520 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND }, 1521 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1522 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1523 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1524 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1525 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1526 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1527 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1528 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND }, 1529 { 0xFFFFFFFF } 1530 }; 1531 1532 static const struct si_cac_config_reg lcac_oland[] = 1533 { 1534 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1535 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1536 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1537 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1538 { 0x110, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1539 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1540 { 0x14f, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1541 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1542 { 0x8c, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1543 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1544 { 0x143, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 1545 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1546 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1547 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1548 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1549 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1550 { 0x164, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1551 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1552 { 0x167, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1553 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1554 { 0x16a, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1555 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1556 { 0x15e, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1557 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1558 { 0x161, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1559 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1560 { 0x15b, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1561 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1562 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1563 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1564 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1565 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1566 { 0x173, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1567 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1568 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1569 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1570 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1571 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1572 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1573 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1574 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1575 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1576 { 0xFFFFFFFF } 1577 }; 1578 1579 static const struct si_cac_config_reg lcac_mars_pro[] = 1580 { 1581 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1582 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1583 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1584 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1585 { 0x110, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1586 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1587 { 0x14f, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1588 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1589 { 0x8c, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1590 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1591 { 0x143, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1592 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1593 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1594 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1595 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1596 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1597 { 0x164, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1598 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1599 { 0x167, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1600 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1601 { 0x16a, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1602 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1603 { 0x15e, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1604 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1605 { 0x161, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1606 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1607 { 0x15b, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1608 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1609 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1610 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1611 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1612 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1613 { 0x173, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1614 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1615 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1616 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1617 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1618 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1619 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1620 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1621 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1622 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1623 { 0xFFFFFFFF } 1624 }; 1625 1626 static const struct si_cac_config_reg cac_override_oland[] = 1627 { 1628 { 0xFFFFFFFF } 1629 }; 1630 1631 static const struct si_powertune_data powertune_data_oland = 1632 { 1633 ((1 << 16) | 0x6993), 1634 5, 1635 0, 1636 7, 1637 105, 1638 { 1639 0UL, 1640 0UL, 1641 7194395UL, 1642 309631529UL, 1643 -1270850L, 1644 4513710L, 1645 100 1646 }, 1647 117830498UL, 1648 12, 1649 { 1650 0, 1651 0, 1652 0, 1653 0, 1654 0, 1655 0, 1656 0, 1657 0 1658 }, 1659 true 1660 }; 1661 1662 static const struct si_powertune_data powertune_data_mars_pro = 1663 { 1664 ((1 << 16) | 0x6993), 1665 5, 1666 0, 1667 7, 1668 105, 1669 { 1670 0UL, 1671 0UL, 1672 7194395UL, 1673 309631529UL, 1674 -1270850L, 1675 4513710L, 1676 100 1677 }, 1678 117830498UL, 1679 12, 1680 { 1681 0, 1682 0, 1683 0, 1684 0, 1685 0, 1686 0, 1687 0, 1688 0 1689 }, 1690 true 1691 }; 1692 1693 static const struct si_dte_data dte_data_oland = 1694 { 1695 { 0, 0, 0, 0, 0 }, 1696 { 0, 0, 0, 0, 0 }, 1697 0, 1698 0, 1699 0, 1700 0, 1701 0, 1702 0, 1703 0, 1704 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1705 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1706 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1707 0, 1708 false 1709 }; 1710 1711 static const struct si_dte_data dte_data_mars_pro = 1712 { 1713 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 1714 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 1715 5, 1716 55000, 1717 105, 1718 0xA, 1719 1, 1720 0, 1721 0x10, 1722 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 1723 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 1724 { 0xF627, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1725 90, 1726 true 1727 }; 1728 1729 static const struct si_dte_data dte_data_sun_xt = 1730 { 1731 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 1732 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 1733 5, 1734 55000, 1735 105, 1736 0xA, 1737 1, 1738 0, 1739 0x10, 1740 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 1741 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 1742 { 0xD555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1743 90, 1744 true 1745 }; 1746 1747 1748 static const struct si_cac_config_reg cac_weights_hainan[] = 1749 { 1750 { 0x0, 0x0000ffff, 0, 0x2d9, SISLANDS_CACCONFIG_CGIND }, 1751 { 0x0, 0xffff0000, 16, 0x22b, SISLANDS_CACCONFIG_CGIND }, 1752 { 0x1, 0x0000ffff, 0, 0x21c, SISLANDS_CACCONFIG_CGIND }, 1753 { 0x1, 0xffff0000, 16, 0x1dc, SISLANDS_CACCONFIG_CGIND }, 1754 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1755 { 0x3, 0x0000ffff, 0, 0x24e, SISLANDS_CACCONFIG_CGIND }, 1756 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1757 { 0x4, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1758 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1759 { 0x5, 0x0000ffff, 0, 0x35e, SISLANDS_CACCONFIG_CGIND }, 1760 { 0x5, 0xffff0000, 16, 0x1143, SISLANDS_CACCONFIG_CGIND }, 1761 { 0x6, 0x0000ffff, 0, 0xe17, SISLANDS_CACCONFIG_CGIND }, 1762 { 0x6, 0xffff0000, 16, 0x441, SISLANDS_CACCONFIG_CGIND }, 1763 { 0x18f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1764 { 0x7, 0x0000ffff, 0, 0x28b, SISLANDS_CACCONFIG_CGIND }, 1765 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1766 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1767 { 0x8, 0xffff0000, 16, 0xabe, SISLANDS_CACCONFIG_CGIND }, 1768 { 0x9, 0x0000ffff, 0, 0xf11, SISLANDS_CACCONFIG_CGIND }, 1769 { 0xa, 0x0000ffff, 0, 0x907, SISLANDS_CACCONFIG_CGIND }, 1770 { 0xb, 0x0000ffff, 0, 0xb45, SISLANDS_CACCONFIG_CGIND }, 1771 { 0xb, 0xffff0000, 16, 0xd1e, SISLANDS_CACCONFIG_CGIND }, 1772 { 0xc, 0x0000ffff, 0, 0xa2c, SISLANDS_CACCONFIG_CGIND }, 1773 { 0xd, 0x0000ffff, 0, 0x62, SISLANDS_CACCONFIG_CGIND }, 1774 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1775 { 0xe, 0x0000ffff, 0, 0x1f3, SISLANDS_CACCONFIG_CGIND }, 1776 { 0xf, 0x0000ffff, 0, 0x42, SISLANDS_CACCONFIG_CGIND }, 1777 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1778 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1779 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1780 { 0x11, 0x0000ffff, 0, 0x709, SISLANDS_CACCONFIG_CGIND }, 1781 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1782 { 0x12, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1783 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1784 { 0x13, 0xffff0000, 16, 0x3a, SISLANDS_CACCONFIG_CGIND }, 1785 { 0x14, 0x0000ffff, 0, 0x357, SISLANDS_CACCONFIG_CGIND }, 1786 { 0x15, 0x0000ffff, 0, 0x9f, SISLANDS_CACCONFIG_CGIND }, 1787 { 0x15, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1788 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1789 { 0x16, 0x0000ffff, 0, 0x314, SISLANDS_CACCONFIG_CGIND }, 1790 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1791 { 0x17, 0x0000ffff, 0, 0x6d, SISLANDS_CACCONFIG_CGIND }, 1792 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1793 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1794 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1795 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1796 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1797 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1798 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1799 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1800 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1801 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1802 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1803 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1804 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1805 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1806 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1807 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1808 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1809 { 0x6d, 0x0000ffff, 0, 0x1b9, SISLANDS_CACCONFIG_CGIND }, 1810 { 0xFFFFFFFF } 1811 }; 1812 1813 static const struct si_powertune_data powertune_data_hainan = 1814 { 1815 ((1 << 16) | 0x6993), 1816 5, 1817 0, 1818 9, 1819 105, 1820 { 1821 0UL, 1822 0UL, 1823 7194395UL, 1824 309631529UL, 1825 -1270850L, 1826 4513710L, 1827 100 1828 }, 1829 117830498UL, 1830 12, 1831 { 1832 0, 1833 0, 1834 0, 1835 0, 1836 0, 1837 0, 1838 0, 1839 0 1840 }, 1841 true 1842 }; 1843 1844 static struct rv7xx_power_info *rv770_get_pi(struct amdgpu_device *adev); 1845 static struct evergreen_power_info *evergreen_get_pi(struct amdgpu_device *adev); 1846 static struct ni_power_info *ni_get_pi(struct amdgpu_device *adev); 1847 static struct si_ps *si_get_ps(struct amdgpu_ps *rps); 1848 1849 static int si_populate_voltage_value(struct amdgpu_device *adev, 1850 const struct atom_voltage_table *table, 1851 u16 value, SISLANDS_SMC_VOLTAGE_VALUE *voltage); 1852 static int si_get_std_voltage_value(struct amdgpu_device *adev, 1853 SISLANDS_SMC_VOLTAGE_VALUE *voltage, 1854 u16 *std_voltage); 1855 static int si_write_smc_soft_register(struct amdgpu_device *adev, 1856 u16 reg_offset, u32 value); 1857 static int si_convert_power_level_to_smc(struct amdgpu_device *adev, 1858 struct rv7xx_pl *pl, 1859 SISLANDS_SMC_HW_PERFORMANCE_LEVEL *level); 1860 static int si_calculate_sclk_params(struct amdgpu_device *adev, 1861 u32 engine_clock, 1862 SISLANDS_SMC_SCLK_VALUE *sclk); 1863 1864 static void si_thermal_start_smc_fan_control(struct amdgpu_device *adev); 1865 static void si_fan_ctrl_set_default_mode(struct amdgpu_device *adev); 1866 static void si_dpm_set_irq_funcs(struct amdgpu_device *adev); 1867 1868 static struct si_power_info *si_get_pi(struct amdgpu_device *adev) 1869 { 1870 struct si_power_info *pi = adev->pm.dpm.priv; 1871 return pi; 1872 } 1873 1874 static void si_calculate_leakage_for_v_and_t_formula(const struct ni_leakage_coeffients *coeff, 1875 u16 v, s32 t, u32 ileakage, u32 *leakage) 1876 { 1877 s64 kt, kv, leakage_w, i_leakage, vddc; 1878 s64 temperature, t_slope, t_intercept, av, bv, t_ref; 1879 s64 tmp; 1880 1881 i_leakage = div64_s64(drm_int2fixp(ileakage), 100); 1882 vddc = div64_s64(drm_int2fixp(v), 1000); 1883 temperature = div64_s64(drm_int2fixp(t), 1000); 1884 1885 t_slope = div64_s64(drm_int2fixp(coeff->t_slope), 100000000); 1886 t_intercept = div64_s64(drm_int2fixp(coeff->t_intercept), 100000000); 1887 av = div64_s64(drm_int2fixp(coeff->av), 100000000); 1888 bv = div64_s64(drm_int2fixp(coeff->bv), 100000000); 1889 t_ref = drm_int2fixp(coeff->t_ref); 1890 1891 tmp = drm_fixp_mul(t_slope, vddc) + t_intercept; 1892 kt = drm_fixp_exp(drm_fixp_mul(tmp, temperature)); 1893 kt = drm_fixp_div(kt, drm_fixp_exp(drm_fixp_mul(tmp, t_ref))); 1894 kv = drm_fixp_mul(av, drm_fixp_exp(drm_fixp_mul(bv, vddc))); 1895 1896 leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc); 1897 1898 *leakage = drm_fixp2int(leakage_w * 1000); 1899 } 1900 1901 static void si_calculate_leakage_for_v_and_t(struct amdgpu_device *adev, 1902 const struct ni_leakage_coeffients *coeff, 1903 u16 v, 1904 s32 t, 1905 u32 i_leakage, 1906 u32 *leakage) 1907 { 1908 si_calculate_leakage_for_v_and_t_formula(coeff, v, t, i_leakage, leakage); 1909 } 1910 1911 static void si_calculate_leakage_for_v_formula(const struct ni_leakage_coeffients *coeff, 1912 const u32 fixed_kt, u16 v, 1913 u32 ileakage, u32 *leakage) 1914 { 1915 s64 kt, kv, leakage_w, i_leakage, vddc; 1916 1917 i_leakage = div64_s64(drm_int2fixp(ileakage), 100); 1918 vddc = div64_s64(drm_int2fixp(v), 1000); 1919 1920 kt = div64_s64(drm_int2fixp(fixed_kt), 100000000); 1921 kv = drm_fixp_mul(div64_s64(drm_int2fixp(coeff->av), 100000000), 1922 drm_fixp_exp(drm_fixp_mul(div64_s64(drm_int2fixp(coeff->bv), 100000000), vddc))); 1923 1924 leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc); 1925 1926 *leakage = drm_fixp2int(leakage_w * 1000); 1927 } 1928 1929 static void si_calculate_leakage_for_v(struct amdgpu_device *adev, 1930 const struct ni_leakage_coeffients *coeff, 1931 const u32 fixed_kt, 1932 u16 v, 1933 u32 i_leakage, 1934 u32 *leakage) 1935 { 1936 si_calculate_leakage_for_v_formula(coeff, fixed_kt, v, i_leakage, leakage); 1937 } 1938 1939 1940 static void si_update_dte_from_pl2(struct amdgpu_device *adev, 1941 struct si_dte_data *dte_data) 1942 { 1943 u32 p_limit1 = adev->pm.dpm.tdp_limit; 1944 u32 p_limit2 = adev->pm.dpm.near_tdp_limit; 1945 u32 k = dte_data->k; 1946 u32 t_max = dte_data->max_t; 1947 u32 t_split[5] = { 10, 15, 20, 25, 30 }; 1948 u32 t_0 = dte_data->t0; 1949 u32 i; 1950 1951 if (p_limit2 != 0 && p_limit2 <= p_limit1) { 1952 dte_data->tdep_count = 3; 1953 1954 for (i = 0; i < k; i++) { 1955 dte_data->r[i] = 1956 (t_split[i] * (t_max - t_0/(u32)1000) * (1 << 14)) / 1957 (p_limit2 * (u32)100); 1958 } 1959 1960 dte_data->tdep_r[1] = dte_data->r[4] * 2; 1961 1962 for (i = 2; i < SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE; i++) { 1963 dte_data->tdep_r[i] = dte_data->r[4]; 1964 } 1965 } else { 1966 DRM_ERROR("Invalid PL2! DTE will not be updated.\n"); 1967 } 1968 } 1969 1970 static struct rv7xx_power_info *rv770_get_pi(struct amdgpu_device *adev) 1971 { 1972 struct rv7xx_power_info *pi = adev->pm.dpm.priv; 1973 1974 return pi; 1975 } 1976 1977 static struct ni_power_info *ni_get_pi(struct amdgpu_device *adev) 1978 { 1979 struct ni_power_info *pi = adev->pm.dpm.priv; 1980 1981 return pi; 1982 } 1983 1984 static struct si_ps *si_get_ps(struct amdgpu_ps *aps) 1985 { 1986 struct si_ps *ps = aps->ps_priv; 1987 1988 return ps; 1989 } 1990 1991 static void si_initialize_powertune_defaults(struct amdgpu_device *adev) 1992 { 1993 struct ni_power_info *ni_pi = ni_get_pi(adev); 1994 struct si_power_info *si_pi = si_get_pi(adev); 1995 bool update_dte_from_pl2 = false; 1996 1997 if (adev->asic_type == CHIP_TAHITI) { 1998 si_pi->cac_weights = cac_weights_tahiti; 1999 si_pi->lcac_config = lcac_tahiti; 2000 si_pi->cac_override = cac_override_tahiti; 2001 si_pi->powertune_data = &powertune_data_tahiti; 2002 si_pi->dte_data = dte_data_tahiti; 2003 2004 switch (adev->pdev->device) { 2005 case 0x6798: 2006 si_pi->dte_data.enable_dte_by_default = true; 2007 break; 2008 case 0x6799: 2009 si_pi->dte_data = dte_data_new_zealand; 2010 break; 2011 case 0x6790: 2012 case 0x6791: 2013 case 0x6792: 2014 case 0x679E: 2015 si_pi->dte_data = dte_data_aruba_pro; 2016 update_dte_from_pl2 = true; 2017 break; 2018 case 0x679B: 2019 si_pi->dte_data = dte_data_malta; 2020 update_dte_from_pl2 = true; 2021 break; 2022 case 0x679A: 2023 si_pi->dte_data = dte_data_tahiti_pro; 2024 update_dte_from_pl2 = true; 2025 break; 2026 default: 2027 if (si_pi->dte_data.enable_dte_by_default == true) 2028 DRM_ERROR("DTE is not enabled!\n"); 2029 break; 2030 } 2031 } else if (adev->asic_type == CHIP_PITCAIRN) { 2032 si_pi->cac_weights = cac_weights_pitcairn; 2033 si_pi->lcac_config = lcac_pitcairn; 2034 si_pi->cac_override = cac_override_pitcairn; 2035 si_pi->powertune_data = &powertune_data_pitcairn; 2036 2037 switch (adev->pdev->device) { 2038 case 0x6810: 2039 case 0x6818: 2040 si_pi->dte_data = dte_data_curacao_xt; 2041 update_dte_from_pl2 = true; 2042 break; 2043 case 0x6819: 2044 case 0x6811: 2045 si_pi->dte_data = dte_data_curacao_pro; 2046 update_dte_from_pl2 = true; 2047 break; 2048 case 0x6800: 2049 case 0x6806: 2050 si_pi->dte_data = dte_data_neptune_xt; 2051 update_dte_from_pl2 = true; 2052 break; 2053 default: 2054 si_pi->dte_data = dte_data_pitcairn; 2055 break; 2056 } 2057 } else if (adev->asic_type == CHIP_VERDE) { 2058 si_pi->lcac_config = lcac_cape_verde; 2059 si_pi->cac_override = cac_override_cape_verde; 2060 si_pi->powertune_data = &powertune_data_cape_verde; 2061 2062 switch (adev->pdev->device) { 2063 case 0x683B: 2064 case 0x683F: 2065 case 0x6829: 2066 case 0x6835: 2067 si_pi->cac_weights = cac_weights_cape_verde_pro; 2068 si_pi->dte_data = dte_data_cape_verde; 2069 break; 2070 case 0x682C: 2071 si_pi->cac_weights = cac_weights_cape_verde_pro; 2072 si_pi->dte_data = dte_data_sun_xt; 2073 update_dte_from_pl2 = true; 2074 break; 2075 case 0x6825: 2076 case 0x6827: 2077 si_pi->cac_weights = cac_weights_heathrow; 2078 si_pi->dte_data = dte_data_cape_verde; 2079 break; 2080 case 0x6824: 2081 case 0x682D: 2082 si_pi->cac_weights = cac_weights_chelsea_xt; 2083 si_pi->dte_data = dte_data_cape_verde; 2084 break; 2085 case 0x682F: 2086 si_pi->cac_weights = cac_weights_chelsea_pro; 2087 si_pi->dte_data = dte_data_cape_verde; 2088 break; 2089 case 0x6820: 2090 si_pi->cac_weights = cac_weights_heathrow; 2091 si_pi->dte_data = dte_data_venus_xtx; 2092 break; 2093 case 0x6821: 2094 si_pi->cac_weights = cac_weights_heathrow; 2095 si_pi->dte_data = dte_data_venus_xt; 2096 break; 2097 case 0x6823: 2098 case 0x682B: 2099 case 0x6822: 2100 case 0x682A: 2101 si_pi->cac_weights = cac_weights_chelsea_pro; 2102 si_pi->dte_data = dte_data_venus_pro; 2103 break; 2104 default: 2105 si_pi->cac_weights = cac_weights_cape_verde; 2106 si_pi->dte_data = dte_data_cape_verde; 2107 break; 2108 } 2109 } else if (adev->asic_type == CHIP_OLAND) { 2110 si_pi->lcac_config = lcac_mars_pro; 2111 si_pi->cac_override = cac_override_oland; 2112 si_pi->powertune_data = &powertune_data_mars_pro; 2113 si_pi->dte_data = dte_data_mars_pro; 2114 2115 switch (adev->pdev->device) { 2116 case 0x6601: 2117 case 0x6621: 2118 case 0x6603: 2119 case 0x6605: 2120 si_pi->cac_weights = cac_weights_mars_pro; 2121 update_dte_from_pl2 = true; 2122 break; 2123 case 0x6600: 2124 case 0x6606: 2125 case 0x6620: 2126 case 0x6604: 2127 si_pi->cac_weights = cac_weights_mars_xt; 2128 update_dte_from_pl2 = true; 2129 break; 2130 case 0x6611: 2131 case 0x6613: 2132 case 0x6608: 2133 si_pi->cac_weights = cac_weights_oland_pro; 2134 update_dte_from_pl2 = true; 2135 break; 2136 case 0x6610: 2137 si_pi->cac_weights = cac_weights_oland_xt; 2138 update_dte_from_pl2 = true; 2139 break; 2140 default: 2141 si_pi->cac_weights = cac_weights_oland; 2142 si_pi->lcac_config = lcac_oland; 2143 si_pi->cac_override = cac_override_oland; 2144 si_pi->powertune_data = &powertune_data_oland; 2145 si_pi->dte_data = dte_data_oland; 2146 break; 2147 } 2148 } else if (adev->asic_type == CHIP_HAINAN) { 2149 si_pi->cac_weights = cac_weights_hainan; 2150 si_pi->lcac_config = lcac_oland; 2151 si_pi->cac_override = cac_override_oland; 2152 si_pi->powertune_data = &powertune_data_hainan; 2153 si_pi->dte_data = dte_data_sun_xt; 2154 update_dte_from_pl2 = true; 2155 } else { 2156 DRM_ERROR("Unknown SI asic revision, failed to initialize PowerTune!\n"); 2157 return; 2158 } 2159 2160 ni_pi->enable_power_containment = false; 2161 ni_pi->enable_cac = false; 2162 ni_pi->enable_sq_ramping = false; 2163 si_pi->enable_dte = false; 2164 2165 if (si_pi->powertune_data->enable_powertune_by_default) { 2166 ni_pi->enable_power_containment = true; 2167 ni_pi->enable_cac = true; 2168 if (si_pi->dte_data.enable_dte_by_default) { 2169 si_pi->enable_dte = true; 2170 if (update_dte_from_pl2) 2171 si_update_dte_from_pl2(adev, &si_pi->dte_data); 2172 2173 } 2174 ni_pi->enable_sq_ramping = true; 2175 } 2176 2177 ni_pi->driver_calculate_cac_leakage = true; 2178 ni_pi->cac_configuration_required = true; 2179 2180 if (ni_pi->cac_configuration_required) { 2181 ni_pi->support_cac_long_term_average = true; 2182 si_pi->dyn_powertune_data.l2_lta_window_size = 2183 si_pi->powertune_data->l2_lta_window_size_default; 2184 si_pi->dyn_powertune_data.lts_truncate = 2185 si_pi->powertune_data->lts_truncate_default; 2186 } else { 2187 ni_pi->support_cac_long_term_average = false; 2188 si_pi->dyn_powertune_data.l2_lta_window_size = 0; 2189 si_pi->dyn_powertune_data.lts_truncate = 0; 2190 } 2191 2192 si_pi->dyn_powertune_data.disable_uvd_powertune = false; 2193 } 2194 2195 static u32 si_get_smc_power_scaling_factor(struct amdgpu_device *adev) 2196 { 2197 return 1; 2198 } 2199 2200 static u32 si_calculate_cac_wintime(struct amdgpu_device *adev) 2201 { 2202 u32 xclk; 2203 u32 wintime; 2204 u32 cac_window; 2205 u32 cac_window_size; 2206 2207 xclk = amdgpu_asic_get_xclk(adev); 2208 2209 if (xclk == 0) 2210 return 0; 2211 2212 cac_window = RREG32(mmCG_CAC_CTRL) & CG_CAC_CTRL__CAC_WINDOW_MASK; 2213 cac_window_size = ((cac_window & 0xFFFF0000) >> 16) * (cac_window & 0x0000FFFF); 2214 2215 wintime = (cac_window_size * 100) / xclk; 2216 2217 return wintime; 2218 } 2219 2220 static u32 si_scale_power_for_smc(u32 power_in_watts, u32 scaling_factor) 2221 { 2222 return power_in_watts; 2223 } 2224 2225 static int si_calculate_adjusted_tdp_limits(struct amdgpu_device *adev, 2226 bool adjust_polarity, 2227 u32 tdp_adjustment, 2228 u32 *tdp_limit, 2229 u32 *near_tdp_limit) 2230 { 2231 u32 adjustment_delta, max_tdp_limit; 2232 2233 if (tdp_adjustment > (u32)adev->pm.dpm.tdp_od_limit) 2234 return -EINVAL; 2235 2236 max_tdp_limit = ((100 + 100) * adev->pm.dpm.tdp_limit) / 100; 2237 2238 if (adjust_polarity) { 2239 *tdp_limit = ((100 + tdp_adjustment) * adev->pm.dpm.tdp_limit) / 100; 2240 *near_tdp_limit = adev->pm.dpm.near_tdp_limit_adjusted + (*tdp_limit - adev->pm.dpm.tdp_limit); 2241 } else { 2242 *tdp_limit = ((100 - tdp_adjustment) * adev->pm.dpm.tdp_limit) / 100; 2243 adjustment_delta = adev->pm.dpm.tdp_limit - *tdp_limit; 2244 if (adjustment_delta < adev->pm.dpm.near_tdp_limit_adjusted) 2245 *near_tdp_limit = adev->pm.dpm.near_tdp_limit_adjusted - adjustment_delta; 2246 else 2247 *near_tdp_limit = 0; 2248 } 2249 2250 if ((*tdp_limit <= 0) || (*tdp_limit > max_tdp_limit)) 2251 return -EINVAL; 2252 if ((*near_tdp_limit <= 0) || (*near_tdp_limit > *tdp_limit)) 2253 return -EINVAL; 2254 2255 return 0; 2256 } 2257 2258 static int si_populate_smc_tdp_limits(struct amdgpu_device *adev, 2259 struct amdgpu_ps *amdgpu_state) 2260 { 2261 struct ni_power_info *ni_pi = ni_get_pi(adev); 2262 struct si_power_info *si_pi = si_get_pi(adev); 2263 2264 if (ni_pi->enable_power_containment) { 2265 SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable; 2266 PP_SIslands_PAPMParameters *papm_parm; 2267 struct amdgpu_ppm_table *ppm = adev->pm.dpm.dyn_state.ppm_table; 2268 u32 scaling_factor = si_get_smc_power_scaling_factor(adev); 2269 u32 tdp_limit; 2270 u32 near_tdp_limit; 2271 int ret; 2272 2273 if (scaling_factor == 0) 2274 return -EINVAL; 2275 2276 ret = si_calculate_adjusted_tdp_limits(adev, 2277 false, /* ??? */ 2278 adev->pm.dpm.tdp_adjustment, 2279 &tdp_limit, 2280 &near_tdp_limit); 2281 if (ret) 2282 return ret; 2283 2284 if (adev->pdev->device == 0x6611 && adev->pdev->revision == 0x87) { 2285 /* Workaround buggy powertune on Radeon 430 and 520. */ 2286 tdp_limit = 32; 2287 near_tdp_limit = 28; 2288 } 2289 2290 smc_table->dpm2Params.TDPLimit = 2291 cpu_to_be32(si_scale_power_for_smc(tdp_limit, scaling_factor) * 1000); 2292 smc_table->dpm2Params.NearTDPLimit = 2293 cpu_to_be32(si_scale_power_for_smc(near_tdp_limit, scaling_factor) * 1000); 2294 smc_table->dpm2Params.SafePowerLimit = 2295 cpu_to_be32(si_scale_power_for_smc((near_tdp_limit * SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100, scaling_factor) * 1000); 2296 2297 ret = amdgpu_si_copy_bytes_to_smc(adev, 2298 (si_pi->state_table_start + offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) + 2299 offsetof(PP_SIslands_DPM2Parameters, TDPLimit)), 2300 (u8 *)(&(smc_table->dpm2Params.TDPLimit)), 2301 sizeof(u32) * 3, 2302 si_pi->sram_end); 2303 if (ret) 2304 return ret; 2305 2306 if (si_pi->enable_ppm) { 2307 papm_parm = &si_pi->papm_parm; 2308 memset(papm_parm, 0, sizeof(PP_SIslands_PAPMParameters)); 2309 papm_parm->NearTDPLimitTherm = cpu_to_be32(ppm->dgpu_tdp); 2310 papm_parm->dGPU_T_Limit = cpu_to_be32(ppm->tj_max); 2311 papm_parm->dGPU_T_Warning = cpu_to_be32(95); 2312 papm_parm->dGPU_T_Hysteresis = cpu_to_be32(5); 2313 papm_parm->PlatformPowerLimit = 0xffffffff; 2314 papm_parm->NearTDPLimitPAPM = 0xffffffff; 2315 2316 ret = amdgpu_si_copy_bytes_to_smc(adev, si_pi->papm_cfg_table_start, 2317 (u8 *)papm_parm, 2318 sizeof(PP_SIslands_PAPMParameters), 2319 si_pi->sram_end); 2320 if (ret) 2321 return ret; 2322 } 2323 } 2324 return 0; 2325 } 2326 2327 static int si_populate_smc_tdp_limits_2(struct amdgpu_device *adev, 2328 struct amdgpu_ps *amdgpu_state) 2329 { 2330 struct ni_power_info *ni_pi = ni_get_pi(adev); 2331 struct si_power_info *si_pi = si_get_pi(adev); 2332 2333 if (ni_pi->enable_power_containment) { 2334 SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable; 2335 int ret; 2336 2337 ret = amdgpu_si_copy_bytes_to_smc(adev, 2338 (si_pi->state_table_start + 2339 offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) + 2340 offsetof(PP_SIslands_DPM2Parameters, NearTDPLimit)), 2341 (u8 *)(&(smc_table->dpm2Params.NearTDPLimit)), 2342 sizeof(u32) * 2, 2343 si_pi->sram_end); 2344 if (ret) 2345 return ret; 2346 } 2347 2348 return 0; 2349 } 2350 2351 static u16 si_calculate_power_efficiency_ratio(struct amdgpu_device *adev, 2352 const u16 prev_std_vddc, 2353 const u16 curr_std_vddc) 2354 { 2355 u64 margin = (u64)SISLANDS_DPM2_PWREFFICIENCYRATIO_MARGIN; 2356 u64 prev_vddc = (u64)prev_std_vddc; 2357 u64 curr_vddc = (u64)curr_std_vddc; 2358 u64 pwr_efficiency_ratio, n, d; 2359 2360 if ((prev_vddc == 0) || (curr_vddc == 0)) 2361 return 0; 2362 2363 n = div64_u64((u64)1024 * curr_vddc * curr_vddc * ((u64)1000 + margin), (u64)1000); 2364 d = prev_vddc * prev_vddc; 2365 pwr_efficiency_ratio = div64_u64(n, d); 2366 2367 if (pwr_efficiency_ratio > (u64)0xFFFF) 2368 return 0; 2369 2370 return (u16)pwr_efficiency_ratio; 2371 } 2372 2373 static bool si_should_disable_uvd_powertune(struct amdgpu_device *adev, 2374 struct amdgpu_ps *amdgpu_state) 2375 { 2376 struct si_power_info *si_pi = si_get_pi(adev); 2377 2378 if (si_pi->dyn_powertune_data.disable_uvd_powertune && 2379 amdgpu_state->vclk && amdgpu_state->dclk) 2380 return true; 2381 2382 return false; 2383 } 2384 2385 struct evergreen_power_info *evergreen_get_pi(struct amdgpu_device *adev) 2386 { 2387 struct evergreen_power_info *pi = adev->pm.dpm.priv; 2388 2389 return pi; 2390 } 2391 2392 static int si_populate_power_containment_values(struct amdgpu_device *adev, 2393 struct amdgpu_ps *amdgpu_state, 2394 SISLANDS_SMC_SWSTATE *smc_state) 2395 { 2396 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); 2397 struct ni_power_info *ni_pi = ni_get_pi(adev); 2398 struct si_ps *state = si_get_ps(amdgpu_state); 2399 SISLANDS_SMC_VOLTAGE_VALUE vddc; 2400 u32 prev_sclk; 2401 u32 max_sclk; 2402 u32 min_sclk; 2403 u16 prev_std_vddc; 2404 u16 curr_std_vddc; 2405 int i; 2406 u16 pwr_efficiency_ratio; 2407 u8 max_ps_percent; 2408 bool disable_uvd_power_tune; 2409 int ret; 2410 2411 if (ni_pi->enable_power_containment == false) 2412 return 0; 2413 2414 if (state->performance_level_count == 0) 2415 return -EINVAL; 2416 2417 if (smc_state->levelCount != state->performance_level_count) 2418 return -EINVAL; 2419 2420 disable_uvd_power_tune = si_should_disable_uvd_powertune(adev, amdgpu_state); 2421 2422 smc_state->levels[0].dpm2.MaxPS = 0; 2423 smc_state->levels[0].dpm2.NearTDPDec = 0; 2424 smc_state->levels[0].dpm2.AboveSafeInc = 0; 2425 smc_state->levels[0].dpm2.BelowSafeInc = 0; 2426 smc_state->levels[0].dpm2.PwrEfficiencyRatio = 0; 2427 2428 for (i = 1; i < state->performance_level_count; i++) { 2429 prev_sclk = state->performance_levels[i-1].sclk; 2430 max_sclk = state->performance_levels[i].sclk; 2431 if (i == 1) 2432 max_ps_percent = SISLANDS_DPM2_MAXPS_PERCENT_M; 2433 else 2434 max_ps_percent = SISLANDS_DPM2_MAXPS_PERCENT_H; 2435 2436 if (prev_sclk > max_sclk) 2437 return -EINVAL; 2438 2439 if ((max_ps_percent == 0) || 2440 (prev_sclk == max_sclk) || 2441 disable_uvd_power_tune) 2442 min_sclk = max_sclk; 2443 else if (i == 1) 2444 min_sclk = prev_sclk; 2445 else 2446 min_sclk = (prev_sclk * (u32)max_ps_percent) / 100; 2447 2448 if (min_sclk < state->performance_levels[0].sclk) 2449 min_sclk = state->performance_levels[0].sclk; 2450 2451 if (min_sclk == 0) 2452 return -EINVAL; 2453 2454 ret = si_populate_voltage_value(adev, &eg_pi->vddc_voltage_table, 2455 state->performance_levels[i-1].vddc, &vddc); 2456 if (ret) 2457 return ret; 2458 2459 ret = si_get_std_voltage_value(adev, &vddc, &prev_std_vddc); 2460 if (ret) 2461 return ret; 2462 2463 ret = si_populate_voltage_value(adev, &eg_pi->vddc_voltage_table, 2464 state->performance_levels[i].vddc, &vddc); 2465 if (ret) 2466 return ret; 2467 2468 ret = si_get_std_voltage_value(adev, &vddc, &curr_std_vddc); 2469 if (ret) 2470 return ret; 2471 2472 pwr_efficiency_ratio = si_calculate_power_efficiency_ratio(adev, 2473 prev_std_vddc, curr_std_vddc); 2474 2475 smc_state->levels[i].dpm2.MaxPS = (u8)((SISLANDS_DPM2_MAX_PULSE_SKIP * (max_sclk - min_sclk)) / max_sclk); 2476 smc_state->levels[i].dpm2.NearTDPDec = SISLANDS_DPM2_NEAR_TDP_DEC; 2477 smc_state->levels[i].dpm2.AboveSafeInc = SISLANDS_DPM2_ABOVE_SAFE_INC; 2478 smc_state->levels[i].dpm2.BelowSafeInc = SISLANDS_DPM2_BELOW_SAFE_INC; 2479 smc_state->levels[i].dpm2.PwrEfficiencyRatio = cpu_to_be16(pwr_efficiency_ratio); 2480 } 2481 2482 return 0; 2483 } 2484 2485 static int si_populate_sq_ramping_values(struct amdgpu_device *adev, 2486 struct amdgpu_ps *amdgpu_state, 2487 SISLANDS_SMC_SWSTATE *smc_state) 2488 { 2489 struct ni_power_info *ni_pi = ni_get_pi(adev); 2490 struct si_ps *state = si_get_ps(amdgpu_state); 2491 u32 sq_power_throttle, sq_power_throttle2; 2492 bool enable_sq_ramping = ni_pi->enable_sq_ramping; 2493 int i; 2494 2495 if (state->performance_level_count == 0) 2496 return -EINVAL; 2497 2498 if (smc_state->levelCount != state->performance_level_count) 2499 return -EINVAL; 2500 2501 if (adev->pm.dpm.sq_ramping_threshold == 0) 2502 return -EINVAL; 2503 2504 if (SISLANDS_DPM2_SQ_RAMP_MAX_POWER > (SQ_POWER_THROTTLE__MAX_POWER_MASK >> SQ_POWER_THROTTLE__MAX_POWER__SHIFT)) 2505 enable_sq_ramping = false; 2506 2507 if (SISLANDS_DPM2_SQ_RAMP_MIN_POWER > (SQ_POWER_THROTTLE__MIN_POWER_MASK >> SQ_POWER_THROTTLE__MIN_POWER__SHIFT)) 2508 enable_sq_ramping = false; 2509 2510 if (SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA > (SQ_POWER_THROTTLE2__MAX_POWER_DELTA_MASK >> SQ_POWER_THROTTLE2__MAX_POWER_DELTA__SHIFT)) 2511 enable_sq_ramping = false; 2512 2513 if (SISLANDS_DPM2_SQ_RAMP_STI_SIZE > (SQ_POWER_THROTTLE2__SHORT_TERM_INTERVAL_SIZE_MASK >> SQ_POWER_THROTTLE2__SHORT_TERM_INTERVAL_SIZE__SHIFT)) 2514 enable_sq_ramping = false; 2515 2516 if (SISLANDS_DPM2_SQ_RAMP_LTI_RATIO > (SQ_POWER_THROTTLE2__LONG_TERM_INTERVAL_RATIO_MASK >> SQ_POWER_THROTTLE2__LONG_TERM_INTERVAL_RATIO__SHIFT)) 2517 enable_sq_ramping = false; 2518 2519 for (i = 0; i < state->performance_level_count; i++) { 2520 sq_power_throttle = 0; 2521 sq_power_throttle2 = 0; 2522 2523 if ((state->performance_levels[i].sclk >= adev->pm.dpm.sq_ramping_threshold) && 2524 enable_sq_ramping) { 2525 sq_power_throttle |= SISLANDS_DPM2_SQ_RAMP_MAX_POWER << SQ_POWER_THROTTLE__MAX_POWER__SHIFT; 2526 sq_power_throttle |= SISLANDS_DPM2_SQ_RAMP_MIN_POWER << SQ_POWER_THROTTLE__MIN_POWER__SHIFT; 2527 sq_power_throttle2 |= SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA << SQ_POWER_THROTTLE2__MAX_POWER_DELTA__SHIFT; 2528 sq_power_throttle2 |= SISLANDS_DPM2_SQ_RAMP_STI_SIZE << SQ_POWER_THROTTLE2__SHORT_TERM_INTERVAL_SIZE__SHIFT; 2529 sq_power_throttle2 |= SISLANDS_DPM2_SQ_RAMP_LTI_RATIO << SQ_POWER_THROTTLE2__LONG_TERM_INTERVAL_RATIO__SHIFT; 2530 } else { 2531 sq_power_throttle |= SQ_POWER_THROTTLE__MAX_POWER_MASK | 2532 SQ_POWER_THROTTLE__MIN_POWER_MASK; 2533 sq_power_throttle2 |= SQ_POWER_THROTTLE2__MAX_POWER_DELTA_MASK | 2534 SQ_POWER_THROTTLE2__SHORT_TERM_INTERVAL_SIZE_MASK | 2535 SQ_POWER_THROTTLE2__LONG_TERM_INTERVAL_RATIO_MASK; 2536 } 2537 2538 smc_state->levels[i].SQPowerThrottle = cpu_to_be32(sq_power_throttle); 2539 smc_state->levels[i].SQPowerThrottle_2 = cpu_to_be32(sq_power_throttle2); 2540 } 2541 2542 return 0; 2543 } 2544 2545 static int si_enable_power_containment(struct amdgpu_device *adev, 2546 struct amdgpu_ps *amdgpu_new_state, 2547 bool enable) 2548 { 2549 struct ni_power_info *ni_pi = ni_get_pi(adev); 2550 PPSMC_Result smc_result; 2551 int ret = 0; 2552 2553 if (ni_pi->enable_power_containment) { 2554 if (enable) { 2555 if (!si_should_disable_uvd_powertune(adev, amdgpu_new_state)) { 2556 smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_TDPClampingActive); 2557 if (smc_result != PPSMC_Result_OK) 2558 ret = -EINVAL; 2559 } 2560 } else { 2561 smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_TDPClampingInactive); 2562 if (smc_result != PPSMC_Result_OK) 2563 ret = -EINVAL; 2564 } 2565 } 2566 2567 return ret; 2568 } 2569 2570 static int si_initialize_smc_dte_tables(struct amdgpu_device *adev) 2571 { 2572 struct si_power_info *si_pi = si_get_pi(adev); 2573 int ret = 0; 2574 struct si_dte_data *dte_data = &si_pi->dte_data; 2575 Smc_SIslands_DTE_Configuration *dte_tables = NULL; 2576 u32 table_size; 2577 u8 tdep_count; 2578 u32 i; 2579 2580 if (dte_data == NULL) 2581 si_pi->enable_dte = false; 2582 2583 if (si_pi->enable_dte == false) 2584 return 0; 2585 2586 if (dte_data->k <= 0) 2587 return -EINVAL; 2588 2589 dte_tables = kzalloc_obj(Smc_SIslands_DTE_Configuration); 2590 if (dte_tables == NULL) { 2591 si_pi->enable_dte = false; 2592 return -ENOMEM; 2593 } 2594 2595 table_size = dte_data->k; 2596 2597 if (table_size > SMC_SISLANDS_DTE_MAX_FILTER_STAGES) 2598 table_size = SMC_SISLANDS_DTE_MAX_FILTER_STAGES; 2599 2600 tdep_count = dte_data->tdep_count; 2601 if (tdep_count > SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE) 2602 tdep_count = SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE; 2603 2604 dte_tables->K = cpu_to_be32(table_size); 2605 dte_tables->T0 = cpu_to_be32(dte_data->t0); 2606 dte_tables->MaxT = cpu_to_be32(dte_data->max_t); 2607 dte_tables->WindowSize = dte_data->window_size; 2608 dte_tables->temp_select = dte_data->temp_select; 2609 dte_tables->DTE_mode = dte_data->dte_mode; 2610 dte_tables->Tthreshold = cpu_to_be32(dte_data->t_threshold); 2611 2612 if (tdep_count > 0) 2613 table_size--; 2614 2615 for (i = 0; i < table_size; i++) { 2616 dte_tables->tau[i] = cpu_to_be32(dte_data->tau[i]); 2617 dte_tables->R[i] = cpu_to_be32(dte_data->r[i]); 2618 } 2619 2620 dte_tables->Tdep_count = tdep_count; 2621 2622 for (i = 0; i < (u32)tdep_count; i++) { 2623 dte_tables->T_limits[i] = dte_data->t_limits[i]; 2624 dte_tables->Tdep_tau[i] = cpu_to_be32(dte_data->tdep_tau[i]); 2625 dte_tables->Tdep_R[i] = cpu_to_be32(dte_data->tdep_r[i]); 2626 } 2627 2628 ret = amdgpu_si_copy_bytes_to_smc(adev, si_pi->dte_table_start, 2629 (u8 *)dte_tables, 2630 sizeof(Smc_SIslands_DTE_Configuration), 2631 si_pi->sram_end); 2632 kfree(dte_tables); 2633 2634 return ret; 2635 } 2636 2637 static int si_get_cac_std_voltage_max_min(struct amdgpu_device *adev, 2638 u16 *max, u16 *min) 2639 { 2640 struct si_power_info *si_pi = si_get_pi(adev); 2641 struct amdgpu_cac_leakage_table *table = 2642 &adev->pm.dpm.dyn_state.cac_leakage_table; 2643 u32 i; 2644 u32 v0_loadline; 2645 2646 if (table == NULL) 2647 return -EINVAL; 2648 2649 *max = 0; 2650 *min = 0xFFFF; 2651 2652 for (i = 0; i < table->count; i++) { 2653 if (table->entries[i].vddc > *max) 2654 *max = table->entries[i].vddc; 2655 if (table->entries[i].vddc < *min) 2656 *min = table->entries[i].vddc; 2657 } 2658 2659 if (si_pi->powertune_data->lkge_lut_v0_percent > 100) 2660 return -EINVAL; 2661 2662 v0_loadline = (*min) * (100 - si_pi->powertune_data->lkge_lut_v0_percent) / 100; 2663 2664 if (v0_loadline > 0xFFFFUL) 2665 return -EINVAL; 2666 2667 *min = (u16)v0_loadline; 2668 2669 if ((*min > *max) || (*max == 0) || (*min == 0)) 2670 return -EINVAL; 2671 2672 return 0; 2673 } 2674 2675 static u16 si_get_cac_std_voltage_step(u16 max, u16 min) 2676 { 2677 return ((max - min) + (SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES - 1)) / 2678 SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; 2679 } 2680 2681 static int si_init_dte_leakage_table(struct amdgpu_device *adev, 2682 PP_SIslands_CacConfig *cac_tables, 2683 u16 vddc_max, u16 vddc_min, u16 vddc_step, 2684 u16 t0, u16 t_step) 2685 { 2686 struct si_power_info *si_pi = si_get_pi(adev); 2687 u32 leakage; 2688 unsigned int i, j; 2689 s32 t; 2690 u32 smc_leakage; 2691 u32 scaling_factor; 2692 u16 voltage; 2693 2694 scaling_factor = si_get_smc_power_scaling_factor(adev); 2695 2696 for (i = 0; i < SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES ; i++) { 2697 t = (1000 * (i * t_step + t0)); 2698 2699 for (j = 0; j < SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; j++) { 2700 voltage = vddc_max - (vddc_step * j); 2701 2702 si_calculate_leakage_for_v_and_t(adev, 2703 &si_pi->powertune_data->leakage_coefficients, 2704 voltage, 2705 t, 2706 si_pi->dyn_powertune_data.cac_leakage, 2707 &leakage); 2708 2709 smc_leakage = si_scale_power_for_smc(leakage, scaling_factor) / 4; 2710 2711 if (smc_leakage > 0xFFFF) 2712 smc_leakage = 0xFFFF; 2713 2714 cac_tables->cac_lkge_lut[i][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES-1-j] = 2715 cpu_to_be16((u16)smc_leakage); 2716 } 2717 } 2718 return 0; 2719 } 2720 2721 static int si_init_simplified_leakage_table(struct amdgpu_device *adev, 2722 PP_SIslands_CacConfig *cac_tables, 2723 u16 vddc_max, u16 vddc_min, u16 vddc_step) 2724 { 2725 struct si_power_info *si_pi = si_get_pi(adev); 2726 u32 leakage; 2727 unsigned int i, j; 2728 u32 smc_leakage; 2729 u32 scaling_factor; 2730 u16 voltage; 2731 2732 scaling_factor = si_get_smc_power_scaling_factor(adev); 2733 2734 for (j = 0; j < SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; j++) { 2735 voltage = vddc_max - (vddc_step * j); 2736 2737 si_calculate_leakage_for_v(adev, 2738 &si_pi->powertune_data->leakage_coefficients, 2739 si_pi->powertune_data->fixed_kt, 2740 voltage, 2741 si_pi->dyn_powertune_data.cac_leakage, 2742 &leakage); 2743 2744 smc_leakage = si_scale_power_for_smc(leakage, scaling_factor) / 4; 2745 2746 if (smc_leakage > 0xFFFF) 2747 smc_leakage = 0xFFFF; 2748 2749 for (i = 0; i < SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES ; i++) 2750 cac_tables->cac_lkge_lut[i][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES-1-j] = 2751 cpu_to_be16((u16)smc_leakage); 2752 } 2753 return 0; 2754 } 2755 2756 static int si_initialize_smc_cac_tables(struct amdgpu_device *adev) 2757 { 2758 struct ni_power_info *ni_pi = ni_get_pi(adev); 2759 struct si_power_info *si_pi = si_get_pi(adev); 2760 PP_SIslands_CacConfig *cac_tables = NULL; 2761 u16 vddc_max, vddc_min, vddc_step; 2762 u16 t0, t_step; 2763 u32 load_line_slope, reg; 2764 int ret = 0; 2765 u32 ticks_per_us = amdgpu_asic_get_xclk(adev) / 100; 2766 2767 if (ni_pi->enable_cac == false) 2768 return 0; 2769 2770 cac_tables = kzalloc_obj(PP_SIslands_CacConfig); 2771 if (!cac_tables) 2772 return -ENOMEM; 2773 2774 reg = RREG32(mmCG_CAC_CTRL) & ~CG_CAC_CTRL__CAC_WINDOW_MASK; 2775 reg |= (si_pi->powertune_data->cac_window << CG_CAC_CTRL__CAC_WINDOW__SHIFT); 2776 WREG32(mmCG_CAC_CTRL, reg); 2777 2778 si_pi->dyn_powertune_data.cac_leakage = adev->pm.dpm.cac_leakage; 2779 si_pi->dyn_powertune_data.dc_pwr_value = 2780 si_pi->powertune_data->dc_cac[NISLANDS_DCCAC_LEVEL_0]; 2781 si_pi->dyn_powertune_data.wintime = si_calculate_cac_wintime(adev); 2782 si_pi->dyn_powertune_data.shift_n = si_pi->powertune_data->shift_n_default; 2783 2784 si_pi->dyn_powertune_data.leakage_minimum_temperature = 80 * 1000; 2785 2786 ret = si_get_cac_std_voltage_max_min(adev, &vddc_max, &vddc_min); 2787 if (ret) 2788 goto done_free; 2789 2790 vddc_step = si_get_cac_std_voltage_step(vddc_max, vddc_min); 2791 vddc_min = vddc_max - (vddc_step * (SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES - 1)); 2792 t_step = 4; 2793 t0 = 60; 2794 2795 if (si_pi->enable_dte || ni_pi->driver_calculate_cac_leakage) 2796 ret = si_init_dte_leakage_table(adev, cac_tables, 2797 vddc_max, vddc_min, vddc_step, 2798 t0, t_step); 2799 else 2800 ret = si_init_simplified_leakage_table(adev, cac_tables, 2801 vddc_max, vddc_min, vddc_step); 2802 if (ret) 2803 goto done_free; 2804 2805 load_line_slope = ((u32)adev->pm.dpm.load_line_slope << SMC_SISLANDS_SCALE_R) / 100; 2806 2807 cac_tables->l2numWin_TDP = cpu_to_be32(si_pi->dyn_powertune_data.l2_lta_window_size); 2808 cac_tables->lts_truncate_n = si_pi->dyn_powertune_data.lts_truncate; 2809 cac_tables->SHIFT_N = si_pi->dyn_powertune_data.shift_n; 2810 cac_tables->lkge_lut_V0 = cpu_to_be32((u32)vddc_min); 2811 cac_tables->lkge_lut_Vstep = cpu_to_be32((u32)vddc_step); 2812 cac_tables->R_LL = cpu_to_be32(load_line_slope); 2813 cac_tables->WinTime = cpu_to_be32(si_pi->dyn_powertune_data.wintime); 2814 cac_tables->calculation_repeats = cpu_to_be32(2); 2815 cac_tables->dc_cac = cpu_to_be32(0); 2816 cac_tables->log2_PG_LKG_SCALE = 12; 2817 cac_tables->cac_temp = si_pi->powertune_data->operating_temp; 2818 cac_tables->lkge_lut_T0 = cpu_to_be32((u32)t0); 2819 cac_tables->lkge_lut_Tstep = cpu_to_be32((u32)t_step); 2820 2821 ret = amdgpu_si_copy_bytes_to_smc(adev, si_pi->cac_table_start, 2822 (u8 *)cac_tables, 2823 sizeof(PP_SIslands_CacConfig), 2824 si_pi->sram_end); 2825 2826 if (ret) 2827 goto done_free; 2828 2829 ret = si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_ticks_per_us, ticks_per_us); 2830 2831 done_free: 2832 if (ret) { 2833 ni_pi->enable_cac = false; 2834 ni_pi->enable_power_containment = false; 2835 } 2836 2837 kfree(cac_tables); 2838 2839 return ret; 2840 } 2841 2842 static int si_program_cac_config_registers(struct amdgpu_device *adev, 2843 const struct si_cac_config_reg *cac_config_regs) 2844 { 2845 const struct si_cac_config_reg *config_regs = cac_config_regs; 2846 u32 data = 0, offset; 2847 2848 if (!config_regs) 2849 return -EINVAL; 2850 2851 while (config_regs->offset != 0xFFFFFFFF) { 2852 switch (config_regs->type) { 2853 case SISLANDS_CACCONFIG_CGIND: 2854 offset = SMC_CG_IND_START + config_regs->offset; 2855 if (offset < SMC_CG_IND_END) 2856 data = RREG32_SMC(offset); 2857 break; 2858 default: 2859 data = RREG32(config_regs->offset); 2860 break; 2861 } 2862 2863 data &= ~config_regs->mask; 2864 data |= ((config_regs->value << config_regs->shift) & config_regs->mask); 2865 2866 switch (config_regs->type) { 2867 case SISLANDS_CACCONFIG_CGIND: 2868 offset = SMC_CG_IND_START + config_regs->offset; 2869 if (offset < SMC_CG_IND_END) 2870 WREG32_SMC(offset, data); 2871 break; 2872 default: 2873 WREG32(config_regs->offset, data); 2874 break; 2875 } 2876 config_regs++; 2877 } 2878 return 0; 2879 } 2880 2881 static int si_initialize_hardware_cac_manager(struct amdgpu_device *adev) 2882 { 2883 struct ni_power_info *ni_pi = ni_get_pi(adev); 2884 struct si_power_info *si_pi = si_get_pi(adev); 2885 int ret; 2886 2887 if ((ni_pi->enable_cac == false) || 2888 (ni_pi->cac_configuration_required == false)) 2889 return 0; 2890 2891 ret = si_program_cac_config_registers(adev, si_pi->lcac_config); 2892 if (ret) 2893 return ret; 2894 ret = si_program_cac_config_registers(adev, si_pi->cac_override); 2895 if (ret) 2896 return ret; 2897 ret = si_program_cac_config_registers(adev, si_pi->cac_weights); 2898 if (ret) 2899 return ret; 2900 2901 return 0; 2902 } 2903 2904 static int si_enable_smc_cac(struct amdgpu_device *adev, 2905 struct amdgpu_ps *amdgpu_new_state, 2906 bool enable) 2907 { 2908 struct ni_power_info *ni_pi = ni_get_pi(adev); 2909 struct si_power_info *si_pi = si_get_pi(adev); 2910 PPSMC_Result smc_result; 2911 int ret = 0; 2912 2913 if (ni_pi->enable_cac) { 2914 if (enable) { 2915 if (!si_should_disable_uvd_powertune(adev, amdgpu_new_state)) { 2916 if (ni_pi->support_cac_long_term_average) { 2917 smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_CACLongTermAvgEnable); 2918 if (smc_result != PPSMC_Result_OK) 2919 ni_pi->support_cac_long_term_average = false; 2920 } 2921 2922 smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_EnableCac); 2923 if (smc_result != PPSMC_Result_OK) { 2924 ret = -EINVAL; 2925 ni_pi->cac_enabled = false; 2926 } else { 2927 ni_pi->cac_enabled = true; 2928 } 2929 2930 if (si_pi->enable_dte) { 2931 smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_EnableDTE); 2932 if (smc_result != PPSMC_Result_OK) 2933 ret = -EINVAL; 2934 } 2935 } 2936 } else if (ni_pi->cac_enabled) { 2937 if (si_pi->enable_dte) 2938 smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_DisableDTE); 2939 2940 smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_DisableCac); 2941 2942 ni_pi->cac_enabled = false; 2943 2944 if (ni_pi->support_cac_long_term_average) 2945 smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_CACLongTermAvgDisable); 2946 } 2947 } 2948 return ret; 2949 } 2950 2951 static int si_init_smc_spll_table(struct amdgpu_device *adev) 2952 { 2953 struct ni_power_info *ni_pi = ni_get_pi(adev); 2954 struct si_power_info *si_pi = si_get_pi(adev); 2955 SMC_SISLANDS_SPLL_DIV_TABLE *spll_table; 2956 SISLANDS_SMC_SCLK_VALUE sclk_params; 2957 u32 fb_div, p_div; 2958 u32 clk_s, clk_v; 2959 u32 sclk = 0; 2960 int ret = 0; 2961 u32 tmp; 2962 int i; 2963 2964 if (si_pi->spll_table_start == 0) 2965 return -EINVAL; 2966 2967 spll_table = kzalloc_obj(SMC_SISLANDS_SPLL_DIV_TABLE); 2968 if (spll_table == NULL) 2969 return -ENOMEM; 2970 2971 for (i = 0; i < 256; i++) { 2972 ret = si_calculate_sclk_params(adev, sclk, &sclk_params); 2973 if (ret) 2974 break; 2975 p_div = (sclk_params.vCG_SPLL_FUNC_CNTL & CG_SPLL_FUNC_CNTL__SPLL_PDIV_A_MASK) >> CG_SPLL_FUNC_CNTL__SPLL_PDIV_A__SHIFT; 2976 fb_div = (sclk_params.vCG_SPLL_FUNC_CNTL_3 & CG_SPLL_FUNC_CNTL_3__SPLL_FB_DIV_MASK) >> CG_SPLL_FUNC_CNTL_3__SPLL_FB_DIV__SHIFT; 2977 clk_s = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM & CG_SPLL_SPREAD_SPECTRUM__CLK_S_MASK) >> CG_SPLL_SPREAD_SPECTRUM__CLK_S__SHIFT; 2978 clk_v = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM_2 & CG_SPLL_SPREAD_SPECTRUM_2__CLK_V_MASK) >> CG_SPLL_SPREAD_SPECTRUM_2__CLK_V__SHIFT; 2979 2980 fb_div &= ~0x00001FFF; 2981 fb_div >>= 1; 2982 clk_v >>= 6; 2983 2984 if (p_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT)) 2985 ret = -EINVAL; 2986 if (fb_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT)) 2987 ret = -EINVAL; 2988 if (clk_s & ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT)) 2989 ret = -EINVAL; 2990 if (clk_v & ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT)) 2991 ret = -EINVAL; 2992 2993 if (ret) 2994 break; 2995 2996 tmp = ((fb_div << SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK) | 2997 ((p_div << SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK); 2998 spll_table->freq[i] = cpu_to_be32(tmp); 2999 3000 tmp = ((clk_v << SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK) | 3001 ((clk_s << SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK); 3002 spll_table->ss[i] = cpu_to_be32(tmp); 3003 3004 sclk += 512; 3005 } 3006 3007 3008 if (!ret) 3009 ret = amdgpu_si_copy_bytes_to_smc(adev, si_pi->spll_table_start, 3010 (u8 *)spll_table, 3011 sizeof(SMC_SISLANDS_SPLL_DIV_TABLE), 3012 si_pi->sram_end); 3013 3014 if (ret) 3015 ni_pi->enable_power_containment = false; 3016 3017 kfree(spll_table); 3018 3019 return ret; 3020 } 3021 3022 static u16 si_get_lower_of_leakage_and_vce_voltage(struct amdgpu_device *adev, 3023 u16 vce_voltage) 3024 { 3025 u16 highest_leakage = 0; 3026 struct si_power_info *si_pi = si_get_pi(adev); 3027 int i; 3028 3029 for (i = 0; i < si_pi->leakage_voltage.count; i++){ 3030 if (highest_leakage < si_pi->leakage_voltage.entries[i].voltage) 3031 highest_leakage = si_pi->leakage_voltage.entries[i].voltage; 3032 } 3033 3034 if (si_pi->leakage_voltage.count && (highest_leakage < vce_voltage)) 3035 return highest_leakage; 3036 3037 return vce_voltage; 3038 } 3039 3040 static int si_get_vce_clock_voltage(struct amdgpu_device *adev, 3041 u32 evclk, u32 ecclk, u16 *voltage) 3042 { 3043 u32 i; 3044 int ret = -EINVAL; 3045 struct amdgpu_vce_clock_voltage_dependency_table *table = 3046 &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table; 3047 3048 if (((evclk == 0) && (ecclk == 0)) || 3049 (table && (table->count == 0))) { 3050 *voltage = 0; 3051 return 0; 3052 } 3053 3054 for (i = 0; i < table->count; i++) { 3055 if ((evclk <= table->entries[i].evclk) && 3056 (ecclk <= table->entries[i].ecclk)) { 3057 *voltage = table->entries[i].v; 3058 ret = 0; 3059 break; 3060 } 3061 } 3062 3063 /* if no match return the highest voltage */ 3064 if (ret) 3065 *voltage = table->entries[table->count - 1].v; 3066 3067 *voltage = si_get_lower_of_leakage_and_vce_voltage(adev, *voltage); 3068 3069 return ret; 3070 } 3071 3072 static bool si_dpm_vblank_too_short(void *handle) 3073 { 3074 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3075 u32 vblank_time = adev->pm.pm_display_cfg.min_vblank_time; 3076 /* we never hit the non-gddr5 limit so disable it */ 3077 u32 switch_limit = adev->gmc.vram_type == AMDGPU_VRAM_TYPE_GDDR5 ? 450 : 0; 3078 3079 /* Disregard vblank time when there are no displays connected */ 3080 if (!adev->pm.pm_display_cfg.num_display) 3081 return false; 3082 3083 /* Consider zero vblank time too short and disable MCLK switching. 3084 * Note that the vblank time is set to maximum when no displays are attached, 3085 * so we'll still enable MCLK switching in that case. 3086 */ 3087 if (vblank_time == 0) 3088 return true; 3089 else if (vblank_time < switch_limit) 3090 return true; 3091 else 3092 return false; 3093 3094 } 3095 3096 static int ni_copy_and_switch_arb_sets(struct amdgpu_device *adev, 3097 u32 arb_freq_src, u32 arb_freq_dest) 3098 { 3099 u32 mc_arb_dram_timing; 3100 u32 mc_arb_dram_timing2; 3101 u32 burst_time; 3102 u32 mc_cg_config; 3103 3104 switch (arb_freq_src) { 3105 case MC_CG_ARB_FREQ_F0: 3106 mc_arb_dram_timing = RREG32(MC_ARB_DRAM_TIMING); 3107 mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2); 3108 burst_time = (RREG32(MC_ARB_BURST_TIME) & STATE0_MASK) >> STATE0_SHIFT; 3109 break; 3110 case MC_CG_ARB_FREQ_F1: 3111 mc_arb_dram_timing = RREG32(MC_ARB_DRAM_TIMING_1); 3112 mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2_1); 3113 burst_time = (RREG32(MC_ARB_BURST_TIME) & STATE1_MASK) >> STATE1_SHIFT; 3114 break; 3115 case MC_CG_ARB_FREQ_F2: 3116 mc_arb_dram_timing = RREG32(MC_ARB_DRAM_TIMING_2); 3117 mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2_2); 3118 burst_time = (RREG32(MC_ARB_BURST_TIME) & STATE2_MASK) >> STATE2_SHIFT; 3119 break; 3120 case MC_CG_ARB_FREQ_F3: 3121 mc_arb_dram_timing = RREG32(MC_ARB_DRAM_TIMING_3); 3122 mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2_3); 3123 burst_time = (RREG32(MC_ARB_BURST_TIME) & STATE3_MASK) >> STATE3_SHIFT; 3124 break; 3125 default: 3126 return -EINVAL; 3127 } 3128 3129 switch (arb_freq_dest) { 3130 case MC_CG_ARB_FREQ_F0: 3131 WREG32(MC_ARB_DRAM_TIMING, mc_arb_dram_timing); 3132 WREG32(MC_ARB_DRAM_TIMING2, mc_arb_dram_timing2); 3133 WREG32_P(MC_ARB_BURST_TIME, STATE0(burst_time), ~STATE0_MASK); 3134 break; 3135 case MC_CG_ARB_FREQ_F1: 3136 WREG32(MC_ARB_DRAM_TIMING_1, mc_arb_dram_timing); 3137 WREG32(MC_ARB_DRAM_TIMING2_1, mc_arb_dram_timing2); 3138 WREG32_P(MC_ARB_BURST_TIME, STATE1(burst_time), ~STATE1_MASK); 3139 break; 3140 case MC_CG_ARB_FREQ_F2: 3141 WREG32(MC_ARB_DRAM_TIMING_2, mc_arb_dram_timing); 3142 WREG32(MC_ARB_DRAM_TIMING2_2, mc_arb_dram_timing2); 3143 WREG32_P(MC_ARB_BURST_TIME, STATE2(burst_time), ~STATE2_MASK); 3144 break; 3145 case MC_CG_ARB_FREQ_F3: 3146 WREG32(MC_ARB_DRAM_TIMING_3, mc_arb_dram_timing); 3147 WREG32(MC_ARB_DRAM_TIMING2_3, mc_arb_dram_timing2); 3148 WREG32_P(MC_ARB_BURST_TIME, STATE3(burst_time), ~STATE3_MASK); 3149 break; 3150 default: 3151 return -EINVAL; 3152 } 3153 3154 mc_cg_config = RREG32(MC_CG_CONFIG) | 0x0000000F; 3155 WREG32(MC_CG_CONFIG, mc_cg_config); 3156 WREG32_P(MC_ARB_CG, CG_ARB_REQ(arb_freq_dest), ~CG_ARB_REQ_MASK); 3157 3158 return 0; 3159 } 3160 3161 static void ni_update_current_ps(struct amdgpu_device *adev, 3162 struct amdgpu_ps *rps) 3163 { 3164 struct si_ps *new_ps = si_get_ps(rps); 3165 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); 3166 struct ni_power_info *ni_pi = ni_get_pi(adev); 3167 3168 eg_pi->current_rps = *rps; 3169 ni_pi->current_ps = *new_ps; 3170 eg_pi->current_rps.ps_priv = &ni_pi->current_ps; 3171 adev->pm.dpm.current_ps = &eg_pi->current_rps; 3172 } 3173 3174 static void ni_update_requested_ps(struct amdgpu_device *adev, 3175 struct amdgpu_ps *rps) 3176 { 3177 struct si_ps *new_ps = si_get_ps(rps); 3178 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); 3179 struct ni_power_info *ni_pi = ni_get_pi(adev); 3180 3181 eg_pi->requested_rps = *rps; 3182 ni_pi->requested_ps = *new_ps; 3183 eg_pi->requested_rps.ps_priv = &ni_pi->requested_ps; 3184 adev->pm.dpm.requested_ps = &eg_pi->requested_rps; 3185 } 3186 3187 static void ni_set_uvd_clock_before_set_eng_clock(struct amdgpu_device *adev, 3188 struct amdgpu_ps *new_ps, 3189 struct amdgpu_ps *old_ps) 3190 { 3191 struct si_ps *new_state = si_get_ps(new_ps); 3192 struct si_ps *current_state = si_get_ps(old_ps); 3193 3194 if ((new_ps->vclk == old_ps->vclk) && 3195 (new_ps->dclk == old_ps->dclk)) 3196 return; 3197 3198 if (new_state->performance_levels[new_state->performance_level_count - 1].sclk >= 3199 current_state->performance_levels[current_state->performance_level_count - 1].sclk) 3200 return; 3201 3202 amdgpu_asic_set_uvd_clocks(adev, new_ps->vclk, new_ps->dclk); 3203 } 3204 3205 static void ni_set_uvd_clock_after_set_eng_clock(struct amdgpu_device *adev, 3206 struct amdgpu_ps *new_ps, 3207 struct amdgpu_ps *old_ps) 3208 { 3209 struct si_ps *new_state = si_get_ps(new_ps); 3210 struct si_ps *current_state = si_get_ps(old_ps); 3211 3212 if ((new_ps->vclk == old_ps->vclk) && 3213 (new_ps->dclk == old_ps->dclk)) 3214 return; 3215 3216 if (new_state->performance_levels[new_state->performance_level_count - 1].sclk < 3217 current_state->performance_levels[current_state->performance_level_count - 1].sclk) 3218 return; 3219 3220 amdgpu_asic_set_uvd_clocks(adev, new_ps->vclk, new_ps->dclk); 3221 } 3222 3223 static u16 btc_find_voltage(struct atom_voltage_table *table, u16 voltage) 3224 { 3225 unsigned int i; 3226 3227 for (i = 0; i < table->count; i++) 3228 if (voltage <= table->entries[i].value) 3229 return table->entries[i].value; 3230 3231 return table->entries[table->count - 1].value; 3232 } 3233 3234 static u32 btc_find_valid_clock(struct amdgpu_clock_array *clocks, 3235 u32 max_clock, u32 requested_clock) 3236 { 3237 unsigned int i; 3238 3239 if ((clocks == NULL) || (clocks->count == 0)) 3240 return (requested_clock < max_clock) ? requested_clock : max_clock; 3241 3242 for (i = 0; i < clocks->count; i++) { 3243 if (clocks->values[i] >= requested_clock) 3244 return (clocks->values[i] < max_clock) ? clocks->values[i] : max_clock; 3245 } 3246 3247 return (clocks->values[clocks->count - 1] < max_clock) ? 3248 clocks->values[clocks->count - 1] : max_clock; 3249 } 3250 3251 static u32 btc_get_valid_mclk(struct amdgpu_device *adev, 3252 u32 max_mclk, u32 requested_mclk) 3253 { 3254 return btc_find_valid_clock(&adev->pm.dpm.dyn_state.valid_mclk_values, 3255 max_mclk, requested_mclk); 3256 } 3257 3258 static u32 btc_get_valid_sclk(struct amdgpu_device *adev, 3259 u32 max_sclk, u32 requested_sclk) 3260 { 3261 return btc_find_valid_clock(&adev->pm.dpm.dyn_state.valid_sclk_values, 3262 max_sclk, requested_sclk); 3263 } 3264 3265 static void btc_get_max_clock_from_voltage_dependency_table(struct amdgpu_clock_voltage_dependency_table *table, 3266 u32 *max_clock) 3267 { 3268 u32 i, clock = 0; 3269 3270 if ((table == NULL) || (table->count == 0)) { 3271 *max_clock = clock; 3272 return; 3273 } 3274 3275 for (i = 0; i < table->count; i++) { 3276 if (clock < table->entries[i].clk) 3277 clock = table->entries[i].clk; 3278 } 3279 *max_clock = clock; 3280 } 3281 3282 static void btc_apply_voltage_dependency_rules(struct amdgpu_clock_voltage_dependency_table *table, 3283 u32 clock, u16 max_voltage, u16 *voltage) 3284 { 3285 u32 i; 3286 3287 if ((table == NULL) || (table->count == 0)) 3288 return; 3289 3290 for (i= 0; i < table->count; i++) { 3291 if (clock <= table->entries[i].clk) { 3292 if (*voltage < table->entries[i].v) 3293 *voltage = (u16)((table->entries[i].v < max_voltage) ? 3294 table->entries[i].v : max_voltage); 3295 return; 3296 } 3297 } 3298 3299 *voltage = (*voltage > max_voltage) ? *voltage : max_voltage; 3300 } 3301 3302 static void btc_adjust_clock_combinations(struct amdgpu_device *adev, 3303 const struct amdgpu_clock_and_voltage_limits *max_limits, 3304 struct rv7xx_pl *pl) 3305 { 3306 3307 if ((pl->mclk == 0) || (pl->sclk == 0)) 3308 return; 3309 3310 if (pl->mclk == pl->sclk) 3311 return; 3312 3313 if (pl->mclk > pl->sclk) { 3314 if (((pl->mclk + (pl->sclk - 1)) / pl->sclk) > adev->pm.dpm.dyn_state.mclk_sclk_ratio) 3315 pl->sclk = btc_get_valid_sclk(adev, 3316 max_limits->sclk, 3317 (pl->mclk + 3318 (adev->pm.dpm.dyn_state.mclk_sclk_ratio - 1)) / 3319 adev->pm.dpm.dyn_state.mclk_sclk_ratio); 3320 } else { 3321 if ((pl->sclk - pl->mclk) > adev->pm.dpm.dyn_state.sclk_mclk_delta) 3322 pl->mclk = btc_get_valid_mclk(adev, 3323 max_limits->mclk, 3324 pl->sclk - 3325 adev->pm.dpm.dyn_state.sclk_mclk_delta); 3326 } 3327 } 3328 3329 static void btc_apply_voltage_delta_rules(struct amdgpu_device *adev, 3330 u16 max_vddc, u16 max_vddci, 3331 u16 *vddc, u16 *vddci) 3332 { 3333 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); 3334 u16 new_voltage; 3335 3336 if ((0 == *vddc) || (0 == *vddci)) 3337 return; 3338 3339 if (*vddc > *vddci) { 3340 if ((*vddc - *vddci) > adev->pm.dpm.dyn_state.vddc_vddci_delta) { 3341 new_voltage = btc_find_voltage(&eg_pi->vddci_voltage_table, 3342 (*vddc - adev->pm.dpm.dyn_state.vddc_vddci_delta)); 3343 *vddci = (new_voltage < max_vddci) ? new_voltage : max_vddci; 3344 } 3345 } else { 3346 if ((*vddci - *vddc) > adev->pm.dpm.dyn_state.vddc_vddci_delta) { 3347 new_voltage = btc_find_voltage(&eg_pi->vddc_voltage_table, 3348 (*vddci - adev->pm.dpm.dyn_state.vddc_vddci_delta)); 3349 *vddc = (new_voltage < max_vddc) ? new_voltage : max_vddc; 3350 } 3351 } 3352 } 3353 3354 static void r600_calculate_u_and_p(u32 i, u32 r_c, u32 p_b, 3355 u32 *p, u32 *u) 3356 { 3357 u32 b_c = 0; 3358 u32 i_c; 3359 u32 tmp; 3360 3361 i_c = (i * r_c) / 100; 3362 tmp = i_c >> p_b; 3363 3364 while (tmp) { 3365 b_c++; 3366 tmp >>= 1; 3367 } 3368 3369 *u = (b_c + 1) / 2; 3370 *p = i_c / (1 << (2 * (*u))); 3371 } 3372 3373 static int r600_calculate_at(u32 t, u32 h, u32 fh, u32 fl, u32 *tl, u32 *th) 3374 { 3375 u32 k, a, ah, al; 3376 u32 t1; 3377 3378 if ((fl == 0) || (fh == 0) || (fl > fh)) 3379 return -EINVAL; 3380 3381 k = (100 * fh) / fl; 3382 t1 = (t * (k - 100)); 3383 a = (1000 * (100 * h + t1)) / (10000 + (t1 / 100)); 3384 a = (a + 5) / 10; 3385 ah = ((a * t) + 5000) / 10000; 3386 al = a - ah; 3387 3388 *th = t - ah; 3389 *tl = t + al; 3390 3391 return 0; 3392 } 3393 3394 static bool r600_is_uvd_state(u32 class, u32 class2) 3395 { 3396 if (class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE) 3397 return true; 3398 if (class & ATOM_PPLIB_CLASSIFICATION_HD2STATE) 3399 return true; 3400 if (class & ATOM_PPLIB_CLASSIFICATION_HDSTATE) 3401 return true; 3402 if (class & ATOM_PPLIB_CLASSIFICATION_SDSTATE) 3403 return true; 3404 if (class2 & ATOM_PPLIB_CLASSIFICATION2_MVC) 3405 return true; 3406 return false; 3407 } 3408 3409 static u8 rv770_get_memory_module_index(struct amdgpu_device *adev) 3410 { 3411 return (u8) ((RREG32(BIOS_SCRATCH_4) >> 16) & 0xff); 3412 } 3413 3414 static void rv770_get_max_vddc(struct amdgpu_device *adev) 3415 { 3416 struct rv7xx_power_info *pi = rv770_get_pi(adev); 3417 u16 vddc; 3418 3419 if (amdgpu_atombios_get_max_vddc(adev, 0, 0, &vddc)) 3420 pi->max_vddc = 0; 3421 else 3422 pi->max_vddc = vddc; 3423 } 3424 3425 static void rv770_get_engine_memory_ss(struct amdgpu_device *adev) 3426 { 3427 struct rv7xx_power_info *pi = rv770_get_pi(adev); 3428 struct amdgpu_atom_ss ss; 3429 3430 pi->sclk_ss = amdgpu_atombios_get_asic_ss_info(adev, &ss, 3431 ASIC_INTERNAL_ENGINE_SS, 0); 3432 pi->mclk_ss = amdgpu_atombios_get_asic_ss_info(adev, &ss, 3433 ASIC_INTERNAL_MEMORY_SS, 0); 3434 3435 if (pi->sclk_ss || pi->mclk_ss) 3436 pi->dynamic_ss = true; 3437 else 3438 pi->dynamic_ss = false; 3439 } 3440 3441 3442 static void si_apply_state_adjust_rules(struct amdgpu_device *adev, 3443 struct amdgpu_ps *rps) 3444 { 3445 const struct amd_pp_display_configuration *display_cfg = 3446 &adev->pm.pm_display_cfg; 3447 struct si_ps *ps = si_get_ps(rps); 3448 struct amdgpu_clock_and_voltage_limits *max_limits; 3449 bool disable_mclk_switching = false; 3450 bool disable_sclk_switching = false; 3451 u32 mclk, sclk; 3452 u16 vddc, vddci, min_vce_voltage = 0; 3453 u32 max_sclk_vddc, max_mclk_vddci, max_mclk_vddc; 3454 u32 max_sclk = 0, max_mclk = 0; 3455 u32 high_pixelclock_count = 0; 3456 int i; 3457 3458 if (adev->asic_type == CHIP_HAINAN) { 3459 if ((adev->pdev->revision == 0x81) || 3460 (adev->pdev->revision == 0xC3) || 3461 (adev->pdev->device == 0x6660) || 3462 (adev->pdev->device == 0x6664) || 3463 (adev->pdev->device == 0x6665) || 3464 (adev->pdev->device == 0x6667) || 3465 (adev->pdev->device == 0x666F)) { 3466 max_sclk = 75000; 3467 } 3468 if ((adev->pdev->revision == 0xC3) || 3469 (adev->pdev->device == 0x6665)) { 3470 max_sclk = 60000; 3471 max_mclk = 80000; 3472 } 3473 if ((adev->pdev->device == 0x666f) && 3474 (adev->pdev->revision == 0x00)) { 3475 max_sclk = 80000; 3476 max_mclk = 95000; 3477 } 3478 } else if (adev->asic_type == CHIP_OLAND) { 3479 if ((adev->pdev->revision == 0xC7) || 3480 (adev->pdev->revision == 0x80) || 3481 (adev->pdev->revision == 0x81) || 3482 (adev->pdev->revision == 0x83) || 3483 (adev->pdev->revision == 0x87 && 3484 adev->pdev->device != 0x6611) || 3485 (adev->pdev->device == 0x6604) || 3486 (adev->pdev->device == 0x6605)) { 3487 max_sclk = 75000; 3488 } else if (adev->pdev->revision == 0x87 && 3489 adev->pdev->device == 0x6611) { 3490 /* Radeon 430 and 520 */ 3491 max_sclk = 78000; 3492 } 3493 } 3494 3495 /* We define "high pixelclock" for SI as higher than necessary for 4K 30Hz. 3496 * For example, 4K 60Hz and 1080p 144Hz fall into this category. 3497 * Find number of such displays connected. 3498 */ 3499 for (i = 0; i < display_cfg->num_display; i++) { 3500 /* The array only contains active displays. */ 3501 if (display_cfg->displays[i].pixel_clock > 297000) 3502 high_pixelclock_count++; 3503 } 3504 3505 /* These are some ad-hoc fixes to some issues observed with SI GPUs. 3506 * They are necessary because we don't have something like dce_calcs 3507 * for these GPUs to calculate bandwidth requirements. 3508 */ 3509 if (high_pixelclock_count) { 3510 /* Work around flickering lines at the bottom edge 3511 * of the screen when using a single 4K 60Hz monitor. 3512 */ 3513 disable_mclk_switching = true; 3514 3515 /* On Oland, we observe some flickering when two 4K 60Hz 3516 * displays are connected, possibly because voltage is too low. 3517 * Raise the voltage by requiring a higher SCLK. 3518 * (Voltage cannot be adjusted independently without also SCLK.) 3519 */ 3520 if (high_pixelclock_count > 1 && adev->asic_type == CHIP_OLAND) 3521 disable_sclk_switching = true; 3522 } 3523 3524 if (rps->vce_active) { 3525 rps->evclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].evclk; 3526 rps->ecclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].ecclk; 3527 si_get_vce_clock_voltage(adev, rps->evclk, rps->ecclk, 3528 &min_vce_voltage); 3529 } else { 3530 rps->evclk = 0; 3531 rps->ecclk = 0; 3532 } 3533 3534 if ((adev->pm.pm_display_cfg.num_display > 1) || 3535 si_dpm_vblank_too_short(adev)) 3536 disable_mclk_switching = true; 3537 3538 if (rps->vclk || rps->dclk) { 3539 disable_mclk_switching = true; 3540 disable_sclk_switching = true; 3541 } 3542 3543 if (adev->pm.ac_power) 3544 max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac; 3545 else 3546 max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_dc; 3547 3548 for (i = ps->performance_level_count - 2; i >= 0; i--) { 3549 if (ps->performance_levels[i].vddc > ps->performance_levels[i+1].vddc) 3550 ps->performance_levels[i].vddc = ps->performance_levels[i+1].vddc; 3551 } 3552 if (adev->pm.ac_power == false) { 3553 for (i = 0; i < ps->performance_level_count; i++) { 3554 if (ps->performance_levels[i].mclk > max_limits->mclk) 3555 ps->performance_levels[i].mclk = max_limits->mclk; 3556 if (ps->performance_levels[i].sclk > max_limits->sclk) 3557 ps->performance_levels[i].sclk = max_limits->sclk; 3558 if (ps->performance_levels[i].vddc > max_limits->vddc) 3559 ps->performance_levels[i].vddc = max_limits->vddc; 3560 if (ps->performance_levels[i].vddci > max_limits->vddci) 3561 ps->performance_levels[i].vddci = max_limits->vddci; 3562 } 3563 } 3564 3565 /* limit clocks to max supported clocks based on voltage dependency tables */ 3566 btc_get_max_clock_from_voltage_dependency_table(&adev->pm.dpm.dyn_state.vddc_dependency_on_sclk, 3567 &max_sclk_vddc); 3568 btc_get_max_clock_from_voltage_dependency_table(&adev->pm.dpm.dyn_state.vddci_dependency_on_mclk, 3569 &max_mclk_vddci); 3570 btc_get_max_clock_from_voltage_dependency_table(&adev->pm.dpm.dyn_state.vddc_dependency_on_mclk, 3571 &max_mclk_vddc); 3572 3573 for (i = 0; i < ps->performance_level_count; i++) { 3574 if (max_sclk_vddc) { 3575 if (ps->performance_levels[i].sclk > max_sclk_vddc) 3576 ps->performance_levels[i].sclk = max_sclk_vddc; 3577 } 3578 if (max_mclk_vddci) { 3579 if (ps->performance_levels[i].mclk > max_mclk_vddci) 3580 ps->performance_levels[i].mclk = max_mclk_vddci; 3581 } 3582 if (max_mclk_vddc) { 3583 if (ps->performance_levels[i].mclk > max_mclk_vddc) 3584 ps->performance_levels[i].mclk = max_mclk_vddc; 3585 } 3586 if (max_mclk) { 3587 if (ps->performance_levels[i].mclk > max_mclk) 3588 ps->performance_levels[i].mclk = max_mclk; 3589 } 3590 if (max_sclk) { 3591 if (ps->performance_levels[i].sclk > max_sclk) 3592 ps->performance_levels[i].sclk = max_sclk; 3593 } 3594 } 3595 3596 /* XXX validate the min clocks required for display */ 3597 3598 if (disable_mclk_switching) { 3599 mclk = ps->performance_levels[ps->performance_level_count - 1].mclk; 3600 vddci = ps->performance_levels[ps->performance_level_count - 1].vddci; 3601 } else { 3602 mclk = ps->performance_levels[0].mclk; 3603 vddci = ps->performance_levels[0].vddci; 3604 } 3605 3606 if (disable_sclk_switching) { 3607 sclk = ps->performance_levels[ps->performance_level_count - 1].sclk; 3608 vddc = ps->performance_levels[ps->performance_level_count - 1].vddc; 3609 } else { 3610 sclk = ps->performance_levels[0].sclk; 3611 vddc = ps->performance_levels[0].vddc; 3612 } 3613 3614 if (rps->vce_active) { 3615 if (sclk < adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].sclk) 3616 sclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].sclk; 3617 if (mclk < adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].mclk) 3618 mclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].mclk; 3619 } 3620 3621 /* adjusted low state */ 3622 ps->performance_levels[0].sclk = sclk; 3623 ps->performance_levels[0].mclk = mclk; 3624 ps->performance_levels[0].vddc = vddc; 3625 ps->performance_levels[0].vddci = vddci; 3626 3627 if (disable_sclk_switching) { 3628 sclk = ps->performance_levels[0].sclk; 3629 for (i = 1; i < ps->performance_level_count; i++) { 3630 if (sclk < ps->performance_levels[i].sclk) 3631 sclk = ps->performance_levels[i].sclk; 3632 } 3633 for (i = 0; i < ps->performance_level_count; i++) { 3634 ps->performance_levels[i].sclk = sclk; 3635 ps->performance_levels[i].vddc = vddc; 3636 } 3637 } else { 3638 for (i = 1; i < ps->performance_level_count; i++) { 3639 if (ps->performance_levels[i].sclk < ps->performance_levels[i - 1].sclk) 3640 ps->performance_levels[i].sclk = ps->performance_levels[i - 1].sclk; 3641 if (ps->performance_levels[i].vddc < ps->performance_levels[i - 1].vddc) 3642 ps->performance_levels[i].vddc = ps->performance_levels[i - 1].vddc; 3643 } 3644 } 3645 3646 if (disable_mclk_switching) { 3647 mclk = ps->performance_levels[0].mclk; 3648 for (i = 1; i < ps->performance_level_count; i++) { 3649 if (mclk < ps->performance_levels[i].mclk) 3650 mclk = ps->performance_levels[i].mclk; 3651 } 3652 for (i = 0; i < ps->performance_level_count; i++) { 3653 ps->performance_levels[i].mclk = mclk; 3654 ps->performance_levels[i].vddci = vddci; 3655 } 3656 } else { 3657 for (i = 1; i < ps->performance_level_count; i++) { 3658 if (ps->performance_levels[i].mclk < ps->performance_levels[i - 1].mclk) 3659 ps->performance_levels[i].mclk = ps->performance_levels[i - 1].mclk; 3660 if (ps->performance_levels[i].vddci < ps->performance_levels[i - 1].vddci) 3661 ps->performance_levels[i].vddci = ps->performance_levels[i - 1].vddci; 3662 } 3663 } 3664 3665 for (i = 0; i < ps->performance_level_count; i++) 3666 btc_adjust_clock_combinations(adev, max_limits, 3667 &ps->performance_levels[i]); 3668 3669 for (i = 0; i < ps->performance_level_count; i++) { 3670 if (ps->performance_levels[i].vddc < min_vce_voltage) 3671 ps->performance_levels[i].vddc = min_vce_voltage; 3672 btc_apply_voltage_dependency_rules(&adev->pm.dpm.dyn_state.vddc_dependency_on_sclk, 3673 ps->performance_levels[i].sclk, 3674 max_limits->vddc, &ps->performance_levels[i].vddc); 3675 btc_apply_voltage_dependency_rules(&adev->pm.dpm.dyn_state.vddci_dependency_on_mclk, 3676 ps->performance_levels[i].mclk, 3677 max_limits->vddci, &ps->performance_levels[i].vddci); 3678 btc_apply_voltage_dependency_rules(&adev->pm.dpm.dyn_state.vddc_dependency_on_mclk, 3679 ps->performance_levels[i].mclk, 3680 max_limits->vddc, &ps->performance_levels[i].vddc); 3681 btc_apply_voltage_dependency_rules(&adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk, 3682 display_cfg->display_clk, 3683 max_limits->vddc, &ps->performance_levels[i].vddc); 3684 } 3685 3686 for (i = 0; i < ps->performance_level_count; i++) { 3687 btc_apply_voltage_delta_rules(adev, 3688 max_limits->vddc, max_limits->vddci, 3689 &ps->performance_levels[i].vddc, 3690 &ps->performance_levels[i].vddci); 3691 } 3692 3693 ps->dc_compatible = true; 3694 for (i = 0; i < ps->performance_level_count; i++) { 3695 if (ps->performance_levels[i].vddc > adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddc) 3696 ps->dc_compatible = false; 3697 } 3698 } 3699 3700 #if 0 3701 static int si_read_smc_soft_register(struct amdgpu_device *adev, 3702 u16 reg_offset, u32 *value) 3703 { 3704 struct si_power_info *si_pi = si_get_pi(adev); 3705 3706 return amdgpu_si_read_smc_sram_dword(adev, 3707 si_pi->soft_regs_start + reg_offset, value, 3708 si_pi->sram_end); 3709 } 3710 #endif 3711 3712 static int si_write_smc_soft_register(struct amdgpu_device *adev, 3713 u16 reg_offset, u32 value) 3714 { 3715 struct si_power_info *si_pi = si_get_pi(adev); 3716 3717 return amdgpu_si_write_smc_sram_dword(adev, 3718 si_pi->soft_regs_start + reg_offset, 3719 value, si_pi->sram_end); 3720 } 3721 3722 static bool si_is_special_1gb_platform(struct amdgpu_device *adev) 3723 { 3724 bool ret = false; 3725 u32 tmp, width, row, column, bank, density; 3726 bool is_memory_gddr5, is_special; 3727 3728 tmp = RREG32(MC_SEQ_MISC0); 3729 is_memory_gddr5 = (MC_SEQ_MISC0_GDDR5_VALUE == ((tmp & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT)); 3730 is_special = (MC_SEQ_MISC0_REV_ID_VALUE == ((tmp & MC_SEQ_MISC0_REV_ID_MASK) >> MC_SEQ_MISC0_REV_ID_SHIFT)) 3731 & (MC_SEQ_MISC0_VEN_ID_VALUE == ((tmp & MC_SEQ_MISC0_VEN_ID_MASK) >> MC_SEQ_MISC0_VEN_ID_SHIFT)); 3732 3733 WREG32(MC_SEQ_IO_DEBUG_INDEX, 0xb); 3734 width = ((RREG32(MC_SEQ_IO_DEBUG_DATA) >> 1) & 1) ? 16 : 32; 3735 3736 tmp = RREG32(mmMC_ARB_RAMCFG); 3737 row = ((tmp & MC_ARB_RAMCFG__NOOFROWS_MASK) >> MC_ARB_RAMCFG__NOOFROWS__SHIFT) + 10; 3738 column = ((tmp & MC_ARB_RAMCFG__NOOFCOLS_MASK) >> MC_ARB_RAMCFG__NOOFCOLS__SHIFT) + 8; 3739 bank = ((tmp & MC_ARB_RAMCFG__NOOFBANK_MASK) >> MC_ARB_RAMCFG__NOOFBANK__SHIFT) + 2; 3740 3741 density = (1 << (row + column - 20 + bank)) * width; 3742 3743 if ((adev->pdev->device == 0x6819) && 3744 is_memory_gddr5 && is_special && (density == 0x400)) 3745 ret = true; 3746 3747 return ret; 3748 } 3749 3750 static void si_get_leakage_vddc(struct amdgpu_device *adev) 3751 { 3752 struct si_power_info *si_pi = si_get_pi(adev); 3753 u16 vddc, count = 0; 3754 int i, ret; 3755 3756 for (i = 0; i < SISLANDS_MAX_LEAKAGE_COUNT; i++) { 3757 ret = amdgpu_atombios_get_leakage_vddc_based_on_leakage_idx(adev, &vddc, SISLANDS_LEAKAGE_INDEX0 + i); 3758 3759 if (!ret && (vddc > 0) && (vddc != (SISLANDS_LEAKAGE_INDEX0 + i))) { 3760 si_pi->leakage_voltage.entries[count].voltage = vddc; 3761 si_pi->leakage_voltage.entries[count].leakage_index = 3762 SISLANDS_LEAKAGE_INDEX0 + i; 3763 count++; 3764 } 3765 } 3766 si_pi->leakage_voltage.count = count; 3767 } 3768 3769 static int si_get_leakage_voltage_from_leakage_index(struct amdgpu_device *adev, 3770 u32 index, u16 *leakage_voltage) 3771 { 3772 struct si_power_info *si_pi = si_get_pi(adev); 3773 int i; 3774 3775 if (leakage_voltage == NULL) 3776 return -EINVAL; 3777 3778 if ((index & 0xff00) != 0xff00) 3779 return -EINVAL; 3780 3781 if ((index & 0xff) > SISLANDS_MAX_LEAKAGE_COUNT + 1) 3782 return -EINVAL; 3783 3784 if (index < SISLANDS_LEAKAGE_INDEX0) 3785 return -EINVAL; 3786 3787 for (i = 0; i < si_pi->leakage_voltage.count; i++) { 3788 if (si_pi->leakage_voltage.entries[i].leakage_index == index) { 3789 *leakage_voltage = si_pi->leakage_voltage.entries[i].voltage; 3790 return 0; 3791 } 3792 } 3793 return -EAGAIN; 3794 } 3795 3796 static void si_set_dpm_event_sources(struct amdgpu_device *adev, u32 sources) 3797 { 3798 struct rv7xx_power_info *pi = rv770_get_pi(adev); 3799 bool want_thermal_protection; 3800 enum si_dpm_event_src dpm_event_src; 3801 3802 switch (sources) { 3803 case 0: 3804 default: 3805 want_thermal_protection = false; 3806 break; 3807 case (1 << SI_DPM_AUTO_THROTTLE_SRC_THERMAL): 3808 want_thermal_protection = true; 3809 dpm_event_src = SI_DPM_EVENT_SRC_DIGITAL; 3810 break; 3811 case (1 << SI_DPM_AUTO_THROTTLE_SRC_EXTERNAL): 3812 want_thermal_protection = true; 3813 dpm_event_src = SI_DPM_EVENT_SRC_EXTERNAL; 3814 break; 3815 case ((1 << SI_DPM_AUTO_THROTTLE_SRC_EXTERNAL) | 3816 (1 << SI_DPM_AUTO_THROTTLE_SRC_THERMAL)): 3817 want_thermal_protection = true; 3818 dpm_event_src = SI_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL; 3819 break; 3820 } 3821 3822 if (want_thermal_protection) { 3823 WREG32_P(mmCG_THERMAL_CTRL, dpm_event_src << CG_THERMAL_CTRL__DPM_EVENT_SRC__SHIFT, ~CG_THERMAL_CTRL__DPM_EVENT_SRC_MASK); 3824 if (pi->thermal_protection) 3825 WREG32_P(mmGENERAL_PWRMGT, 0, ~GENERAL_PWRMGT__THERMAL_PROTECTION_DIS_MASK); 3826 } else { 3827 WREG32_P(mmGENERAL_PWRMGT, GENERAL_PWRMGT__THERMAL_PROTECTION_DIS_MASK, ~GENERAL_PWRMGT__THERMAL_PROTECTION_DIS_MASK); 3828 } 3829 } 3830 3831 static void si_enable_auto_throttle_source(struct amdgpu_device *adev, 3832 enum si_dpm_auto_throttle_src source, 3833 bool enable) 3834 { 3835 struct rv7xx_power_info *pi = rv770_get_pi(adev); 3836 3837 if (enable) { 3838 if (!(pi->active_auto_throttle_sources & (1 << source))) { 3839 pi->active_auto_throttle_sources |= 1 << source; 3840 si_set_dpm_event_sources(adev, pi->active_auto_throttle_sources); 3841 } 3842 } else { 3843 if (pi->active_auto_throttle_sources & (1 << source)) { 3844 pi->active_auto_throttle_sources &= ~(1 << source); 3845 si_set_dpm_event_sources(adev, pi->active_auto_throttle_sources); 3846 } 3847 } 3848 } 3849 3850 static void si_start_dpm(struct amdgpu_device *adev) 3851 { 3852 WREG32_P(mmGENERAL_PWRMGT, GENERAL_PWRMGT__GLOBAL_PWRMGT_EN_MASK, ~GENERAL_PWRMGT__GLOBAL_PWRMGT_EN_MASK); 3853 } 3854 3855 static void si_stop_dpm(struct amdgpu_device *adev) 3856 { 3857 WREG32_P(mmGENERAL_PWRMGT, 0, ~GENERAL_PWRMGT__GLOBAL_PWRMGT_EN_MASK); 3858 } 3859 3860 static void si_enable_sclk_control(struct amdgpu_device *adev, bool enable) 3861 { 3862 if (enable) 3863 WREG32_P(mmSCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_CNTL__SCLK_PWRMGT_OFF_MASK); 3864 else 3865 WREG32_P(mmSCLK_PWRMGT_CNTL, SCLK_PWRMGT_CNTL__SCLK_PWRMGT_OFF_MASK, ~SCLK_PWRMGT_CNTL__SCLK_PWRMGT_OFF_MASK); 3866 3867 } 3868 3869 #if 0 3870 static int si_notify_hardware_of_thermal_state(struct amdgpu_device *adev, 3871 u32 thermal_level) 3872 { 3873 PPSMC_Result ret; 3874 3875 if (thermal_level == 0) { 3876 ret = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_EnableThermalInterrupt); 3877 if (ret == PPSMC_Result_OK) 3878 return 0; 3879 else 3880 return -EINVAL; 3881 } 3882 return 0; 3883 } 3884 3885 static void si_notify_hardware_vpu_recovery_event(struct amdgpu_device *adev) 3886 { 3887 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_tdr_is_about_to_happen, true); 3888 } 3889 #endif 3890 3891 static void si_notify_hw_of_powersource(void *handle) 3892 { 3893 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3894 3895 /* 3896 * Check if the platform already manages the AC/DC switch via dedicated GPIO. 3897 * Otherwise SMU automatically notices DC, but needs to be notified of AC. 3898 */ 3899 if (adev->pm.ac_power && 3900 (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC)) 3901 amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_RunningOnAC); 3902 3903 /* Recompute clocks with updated max_limits. */ 3904 amdgpu_legacy_dpm_compute_clocks(adev); 3905 } 3906 3907 static PPSMC_Result si_send_msg_to_smc_with_parameter(struct amdgpu_device *adev, 3908 PPSMC_Msg msg, u32 parameter) 3909 { 3910 WREG32(mmSMC_SCRATCH0, parameter); 3911 return amdgpu_si_send_msg_to_smc(adev, msg); 3912 } 3913 3914 static int si_restrict_performance_levels_before_switch(struct amdgpu_device *adev) 3915 { 3916 if (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_NoForcedLevel) != PPSMC_Result_OK) 3917 return -EINVAL; 3918 3919 return (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetEnabledLevels, 1) == PPSMC_Result_OK) ? 3920 0 : -EINVAL; 3921 } 3922 3923 static int si_dpm_force_performance_level(void *handle, 3924 enum amd_dpm_forced_level level) 3925 { 3926 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3927 struct amdgpu_ps *rps = adev->pm.dpm.current_ps; 3928 struct si_ps *ps = si_get_ps(rps); 3929 u32 levels = ps->performance_level_count; 3930 3931 if (level == AMD_DPM_FORCED_LEVEL_HIGH) { 3932 if (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK) 3933 return -EINVAL; 3934 3935 if (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetForcedLevels, 1) != PPSMC_Result_OK) 3936 return -EINVAL; 3937 } else if (level == AMD_DPM_FORCED_LEVEL_LOW) { 3938 if (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK) 3939 return -EINVAL; 3940 3941 if (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetEnabledLevels, 1) != PPSMC_Result_OK) 3942 return -EINVAL; 3943 } else if (level == AMD_DPM_FORCED_LEVEL_AUTO) { 3944 if (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK) 3945 return -EINVAL; 3946 3947 if (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK) 3948 return -EINVAL; 3949 } 3950 3951 adev->pm.dpm.forced_level = level; 3952 3953 return 0; 3954 } 3955 3956 #if 0 3957 static int si_set_boot_state(struct amdgpu_device *adev) 3958 { 3959 return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_SwitchToInitialState) == PPSMC_Result_OK) ? 3960 0 : -EINVAL; 3961 } 3962 #endif 3963 3964 static int si_set_sw_state(struct amdgpu_device *adev) 3965 { 3966 return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_SwitchToSwState) == PPSMC_Result_OK) ? 3967 0 : -EINVAL; 3968 } 3969 3970 static int si_halt_smc(struct amdgpu_device *adev) 3971 { 3972 if (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_Halt) != PPSMC_Result_OK) 3973 return -EINVAL; 3974 3975 return (amdgpu_si_wait_for_smc_inactive(adev) == PPSMC_Result_OK) ? 3976 0 : -EINVAL; 3977 } 3978 3979 static int si_resume_smc(struct amdgpu_device *adev) 3980 { 3981 if (amdgpu_si_send_msg_to_smc(adev, PPSMC_FlushDataCache) != PPSMC_Result_OK) 3982 return -EINVAL; 3983 3984 return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_Resume) == PPSMC_Result_OK) ? 3985 0 : -EINVAL; 3986 } 3987 3988 static void si_dpm_start_smc(struct amdgpu_device *adev) 3989 { 3990 amdgpu_si_program_jump_on_start(adev); 3991 amdgpu_si_start_smc(adev); 3992 amdgpu_si_smc_clock(adev, true); 3993 } 3994 3995 static void si_dpm_stop_smc(struct amdgpu_device *adev) 3996 { 3997 amdgpu_si_reset_smc(adev); 3998 amdgpu_si_smc_clock(adev, false); 3999 } 4000 4001 static int si_process_firmware_header(struct amdgpu_device *adev) 4002 { 4003 struct si_power_info *si_pi = si_get_pi(adev); 4004 u32 tmp; 4005 int ret; 4006 4007 ret = amdgpu_si_read_smc_sram_dword(adev, 4008 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 4009 SISLANDS_SMC_FIRMWARE_HEADER_stateTable, 4010 &tmp, si_pi->sram_end); 4011 if (ret) 4012 return ret; 4013 4014 si_pi->state_table_start = tmp; 4015 4016 ret = amdgpu_si_read_smc_sram_dword(adev, 4017 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 4018 SISLANDS_SMC_FIRMWARE_HEADER_softRegisters, 4019 &tmp, si_pi->sram_end); 4020 if (ret) 4021 return ret; 4022 4023 si_pi->soft_regs_start = tmp; 4024 4025 ret = amdgpu_si_read_smc_sram_dword(adev, 4026 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 4027 SISLANDS_SMC_FIRMWARE_HEADER_mcRegisterTable, 4028 &tmp, si_pi->sram_end); 4029 if (ret) 4030 return ret; 4031 4032 si_pi->mc_reg_table_start = tmp; 4033 4034 ret = amdgpu_si_read_smc_sram_dword(adev, 4035 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 4036 SISLANDS_SMC_FIRMWARE_HEADER_fanTable, 4037 &tmp, si_pi->sram_end); 4038 if (ret) 4039 return ret; 4040 4041 si_pi->fan_table_start = tmp; 4042 4043 ret = amdgpu_si_read_smc_sram_dword(adev, 4044 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 4045 SISLANDS_SMC_FIRMWARE_HEADER_mcArbDramAutoRefreshTable, 4046 &tmp, si_pi->sram_end); 4047 if (ret) 4048 return ret; 4049 4050 si_pi->arb_table_start = tmp; 4051 4052 ret = amdgpu_si_read_smc_sram_dword(adev, 4053 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 4054 SISLANDS_SMC_FIRMWARE_HEADER_CacConfigTable, 4055 &tmp, si_pi->sram_end); 4056 if (ret) 4057 return ret; 4058 4059 si_pi->cac_table_start = tmp; 4060 4061 ret = amdgpu_si_read_smc_sram_dword(adev, 4062 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 4063 SISLANDS_SMC_FIRMWARE_HEADER_DteConfiguration, 4064 &tmp, si_pi->sram_end); 4065 if (ret) 4066 return ret; 4067 4068 si_pi->dte_table_start = tmp; 4069 4070 ret = amdgpu_si_read_smc_sram_dword(adev, 4071 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 4072 SISLANDS_SMC_FIRMWARE_HEADER_spllTable, 4073 &tmp, si_pi->sram_end); 4074 if (ret) 4075 return ret; 4076 4077 si_pi->spll_table_start = tmp; 4078 4079 ret = amdgpu_si_read_smc_sram_dword(adev, 4080 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 4081 SISLANDS_SMC_FIRMWARE_HEADER_PAPMParameters, 4082 &tmp, si_pi->sram_end); 4083 if (ret) 4084 return ret; 4085 4086 si_pi->papm_cfg_table_start = tmp; 4087 4088 return ret; 4089 } 4090 4091 static void si_read_clock_registers(struct amdgpu_device *adev) 4092 { 4093 struct si_power_info *si_pi = si_get_pi(adev); 4094 4095 si_pi->clock_registers.cg_spll_func_cntl = RREG32(mmCG_SPLL_FUNC_CNTL); 4096 si_pi->clock_registers.cg_spll_func_cntl_2 = RREG32(mmCG_SPLL_FUNC_CNTL_2); 4097 si_pi->clock_registers.cg_spll_func_cntl_3 = RREG32(mmCG_SPLL_FUNC_CNTL_3); 4098 si_pi->clock_registers.cg_spll_func_cntl_4 = RREG32(mmCG_SPLL_FUNC_CNTL_4); 4099 si_pi->clock_registers.cg_spll_spread_spectrum = RREG32(mmCG_SPLL_SPREAD_SPECTRUM); 4100 si_pi->clock_registers.cg_spll_spread_spectrum_2 = RREG32(mmCG_SPLL_SPREAD_SPECTRUM_2); 4101 si_pi->clock_registers.dll_cntl = RREG32(DLL_CNTL); 4102 si_pi->clock_registers.mclk_pwrmgt_cntl = RREG32(MCLK_PWRMGT_CNTL); 4103 si_pi->clock_registers.mpll_ad_func_cntl = RREG32(MPLL_AD_FUNC_CNTL); 4104 si_pi->clock_registers.mpll_dq_func_cntl = RREG32(MPLL_DQ_FUNC_CNTL); 4105 si_pi->clock_registers.mpll_func_cntl = RREG32(MPLL_FUNC_CNTL); 4106 si_pi->clock_registers.mpll_func_cntl_1 = RREG32(MPLL_FUNC_CNTL_1); 4107 si_pi->clock_registers.mpll_func_cntl_2 = RREG32(MPLL_FUNC_CNTL_2); 4108 si_pi->clock_registers.mpll_ss1 = RREG32(MPLL_SS1); 4109 si_pi->clock_registers.mpll_ss2 = RREG32(MPLL_SS2); 4110 } 4111 4112 static void si_enable_thermal_protection(struct amdgpu_device *adev, 4113 bool enable) 4114 { 4115 if (enable) 4116 WREG32_P(mmGENERAL_PWRMGT, 0, ~GENERAL_PWRMGT__THERMAL_PROTECTION_DIS_MASK); 4117 else 4118 WREG32_P(mmGENERAL_PWRMGT, GENERAL_PWRMGT__THERMAL_PROTECTION_DIS_MASK, ~GENERAL_PWRMGT__THERMAL_PROTECTION_DIS_MASK); 4119 } 4120 4121 static void si_enable_acpi_power_management(struct amdgpu_device *adev) 4122 { 4123 WREG32_P(mmGENERAL_PWRMGT, GENERAL_PWRMGT__STATIC_PM_EN_MASK, ~GENERAL_PWRMGT__STATIC_PM_EN_MASK); 4124 } 4125 4126 #if 0 4127 static int si_enter_ulp_state(struct amdgpu_device *adev) 4128 { 4129 WREG32(SMC_MESSAGE_0, PPSMC_MSG_SwitchToMinimumPower); 4130 4131 udelay(25000); 4132 4133 return 0; 4134 } 4135 4136 static int si_exit_ulp_state(struct amdgpu_device *adev) 4137 { 4138 int i; 4139 4140 WREG32(SMC_MESSAGE_0, PPSMC_MSG_ResumeFromMinimumPower); 4141 4142 udelay(7000); 4143 4144 for (i = 0; i < adev->usec_timeout; i++) { 4145 if (RREG32(SMC_RESP_0) == 1) 4146 break; 4147 udelay(1000); 4148 } 4149 4150 return 0; 4151 } 4152 #endif 4153 4154 static int si_notify_smc_display_change(struct amdgpu_device *adev, 4155 bool has_display) 4156 { 4157 PPSMC_Msg msg = has_display ? 4158 PPSMC_MSG_HasDisplay : PPSMC_MSG_NoDisplay; 4159 4160 return (amdgpu_si_send_msg_to_smc(adev, msg) == PPSMC_Result_OK) ? 4161 0 : -EINVAL; 4162 } 4163 4164 static void si_program_response_times(struct amdgpu_device *adev) 4165 { 4166 u32 voltage_response_time, acpi_delay_time, vbi_time_out; 4167 u32 vddc_dly, acpi_dly, vbi_dly; 4168 u32 reference_clock; 4169 4170 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_mvdd_chg_time, 1); 4171 4172 voltage_response_time = (u32)adev->pm.dpm.voltage_response_time; 4173 4174 if (voltage_response_time == 0) 4175 voltage_response_time = 1000; 4176 4177 acpi_delay_time = 15000; 4178 vbi_time_out = 100000; 4179 4180 reference_clock = amdgpu_asic_get_xclk(adev); 4181 4182 vddc_dly = (voltage_response_time * reference_clock) / 100; 4183 acpi_dly = (acpi_delay_time * reference_clock) / 100; 4184 vbi_dly = (vbi_time_out * reference_clock) / 100; 4185 4186 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_delay_vreg, vddc_dly); 4187 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_delay_acpi, acpi_dly); 4188 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_mclk_chg_timeout, vbi_dly); 4189 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_mc_block_delay, 0xAA); 4190 } 4191 4192 static void si_program_ds_registers(struct amdgpu_device *adev) 4193 { 4194 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); 4195 u32 tmp; 4196 4197 /* DEEP_SLEEP_CLK_SEL field should be 0x10 on tahiti A0 */ 4198 if (adev->asic_type == CHIP_TAHITI && adev->rev_id == 0x0) 4199 tmp = 0x10; 4200 else 4201 tmp = 0x1; 4202 4203 if (eg_pi->sclk_deep_sleep) { 4204 WREG32_P(mmMISC_CLK_CNTL, (tmp << MISC_CLK_CNTL__DEEP_SLEEP_CLK_SEL__SHIFT), ~MISC_CLK_CNTL__DEEP_SLEEP_CLK_SEL_MASK); 4205 WREG32_P(mmCG_SPLL_AUTOSCALE_CNTL, CG_SPLL_AUTOSCALE_CNTL__AUTOSCALE_ON_SS_CLEAR_MASK, 4206 ~CG_SPLL_AUTOSCALE_CNTL__AUTOSCALE_ON_SS_CLEAR_MASK); 4207 } 4208 } 4209 4210 static void si_program_display_gap(struct amdgpu_device *adev) 4211 { 4212 const struct amd_pp_display_configuration *cfg = &adev->pm.pm_display_cfg; 4213 u32 tmp, pipe; 4214 4215 tmp = RREG32(mmCG_DISPLAY_GAP_CNTL) & ~(CG_DISPLAY_GAP_CNTL__DISP1_GAP_MASK | CG_DISPLAY_GAP_CNTL__DISP2_GAP_MASK); 4216 if (cfg->num_display > 0) 4217 tmp |= R600_PM_DISPLAY_GAP_VBLANK_OR_WM << CG_DISPLAY_GAP_CNTL__DISP1_GAP__SHIFT; 4218 else 4219 tmp |= R600_PM_DISPLAY_GAP_IGNORE << CG_DISPLAY_GAP_CNTL__DISP1_GAP__SHIFT; 4220 4221 if (cfg->num_display > 1) 4222 tmp |= R600_PM_DISPLAY_GAP_VBLANK_OR_WM << CG_DISPLAY_GAP_CNTL__DISP2_GAP__SHIFT; 4223 else 4224 tmp |= R600_PM_DISPLAY_GAP_IGNORE << CG_DISPLAY_GAP_CNTL__DISP2_GAP__SHIFT; 4225 4226 WREG32(mmCG_DISPLAY_GAP_CNTL, tmp); 4227 4228 tmp = RREG32(DCCG_DISP_SLOW_SELECT_REG); 4229 pipe = (tmp & DCCG_DISP1_SLOW_SELECT_MASK) >> DCCG_DISP1_SLOW_SELECT_SHIFT; 4230 4231 if (cfg->num_display > 0 && pipe != cfg->crtc_index) { 4232 pipe = cfg->crtc_index; 4233 4234 tmp &= ~DCCG_DISP1_SLOW_SELECT_MASK; 4235 tmp |= DCCG_DISP1_SLOW_SELECT(pipe); 4236 WREG32(DCCG_DISP_SLOW_SELECT_REG, tmp); 4237 } 4238 4239 /* Setting this to false forces the performance state to low if the crtcs are disabled. 4240 * This can be a problem on PowerXpress systems or if you want to use the card 4241 * for offscreen rendering or compute if there are no crtcs enabled. 4242 */ 4243 si_notify_smc_display_change(adev, cfg->num_display > 0); 4244 } 4245 4246 static void si_enable_spread_spectrum(struct amdgpu_device *adev, bool enable) 4247 { 4248 struct rv7xx_power_info *pi = rv770_get_pi(adev); 4249 4250 if (enable) { 4251 if (pi->sclk_ss) 4252 WREG32_P(mmGENERAL_PWRMGT, GENERAL_PWRMGT__DYN_SPREAD_SPECTRUM_EN_MASK, ~GENERAL_PWRMGT__DYN_SPREAD_SPECTRUM_EN_MASK); 4253 } else { 4254 WREG32_P(mmCG_SPLL_SPREAD_SPECTRUM, 0, ~CG_SPLL_SPREAD_SPECTRUM__SSEN_MASK); 4255 WREG32_P(mmGENERAL_PWRMGT, 0, ~GENERAL_PWRMGT__DYN_SPREAD_SPECTRUM_EN_MASK); 4256 } 4257 } 4258 4259 static void si_setup_bsp(struct amdgpu_device *adev) 4260 { 4261 struct rv7xx_power_info *pi = rv770_get_pi(adev); 4262 u32 xclk = amdgpu_asic_get_xclk(adev); 4263 4264 r600_calculate_u_and_p(pi->asi, 4265 xclk, 4266 16, 4267 &pi->bsp, 4268 &pi->bsu); 4269 4270 r600_calculate_u_and_p(pi->pasi, 4271 xclk, 4272 16, 4273 &pi->pbsp, 4274 &pi->pbsu); 4275 4276 4277 pi->dsp = (pi->bsp << CG_BSP__BSP__SHIFT) | (pi->bsu << CG_BSP__BSU__SHIFT); 4278 pi->psp = (pi->pbsp << CG_BSP__BSP__SHIFT) | (pi->pbsu << CG_BSP__BSU__SHIFT); 4279 4280 WREG32(mmCG_BSP, pi->dsp); 4281 } 4282 4283 static void si_program_git(struct amdgpu_device *adev) 4284 { 4285 WREG32_P(mmCG_GIT, R600_GICST_DFLT << CG_GIT__CG_GICST__SHIFT, ~CG_GIT__CG_GICST_MASK); 4286 } 4287 4288 static void si_program_tp(struct amdgpu_device *adev) 4289 { 4290 int i; 4291 enum r600_td td = R600_TD_DFLT; 4292 4293 for (i = 0; i < R600_PM_NUMBER_OF_TC; i++) 4294 WREG32(mmCG_FFCT_0 + i, (r600_utc[i] << CG_FFCT_0__UTC_0__SHIFT | r600_dtc[i] << CG_FFCT_0__DTC_0__SHIFT)); 4295 4296 if (td == R600_TD_AUTO) 4297 WREG32_P(mmSCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_CNTL__FIR_FORCE_TREND_SEL_MASK); 4298 else 4299 WREG32_P(mmSCLK_PWRMGT_CNTL, SCLK_PWRMGT_CNTL__FIR_FORCE_TREND_SEL_MASK, ~SCLK_PWRMGT_CNTL__FIR_FORCE_TREND_SEL_MASK); 4300 4301 if (td == R600_TD_UP) 4302 WREG32_P(mmSCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_CNTL__FIR_TREND_MODE_MASK); 4303 4304 if (td == R600_TD_DOWN) 4305 WREG32_P(mmSCLK_PWRMGT_CNTL, SCLK_PWRMGT_CNTL__FIR_TREND_MODE_MASK, ~SCLK_PWRMGT_CNTL__FIR_TREND_MODE_MASK); 4306 } 4307 4308 static void si_program_tpp(struct amdgpu_device *adev) 4309 { 4310 WREG32(mmCG_TPC, R600_TPC_DFLT); 4311 } 4312 4313 static void si_program_sstp(struct amdgpu_device *adev) 4314 { 4315 WREG32(mmCG_SSP, (R600_SSTU_DFLT << CG_SSP__SSTU__SHIFT| R600_SST_DFLT << CG_SSP__SST__SHIFT)); 4316 } 4317 4318 static void si_enable_display_gap(struct amdgpu_device *adev) 4319 { 4320 u32 tmp = RREG32(mmCG_DISPLAY_GAP_CNTL); 4321 4322 tmp &= ~(CG_DISPLAY_GAP_CNTL__DISP1_GAP_MASK | CG_DISPLAY_GAP_CNTL__DISP2_GAP_MASK); 4323 tmp |= (R600_PM_DISPLAY_GAP_IGNORE << CG_DISPLAY_GAP_CNTL__DISP1_GAP__SHIFT | 4324 R600_PM_DISPLAY_GAP_IGNORE << CG_DISPLAY_GAP_CNTL__DISP2_GAP__SHIFT); 4325 4326 tmp &= ~(CG_DISPLAY_GAP_CNTL__DISP1_GAP_MCHG_MASK | CG_DISPLAY_GAP_CNTL__DISP2_GAP_MCHG_MASK); 4327 tmp |= (R600_PM_DISPLAY_GAP_VBLANK << CG_DISPLAY_GAP_CNTL__DISP1_GAP_MCHG__SHIFT | 4328 R600_PM_DISPLAY_GAP_IGNORE << CG_DISPLAY_GAP_CNTL__DISP2_GAP_MCHG__SHIFT); 4329 WREG32(mmCG_DISPLAY_GAP_CNTL, tmp); 4330 } 4331 4332 static void si_program_vc(struct amdgpu_device *adev) 4333 { 4334 struct rv7xx_power_info *pi = rv770_get_pi(adev); 4335 4336 WREG32(mmCG_FTV, pi->vrc); 4337 } 4338 4339 static void si_clear_vc(struct amdgpu_device *adev) 4340 { 4341 WREG32(mmCG_FTV, 0); 4342 } 4343 4344 static u8 si_get_ddr3_mclk_frequency_ratio(u32 memory_clock) 4345 { 4346 u8 mc_para_index; 4347 4348 if (memory_clock < 10000) 4349 mc_para_index = 0; 4350 else if (memory_clock >= 80000) 4351 mc_para_index = 0x0f; 4352 else 4353 mc_para_index = (u8)((memory_clock - 10000) / 5000 + 1); 4354 return mc_para_index; 4355 } 4356 4357 static u8 si_get_mclk_frequency_ratio(u32 memory_clock, bool strobe_mode) 4358 { 4359 u8 mc_para_index; 4360 4361 if (strobe_mode) { 4362 if (memory_clock < 12500) 4363 mc_para_index = 0x00; 4364 else if (memory_clock > 47500) 4365 mc_para_index = 0x0f; 4366 else 4367 mc_para_index = (u8)((memory_clock - 10000) / 2500); 4368 } else { 4369 if (memory_clock < 65000) 4370 mc_para_index = 0x00; 4371 else if (memory_clock > 135000) 4372 mc_para_index = 0x0f; 4373 else 4374 mc_para_index = (u8)((memory_clock - 60000) / 5000); 4375 } 4376 return mc_para_index; 4377 } 4378 4379 static u8 si_get_strobe_mode_settings(struct amdgpu_device *adev, u32 mclk) 4380 { 4381 struct rv7xx_power_info *pi = rv770_get_pi(adev); 4382 bool strobe_mode = false; 4383 u8 result = 0; 4384 4385 if (mclk <= pi->mclk_strobe_mode_threshold) 4386 strobe_mode = true; 4387 4388 if (adev->gmc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) 4389 result = si_get_mclk_frequency_ratio(mclk, strobe_mode); 4390 else 4391 result = si_get_ddr3_mclk_frequency_ratio(mclk); 4392 4393 if (strobe_mode) 4394 result |= SISLANDS_SMC_STROBE_ENABLE; 4395 4396 return result; 4397 } 4398 4399 static int si_upload_firmware(struct amdgpu_device *adev) 4400 { 4401 struct si_power_info *si_pi = si_get_pi(adev); 4402 4403 amdgpu_si_reset_smc(adev); 4404 amdgpu_si_smc_clock(adev, false); 4405 4406 return amdgpu_si_load_smc_ucode(adev, si_pi->sram_end); 4407 } 4408 4409 static bool si_validate_phase_shedding_tables(struct amdgpu_device *adev, 4410 const struct atom_voltage_table *table, 4411 const struct amdgpu_phase_shedding_limits_table *limits) 4412 { 4413 u32 data, num_bits, num_levels; 4414 4415 if ((table == NULL) || (limits == NULL)) 4416 return false; 4417 4418 data = table->mask_low; 4419 4420 num_bits = hweight32(data); 4421 4422 if (num_bits == 0) 4423 return false; 4424 4425 num_levels = (1 << num_bits); 4426 4427 if (table->count != num_levels) 4428 return false; 4429 4430 if (limits->count != (num_levels - 1)) 4431 return false; 4432 4433 return true; 4434 } 4435 4436 static void si_trim_voltage_table_to_fit_state_table(struct amdgpu_device *adev, 4437 u32 max_voltage_steps, 4438 struct atom_voltage_table *voltage_table) 4439 { 4440 unsigned int i, diff; 4441 4442 if (voltage_table->count <= max_voltage_steps) 4443 return; 4444 4445 diff = voltage_table->count - max_voltage_steps; 4446 4447 for (i= 0; i < max_voltage_steps; i++) 4448 voltage_table->entries[i] = voltage_table->entries[i + diff]; 4449 4450 voltage_table->count = max_voltage_steps; 4451 } 4452 4453 static int si_get_svi2_voltage_table(struct amdgpu_device *adev, 4454 struct amdgpu_clock_voltage_dependency_table *voltage_dependency_table, 4455 struct atom_voltage_table *voltage_table) 4456 { 4457 u32 i; 4458 4459 if (voltage_dependency_table == NULL) 4460 return -EINVAL; 4461 4462 voltage_table->mask_low = 0; 4463 voltage_table->phase_delay = 0; 4464 4465 voltage_table->count = voltage_dependency_table->count; 4466 for (i = 0; i < voltage_table->count; i++) { 4467 voltage_table->entries[i].value = voltage_dependency_table->entries[i].v; 4468 voltage_table->entries[i].smio_low = 0; 4469 } 4470 4471 return 0; 4472 } 4473 4474 static int si_construct_voltage_tables(struct amdgpu_device *adev) 4475 { 4476 struct rv7xx_power_info *pi = rv770_get_pi(adev); 4477 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); 4478 struct si_power_info *si_pi = si_get_pi(adev); 4479 int ret; 4480 4481 if (pi->voltage_control) { 4482 ret = amdgpu_atombios_get_voltage_table(adev, VOLTAGE_TYPE_VDDC, 4483 VOLTAGE_OBJ_GPIO_LUT, &eg_pi->vddc_voltage_table); 4484 if (ret) 4485 return ret; 4486 4487 if (eg_pi->vddc_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS) 4488 si_trim_voltage_table_to_fit_state_table(adev, 4489 SISLANDS_MAX_NO_VREG_STEPS, 4490 &eg_pi->vddc_voltage_table); 4491 } else if (si_pi->voltage_control_svi2) { 4492 ret = si_get_svi2_voltage_table(adev, 4493 &adev->pm.dpm.dyn_state.vddc_dependency_on_mclk, 4494 &eg_pi->vddc_voltage_table); 4495 if (ret) 4496 return ret; 4497 } else { 4498 return -EINVAL; 4499 } 4500 4501 if (eg_pi->vddci_control) { 4502 ret = amdgpu_atombios_get_voltage_table(adev, VOLTAGE_TYPE_VDDCI, 4503 VOLTAGE_OBJ_GPIO_LUT, &eg_pi->vddci_voltage_table); 4504 if (ret) 4505 return ret; 4506 4507 if (eg_pi->vddci_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS) 4508 si_trim_voltage_table_to_fit_state_table(adev, 4509 SISLANDS_MAX_NO_VREG_STEPS, 4510 &eg_pi->vddci_voltage_table); 4511 } 4512 if (si_pi->vddci_control_svi2) { 4513 ret = si_get_svi2_voltage_table(adev, 4514 &adev->pm.dpm.dyn_state.vddci_dependency_on_mclk, 4515 &eg_pi->vddci_voltage_table); 4516 if (ret) 4517 return ret; 4518 } 4519 4520 if (pi->mvdd_control) { 4521 ret = amdgpu_atombios_get_voltage_table(adev, VOLTAGE_TYPE_MVDDC, 4522 VOLTAGE_OBJ_GPIO_LUT, &si_pi->mvdd_voltage_table); 4523 4524 if (ret) { 4525 pi->mvdd_control = false; 4526 return ret; 4527 } 4528 4529 if (si_pi->mvdd_voltage_table.count == 0) { 4530 pi->mvdd_control = false; 4531 return -EINVAL; 4532 } 4533 4534 if (si_pi->mvdd_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS) 4535 si_trim_voltage_table_to_fit_state_table(adev, 4536 SISLANDS_MAX_NO_VREG_STEPS, 4537 &si_pi->mvdd_voltage_table); 4538 } 4539 4540 if (si_pi->vddc_phase_shed_control) { 4541 ret = amdgpu_atombios_get_voltage_table(adev, VOLTAGE_TYPE_VDDC, 4542 VOLTAGE_OBJ_PHASE_LUT, &si_pi->vddc_phase_shed_table); 4543 if (ret) 4544 si_pi->vddc_phase_shed_control = false; 4545 4546 if ((si_pi->vddc_phase_shed_table.count == 0) || 4547 (si_pi->vddc_phase_shed_table.count > SISLANDS_MAX_NO_VREG_STEPS)) 4548 si_pi->vddc_phase_shed_control = false; 4549 } 4550 4551 return 0; 4552 } 4553 4554 static void si_populate_smc_voltage_table(struct amdgpu_device *adev, 4555 const struct atom_voltage_table *voltage_table, 4556 SISLANDS_SMC_STATETABLE *table) 4557 { 4558 unsigned int i; 4559 4560 for (i = 0; i < voltage_table->count; i++) 4561 table->lowSMIO[i] |= cpu_to_be32(voltage_table->entries[i].smio_low); 4562 } 4563 4564 static int si_populate_smc_voltage_tables(struct amdgpu_device *adev, 4565 SISLANDS_SMC_STATETABLE *table) 4566 { 4567 struct rv7xx_power_info *pi = rv770_get_pi(adev); 4568 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); 4569 struct si_power_info *si_pi = si_get_pi(adev); 4570 u8 i; 4571 4572 if (si_pi->voltage_control_svi2) { 4573 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svc, 4574 si_pi->svc_gpio_id); 4575 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svd, 4576 si_pi->svd_gpio_id); 4577 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_svi_rework_plat_type, 4578 2); 4579 } else { 4580 if (eg_pi->vddc_voltage_table.count) { 4581 si_populate_smc_voltage_table(adev, &eg_pi->vddc_voltage_table, table); 4582 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC] = 4583 cpu_to_be32(eg_pi->vddc_voltage_table.mask_low); 4584 4585 for (i = 0; i < eg_pi->vddc_voltage_table.count; i++) { 4586 if (pi->max_vddc_in_table <= eg_pi->vddc_voltage_table.entries[i].value) { 4587 table->maxVDDCIndexInPPTable = i; 4588 break; 4589 } 4590 } 4591 } 4592 4593 if (eg_pi->vddci_voltage_table.count) { 4594 si_populate_smc_voltage_table(adev, &eg_pi->vddci_voltage_table, table); 4595 4596 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDCI] = 4597 cpu_to_be32(eg_pi->vddci_voltage_table.mask_low); 4598 } 4599 4600 4601 if (si_pi->mvdd_voltage_table.count) { 4602 si_populate_smc_voltage_table(adev, &si_pi->mvdd_voltage_table, table); 4603 4604 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_MVDD] = 4605 cpu_to_be32(si_pi->mvdd_voltage_table.mask_low); 4606 } 4607 4608 if (si_pi->vddc_phase_shed_control) { 4609 if (si_validate_phase_shedding_tables(adev, &si_pi->vddc_phase_shed_table, 4610 &adev->pm.dpm.dyn_state.phase_shedding_limits_table)) { 4611 si_populate_smc_voltage_table(adev, &si_pi->vddc_phase_shed_table, table); 4612 4613 table->phaseMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC_PHASE_SHEDDING] = 4614 cpu_to_be32(si_pi->vddc_phase_shed_table.mask_low); 4615 4616 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_phase_shedding_delay, 4617 (u32)si_pi->vddc_phase_shed_table.phase_delay); 4618 } else { 4619 si_pi->vddc_phase_shed_control = false; 4620 } 4621 } 4622 } 4623 4624 return 0; 4625 } 4626 4627 static int si_populate_voltage_value(struct amdgpu_device *adev, 4628 const struct atom_voltage_table *table, 4629 u16 value, SISLANDS_SMC_VOLTAGE_VALUE *voltage) 4630 { 4631 unsigned int i; 4632 4633 for (i = 0; i < table->count; i++) { 4634 if (value <= table->entries[i].value) { 4635 voltage->index = (u8)i; 4636 voltage->value = cpu_to_be16(table->entries[i].value); 4637 break; 4638 } 4639 } 4640 4641 if (i >= table->count) 4642 return -EINVAL; 4643 4644 return 0; 4645 } 4646 4647 static int si_populate_mvdd_value(struct amdgpu_device *adev, u32 mclk, 4648 SISLANDS_SMC_VOLTAGE_VALUE *voltage) 4649 { 4650 struct rv7xx_power_info *pi = rv770_get_pi(adev); 4651 struct si_power_info *si_pi = si_get_pi(adev); 4652 4653 if (pi->mvdd_control) { 4654 if (mclk <= pi->mvdd_split_frequency) 4655 voltage->index = 0; 4656 else 4657 voltage->index = (u8)(si_pi->mvdd_voltage_table.count) - 1; 4658 4659 voltage->value = cpu_to_be16(si_pi->mvdd_voltage_table.entries[voltage->index].value); 4660 } 4661 return 0; 4662 } 4663 4664 static int si_get_std_voltage_value(struct amdgpu_device *adev, 4665 SISLANDS_SMC_VOLTAGE_VALUE *voltage, 4666 u16 *std_voltage) 4667 { 4668 u16 v_index; 4669 bool voltage_found = false; 4670 *std_voltage = be16_to_cpu(voltage->value); 4671 4672 if (adev->pm.dpm.dyn_state.cac_leakage_table.entries) { 4673 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_NEW_CAC_VOLTAGE) { 4674 if (adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries == NULL) 4675 return -EINVAL; 4676 4677 for (v_index = 0; (u32)v_index < adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) { 4678 if (be16_to_cpu(voltage->value) == 4679 (u16)adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) { 4680 voltage_found = true; 4681 if ((u32)v_index < adev->pm.dpm.dyn_state.cac_leakage_table.count) 4682 *std_voltage = 4683 adev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc; 4684 else 4685 *std_voltage = 4686 adev->pm.dpm.dyn_state.cac_leakage_table.entries[adev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc; 4687 break; 4688 } 4689 } 4690 4691 if (!voltage_found) { 4692 for (v_index = 0; (u32)v_index < adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) { 4693 if (be16_to_cpu(voltage->value) <= 4694 (u16)adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) { 4695 voltage_found = true; 4696 if ((u32)v_index < adev->pm.dpm.dyn_state.cac_leakage_table.count) 4697 *std_voltage = 4698 adev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc; 4699 else 4700 *std_voltage = 4701 adev->pm.dpm.dyn_state.cac_leakage_table.entries[adev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc; 4702 break; 4703 } 4704 } 4705 } 4706 } else { 4707 if ((u32)voltage->index < adev->pm.dpm.dyn_state.cac_leakage_table.count) 4708 *std_voltage = adev->pm.dpm.dyn_state.cac_leakage_table.entries[voltage->index].vddc; 4709 } 4710 } 4711 4712 return 0; 4713 } 4714 4715 static int si_populate_std_voltage_value(struct amdgpu_device *adev, 4716 u16 value, u8 index, 4717 SISLANDS_SMC_VOLTAGE_VALUE *voltage) 4718 { 4719 voltage->index = index; 4720 voltage->value = cpu_to_be16(value); 4721 4722 return 0; 4723 } 4724 4725 static int si_populate_phase_shedding_value(struct amdgpu_device *adev, 4726 const struct amdgpu_phase_shedding_limits_table *limits, 4727 u16 voltage, u32 sclk, u32 mclk, 4728 SISLANDS_SMC_VOLTAGE_VALUE *smc_voltage) 4729 { 4730 unsigned int i; 4731 4732 for (i = 0; i < limits->count; i++) { 4733 if ((voltage <= limits->entries[i].voltage) && 4734 (sclk <= limits->entries[i].sclk) && 4735 (mclk <= limits->entries[i].mclk)) 4736 break; 4737 } 4738 4739 smc_voltage->phase_settings = (u8)i; 4740 4741 return 0; 4742 } 4743 4744 static int si_init_arb_table_index(struct amdgpu_device *adev) 4745 { 4746 struct si_power_info *si_pi = si_get_pi(adev); 4747 u32 tmp; 4748 int ret; 4749 4750 ret = amdgpu_si_read_smc_sram_dword(adev, si_pi->arb_table_start, 4751 &tmp, si_pi->sram_end); 4752 if (ret) 4753 return ret; 4754 4755 tmp &= 0x00FFFFFF; 4756 tmp |= MC_CG_ARB_FREQ_F1 << 24; 4757 4758 return amdgpu_si_write_smc_sram_dword(adev, si_pi->arb_table_start, 4759 tmp, si_pi->sram_end); 4760 } 4761 4762 static int si_initial_switch_from_arb_f0_to_f1(struct amdgpu_device *adev) 4763 { 4764 return ni_copy_and_switch_arb_sets(adev, MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1); 4765 } 4766 4767 static int si_reset_to_default(struct amdgpu_device *adev) 4768 { 4769 return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_ResetToDefaults) == PPSMC_Result_OK) ? 4770 0 : -EINVAL; 4771 } 4772 4773 static int si_force_switch_to_arb_f0(struct amdgpu_device *adev) 4774 { 4775 struct si_power_info *si_pi = si_get_pi(adev); 4776 u32 tmp; 4777 int ret; 4778 4779 ret = amdgpu_si_read_smc_sram_dword(adev, si_pi->arb_table_start, 4780 &tmp, si_pi->sram_end); 4781 if (ret) 4782 return ret; 4783 4784 tmp = (tmp >> 24) & 0xff; 4785 4786 if (tmp == MC_CG_ARB_FREQ_F0) 4787 return 0; 4788 4789 return ni_copy_and_switch_arb_sets(adev, tmp, MC_CG_ARB_FREQ_F0); 4790 } 4791 4792 static u32 si_calculate_memory_refresh_rate(struct amdgpu_device *adev, 4793 u32 engine_clock) 4794 { 4795 u32 dram_rows; 4796 u32 dram_refresh_rate; 4797 u32 mc_arb_rfsh_rate; 4798 u32 tmp = (RREG32(mmMC_ARB_RAMCFG) & MC_ARB_RAMCFG__NOOFROWS_MASK) >> MC_ARB_RAMCFG__NOOFROWS__SHIFT; 4799 4800 if (tmp >= 4) 4801 dram_rows = 16384; 4802 else 4803 dram_rows = 1 << (tmp + 10); 4804 4805 dram_refresh_rate = 1 << ((RREG32(MC_SEQ_MISC0) & 0x3) + 3); 4806 mc_arb_rfsh_rate = ((engine_clock * 10) * dram_refresh_rate / dram_rows - 32) / 64; 4807 4808 return mc_arb_rfsh_rate; 4809 } 4810 4811 static int si_populate_memory_timing_parameters(struct amdgpu_device *adev, 4812 struct rv7xx_pl *pl, 4813 SMC_SIslands_MCArbDramTimingRegisterSet *arb_regs) 4814 { 4815 u32 dram_timing; 4816 u32 dram_timing2; 4817 u32 burst_time; 4818 int ret; 4819 4820 arb_regs->mc_arb_rfsh_rate = 4821 (u8)si_calculate_memory_refresh_rate(adev, pl->sclk); 4822 4823 ret = amdgpu_atombios_set_engine_dram_timings(adev, pl->sclk, 4824 pl->mclk); 4825 if (ret) 4826 return ret; 4827 4828 dram_timing = RREG32(MC_ARB_DRAM_TIMING); 4829 dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2); 4830 burst_time = RREG32(MC_ARB_BURST_TIME) & STATE0_MASK; 4831 4832 arb_regs->mc_arb_dram_timing = cpu_to_be32(dram_timing); 4833 arb_regs->mc_arb_dram_timing2 = cpu_to_be32(dram_timing2); 4834 arb_regs->mc_arb_burst_time = (u8)burst_time; 4835 4836 return 0; 4837 } 4838 4839 static int si_do_program_memory_timing_parameters(struct amdgpu_device *adev, 4840 struct amdgpu_ps *amdgpu_state, 4841 unsigned int first_arb_set) 4842 { 4843 struct si_power_info *si_pi = si_get_pi(adev); 4844 struct si_ps *state = si_get_ps(amdgpu_state); 4845 SMC_SIslands_MCArbDramTimingRegisterSet arb_regs = { 0 }; 4846 int i, ret = 0; 4847 4848 for (i = 0; i < state->performance_level_count; i++) { 4849 ret = si_populate_memory_timing_parameters(adev, &state->performance_levels[i], &arb_regs); 4850 if (ret) 4851 break; 4852 ret = amdgpu_si_copy_bytes_to_smc(adev, 4853 si_pi->arb_table_start + 4854 offsetof(SMC_SIslands_MCArbDramTimingRegisters, data) + 4855 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet) * (first_arb_set + i), 4856 (u8 *)&arb_regs, 4857 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet), 4858 si_pi->sram_end); 4859 if (ret) 4860 break; 4861 } 4862 4863 return ret; 4864 } 4865 4866 static int si_program_memory_timing_parameters(struct amdgpu_device *adev, 4867 struct amdgpu_ps *amdgpu_new_state) 4868 { 4869 return si_do_program_memory_timing_parameters(adev, amdgpu_new_state, 4870 SISLANDS_DRIVER_STATE_ARB_INDEX); 4871 } 4872 4873 static int si_populate_initial_mvdd_value(struct amdgpu_device *adev, 4874 struct SISLANDS_SMC_VOLTAGE_VALUE *voltage) 4875 { 4876 struct rv7xx_power_info *pi = rv770_get_pi(adev); 4877 struct si_power_info *si_pi = si_get_pi(adev); 4878 4879 if (pi->mvdd_control) 4880 return si_populate_voltage_value(adev, &si_pi->mvdd_voltage_table, 4881 si_pi->mvdd_bootup_value, voltage); 4882 4883 return 0; 4884 } 4885 4886 static int si_populate_smc_initial_state(struct amdgpu_device *adev, 4887 struct amdgpu_ps *amdgpu_initial_state, 4888 SISLANDS_SMC_STATETABLE *table) 4889 { 4890 struct si_ps *initial_state = si_get_ps(amdgpu_initial_state); 4891 struct rv7xx_power_info *pi = rv770_get_pi(adev); 4892 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); 4893 struct si_power_info *si_pi = si_get_pi(adev); 4894 u32 reg; 4895 int ret; 4896 4897 table->initialState.level.mclk.vDLL_CNTL = 4898 cpu_to_be32(si_pi->clock_registers.dll_cntl); 4899 table->initialState.level.mclk.vMCLK_PWRMGT_CNTL = 4900 cpu_to_be32(si_pi->clock_registers.mclk_pwrmgt_cntl); 4901 table->initialState.level.mclk.vMPLL_AD_FUNC_CNTL = 4902 cpu_to_be32(si_pi->clock_registers.mpll_ad_func_cntl); 4903 table->initialState.level.mclk.vMPLL_DQ_FUNC_CNTL = 4904 cpu_to_be32(si_pi->clock_registers.mpll_dq_func_cntl); 4905 table->initialState.level.mclk.vMPLL_FUNC_CNTL = 4906 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl); 4907 table->initialState.level.mclk.vMPLL_FUNC_CNTL_1 = 4908 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_1); 4909 table->initialState.level.mclk.vMPLL_FUNC_CNTL_2 = 4910 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_2); 4911 table->initialState.level.mclk.vMPLL_SS = 4912 cpu_to_be32(si_pi->clock_registers.mpll_ss1); 4913 table->initialState.level.mclk.vMPLL_SS2 = 4914 cpu_to_be32(si_pi->clock_registers.mpll_ss2); 4915 4916 table->initialState.level.mclk.mclk_value = 4917 cpu_to_be32(initial_state->performance_levels[0].mclk); 4918 4919 table->initialState.level.sclk.vCG_SPLL_FUNC_CNTL = 4920 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl); 4921 table->initialState.level.sclk.vCG_SPLL_FUNC_CNTL_2 = 4922 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_2); 4923 table->initialState.level.sclk.vCG_SPLL_FUNC_CNTL_3 = 4924 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_3); 4925 table->initialState.level.sclk.vCG_SPLL_FUNC_CNTL_4 = 4926 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_4); 4927 table->initialState.level.sclk.vCG_SPLL_SPREAD_SPECTRUM = 4928 cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum); 4929 table->initialState.level.sclk.vCG_SPLL_SPREAD_SPECTRUM_2 = 4930 cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum_2); 4931 4932 table->initialState.level.sclk.sclk_value = 4933 cpu_to_be32(initial_state->performance_levels[0].sclk); 4934 4935 table->initialState.level.arbRefreshState = 4936 SISLANDS_INITIAL_STATE_ARB_INDEX; 4937 4938 table->initialState.level.ACIndex = 0; 4939 4940 ret = si_populate_voltage_value(adev, &eg_pi->vddc_voltage_table, 4941 initial_state->performance_levels[0].vddc, 4942 &table->initialState.level.vddc); 4943 4944 if (!ret) { 4945 u16 std_vddc; 4946 4947 ret = si_get_std_voltage_value(adev, 4948 &table->initialState.level.vddc, 4949 &std_vddc); 4950 if (!ret) 4951 si_populate_std_voltage_value(adev, std_vddc, 4952 table->initialState.level.vddc.index, 4953 &table->initialState.level.std_vddc); 4954 } 4955 4956 if (eg_pi->vddci_control) 4957 si_populate_voltage_value(adev, 4958 &eg_pi->vddci_voltage_table, 4959 initial_state->performance_levels[0].vddci, 4960 &table->initialState.level.vddci); 4961 4962 if (si_pi->vddc_phase_shed_control) 4963 si_populate_phase_shedding_value(adev, 4964 &adev->pm.dpm.dyn_state.phase_shedding_limits_table, 4965 initial_state->performance_levels[0].vddc, 4966 initial_state->performance_levels[0].sclk, 4967 initial_state->performance_levels[0].mclk, 4968 &table->initialState.level.vddc); 4969 4970 si_populate_initial_mvdd_value(adev, &table->initialState.level.mvdd); 4971 4972 reg = 0xffff << CG_AT__CG_R__SHIFT | 0 << CG_AT__CG_L__SHIFT; 4973 table->initialState.level.aT = cpu_to_be32(reg); 4974 table->initialState.level.bSP = cpu_to_be32(pi->dsp); 4975 table->initialState.level.gen2PCIE = (u8)si_pi->boot_pcie_gen; 4976 4977 if (adev->gmc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) { 4978 table->initialState.level.strobeMode = 4979 si_get_strobe_mode_settings(adev, 4980 initial_state->performance_levels[0].mclk); 4981 4982 if (initial_state->performance_levels[0].mclk > pi->mclk_edc_enable_threshold) 4983 table->initialState.level.mcFlags = SISLANDS_SMC_MC_EDC_RD_FLAG | SISLANDS_SMC_MC_EDC_WR_FLAG; 4984 else 4985 table->initialState.level.mcFlags = 0; 4986 } 4987 4988 table->initialState.levelCount = 1; 4989 4990 table->initialState.flags |= PPSMC_SWSTATE_FLAG_DC; 4991 4992 table->initialState.level.dpm2.MaxPS = 0; 4993 table->initialState.level.dpm2.NearTDPDec = 0; 4994 table->initialState.level.dpm2.AboveSafeInc = 0; 4995 table->initialState.level.dpm2.BelowSafeInc = 0; 4996 table->initialState.level.dpm2.PwrEfficiencyRatio = 0; 4997 4998 reg = SQ_POWER_THROTTLE__MIN_POWER_MASK | 4999 SQ_POWER_THROTTLE__MAX_POWER_MASK; 5000 table->initialState.level.SQPowerThrottle = cpu_to_be32(reg); 5001 5002 reg = SQ_POWER_THROTTLE2__MAX_POWER_DELTA_MASK | 5003 SQ_POWER_THROTTLE2__SHORT_TERM_INTERVAL_SIZE_MASK | 5004 SQ_POWER_THROTTLE2__LONG_TERM_INTERVAL_RATIO_MASK; 5005 table->initialState.level.SQPowerThrottle_2 = cpu_to_be32(reg); 5006 5007 return 0; 5008 } 5009 5010 static enum si_pcie_gen si_gen_pcie_gen_support(struct amdgpu_device *adev, 5011 u32 sys_mask, 5012 enum si_pcie_gen asic_gen, 5013 enum si_pcie_gen default_gen) 5014 { 5015 switch (asic_gen) { 5016 case SI_PCIE_GEN1: 5017 return SI_PCIE_GEN1; 5018 case SI_PCIE_GEN2: 5019 return SI_PCIE_GEN2; 5020 case SI_PCIE_GEN3: 5021 return SI_PCIE_GEN3; 5022 default: 5023 if ((sys_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) && 5024 (default_gen == SI_PCIE_GEN3)) 5025 return SI_PCIE_GEN3; 5026 else if ((sys_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2) && 5027 (default_gen == SI_PCIE_GEN2)) 5028 return SI_PCIE_GEN2; 5029 else 5030 return SI_PCIE_GEN1; 5031 } 5032 return SI_PCIE_GEN1; 5033 } 5034 5035 static int si_populate_smc_acpi_state(struct amdgpu_device *adev, 5036 SISLANDS_SMC_STATETABLE *table) 5037 { 5038 struct rv7xx_power_info *pi = rv770_get_pi(adev); 5039 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); 5040 struct si_power_info *si_pi = si_get_pi(adev); 5041 u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl; 5042 u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2; 5043 u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3; 5044 u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4; 5045 u32 dll_cntl = si_pi->clock_registers.dll_cntl; 5046 u32 mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl; 5047 u32 mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl; 5048 u32 mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl; 5049 u32 mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl; 5050 u32 mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1; 5051 u32 mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2; 5052 u32 reg; 5053 int ret; 5054 5055 table->ACPIState = table->initialState; 5056 5057 table->ACPIState.flags &= ~PPSMC_SWSTATE_FLAG_DC; 5058 5059 if (pi->acpi_vddc) { 5060 ret = si_populate_voltage_value(adev, &eg_pi->vddc_voltage_table, 5061 pi->acpi_vddc, &table->ACPIState.level.vddc); 5062 if (!ret) { 5063 u16 std_vddc; 5064 5065 ret = si_get_std_voltage_value(adev, 5066 &table->ACPIState.level.vddc, &std_vddc); 5067 if (!ret) 5068 si_populate_std_voltage_value(adev, std_vddc, 5069 table->ACPIState.level.vddc.index, 5070 &table->ACPIState.level.std_vddc); 5071 } 5072 table->ACPIState.level.gen2PCIE = si_pi->acpi_pcie_gen; 5073 5074 if (si_pi->vddc_phase_shed_control) { 5075 si_populate_phase_shedding_value(adev, 5076 &adev->pm.dpm.dyn_state.phase_shedding_limits_table, 5077 pi->acpi_vddc, 5078 0, 5079 0, 5080 &table->ACPIState.level.vddc); 5081 } 5082 } else { 5083 ret = si_populate_voltage_value(adev, &eg_pi->vddc_voltage_table, 5084 pi->min_vddc_in_table, &table->ACPIState.level.vddc); 5085 if (!ret) { 5086 u16 std_vddc; 5087 5088 ret = si_get_std_voltage_value(adev, 5089 &table->ACPIState.level.vddc, &std_vddc); 5090 5091 if (!ret) 5092 si_populate_std_voltage_value(adev, std_vddc, 5093 table->ACPIState.level.vddc.index, 5094 &table->ACPIState.level.std_vddc); 5095 } 5096 table->ACPIState.level.gen2PCIE = 5097 (u8)si_gen_pcie_gen_support(adev, 5098 si_pi->sys_pcie_mask, 5099 si_pi->boot_pcie_gen, 5100 SI_PCIE_GEN1); 5101 5102 if (si_pi->vddc_phase_shed_control) 5103 si_populate_phase_shedding_value(adev, 5104 &adev->pm.dpm.dyn_state.phase_shedding_limits_table, 5105 pi->min_vddc_in_table, 5106 0, 5107 0, 5108 &table->ACPIState.level.vddc); 5109 } 5110 5111 if (pi->acpi_vddc) { 5112 if (eg_pi->acpi_vddci) 5113 si_populate_voltage_value(adev, &eg_pi->vddci_voltage_table, 5114 eg_pi->acpi_vddci, 5115 &table->ACPIState.level.vddci); 5116 } 5117 5118 mclk_pwrmgt_cntl |= MRDCK0_RESET | MRDCK1_RESET; 5119 mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB); 5120 5121 dll_cntl &= ~(MRDCK0_BYPASS | MRDCK1_BYPASS); 5122 5123 spll_func_cntl_2 &= ~CG_SPLL_FUNC_CNTL_2__SCLK_MUX_SEL_MASK; 5124 spll_func_cntl_2 |= 4 << CG_SPLL_FUNC_CNTL_2__SCLK_MUX_SEL__SHIFT; 5125 5126 table->ACPIState.level.mclk.vDLL_CNTL = 5127 cpu_to_be32(dll_cntl); 5128 table->ACPIState.level.mclk.vMCLK_PWRMGT_CNTL = 5129 cpu_to_be32(mclk_pwrmgt_cntl); 5130 table->ACPIState.level.mclk.vMPLL_AD_FUNC_CNTL = 5131 cpu_to_be32(mpll_ad_func_cntl); 5132 table->ACPIState.level.mclk.vMPLL_DQ_FUNC_CNTL = 5133 cpu_to_be32(mpll_dq_func_cntl); 5134 table->ACPIState.level.mclk.vMPLL_FUNC_CNTL = 5135 cpu_to_be32(mpll_func_cntl); 5136 table->ACPIState.level.mclk.vMPLL_FUNC_CNTL_1 = 5137 cpu_to_be32(mpll_func_cntl_1); 5138 table->ACPIState.level.mclk.vMPLL_FUNC_CNTL_2 = 5139 cpu_to_be32(mpll_func_cntl_2); 5140 table->ACPIState.level.mclk.vMPLL_SS = 5141 cpu_to_be32(si_pi->clock_registers.mpll_ss1); 5142 table->ACPIState.level.mclk.vMPLL_SS2 = 5143 cpu_to_be32(si_pi->clock_registers.mpll_ss2); 5144 5145 table->ACPIState.level.sclk.vCG_SPLL_FUNC_CNTL = 5146 cpu_to_be32(spll_func_cntl); 5147 table->ACPIState.level.sclk.vCG_SPLL_FUNC_CNTL_2 = 5148 cpu_to_be32(spll_func_cntl_2); 5149 table->ACPIState.level.sclk.vCG_SPLL_FUNC_CNTL_3 = 5150 cpu_to_be32(spll_func_cntl_3); 5151 table->ACPIState.level.sclk.vCG_SPLL_FUNC_CNTL_4 = 5152 cpu_to_be32(spll_func_cntl_4); 5153 5154 table->ACPIState.level.mclk.mclk_value = 0; 5155 table->ACPIState.level.sclk.sclk_value = 0; 5156 5157 si_populate_mvdd_value(adev, 0, &table->ACPIState.level.mvdd); 5158 5159 if (eg_pi->dynamic_ac_timing) 5160 table->ACPIState.level.ACIndex = 0; 5161 5162 table->ACPIState.level.dpm2.MaxPS = 0; 5163 table->ACPIState.level.dpm2.NearTDPDec = 0; 5164 table->ACPIState.level.dpm2.AboveSafeInc = 0; 5165 table->ACPIState.level.dpm2.BelowSafeInc = 0; 5166 table->ACPIState.level.dpm2.PwrEfficiencyRatio = 0; 5167 5168 reg = SQ_POWER_THROTTLE__MIN_POWER_MASK | SQ_POWER_THROTTLE__MAX_POWER_MASK; 5169 table->ACPIState.level.SQPowerThrottle = cpu_to_be32(reg); 5170 5171 reg = SQ_POWER_THROTTLE2__MAX_POWER_DELTA_MASK | SQ_POWER_THROTTLE2__SHORT_TERM_INTERVAL_SIZE_MASK | SQ_POWER_THROTTLE2__LONG_TERM_INTERVAL_RATIO_MASK; 5172 table->ACPIState.level.SQPowerThrottle_2 = cpu_to_be32(reg); 5173 5174 return 0; 5175 } 5176 5177 static int si_populate_ulv_state(struct amdgpu_device *adev, 5178 struct SISLANDS_SMC_SWSTATE_SINGLE *state) 5179 { 5180 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); 5181 struct si_power_info *si_pi = si_get_pi(adev); 5182 struct si_ulv_param *ulv = &si_pi->ulv; 5183 u32 sclk_in_sr = 1350; /* ??? */ 5184 int ret; 5185 5186 ret = si_convert_power_level_to_smc(adev, &ulv->pl, 5187 &state->level); 5188 if (!ret) { 5189 if (eg_pi->sclk_deep_sleep) { 5190 if (sclk_in_sr <= SCLK_MIN_DEEPSLEEP_FREQ) 5191 state->level.stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS; 5192 else 5193 state->level.stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE; 5194 } 5195 if (ulv->one_pcie_lane_in_ulv) 5196 state->flags |= PPSMC_SWSTATE_FLAG_PCIE_X1; 5197 state->level.arbRefreshState = (u8)(SISLANDS_ULV_STATE_ARB_INDEX); 5198 state->level.ACIndex = 1; 5199 state->level.std_vddc = state->level.vddc; 5200 state->levelCount = 1; 5201 5202 state->flags |= PPSMC_SWSTATE_FLAG_DC; 5203 } 5204 5205 return ret; 5206 } 5207 5208 static int si_program_ulv_memory_timing_parameters(struct amdgpu_device *adev) 5209 { 5210 struct si_power_info *si_pi = si_get_pi(adev); 5211 struct si_ulv_param *ulv = &si_pi->ulv; 5212 SMC_SIslands_MCArbDramTimingRegisterSet arb_regs = { 0 }; 5213 int ret; 5214 5215 ret = si_populate_memory_timing_parameters(adev, &ulv->pl, 5216 &arb_regs); 5217 if (ret) 5218 return ret; 5219 5220 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_ulv_volt_change_delay, 5221 ulv->volt_change_delay); 5222 5223 ret = amdgpu_si_copy_bytes_to_smc(adev, 5224 si_pi->arb_table_start + 5225 offsetof(SMC_SIslands_MCArbDramTimingRegisters, data) + 5226 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet) * SISLANDS_ULV_STATE_ARB_INDEX, 5227 (u8 *)&arb_regs, 5228 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet), 5229 si_pi->sram_end); 5230 5231 return ret; 5232 } 5233 5234 static void si_get_mvdd_configuration(struct amdgpu_device *adev) 5235 { 5236 struct rv7xx_power_info *pi = rv770_get_pi(adev); 5237 5238 pi->mvdd_split_frequency = 30000; 5239 } 5240 5241 static int si_init_smc_table(struct amdgpu_device *adev) 5242 { 5243 struct si_power_info *si_pi = si_get_pi(adev); 5244 struct amdgpu_ps *amdgpu_boot_state = adev->pm.dpm.boot_ps; 5245 const struct si_ulv_param *ulv = &si_pi->ulv; 5246 SISLANDS_SMC_STATETABLE *table = &si_pi->smc_statetable; 5247 int ret; 5248 u32 lane_width; 5249 u32 vr_hot_gpio; 5250 5251 si_populate_smc_voltage_tables(adev, table); 5252 5253 switch (adev->pm.int_thermal_type) { 5254 case THERMAL_TYPE_SI: 5255 case THERMAL_TYPE_EMC2103_WITH_INTERNAL: 5256 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_INTERNAL; 5257 break; 5258 case THERMAL_TYPE_NONE: 5259 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_NONE; 5260 break; 5261 default: 5262 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL; 5263 break; 5264 } 5265 5266 if ((adev->flags & AMD_IS_MOBILITY) && 5267 (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC)) 5268 table->systemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC; 5269 5270 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REGULATOR_HOT) { 5271 if ((adev->pdev->device != 0x6818) && (adev->pdev->device != 0x6819)) 5272 table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT; 5273 } 5274 5275 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC) 5276 table->systemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC; 5277 5278 if (adev->gmc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) 5279 table->systemFlags |= PPSMC_SYSTEMFLAG_GDDR5; 5280 5281 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REVERT_GPIO5_POLARITY) 5282 table->extraFlags |= PPSMC_EXTRAFLAGS_AC2DC_GPIO5_POLARITY_HIGH; 5283 5284 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_VRHOT_GPIO_CONFIGURABLE) { 5285 table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT_PROG_GPIO; 5286 vr_hot_gpio = adev->pm.dpm.backbias_response_time; 5287 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_vr_hot_gpio, 5288 vr_hot_gpio); 5289 } 5290 5291 ret = si_populate_smc_initial_state(adev, amdgpu_boot_state, table); 5292 if (ret) 5293 return ret; 5294 5295 ret = si_populate_smc_acpi_state(adev, table); 5296 if (ret) 5297 return ret; 5298 5299 table->driverState.flags = table->initialState.flags; 5300 table->driverState.levelCount = table->initialState.levelCount; 5301 table->driverState.levels[0] = table->initialState.level; 5302 5303 ret = si_do_program_memory_timing_parameters(adev, amdgpu_boot_state, 5304 SISLANDS_INITIAL_STATE_ARB_INDEX); 5305 if (ret) 5306 return ret; 5307 5308 if (ulv->supported && ulv->pl.vddc) { 5309 ret = si_populate_ulv_state(adev, &table->ULVState); 5310 if (ret) 5311 return ret; 5312 5313 ret = si_program_ulv_memory_timing_parameters(adev); 5314 if (ret) 5315 return ret; 5316 5317 WREG32(mmCG_ULV_CONTROL, ulv->cg_ulv_control); 5318 WREG32(mmCG_ULV_PARAMETER, ulv->cg_ulv_parameter); 5319 5320 lane_width = amdgpu_get_pcie_lanes(adev); 5321 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width); 5322 } else { 5323 table->ULVState = table->initialState; 5324 } 5325 5326 return amdgpu_si_copy_bytes_to_smc(adev, si_pi->state_table_start, 5327 (u8 *)table, sizeof(SISLANDS_SMC_STATETABLE), 5328 si_pi->sram_end); 5329 } 5330 5331 static int si_calculate_sclk_params(struct amdgpu_device *adev, 5332 u32 engine_clock, 5333 SISLANDS_SMC_SCLK_VALUE *sclk) 5334 { 5335 struct rv7xx_power_info *pi = rv770_get_pi(adev); 5336 struct si_power_info *si_pi = si_get_pi(adev); 5337 struct atom_clock_dividers dividers; 5338 u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl; 5339 u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2; 5340 u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3; 5341 u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4; 5342 u32 cg_spll_spread_spectrum = si_pi->clock_registers.cg_spll_spread_spectrum; 5343 u32 cg_spll_spread_spectrum_2 = si_pi->clock_registers.cg_spll_spread_spectrum_2; 5344 u64 tmp; 5345 u32 reference_clock = adev->clock.spll.reference_freq; 5346 u32 reference_divider; 5347 u32 fbdiv; 5348 int ret; 5349 5350 ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_ENGINE_PLL_PARAM, 5351 engine_clock, false, ÷rs); 5352 if (ret) 5353 return ret; 5354 5355 reference_divider = 1 + dividers.ref_div; 5356 5357 tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16384; 5358 do_div(tmp, reference_clock); 5359 fbdiv = (u32) tmp; 5360 5361 spll_func_cntl &= ~(CG_SPLL_FUNC_CNTL__SPLL_PDIV_A_MASK | CG_SPLL_FUNC_CNTL__SPLL_REF_DIV_MASK); 5362 spll_func_cntl |= dividers.ref_div << CG_SPLL_FUNC_CNTL__SPLL_REF_DIV__SHIFT; 5363 spll_func_cntl |= dividers.post_div << CG_SPLL_FUNC_CNTL__SPLL_PDIV_A__SHIFT; 5364 5365 spll_func_cntl_2 &= ~CG_SPLL_FUNC_CNTL_2__SCLK_MUX_SEL_MASK; 5366 spll_func_cntl_2 |= 2 << CG_SPLL_FUNC_CNTL_2__SCLK_MUX_SEL__SHIFT; 5367 5368 spll_func_cntl_3 &= ~CG_SPLL_FUNC_CNTL_3__SPLL_FB_DIV_MASK; 5369 spll_func_cntl_3 |= fbdiv << CG_SPLL_FUNC_CNTL_3__SPLL_FB_DIV__SHIFT; 5370 spll_func_cntl_3 |= CG_SPLL_FUNC_CNTL_3__SPLL_DITHEN_MASK; 5371 5372 if (pi->sclk_ss) { 5373 struct amdgpu_atom_ss ss; 5374 u32 vco_freq = engine_clock * dividers.post_div; 5375 5376 if (amdgpu_atombios_get_asic_ss_info(adev, &ss, 5377 ASIC_INTERNAL_ENGINE_SS, vco_freq)) { 5378 u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate); 5379 u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000); 5380 5381 cg_spll_spread_spectrum &= ~CG_SPLL_SPREAD_SPECTRUM__CLK_S_MASK; 5382 cg_spll_spread_spectrum |= clk_s << CG_SPLL_SPREAD_SPECTRUM__CLK_S__SHIFT; 5383 cg_spll_spread_spectrum |= CG_SPLL_SPREAD_SPECTRUM__SSEN_MASK; 5384 5385 cg_spll_spread_spectrum_2 &= ~CG_SPLL_SPREAD_SPECTRUM_2__CLK_V_MASK; 5386 cg_spll_spread_spectrum_2 |= clk_v << CG_SPLL_SPREAD_SPECTRUM_2__CLK_V__SHIFT; 5387 } 5388 } 5389 5390 sclk->sclk_value = engine_clock; 5391 sclk->vCG_SPLL_FUNC_CNTL = spll_func_cntl; 5392 sclk->vCG_SPLL_FUNC_CNTL_2 = spll_func_cntl_2; 5393 sclk->vCG_SPLL_FUNC_CNTL_3 = spll_func_cntl_3; 5394 sclk->vCG_SPLL_FUNC_CNTL_4 = spll_func_cntl_4; 5395 sclk->vCG_SPLL_SPREAD_SPECTRUM = cg_spll_spread_spectrum; 5396 sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cg_spll_spread_spectrum_2; 5397 5398 return 0; 5399 } 5400 5401 static int si_populate_sclk_value(struct amdgpu_device *adev, 5402 u32 engine_clock, 5403 SISLANDS_SMC_SCLK_VALUE *sclk) 5404 { 5405 SISLANDS_SMC_SCLK_VALUE sclk_tmp; 5406 int ret; 5407 5408 ret = si_calculate_sclk_params(adev, engine_clock, &sclk_tmp); 5409 if (!ret) { 5410 sclk->sclk_value = cpu_to_be32(sclk_tmp.sclk_value); 5411 sclk->vCG_SPLL_FUNC_CNTL = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL); 5412 sclk->vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_2); 5413 sclk->vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_3); 5414 sclk->vCG_SPLL_FUNC_CNTL_4 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_4); 5415 sclk->vCG_SPLL_SPREAD_SPECTRUM = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM); 5416 sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM_2); 5417 } 5418 5419 return ret; 5420 } 5421 5422 static int si_populate_mclk_value(struct amdgpu_device *adev, 5423 u32 engine_clock, 5424 u32 memory_clock, 5425 SISLANDS_SMC_MCLK_VALUE *mclk, 5426 bool strobe_mode, 5427 bool dll_state_on) 5428 { 5429 struct rv7xx_power_info *pi = rv770_get_pi(adev); 5430 struct si_power_info *si_pi = si_get_pi(adev); 5431 u32 dll_cntl = si_pi->clock_registers.dll_cntl; 5432 u32 mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl; 5433 u32 mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl; 5434 u32 mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl; 5435 u32 mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl; 5436 u32 mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1; 5437 u32 mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2; 5438 u32 mpll_ss1 = si_pi->clock_registers.mpll_ss1; 5439 u32 mpll_ss2 = si_pi->clock_registers.mpll_ss2; 5440 struct atom_mpll_param mpll_param; 5441 int ret; 5442 5443 ret = amdgpu_atombios_get_memory_pll_dividers(adev, memory_clock, strobe_mode, &mpll_param); 5444 if (ret) 5445 return ret; 5446 5447 mpll_func_cntl &= ~BWCTRL_MASK; 5448 mpll_func_cntl |= BWCTRL(mpll_param.bwcntl); 5449 5450 mpll_func_cntl_1 &= ~(CLKF_MASK | CLKFRAC_MASK | VCO_MODE_MASK); 5451 mpll_func_cntl_1 |= CLKF(mpll_param.clkf) | 5452 CLKFRAC(mpll_param.clkfrac) | VCO_MODE(mpll_param.vco_mode); 5453 5454 mpll_ad_func_cntl &= ~YCLK_POST_DIV_MASK; 5455 mpll_ad_func_cntl |= YCLK_POST_DIV(mpll_param.post_div); 5456 5457 if (adev->gmc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) { 5458 mpll_dq_func_cntl &= ~(YCLK_SEL_MASK | YCLK_POST_DIV_MASK); 5459 mpll_dq_func_cntl |= YCLK_SEL(mpll_param.yclk_sel) | 5460 YCLK_POST_DIV(mpll_param.post_div); 5461 } 5462 5463 if (pi->mclk_ss) { 5464 struct amdgpu_atom_ss ss; 5465 u32 freq_nom; 5466 u32 tmp; 5467 u32 reference_clock = adev->clock.mpll.reference_freq; 5468 5469 if (adev->gmc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) 5470 freq_nom = memory_clock * 4; 5471 else 5472 freq_nom = memory_clock * 2; 5473 5474 tmp = freq_nom / reference_clock; 5475 tmp = tmp * tmp; 5476 if (amdgpu_atombios_get_asic_ss_info(adev, &ss, 5477 ASIC_INTERNAL_MEMORY_SS, freq_nom)) { 5478 u32 clks = reference_clock * 5 / ss.rate; 5479 u32 clkv = (u32)((((131 * ss.percentage * ss.rate) / 100) * tmp) / freq_nom); 5480 5481 mpll_ss1 &= ~CLKV_MASK; 5482 mpll_ss1 |= CLKV(clkv); 5483 5484 mpll_ss2 &= ~CLKS_MASK; 5485 mpll_ss2 |= CLKS(clks); 5486 } 5487 } 5488 5489 mclk_pwrmgt_cntl &= ~DLL_SPEED_MASK; 5490 mclk_pwrmgt_cntl |= DLL_SPEED(mpll_param.dll_speed); 5491 5492 if (dll_state_on) 5493 mclk_pwrmgt_cntl |= MRDCK0_PDNB | MRDCK1_PDNB; 5494 else 5495 mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB); 5496 5497 mclk->mclk_value = cpu_to_be32(memory_clock); 5498 mclk->vMPLL_FUNC_CNTL = cpu_to_be32(mpll_func_cntl); 5499 mclk->vMPLL_FUNC_CNTL_1 = cpu_to_be32(mpll_func_cntl_1); 5500 mclk->vMPLL_FUNC_CNTL_2 = cpu_to_be32(mpll_func_cntl_2); 5501 mclk->vMPLL_AD_FUNC_CNTL = cpu_to_be32(mpll_ad_func_cntl); 5502 mclk->vMPLL_DQ_FUNC_CNTL = cpu_to_be32(mpll_dq_func_cntl); 5503 mclk->vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl); 5504 mclk->vDLL_CNTL = cpu_to_be32(dll_cntl); 5505 mclk->vMPLL_SS = cpu_to_be32(mpll_ss1); 5506 mclk->vMPLL_SS2 = cpu_to_be32(mpll_ss2); 5507 5508 return 0; 5509 } 5510 5511 static void si_populate_smc_sp(struct amdgpu_device *adev, 5512 struct amdgpu_ps *amdgpu_state, 5513 SISLANDS_SMC_SWSTATE *smc_state) 5514 { 5515 struct si_ps *ps = si_get_ps(amdgpu_state); 5516 struct rv7xx_power_info *pi = rv770_get_pi(adev); 5517 int i; 5518 5519 for (i = 0; i < ps->performance_level_count - 1; i++) 5520 smc_state->levels[i].bSP = cpu_to_be32(pi->dsp); 5521 5522 smc_state->levels[ps->performance_level_count - 1].bSP = 5523 cpu_to_be32(pi->psp); 5524 } 5525 5526 static int si_convert_power_level_to_smc(struct amdgpu_device *adev, 5527 struct rv7xx_pl *pl, 5528 SISLANDS_SMC_HW_PERFORMANCE_LEVEL *level) 5529 { 5530 struct rv7xx_power_info *pi = rv770_get_pi(adev); 5531 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); 5532 struct si_power_info *si_pi = si_get_pi(adev); 5533 int ret; 5534 bool dll_state_on; 5535 u16 std_vddc; 5536 5537 if (eg_pi->pcie_performance_request && 5538 (si_pi->force_pcie_gen != SI_PCIE_GEN_INVALID)) 5539 level->gen2PCIE = (u8)si_pi->force_pcie_gen; 5540 else 5541 level->gen2PCIE = (u8)pl->pcie_gen; 5542 5543 ret = si_populate_sclk_value(adev, pl->sclk, &level->sclk); 5544 if (ret) 5545 return ret; 5546 5547 level->mcFlags = 0; 5548 5549 if (pi->mclk_stutter_mode_threshold && 5550 (pl->mclk <= pi->mclk_stutter_mode_threshold) && 5551 !eg_pi->uvd_enabled && 5552 (RREG32(mmDPG_PIPE_STUTTER_CONTROL) & DPG_PIPE_STUTTER_CONTROL__STUTTER_ENABLE_MASK) && 5553 (adev->pm.pm_display_cfg.num_display <= 2)) { 5554 level->mcFlags |= SISLANDS_SMC_MC_STUTTER_EN; 5555 } 5556 5557 if (adev->gmc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) { 5558 if (pl->mclk > pi->mclk_edc_enable_threshold) 5559 level->mcFlags |= SISLANDS_SMC_MC_EDC_RD_FLAG; 5560 5561 if (pl->mclk > eg_pi->mclk_edc_wr_enable_threshold) 5562 level->mcFlags |= SISLANDS_SMC_MC_EDC_WR_FLAG; 5563 5564 level->strobeMode = si_get_strobe_mode_settings(adev, pl->mclk); 5565 5566 if (level->strobeMode & SISLANDS_SMC_STROBE_ENABLE) { 5567 if (si_get_mclk_frequency_ratio(pl->mclk, true) >= 5568 ((RREG32(MC_SEQ_MISC7) >> 16) & 0xf)) 5569 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false; 5570 else 5571 dll_state_on = ((RREG32(MC_SEQ_MISC6) >> 1) & 0x1) ? true : false; 5572 } else { 5573 dll_state_on = false; 5574 } 5575 } else { 5576 level->strobeMode = si_get_strobe_mode_settings(adev, 5577 pl->mclk); 5578 5579 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false; 5580 } 5581 5582 ret = si_populate_mclk_value(adev, 5583 pl->sclk, 5584 pl->mclk, 5585 &level->mclk, 5586 (level->strobeMode & SISLANDS_SMC_STROBE_ENABLE) != 0, dll_state_on); 5587 if (ret) 5588 return ret; 5589 5590 ret = si_populate_voltage_value(adev, 5591 &eg_pi->vddc_voltage_table, 5592 pl->vddc, &level->vddc); 5593 if (ret) 5594 return ret; 5595 5596 5597 ret = si_get_std_voltage_value(adev, &level->vddc, &std_vddc); 5598 if (ret) 5599 return ret; 5600 5601 ret = si_populate_std_voltage_value(adev, std_vddc, 5602 level->vddc.index, &level->std_vddc); 5603 if (ret) 5604 return ret; 5605 5606 if (eg_pi->vddci_control) { 5607 ret = si_populate_voltage_value(adev, &eg_pi->vddci_voltage_table, 5608 pl->vddci, &level->vddci); 5609 if (ret) 5610 return ret; 5611 } 5612 5613 if (si_pi->vddc_phase_shed_control) { 5614 ret = si_populate_phase_shedding_value(adev, 5615 &adev->pm.dpm.dyn_state.phase_shedding_limits_table, 5616 pl->vddc, 5617 pl->sclk, 5618 pl->mclk, 5619 &level->vddc); 5620 if (ret) 5621 return ret; 5622 } 5623 5624 level->MaxPoweredUpCU = si_pi->max_cu; 5625 5626 ret = si_populate_mvdd_value(adev, pl->mclk, &level->mvdd); 5627 5628 return ret; 5629 } 5630 5631 static int si_populate_smc_t(struct amdgpu_device *adev, 5632 struct amdgpu_ps *amdgpu_state, 5633 SISLANDS_SMC_SWSTATE *smc_state) 5634 { 5635 struct rv7xx_power_info *pi = rv770_get_pi(adev); 5636 struct si_ps *state = si_get_ps(amdgpu_state); 5637 u32 a_t; 5638 u32 t_l, t_h; 5639 u32 high_bsp; 5640 int i, ret; 5641 5642 if (state->performance_level_count >= 9) 5643 return -EINVAL; 5644 5645 if (state->performance_level_count < 2) { 5646 a_t = 0xffff << CG_AT__CG_R__SHIFT | 0 << CG_AT__CG_L__SHIFT; 5647 smc_state->levels[0].aT = cpu_to_be32(a_t); 5648 return 0; 5649 } 5650 5651 smc_state->levels[0].aT = cpu_to_be32(0); 5652 5653 for (i = 0; i <= state->performance_level_count - 2; i++) { 5654 ret = r600_calculate_at( 5655 (50 / SISLANDS_MAX_HARDWARE_POWERLEVELS) * 100 * (i + 1), 5656 100 * R600_AH_DFLT, 5657 state->performance_levels[i + 1].sclk, 5658 state->performance_levels[i].sclk, 5659 &t_l, 5660 &t_h); 5661 5662 if (ret) { 5663 t_h = (i + 1) * 1000 - 50 * R600_AH_DFLT; 5664 t_l = (i + 1) * 1000 + 50 * R600_AH_DFLT; 5665 } 5666 5667 a_t = be32_to_cpu(smc_state->levels[i].aT) & ~CG_AT__CG_R_MASK; 5668 a_t |= (t_l * pi->bsp / 20000) << CG_AT__CG_R__SHIFT; 5669 smc_state->levels[i].aT = cpu_to_be32(a_t); 5670 5671 high_bsp = (i == state->performance_level_count - 2) ? 5672 pi->pbsp : pi->bsp; 5673 a_t = (0xffff) << CG_AT__CG_R__SHIFT | (t_h * high_bsp / 20000) << CG_AT__CG_L__SHIFT; 5674 smc_state->levels[i + 1].aT = cpu_to_be32(a_t); 5675 } 5676 5677 return 0; 5678 } 5679 5680 static int si_disable_ulv(struct amdgpu_device *adev) 5681 { 5682 PPSMC_Result r; 5683 5684 r = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_DisableULV); 5685 return (r == PPSMC_Result_OK) ? 0 : -EINVAL; 5686 } 5687 5688 static bool si_is_state_ulv_compatible(struct amdgpu_device *adev, 5689 struct amdgpu_ps *amdgpu_state) 5690 { 5691 const struct si_power_info *si_pi = si_get_pi(adev); 5692 const struct si_ulv_param *ulv = &si_pi->ulv; 5693 const struct si_ps *state = si_get_ps(amdgpu_state); 5694 int i; 5695 5696 if (state->performance_levels[0].mclk != ulv->pl.mclk) 5697 return false; 5698 5699 /* XXX validate against display requirements! */ 5700 5701 for (i = 0; i < adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count; i++) { 5702 if (adev->pm.pm_display_cfg.display_clk <= 5703 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].clk) { 5704 if (ulv->pl.vddc < 5705 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].v) 5706 return false; 5707 } 5708 } 5709 5710 if ((amdgpu_state->vclk != 0) || (amdgpu_state->dclk != 0)) 5711 return false; 5712 5713 return true; 5714 } 5715 5716 static int si_set_power_state_conditionally_enable_ulv(struct amdgpu_device *adev, 5717 struct amdgpu_ps *amdgpu_new_state) 5718 { 5719 const struct si_power_info *si_pi = si_get_pi(adev); 5720 const struct si_ulv_param *ulv = &si_pi->ulv; 5721 5722 if (ulv->supported) { 5723 if (si_is_state_ulv_compatible(adev, amdgpu_new_state)) 5724 return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_EnableULV) == PPSMC_Result_OK) ? 5725 0 : -EINVAL; 5726 } 5727 return 0; 5728 } 5729 5730 static int si_convert_power_state_to_smc(struct amdgpu_device *adev, 5731 struct amdgpu_ps *amdgpu_state, 5732 SISLANDS_SMC_SWSTATE *smc_state) 5733 { 5734 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); 5735 struct ni_power_info *ni_pi = ni_get_pi(adev); 5736 struct si_power_info *si_pi = si_get_pi(adev); 5737 struct si_ps *state = si_get_ps(amdgpu_state); 5738 int i, ret; 5739 u32 threshold; 5740 u32 sclk_in_sr = 1350; /* ??? */ 5741 5742 if (state->performance_level_count > SISLANDS_MAX_HARDWARE_POWERLEVELS) 5743 return -EINVAL; 5744 5745 threshold = state->performance_levels[state->performance_level_count-1].sclk * 100 / 100; 5746 5747 if (amdgpu_state->vclk && amdgpu_state->dclk) { 5748 eg_pi->uvd_enabled = true; 5749 if (eg_pi->smu_uvd_hs) 5750 smc_state->flags |= PPSMC_SWSTATE_FLAG_UVD; 5751 } else { 5752 eg_pi->uvd_enabled = false; 5753 } 5754 5755 if (state->dc_compatible) 5756 smc_state->flags |= PPSMC_SWSTATE_FLAG_DC; 5757 5758 smc_state->levelCount = 0; 5759 for (i = 0; i < state->performance_level_count; i++) { 5760 if (eg_pi->sclk_deep_sleep) { 5761 if ((i == 0) || si_pi->sclk_deep_sleep_above_low) { 5762 if (sclk_in_sr <= SCLK_MIN_DEEPSLEEP_FREQ) 5763 smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS; 5764 else 5765 smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE; 5766 } 5767 } 5768 5769 ret = si_convert_power_level_to_smc(adev, &state->performance_levels[i], 5770 &smc_state->levels[i]); 5771 smc_state->levels[i].arbRefreshState = 5772 (u8)(SISLANDS_DRIVER_STATE_ARB_INDEX + i); 5773 5774 if (ret) 5775 return ret; 5776 5777 if (ni_pi->enable_power_containment) 5778 smc_state->levels[i].displayWatermark = 5779 (state->performance_levels[i].sclk < threshold) ? 5780 PPSMC_DISPLAY_WATERMARK_LOW : PPSMC_DISPLAY_WATERMARK_HIGH; 5781 else 5782 smc_state->levels[i].displayWatermark = (i < 2) ? 5783 PPSMC_DISPLAY_WATERMARK_LOW : PPSMC_DISPLAY_WATERMARK_HIGH; 5784 5785 if (eg_pi->dynamic_ac_timing) 5786 smc_state->levels[i].ACIndex = SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i; 5787 else 5788 smc_state->levels[i].ACIndex = 0; 5789 5790 smc_state->levelCount++; 5791 } 5792 5793 si_write_smc_soft_register(adev, 5794 SI_SMC_SOFT_REGISTER_watermark_threshold, 5795 threshold / 512); 5796 5797 si_populate_smc_sp(adev, amdgpu_state, smc_state); 5798 5799 ret = si_populate_power_containment_values(adev, amdgpu_state, smc_state); 5800 if (ret) 5801 ni_pi->enable_power_containment = false; 5802 5803 ret = si_populate_sq_ramping_values(adev, amdgpu_state, smc_state); 5804 if (ret) 5805 ni_pi->enable_sq_ramping = false; 5806 5807 return si_populate_smc_t(adev, amdgpu_state, smc_state); 5808 } 5809 5810 static int si_upload_sw_state(struct amdgpu_device *adev, 5811 struct amdgpu_ps *amdgpu_new_state) 5812 { 5813 struct si_power_info *si_pi = si_get_pi(adev); 5814 struct si_ps *new_state = si_get_ps(amdgpu_new_state); 5815 int ret; 5816 u32 address = si_pi->state_table_start + 5817 offsetof(SISLANDS_SMC_STATETABLE, driverState); 5818 SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.driverState; 5819 size_t state_size = struct_size(smc_state, levels, 5820 new_state->performance_level_count); 5821 memset(smc_state, 0, state_size); 5822 5823 ret = si_convert_power_state_to_smc(adev, amdgpu_new_state, smc_state); 5824 if (ret) 5825 return ret; 5826 5827 return amdgpu_si_copy_bytes_to_smc(adev, address, (u8 *)smc_state, 5828 state_size, si_pi->sram_end); 5829 } 5830 5831 static int si_upload_ulv_state(struct amdgpu_device *adev) 5832 { 5833 struct si_power_info *si_pi = si_get_pi(adev); 5834 struct si_ulv_param *ulv = &si_pi->ulv; 5835 int ret = 0; 5836 5837 if (ulv->supported && ulv->pl.vddc) { 5838 u32 address = si_pi->state_table_start + 5839 offsetof(SISLANDS_SMC_STATETABLE, ULVState); 5840 struct SISLANDS_SMC_SWSTATE_SINGLE *smc_state = &si_pi->smc_statetable.ULVState; 5841 u32 state_size = sizeof(struct SISLANDS_SMC_SWSTATE_SINGLE); 5842 5843 memset(smc_state, 0, state_size); 5844 5845 ret = si_populate_ulv_state(adev, smc_state); 5846 if (!ret) 5847 ret = amdgpu_si_copy_bytes_to_smc(adev, address, (u8 *)smc_state, 5848 state_size, si_pi->sram_end); 5849 } 5850 5851 return ret; 5852 } 5853 5854 static int si_upload_smc_data(struct amdgpu_device *adev) 5855 { 5856 const struct amd_pp_display_configuration *cfg = &adev->pm.pm_display_cfg; 5857 u32 crtc_index = 0; 5858 u32 mclk_change_block_cp_min = 0; 5859 u32 mclk_change_block_cp_max = 0; 5860 5861 /* When a display is plugged in, program these so that the SMC 5862 * performs MCLK switching when it doesn't cause flickering. 5863 * When no display is plugged in, there is no need to restrict 5864 * MCLK switching, so program them to zero. 5865 */ 5866 if (cfg->num_display) { 5867 crtc_index = cfg->crtc_index; 5868 5869 if (cfg->line_time_in_us) { 5870 mclk_change_block_cp_min = 200 / cfg->line_time_in_us; 5871 mclk_change_block_cp_max = 100 / cfg->line_time_in_us; 5872 } 5873 } 5874 5875 si_write_smc_soft_register(adev, 5876 SI_SMC_SOFT_REGISTER_crtc_index, 5877 crtc_index); 5878 5879 si_write_smc_soft_register(adev, 5880 SI_SMC_SOFT_REGISTER_mclk_change_block_cp_min, 5881 mclk_change_block_cp_min); 5882 5883 si_write_smc_soft_register(adev, 5884 SI_SMC_SOFT_REGISTER_mclk_change_block_cp_max, 5885 mclk_change_block_cp_max); 5886 5887 return 0; 5888 } 5889 5890 static int si_set_mc_special_registers(struct amdgpu_device *adev, 5891 struct si_mc_reg_table *table) 5892 { 5893 u8 i, j, k; 5894 u32 temp_reg; 5895 5896 for (i = 0, j = table->last; i < table->last; i++) { 5897 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5898 return -EINVAL; 5899 switch (table->mc_reg_address[i].s1) { 5900 case MC_SEQ_MISC1: 5901 temp_reg = RREG32(MC_PMG_CMD_EMRS); 5902 table->mc_reg_address[j].s1 = MC_PMG_CMD_EMRS; 5903 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_EMRS_LP; 5904 for (k = 0; k < table->num_entries; k++) 5905 table->mc_reg_table_entry[k].mc_data[j] = 5906 ((temp_reg & 0xffff0000)) | 5907 ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16); 5908 j++; 5909 5910 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5911 return -EINVAL; 5912 temp_reg = RREG32(MC_PMG_CMD_MRS); 5913 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS; 5914 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS_LP; 5915 for (k = 0; k < table->num_entries; k++) { 5916 table->mc_reg_table_entry[k].mc_data[j] = 5917 (temp_reg & 0xffff0000) | 5918 (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff); 5919 if (adev->gmc.vram_type != AMDGPU_VRAM_TYPE_GDDR5) 5920 table->mc_reg_table_entry[k].mc_data[j] |= 0x100; 5921 } 5922 j++; 5923 5924 if (adev->gmc.vram_type != AMDGPU_VRAM_TYPE_GDDR5) { 5925 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5926 return -EINVAL; 5927 table->mc_reg_address[j].s1 = MC_PMG_AUTO_CMD; 5928 table->mc_reg_address[j].s0 = MC_PMG_AUTO_CMD; 5929 for (k = 0; k < table->num_entries; k++) 5930 table->mc_reg_table_entry[k].mc_data[j] = 5931 (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16; 5932 j++; 5933 } 5934 break; 5935 case MC_SEQ_RESERVE_M: 5936 temp_reg = RREG32(MC_PMG_CMD_MRS1); 5937 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS1; 5938 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS1_LP; 5939 for(k = 0; k < table->num_entries; k++) 5940 table->mc_reg_table_entry[k].mc_data[j] = 5941 (temp_reg & 0xffff0000) | 5942 (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff); 5943 j++; 5944 break; 5945 default: 5946 break; 5947 } 5948 } 5949 5950 table->last = j; 5951 5952 return 0; 5953 } 5954 5955 static bool si_check_s0_mc_reg_index(u16 in_reg, u16 *out_reg) 5956 { 5957 bool result = true; 5958 switch (in_reg) { 5959 case MC_SEQ_RAS_TIMING: 5960 *out_reg = MC_SEQ_RAS_TIMING_LP; 5961 break; 5962 case MC_SEQ_CAS_TIMING: 5963 *out_reg = MC_SEQ_CAS_TIMING_LP; 5964 break; 5965 case MC_SEQ_MISC_TIMING: 5966 *out_reg = MC_SEQ_MISC_TIMING_LP; 5967 break; 5968 case MC_SEQ_MISC_TIMING2: 5969 *out_reg = MC_SEQ_MISC_TIMING2_LP; 5970 break; 5971 case MC_SEQ_RD_CTL_D0: 5972 *out_reg = MC_SEQ_RD_CTL_D0_LP; 5973 break; 5974 case MC_SEQ_RD_CTL_D1: 5975 *out_reg = MC_SEQ_RD_CTL_D1_LP; 5976 break; 5977 case MC_SEQ_WR_CTL_D0: 5978 *out_reg = MC_SEQ_WR_CTL_D0_LP; 5979 break; 5980 case MC_SEQ_WR_CTL_D1: 5981 *out_reg = MC_SEQ_WR_CTL_D1_LP; 5982 break; 5983 case MC_PMG_CMD_EMRS: 5984 *out_reg = MC_SEQ_PMG_CMD_EMRS_LP; 5985 break; 5986 case MC_PMG_CMD_MRS: 5987 *out_reg = MC_SEQ_PMG_CMD_MRS_LP; 5988 break; 5989 case MC_PMG_CMD_MRS1: 5990 *out_reg = MC_SEQ_PMG_CMD_MRS1_LP; 5991 break; 5992 case MC_SEQ_PMG_TIMING: 5993 *out_reg = MC_SEQ_PMG_TIMING_LP; 5994 break; 5995 case MC_PMG_CMD_MRS2: 5996 *out_reg = MC_SEQ_PMG_CMD_MRS2_LP; 5997 break; 5998 case MC_SEQ_WR_CTL_2: 5999 *out_reg = MC_SEQ_WR_CTL_2_LP; 6000 break; 6001 default: 6002 result = false; 6003 break; 6004 } 6005 6006 return result; 6007 } 6008 6009 static void si_set_valid_flag(struct si_mc_reg_table *table) 6010 { 6011 u8 i, j; 6012 6013 for (i = 0; i < table->last; i++) { 6014 for (j = 1; j < table->num_entries; j++) { 6015 if (table->mc_reg_table_entry[j-1].mc_data[i] != table->mc_reg_table_entry[j].mc_data[i]) { 6016 table->valid_flag |= 1 << i; 6017 break; 6018 } 6019 } 6020 } 6021 } 6022 6023 static void si_set_s0_mc_reg_index(struct si_mc_reg_table *table) 6024 { 6025 u32 i; 6026 u16 address; 6027 6028 for (i = 0; i < table->last; i++) 6029 table->mc_reg_address[i].s0 = si_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address) ? 6030 address : table->mc_reg_address[i].s1; 6031 6032 } 6033 6034 static int si_copy_vbios_mc_reg_table(struct atom_mc_reg_table *table, 6035 struct si_mc_reg_table *si_table) 6036 { 6037 u8 i, j; 6038 6039 if (table->last > SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 6040 return -EINVAL; 6041 if (table->num_entries > MAX_AC_TIMING_ENTRIES) 6042 return -EINVAL; 6043 6044 for (i = 0; i < table->last; i++) 6045 si_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1; 6046 si_table->last = table->last; 6047 6048 for (i = 0; i < table->num_entries; i++) { 6049 si_table->mc_reg_table_entry[i].mclk_max = 6050 table->mc_reg_table_entry[i].mclk_max; 6051 for (j = 0; j < table->last; j++) { 6052 si_table->mc_reg_table_entry[i].mc_data[j] = 6053 table->mc_reg_table_entry[i].mc_data[j]; 6054 } 6055 } 6056 si_table->num_entries = table->num_entries; 6057 6058 return 0; 6059 } 6060 6061 static int si_initialize_mc_reg_table(struct amdgpu_device *adev) 6062 { 6063 struct si_power_info *si_pi = si_get_pi(adev); 6064 struct atom_mc_reg_table *table; 6065 struct si_mc_reg_table *si_table = &si_pi->mc_reg_table; 6066 u8 module_index = rv770_get_memory_module_index(adev); 6067 int ret; 6068 6069 table = kzalloc_obj(struct atom_mc_reg_table); 6070 if (!table) 6071 return -ENOMEM; 6072 6073 WREG32(MC_SEQ_RAS_TIMING_LP, RREG32(MC_SEQ_RAS_TIMING)); 6074 WREG32(MC_SEQ_CAS_TIMING_LP, RREG32(MC_SEQ_CAS_TIMING)); 6075 WREG32(MC_SEQ_MISC_TIMING_LP, RREG32(MC_SEQ_MISC_TIMING)); 6076 WREG32(MC_SEQ_MISC_TIMING2_LP, RREG32(MC_SEQ_MISC_TIMING2)); 6077 WREG32(MC_SEQ_PMG_CMD_EMRS_LP, RREG32(MC_PMG_CMD_EMRS)); 6078 WREG32(MC_SEQ_PMG_CMD_MRS_LP, RREG32(MC_PMG_CMD_MRS)); 6079 WREG32(MC_SEQ_PMG_CMD_MRS1_LP, RREG32(MC_PMG_CMD_MRS1)); 6080 WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0)); 6081 WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1)); 6082 WREG32(MC_SEQ_RD_CTL_D0_LP, RREG32(MC_SEQ_RD_CTL_D0)); 6083 WREG32(MC_SEQ_RD_CTL_D1_LP, RREG32(MC_SEQ_RD_CTL_D1)); 6084 WREG32(MC_SEQ_PMG_TIMING_LP, RREG32(MC_SEQ_PMG_TIMING)); 6085 WREG32(MC_SEQ_PMG_CMD_MRS2_LP, RREG32(MC_PMG_CMD_MRS2)); 6086 WREG32(MC_SEQ_WR_CTL_2_LP, RREG32(MC_SEQ_WR_CTL_2)); 6087 6088 ret = amdgpu_atombios_init_mc_reg_table(adev, module_index, table); 6089 if (ret) 6090 goto init_mc_done; 6091 6092 ret = si_copy_vbios_mc_reg_table(table, si_table); 6093 if (ret) 6094 goto init_mc_done; 6095 6096 si_set_s0_mc_reg_index(si_table); 6097 6098 ret = si_set_mc_special_registers(adev, si_table); 6099 if (ret) 6100 goto init_mc_done; 6101 6102 si_set_valid_flag(si_table); 6103 6104 init_mc_done: 6105 kfree(table); 6106 6107 return ret; 6108 6109 } 6110 6111 static void si_populate_mc_reg_addresses(struct amdgpu_device *adev, 6112 SMC_SIslands_MCRegisters *mc_reg_table) 6113 { 6114 struct si_power_info *si_pi = si_get_pi(adev); 6115 u32 i, j; 6116 6117 for (i = 0, j = 0; j < si_pi->mc_reg_table.last; j++) { 6118 if (si_pi->mc_reg_table.valid_flag & (1 << j)) { 6119 if (i >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 6120 break; 6121 mc_reg_table->address[i].s0 = 6122 cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s0); 6123 mc_reg_table->address[i].s1 = 6124 cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s1); 6125 i++; 6126 } 6127 } 6128 mc_reg_table->last = (u8)i; 6129 } 6130 6131 static void si_convert_mc_registers(const struct si_mc_reg_entry *entry, 6132 SMC_SIslands_MCRegisterSet *data, 6133 u32 num_entries, u32 valid_flag) 6134 { 6135 u32 i, j; 6136 6137 for(i = 0, j = 0; j < num_entries; j++) { 6138 if (valid_flag & (1 << j)) { 6139 data->value[i] = cpu_to_be32(entry->mc_data[j]); 6140 i++; 6141 } 6142 } 6143 } 6144 6145 static void si_convert_mc_reg_table_entry_to_smc(struct amdgpu_device *adev, 6146 struct rv7xx_pl *pl, 6147 SMC_SIslands_MCRegisterSet *mc_reg_table_data) 6148 { 6149 struct si_power_info *si_pi = si_get_pi(adev); 6150 u32 i = 0; 6151 6152 for (i = 0; i < si_pi->mc_reg_table.num_entries; i++) { 6153 if (pl->mclk <= si_pi->mc_reg_table.mc_reg_table_entry[i].mclk_max) 6154 break; 6155 } 6156 6157 if ((i == si_pi->mc_reg_table.num_entries) && (i > 0)) 6158 --i; 6159 6160 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[i], 6161 mc_reg_table_data, si_pi->mc_reg_table.last, 6162 si_pi->mc_reg_table.valid_flag); 6163 } 6164 6165 static void si_convert_mc_reg_table_to_smc(struct amdgpu_device *adev, 6166 struct amdgpu_ps *amdgpu_state, 6167 SMC_SIslands_MCRegisters *mc_reg_table) 6168 { 6169 struct si_ps *state = si_get_ps(amdgpu_state); 6170 int i; 6171 6172 for (i = 0; i < state->performance_level_count; i++) { 6173 si_convert_mc_reg_table_entry_to_smc(adev, 6174 &state->performance_levels[i], 6175 &mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i]); 6176 } 6177 } 6178 6179 static int si_populate_mc_reg_table(struct amdgpu_device *adev, 6180 struct amdgpu_ps *amdgpu_boot_state) 6181 { 6182 struct si_ps *boot_state = si_get_ps(amdgpu_boot_state); 6183 struct si_power_info *si_pi = si_get_pi(adev); 6184 struct si_ulv_param *ulv = &si_pi->ulv; 6185 SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table; 6186 6187 memset(smc_mc_reg_table, 0, sizeof(SMC_SIslands_MCRegisters)); 6188 6189 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_seq_index, 1); 6190 6191 si_populate_mc_reg_addresses(adev, smc_mc_reg_table); 6192 6193 si_convert_mc_reg_table_entry_to_smc(adev, &boot_state->performance_levels[0], 6194 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_INITIAL_SLOT]); 6195 6196 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0], 6197 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ACPI_SLOT], 6198 si_pi->mc_reg_table.last, 6199 si_pi->mc_reg_table.valid_flag); 6200 6201 if (ulv->supported && ulv->pl.vddc != 0) 6202 si_convert_mc_reg_table_entry_to_smc(adev, &ulv->pl, 6203 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ULV_SLOT]); 6204 else 6205 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0], 6206 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ULV_SLOT], 6207 si_pi->mc_reg_table.last, 6208 si_pi->mc_reg_table.valid_flag); 6209 6210 si_convert_mc_reg_table_to_smc(adev, amdgpu_boot_state, smc_mc_reg_table); 6211 6212 return amdgpu_si_copy_bytes_to_smc(adev, si_pi->mc_reg_table_start, 6213 (u8 *)smc_mc_reg_table, 6214 sizeof(SMC_SIslands_MCRegisters), si_pi->sram_end); 6215 } 6216 6217 static int si_upload_mc_reg_table(struct amdgpu_device *adev, 6218 struct amdgpu_ps *amdgpu_new_state) 6219 { 6220 struct si_ps *new_state = si_get_ps(amdgpu_new_state); 6221 struct si_power_info *si_pi = si_get_pi(adev); 6222 u32 address = si_pi->mc_reg_table_start + 6223 offsetof(SMC_SIslands_MCRegisters, 6224 data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT]); 6225 SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table; 6226 6227 memset(smc_mc_reg_table, 0, sizeof(SMC_SIslands_MCRegisters)); 6228 6229 si_convert_mc_reg_table_to_smc(adev, amdgpu_new_state, smc_mc_reg_table); 6230 6231 return amdgpu_si_copy_bytes_to_smc(adev, address, 6232 (u8 *)&smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT], 6233 sizeof(SMC_SIslands_MCRegisterSet) * new_state->performance_level_count, 6234 si_pi->sram_end); 6235 } 6236 6237 static void si_enable_voltage_control(struct amdgpu_device *adev, bool enable) 6238 { 6239 if (enable) 6240 WREG32_P(mmGENERAL_PWRMGT, GENERAL_PWRMGT__VOLT_PWRMGT_EN_MASK, ~GENERAL_PWRMGT__VOLT_PWRMGT_EN_MASK); 6241 else 6242 WREG32_P(mmGENERAL_PWRMGT, 0, ~GENERAL_PWRMGT__VOLT_PWRMGT_EN_MASK); 6243 } 6244 6245 static enum si_pcie_gen si_get_maximum_link_speed(struct amdgpu_device *adev, 6246 struct amdgpu_ps *amdgpu_state) 6247 { 6248 struct si_ps *state = si_get_ps(amdgpu_state); 6249 int i; 6250 u16 pcie_speed, max_speed = 0; 6251 6252 for (i = 0; i < state->performance_level_count; i++) { 6253 pcie_speed = state->performance_levels[i].pcie_gen; 6254 if (max_speed < pcie_speed) 6255 max_speed = pcie_speed; 6256 } 6257 return max_speed; 6258 } 6259 6260 static u16 si_get_current_pcie_speed(struct amdgpu_device *adev) 6261 { 6262 u32 speed_cntl; 6263 6264 speed_cntl = RREG32_PCIE_PORT(ixPCIE_LC_SPEED_CNTL) & PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK; 6265 speed_cntl >>= PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT; 6266 6267 return (u16)speed_cntl; 6268 } 6269 6270 static void si_request_link_speed_change_before_state_change(struct amdgpu_device *adev, 6271 struct amdgpu_ps *amdgpu_new_state, 6272 struct amdgpu_ps *amdgpu_current_state) 6273 { 6274 struct si_power_info *si_pi = si_get_pi(adev); 6275 enum si_pcie_gen target_link_speed = si_get_maximum_link_speed(adev, amdgpu_new_state); 6276 enum si_pcie_gen current_link_speed; 6277 6278 if (si_pi->force_pcie_gen == SI_PCIE_GEN_INVALID) 6279 current_link_speed = si_get_maximum_link_speed(adev, amdgpu_current_state); 6280 else 6281 current_link_speed = si_pi->force_pcie_gen; 6282 6283 si_pi->force_pcie_gen = SI_PCIE_GEN_INVALID; 6284 si_pi->pspp_notify_required = false; 6285 if (target_link_speed > current_link_speed) { 6286 switch (target_link_speed) { 6287 #if defined(CONFIG_ACPI) 6288 case SI_PCIE_GEN3: 6289 if (amdgpu_acpi_pcie_performance_request(adev, PCIE_PERF_REQ_PECI_GEN3, false) == 0) 6290 break; 6291 si_pi->force_pcie_gen = SI_PCIE_GEN2; 6292 if (current_link_speed == SI_PCIE_GEN2) 6293 break; 6294 fallthrough; 6295 case SI_PCIE_GEN2: 6296 if (amdgpu_acpi_pcie_performance_request(adev, PCIE_PERF_REQ_PECI_GEN2, false) == 0) 6297 break; 6298 fallthrough; 6299 #endif 6300 default: 6301 si_pi->force_pcie_gen = si_get_current_pcie_speed(adev); 6302 break; 6303 } 6304 } else { 6305 if (target_link_speed < current_link_speed) 6306 si_pi->pspp_notify_required = true; 6307 } 6308 } 6309 6310 static void si_notify_link_speed_change_after_state_change(struct amdgpu_device *adev, 6311 struct amdgpu_ps *amdgpu_new_state, 6312 struct amdgpu_ps *amdgpu_current_state) 6313 { 6314 struct si_power_info *si_pi = si_get_pi(adev); 6315 enum si_pcie_gen target_link_speed = si_get_maximum_link_speed(adev, amdgpu_new_state); 6316 u8 request; 6317 6318 if (si_pi->pspp_notify_required) { 6319 if (target_link_speed == SI_PCIE_GEN3) 6320 request = PCIE_PERF_REQ_PECI_GEN3; 6321 else if (target_link_speed == SI_PCIE_GEN2) 6322 request = PCIE_PERF_REQ_PECI_GEN2; 6323 else 6324 request = PCIE_PERF_REQ_PECI_GEN1; 6325 6326 if ((request == PCIE_PERF_REQ_PECI_GEN1) && 6327 (si_get_current_pcie_speed(adev) > 0)) 6328 return; 6329 6330 #if defined(CONFIG_ACPI) 6331 amdgpu_acpi_pcie_performance_request(adev, request, false); 6332 #endif 6333 } 6334 } 6335 6336 #if 0 6337 static int si_ds_request(struct amdgpu_device *adev, 6338 bool ds_status_on, u32 count_write) 6339 { 6340 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); 6341 6342 if (eg_pi->sclk_deep_sleep) { 6343 if (ds_status_on) 6344 return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_CancelThrottleOVRDSCLKDS) == 6345 PPSMC_Result_OK) ? 6346 0 : -EINVAL; 6347 else 6348 return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_ThrottleOVRDSCLKDS) == 6349 PPSMC_Result_OK) ? 0 : -EINVAL; 6350 } 6351 return 0; 6352 } 6353 #endif 6354 6355 static void si_set_max_cu_value(struct amdgpu_device *adev) 6356 { 6357 struct si_power_info *si_pi = si_get_pi(adev); 6358 6359 if (adev->asic_type == CHIP_VERDE) { 6360 switch (adev->pdev->device) { 6361 case 0x6820: 6362 case 0x6825: 6363 case 0x6821: 6364 case 0x6823: 6365 case 0x6827: 6366 si_pi->max_cu = 10; 6367 break; 6368 case 0x682D: 6369 case 0x6824: 6370 case 0x682F: 6371 case 0x6826: 6372 si_pi->max_cu = 8; 6373 break; 6374 case 0x6828: 6375 case 0x6830: 6376 case 0x6831: 6377 case 0x6838: 6378 case 0x6839: 6379 case 0x683D: 6380 si_pi->max_cu = 10; 6381 break; 6382 case 0x683B: 6383 case 0x683F: 6384 case 0x6829: 6385 si_pi->max_cu = 8; 6386 break; 6387 default: 6388 si_pi->max_cu = 0; 6389 break; 6390 } 6391 } else { 6392 si_pi->max_cu = 0; 6393 } 6394 } 6395 6396 static int si_patch_single_dependency_table_based_on_leakage(struct amdgpu_device *adev, 6397 struct amdgpu_clock_voltage_dependency_table *table) 6398 { 6399 u32 i; 6400 int j; 6401 u16 leakage_voltage; 6402 6403 if (table) { 6404 for (i = 0; i < table->count; i++) { 6405 switch (si_get_leakage_voltage_from_leakage_index(adev, 6406 table->entries[i].v, 6407 &leakage_voltage)) { 6408 case 0: 6409 table->entries[i].v = leakage_voltage; 6410 break; 6411 case -EAGAIN: 6412 return -EINVAL; 6413 case -EINVAL: 6414 default: 6415 break; 6416 } 6417 } 6418 6419 for (j = (table->count - 2); j >= 0; j--) { 6420 table->entries[j].v = (table->entries[j].v <= table->entries[j + 1].v) ? 6421 table->entries[j].v : table->entries[j + 1].v; 6422 } 6423 } 6424 return 0; 6425 } 6426 6427 static int si_patch_dependency_tables_based_on_leakage(struct amdgpu_device *adev) 6428 { 6429 int ret = 0; 6430 6431 ret = si_patch_single_dependency_table_based_on_leakage(adev, 6432 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk); 6433 if (ret) 6434 DRM_ERROR("Could not patch vddc_on_sclk leakage table\n"); 6435 ret = si_patch_single_dependency_table_based_on_leakage(adev, 6436 &adev->pm.dpm.dyn_state.vddc_dependency_on_mclk); 6437 if (ret) 6438 DRM_ERROR("Could not patch vddc_on_mclk leakage table\n"); 6439 ret = si_patch_single_dependency_table_based_on_leakage(adev, 6440 &adev->pm.dpm.dyn_state.vddci_dependency_on_mclk); 6441 if (ret) 6442 DRM_ERROR("Could not patch vddci_on_mclk leakage table\n"); 6443 return ret; 6444 } 6445 6446 static void si_set_pcie_lane_width_in_smc(struct amdgpu_device *adev, 6447 struct amdgpu_ps *amdgpu_new_state, 6448 struct amdgpu_ps *amdgpu_current_state) 6449 { 6450 u32 lane_width; 6451 u32 new_lane_width = 6452 ((amdgpu_new_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1; 6453 u32 current_lane_width = 6454 ((amdgpu_current_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1; 6455 6456 if (new_lane_width != current_lane_width) { 6457 amdgpu_set_pcie_lanes(adev, new_lane_width); 6458 lane_width = amdgpu_get_pcie_lanes(adev); 6459 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width); 6460 } 6461 } 6462 6463 static void si_dpm_setup_asic(struct amdgpu_device *adev) 6464 { 6465 si_read_clock_registers(adev); 6466 si_enable_acpi_power_management(adev); 6467 } 6468 6469 static int si_thermal_enable_alert(struct amdgpu_device *adev, 6470 bool enable) 6471 { 6472 u32 thermal_int = RREG32(mmCG_THERMAL_INT); 6473 6474 if (enable) { 6475 PPSMC_Result result; 6476 6477 thermal_int &= ~(CG_THERMAL_INT__THERM_INT_MASK_HIGH_MASK | CG_THERMAL_INT__THERM_INT_MASK_LOW_MASK); 6478 WREG32(mmCG_THERMAL_INT, thermal_int); 6479 result = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_EnableThermalInterrupt); 6480 if (result != PPSMC_Result_OK) { 6481 DRM_DEBUG_KMS("Could not enable thermal interrupts.\n"); 6482 return -EINVAL; 6483 } 6484 } else { 6485 thermal_int |= CG_THERMAL_INT__THERM_INT_MASK_HIGH_MASK | CG_THERMAL_INT__THERM_INT_MASK_LOW_MASK; 6486 WREG32(mmCG_THERMAL_INT, thermal_int); 6487 } 6488 6489 return 0; 6490 } 6491 6492 static int si_thermal_set_temperature_range(struct amdgpu_device *adev, 6493 int min_temp, int max_temp) 6494 { 6495 int low_temp = 0 * 1000; 6496 int high_temp = 255 * 1000; 6497 6498 if (low_temp < min_temp) 6499 low_temp = min_temp; 6500 if (high_temp > max_temp) 6501 high_temp = max_temp; 6502 if (high_temp < low_temp) { 6503 DRM_ERROR("invalid thermal range: %d - %d\n", low_temp, high_temp); 6504 return -EINVAL; 6505 } 6506 6507 WREG32_P(mmCG_THERMAL_INT, (high_temp / 1000) << CG_THERMAL_INT__DIG_THERM_INTH__SHIFT, ~CG_THERMAL_INT__DIG_THERM_INTH_MASK); 6508 WREG32_P(mmCG_THERMAL_INT, (low_temp / 1000) << CG_THERMAL_INT__DIG_THERM_INTL__SHIFT, ~CG_THERMAL_INT__DIG_THERM_INTL_MASK); 6509 WREG32_P(mmCG_THERMAL_CTRL, (high_temp / 1000) << CG_THERMAL_CTRL__DIG_THERM_DPM__SHIFT, ~CG_THERMAL_CTRL__DIG_THERM_DPM_MASK); 6510 6511 adev->pm.dpm.thermal.min_temp = low_temp; 6512 adev->pm.dpm.thermal.max_temp = high_temp; 6513 6514 return 0; 6515 } 6516 6517 static void si_fan_ctrl_set_static_mode(struct amdgpu_device *adev, u32 mode) 6518 { 6519 struct si_power_info *si_pi = si_get_pi(adev); 6520 u32 tmp; 6521 6522 if (si_pi->fan_ctrl_is_in_default_mode) { 6523 tmp = (RREG32(mmCG_FDO_CTRL2) & CG_FDO_CTRL2__FDO_PWM_MODE_MASK) >> CG_FDO_CTRL2__FDO_PWM_MODE__SHIFT; 6524 si_pi->fan_ctrl_default_mode = tmp; 6525 tmp = (RREG32(mmCG_FDO_CTRL2) & CG_FDO_CTRL2__TMIN_MASK) >> CG_FDO_CTRL2__TMIN__SHIFT; 6526 si_pi->t_min = tmp; 6527 si_pi->fan_ctrl_is_in_default_mode = false; 6528 } 6529 6530 tmp = RREG32(mmCG_FDO_CTRL2) & ~CG_FDO_CTRL2__TMIN_MASK; 6531 tmp |= 0 << CG_FDO_CTRL2__TMIN__SHIFT; 6532 WREG32(mmCG_FDO_CTRL2, tmp); 6533 6534 tmp = RREG32(mmCG_FDO_CTRL2) & ~CG_FDO_CTRL2__FDO_PWM_MODE_MASK; 6535 tmp |= mode << CG_FDO_CTRL2__FDO_PWM_MODE__SHIFT; 6536 WREG32(mmCG_FDO_CTRL2, tmp); 6537 } 6538 6539 static int si_thermal_setup_fan_table(struct amdgpu_device *adev) 6540 { 6541 struct si_power_info *si_pi = si_get_pi(adev); 6542 PP_SIslands_FanTable fan_table = { FDO_MODE_HARDWARE }; 6543 u32 duty100; 6544 u32 t_diff1, t_diff2, pwm_diff1, pwm_diff2; 6545 u16 fdo_min, slope1, slope2; 6546 u32 reference_clock, tmp; 6547 int ret; 6548 u64 tmp64; 6549 6550 if (!si_pi->fan_table_start) { 6551 adev->pm.dpm.fan.ucode_fan_control = false; 6552 return 0; 6553 } 6554 6555 duty100 = (RREG32(mmCG_FDO_CTRL1) & CG_FDO_CTRL1__FMAX_DUTY100_MASK) >> CG_FDO_CTRL1__FMAX_DUTY100__SHIFT; 6556 6557 if (duty100 == 0) { 6558 adev->pm.dpm.fan.ucode_fan_control = false; 6559 return 0; 6560 } 6561 6562 tmp64 = (u64)adev->pm.dpm.fan.pwm_min * duty100; 6563 do_div(tmp64, 10000); 6564 fdo_min = (u16)tmp64; 6565 6566 t_diff1 = adev->pm.dpm.fan.t_med - adev->pm.dpm.fan.t_min; 6567 t_diff2 = adev->pm.dpm.fan.t_high - adev->pm.dpm.fan.t_med; 6568 6569 pwm_diff1 = adev->pm.dpm.fan.pwm_med - adev->pm.dpm.fan.pwm_min; 6570 pwm_diff2 = adev->pm.dpm.fan.pwm_high - adev->pm.dpm.fan.pwm_med; 6571 6572 slope1 = (u16)((50 + ((16 * duty100 * pwm_diff1) / t_diff1)) / 100); 6573 slope2 = (u16)((50 + ((16 * duty100 * pwm_diff2) / t_diff2)) / 100); 6574 6575 fan_table.temp_min = cpu_to_be16((50 + adev->pm.dpm.fan.t_min) / 100); 6576 fan_table.temp_med = cpu_to_be16((50 + adev->pm.dpm.fan.t_med) / 100); 6577 fan_table.temp_max = cpu_to_be16((50 + adev->pm.dpm.fan.t_max) / 100); 6578 fan_table.slope1 = cpu_to_be16(slope1); 6579 fan_table.slope2 = cpu_to_be16(slope2); 6580 fan_table.fdo_min = cpu_to_be16(fdo_min); 6581 fan_table.hys_down = cpu_to_be16(adev->pm.dpm.fan.t_hyst); 6582 fan_table.hys_up = cpu_to_be16(1); 6583 fan_table.hys_slope = cpu_to_be16(1); 6584 fan_table.temp_resp_lim = cpu_to_be16(5); 6585 reference_clock = amdgpu_asic_get_xclk(adev); 6586 6587 fan_table.refresh_period = cpu_to_be32((adev->pm.dpm.fan.cycle_delay * 6588 reference_clock) / 1600); 6589 fan_table.fdo_max = cpu_to_be16((u16)duty100); 6590 6591 tmp = (RREG32(mmCG_MULT_THERMAL_CTRL) & CG_MULT_THERMAL_CTRL__TEMP_SEL_MASK) >> CG_MULT_THERMAL_CTRL__TEMP_SEL__SHIFT; 6592 fan_table.temp_src = (uint8_t)tmp; 6593 6594 ret = amdgpu_si_copy_bytes_to_smc(adev, 6595 si_pi->fan_table_start, 6596 (u8 *)(&fan_table), 6597 sizeof(fan_table), 6598 si_pi->sram_end); 6599 6600 if (ret) { 6601 DRM_ERROR("Failed to load fan table to the SMC."); 6602 adev->pm.dpm.fan.ucode_fan_control = false; 6603 } 6604 6605 return ret; 6606 } 6607 6608 static int si_fan_ctrl_start_smc_fan_control(struct amdgpu_device *adev) 6609 { 6610 struct si_power_info *si_pi = si_get_pi(adev); 6611 PPSMC_Result ret; 6612 6613 ret = amdgpu_si_send_msg_to_smc(adev, PPSMC_StartFanControl); 6614 if (ret == PPSMC_Result_OK) { 6615 si_pi->fan_is_controlled_by_smc = true; 6616 return 0; 6617 } else { 6618 return -EINVAL; 6619 } 6620 } 6621 6622 static int si_fan_ctrl_stop_smc_fan_control(struct amdgpu_device *adev) 6623 { 6624 struct si_power_info *si_pi = si_get_pi(adev); 6625 PPSMC_Result ret; 6626 6627 ret = amdgpu_si_send_msg_to_smc(adev, PPSMC_StopFanControl); 6628 6629 if (ret == PPSMC_Result_OK) { 6630 si_pi->fan_is_controlled_by_smc = false; 6631 return 0; 6632 } else { 6633 return -EINVAL; 6634 } 6635 } 6636 6637 static int si_dpm_get_fan_speed_pwm(void *handle, 6638 u32 *speed) 6639 { 6640 u32 duty, duty100; 6641 u64 tmp64; 6642 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 6643 6644 if (!speed) 6645 return -EINVAL; 6646 6647 if (adev->pm.no_fan) 6648 return -ENOENT; 6649 6650 duty100 = (RREG32(mmCG_FDO_CTRL1) & CG_FDO_CTRL1__FMAX_DUTY100_MASK) >> CG_FDO_CTRL1__FMAX_DUTY100__SHIFT; 6651 duty = (RREG32(mmCG_THERMAL_STATUS) & CG_THERMAL_STATUS__FDO_PWM_DUTY_MASK) >> CG_THERMAL_STATUS__FDO_PWM_DUTY__SHIFT; 6652 6653 if (duty100 == 0) 6654 return -EINVAL; 6655 6656 tmp64 = (u64)duty * 255; 6657 do_div(tmp64, duty100); 6658 *speed = min_t(u32, tmp64, 255); 6659 6660 return 0; 6661 } 6662 6663 static int si_dpm_set_fan_speed_pwm(void *handle, 6664 u32 speed) 6665 { 6666 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 6667 struct si_power_info *si_pi = si_get_pi(adev); 6668 u32 tmp; 6669 u32 duty, duty100; 6670 u64 tmp64; 6671 6672 if (adev->pm.no_fan) 6673 return -ENOENT; 6674 6675 if (si_pi->fan_is_controlled_by_smc) 6676 return -EINVAL; 6677 6678 if (speed > 255) 6679 return -EINVAL; 6680 6681 duty100 = (RREG32(mmCG_FDO_CTRL1) & CG_FDO_CTRL1__FMAX_DUTY100_MASK) >> CG_FDO_CTRL1__FMAX_DUTY100__SHIFT; 6682 6683 if (duty100 == 0) 6684 return -EINVAL; 6685 6686 tmp64 = (u64)speed * duty100; 6687 do_div(tmp64, 255); 6688 duty = (u32)tmp64; 6689 6690 tmp = RREG32(mmCG_FDO_CTRL0) & ~CG_FDO_CTRL0__FDO_STATIC_DUTY_MASK; 6691 tmp |= duty << CG_FDO_CTRL0__FDO_STATIC_DUTY__SHIFT; 6692 WREG32(mmCG_FDO_CTRL0, tmp); 6693 6694 return 0; 6695 } 6696 6697 static int si_dpm_set_fan_control_mode(void *handle, u32 mode) 6698 { 6699 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 6700 6701 if (mode == U32_MAX) 6702 return -EINVAL; 6703 6704 if (mode) { 6705 /* stop auto-manage */ 6706 if (adev->pm.dpm.fan.ucode_fan_control) 6707 si_fan_ctrl_stop_smc_fan_control(adev); 6708 si_fan_ctrl_set_static_mode(adev, mode); 6709 } else { 6710 /* restart auto-manage */ 6711 if (adev->pm.dpm.fan.ucode_fan_control) 6712 si_thermal_start_smc_fan_control(adev); 6713 else 6714 si_fan_ctrl_set_default_mode(adev); 6715 } 6716 6717 return 0; 6718 } 6719 6720 static int si_dpm_get_fan_control_mode(void *handle, u32 *fan_mode) 6721 { 6722 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 6723 struct si_power_info *si_pi = si_get_pi(adev); 6724 u32 tmp; 6725 6726 if (!fan_mode) 6727 return -EINVAL; 6728 6729 if (si_pi->fan_is_controlled_by_smc) 6730 return 0; 6731 6732 tmp = RREG32(mmCG_FDO_CTRL2) & CG_FDO_CTRL2__FDO_PWM_MODE_MASK; 6733 *fan_mode = (tmp >> CG_FDO_CTRL2__FDO_PWM_MODE__SHIFT); 6734 6735 return 0; 6736 } 6737 6738 #if 0 6739 static int si_fan_ctrl_get_fan_speed_rpm(struct amdgpu_device *adev, 6740 u32 *speed) 6741 { 6742 u32 tach_period; 6743 u32 xclk = amdgpu_asic_get_xclk(adev); 6744 6745 if (adev->pm.no_fan) 6746 return -ENOENT; 6747 6748 if (adev->pm.fan_pulses_per_revolution == 0) 6749 return -ENOENT; 6750 6751 tach_period = (RREG32(mmCG_TACH_STATUS) & CG_TACH_STATUS__TACH_PERIOD_MASK) >> CG_TACH_STATUS__TACH_PERIOD__SHIFT; 6752 if (tach_period == 0) 6753 return -ENOENT; 6754 6755 *speed = 60 * xclk * 10000 / tach_period; 6756 6757 return 0; 6758 } 6759 6760 static int si_fan_ctrl_set_fan_speed_rpm(struct amdgpu_device *adev, 6761 u32 speed) 6762 { 6763 u32 tach_period, tmp; 6764 u32 xclk = amdgpu_asic_get_xclk(adev); 6765 6766 if (adev->pm.no_fan) 6767 return -ENOENT; 6768 6769 if (adev->pm.fan_pulses_per_revolution == 0) 6770 return -ENOENT; 6771 6772 if ((speed < adev->pm.fan_min_rpm) || 6773 (speed > adev->pm.fan_max_rpm)) 6774 return -EINVAL; 6775 6776 if (adev->pm.dpm.fan.ucode_fan_control) 6777 si_fan_ctrl_stop_smc_fan_control(adev); 6778 6779 tach_period = 60 * xclk * 10000 / (8 * speed); 6780 tmp = RREG32(mmCG_TACH_CTRL) & ~CG_TACH_CTRL__TARGET_PERIOD_MASK; 6781 tmp |= tach_period << CG_TACH_CTRL__TARGET_PERIOD__SHIFT; 6782 WREG32(mmCG_TACH_CTRL, tmp); 6783 6784 si_fan_ctrl_set_static_mode(adev, FDO_PWM_MODE_STATIC_RPM); 6785 6786 return 0; 6787 } 6788 #endif 6789 6790 static void si_fan_ctrl_set_default_mode(struct amdgpu_device *adev) 6791 { 6792 struct si_power_info *si_pi = si_get_pi(adev); 6793 u32 tmp; 6794 6795 if (!si_pi->fan_ctrl_is_in_default_mode) { 6796 tmp = RREG32(mmCG_FDO_CTRL2) & ~CG_FDO_CTRL2__FDO_PWM_MODE_MASK; 6797 tmp |= si_pi->fan_ctrl_default_mode << CG_FDO_CTRL2__FDO_PWM_MODE__SHIFT; 6798 WREG32(mmCG_FDO_CTRL2, tmp); 6799 6800 tmp = RREG32(mmCG_FDO_CTRL2) & ~CG_FDO_CTRL2__TMIN_MASK; 6801 tmp |= si_pi->t_min << CG_FDO_CTRL2__TMIN__SHIFT; 6802 WREG32(mmCG_FDO_CTRL2, tmp); 6803 si_pi->fan_ctrl_is_in_default_mode = true; 6804 } 6805 } 6806 6807 static void si_thermal_start_smc_fan_control(struct amdgpu_device *adev) 6808 { 6809 if (adev->pm.dpm.fan.ucode_fan_control) { 6810 si_fan_ctrl_start_smc_fan_control(adev); 6811 si_fan_ctrl_set_static_mode(adev, FDO_PWM_MODE_STATIC); 6812 } 6813 } 6814 6815 static void si_thermal_initialize(struct amdgpu_device *adev) 6816 { 6817 u32 tmp; 6818 6819 if (adev->pm.fan_pulses_per_revolution) { 6820 tmp = RREG32(mmCG_TACH_CTRL) & ~CG_TACH_CTRL__EDGE_PER_REV_MASK; 6821 tmp |= (adev->pm.fan_pulses_per_revolution -1) << CG_TACH_CTRL__EDGE_PER_REV__SHIFT; 6822 WREG32(mmCG_TACH_CTRL, tmp); 6823 } 6824 6825 tmp = RREG32(mmCG_FDO_CTRL2) & ~CG_FDO_CTRL2__TACH_PWM_RESP_RATE_MASK; 6826 tmp |= 0x28 << CG_FDO_CTRL2__TACH_PWM_RESP_RATE__SHIFT; 6827 WREG32(mmCG_FDO_CTRL2, tmp); 6828 } 6829 6830 static int si_thermal_start_thermal_controller(struct amdgpu_device *adev) 6831 { 6832 int ret; 6833 6834 si_thermal_initialize(adev); 6835 ret = si_thermal_set_temperature_range(adev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX); 6836 if (ret) 6837 return ret; 6838 ret = si_thermal_enable_alert(adev, true); 6839 if (ret) 6840 return ret; 6841 if (adev->pm.dpm.fan.ucode_fan_control) { 6842 ret = si_halt_smc(adev); 6843 if (ret) 6844 return ret; 6845 ret = si_thermal_setup_fan_table(adev); 6846 if (ret) 6847 return ret; 6848 ret = si_resume_smc(adev); 6849 if (ret) 6850 return ret; 6851 si_thermal_start_smc_fan_control(adev); 6852 } 6853 6854 return 0; 6855 } 6856 6857 static void si_thermal_stop_thermal_controller(struct amdgpu_device *adev) 6858 { 6859 if (!adev->pm.no_fan) { 6860 si_fan_ctrl_set_default_mode(adev); 6861 si_fan_ctrl_stop_smc_fan_control(adev); 6862 } 6863 } 6864 6865 static int si_dpm_enable(struct amdgpu_device *adev) 6866 { 6867 struct rv7xx_power_info *pi = rv770_get_pi(adev); 6868 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); 6869 struct si_power_info *si_pi = si_get_pi(adev); 6870 struct amdgpu_ps *boot_ps = adev->pm.dpm.boot_ps; 6871 int ret; 6872 6873 if (amdgpu_si_is_smc_running(adev)) 6874 return -EINVAL; 6875 if (pi->voltage_control || si_pi->voltage_control_svi2) 6876 si_enable_voltage_control(adev, true); 6877 if (pi->mvdd_control) 6878 si_get_mvdd_configuration(adev); 6879 if (pi->voltage_control || si_pi->voltage_control_svi2) { 6880 ret = si_construct_voltage_tables(adev); 6881 if (ret) { 6882 DRM_ERROR("si_construct_voltage_tables failed\n"); 6883 return ret; 6884 } 6885 } 6886 if (eg_pi->dynamic_ac_timing) { 6887 ret = si_initialize_mc_reg_table(adev); 6888 if (ret) 6889 eg_pi->dynamic_ac_timing = false; 6890 } 6891 if (pi->dynamic_ss) 6892 si_enable_spread_spectrum(adev, true); 6893 if (pi->thermal_protection) 6894 si_enable_thermal_protection(adev, true); 6895 si_setup_bsp(adev); 6896 si_program_git(adev); 6897 si_program_tp(adev); 6898 si_program_tpp(adev); 6899 si_program_sstp(adev); 6900 si_enable_display_gap(adev); 6901 si_program_vc(adev); 6902 ret = si_upload_firmware(adev); 6903 if (ret) { 6904 DRM_ERROR("si_upload_firmware failed\n"); 6905 return ret; 6906 } 6907 ret = si_process_firmware_header(adev); 6908 if (ret) { 6909 DRM_ERROR("si_process_firmware_header failed\n"); 6910 return ret; 6911 } 6912 ret = si_initial_switch_from_arb_f0_to_f1(adev); 6913 if (ret) { 6914 DRM_ERROR("si_initial_switch_from_arb_f0_to_f1 failed\n"); 6915 return ret; 6916 } 6917 ret = si_init_smc_table(adev); 6918 if (ret) { 6919 DRM_ERROR("si_init_smc_table failed\n"); 6920 return ret; 6921 } 6922 ret = si_init_smc_spll_table(adev); 6923 if (ret) { 6924 DRM_ERROR("si_init_smc_spll_table failed\n"); 6925 return ret; 6926 } 6927 ret = si_init_arb_table_index(adev); 6928 if (ret) { 6929 DRM_ERROR("si_init_arb_table_index failed\n"); 6930 return ret; 6931 } 6932 if (eg_pi->dynamic_ac_timing) { 6933 ret = si_populate_mc_reg_table(adev, boot_ps); 6934 if (ret) { 6935 DRM_ERROR("si_populate_mc_reg_table failed\n"); 6936 return ret; 6937 } 6938 } 6939 ret = si_initialize_smc_cac_tables(adev); 6940 if (ret) { 6941 DRM_ERROR("si_initialize_smc_cac_tables failed\n"); 6942 return ret; 6943 } 6944 ret = si_initialize_hardware_cac_manager(adev); 6945 if (ret) { 6946 DRM_ERROR("si_initialize_hardware_cac_manager failed\n"); 6947 return ret; 6948 } 6949 ret = si_initialize_smc_dte_tables(adev); 6950 if (ret) { 6951 DRM_ERROR("si_initialize_smc_dte_tables failed\n"); 6952 return ret; 6953 } 6954 ret = si_populate_smc_tdp_limits(adev, boot_ps); 6955 if (ret) { 6956 DRM_ERROR("si_populate_smc_tdp_limits failed\n"); 6957 return ret; 6958 } 6959 ret = si_populate_smc_tdp_limits_2(adev, boot_ps); 6960 if (ret) { 6961 DRM_ERROR("si_populate_smc_tdp_limits_2 failed\n"); 6962 return ret; 6963 } 6964 si_program_response_times(adev); 6965 si_program_ds_registers(adev); 6966 si_dpm_start_smc(adev); 6967 ret = si_notify_smc_display_change(adev, false); 6968 if (ret) { 6969 DRM_ERROR("si_notify_smc_display_change failed\n"); 6970 return ret; 6971 } 6972 si_enable_sclk_control(adev, true); 6973 si_start_dpm(adev); 6974 6975 si_enable_auto_throttle_source(adev, SI_DPM_AUTO_THROTTLE_SRC_THERMAL, true); 6976 si_thermal_start_thermal_controller(adev); 6977 6978 ni_update_current_ps(adev, boot_ps); 6979 6980 return 0; 6981 } 6982 6983 static int si_set_temperature_range(struct amdgpu_device *adev) 6984 { 6985 int ret; 6986 6987 ret = si_thermal_enable_alert(adev, false); 6988 if (ret) 6989 return ret; 6990 ret = si_thermal_set_temperature_range(adev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX); 6991 if (ret) 6992 return ret; 6993 ret = si_thermal_enable_alert(adev, true); 6994 if (ret) 6995 return ret; 6996 6997 return ret; 6998 } 6999 7000 static void si_dpm_disable(struct amdgpu_device *adev) 7001 { 7002 struct rv7xx_power_info *pi = rv770_get_pi(adev); 7003 struct amdgpu_ps *boot_ps = adev->pm.dpm.boot_ps; 7004 7005 if (!amdgpu_si_is_smc_running(adev)) 7006 return; 7007 si_thermal_stop_thermal_controller(adev); 7008 si_disable_ulv(adev); 7009 si_clear_vc(adev); 7010 if (pi->thermal_protection) 7011 si_enable_thermal_protection(adev, false); 7012 si_enable_power_containment(adev, boot_ps, false); 7013 si_enable_smc_cac(adev, boot_ps, false); 7014 si_enable_spread_spectrum(adev, false); 7015 si_enable_auto_throttle_source(adev, SI_DPM_AUTO_THROTTLE_SRC_THERMAL, false); 7016 si_stop_dpm(adev); 7017 si_reset_to_default(adev); 7018 si_dpm_stop_smc(adev); 7019 si_force_switch_to_arb_f0(adev); 7020 7021 ni_update_current_ps(adev, boot_ps); 7022 } 7023 7024 static int si_dpm_pre_set_power_state(void *handle) 7025 { 7026 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7027 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); 7028 struct amdgpu_ps requested_ps = *adev->pm.dpm.requested_ps; 7029 struct amdgpu_ps *new_ps = &requested_ps; 7030 7031 ni_update_requested_ps(adev, new_ps); 7032 si_apply_state_adjust_rules(adev, &eg_pi->requested_rps); 7033 7034 return 0; 7035 } 7036 7037 static int si_power_control_set_level(struct amdgpu_device *adev) 7038 { 7039 struct amdgpu_ps *new_ps = adev->pm.dpm.requested_ps; 7040 int ret; 7041 7042 ret = si_restrict_performance_levels_before_switch(adev); 7043 if (ret) 7044 return ret; 7045 ret = si_halt_smc(adev); 7046 if (ret) 7047 return ret; 7048 ret = si_populate_smc_tdp_limits(adev, new_ps); 7049 if (ret) 7050 return ret; 7051 ret = si_populate_smc_tdp_limits_2(adev, new_ps); 7052 if (ret) 7053 return ret; 7054 ret = si_resume_smc(adev); 7055 if (ret) 7056 return ret; 7057 return si_set_sw_state(adev); 7058 } 7059 7060 static void si_set_vce_clock(struct amdgpu_device *adev, 7061 struct amdgpu_ps *new_rps, 7062 struct amdgpu_ps *old_rps) 7063 { 7064 if ((old_rps->evclk != new_rps->evclk) || 7065 (old_rps->ecclk != new_rps->ecclk)) { 7066 /* Turn the clocks on when encoding, off otherwise */ 7067 dev_dbg(adev->dev, "set VCE clocks: %u, %u\n", new_rps->evclk, new_rps->ecclk); 7068 7069 if (new_rps->evclk || new_rps->ecclk) { 7070 amdgpu_asic_set_vce_clocks(adev, new_rps->evclk, new_rps->ecclk); 7071 amdgpu_device_ip_set_clockgating_state( 7072 adev, AMD_IP_BLOCK_TYPE_VCE, AMD_CG_STATE_UNGATE); 7073 amdgpu_device_ip_set_powergating_state( 7074 adev, AMD_IP_BLOCK_TYPE_VCE, AMD_PG_STATE_UNGATE); 7075 } else { 7076 amdgpu_device_ip_set_powergating_state( 7077 adev, AMD_IP_BLOCK_TYPE_VCE, AMD_PG_STATE_GATE); 7078 amdgpu_device_ip_set_clockgating_state( 7079 adev, AMD_IP_BLOCK_TYPE_VCE, AMD_CG_STATE_GATE); 7080 amdgpu_asic_set_vce_clocks(adev, 0, 0); 7081 } 7082 } 7083 } 7084 7085 static int si_dpm_set_power_state(void *handle) 7086 { 7087 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7088 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); 7089 struct amdgpu_ps *new_ps = &eg_pi->requested_rps; 7090 struct amdgpu_ps *old_ps = &eg_pi->current_rps; 7091 int ret; 7092 7093 ret = si_disable_ulv(adev); 7094 if (ret) { 7095 DRM_ERROR("si_disable_ulv failed\n"); 7096 return ret; 7097 } 7098 ret = si_restrict_performance_levels_before_switch(adev); 7099 if (ret) { 7100 DRM_ERROR("si_restrict_performance_levels_before_switch failed\n"); 7101 return ret; 7102 } 7103 if (eg_pi->pcie_performance_request) 7104 si_request_link_speed_change_before_state_change(adev, new_ps, old_ps); 7105 ni_set_uvd_clock_before_set_eng_clock(adev, new_ps, old_ps); 7106 ret = si_enable_power_containment(adev, new_ps, false); 7107 if (ret) { 7108 DRM_ERROR("si_enable_power_containment failed\n"); 7109 return ret; 7110 } 7111 ret = si_enable_smc_cac(adev, new_ps, false); 7112 if (ret) { 7113 DRM_ERROR("si_enable_smc_cac failed\n"); 7114 return ret; 7115 } 7116 ret = si_halt_smc(adev); 7117 if (ret) { 7118 DRM_ERROR("si_halt_smc failed\n"); 7119 return ret; 7120 } 7121 ret = si_upload_sw_state(adev, new_ps); 7122 if (ret) { 7123 DRM_ERROR("si_upload_sw_state failed\n"); 7124 return ret; 7125 } 7126 ret = si_upload_smc_data(adev); 7127 if (ret) { 7128 DRM_ERROR("si_upload_smc_data failed\n"); 7129 return ret; 7130 } 7131 ret = si_upload_ulv_state(adev); 7132 if (ret) { 7133 DRM_ERROR("si_upload_ulv_state failed\n"); 7134 return ret; 7135 } 7136 if (eg_pi->dynamic_ac_timing) { 7137 ret = si_upload_mc_reg_table(adev, new_ps); 7138 if (ret) { 7139 DRM_ERROR("si_upload_mc_reg_table failed\n"); 7140 return ret; 7141 } 7142 } 7143 ret = si_program_memory_timing_parameters(adev, new_ps); 7144 if (ret) { 7145 DRM_ERROR("si_program_memory_timing_parameters failed\n"); 7146 return ret; 7147 } 7148 si_set_pcie_lane_width_in_smc(adev, new_ps, old_ps); 7149 7150 ret = si_resume_smc(adev); 7151 if (ret) { 7152 DRM_ERROR("si_resume_smc failed\n"); 7153 return ret; 7154 } 7155 ret = si_set_sw_state(adev); 7156 if (ret) { 7157 DRM_ERROR("si_set_sw_state failed\n"); 7158 return ret; 7159 } 7160 ni_set_uvd_clock_after_set_eng_clock(adev, new_ps, old_ps); 7161 si_set_vce_clock(adev, new_ps, old_ps); 7162 if (eg_pi->pcie_performance_request) 7163 si_notify_link_speed_change_after_state_change(adev, new_ps, old_ps); 7164 ret = si_set_power_state_conditionally_enable_ulv(adev, new_ps); 7165 if (ret) { 7166 DRM_ERROR("si_set_power_state_conditionally_enable_ulv failed\n"); 7167 return ret; 7168 } 7169 ret = si_enable_smc_cac(adev, new_ps, true); 7170 if (ret) { 7171 DRM_ERROR("si_enable_smc_cac failed\n"); 7172 return ret; 7173 } 7174 ret = si_enable_power_containment(adev, new_ps, true); 7175 if (ret) { 7176 DRM_ERROR("si_enable_power_containment failed\n"); 7177 return ret; 7178 } 7179 7180 ret = si_power_control_set_level(adev); 7181 if (ret) { 7182 DRM_ERROR("si_power_control_set_level failed\n"); 7183 return ret; 7184 } 7185 7186 return 0; 7187 } 7188 7189 static void si_dpm_post_set_power_state(void *handle) 7190 { 7191 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7192 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); 7193 struct amdgpu_ps *new_ps = &eg_pi->requested_rps; 7194 7195 ni_update_current_ps(adev, new_ps); 7196 } 7197 7198 #if 0 7199 void si_dpm_reset_asic(struct amdgpu_device *adev) 7200 { 7201 si_restrict_performance_levels_before_switch(adev); 7202 si_disable_ulv(adev); 7203 si_set_boot_state(adev); 7204 } 7205 #endif 7206 7207 static void si_dpm_display_configuration_changed(void *handle) 7208 { 7209 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7210 7211 si_program_display_gap(adev); 7212 } 7213 7214 7215 static void si_parse_pplib_non_clock_info(struct amdgpu_device *adev, 7216 struct amdgpu_ps *rps, 7217 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info, 7218 u8 table_rev) 7219 { 7220 rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings); 7221 rps->class = le16_to_cpu(non_clock_info->usClassification); 7222 rps->class2 = le16_to_cpu(non_clock_info->usClassification2); 7223 7224 if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) { 7225 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK); 7226 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK); 7227 } else if (r600_is_uvd_state(rps->class, rps->class2)) { 7228 rps->vclk = RV770_DEFAULT_VCLK_FREQ; 7229 rps->dclk = RV770_DEFAULT_DCLK_FREQ; 7230 } else { 7231 rps->vclk = 0; 7232 rps->dclk = 0; 7233 } 7234 7235 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) 7236 adev->pm.dpm.boot_ps = rps; 7237 if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE) 7238 adev->pm.dpm.uvd_ps = rps; 7239 } 7240 7241 static void si_update_limits(struct amdgpu_clock_and_voltage_limits *limits, 7242 struct rv7xx_pl *pl) 7243 { 7244 if (pl->sclk > limits->sclk) 7245 limits->sclk = pl->sclk; 7246 if (pl->mclk > limits->mclk) 7247 limits->mclk = pl->mclk; 7248 if (pl->vddc > limits->vddc) 7249 limits->vddc = pl->vddc; 7250 if (pl->vddci > limits->vddci) 7251 limits->vddci = pl->vddci; 7252 } 7253 7254 static void si_parse_pplib_clock_info(struct amdgpu_device *adev, 7255 struct amdgpu_ps *rps, int index, 7256 union pplib_clock_info *clock_info) 7257 { 7258 struct rv7xx_power_info *pi = rv770_get_pi(adev); 7259 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); 7260 struct si_power_info *si_pi = si_get_pi(adev); 7261 struct si_ps *ps = si_get_ps(rps); 7262 u16 leakage_voltage; 7263 struct rv7xx_pl *pl = &ps->performance_levels[index]; 7264 int ret; 7265 7266 ps->performance_level_count = index + 1; 7267 7268 pl->sclk = le16_to_cpu(clock_info->si.usEngineClockLow); 7269 pl->sclk |= clock_info->si.ucEngineClockHigh << 16; 7270 pl->mclk = le16_to_cpu(clock_info->si.usMemoryClockLow); 7271 pl->mclk |= clock_info->si.ucMemoryClockHigh << 16; 7272 7273 pl->vddc = le16_to_cpu(clock_info->si.usVDDC); 7274 pl->vddci = le16_to_cpu(clock_info->si.usVDDCI); 7275 pl->flags = le32_to_cpu(clock_info->si.ulFlags); 7276 pl->pcie_gen = si_gen_pcie_gen_support(adev, 7277 si_pi->sys_pcie_mask, 7278 si_pi->boot_pcie_gen, 7279 clock_info->si.ucPCIEGen); 7280 7281 /* patch up vddc if necessary */ 7282 ret = si_get_leakage_voltage_from_leakage_index(adev, pl->vddc, 7283 &leakage_voltage); 7284 if (ret == 0) 7285 pl->vddc = leakage_voltage; 7286 7287 if (rps->class & ATOM_PPLIB_CLASSIFICATION_ACPI) { 7288 pi->acpi_vddc = pl->vddc; 7289 eg_pi->acpi_vddci = pl->vddci; 7290 si_pi->acpi_pcie_gen = pl->pcie_gen; 7291 } 7292 7293 if ((rps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV) && 7294 index == 0) { 7295 /* XXX disable for A0 tahiti */ 7296 si_pi->ulv.supported = false; 7297 si_pi->ulv.pl = *pl; 7298 si_pi->ulv.one_pcie_lane_in_ulv = false; 7299 si_pi->ulv.volt_change_delay = SISLANDS_ULVVOLTAGECHANGEDELAY_DFLT; 7300 si_pi->ulv.cg_ulv_parameter = SISLANDS_CGULVPARAMETER_DFLT; 7301 si_pi->ulv.cg_ulv_control = SISLANDS_CGULVCONTROL_DFLT; 7302 } 7303 7304 if (pi->min_vddc_in_table > pl->vddc) 7305 pi->min_vddc_in_table = pl->vddc; 7306 7307 if (pi->max_vddc_in_table < pl->vddc) 7308 pi->max_vddc_in_table = pl->vddc; 7309 7310 /* patch up boot state */ 7311 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) { 7312 u16 vddc, vddci, mvdd; 7313 amdgpu_atombios_get_default_voltages(adev, &vddc, &vddci, &mvdd); 7314 pl->mclk = adev->clock.default_mclk; 7315 pl->sclk = adev->clock.default_sclk; 7316 pl->vddc = vddc; 7317 pl->vddci = vddci; 7318 si_pi->mvdd_bootup_value = mvdd; 7319 } 7320 7321 /* 7322 * Update maximum allowed clock limits. 7323 * VBIOS can contain conflicting values between: 7324 * - the maximum allowed clocks and voltages on AC or DC 7325 * - the clocks and voltages in power states on AC or DC 7326 * 7327 * Assume that the AC limits are the maximum of all power states, 7328 * and the DC limits are the maximum of battery power states. 7329 */ 7330 si_update_limits(&adev->pm.dpm.dyn_state.max_clock_voltage_on_ac, pl); 7331 if ((rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) == 7332 ATOM_PPLIB_CLASSIFICATION_UI_BATTERY) 7333 si_update_limits(&adev->pm.dpm.dyn_state.max_clock_voltage_on_dc, pl); 7334 } 7335 7336 union pplib_power_state { 7337 struct _ATOM_PPLIB_STATE v1; 7338 struct _ATOM_PPLIB_STATE_V2 v2; 7339 }; 7340 7341 static int si_parse_power_table(struct amdgpu_device *adev) 7342 { 7343 struct amdgpu_mode_info *mode_info = &adev->mode_info; 7344 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info; 7345 union pplib_power_state *power_state; 7346 int i, j, k, non_clock_array_index, clock_array_index; 7347 union pplib_clock_info *clock_info; 7348 struct _StateArray *state_array; 7349 struct _ClockInfoArray *clock_info_array; 7350 struct _NonClockInfoArray *non_clock_info_array; 7351 union power_info *power_info; 7352 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo); 7353 u16 data_offset; 7354 u8 frev, crev; 7355 u8 *power_state_offset; 7356 struct si_ps *ps; 7357 7358 if (!amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL, 7359 &frev, &crev, &data_offset)) 7360 return -EINVAL; 7361 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset); 7362 7363 amdgpu_add_thermal_controller(adev); 7364 7365 state_array = (struct _StateArray *) 7366 (mode_info->atom_context->bios + data_offset + 7367 le16_to_cpu(power_info->pplib.usStateArrayOffset)); 7368 clock_info_array = (struct _ClockInfoArray *) 7369 (mode_info->atom_context->bios + data_offset + 7370 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset)); 7371 non_clock_info_array = (struct _NonClockInfoArray *) 7372 (mode_info->atom_context->bios + data_offset + 7373 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset)); 7374 7375 adev->pm.dpm.ps = kzalloc_objs(struct amdgpu_ps, 7376 state_array->ucNumEntries); 7377 if (!adev->pm.dpm.ps) 7378 return -ENOMEM; 7379 power_state_offset = (u8 *)state_array->states; 7380 for (adev->pm.dpm.num_ps = 0, i = 0; i < state_array->ucNumEntries; i++) { 7381 u8 *idx; 7382 power_state = (union pplib_power_state *)power_state_offset; 7383 non_clock_array_index = power_state->v2.nonClockInfoIndex; 7384 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *) 7385 &non_clock_info_array->nonClockInfo[non_clock_array_index]; 7386 ps = kzalloc_obj(struct si_ps); 7387 if (ps == NULL) 7388 return -ENOMEM; 7389 adev->pm.dpm.ps[i].ps_priv = ps; 7390 si_parse_pplib_non_clock_info(adev, &adev->pm.dpm.ps[i], 7391 non_clock_info, 7392 non_clock_info_array->ucEntrySize); 7393 k = 0; 7394 idx = (u8 *)&power_state->v2.clockInfoIndex[0]; 7395 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) { 7396 clock_array_index = idx[j]; 7397 if (clock_array_index >= clock_info_array->ucNumEntries) 7398 continue; 7399 if (k >= SISLANDS_MAX_HARDWARE_POWERLEVELS) 7400 break; 7401 clock_info = (union pplib_clock_info *) 7402 ((u8 *)&clock_info_array->clockInfo[0] + 7403 (clock_array_index * clock_info_array->ucEntrySize)); 7404 si_parse_pplib_clock_info(adev, 7405 &adev->pm.dpm.ps[i], k, 7406 clock_info); 7407 k++; 7408 } 7409 power_state_offset += 2 + power_state->v2.ucNumDPMLevels; 7410 adev->pm.dpm.num_ps++; 7411 } 7412 7413 /* fill in the vce power states */ 7414 for (i = 0; i < adev->pm.dpm.num_of_vce_states; i++) { 7415 u32 sclk, mclk; 7416 clock_array_index = adev->pm.dpm.vce_states[i].clk_idx; 7417 clock_info = (union pplib_clock_info *) 7418 &clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize]; 7419 sclk = le16_to_cpu(clock_info->si.usEngineClockLow); 7420 sclk |= clock_info->si.ucEngineClockHigh << 16; 7421 mclk = le16_to_cpu(clock_info->si.usMemoryClockLow); 7422 mclk |= clock_info->si.ucMemoryClockHigh << 16; 7423 adev->pm.dpm.vce_states[i].sclk = sclk; 7424 adev->pm.dpm.vce_states[i].mclk = mclk; 7425 } 7426 7427 return 0; 7428 } 7429 7430 static int si_dpm_init(struct amdgpu_device *adev) 7431 { 7432 struct rv7xx_power_info *pi; 7433 struct evergreen_power_info *eg_pi; 7434 struct ni_power_info *ni_pi; 7435 struct si_power_info *si_pi; 7436 struct atom_clock_dividers dividers; 7437 int ret; 7438 7439 si_pi = kzalloc_obj(struct si_power_info); 7440 if (si_pi == NULL) 7441 return -ENOMEM; 7442 adev->pm.dpm.priv = si_pi; 7443 ni_pi = &si_pi->ni; 7444 eg_pi = &ni_pi->eg; 7445 pi = &eg_pi->rv7xx; 7446 7447 si_pi->sys_pcie_mask = 7448 adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_MASK; 7449 si_pi->force_pcie_gen = SI_PCIE_GEN_INVALID; 7450 si_pi->boot_pcie_gen = si_get_current_pcie_speed(adev); 7451 7452 si_set_max_cu_value(adev); 7453 7454 rv770_get_max_vddc(adev); 7455 si_get_leakage_vddc(adev); 7456 si_patch_dependency_tables_based_on_leakage(adev); 7457 7458 pi->acpi_vddc = 0; 7459 eg_pi->acpi_vddci = 0; 7460 pi->min_vddc_in_table = 0; 7461 pi->max_vddc_in_table = 0; 7462 7463 ret = amdgpu_get_platform_caps(adev); 7464 if (ret) 7465 return ret; 7466 7467 ret = amdgpu_parse_extended_power_table(adev); 7468 if (ret) 7469 return ret; 7470 7471 ret = si_parse_power_table(adev); 7472 if (ret) 7473 return ret; 7474 7475 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries = 7476 kzalloc_objs(struct amdgpu_clock_voltage_dependency_entry, 4); 7477 if (!adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries) 7478 return -ENOMEM; 7479 7480 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count = 4; 7481 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].clk = 0; 7482 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].v = 0; 7483 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].clk = 36000; 7484 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].v = 720; 7485 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].clk = 54000; 7486 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].v = 810; 7487 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].clk = 72000; 7488 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].v = 900; 7489 7490 if (adev->pm.dpm.voltage_response_time == 0) 7491 adev->pm.dpm.voltage_response_time = R600_VOLTAGERESPONSETIME_DFLT; 7492 if (adev->pm.dpm.backbias_response_time == 0) 7493 adev->pm.dpm.backbias_response_time = R600_BACKBIASRESPONSETIME_DFLT; 7494 7495 ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_ENGINE_PLL_PARAM, 7496 0, false, ÷rs); 7497 if (ret) 7498 pi->ref_div = dividers.ref_div + 1; 7499 else 7500 pi->ref_div = R600_REFERENCEDIVIDER_DFLT; 7501 7502 eg_pi->smu_uvd_hs = false; 7503 7504 pi->mclk_strobe_mode_threshold = 40000; 7505 if (si_is_special_1gb_platform(adev)) 7506 pi->mclk_stutter_mode_threshold = 0; 7507 else 7508 pi->mclk_stutter_mode_threshold = pi->mclk_strobe_mode_threshold; 7509 pi->mclk_edc_enable_threshold = 40000; 7510 eg_pi->mclk_edc_wr_enable_threshold = 40000; 7511 7512 ni_pi->mclk_rtt_mode_threshold = eg_pi->mclk_edc_wr_enable_threshold; 7513 7514 pi->voltage_control = 7515 amdgpu_atombios_is_voltage_gpio(adev, SET_VOLTAGE_TYPE_ASIC_VDDC, 7516 VOLTAGE_OBJ_GPIO_LUT); 7517 if (!pi->voltage_control) { 7518 si_pi->voltage_control_svi2 = 7519 amdgpu_atombios_is_voltage_gpio(adev, SET_VOLTAGE_TYPE_ASIC_VDDC, 7520 VOLTAGE_OBJ_SVID2); 7521 if (si_pi->voltage_control_svi2) 7522 amdgpu_atombios_get_svi2_info(adev, SET_VOLTAGE_TYPE_ASIC_VDDC, 7523 &si_pi->svd_gpio_id, &si_pi->svc_gpio_id); 7524 } 7525 7526 pi->mvdd_control = 7527 amdgpu_atombios_is_voltage_gpio(adev, SET_VOLTAGE_TYPE_ASIC_MVDDC, 7528 VOLTAGE_OBJ_GPIO_LUT); 7529 7530 eg_pi->vddci_control = 7531 amdgpu_atombios_is_voltage_gpio(adev, SET_VOLTAGE_TYPE_ASIC_VDDCI, 7532 VOLTAGE_OBJ_GPIO_LUT); 7533 if (!eg_pi->vddci_control) 7534 si_pi->vddci_control_svi2 = 7535 amdgpu_atombios_is_voltage_gpio(adev, SET_VOLTAGE_TYPE_ASIC_VDDCI, 7536 VOLTAGE_OBJ_SVID2); 7537 7538 si_pi->vddc_phase_shed_control = 7539 amdgpu_atombios_is_voltage_gpio(adev, SET_VOLTAGE_TYPE_ASIC_VDDC, 7540 VOLTAGE_OBJ_PHASE_LUT); 7541 7542 rv770_get_engine_memory_ss(adev); 7543 7544 pi->asi = RV770_ASI_DFLT; 7545 pi->pasi = CYPRESS_HASI_DFLT; 7546 pi->vrc = SISLANDS_VRC_DFLT; 7547 7548 eg_pi->sclk_deep_sleep = true; 7549 si_pi->sclk_deep_sleep_above_low = false; 7550 7551 if (adev->pm.int_thermal_type != THERMAL_TYPE_NONE) 7552 pi->thermal_protection = true; 7553 else 7554 pi->thermal_protection = false; 7555 7556 eg_pi->dynamic_ac_timing = true; 7557 7558 #if defined(CONFIG_ACPI) 7559 eg_pi->pcie_performance_request = 7560 amdgpu_acpi_is_pcie_performance_request_supported(adev); 7561 #else 7562 eg_pi->pcie_performance_request = false; 7563 #endif 7564 7565 si_pi->sram_end = SMC_RAM_END; 7566 7567 adev->pm.dpm.dyn_state.mclk_sclk_ratio = 4; 7568 adev->pm.dpm.dyn_state.sclk_mclk_delta = 15000; 7569 adev->pm.dpm.dyn_state.vddc_vddci_delta = 200; 7570 adev->pm.dpm.dyn_state.valid_sclk_values.count = 0; 7571 adev->pm.dpm.dyn_state.valid_sclk_values.values = NULL; 7572 adev->pm.dpm.dyn_state.valid_mclk_values.count = 0; 7573 adev->pm.dpm.dyn_state.valid_mclk_values.values = NULL; 7574 7575 si_initialize_powertune_defaults(adev); 7576 7577 /* make sure dc limits are valid */ 7578 if ((adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk == 0) || 7579 (adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk == 0)) 7580 adev->pm.dpm.dyn_state.max_clock_voltage_on_dc = 7581 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac; 7582 7583 si_pi->fan_ctrl_is_in_default_mode = true; 7584 7585 return 0; 7586 } 7587 7588 static void si_dpm_fini(struct amdgpu_device *adev) 7589 { 7590 int i; 7591 7592 if (adev->pm.dpm.ps) 7593 for (i = 0; i < adev->pm.dpm.num_ps; i++) 7594 kfree(adev->pm.dpm.ps[i].ps_priv); 7595 kfree(adev->pm.dpm.ps); 7596 kfree(adev->pm.dpm.priv); 7597 kfree(adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries); 7598 amdgpu_free_extended_power_table(adev); 7599 } 7600 7601 static void si_dpm_debugfs_print_current_performance_level(void *handle, 7602 struct seq_file *m) 7603 { 7604 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7605 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); 7606 struct amdgpu_ps *rps = &eg_pi->current_rps; 7607 struct si_ps *ps = si_get_ps(rps); 7608 struct rv7xx_pl *pl; 7609 u32 current_index = 7610 (RREG32(mmTARGET_AND_CURRENT_PROFILE_INDEX) & TARGET_AND_CURRENT_PROFILE_INDEX__CURRENT_STATE_INDEX_MASK) >> 7611 TARGET_AND_CURRENT_PROFILE_INDEX__CURRENT_STATE_INDEX__SHIFT; 7612 7613 if (current_index >= ps->performance_level_count) { 7614 seq_printf(m, "invalid dpm profile %d\n", current_index); 7615 } else { 7616 pl = &ps->performance_levels[current_index]; 7617 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); 7618 seq_printf(m, "vce evclk: %d ecclk: %d\n", rps->evclk, rps->ecclk); 7619 seq_printf(m, "power level %d sclk: %u mclk: %u vddc: %u vddci: %u pcie gen: %u\n", 7620 current_index, pl->sclk, pl->mclk, pl->vddc, pl->vddci, pl->pcie_gen + 1); 7621 } 7622 } 7623 7624 static int si_dpm_set_interrupt_state(struct amdgpu_device *adev, 7625 struct amdgpu_irq_src *source, 7626 unsigned type, 7627 enum amdgpu_interrupt_state state) 7628 { 7629 u32 cg_thermal_int; 7630 7631 switch (type) { 7632 case AMDGPU_THERMAL_IRQ_LOW_TO_HIGH: 7633 switch (state) { 7634 case AMDGPU_IRQ_STATE_DISABLE: 7635 cg_thermal_int = RREG32_SMC(mmCG_THERMAL_INT); 7636 cg_thermal_int |= CG_THERMAL_INT__THERM_INT_MASK_HIGH_MASK; 7637 WREG32(mmCG_THERMAL_INT, cg_thermal_int); 7638 break; 7639 case AMDGPU_IRQ_STATE_ENABLE: 7640 cg_thermal_int = RREG32_SMC(mmCG_THERMAL_INT); 7641 cg_thermal_int &= ~CG_THERMAL_INT__THERM_INT_MASK_HIGH_MASK; 7642 WREG32(mmCG_THERMAL_INT, cg_thermal_int); 7643 break; 7644 default: 7645 break; 7646 } 7647 break; 7648 7649 case AMDGPU_THERMAL_IRQ_HIGH_TO_LOW: 7650 switch (state) { 7651 case AMDGPU_IRQ_STATE_DISABLE: 7652 cg_thermal_int = RREG32_SMC(mmCG_THERMAL_INT); 7653 cg_thermal_int |= CG_THERMAL_INT__THERM_INT_MASK_LOW_MASK; 7654 WREG32(mmCG_THERMAL_INT, cg_thermal_int); 7655 break; 7656 case AMDGPU_IRQ_STATE_ENABLE: 7657 cg_thermal_int = RREG32_SMC(mmCG_THERMAL_INT); 7658 cg_thermal_int &= ~CG_THERMAL_INT__THERM_INT_MASK_LOW_MASK; 7659 WREG32(mmCG_THERMAL_INT, cg_thermal_int); 7660 break; 7661 default: 7662 break; 7663 } 7664 break; 7665 7666 default: 7667 break; 7668 } 7669 return 0; 7670 } 7671 7672 static int si_dpm_process_interrupt(struct amdgpu_device *adev, 7673 struct amdgpu_irq_src *source, 7674 struct amdgpu_iv_entry *entry) 7675 { 7676 bool queue_thermal = false; 7677 7678 if (entry == NULL) 7679 return -EINVAL; 7680 7681 switch (entry->src_id) { 7682 case 230: /* thermal low to high */ 7683 DRM_DEBUG("IH: thermal low to high\n"); 7684 adev->pm.dpm.thermal.high_to_low = false; 7685 queue_thermal = true; 7686 break; 7687 case 231: /* thermal high to low */ 7688 DRM_DEBUG("IH: thermal high to low\n"); 7689 adev->pm.dpm.thermal.high_to_low = true; 7690 queue_thermal = true; 7691 break; 7692 default: 7693 break; 7694 } 7695 7696 if (queue_thermal && amdgpu_dpm) 7697 schedule_work(&adev->pm.dpm.thermal.work); 7698 7699 return 0; 7700 } 7701 7702 static int si_dpm_late_init(struct amdgpu_ip_block *ip_block) 7703 { 7704 int ret; 7705 struct amdgpu_device *adev = ip_block->adev; 7706 7707 if (!adev->pm.dpm_enabled) 7708 return 0; 7709 7710 ret = si_set_temperature_range(adev); 7711 if (ret) 7712 return ret; 7713 #if 0 //TODO ? 7714 si_dpm_powergate_uvd(adev, true); 7715 #endif 7716 return 0; 7717 } 7718 7719 /** 7720 * si_dpm_init_microcode - load ucode images from disk 7721 * 7722 * @adev: amdgpu_device pointer 7723 * 7724 * Use the firmware interface to load the ucode images into 7725 * the driver (not loaded into hw). 7726 * Returns 0 on success, error on failure. 7727 */ 7728 static int si_dpm_init_microcode(struct amdgpu_device *adev) 7729 { 7730 const char *chip_name; 7731 int err; 7732 7733 DRM_DEBUG("\n"); 7734 switch (adev->asic_type) { 7735 case CHIP_TAHITI: 7736 chip_name = "tahiti"; 7737 break; 7738 case CHIP_PITCAIRN: 7739 if ((adev->pdev->revision == 0x81) && 7740 ((adev->pdev->device == 0x6810) || 7741 (adev->pdev->device == 0x6811))) 7742 chip_name = "pitcairn_k"; 7743 else 7744 chip_name = "pitcairn"; 7745 break; 7746 case CHIP_VERDE: 7747 if (((adev->pdev->device == 0x6820) && 7748 ((adev->pdev->revision == 0x81) || 7749 (adev->pdev->revision == 0x83))) || 7750 ((adev->pdev->device == 0x6821) && 7751 ((adev->pdev->revision == 0x83) || 7752 (adev->pdev->revision == 0x87))) || 7753 ((adev->pdev->revision == 0x87) && 7754 ((adev->pdev->device == 0x6823) || 7755 (adev->pdev->device == 0x682b)))) 7756 chip_name = "verde_k"; 7757 else 7758 chip_name = "verde"; 7759 break; 7760 case CHIP_OLAND: 7761 if (((adev->pdev->revision == 0x81) && 7762 ((adev->pdev->device == 0x6600) || 7763 (adev->pdev->device == 0x6604) || 7764 (adev->pdev->device == 0x6605) || 7765 (adev->pdev->device == 0x6610))) || 7766 ((adev->pdev->revision == 0x83) && 7767 (adev->pdev->device == 0x6610))) 7768 chip_name = "oland_k"; 7769 else 7770 chip_name = "oland"; 7771 break; 7772 case CHIP_HAINAN: 7773 if (((adev->pdev->revision == 0x81) && 7774 (adev->pdev->device == 0x6660)) || 7775 ((adev->pdev->revision == 0x83) && 7776 ((adev->pdev->device == 0x6660) || 7777 (adev->pdev->device == 0x6663) || 7778 (adev->pdev->device == 0x6665) || 7779 (adev->pdev->device == 0x6667)))) 7780 chip_name = "hainan_k"; 7781 else if ((adev->pdev->revision == 0xc3) && 7782 (adev->pdev->device == 0x6665)) 7783 chip_name = "banks_k_2"; 7784 else 7785 chip_name = "hainan"; 7786 break; 7787 default: BUG(); 7788 } 7789 7790 err = amdgpu_ucode_request(adev, &adev->pm.fw, AMDGPU_UCODE_REQUIRED, 7791 "amdgpu/%s_smc.bin", chip_name); 7792 if (err) { 7793 DRM_ERROR("si_smc: Failed to load firmware. err = %d\"%s_smc.bin\"\n", 7794 err, chip_name); 7795 amdgpu_ucode_release(&adev->pm.fw); 7796 } 7797 return err; 7798 } 7799 7800 static int si_dpm_sw_init(struct amdgpu_ip_block *ip_block) 7801 { 7802 int ret; 7803 struct amdgpu_device *adev = ip_block->adev; 7804 7805 ret = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 230, &adev->pm.dpm.thermal.irq); 7806 if (ret) 7807 return ret; 7808 7809 ret = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 231, &adev->pm.dpm.thermal.irq); 7810 if (ret) 7811 return ret; 7812 7813 /* default to balanced state */ 7814 adev->pm.dpm.state = POWER_STATE_TYPE_BALANCED; 7815 adev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED; 7816 adev->pm.dpm.forced_level = AMD_DPM_FORCED_LEVEL_AUTO; 7817 adev->pm.default_sclk = adev->clock.default_sclk; 7818 adev->pm.default_mclk = adev->clock.default_mclk; 7819 adev->pm.current_sclk = adev->clock.default_sclk; 7820 adev->pm.current_mclk = adev->clock.default_mclk; 7821 adev->pm.int_thermal_type = THERMAL_TYPE_NONE; 7822 7823 if (amdgpu_dpm == 0) 7824 return 0; 7825 7826 ret = si_dpm_init_microcode(adev); 7827 if (ret) 7828 return ret; 7829 7830 INIT_WORK(&adev->pm.dpm.thermal.work, amdgpu_dpm_thermal_work_handler); 7831 ret = si_dpm_init(adev); 7832 if (ret) 7833 goto dpm_failed; 7834 adev->pm.dpm.current_ps = adev->pm.dpm.requested_ps = adev->pm.dpm.boot_ps; 7835 if (amdgpu_dpm == 1) 7836 amdgpu_pm_print_power_states(adev); 7837 drm_info(adev_to_drm(adev), "si dpm initialized\n"); 7838 return 0; 7839 7840 dpm_failed: 7841 si_dpm_fini(adev); 7842 drm_err(adev_to_drm(adev), "dpm initialization failed\n"); 7843 return ret; 7844 } 7845 7846 static int si_dpm_sw_fini(struct amdgpu_ip_block *ip_block) 7847 { 7848 struct amdgpu_device *adev = ip_block->adev; 7849 7850 flush_work(&adev->pm.dpm.thermal.work); 7851 7852 si_dpm_fini(adev); 7853 7854 return 0; 7855 } 7856 7857 static int si_dpm_hw_init(struct amdgpu_ip_block *ip_block) 7858 { 7859 int ret; 7860 7861 struct amdgpu_device *adev = ip_block->adev; 7862 7863 if (!amdgpu_dpm) 7864 return 0; 7865 7866 mutex_lock(&adev->pm.mutex); 7867 si_dpm_setup_asic(adev); 7868 ret = si_dpm_enable(adev); 7869 if (ret) 7870 adev->pm.dpm_enabled = false; 7871 else 7872 adev->pm.dpm_enabled = true; 7873 amdgpu_legacy_dpm_compute_clocks(adev); 7874 mutex_unlock(&adev->pm.mutex); 7875 return ret; 7876 } 7877 7878 static int si_dpm_hw_fini(struct amdgpu_ip_block *ip_block) 7879 { 7880 struct amdgpu_device *adev = ip_block->adev; 7881 7882 if (adev->pm.dpm_enabled) 7883 si_dpm_disable(adev); 7884 7885 return 0; 7886 } 7887 7888 static int si_dpm_suspend(struct amdgpu_ip_block *ip_block) 7889 { 7890 struct amdgpu_device *adev = ip_block->adev; 7891 7892 cancel_work_sync(&adev->pm.dpm.thermal.work); 7893 7894 if (adev->pm.dpm_enabled) { 7895 mutex_lock(&adev->pm.mutex); 7896 adev->pm.dpm_enabled = false; 7897 /* disable dpm */ 7898 si_dpm_disable(adev); 7899 /* reset the power state */ 7900 adev->pm.dpm.current_ps = adev->pm.dpm.requested_ps = adev->pm.dpm.boot_ps; 7901 mutex_unlock(&adev->pm.mutex); 7902 } 7903 7904 return 0; 7905 } 7906 7907 static int si_dpm_resume(struct amdgpu_ip_block *ip_block) 7908 { 7909 int ret = 0; 7910 struct amdgpu_device *adev = ip_block->adev; 7911 7912 if (!amdgpu_dpm) 7913 return 0; 7914 7915 if (!adev->pm.dpm_enabled) { 7916 /* asic init will reset to the boot state */ 7917 mutex_lock(&adev->pm.mutex); 7918 si_dpm_setup_asic(adev); 7919 ret = si_dpm_enable(adev); 7920 if (ret) { 7921 adev->pm.dpm_enabled = false; 7922 } else { 7923 adev->pm.dpm_enabled = true; 7924 amdgpu_legacy_dpm_compute_clocks(adev); 7925 } 7926 mutex_unlock(&adev->pm.mutex); 7927 } 7928 7929 return ret; 7930 } 7931 7932 static bool si_dpm_is_idle(struct amdgpu_ip_block *ip_block) 7933 { 7934 /* XXX */ 7935 return true; 7936 } 7937 7938 static int si_dpm_wait_for_idle(struct amdgpu_ip_block *ip_block) 7939 { 7940 /* XXX */ 7941 return 0; 7942 } 7943 7944 static int si_dpm_set_clockgating_state(struct amdgpu_ip_block *ip_block, 7945 enum amd_clockgating_state state) 7946 { 7947 return 0; 7948 } 7949 7950 static int si_dpm_set_powergating_state(struct amdgpu_ip_block *ip_block, 7951 enum amd_powergating_state state) 7952 { 7953 return 0; 7954 } 7955 7956 /* get temperature in millidegrees */ 7957 static int si_dpm_get_temp(void *handle) 7958 { 7959 u32 temp; 7960 int actual_temp = 0; 7961 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7962 7963 temp = (RREG32(mmCG_MULT_THERMAL_STATUS) & CG_MULT_THERMAL_STATUS__CTF_TEMP_MASK) >> 7964 CG_MULT_THERMAL_STATUS__CTF_TEMP__SHIFT; 7965 7966 if (temp & 0x200) 7967 actual_temp = 255; 7968 else 7969 actual_temp = temp & 0x1ff; 7970 7971 actual_temp = (actual_temp * 1000); 7972 7973 return actual_temp; 7974 } 7975 7976 static u32 si_dpm_get_sclk(void *handle, bool low) 7977 { 7978 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7979 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); 7980 struct si_ps *requested_state = si_get_ps(&eg_pi->requested_rps); 7981 7982 if (low) 7983 return requested_state->performance_levels[0].sclk; 7984 else 7985 return requested_state->performance_levels[requested_state->performance_level_count - 1].sclk; 7986 } 7987 7988 static u32 si_dpm_get_mclk(void *handle, bool low) 7989 { 7990 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7991 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); 7992 struct si_ps *requested_state = si_get_ps(&eg_pi->requested_rps); 7993 7994 if (low) 7995 return requested_state->performance_levels[0].mclk; 7996 else 7997 return requested_state->performance_levels[requested_state->performance_level_count - 1].mclk; 7998 } 7999 8000 static void si_dpm_print_power_state(void *handle, 8001 void *current_ps) 8002 { 8003 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 8004 struct amdgpu_ps *rps = (struct amdgpu_ps *)current_ps; 8005 struct si_ps *ps = si_get_ps(rps); 8006 struct rv7xx_pl *pl; 8007 int i; 8008 8009 amdgpu_dpm_dbg_print_class_info(adev, rps->class, rps->class2); 8010 amdgpu_dpm_dbg_print_cap_info(adev, rps->caps); 8011 drm_dbg(adev_to_drm(adev), "\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); 8012 drm_dbg(adev_to_drm(adev), "\tvce evclk: %d ecclk: %d\n", rps->evclk, rps->ecclk); 8013 for (i = 0; i < ps->performance_level_count; i++) { 8014 pl = &ps->performance_levels[i]; 8015 drm_dbg(adev_to_drm(adev), "\t\tpower level %d sclk: %u mclk: %u vddc: %u vddci: %u pcie gen: %u\n", 8016 i, pl->sclk, pl->mclk, pl->vddc, pl->vddci, pl->pcie_gen + 1); 8017 } 8018 amdgpu_dpm_dbg_print_ps_status(adev, rps); 8019 } 8020 8021 static int si_dpm_early_init(struct amdgpu_ip_block *ip_block) 8022 { 8023 8024 struct amdgpu_device *adev = ip_block->adev; 8025 8026 adev->powerplay.pp_funcs = &si_dpm_funcs; 8027 adev->powerplay.pp_handle = adev; 8028 si_dpm_set_irq_funcs(adev); 8029 return 0; 8030 } 8031 8032 static inline bool si_are_power_levels_equal(const struct rv7xx_pl *si_cpl1, 8033 const struct rv7xx_pl *si_cpl2) 8034 { 8035 return ((si_cpl1->mclk == si_cpl2->mclk) && 8036 (si_cpl1->sclk == si_cpl2->sclk) && 8037 (si_cpl1->pcie_gen == si_cpl2->pcie_gen) && 8038 (si_cpl1->vddc == si_cpl2->vddc) && 8039 (si_cpl1->vddci == si_cpl2->vddci)); 8040 } 8041 8042 static int si_check_state_equal(void *handle, 8043 void *current_ps, 8044 void *request_ps, 8045 bool *equal) 8046 { 8047 struct si_ps *si_cps; 8048 struct si_ps *si_rps; 8049 int i; 8050 struct amdgpu_ps *cps = (struct amdgpu_ps *)current_ps; 8051 struct amdgpu_ps *rps = (struct amdgpu_ps *)request_ps; 8052 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 8053 8054 if (adev == NULL || cps == NULL || rps == NULL || equal == NULL) 8055 return -EINVAL; 8056 8057 si_cps = si_get_ps((struct amdgpu_ps *)cps); 8058 si_rps = si_get_ps((struct amdgpu_ps *)rps); 8059 8060 if (si_cps == NULL) { 8061 printk("si_cps is NULL\n"); 8062 *equal = false; 8063 return 0; 8064 } 8065 8066 if (si_cps->performance_level_count != si_rps->performance_level_count) { 8067 *equal = false; 8068 return 0; 8069 } 8070 8071 for (i = 0; i < si_cps->performance_level_count; i++) { 8072 if (!si_are_power_levels_equal(&(si_cps->performance_levels[i]), 8073 &(si_rps->performance_levels[i]))) { 8074 *equal = false; 8075 return 0; 8076 } 8077 } 8078 8079 /* If all performance levels are the same try to use the UVD clocks to break the tie.*/ 8080 *equal = ((cps->vclk == rps->vclk) && (cps->dclk == rps->dclk)); 8081 *equal &= ((cps->evclk == rps->evclk) && (cps->ecclk == rps->ecclk)); 8082 8083 return 0; 8084 } 8085 8086 static int si_dpm_read_sensor(void *handle, int idx, 8087 void *value, int *size) 8088 { 8089 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 8090 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev); 8091 struct amdgpu_ps *rps = &eg_pi->current_rps; 8092 struct si_ps *ps = si_get_ps(rps); 8093 uint32_t sclk, mclk; 8094 u32 pl_index = 8095 (RREG32(mmTARGET_AND_CURRENT_PROFILE_INDEX) & TARGET_AND_CURRENT_PROFILE_INDEX__CURRENT_STATE_INDEX_MASK) >> 8096 TARGET_AND_CURRENT_PROFILE_INDEX__CURRENT_STATE_INDEX__SHIFT; 8097 8098 /* size must be at least 4 bytes for all sensors */ 8099 if (*size < 4) 8100 return -EINVAL; 8101 8102 switch (idx) { 8103 case AMDGPU_PP_SENSOR_GFX_SCLK: 8104 if (pl_index < ps->performance_level_count) { 8105 sclk = ps->performance_levels[pl_index].sclk; 8106 *((uint32_t *)value) = sclk; 8107 *size = 4; 8108 return 0; 8109 } 8110 return -EINVAL; 8111 case AMDGPU_PP_SENSOR_GFX_MCLK: 8112 if (pl_index < ps->performance_level_count) { 8113 mclk = ps->performance_levels[pl_index].mclk; 8114 *((uint32_t *)value) = mclk; 8115 *size = 4; 8116 return 0; 8117 } 8118 return -EINVAL; 8119 case AMDGPU_PP_SENSOR_GPU_TEMP: 8120 *((uint32_t *)value) = si_dpm_get_temp(adev); 8121 *size = 4; 8122 return 0; 8123 default: 8124 return -EOPNOTSUPP; 8125 } 8126 } 8127 8128 static const struct amd_ip_funcs si_dpm_ip_funcs = { 8129 .name = "si_dpm", 8130 .early_init = si_dpm_early_init, 8131 .late_init = si_dpm_late_init, 8132 .sw_init = si_dpm_sw_init, 8133 .sw_fini = si_dpm_sw_fini, 8134 .hw_init = si_dpm_hw_init, 8135 .hw_fini = si_dpm_hw_fini, 8136 .suspend = si_dpm_suspend, 8137 .resume = si_dpm_resume, 8138 .is_idle = si_dpm_is_idle, 8139 .wait_for_idle = si_dpm_wait_for_idle, 8140 .set_clockgating_state = si_dpm_set_clockgating_state, 8141 .set_powergating_state = si_dpm_set_powergating_state, 8142 }; 8143 8144 const struct amdgpu_ip_block_version si_smu_ip_block = 8145 { 8146 .type = AMD_IP_BLOCK_TYPE_SMC, 8147 .major = 6, 8148 .minor = 0, 8149 .rev = 0, 8150 .funcs = &si_dpm_ip_funcs, 8151 }; 8152 8153 static const struct amd_pm_funcs si_dpm_funcs = { 8154 .pre_set_power_state = &si_dpm_pre_set_power_state, 8155 .set_power_state = &si_dpm_set_power_state, 8156 .post_set_power_state = &si_dpm_post_set_power_state, 8157 .display_configuration_changed = &si_dpm_display_configuration_changed, 8158 .get_sclk = &si_dpm_get_sclk, 8159 .get_mclk = &si_dpm_get_mclk, 8160 .print_power_state = &si_dpm_print_power_state, 8161 .debugfs_print_current_performance_level = &si_dpm_debugfs_print_current_performance_level, 8162 .force_performance_level = &si_dpm_force_performance_level, 8163 .vblank_too_short = &si_dpm_vblank_too_short, 8164 .set_fan_control_mode = &si_dpm_set_fan_control_mode, 8165 .get_fan_control_mode = &si_dpm_get_fan_control_mode, 8166 .set_fan_speed_pwm = &si_dpm_set_fan_speed_pwm, 8167 .get_fan_speed_pwm = &si_dpm_get_fan_speed_pwm, 8168 .check_state_equal = &si_check_state_equal, 8169 .get_vce_clock_state = amdgpu_get_vce_clock_state, 8170 .read_sensor = &si_dpm_read_sensor, 8171 .pm_compute_clocks = amdgpu_legacy_dpm_compute_clocks, 8172 .notify_ac_dc = si_notify_hw_of_powersource, 8173 }; 8174 8175 static const struct amdgpu_irq_src_funcs si_dpm_irq_funcs = { 8176 .set = si_dpm_set_interrupt_state, 8177 .process = si_dpm_process_interrupt, 8178 }; 8179 8180 static void si_dpm_set_irq_funcs(struct amdgpu_device *adev) 8181 { 8182 adev->pm.dpm.thermal.irq.num_types = AMDGPU_THERMAL_IRQ_LAST; 8183 adev->pm.dpm.thermal.irq.funcs = &si_dpm_irq_funcs; 8184 } 8185 8186