xref: /freebsd/sys/contrib/device-tree/src/arm64/freescale/fsl-lx2162a-clearfog.dts (revision 69ed3df4f588860308677cda76cbcce1f19a54c9) 
1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2//
3// Device Tree file for LX2162A Clearfog
4//
5// Copyright 2023 Josua Mayer <josua@solid-run.com>
6
7/dts-v1/;
8
9#include "fsl-lx2160a.dtsi"
10#include "fsl-lx2162a-sr-som.dtsi"
11
12/ {
13	model = "SolidRun LX2162A Clearfog";
14	compatible = "solidrun,lx2162a-clearfog", "solidrun,lx2162a-som", "fsl,lx2160a";
15
16	aliases {
17		crypto = &crypto;
18		i2c0 = &i2c0;
19		i2c1 = &i2c2;
20		i2c2 = &i2c4;
21		i2c3 = &sfp_i2c0;
22		i2c4 = &sfp_i2c1;
23		i2c5 = &sfp_i2c2;
24		i2c6 = &sfp_i2c3;
25		i2c7 = &mpcie1_i2c;
26		i2c8 = &mpcie0_i2c;
27		i2c9 = &pcieclk_i2c;
28		i2c10 = &i2c5;
29		mmc0 = &esdhc0;
30		mmc1 = &esdhc1;
31		serial0 = &uart0;
32	};
33
34	chosen {
35		stdout-path = "serial0:115200n8";
36	};
37
38	leds {
39		compatible = "gpio-leds";
40
41		led_sfp_at: led-sfp-at {
42			gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>; /* PROC_IRQ5 */
43			default-state = "off";
44			linux,default-trigger = "netdev";
45			trigger-sources = <&dpmac3>;
46		};
47
48		led_sfp_ab: led-sfp-ab {
49			gpios = <&gpio2 11 GPIO_ACTIVE_HIGH>; /* PROC_IRQ11 */
50			default-state = "off";
51			linux,default-trigger = "netdev";
52			trigger-sources = <&dpmac4>;
53		};
54
55		led_sfp_bt: led-sfp-bt {
56			gpios = <&gpio2 13 GPIO_ACTIVE_HIGH>; /* EVT1_B */
57			default-state = "off";
58			linux,default-trigger = "netdev";
59			trigger-sources = <&dpmac5>;
60		};
61
62		led_sfp_bb: led-sfp-bb {
63			gpios = <&gpio2 14 GPIO_ACTIVE_HIGH>; /* EVT2_B */
64			default-state = "off";
65			linux,default-trigger = "netdev";
66			trigger-sources = <&dpmac6>;
67		};
68	};
69
70	sfp_at: sfp-at {
71		compatible = "sff,sfp";
72		i2c-bus = <&sfp_i2c0>;
73		mod-def0-gpios = <&gpio2 16 GPIO_ACTIVE_LOW>; /* EVT4_B */
74		maximum-power-milliwatt = <2000>;
75	};
76
77	sfp_ab: sfp-ab {
78		compatible = "sff,sfp";
79		i2c-bus = <&sfp_i2c1>;
80		mod-def0-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; /* PROC_IRQ1 */
81		maximum-power-milliwatt = <2000>;
82	};
83
84	sfp_bt: sfp-bt {
85		compatible = "sff,sfp";
86		i2c-bus = <&sfp_i2c2>;
87		mod-def0-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>; /* PROC_IRQ10 */
88		maximum-power-milliwatt = <2000>;
89	};
90
91	sfp_bb: sfp-bb {
92		compatible = "sff,sfp";
93		i2c-bus = <&sfp_i2c3>;
94		mod-def0-gpios = <&gpio2 15 GPIO_ACTIVE_LOW>; /* EVT3_B */
95		maximum-power-milliwatt = <2000>;
96	};
97};
98
99&dpmac3 {
100	sfp = <&sfp_at>;
101	managed = "in-band-status";
102	phys = <&serdes_1 7>;
103};
104
105&dpmac4 {
106	sfp = <&sfp_ab>;
107	managed = "in-band-status";
108	phys = <&serdes_1 6>;
109};
110
111&dpmac5 {
112	sfp = <&sfp_bt>;
113	managed = "in-band-status";
114	phys = <&serdes_1 5>;
115};
116
117&dpmac6 {
118	sfp = <&sfp_bb>;
119	managed = "in-band-status";
120	phys = <&serdes_1 4>;
121};
122
123&dpmac11 {
124	phys = <&serdes_2 0>;
125	phy-handle = <&ethernet_phy3>;
126	phy-connection-type = "sgmii";
127	status = "okay";
128};
129
130&dpmac12 {
131	phys = <&serdes_2 1>;
132	phy-handle = <&ethernet_phy1>;
133	phy-connection-type = "sgmii";
134	status = "okay";
135};
136
137&dpmac13 {
138	phys = <&serdes_2 6>;
139	phy-handle = <&ethernet_phy6>;
140	phy-connection-type = "sgmii";
141	status = "okay";
142};
143
144&dpmac14 {
145	phys = <&serdes_2 7>;
146	phy-handle = <&ethernet_phy8>;
147	phy-connection-type = "sgmii";
148	status = "okay";
149};
150
151&dpmac15 {
152	phys = <&serdes_2 4>;
153	phy-handle = <&ethernet_phy4>;
154	phy-connection-type = "sgmii";
155	status = "okay";
156};
157
158&dpmac16 {
159	phys = <&serdes_2 5>;
160	phy-handle = <&ethernet_phy2>;
161	phy-connection-type = "sgmii";
162	status = "okay";
163};
164
165&dpmac17 {
166	/* override connection to on-SoM phy */
167	/delete-property/ phy-handle;
168	/delete-property/ phy-connection-type;
169
170	phys = <&serdes_2 2>;
171	phy-handle = <&ethernet_phy5>;
172	phy-connection-type = "sgmii";
173	status = "okay";
174};
175
176&dpmac18 {
177	phys = <&serdes_2 3>;
178	phy-handle = <&ethernet_phy7>;
179	phy-connection-type = "sgmii";
180	status = "okay";
181};
182
183&emdio1 {
184	ethernet_phy1: ethernet-phy@8 {
185		compatible = "ethernet-phy-ieee802.3-c45";
186		reg = <8>;
187		max-speed = <1000>;
188	};
189
190	ethernet_phy2: ethernet-phy@9 {
191		compatible = "ethernet-phy-ieee802.3-c45";
192		reg = <9>;
193		max-speed = <1000>;
194	};
195
196	ethernet_phy3: ethernet-phy@10 {
197		compatible = "ethernet-phy-ieee802.3-c45";
198		reg = <10>;
199		max-speed = <1000>;
200	};
201
202	ethernet_phy4: ethernet-phy@11 {
203		compatible = "ethernet-phy-ieee802.3-c45";
204		reg = <11>;
205		max-speed = <1000>;
206	};
207
208	ethernet_phy5: ethernet-phy@12 {
209		compatible = "ethernet-phy-ieee802.3-c45";
210		reg = <12>;
211		max-speed = <1000>;
212	};
213
214	ethernet_phy6: ethernet-phy@13 {
215		compatible = "ethernet-phy-ieee802.3-c45";
216		reg = <13>;
217		max-speed = <1000>;
218	};
219
220	ethernet_phy7: ethernet-phy@14 {
221		compatible = "ethernet-phy-ieee802.3-c45";
222		reg = <14>;
223		max-speed = <1000>;
224	};
225
226	ethernet_phy8: ethernet-phy@15 {
227		compatible = "ethernet-phy-ieee802.3-c45";
228		reg = <15>;
229		max-speed = <1000>;
230	};
231};
232
233&esdhc0 {
234	pinctrl-names = "default";
235	pinctrl-0 = <&esdhc0_cd_wp_pins>, <&esdhc0_cmd_data30_clk_vsel_pins>;
236	sd-uhs-sdr104;
237	sd-uhs-sdr50;
238	sd-uhs-sdr25;
239	sd-uhs-sdr12;
240	status = "okay";
241};
242
243&ethernet_phy0 {
244	/*
245	 * SoM has a phy at address 1 connected to SoC Ethernet Controller 1.
246	 * It competes for WRIOP MAC17, and no connector has been wired.
247	 */
248	status = "disabled";
249};
250
251&i2c2 {
252	status = "okay";
253
254	/* retimer@18 */
255
256	i2c-mux@70 {
257		compatible = "nxp,pca9546";
258		reg = <0x70>;
259		#address-cells = <1>;
260		#size-cells = <0>;
261		i2c-mux-idle-disconnect;
262
263		sfp_i2c0: i2c@0 {
264			#address-cells = <1>;
265			#size-cells = <0>;
266			reg = <0>;
267		};
268
269		sfp_i2c1: i2c@1 {
270			#address-cells = <1>;
271			#size-cells = <0>;
272			reg = <1>;
273		};
274
275		sfp_i2c2: i2c@2 {
276			#address-cells = <1>;
277			#size-cells = <0>;
278			reg = <2>;
279		};
280
281		sfp_i2c3: i2c@3 {
282			#address-cells = <1>;
283			#size-cells = <0>;
284			reg = <3>;
285		};
286	};
287
288	i2c-mux@71 {
289		compatible = "nxp,pca9546";
290		reg = <0x71>;
291		#address-cells = <1>;
292		#size-cells = <0>;
293		i2c-mux-idle-disconnect;
294
295		mpcie1_i2c: i2c@0 {
296			#address-cells = <1>;
297			#size-cells = <0>;
298			reg = <0>;
299		};
300
301		mpcie0_i2c: i2c@1 {
302			#address-cells = <1>;
303			#size-cells = <0>;
304			reg = <1>;
305		};
306
307		pcieclk_i2c: i2c@2 {
308			#address-cells = <1>;
309			#size-cells = <0>;
310			reg = <2>;
311
312			/* clock-controller@6b */
313		};
314	};
315};
316
317&pcie3 {
318	status = "disabled";
319};
320
321&pcie4 {
322	status = "disabled";
323};
324
325&pcs_mdio3 {
326	status = "okay";
327};
328
329&pcs_mdio4 {
330	status = "okay";
331};
332
333&pcs_mdio5 {
334	status = "okay";
335};
336
337&pcs_mdio6 {
338	status = "okay";
339};
340
341&pcs_mdio11 {
342	status = "okay";
343};
344
345&pcs_mdio12 {
346	status = "okay";
347};
348
349&pcs_mdio13 {
350	status = "okay";
351};
352
353&pcs_mdio14 {
354	status = "okay";
355};
356
357&pcs_mdio15 {
358	status = "okay";
359};
360
361&pcs_mdio16 {
362	status = "okay";
363};
364
365&pcs_mdio17 {
366	status = "okay";
367};
368
369&pcs_mdio18 {
370	status = "okay";
371};
372
373&serdes_1 {
374	status = "okay";
375};
376
377&serdes_2 {
378	status = "okay";
379};
380
381&uart0 {
382	status = "okay";
383};
384
385&usb0 {
386	status = "okay";
387};
388