1 /*- 2 * Copyright (c) 2015 Ruslan Bukin <br@bsdpad.com> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 /* 28 * i.MX6 Synchronous Serial Interface (SSI) 29 * 30 * Chapter 61, i.MX 6Dual/6Quad Applications Processor Reference Manual, 31 * Rev. 1, 04/2013 32 */ 33 34 #include <sys/param.h> 35 #include <sys/systm.h> 36 #include <sys/bus.h> 37 #include <sys/kernel.h> 38 #include <sys/module.h> 39 #include <sys/malloc.h> 40 #include <sys/rman.h> 41 #include <sys/timeet.h> 42 #include <sys/timetc.h> 43 44 #include <dev/sound/pcm/sound.h> 45 #include <mixer_if.h> 46 47 #include <dev/ofw/openfirm.h> 48 #include <dev/ofw/ofw_bus.h> 49 #include <dev/ofw/ofw_bus_subr.h> 50 51 #include <machine/bus.h> 52 #include <machine/cpu.h> 53 #include <machine/intr.h> 54 55 #include <arm/freescale/imx/imx6_sdma.h> 56 #include <arm/freescale/imx/imx6_anatopvar.h> 57 #include <arm/freescale/imx/imx_ccmvar.h> 58 59 #define READ4(_sc, _reg) \ 60 bus_space_read_4(_sc->bst, _sc->bsh, _reg) 61 #define WRITE4(_sc, _reg, _val) \ 62 bus_space_write_4(_sc->bst, _sc->bsh, _reg, _val) 63 64 #define SSI_NCHANNELS 1 65 #define DMAS_TOTAL 8 66 67 /* i.MX6 SSI registers */ 68 69 #define SSI_STX0 0x00 /* Transmit Data Register n */ 70 #define SSI_STX1 0x04 /* Transmit Data Register n */ 71 #define SSI_SRX0 0x08 /* Receive Data Register n */ 72 #define SSI_SRX1 0x0C /* Receive Data Register n */ 73 #define SSI_SCR 0x10 /* Control Register */ 74 #define SCR_I2S_MODE_S 5 /* I2S Mode Select. */ 75 #define SCR_I2S_MODE_M 0x3 76 #define SCR_SYN (1 << 4) 77 #define SCR_NET (1 << 3) /* Network mode */ 78 #define SCR_RE (1 << 2) /* Receive Enable. */ 79 #define SCR_TE (1 << 1) /* Transmit Enable. */ 80 #define SCR_SSIEN (1 << 0) /* SSI Enable */ 81 #define SSI_SISR 0x14 /* Interrupt Status Register */ 82 #define SSI_SIER 0x18 /* Interrupt Enable Register */ 83 #define SIER_RDMAE (1 << 22) /* Receive DMA Enable. */ 84 #define SIER_RIE (1 << 21) /* Receive Interrupt Enable. */ 85 #define SIER_TDMAE (1 << 20) /* Transmit DMA Enable. */ 86 #define SIER_TIE (1 << 19) /* Transmit Interrupt Enable. */ 87 #define SIER_TDE0IE (1 << 12) /* Transmit Data Register Empty 0. */ 88 #define SIER_TUE0IE (1 << 8) /* Transmitter Underrun Error 0. */ 89 #define SIER_TFE0IE (1 << 0) /* Transmit FIFO Empty 0 IE. */ 90 #define SSI_STCR 0x1C /* Transmit Configuration Register */ 91 #define STCR_TXBIT0 (1 << 9) /* Transmit Bit 0 shift MSB/LSB */ 92 #define STCR_TFEN1 (1 << 8) /* Transmit FIFO Enable 1. */ 93 #define STCR_TFEN0 (1 << 7) /* Transmit FIFO Enable 0. */ 94 #define STCR_TFDIR (1 << 6) /* Transmit Frame Direction. */ 95 #define STCR_TXDIR (1 << 5) /* Transmit Clock Direction. */ 96 #define STCR_TSHFD (1 << 4) /* Transmit Shift Direction. */ 97 #define STCR_TSCKP (1 << 3) /* Transmit Clock Polarity. */ 98 #define STCR_TFSI (1 << 2) /* Transmit Frame Sync Invert. */ 99 #define STCR_TFSL (1 << 1) /* Transmit Frame Sync Length. */ 100 #define STCR_TEFS (1 << 0) /* Transmit Early Frame Sync. */ 101 #define SSI_SRCR 0x20 /* Receive Configuration Register */ 102 #define SSI_STCCR 0x24 /* Transmit Clock Control Register */ 103 #define STCCR_DIV2 (1 << 18) /* Divide By 2. */ 104 #define STCCR_PSR (1 << 17) /* Divide clock by 8. */ 105 #define WL3_WL0_S 13 106 #define WL3_WL0_M 0xf 107 #define DC4_DC0_S 8 108 #define DC4_DC0_M 0x1f 109 #define PM7_PM0_S 0 110 #define PM7_PM0_M 0xff 111 #define SSI_SRCCR 0x28 /* Receive Clock Control Register */ 112 #define SSI_SFCSR 0x2C /* FIFO Control/Status Register */ 113 #define SFCSR_RFWM1_S 20 /* Receive FIFO Empty WaterMark 1 */ 114 #define SFCSR_RFWM1_M 0xf 115 #define SFCSR_TFWM1_S 16 /* Transmit FIFO Empty WaterMark 1 */ 116 #define SFCSR_TFWM1_M 0xf 117 #define SFCSR_RFWM0_S 4 /* Receive FIFO Empty WaterMark 0 */ 118 #define SFCSR_RFWM0_M 0xf 119 #define SFCSR_TFWM0_S 0 /* Transmit FIFO Empty WaterMark 0 */ 120 #define SFCSR_TFWM0_M 0xf 121 #define SSI_SACNT 0x38 /* AC97 Control Register */ 122 #define SSI_SACADD 0x3C /* AC97 Command Address Register */ 123 #define SSI_SACDAT 0x40 /* AC97 Command Data Register */ 124 #define SSI_SATAG 0x44 /* AC97 Tag Register */ 125 #define SSI_STMSK 0x48 /* Transmit Time Slot Mask Register */ 126 #define SSI_SRMSK 0x4C /* Receive Time Slot Mask Register */ 127 #define SSI_SACCST 0x50 /* AC97 Channel Status Register */ 128 #define SSI_SACCEN 0x54 /* AC97 Channel Enable Register */ 129 #define SSI_SACCDIS 0x58 /* AC97 Channel Disable Register */ 130 131 static MALLOC_DEFINE(M_SSI, "ssi", "ssi audio"); 132 133 uint32_t ssi_dma_intr(void *arg, int chn); 134 135 struct ssi_rate { 136 uint32_t speed; 137 uint32_t mfi; /* PLL4 Multiplication Factor Integer */ 138 uint32_t mfn; /* PLL4 Multiplication Factor Numerator */ 139 uint32_t mfd; /* PLL4 Multiplication Factor Denominator */ 140 /* More dividers to configure can be added here */ 141 }; 142 143 static struct ssi_rate rate_map[] = { 144 { 192000, 49, 152, 1000 }, /* PLL4 49.152 Mhz */ 145 /* TODO: add more frequences */ 146 { 0, 0 }, 147 }; 148 149 /* 150 * i.MX6 example bit clock formula 151 * 152 * BCLK = 2 channels * 192000 hz * 24 bit = 9216000 hz = 153 * (24000000 * (49 + 152/1000.0) / 4 / 4 / 2 / 2 / 2 / 1 / 1) 154 * ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ 155 * | | | | | | | | | | | 156 * Fref ------/ | | | | | | | | | | 157 * PLL4 div select -/ | | | | | | | | | 158 * PLL4 num --------------/ | | | | | | | | 159 * PLL4 denom -------------------/ | | | | | | | 160 * PLL4 post div ---------------------/ | | | | | | 161 * CCM ssi pre div (CCM_CS1CDR) ----------/ | | | | | 162 * CCM ssi post div (CCM_CS1CDR) -------------/ | | | | 163 * SSI PM7_PM0_S ---------------------------------/ | | | 164 * SSI Fixed divider ---------------------------------/ | | 165 * SSI DIV2 ----------------------------------------------/ | 166 * SSI PSR (prescaler /1 or /8) ------------------------------/ 167 * 168 * MCLK (Master clock) depends on DAC, usually BCLK * 4 169 */ 170 171 struct sc_info { 172 struct resource *res[2]; 173 bus_space_tag_t bst; 174 bus_space_handle_t bsh; 175 device_t dev; 176 struct mtx lock; 177 void *ih; 178 int pos; 179 int dma_size; 180 bus_dma_tag_t dma_tag; 181 bus_dmamap_t dma_map; 182 bus_addr_t buf_base_phys; 183 uint32_t *buf_base; 184 struct sdma_conf *conf; 185 struct ssi_rate *sr; 186 struct sdma_softc *sdma_sc; 187 uint32_t sdma_ev_rx; 188 uint32_t sdma_ev_tx; 189 int sdma_channel; 190 }; 191 192 /* Channel registers */ 193 struct sc_chinfo { 194 struct snd_dbuf *buffer; 195 struct pcm_channel *channel; 196 struct sc_pcminfo *parent; 197 198 /* Channel information */ 199 uint32_t dir; 200 uint32_t format; 201 202 /* Flags */ 203 uint32_t run; 204 }; 205 206 /* PCM device private data */ 207 struct sc_pcminfo { 208 device_t dev; 209 uint32_t (*ih)(struct sc_pcminfo *scp); 210 uint32_t chnum; 211 struct sc_chinfo chan[SSI_NCHANNELS]; 212 struct sc_info *sc; 213 }; 214 215 static struct resource_spec ssi_spec[] = { 216 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 217 { SYS_RES_IRQ, 0, RF_ACTIVE }, 218 { -1, 0 } 219 }; 220 221 static int setup_dma(struct sc_pcminfo *scp); 222 static void setup_ssi(struct sc_info *); 223 static void ssi_configure_clock(struct sc_info *); 224 225 /* 226 * Mixer interface. 227 */ 228 229 static int 230 ssimixer_init(struct snd_mixer *m) 231 { 232 struct sc_pcminfo *scp; 233 struct sc_info *sc; 234 int mask; 235 236 scp = mix_getdevinfo(m); 237 sc = scp->sc; 238 239 if (sc == NULL) 240 return -1; 241 242 mask = SOUND_MASK_PCM; 243 mask |= SOUND_MASK_VOLUME; 244 245 mtx_lock(&sc->lock); 246 pcm_setflags(scp->dev, pcm_getflags(scp->dev) | SD_F_SOFTPCMVOL); 247 mix_setdevs(m, mask); 248 mtx_unlock(&sc->lock); 249 250 return (0); 251 } 252 253 static int 254 ssimixer_set(struct snd_mixer *m, unsigned dev, 255 unsigned left, unsigned right) 256 { 257 struct sc_pcminfo *scp; 258 259 scp = mix_getdevinfo(m); 260 261 /* Here we can configure hardware volume on our DAC */ 262 263 #if 1 264 device_printf(scp->dev, "ssimixer_set() %d %d\n", 265 left, right); 266 #endif 267 268 return (0); 269 } 270 271 static kobj_method_t ssimixer_methods[] = { 272 KOBJMETHOD(mixer_init, ssimixer_init), 273 KOBJMETHOD(mixer_set, ssimixer_set), 274 KOBJMETHOD_END 275 }; 276 MIXER_DECLARE(ssimixer); 277 278 /* 279 * Channel interface. 280 */ 281 282 static void * 283 ssichan_init(kobj_t obj, void *devinfo, struct snd_dbuf *b, 284 struct pcm_channel *c, int dir) 285 { 286 struct sc_pcminfo *scp; 287 struct sc_chinfo *ch; 288 struct sc_info *sc; 289 290 scp = (struct sc_pcminfo *)devinfo; 291 sc = scp->sc; 292 293 mtx_lock(&sc->lock); 294 ch = &scp->chan[0]; 295 ch->dir = dir; 296 ch->run = 0; 297 ch->buffer = b; 298 ch->channel = c; 299 ch->parent = scp; 300 mtx_unlock(&sc->lock); 301 302 if (sndbuf_setup(ch->buffer, sc->buf_base, sc->dma_size) != 0) { 303 device_printf(scp->dev, "Can't setup sndbuf.\n"); 304 return NULL; 305 } 306 307 return ch; 308 } 309 310 static int 311 ssichan_free(kobj_t obj, void *data) 312 { 313 struct sc_chinfo *ch = data; 314 struct sc_pcminfo *scp = ch->parent; 315 struct sc_info *sc = scp->sc; 316 317 #if 0 318 device_printf(scp->dev, "ssichan_free()\n"); 319 #endif 320 321 mtx_lock(&sc->lock); 322 /* TODO: free channel buffer */ 323 mtx_unlock(&sc->lock); 324 325 return (0); 326 } 327 328 static int 329 ssichan_setformat(kobj_t obj, void *data, uint32_t format) 330 { 331 struct sc_chinfo *ch = data; 332 333 ch->format = format; 334 335 return (0); 336 } 337 338 static uint32_t 339 ssichan_setspeed(kobj_t obj, void *data, uint32_t speed) 340 { 341 struct sc_pcminfo *scp; 342 struct sc_chinfo *ch; 343 struct ssi_rate *sr; 344 struct sc_info *sc; 345 int threshold; 346 int i; 347 348 ch = data; 349 scp = ch->parent; 350 sc = scp->sc; 351 352 sr = NULL; 353 354 /* First look for equal frequency. */ 355 for (i = 0; rate_map[i].speed != 0; i++) { 356 if (rate_map[i].speed == speed) 357 sr = &rate_map[i]; 358 } 359 360 /* If no match, just find nearest. */ 361 if (sr == NULL) { 362 for (i = 0; rate_map[i].speed != 0; i++) { 363 sr = &rate_map[i]; 364 threshold = sr->speed + ((rate_map[i + 1].speed != 0) ? 365 ((rate_map[i + 1].speed - sr->speed) >> 1) : 0); 366 if (speed < threshold) 367 break; 368 } 369 } 370 371 sc->sr = sr; 372 373 ssi_configure_clock(sc); 374 375 return (sr->speed); 376 } 377 378 static void 379 ssi_configure_clock(struct sc_info *sc) 380 { 381 struct ssi_rate *sr; 382 383 sr = sc->sr; 384 385 pll4_configure_output(sr->mfi, sr->mfn, sr->mfd); 386 387 /* Configure other dividers here, if any */ 388 } 389 390 static uint32_t 391 ssichan_setblocksize(kobj_t obj, void *data, uint32_t blocksize) 392 { 393 struct sc_chinfo *ch = data; 394 struct sc_pcminfo *scp = ch->parent; 395 struct sc_info *sc = scp->sc; 396 397 if (sndbuf_resize(ch->buffer, sc->dma_size / blocksize, blocksize) != 0) 398 return (0); 399 400 setup_dma(scp); 401 402 return (ch->buffer->blksz); 403 } 404 405 uint32_t 406 ssi_dma_intr(void *arg, int chn) 407 { 408 struct sc_pcminfo *scp; 409 struct sdma_conf *conf; 410 struct sc_chinfo *ch; 411 struct sc_info *sc; 412 int bufsize; 413 414 scp = arg; 415 ch = &scp->chan[0]; 416 sc = scp->sc; 417 conf = sc->conf; 418 419 bufsize = ch->buffer->bufsize; 420 421 sc->pos += conf->period; 422 if (sc->pos >= bufsize) 423 sc->pos -= bufsize; 424 425 if (ch->run) 426 chn_intr(ch->channel); 427 428 return (0); 429 } 430 431 static int 432 find_sdma_controller(struct sc_info *sc) 433 { 434 struct sdma_softc *sdma_sc; 435 phandle_t node; 436 device_t sdma_dev; 437 pcell_t dts_value[DMAS_TOTAL]; 438 int len; 439 440 if ((node = ofw_bus_get_node(sc->dev)) == -1) 441 return (ENXIO); 442 443 if ((len = OF_getproplen(node, "dmas")) <= 0) 444 return (ENXIO); 445 446 if (len != sizeof(dts_value)) { 447 device_printf(sc->dev, 448 "\"dmas\" property length is invalid: %d (expected %d)", 449 len, sizeof(dts_value)); 450 return (ENXIO); 451 } 452 453 OF_getencprop(node, "dmas", dts_value, sizeof(dts_value)); 454 455 sc->sdma_ev_rx = dts_value[1]; 456 sc->sdma_ev_tx = dts_value[5]; 457 458 sdma_sc = NULL; 459 460 sdma_dev = devclass_get_device(devclass_find("sdma"), 0); 461 if (sdma_dev) 462 sdma_sc = device_get_softc(sdma_dev); 463 464 if (sdma_sc == NULL) { 465 device_printf(sc->dev, "No sDMA found. Can't operate\n"); 466 return (ENXIO); 467 } 468 469 sc->sdma_sc = sdma_sc; 470 471 return (0); 472 }; 473 474 static int 475 setup_dma(struct sc_pcminfo *scp) 476 { 477 struct sdma_conf *conf; 478 struct sc_chinfo *ch; 479 struct sc_info *sc; 480 int fmt; 481 482 ch = &scp->chan[0]; 483 sc = scp->sc; 484 conf = sc->conf; 485 486 conf->ih = ssi_dma_intr; 487 conf->ih_user = scp; 488 conf->saddr = sc->buf_base_phys; 489 conf->daddr = rman_get_start(sc->res[0]) + SSI_STX0; 490 conf->event = sc->sdma_ev_tx; /* SDMA TX event */ 491 conf->period = ch->buffer->blksz; 492 conf->num_bd = ch->buffer->blkcnt; 493 494 /* 495 * Word Length 496 * Can be 32, 24, 16 or 8 for sDMA. 497 * 498 * SSI supports 24 at max. 499 */ 500 501 fmt = ch->buffer->fmt; 502 503 if (fmt & AFMT_16BIT) { 504 conf->word_length = 16; 505 conf->command = CMD_2BYTES; 506 } else if (fmt & AFMT_24BIT) { 507 conf->word_length = 24; 508 conf->command = CMD_3BYTES; 509 } else { 510 device_printf(sc->dev, "Unknown format\n"); 511 return (-1); 512 } 513 514 return (0); 515 } 516 517 static int 518 ssi_start(struct sc_pcminfo *scp) 519 { 520 struct sc_info *sc; 521 int reg; 522 523 sc = scp->sc; 524 525 if (sdma_configure(sc->sdma_channel, sc->conf) != 0) { 526 device_printf(sc->dev, "Can't configure sDMA\n"); 527 return (-1); 528 } 529 530 /* Enable DMA interrupt */ 531 reg = (SIER_TDMAE); 532 WRITE4(sc, SSI_SIER, reg); 533 534 sdma_start(sc->sdma_channel); 535 536 return (0); 537 } 538 539 static int 540 ssi_stop(struct sc_pcminfo *scp) 541 { 542 struct sc_info *sc; 543 int reg; 544 545 sc = scp->sc; 546 547 reg = READ4(sc, SSI_SIER); 548 reg &= ~(SIER_TDMAE); 549 WRITE4(sc, SSI_SIER, reg); 550 551 sdma_stop(sc->sdma_channel); 552 553 bzero(sc->buf_base, sc->dma_size); 554 555 return (0); 556 } 557 558 static int 559 ssichan_trigger(kobj_t obj, void *data, int go) 560 { 561 struct sc_pcminfo *scp; 562 struct sc_chinfo *ch; 563 struct sc_info *sc; 564 565 ch = data; 566 scp = ch->parent; 567 sc = scp->sc; 568 569 mtx_lock(&sc->lock); 570 571 switch (go) { 572 case PCMTRIG_START: 573 #if 0 574 device_printf(scp->dev, "trigger start\n"); 575 #endif 576 ch->run = 1; 577 578 ssi_start(scp); 579 580 break; 581 582 case PCMTRIG_STOP: 583 case PCMTRIG_ABORT: 584 #if 0 585 device_printf(scp->dev, "trigger stop or abort\n"); 586 #endif 587 ch->run = 0; 588 589 ssi_stop(scp); 590 591 break; 592 } 593 594 mtx_unlock(&sc->lock); 595 596 return (0); 597 } 598 599 static uint32_t 600 ssichan_getptr(kobj_t obj, void *data) 601 { 602 struct sc_pcminfo *scp; 603 struct sc_chinfo *ch; 604 struct sc_info *sc; 605 606 ch = data; 607 scp = ch->parent; 608 sc = scp->sc; 609 610 return (sc->pos); 611 } 612 613 static uint32_t ssi_pfmt[] = { 614 SND_FORMAT(AFMT_S24_LE, 2, 0), 615 0 616 }; 617 618 static struct pcmchan_caps ssi_pcaps = {44100, 192000, ssi_pfmt, 0}; 619 620 static struct pcmchan_caps * 621 ssichan_getcaps(kobj_t obj, void *data) 622 { 623 624 return (&ssi_pcaps); 625 } 626 627 static kobj_method_t ssichan_methods[] = { 628 KOBJMETHOD(channel_init, ssichan_init), 629 KOBJMETHOD(channel_free, ssichan_free), 630 KOBJMETHOD(channel_setformat, ssichan_setformat), 631 KOBJMETHOD(channel_setspeed, ssichan_setspeed), 632 KOBJMETHOD(channel_setblocksize, ssichan_setblocksize), 633 KOBJMETHOD(channel_trigger, ssichan_trigger), 634 KOBJMETHOD(channel_getptr, ssichan_getptr), 635 KOBJMETHOD(channel_getcaps, ssichan_getcaps), 636 KOBJMETHOD_END 637 }; 638 CHANNEL_DECLARE(ssichan); 639 640 static int 641 ssi_probe(device_t dev) 642 { 643 644 if (!ofw_bus_status_okay(dev)) 645 return (ENXIO); 646 647 if (!ofw_bus_is_compatible(dev, "fsl,imx6q-ssi")) 648 return (ENXIO); 649 650 device_set_desc(dev, "i.MX6 Synchronous Serial Interface (SSI)"); 651 return (BUS_PROBE_DEFAULT); 652 } 653 654 static void 655 ssi_intr(void *arg) 656 { 657 #if 0 658 struct sc_pcminfo *scp; 659 struct sc_info *sc; 660 661 scp = arg; 662 sc = scp->sc; 663 #endif 664 665 /* We don't use SSI interrupt */ 666 #if 0 667 device_printf(scp->sc->dev, "SSI Intr 0x%08x\n", 668 READ4(sc, SSI_SISR)); 669 #endif 670 } 671 672 static void 673 setup_ssi(struct sc_info *sc) 674 { 675 int reg; 676 677 reg = READ4(sc, SSI_STCCR); 678 reg &= ~(WL3_WL0_M << WL3_WL0_S); 679 reg |= (0xb << WL3_WL0_S); /* 24 bit */ 680 reg &= ~(DC4_DC0_M << DC4_DC0_S); 681 reg |= (1 << DC4_DC0_S); /* 2 words per frame */ 682 reg &= ~(STCCR_DIV2); /* Divide by 1 */ 683 reg &= ~(STCCR_PSR); /* Divide by 1 */ 684 reg &= ~(PM7_PM0_M << PM7_PM0_S); 685 reg |= (1 << PM7_PM0_S); /* Divide by 2 */ 686 WRITE4(sc, SSI_STCCR, reg); 687 688 reg = READ4(sc, SSI_SFCSR); 689 reg &= ~(SFCSR_TFWM0_M << SFCSR_TFWM0_S); 690 reg |= (8 << SFCSR_TFWM0_S); /* empty slots */ 691 WRITE4(sc, SSI_SFCSR, reg); 692 693 reg = READ4(sc, SSI_STCR); 694 reg |= (STCR_TFEN0); 695 reg &= ~(STCR_TFEN1); 696 reg &= ~(STCR_TSHFD); /* MSB */ 697 reg |= (STCR_TXBIT0); 698 reg |= (STCR_TXDIR | STCR_TFDIR); 699 reg |= (STCR_TSCKP); /* falling edge */ 700 reg |= (STCR_TFSI); 701 reg &= ~(STCR_TFSI); /* active high frame sync */ 702 reg &= ~(STCR_TFSL); 703 reg |= STCR_TEFS; 704 WRITE4(sc, SSI_STCR, reg); 705 706 reg = READ4(sc, SSI_SCR); 707 reg &= ~(SCR_I2S_MODE_M << SCR_I2S_MODE_S); /* Not master */ 708 reg |= (SCR_SSIEN | SCR_TE); 709 reg |= (SCR_NET); 710 reg |= (SCR_SYN); 711 WRITE4(sc, SSI_SCR, reg); 712 } 713 714 static void 715 ssi_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int err) 716 { 717 bus_addr_t *addr; 718 719 if (err) 720 return; 721 722 addr = (bus_addr_t*)arg; 723 *addr = segs[0].ds_addr; 724 } 725 726 static int 727 ssi_attach(device_t dev) 728 { 729 char status[SND_STATUSLEN]; 730 struct sc_pcminfo *scp; 731 struct sc_info *sc; 732 int err; 733 734 sc = malloc(sizeof(*sc), M_DEVBUF, M_WAITOK | M_ZERO); 735 sc->dev = dev; 736 sc->sr = &rate_map[0]; 737 sc->pos = 0; 738 sc->conf = malloc(sizeof(struct sdma_conf), M_DEVBUF, M_WAITOK | M_ZERO); 739 740 mtx_init(&sc->lock, device_get_nameunit(dev), "ssi softc", MTX_DEF); 741 742 if (bus_alloc_resources(dev, ssi_spec, sc->res)) { 743 device_printf(dev, "could not allocate resources\n"); 744 return (ENXIO); 745 } 746 747 /* Memory interface */ 748 sc->bst = rman_get_bustag(sc->res[0]); 749 sc->bsh = rman_get_bushandle(sc->res[0]); 750 751 /* SDMA */ 752 if (find_sdma_controller(sc)) { 753 device_printf(dev, "could not find active SDMA\n"); 754 return (ENXIO); 755 } 756 757 /* Setup PCM */ 758 scp = malloc(sizeof(struct sc_pcminfo), M_DEVBUF, M_NOWAIT | M_ZERO); 759 scp->sc = sc; 760 scp->dev = dev; 761 762 /* 763 * Maximum possible DMA buffer. 764 * Will be used partially to match 24 bit word. 765 */ 766 sc->dma_size = 131072; 767 768 /* 769 * Must use dma_size boundary as modulo feature required. 770 * Modulo feature allows setup circular buffer. 771 */ 772 773 err = bus_dma_tag_create( 774 bus_get_dma_tag(sc->dev), 775 4, sc->dma_size, /* alignment, boundary */ 776 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 777 BUS_SPACE_MAXADDR, /* highaddr */ 778 NULL, NULL, /* filter, filterarg */ 779 sc->dma_size, 1, /* maxsize, nsegments */ 780 sc->dma_size, 0, /* maxsegsize, flags */ 781 NULL, NULL, /* lockfunc, lockarg */ 782 &sc->dma_tag); 783 784 err = bus_dmamem_alloc(sc->dma_tag, (void **)&sc->buf_base, 785 BUS_DMA_NOWAIT | BUS_DMA_COHERENT, &sc->dma_map); 786 if (err) { 787 device_printf(dev, "cannot allocate framebuffer\n"); 788 return (ENXIO); 789 } 790 791 err = bus_dmamap_load(sc->dma_tag, sc->dma_map, sc->buf_base, 792 sc->dma_size, ssi_dmamap_cb, &sc->buf_base_phys, BUS_DMA_NOWAIT); 793 if (err) { 794 device_printf(dev, "cannot load DMA map\n"); 795 return (ENXIO); 796 } 797 798 bzero(sc->buf_base, sc->dma_size); 799 800 /* Setup interrupt handler */ 801 err = bus_setup_intr(dev, sc->res[1], INTR_MPSAFE | INTR_TYPE_AV, 802 NULL, ssi_intr, scp, &sc->ih); 803 if (err) { 804 device_printf(dev, "Unable to alloc interrupt resource.\n"); 805 return (ENXIO); 806 } 807 808 pcm_setflags(dev, pcm_getflags(dev) | SD_F_MPSAFE); 809 810 pcm_init(dev, scp); 811 812 mixer_init(dev, &ssimixer_class, scp); 813 814 scp->chnum = 0; 815 pcm_addchan(dev, PCMDIR_PLAY, &ssichan_class, scp); 816 scp->chnum++; 817 818 snprintf(status, SND_STATUSLEN, "at simplebus"); 819 err = pcm_register(dev, status); 820 if (err) { 821 device_printf(dev, "Can't register pcm.\n"); 822 return (ENXIO); 823 } 824 825 setup_ssi(sc); 826 827 imx_ccm_ssi_configure(dev); 828 829 sc->sdma_channel = sdma_alloc(); 830 if (sc->sdma_channel < 0) { 831 device_printf(sc->dev, "Can't get sDMA channel\n"); 832 return (1); 833 } 834 835 return (0); 836 } 837 838 static device_method_t ssi_pcm_methods[] = { 839 DEVMETHOD(device_probe, ssi_probe), 840 DEVMETHOD(device_attach, ssi_attach), 841 { 0, 0 } 842 }; 843 844 static driver_t ssi_pcm_driver = { 845 "pcm", 846 ssi_pcm_methods, 847 PCM_SOFTC_SIZE, 848 }; 849 850 DRIVER_MODULE(ssi, simplebus, ssi_pcm_driver, 0, 0); 851 MODULE_DEPEND(ssi, sound, 1, 1, 1); 852 MODULE_DEPEND(ssi, sdma, 0, 0, 0); 853 MODULE_VERSION(ssi, 1); 854