1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2 /* Copyright(c) 2019-2020 Realtek Corporation
3 */
4
5 #ifndef __RTW89_CORE_H__
6 #define __RTW89_CORE_H__
7
8 #include <linux/average.h>
9 #include <linux/bitfield.h>
10 #include <linux/dmi.h>
11 #include <linux/firmware.h>
12 #include <linux/iopoll.h>
13 #include <linux/workqueue.h>
14 #include <net/mac80211.h>
15 #if defined(__FreeBSD__)
16 #include <linux/seq_file.h>
17 #include <linux/lockdep.h>
18 #include <linux/interrupt.h>
19 #include <linux/pm.h>
20 #endif
21
22 struct rtw89_dev;
23 struct rtw89_pci_info;
24 struct rtw89_usb_info;
25 struct rtw89_mac_gen_def;
26 struct rtw89_phy_gen_def;
27 struct rtw89_fw_blacklist;
28 struct rtw89_efuse_block_cfg;
29 struct rtw89_h2c_rf_tssi;
30 struct rtw89_fw_txpwr_track_cfg;
31 struct rtw89_phy_rfk_log_fmt;
32 struct rtw89_debugfs;
33 struct rtw89_regd_data;
34
35 extern const struct ieee80211_ops rtw89_ops;
36
37 #define MASKBYTE0 0xff
38 #define MASKBYTE1 0xff00
39 #define MASKBYTE2 0xff0000
40 #define MASKBYTE3 0xff000000
41 #define MASKBYTE4 0xff00000000ULL
42 #define MASKHWORD 0xffff0000
43 #define MASKLWORD 0x0000ffff
44 #define MASKDWORD 0xffffffff
45 #define RFREG_MASK 0xfffff
46 #define INV_RF_DATA 0xffffffff
47 #define BYPASS_CR_DATA 0xbabecafe
48 #define RTW89_R32_EA 0xEAEAEAEA
49 #define RTW89_R32_DEAD 0xDEADBEEF
50
51 #define RTW89_TRACK_WORK_PERIOD round_jiffies_relative(HZ * 2)
52 #define RTW89_TRACK_PS_WORK_PERIOD msecs_to_jiffies(100)
53 #define RTW89_FORBID_BA_TIMER round_jiffies_relative(HZ * 4)
54 #define RTW89_PS_HANG_MAX_CNT 3
55 #define CFO_TRACK_MAX_USER 64
56 #define MAX_RSSI 110
57 #define RSSI_FACTOR 1
58 #define RTW89_RSSI_RAW_TO_DBM(rssi) ((s8)((rssi) >> RSSI_FACTOR) - MAX_RSSI)
59 #define RTW89_TX_DIV_RSSI_RAW_TH (2 << RSSI_FACTOR)
60 #define DELTA_SWINGIDX_SIZE 30
61
62 #define RTW89_RADIOTAP_ROOM_HE sizeof(struct ieee80211_radiotap_he)
63 #define RTW89_RADIOTAP_ROOM_EHT \
64 (sizeof(struct ieee80211_radiotap_tlv) + \
65 ALIGN(struct_size((struct ieee80211_radiotap_eht *)0, user_info, 1), 4) + \
66 sizeof(struct ieee80211_radiotap_tlv) + \
67 ALIGN(sizeof(struct ieee80211_radiotap_eht_usig), 4))
68 #define RTW89_RADIOTAP_ROOM \
69 ALIGN(max(RTW89_RADIOTAP_ROOM_HE, RTW89_RADIOTAP_ROOM_EHT), 64)
70
71 #define RTW89_HTC_MASK_VARIANT GENMASK(1, 0)
72 #define RTW89_HTC_VARIANT_HE 3
73 #define RTW89_HTC_MASK_CTL_ID GENMASK(5, 2)
74 #define RTW89_HTC_VARIANT_HE_CID_OM 1
75 #define RTW89_HTC_VARIANT_HE_CID_CAS 6
76 #define RTW89_HTC_MASK_CTL_INFO GENMASK(31, 6)
77
78 #define RTW89_HTC_MASK_HTC_OM_RX_NSS GENMASK(8, 6)
79 enum htc_om_channel_width {
80 HTC_OM_CHANNEL_WIDTH_20 = 0,
81 HTC_OM_CHANNEL_WIDTH_40 = 1,
82 HTC_OM_CHANNEL_WIDTH_80 = 2,
83 HTC_OM_CHANNEL_WIDTH_160_OR_80_80 = 3,
84 };
85 #define RTW89_HTC_MASK_HTC_OM_CH_WIDTH GENMASK(10, 9)
86 #define RTW89_HTC_MASK_HTC_OM_UL_MU_DIS BIT(11)
87 #define RTW89_HTC_MASK_HTC_OM_TX_NSTS GENMASK(14, 12)
88 #define RTW89_HTC_MASK_HTC_OM_ER_SU_DIS BIT(15)
89 #define RTW89_HTC_MASK_HTC_OM_DL_MU_MIMO_RR BIT(16)
90 #define RTW89_HTC_MASK_HTC_OM_UL_MU_DATA_DIS BIT(17)
91
92 #define RTW89_TF_PAD GENMASK(11, 0)
93 #define RTW89_TF_BASIC_USER_INFO_SZ 6
94
95 #define RTW89_GET_TF_USER_INFO_AID12(data) \
96 le32_get_bits(*((const __le32 *)(data)), GENMASK(11, 0))
97 #define RTW89_GET_TF_USER_INFO_RUA(data) \
98 le32_get_bits(*((const __le32 *)(data)), GENMASK(19, 12))
99 #define RTW89_GET_TF_USER_INFO_UL_MCS(data) \
100 le32_get_bits(*((const __le32 *)(data)), GENMASK(24, 21))
101
102 enum rtw89_subband {
103 RTW89_CH_2G = 0,
104 RTW89_CH_5G_BAND_1 = 1,
105 /* RTW89_CH_5G_BAND_2 = 2, unused */
106 RTW89_CH_5G_BAND_3 = 3,
107 RTW89_CH_5G_BAND_4 = 4,
108
109 RTW89_CH_6G_BAND_IDX0, /* Low */
110 RTW89_CH_6G_BAND_IDX1, /* Low */
111 RTW89_CH_6G_BAND_IDX2, /* Mid */
112 RTW89_CH_6G_BAND_IDX3, /* Mid */
113 RTW89_CH_6G_BAND_IDX4, /* High */
114 RTW89_CH_6G_BAND_IDX5, /* High */
115 RTW89_CH_6G_BAND_IDX6, /* Ultra-high */
116 RTW89_CH_6G_BAND_IDX7, /* Ultra-high */
117
118 RTW89_SUBBAND_NR,
119 RTW89_SUBBAND_2GHZ_5GHZ_NR = RTW89_CH_5G_BAND_4 + 1,
120 };
121
122 enum rtw89_gain_offset {
123 RTW89_GAIN_OFFSET_2G_CCK,
124 RTW89_GAIN_OFFSET_2G_OFDM,
125 RTW89_GAIN_OFFSET_5G_LOW,
126 RTW89_GAIN_OFFSET_5G_MID,
127 RTW89_GAIN_OFFSET_5G_HIGH,
128 RTW89_GAIN_OFFSET_6G_L0,
129 RTW89_GAIN_OFFSET_6G_L1,
130 RTW89_GAIN_OFFSET_6G_M0,
131 RTW89_GAIN_OFFSET_6G_M1,
132 RTW89_GAIN_OFFSET_6G_H0,
133 RTW89_GAIN_OFFSET_6G_H1,
134 RTW89_GAIN_OFFSET_6G_UH0,
135 RTW89_GAIN_OFFSET_6G_UH1,
136
137 RTW89_GAIN_OFFSET_NR,
138 };
139
140 enum rtw89_hci_type {
141 RTW89_HCI_TYPE_PCIE,
142 RTW89_HCI_TYPE_USB,
143 RTW89_HCI_TYPE_SDIO,
144
145 RTW89_HCI_TYPE_NUM,
146 };
147
148 enum rtw89_hci_dle_type {
149 RTW89_HCI_DLE_TYPE_PCIE,
150 RTW89_HCI_DLE_TYPE_USB2,
151 RTW89_HCI_DLE_TYPE_USB3,
152 RTW89_HCI_DLE_TYPE_SDIO,
153
154 RTW89_HCI_DLE_TYPE_NUM,
155 };
156
157 enum rtw89_core_chip_id {
158 RTL8852A,
159 RTL8852B,
160 RTL8852BT,
161 RTL8852C,
162 RTL8851B,
163 RTL8922A,
164 RTL8922D,
165 };
166
167 enum rtw89_chip_gen {
168 RTW89_CHIP_AX,
169 RTW89_CHIP_BE,
170
171 RTW89_CHIP_GEN_NUM,
172 };
173
174 enum rtw89_cv {
175 CHIP_CAV,
176 CHIP_CBV,
177 CHIP_CCV,
178 CHIP_CDV,
179 CHIP_CEV,
180 CHIP_CFV,
181 CHIP_CV_MAX,
182 CHIP_CV_INVALID = CHIP_CV_MAX,
183 };
184
185 enum rtw89_bacam_ver {
186 RTW89_BACAM_V0,
187 RTW89_BACAM_V1,
188
189 RTW89_BACAM_V0_EXT = 99,
190 };
191
192 enum rtw89_core_tx_type {
193 RTW89_CORE_TX_TYPE_DATA,
194 RTW89_CORE_TX_TYPE_MGMT,
195 RTW89_CORE_TX_TYPE_FWCMD,
196 };
197
198 enum rtw89_core_rx_type {
199 RTW89_CORE_RX_TYPE_WIFI = 0,
200 RTW89_CORE_RX_TYPE_PPDU_STAT = 1,
201 RTW89_CORE_RX_TYPE_CHAN_INFO = 2,
202 RTW89_CORE_RX_TYPE_BB_SCOPE = 3,
203 RTW89_CORE_RX_TYPE_F2P_TXCMD = 4,
204 RTW89_CORE_RX_TYPE_SS2FW = 5,
205 RTW89_CORE_RX_TYPE_TX_REPORT = 6,
206 RTW89_CORE_RX_TYPE_TX_REL_HOST = 7,
207 RTW89_CORE_RX_TYPE_DFS_REPORT = 8,
208 RTW89_CORE_RX_TYPE_TX_REL_CPU = 9,
209 RTW89_CORE_RX_TYPE_C2H = 10,
210 RTW89_CORE_RX_TYPE_CSI = 11,
211 RTW89_CORE_RX_TYPE_CQI = 12,
212 RTW89_CORE_RX_TYPE_H2C = 13,
213 RTW89_CORE_RX_TYPE_FWDL = 14,
214 };
215
216 enum rtw89_txq_flags {
217 RTW89_TXQ_F_AMPDU = 0,
218 RTW89_TXQ_F_BLOCK_BA = 1,
219 RTW89_TXQ_F_FORBID_BA = 2,
220 };
221
222 enum rtw89_net_type {
223 RTW89_NET_TYPE_NO_LINK = 0,
224 RTW89_NET_TYPE_AD_HOC = 1,
225 RTW89_NET_TYPE_INFRA = 2,
226 RTW89_NET_TYPE_AP_MODE = 3,
227 };
228
229 enum rtw89_wifi_role {
230 RTW89_WIFI_ROLE_NONE,
231 RTW89_WIFI_ROLE_STATION,
232 RTW89_WIFI_ROLE_AP,
233 RTW89_WIFI_ROLE_AP_VLAN,
234 RTW89_WIFI_ROLE_ADHOC,
235 RTW89_WIFI_ROLE_ADHOC_MASTER,
236 RTW89_WIFI_ROLE_MESH_POINT,
237 RTW89_WIFI_ROLE_MONITOR,
238 RTW89_WIFI_ROLE_P2P_DEVICE,
239 RTW89_WIFI_ROLE_P2P_CLIENT,
240 RTW89_WIFI_ROLE_P2P_GO,
241 RTW89_WIFI_ROLE_NAN,
242 RTW89_WIFI_ROLE_MLME_MAX
243 };
244
245 enum rtw89_upd_mode {
246 RTW89_ROLE_CREATE,
247 RTW89_ROLE_REMOVE,
248 RTW89_ROLE_TYPE_CHANGE,
249 RTW89_ROLE_INFO_CHANGE,
250 RTW89_ROLE_CON_DISCONN,
251 RTW89_ROLE_BAND_SW,
252 RTW89_ROLE_FW_RESTORE,
253 };
254
255 enum rtw89_self_role {
256 RTW89_SELF_ROLE_CLIENT,
257 RTW89_SELF_ROLE_AP,
258 RTW89_SELF_ROLE_AP_CLIENT
259 };
260
261 enum rtw89_msk_sO_el {
262 RTW89_NO_MSK,
263 RTW89_SMA,
264 RTW89_TMA,
265 RTW89_BSSID
266 };
267
268 enum rtw89_sch_tx_sel {
269 RTW89_SCH_TX_SEL_ALL,
270 RTW89_SCH_TX_SEL_HIQ,
271 RTW89_SCH_TX_SEL_MG0,
272 RTW89_SCH_TX_SEL_MACID,
273 };
274
275 /* RTW89_ADDR_CAM_SEC_NONE : not enabled
276 * RTW89_ADDR_CAM_SEC_ALL_UNI : 0 - 6 unicast
277 * RTW89_ADDR_CAM_SEC_NORMAL : 0 - 1 unicast, 2 - 4 group, 5 - 6 BIP
278 * RTW89_ADDR_CAM_SEC_4GROUP : 0 - 1 unicast, 2 - 5 group, 6 BIP
279 */
280 enum rtw89_add_cam_sec_mode {
281 RTW89_ADDR_CAM_SEC_NONE = 0,
282 RTW89_ADDR_CAM_SEC_ALL_UNI = 1,
283 RTW89_ADDR_CAM_SEC_NORMAL = 2,
284 RTW89_ADDR_CAM_SEC_4GROUP = 3,
285 };
286
287 enum rtw89_sec_key_type {
288 RTW89_SEC_KEY_TYPE_NONE = 0,
289 RTW89_SEC_KEY_TYPE_WEP40 = 1,
290 RTW89_SEC_KEY_TYPE_WEP104 = 2,
291 RTW89_SEC_KEY_TYPE_TKIP = 3,
292 RTW89_SEC_KEY_TYPE_WAPI = 4,
293 RTW89_SEC_KEY_TYPE_GCMSMS4 = 5,
294 RTW89_SEC_KEY_TYPE_CCMP128 = 6,
295 RTW89_SEC_KEY_TYPE_CCMP256 = 7,
296 RTW89_SEC_KEY_TYPE_GCMP128 = 8,
297 RTW89_SEC_KEY_TYPE_GCMP256 = 9,
298 RTW89_SEC_KEY_TYPE_BIP_CCMP128 = 10,
299 };
300
301 enum rtw89_port {
302 RTW89_PORT_0 = 0,
303 RTW89_PORT_1 = 1,
304 RTW89_PORT_2 = 2,
305 RTW89_PORT_3 = 3,
306 RTW89_PORT_4 = 4,
307 RTW89_PORT_NUM
308 };
309
310 enum rtw89_band {
311 RTW89_BAND_2G = 0,
312 RTW89_BAND_5G = 1,
313 RTW89_BAND_6G = 2,
314 RTW89_BAND_NUM,
315 };
316
317 enum rtw89_hw_rate {
318 RTW89_HW_RATE_CCK1 = 0x0,
319 RTW89_HW_RATE_CCK2 = 0x1,
320 RTW89_HW_RATE_CCK5_5 = 0x2,
321 RTW89_HW_RATE_CCK11 = 0x3,
322 RTW89_HW_RATE_OFDM6 = 0x4,
323 RTW89_HW_RATE_OFDM9 = 0x5,
324 RTW89_HW_RATE_OFDM12 = 0x6,
325 RTW89_HW_RATE_OFDM18 = 0x7,
326 RTW89_HW_RATE_OFDM24 = 0x8,
327 RTW89_HW_RATE_OFDM36 = 0x9,
328 RTW89_HW_RATE_OFDM48 = 0xA,
329 RTW89_HW_RATE_OFDM54 = 0xB,
330 RTW89_HW_RATE_MCS0 = 0x80,
331 RTW89_HW_RATE_MCS1 = 0x81,
332 RTW89_HW_RATE_MCS2 = 0x82,
333 RTW89_HW_RATE_MCS3 = 0x83,
334 RTW89_HW_RATE_MCS4 = 0x84,
335 RTW89_HW_RATE_MCS5 = 0x85,
336 RTW89_HW_RATE_MCS6 = 0x86,
337 RTW89_HW_RATE_MCS7 = 0x87,
338 RTW89_HW_RATE_MCS8 = 0x88,
339 RTW89_HW_RATE_MCS9 = 0x89,
340 RTW89_HW_RATE_MCS10 = 0x8A,
341 RTW89_HW_RATE_MCS11 = 0x8B,
342 RTW89_HW_RATE_MCS12 = 0x8C,
343 RTW89_HW_RATE_MCS13 = 0x8D,
344 RTW89_HW_RATE_MCS14 = 0x8E,
345 RTW89_HW_RATE_MCS15 = 0x8F,
346 RTW89_HW_RATE_MCS16 = 0x90,
347 RTW89_HW_RATE_MCS17 = 0x91,
348 RTW89_HW_RATE_MCS18 = 0x92,
349 RTW89_HW_RATE_MCS19 = 0x93,
350 RTW89_HW_RATE_MCS20 = 0x94,
351 RTW89_HW_RATE_MCS21 = 0x95,
352 RTW89_HW_RATE_MCS22 = 0x96,
353 RTW89_HW_RATE_MCS23 = 0x97,
354 RTW89_HW_RATE_MCS24 = 0x98,
355 RTW89_HW_RATE_MCS25 = 0x99,
356 RTW89_HW_RATE_MCS26 = 0x9A,
357 RTW89_HW_RATE_MCS27 = 0x9B,
358 RTW89_HW_RATE_MCS28 = 0x9C,
359 RTW89_HW_RATE_MCS29 = 0x9D,
360 RTW89_HW_RATE_MCS30 = 0x9E,
361 RTW89_HW_RATE_MCS31 = 0x9F,
362 RTW89_HW_RATE_VHT_NSS1_MCS0 = 0x100,
363 RTW89_HW_RATE_VHT_NSS1_MCS1 = 0x101,
364 RTW89_HW_RATE_VHT_NSS1_MCS2 = 0x102,
365 RTW89_HW_RATE_VHT_NSS1_MCS3 = 0x103,
366 RTW89_HW_RATE_VHT_NSS1_MCS4 = 0x104,
367 RTW89_HW_RATE_VHT_NSS1_MCS5 = 0x105,
368 RTW89_HW_RATE_VHT_NSS1_MCS6 = 0x106,
369 RTW89_HW_RATE_VHT_NSS1_MCS7 = 0x107,
370 RTW89_HW_RATE_VHT_NSS1_MCS8 = 0x108,
371 RTW89_HW_RATE_VHT_NSS1_MCS9 = 0x109,
372 RTW89_HW_RATE_VHT_NSS2_MCS0 = 0x110,
373 RTW89_HW_RATE_VHT_NSS2_MCS1 = 0x111,
374 RTW89_HW_RATE_VHT_NSS2_MCS2 = 0x112,
375 RTW89_HW_RATE_VHT_NSS2_MCS3 = 0x113,
376 RTW89_HW_RATE_VHT_NSS2_MCS4 = 0x114,
377 RTW89_HW_RATE_VHT_NSS2_MCS5 = 0x115,
378 RTW89_HW_RATE_VHT_NSS2_MCS6 = 0x116,
379 RTW89_HW_RATE_VHT_NSS2_MCS7 = 0x117,
380 RTW89_HW_RATE_VHT_NSS2_MCS8 = 0x118,
381 RTW89_HW_RATE_VHT_NSS2_MCS9 = 0x119,
382 RTW89_HW_RATE_VHT_NSS3_MCS0 = 0x120,
383 RTW89_HW_RATE_VHT_NSS3_MCS1 = 0x121,
384 RTW89_HW_RATE_VHT_NSS3_MCS2 = 0x122,
385 RTW89_HW_RATE_VHT_NSS3_MCS3 = 0x123,
386 RTW89_HW_RATE_VHT_NSS3_MCS4 = 0x124,
387 RTW89_HW_RATE_VHT_NSS3_MCS5 = 0x125,
388 RTW89_HW_RATE_VHT_NSS3_MCS6 = 0x126,
389 RTW89_HW_RATE_VHT_NSS3_MCS7 = 0x127,
390 RTW89_HW_RATE_VHT_NSS3_MCS8 = 0x128,
391 RTW89_HW_RATE_VHT_NSS3_MCS9 = 0x129,
392 RTW89_HW_RATE_VHT_NSS4_MCS0 = 0x130,
393 RTW89_HW_RATE_VHT_NSS4_MCS1 = 0x131,
394 RTW89_HW_RATE_VHT_NSS4_MCS2 = 0x132,
395 RTW89_HW_RATE_VHT_NSS4_MCS3 = 0x133,
396 RTW89_HW_RATE_VHT_NSS4_MCS4 = 0x134,
397 RTW89_HW_RATE_VHT_NSS4_MCS5 = 0x135,
398 RTW89_HW_RATE_VHT_NSS4_MCS6 = 0x136,
399 RTW89_HW_RATE_VHT_NSS4_MCS7 = 0x137,
400 RTW89_HW_RATE_VHT_NSS4_MCS8 = 0x138,
401 RTW89_HW_RATE_VHT_NSS4_MCS9 = 0x139,
402 RTW89_HW_RATE_HE_NSS1_MCS0 = 0x180,
403 RTW89_HW_RATE_HE_NSS1_MCS1 = 0x181,
404 RTW89_HW_RATE_HE_NSS1_MCS2 = 0x182,
405 RTW89_HW_RATE_HE_NSS1_MCS3 = 0x183,
406 RTW89_HW_RATE_HE_NSS1_MCS4 = 0x184,
407 RTW89_HW_RATE_HE_NSS1_MCS5 = 0x185,
408 RTW89_HW_RATE_HE_NSS1_MCS6 = 0x186,
409 RTW89_HW_RATE_HE_NSS1_MCS7 = 0x187,
410 RTW89_HW_RATE_HE_NSS1_MCS8 = 0x188,
411 RTW89_HW_RATE_HE_NSS1_MCS9 = 0x189,
412 RTW89_HW_RATE_HE_NSS1_MCS10 = 0x18A,
413 RTW89_HW_RATE_HE_NSS1_MCS11 = 0x18B,
414 RTW89_HW_RATE_HE_NSS2_MCS0 = 0x190,
415 RTW89_HW_RATE_HE_NSS2_MCS1 = 0x191,
416 RTW89_HW_RATE_HE_NSS2_MCS2 = 0x192,
417 RTW89_HW_RATE_HE_NSS2_MCS3 = 0x193,
418 RTW89_HW_RATE_HE_NSS2_MCS4 = 0x194,
419 RTW89_HW_RATE_HE_NSS2_MCS5 = 0x195,
420 RTW89_HW_RATE_HE_NSS2_MCS6 = 0x196,
421 RTW89_HW_RATE_HE_NSS2_MCS7 = 0x197,
422 RTW89_HW_RATE_HE_NSS2_MCS8 = 0x198,
423 RTW89_HW_RATE_HE_NSS2_MCS9 = 0x199,
424 RTW89_HW_RATE_HE_NSS2_MCS10 = 0x19A,
425 RTW89_HW_RATE_HE_NSS2_MCS11 = 0x19B,
426 RTW89_HW_RATE_HE_NSS3_MCS0 = 0x1A0,
427 RTW89_HW_RATE_HE_NSS3_MCS1 = 0x1A1,
428 RTW89_HW_RATE_HE_NSS3_MCS2 = 0x1A2,
429 RTW89_HW_RATE_HE_NSS3_MCS3 = 0x1A3,
430 RTW89_HW_RATE_HE_NSS3_MCS4 = 0x1A4,
431 RTW89_HW_RATE_HE_NSS3_MCS5 = 0x1A5,
432 RTW89_HW_RATE_HE_NSS3_MCS6 = 0x1A6,
433 RTW89_HW_RATE_HE_NSS3_MCS7 = 0x1A7,
434 RTW89_HW_RATE_HE_NSS3_MCS8 = 0x1A8,
435 RTW89_HW_RATE_HE_NSS3_MCS9 = 0x1A9,
436 RTW89_HW_RATE_HE_NSS3_MCS10 = 0x1AA,
437 RTW89_HW_RATE_HE_NSS3_MCS11 = 0x1AB,
438 RTW89_HW_RATE_HE_NSS4_MCS0 = 0x1B0,
439 RTW89_HW_RATE_HE_NSS4_MCS1 = 0x1B1,
440 RTW89_HW_RATE_HE_NSS4_MCS2 = 0x1B2,
441 RTW89_HW_RATE_HE_NSS4_MCS3 = 0x1B3,
442 RTW89_HW_RATE_HE_NSS4_MCS4 = 0x1B4,
443 RTW89_HW_RATE_HE_NSS4_MCS5 = 0x1B5,
444 RTW89_HW_RATE_HE_NSS4_MCS6 = 0x1B6,
445 RTW89_HW_RATE_HE_NSS4_MCS7 = 0x1B7,
446 RTW89_HW_RATE_HE_NSS4_MCS8 = 0x1B8,
447 RTW89_HW_RATE_HE_NSS4_MCS9 = 0x1B9,
448 RTW89_HW_RATE_HE_NSS4_MCS10 = 0x1BA,
449 RTW89_HW_RATE_HE_NSS4_MCS11 = 0x1BB,
450
451 RTW89_HW_RATE_V1_MCS0 = 0x100,
452 RTW89_HW_RATE_V1_MCS1 = 0x101,
453 RTW89_HW_RATE_V1_MCS2 = 0x102,
454 RTW89_HW_RATE_V1_MCS3 = 0x103,
455 RTW89_HW_RATE_V1_MCS4 = 0x104,
456 RTW89_HW_RATE_V1_MCS5 = 0x105,
457 RTW89_HW_RATE_V1_MCS6 = 0x106,
458 RTW89_HW_RATE_V1_MCS7 = 0x107,
459 RTW89_HW_RATE_V1_MCS8 = 0x108,
460 RTW89_HW_RATE_V1_MCS9 = 0x109,
461 RTW89_HW_RATE_V1_MCS10 = 0x10A,
462 RTW89_HW_RATE_V1_MCS11 = 0x10B,
463 RTW89_HW_RATE_V1_MCS12 = 0x10C,
464 RTW89_HW_RATE_V1_MCS13 = 0x10D,
465 RTW89_HW_RATE_V1_MCS14 = 0x10E,
466 RTW89_HW_RATE_V1_MCS15 = 0x10F,
467 RTW89_HW_RATE_V1_MCS16 = 0x110,
468 RTW89_HW_RATE_V1_MCS17 = 0x111,
469 RTW89_HW_RATE_V1_MCS18 = 0x112,
470 RTW89_HW_RATE_V1_MCS19 = 0x113,
471 RTW89_HW_RATE_V1_MCS20 = 0x114,
472 RTW89_HW_RATE_V1_MCS21 = 0x115,
473 RTW89_HW_RATE_V1_MCS22 = 0x116,
474 RTW89_HW_RATE_V1_MCS23 = 0x117,
475 RTW89_HW_RATE_V1_MCS24 = 0x118,
476 RTW89_HW_RATE_V1_MCS25 = 0x119,
477 RTW89_HW_RATE_V1_MCS26 = 0x11A,
478 RTW89_HW_RATE_V1_MCS27 = 0x11B,
479 RTW89_HW_RATE_V1_MCS28 = 0x11C,
480 RTW89_HW_RATE_V1_MCS29 = 0x11D,
481 RTW89_HW_RATE_V1_MCS30 = 0x11E,
482 RTW89_HW_RATE_V1_MCS31 = 0x11F,
483 RTW89_HW_RATE_V1_VHT_NSS1_MCS0 = 0x200,
484 RTW89_HW_RATE_V1_VHT_NSS1_MCS1 = 0x201,
485 RTW89_HW_RATE_V1_VHT_NSS1_MCS2 = 0x202,
486 RTW89_HW_RATE_V1_VHT_NSS1_MCS3 = 0x203,
487 RTW89_HW_RATE_V1_VHT_NSS1_MCS4 = 0x204,
488 RTW89_HW_RATE_V1_VHT_NSS1_MCS5 = 0x205,
489 RTW89_HW_RATE_V1_VHT_NSS1_MCS6 = 0x206,
490 RTW89_HW_RATE_V1_VHT_NSS1_MCS7 = 0x207,
491 RTW89_HW_RATE_V1_VHT_NSS1_MCS8 = 0x208,
492 RTW89_HW_RATE_V1_VHT_NSS1_MCS9 = 0x209,
493 RTW89_HW_RATE_V1_VHT_NSS1_MCS10 = 0x20A,
494 RTW89_HW_RATE_V1_VHT_NSS1_MCS11 = 0x20B,
495 RTW89_HW_RATE_V1_VHT_NSS2_MCS0 = 0x220,
496 RTW89_HW_RATE_V1_VHT_NSS2_MCS1 = 0x221,
497 RTW89_HW_RATE_V1_VHT_NSS2_MCS2 = 0x222,
498 RTW89_HW_RATE_V1_VHT_NSS2_MCS3 = 0x223,
499 RTW89_HW_RATE_V1_VHT_NSS2_MCS4 = 0x224,
500 RTW89_HW_RATE_V1_VHT_NSS2_MCS5 = 0x225,
501 RTW89_HW_RATE_V1_VHT_NSS2_MCS6 = 0x226,
502 RTW89_HW_RATE_V1_VHT_NSS2_MCS7 = 0x227,
503 RTW89_HW_RATE_V1_VHT_NSS2_MCS8 = 0x228,
504 RTW89_HW_RATE_V1_VHT_NSS2_MCS9 = 0x229,
505 RTW89_HW_RATE_V1_VHT_NSS2_MCS10 = 0x22A,
506 RTW89_HW_RATE_V1_VHT_NSS2_MCS11 = 0x22B,
507 RTW89_HW_RATE_V1_VHT_NSS3_MCS0 = 0x240,
508 RTW89_HW_RATE_V1_VHT_NSS3_MCS1 = 0x241,
509 RTW89_HW_RATE_V1_VHT_NSS3_MCS2 = 0x242,
510 RTW89_HW_RATE_V1_VHT_NSS3_MCS3 = 0x243,
511 RTW89_HW_RATE_V1_VHT_NSS3_MCS4 = 0x244,
512 RTW89_HW_RATE_V1_VHT_NSS3_MCS5 = 0x245,
513 RTW89_HW_RATE_V1_VHT_NSS3_MCS6 = 0x246,
514 RTW89_HW_RATE_V1_VHT_NSS3_MCS7 = 0x247,
515 RTW89_HW_RATE_V1_VHT_NSS3_MCS8 = 0x248,
516 RTW89_HW_RATE_V1_VHT_NSS3_MCS9 = 0x249,
517 RTW89_HW_RATE_V1_VHT_NSS3_MCS10 = 0x24A,
518 RTW89_HW_RATE_V1_VHT_NSS3_MCS11 = 0x24B,
519 RTW89_HW_RATE_V1_VHT_NSS4_MCS0 = 0x260,
520 RTW89_HW_RATE_V1_VHT_NSS4_MCS1 = 0x261,
521 RTW89_HW_RATE_V1_VHT_NSS4_MCS2 = 0x262,
522 RTW89_HW_RATE_V1_VHT_NSS4_MCS3 = 0x263,
523 RTW89_HW_RATE_V1_VHT_NSS4_MCS4 = 0x264,
524 RTW89_HW_RATE_V1_VHT_NSS4_MCS5 = 0x265,
525 RTW89_HW_RATE_V1_VHT_NSS4_MCS6 = 0x266,
526 RTW89_HW_RATE_V1_VHT_NSS4_MCS7 = 0x267,
527 RTW89_HW_RATE_V1_VHT_NSS4_MCS8 = 0x268,
528 RTW89_HW_RATE_V1_VHT_NSS4_MCS9 = 0x269,
529 RTW89_HW_RATE_V1_VHT_NSS4_MCS10 = 0x26A,
530 RTW89_HW_RATE_V1_VHT_NSS4_MCS11 = 0x26B,
531 RTW89_HW_RATE_V1_HE_NSS1_MCS0 = 0x300,
532 RTW89_HW_RATE_V1_HE_NSS1_MCS1 = 0x301,
533 RTW89_HW_RATE_V1_HE_NSS1_MCS2 = 0x302,
534 RTW89_HW_RATE_V1_HE_NSS1_MCS3 = 0x303,
535 RTW89_HW_RATE_V1_HE_NSS1_MCS4 = 0x304,
536 RTW89_HW_RATE_V1_HE_NSS1_MCS5 = 0x305,
537 RTW89_HW_RATE_V1_HE_NSS1_MCS6 = 0x306,
538 RTW89_HW_RATE_V1_HE_NSS1_MCS7 = 0x307,
539 RTW89_HW_RATE_V1_HE_NSS1_MCS8 = 0x308,
540 RTW89_HW_RATE_V1_HE_NSS1_MCS9 = 0x309,
541 RTW89_HW_RATE_V1_HE_NSS1_MCS10 = 0x30A,
542 RTW89_HW_RATE_V1_HE_NSS1_MCS11 = 0x30B,
543 RTW89_HW_RATE_V1_HE_NSS2_MCS0 = 0x320,
544 RTW89_HW_RATE_V1_HE_NSS2_MCS1 = 0x321,
545 RTW89_HW_RATE_V1_HE_NSS2_MCS2 = 0x322,
546 RTW89_HW_RATE_V1_HE_NSS2_MCS3 = 0x323,
547 RTW89_HW_RATE_V1_HE_NSS2_MCS4 = 0x324,
548 RTW89_HW_RATE_V1_HE_NSS2_MCS5 = 0x325,
549 RTW89_HW_RATE_V1_HE_NSS2_MCS6 = 0x326,
550 RTW89_HW_RATE_V1_HE_NSS2_MCS7 = 0x327,
551 RTW89_HW_RATE_V1_HE_NSS2_MCS8 = 0x328,
552 RTW89_HW_RATE_V1_HE_NSS2_MCS9 = 0x329,
553 RTW89_HW_RATE_V1_HE_NSS2_MCS10 = 0x32A,
554 RTW89_HW_RATE_V1_HE_NSS2_MCS11 = 0x32B,
555 RTW89_HW_RATE_V1_HE_NSS3_MCS0 = 0x340,
556 RTW89_HW_RATE_V1_HE_NSS3_MCS1 = 0x341,
557 RTW89_HW_RATE_V1_HE_NSS3_MCS2 = 0x342,
558 RTW89_HW_RATE_V1_HE_NSS3_MCS3 = 0x343,
559 RTW89_HW_RATE_V1_HE_NSS3_MCS4 = 0x344,
560 RTW89_HW_RATE_V1_HE_NSS3_MCS5 = 0x345,
561 RTW89_HW_RATE_V1_HE_NSS3_MCS6 = 0x346,
562 RTW89_HW_RATE_V1_HE_NSS3_MCS7 = 0x347,
563 RTW89_HW_RATE_V1_HE_NSS3_MCS8 = 0x348,
564 RTW89_HW_RATE_V1_HE_NSS3_MCS9 = 0x349,
565 RTW89_HW_RATE_V1_HE_NSS3_MCS10 = 0x34A,
566 RTW89_HW_RATE_V1_HE_NSS3_MCS11 = 0x34B,
567 RTW89_HW_RATE_V1_HE_NSS4_MCS0 = 0x360,
568 RTW89_HW_RATE_V1_HE_NSS4_MCS1 = 0x361,
569 RTW89_HW_RATE_V1_HE_NSS4_MCS2 = 0x362,
570 RTW89_HW_RATE_V1_HE_NSS4_MCS3 = 0x363,
571 RTW89_HW_RATE_V1_HE_NSS4_MCS4 = 0x364,
572 RTW89_HW_RATE_V1_HE_NSS4_MCS5 = 0x365,
573 RTW89_HW_RATE_V1_HE_NSS4_MCS6 = 0x366,
574 RTW89_HW_RATE_V1_HE_NSS4_MCS7 = 0x367,
575 RTW89_HW_RATE_V1_HE_NSS4_MCS8 = 0x368,
576 RTW89_HW_RATE_V1_HE_NSS4_MCS9 = 0x369,
577 RTW89_HW_RATE_V1_HE_NSS4_MCS10 = 0x36A,
578 RTW89_HW_RATE_V1_HE_NSS4_MCS11 = 0x36B,
579 RTW89_HW_RATE_V1_EHT_NSS1_MCS0 = 0x400,
580 RTW89_HW_RATE_V1_EHT_NSS1_MCS1 = 0x401,
581 RTW89_HW_RATE_V1_EHT_NSS1_MCS2 = 0x402,
582 RTW89_HW_RATE_V1_EHT_NSS1_MCS3 = 0x403,
583 RTW89_HW_RATE_V1_EHT_NSS1_MCS4 = 0x404,
584 RTW89_HW_RATE_V1_EHT_NSS1_MCS5 = 0x405,
585 RTW89_HW_RATE_V1_EHT_NSS1_MCS6 = 0x406,
586 RTW89_HW_RATE_V1_EHT_NSS1_MCS7 = 0x407,
587 RTW89_HW_RATE_V1_EHT_NSS1_MCS8 = 0x408,
588 RTW89_HW_RATE_V1_EHT_NSS1_MCS9 = 0x409,
589 RTW89_HW_RATE_V1_EHT_NSS1_MCS10 = 0x40A,
590 RTW89_HW_RATE_V1_EHT_NSS1_MCS11 = 0x40B,
591 RTW89_HW_RATE_V1_EHT_NSS1_MCS12 = 0x40C,
592 RTW89_HW_RATE_V1_EHT_NSS1_MCS13 = 0x40D,
593 RTW89_HW_RATE_V1_EHT_NSS1_MCS14 = 0x40E,
594 RTW89_HW_RATE_V1_EHT_NSS1_MCS15 = 0x40F,
595 RTW89_HW_RATE_V1_EHT_NSS2_MCS0 = 0x420,
596 RTW89_HW_RATE_V1_EHT_NSS2_MCS1 = 0x421,
597 RTW89_HW_RATE_V1_EHT_NSS2_MCS2 = 0x422,
598 RTW89_HW_RATE_V1_EHT_NSS2_MCS3 = 0x423,
599 RTW89_HW_RATE_V1_EHT_NSS2_MCS4 = 0x424,
600 RTW89_HW_RATE_V1_EHT_NSS2_MCS5 = 0x425,
601 RTW89_HW_RATE_V1_EHT_NSS2_MCS6 = 0x426,
602 RTW89_HW_RATE_V1_EHT_NSS2_MCS7 = 0x427,
603 RTW89_HW_RATE_V1_EHT_NSS2_MCS8 = 0x428,
604 RTW89_HW_RATE_V1_EHT_NSS2_MCS9 = 0x429,
605 RTW89_HW_RATE_V1_EHT_NSS2_MCS10 = 0x42A,
606 RTW89_HW_RATE_V1_EHT_NSS2_MCS11 = 0x42B,
607 RTW89_HW_RATE_V1_EHT_NSS2_MCS12 = 0x42C,
608 RTW89_HW_RATE_V1_EHT_NSS2_MCS13 = 0x42D,
609 RTW89_HW_RATE_V1_EHT_NSS3_MCS0 = 0x440,
610 RTW89_HW_RATE_V1_EHT_NSS3_MCS1 = 0x441,
611 RTW89_HW_RATE_V1_EHT_NSS3_MCS2 = 0x442,
612 RTW89_HW_RATE_V1_EHT_NSS3_MCS3 = 0x443,
613 RTW89_HW_RATE_V1_EHT_NSS3_MCS4 = 0x444,
614 RTW89_HW_RATE_V1_EHT_NSS3_MCS5 = 0x445,
615 RTW89_HW_RATE_V1_EHT_NSS3_MCS6 = 0x446,
616 RTW89_HW_RATE_V1_EHT_NSS3_MCS7 = 0x447,
617 RTW89_HW_RATE_V1_EHT_NSS3_MCS8 = 0x448,
618 RTW89_HW_RATE_V1_EHT_NSS3_MCS9 = 0x449,
619 RTW89_HW_RATE_V1_EHT_NSS3_MCS10 = 0x44A,
620 RTW89_HW_RATE_V1_EHT_NSS3_MCS11 = 0x44B,
621 RTW89_HW_RATE_V1_EHT_NSS3_MCS12 = 0x44C,
622 RTW89_HW_RATE_V1_EHT_NSS3_MCS13 = 0x44D,
623 RTW89_HW_RATE_V1_EHT_NSS4_MCS0 = 0x460,
624 RTW89_HW_RATE_V1_EHT_NSS4_MCS1 = 0x461,
625 RTW89_HW_RATE_V1_EHT_NSS4_MCS2 = 0x462,
626 RTW89_HW_RATE_V1_EHT_NSS4_MCS3 = 0x463,
627 RTW89_HW_RATE_V1_EHT_NSS4_MCS4 = 0x464,
628 RTW89_HW_RATE_V1_EHT_NSS4_MCS5 = 0x465,
629 RTW89_HW_RATE_V1_EHT_NSS4_MCS6 = 0x466,
630 RTW89_HW_RATE_V1_EHT_NSS4_MCS7 = 0x467,
631 RTW89_HW_RATE_V1_EHT_NSS4_MCS8 = 0x468,
632 RTW89_HW_RATE_V1_EHT_NSS4_MCS9 = 0x469,
633 RTW89_HW_RATE_V1_EHT_NSS4_MCS10 = 0x46A,
634 RTW89_HW_RATE_V1_EHT_NSS4_MCS11 = 0x46B,
635 RTW89_HW_RATE_V1_EHT_NSS4_MCS12 = 0x46C,
636 RTW89_HW_RATE_V1_EHT_NSS4_MCS13 = 0x46D,
637
638 RTW89_HW_RATE_NR,
639 RTW89_HW_RATE_INVAL,
640
641 RTW89_HW_RATE_MASK_MOD = GENMASK(8, 7),
642 RTW89_HW_RATE_MASK_VAL = GENMASK(6, 0),
643 RTW89_HW_RATE_V1_MASK_MOD = GENMASK(10, 8),
644 RTW89_HW_RATE_V1_MASK_VAL = GENMASK(7, 0),
645 };
646
647 /* 2G channels,
648 * 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14
649 */
650 #define RTW89_2G_CH_NUM 14
651
652 /* 5G channels,
653 * 36, 38, 40, 42, 44, 46, 48, 50,
654 * 52, 54, 56, 58, 60, 62, 64,
655 * 100, 102, 104, 106, 108, 110, 112, 114,
656 * 116, 118, 120, 122, 124, 126, 128, 130,
657 * 132, 134, 136, 138, 140, 142, 144,
658 * 149, 151, 153, 155, 157, 159, 161, 163,
659 * 165, 167, 169, 171, 173, 175, 177
660 */
661 #define RTW89_5G_CH_NUM 53
662
663 /* 6G channels,
664 * 1, 3, 5, 7, 9, 11, 13, 15,
665 * 17, 19, 21, 23, 25, 27, 29, 33,
666 * 35, 37, 39, 41, 43, 45, 47, 49,
667 * 51, 53, 55, 57, 59, 61, 65, 67,
668 * 69, 71, 73, 75, 77, 79, 81, 83,
669 * 85, 87, 89, 91, 93, 97, 99, 101,
670 * 103, 105, 107, 109, 111, 113, 115, 117,
671 * 119, 121, 123, 125, 129, 131, 133, 135,
672 * 137, 139, 141, 143, 145, 147, 149, 151,
673 * 153, 155, 157, 161, 163, 165, 167, 169,
674 * 171, 173, 175, 177, 179, 181, 183, 185,
675 * 187, 189, 193, 195, 197, 199, 201, 203,
676 * 205, 207, 209, 211, 213, 215, 217, 219,
677 * 221, 225, 227, 229, 231, 233, 235, 237,
678 * 239, 241, 243, 245, 247, 249, 251, 253,
679 */
680 #define RTW89_6G_CH_NUM 120
681
682 enum rtw89_rate_section {
683 RTW89_RS_CCK,
684 RTW89_RS_OFDM,
685 RTW89_RS_MCS, /* for HT/VHT/HE */
686 RTW89_RS_HEDCM,
687 RTW89_RS_OFFSET,
688 RTW89_RS_NUM,
689 RTW89_RS_LMT_NUM = RTW89_RS_MCS + 1,
690 RTW89_RS_TX_SHAPE_NUM = RTW89_RS_OFDM + 1,
691 };
692
693 enum rtw89_rate_offset_indexes {
694 RTW89_RATE_OFFSET_HE,
695 RTW89_RATE_OFFSET_VHT,
696 RTW89_RATE_OFFSET_HT,
697 RTW89_RATE_OFFSET_OFDM,
698 RTW89_RATE_OFFSET_CCK,
699 RTW89_RATE_OFFSET_DLRU_EHT,
700 RTW89_RATE_OFFSET_DLRU_HE,
701 RTW89_RATE_OFFSET_EHT,
702 __RTW89_RATE_OFFSET_NUM,
703
704 RTW89_RATE_OFFSET_NUM_AX = RTW89_RATE_OFFSET_CCK + 1,
705 RTW89_RATE_OFFSET_NUM_BE = RTW89_RATE_OFFSET_EHT + 1,
706 };
707
708 enum rtw89_rate_num {
709 RTW89_RATE_CCK_NUM = 4,
710 RTW89_RATE_OFDM_NUM = 8,
711 RTW89_RATE_HEDCM_NUM = 4, /* for HEDCM MCS0/1/3/4 */
712
713 RTW89_RATE_MCS_NUM_AX = 12,
714 RTW89_RATE_MCS_NUM_BE = 16,
715 __RTW89_RATE_MCS_NUM = 16,
716 };
717
718 enum rtw89_nss {
719 RTW89_NSS_1 = 0,
720 RTW89_NSS_2 = 1,
721 /* HE DCM only support 1ss and 2ss */
722 RTW89_NSS_HEDCM_NUM = RTW89_NSS_2 + 1,
723 RTW89_NSS_3 = 2,
724 RTW89_NSS_4 = 3,
725 RTW89_NSS_NUM,
726 };
727
728 enum rtw89_ntx {
729 RTW89_1TX = 0,
730 RTW89_2TX = 1,
731 RTW89_NTX_NUM,
732 };
733
734 enum rtw89_beamforming_type {
735 RTW89_NONBF = 0,
736 RTW89_BF = 1,
737 RTW89_BF_NUM,
738 };
739
740 enum rtw89_ofdma_type {
741 RTW89_NON_OFDMA = 0,
742 RTW89_OFDMA = 1,
743 RTW89_OFDMA_NUM,
744 };
745
746 /* neither insert new in the middle, nor change any given definition */
747 enum rtw89_regulation_type {
748 RTW89_WW = 0,
749 RTW89_ETSI = 1,
750 RTW89_FCC = 2,
751 RTW89_MKK = 3,
752 RTW89_NA = 4,
753 RTW89_IC = 5,
754 RTW89_KCC = 6,
755 RTW89_ACMA = 7,
756 RTW89_NCC = 8,
757 RTW89_MEXICO = 9,
758 RTW89_CHILE = 10,
759 RTW89_UKRAINE = 11,
760 RTW89_CN = 12,
761 RTW89_QATAR = 13,
762 RTW89_UK = 14,
763 RTW89_THAILAND = 15,
764 RTW89_REGD_NUM,
765 };
766
767 enum rtw89_reg_6ghz_power {
768 RTW89_REG_6GHZ_POWER_VLP = 0,
769 RTW89_REG_6GHZ_POWER_LPI = 1,
770 RTW89_REG_6GHZ_POWER_STD = 2,
771
772 NUM_OF_RTW89_REG_6GHZ_POWER,
773 RTW89_REG_6GHZ_POWER_DFLT = RTW89_REG_6GHZ_POWER_VLP,
774 };
775
776 #define RTW89_MIN_VALID_POWER_CONSTRAINT (-10) /* unit: dBm */
777
778 /* calculate based on ieee80211 Transmit Power Envelope */
779 struct rtw89_reg_6ghz_tpe {
780 bool valid;
781 s8 constraint; /* unit: dBm */
782 };
783
784 enum rtw89_fw_pkt_ofld_type {
785 RTW89_PKT_OFLD_TYPE_PROBE_RSP = 0,
786 RTW89_PKT_OFLD_TYPE_PS_POLL = 1,
787 RTW89_PKT_OFLD_TYPE_NULL_DATA = 2,
788 RTW89_PKT_OFLD_TYPE_QOS_NULL = 3,
789 RTW89_PKT_OFLD_TYPE_CTS2SELF = 4,
790 RTW89_PKT_OFLD_TYPE_ARP_RSP = 5,
791 RTW89_PKT_OFLD_TYPE_NDP = 6,
792 RTW89_PKT_OFLD_TYPE_EAPOL_KEY = 7,
793 RTW89_PKT_OFLD_TYPE_SA_QUERY = 8,
794 RTW89_PKT_OFLD_TYPE_PROBE_REQ = 12,
795 RTW89_PKT_OFLD_TYPE_NUM,
796 };
797
798 struct rtw89_txpwr_byrate {
799 s8 cck[RTW89_RATE_CCK_NUM];
800 s8 ofdm[RTW89_RATE_OFDM_NUM];
801 s8 mcs[RTW89_OFDMA_NUM][RTW89_NSS_NUM][__RTW89_RATE_MCS_NUM];
802 s8 hedcm[RTW89_OFDMA_NUM][RTW89_NSS_HEDCM_NUM][RTW89_RATE_HEDCM_NUM];
803 s8 offset[__RTW89_RATE_OFFSET_NUM];
804 s8 trap;
805 };
806
807 struct rtw89_rate_desc {
808 enum rtw89_nss nss;
809 enum rtw89_rate_section rs;
810 enum rtw89_ofdma_type ofdma;
811 u8 idx;
812 };
813
814 #define PHY_STS_HDR_LEN 8
815 #define RF_PATH_MAX 4
816 #define RTW89_MAX_PPDU_CNT 8
817 struct rtw89_rx_phy_ppdu {
818 void *buf;
819 u32 len;
820 u8 rssi_avg;
821 u8 rssi[RF_PATH_MAX];
822 u8 mac_id;
823 u8 chan_idx;
824 u8 phy_idx;
825 u8 ie;
826 u16 rate;
827 u8 rpl_avg;
828 u8 rpl_path[RF_PATH_MAX];
829 u8 rpl_fd[RF_PATH_MAX];
830 u8 bw_idx;
831 u8 rx_path_en;
832 struct {
833 bool has;
834 u8 avg_snr;
835 u8 evm_max;
836 u8 evm_min;
837 } ofdm;
838 bool has_data;
839 bool has_bcn;
840 bool ldpc;
841 bool stbc;
842 bool to_self;
843 bool valid;
844 bool hdr_2_en;
845 };
846
847 enum rtw89_mac_idx {
848 RTW89_MAC_0 = 0,
849 RTW89_MAC_1 = 1,
850 RTW89_MAC_NUM,
851 };
852
853 enum rtw89_phy_idx {
854 RTW89_PHY_0 = 0,
855 RTW89_PHY_1 = 1,
856 RTW89_PHY_NUM,
857 };
858
859 #define __RTW89_MLD_MAX_LINK_NUM 2
860 #define RTW89_MLD_NON_STA_LINK_NUM 1
861
862 enum rtw89_chanctx_idx {
863 RTW89_CHANCTX_0 = 0,
864 RTW89_CHANCTX_1 = 1,
865
866 NUM_OF_RTW89_CHANCTX,
867 RTW89_CHANCTX_IDLE = NUM_OF_RTW89_CHANCTX,
868 };
869
870 enum rtw89_rf_path {
871 RF_PATH_A = 0,
872 RF_PATH_B = 1,
873 RF_PATH_C = 2,
874 RF_PATH_D = 3,
875 RF_PATH_AB,
876 RF_PATH_AC,
877 RF_PATH_AD,
878 RF_PATH_BC,
879 RF_PATH_BD,
880 RF_PATH_CD,
881 RF_PATH_ABC,
882 RF_PATH_ABD,
883 RF_PATH_ACD,
884 RF_PATH_BCD,
885 RF_PATH_ABCD,
886 };
887
888 enum rtw89_rf_path_bit {
889 RF_A = BIT(0),
890 RF_B = BIT(1),
891 RF_C = BIT(2),
892 RF_D = BIT(3),
893
894 RF_AB = (RF_A | RF_B),
895 RF_AC = (RF_A | RF_C),
896 RF_AD = (RF_A | RF_D),
897 RF_BC = (RF_B | RF_C),
898 RF_BD = (RF_B | RF_D),
899 RF_CD = (RF_C | RF_D),
900
901 RF_ABC = (RF_A | RF_B | RF_C),
902 RF_ABD = (RF_A | RF_B | RF_D),
903 RF_ACD = (RF_A | RF_C | RF_D),
904 RF_BCD = (RF_B | RF_C | RF_D),
905
906 RF_ABCD = (RF_A | RF_B | RF_C | RF_D),
907 };
908
909 enum rtw89_bandwidth {
910 RTW89_CHANNEL_WIDTH_20 = 0,
911 RTW89_CHANNEL_WIDTH_40 = 1,
912 RTW89_CHANNEL_WIDTH_80 = 2,
913 RTW89_CHANNEL_WIDTH_160 = 3,
914 RTW89_CHANNEL_WIDTH_320 = 4,
915
916 /* keep index order above */
917 RTW89_CHANNEL_WIDTH_ORDINARY_NUM = 5,
918
919 RTW89_CHANNEL_WIDTH_80_80 = 5,
920 RTW89_CHANNEL_WIDTH_5 = 6,
921 RTW89_CHANNEL_WIDTH_10 = 7,
922 };
923
924 enum rtw89_ps_mode {
925 RTW89_PS_MODE_NONE = 0,
926 RTW89_PS_MODE_RFOFF = 1,
927 RTW89_PS_MODE_CLK_GATED = 2,
928 RTW89_PS_MODE_PWR_GATED = 3,
929 };
930
931 #define RTW89_2G_BW_NUM (RTW89_CHANNEL_WIDTH_40 + 1)
932 #define RTW89_5G_BW_NUM (RTW89_CHANNEL_WIDTH_160 + 1)
933 #define RTW89_6G_BW_NUM (RTW89_CHANNEL_WIDTH_320 + 1)
934 #define RTW89_BYR_BW_NUM (RTW89_CHANNEL_WIDTH_320 + 1)
935 #define RTW89_PPE_BW_NUM (RTW89_CHANNEL_WIDTH_320 + 1)
936
937 enum rtw89_pe_duration {
938 RTW89_PE_DURATION_0 = 0,
939 RTW89_PE_DURATION_8 = 1,
940 RTW89_PE_DURATION_16 = 2,
941 RTW89_PE_DURATION_16_20 = 3,
942 };
943
944 enum rtw89_ru_bandwidth {
945 RTW89_RU26 = 0,
946 RTW89_RU52 = 1,
947 RTW89_RU106 = 2,
948 RTW89_RU52_26 = 3,
949 RTW89_RU106_26 = 4,
950 RTW89_RU_NUM,
951 };
952
953 enum rtw89_sc_offset {
954 RTW89_SC_DONT_CARE = 0,
955 RTW89_SC_20_UPPER = 1,
956 RTW89_SC_20_LOWER = 2,
957 RTW89_SC_20_UPMOST = 3,
958 RTW89_SC_20_LOWEST = 4,
959 RTW89_SC_20_UP2X = 5,
960 RTW89_SC_20_LOW2X = 6,
961 RTW89_SC_20_UP3X = 7,
962 RTW89_SC_20_LOW3X = 8,
963 RTW89_SC_40_UPPER = 9,
964 RTW89_SC_40_LOWER = 10,
965 };
966
967 /* only mgd features can be added to the enum */
968 enum rtw89_wow_flags {
969 RTW89_WOW_FLAG_EN_MAGIC_PKT,
970 RTW89_WOW_FLAG_EN_REKEY_PKT,
971 RTW89_WOW_FLAG_EN_DISCONNECT,
972 RTW89_WOW_FLAG_EN_PATTERN,
973 RTW89_WOW_FLAG_NUM,
974 };
975
976 struct rtw89_chan {
977 u8 channel;
978 u8 primary_channel;
979 enum rtw89_band band_type;
980 enum rtw89_bandwidth band_width;
981
982 /* The follow-up are derived from the above. We must ensure that it
983 * is assigned correctly in rtw89_chan_create() if new one is added.
984 */
985 u32 freq;
986 enum rtw89_subband subband_type;
987 enum rtw89_sc_offset pri_ch_idx;
988 u8 pri_sb_idx;
989 };
990
991 struct rtw89_chan_rcd {
992 u8 prev_primary_channel;
993 enum rtw89_band prev_band_type;
994 bool band_changed;
995 };
996
997 struct rtw89_channel_help_params {
998 u32 tx_en;
999 };
1000
1001 struct rtw89_port_reg {
1002 u32 port_cfg;
1003 u32 tbtt_prohib;
1004 u32 bcn_area;
1005 u32 bcn_early;
1006 u32 tbtt_early;
1007 u32 tbtt_agg;
1008 u32 bcn_space;
1009 u32 bcn_forcetx;
1010 u32 bcn_err_cnt;
1011 u32 bcn_err_flag;
1012 u32 dtim_ctrl;
1013 u32 tbtt_shift;
1014 u32 bcn_cnt_tmr;
1015 u32 tsftr_l;
1016 u32 tsftr_h;
1017 u32 md_tsft;
1018 u32 bss_color;
1019 u32 mbssid;
1020 u32 mbssid_drop;
1021 u32 tsf_sync;
1022 u32 ptcl_dbg;
1023 u32 ptcl_dbg_info;
1024 u32 bcn_drop_all;
1025 u32 bcn_psr_rpt;
1026 u32 hiq_win[RTW89_PORT_NUM];
1027 };
1028
1029 struct rtw89_txwd_body {
1030 __le32 dword0;
1031 __le32 dword1;
1032 __le32 dword2;
1033 __le32 dword3;
1034 __le32 dword4;
1035 __le32 dword5;
1036 } __packed;
1037
1038 struct rtw89_txwd_body_v1 {
1039 __le32 dword0;
1040 __le32 dword1;
1041 __le32 dword2;
1042 __le32 dword3;
1043 __le32 dword4;
1044 __le32 dword5;
1045 __le32 dword6;
1046 __le32 dword7;
1047 } __packed;
1048
1049 struct rtw89_txwd_body_v2 {
1050 __le32 dword0;
1051 __le32 dword1;
1052 __le32 dword2;
1053 __le32 dword3;
1054 __le32 dword4;
1055 __le32 dword5;
1056 __le32 dword6;
1057 __le32 dword7;
1058 } __packed;
1059
1060 struct rtw89_txwd_info {
1061 __le32 dword0;
1062 __le32 dword1;
1063 __le32 dword2;
1064 __le32 dword3;
1065 __le32 dword4;
1066 __le32 dword5;
1067 } __packed;
1068
1069 struct rtw89_txwd_info_v2 {
1070 __le32 dword0;
1071 __le32 dword1;
1072 __le32 dword2;
1073 __le32 dword3;
1074 __le32 dword4;
1075 __le32 dword5;
1076 __le32 dword6;
1077 __le32 dword7;
1078 } __packed;
1079
1080 struct rtw89_rx_desc_info {
1081 u16 pkt_size;
1082 u8 pkt_type;
1083 u8 drv_info_size;
1084 u8 phy_rpt_size;
1085 u8 hdr_cnv_size;
1086 u8 shift;
1087 u8 wl_hd_iv_len;
1088 bool long_rxdesc;
1089 bool bb_sel;
1090 bool mac_info_valid;
1091 u16 data_rate;
1092 u8 gi_ltf;
1093 u8 bw;
1094 u32 free_run_cnt;
1095 u8 user_id;
1096 bool sr_en;
1097 u8 ppdu_cnt;
1098 u8 ppdu_type;
1099 bool icv_err;
1100 bool crc32_err;
1101 bool hw_dec;
1102 bool sw_dec;
1103 bool addr1_match;
1104 u8 frag;
1105 u16 seq;
1106 u8 frame_type;
1107 u8 rx_pl_id;
1108 bool addr_cam_valid;
1109 u8 addr_cam_id;
1110 u8 sec_cam_id;
1111 u8 mac_id;
1112 u16 offset;
1113 u16 rxd_len;
1114 bool ready;
1115 u16 rssi;
1116 };
1117
1118 struct rtw89_rxdesc_short {
1119 __le32 dword0;
1120 __le32 dword1;
1121 __le32 dword2;
1122 __le32 dword3;
1123 } __packed;
1124
1125 struct rtw89_rxdesc_short_v2 {
1126 __le32 dword0;
1127 __le32 dword1;
1128 __le32 dword2;
1129 __le32 dword3;
1130 __le32 dword4;
1131 __le32 dword5;
1132 } __packed;
1133
1134 struct rtw89_rxdesc_long {
1135 __le32 dword0;
1136 __le32 dword1;
1137 __le32 dword2;
1138 __le32 dword3;
1139 __le32 dword4;
1140 __le32 dword5;
1141 __le32 dword6;
1142 __le32 dword7;
1143 } __packed;
1144
1145 struct rtw89_rxdesc_long_v2 {
1146 __le32 dword0;
1147 __le32 dword1;
1148 __le32 dword2;
1149 __le32 dword3;
1150 __le32 dword4;
1151 __le32 dword5;
1152 __le32 dword6;
1153 __le32 dword7;
1154 __le32 dword8;
1155 __le32 dword9;
1156 } __packed;
1157
1158 struct rtw89_rxdesc_phy_rpt_v2 {
1159 __le32 dword0;
1160 __le32 dword1;
1161 } __packed;
1162
1163 struct rtw89_tx_desc_info {
1164 u16 pkt_size;
1165 u8 wp_offset;
1166 u8 mac_id;
1167 u8 qsel;
1168 u8 ch_dma;
1169 u8 hdr_llc_len;
1170 bool is_bmc;
1171 bool en_wd_info;
1172 bool wd_page;
1173 bool use_rate;
1174 bool dis_data_fb;
1175 bool tid_indicate;
1176 bool agg_en;
1177 bool bk;
1178 u8 ampdu_density;
1179 u8 ampdu_num;
1180 bool sec_en;
1181 bool report;
1182 bool tx_cnt_lmt_en;
1183 u8 sn: 4;
1184 u8 tx_cnt_lmt: 6;
1185 u8 addr_info_nr;
1186 u8 sec_keyid;
1187 u8 sec_type;
1188 u8 sec_cam_idx;
1189 u8 sec_seq[6];
1190 u16 data_rate;
1191 u16 data_retry_lowest_rate;
1192 u8 data_bw;
1193 u8 gi_ltf;
1194 bool fw_dl;
1195 u16 seq;
1196 bool a_ctrl_bsr;
1197 u8 hw_ssn_sel;
1198 #define RTW89_MGMT_HW_SSN_SEL 1
1199 u8 hw_seq_mode;
1200 #define RTW89_MGMT_HW_SEQ_MODE 1
1201 bool hiq;
1202 u8 port;
1203 bool er_cap;
1204 bool stbc;
1205 bool ldpc;
1206 bool upd_wlan_hdr;
1207 bool mlo;
1208 bool sw_mld;
1209 };
1210
1211 struct rtw89_core_tx_request {
1212 enum rtw89_core_tx_type tx_type;
1213
1214 struct sk_buff *skb;
1215 struct ieee80211_vif *vif;
1216 struct ieee80211_sta *sta;
1217 struct rtw89_vif_link *rtwvif_link;
1218 struct rtw89_sta_link *rtwsta_link;
1219 struct rtw89_tx_desc_info desc_info;
1220 };
1221
1222 struct rtw89_txq {
1223 struct list_head list;
1224 unsigned long flags;
1225 int wait_cnt;
1226 };
1227
1228 struct rtw89_mac_ax_gnt {
1229 u8 gnt_bt_sw_en;
1230 u8 gnt_bt;
1231 u8 gnt_wl_sw_en;
1232 u8 gnt_wl;
1233 } __packed;
1234
1235 struct rtw89_mac_ax_wl_act {
1236 u8 wlan_act_en;
1237 u8 wlan_act;
1238 } __packed;
1239
1240 #define RTW89_MAC_AX_COEX_GNT_NR 2
1241 struct rtw89_mac_ax_coex_gnt {
1242 struct rtw89_mac_ax_gnt band[RTW89_MAC_AX_COEX_GNT_NR];
1243 struct rtw89_mac_ax_wl_act bt[RTW89_MAC_AX_COEX_GNT_NR];
1244 };
1245
1246 enum rtw89_btc_ncnt {
1247 BTC_NCNT_POWER_ON = 0x0,
1248 BTC_NCNT_POWER_OFF,
1249 BTC_NCNT_INIT_COEX,
1250 BTC_NCNT_SCAN_START,
1251 BTC_NCNT_SCAN_FINISH,
1252 BTC_NCNT_SPECIAL_PACKET,
1253 BTC_NCNT_SWITCH_BAND,
1254 BTC_NCNT_RFK_TIMEOUT,
1255 BTC_NCNT_SHOW_COEX_INFO,
1256 BTC_NCNT_ROLE_INFO,
1257 BTC_NCNT_CONTROL,
1258 BTC_NCNT_RADIO_STATE,
1259 BTC_NCNT_CUSTOMERIZE,
1260 BTC_NCNT_WL_RFK,
1261 BTC_NCNT_WL_STA,
1262 BTC_NCNT_WL_STA_LAST,
1263 BTC_NCNT_FWINFO,
1264 BTC_NCNT_TIMER,
1265 BTC_NCNT_SWITCH_CHBW,
1266 BTC_NCNT_RESUME_DL_FW,
1267 BTC_NCNT_COUNTRYCODE,
1268 BTC_NCNT_NUM,
1269 };
1270
1271 enum rtw89_btc_btinfo {
1272 BTC_BTINFO_L0 = 0,
1273 BTC_BTINFO_L1,
1274 BTC_BTINFO_L2,
1275 BTC_BTINFO_L3,
1276 BTC_BTINFO_H0,
1277 BTC_BTINFO_H1,
1278 BTC_BTINFO_H2,
1279 BTC_BTINFO_H3,
1280 BTC_BTINFO_MAX
1281 };
1282
1283 enum rtw89_btc_dcnt {
1284 BTC_DCNT_RUN = 0x0,
1285 BTC_DCNT_CX_RUNINFO,
1286 BTC_DCNT_RPT,
1287 BTC_DCNT_RPT_HANG,
1288 BTC_DCNT_CYCLE,
1289 BTC_DCNT_CYCLE_HANG,
1290 BTC_DCNT_W1,
1291 BTC_DCNT_W1_HANG,
1292 BTC_DCNT_B1,
1293 BTC_DCNT_B1_HANG,
1294 BTC_DCNT_TDMA_NONSYNC,
1295 BTC_DCNT_SLOT_NONSYNC,
1296 BTC_DCNT_BTCNT_HANG,
1297 BTC_DCNT_BTTX_HANG,
1298 BTC_DCNT_WL_SLOT_DRIFT,
1299 BTC_DCNT_WL_STA_LAST,
1300 BTC_DCNT_BT_SLOT_DRIFT,
1301 BTC_DCNT_BT_SLOT_FLOOD,
1302 BTC_DCNT_FDDT_TRIG,
1303 BTC_DCNT_E2G,
1304 BTC_DCNT_E2G_HANG,
1305 BTC_DCNT_WL_FW_VER_MATCH,
1306 BTC_DCNT_NULL_TX_FAIL,
1307 BTC_DCNT_WL_STA_NTFY,
1308 BTC_DCNT_NUM,
1309 };
1310
1311 enum rtw89_btc_wl_state_cnt {
1312 BTC_WCNT_SCANAP = 0x0,
1313 BTC_WCNT_DHCP,
1314 BTC_WCNT_EAPOL,
1315 BTC_WCNT_ARP,
1316 BTC_WCNT_SCBDUPDATE,
1317 BTC_WCNT_RFK_REQ,
1318 BTC_WCNT_RFK_GO,
1319 BTC_WCNT_RFK_REJECT,
1320 BTC_WCNT_RFK_TIMEOUT,
1321 BTC_WCNT_CH_UPDATE,
1322 BTC_WCNT_DBCC_ALL_2G,
1323 BTC_WCNT_DBCC_CHG,
1324 BTC_WCNT_RX_OK_LAST,
1325 BTC_WCNT_RX_OK_LAST2S,
1326 BTC_WCNT_RX_ERR_LAST,
1327 BTC_WCNT_RX_ERR_LAST2S,
1328 BTC_WCNT_RX_LAST,
1329 BTC_WCNT_NUM
1330 };
1331
1332 enum rtw89_btc_bt_state_cnt {
1333 BTC_BCNT_RETRY = 0x0,
1334 BTC_BCNT_REINIT,
1335 BTC_BCNT_REENABLE,
1336 BTC_BCNT_SCBDREAD,
1337 BTC_BCNT_RELINK,
1338 BTC_BCNT_IGNOWL,
1339 BTC_BCNT_INQPAG,
1340 BTC_BCNT_INQ,
1341 BTC_BCNT_PAGE,
1342 BTC_BCNT_ROLESW,
1343 BTC_BCNT_AFH,
1344 BTC_BCNT_INFOUPDATE,
1345 BTC_BCNT_INFOSAME,
1346 BTC_BCNT_SCBDUPDATE,
1347 BTC_BCNT_HIPRI_TX,
1348 BTC_BCNT_HIPRI_RX,
1349 BTC_BCNT_LOPRI_TX,
1350 BTC_BCNT_LOPRI_RX,
1351 BTC_BCNT_POLUT,
1352 BTC_BCNT_POLUT_NOW,
1353 BTC_BCNT_POLUT_DIFF,
1354 BTC_BCNT_RATECHG,
1355 BTC_BCNT_BTTXPWR_UPDATE,
1356 BTC_BCNT_NUM,
1357 };
1358
1359 enum rtw89_btc_bt_profile {
1360 BTC_BT_NOPROFILE = 0,
1361 BTC_BT_HFP = BIT(0),
1362 BTC_BT_HID = BIT(1),
1363 BTC_BT_A2DP = BIT(2),
1364 BTC_BT_PAN = BIT(3),
1365 BTC_PROFILE_MAX = 4,
1366 };
1367
1368 struct rtw89_btc_ant_info {
1369 u8 type; /* shared, dedicated */
1370 u8 num;
1371 u8 isolation;
1372
1373 u8 single_pos: 1;/* Single antenna at S0 or S1 */
1374 u8 diversity: 1;
1375 u8 btg_pos: 2;
1376 u8 stream_cnt: 4;
1377 };
1378
1379 struct rtw89_btc_ant_info_v7 {
1380 u8 type; /* shared, dedicated(non-shared) */
1381 u8 num; /* antenna count */
1382 u8 isolation;
1383 u8 single_pos;/* wifi 1ss-1ant at 0:S0 or 1:S1 */
1384
1385 u8 diversity; /* only for wifi use 1-antenna */
1386 u8 btg_pos; /* btg-circuit at 0:S0/1:S1/others:all */
1387 u8 stream_cnt; /* spatial_stream count */
1388 u8 rsvd;
1389 } __packed;
1390
1391 enum rtw89_tfc_dir {
1392 RTW89_TFC_UL,
1393 RTW89_TFC_DL,
1394 };
1395
1396 struct rtw89_btc_wl_smap {
1397 u32 busy: 1;
1398 u32 scan: 1;
1399 u32 connecting: 1;
1400 u32 roaming: 1;
1401 u32 dbccing: 1;
1402 u32 _4way: 1;
1403 u32 rf_off: 1;
1404 u32 lps: 2;
1405 u32 ips: 1;
1406 u32 init_ok: 1;
1407 u32 traffic_dir : 2;
1408 u32 rf_off_pre: 1;
1409 u32 lps_pre: 2;
1410 u32 lps_exiting: 1;
1411 u32 emlsr: 1;
1412 };
1413
1414 enum rtw89_tfc_interval {
1415 RTW89_TFC_INTERVAL_100MS,
1416 RTW89_TFC_INTERVAL_2SEC,
1417 };
1418
1419 enum rtw89_tfc_lv {
1420 RTW89_TFC_IDLE,
1421 RTW89_TFC_ULTRA_LOW,
1422 RTW89_TFC_LOW,
1423 RTW89_TFC_MID,
1424 RTW89_TFC_HIGH,
1425 };
1426
1427 DECLARE_EWMA(tp, 10, 2);
1428
1429 struct rtw89_traffic_stats {
1430 /* units in bytes */
1431 u64 tx_unicast;
1432 u64 rx_unicast;
1433 u32 tx_avg_len;
1434 u32 rx_avg_len;
1435
1436 /* count for packets */
1437 u64 tx_cnt;
1438 u64 rx_cnt;
1439
1440 /* units in Mbps */
1441 u32 tx_throughput;
1442 u32 rx_throughput;
1443 u32 tx_throughput_raw;
1444 u32 rx_throughput_raw;
1445
1446 u32 rx_tf_acc;
1447 u32 rx_tf_periodic;
1448
1449 enum rtw89_tfc_lv tx_tfc_lv;
1450 enum rtw89_tfc_lv rx_tfc_lv;
1451 struct ewma_tp tx_ewma_tp;
1452 struct ewma_tp rx_ewma_tp;
1453
1454 u16 tx_rate;
1455 u16 rx_rate;
1456 };
1457
1458 struct rtw89_btc_chdef {
1459 u8 center_ch;
1460 u8 band;
1461 u8 chan;
1462 enum rtw89_sc_offset offset;
1463 enum rtw89_bandwidth bw;
1464 };
1465
1466 struct rtw89_btc_statistic {
1467 u8 rssi; /* 0%~110% (dBm = rssi -110) */
1468 struct rtw89_traffic_stats traffic;
1469 };
1470
1471 #define BTC_WL_RSSI_THMAX 4
1472
1473 struct rtw89_btc_wl_link_info {
1474 struct rtw89_btc_chdef chdef;
1475 struct rtw89_btc_statistic stat;
1476 enum rtw89_tfc_dir dir;
1477 u8 rssi_state[BTC_WL_RSSI_THMAX];
1478 u8 mac_addr[ETH_ALEN];
1479 u8 busy;
1480 u8 ch;
1481 u8 bw;
1482 u8 band;
1483 u8 role;
1484 u8 pid;
1485 u8 phy;
1486 u8 dtim_period;
1487 u8 mode;
1488 u8 tx_1ss_limit;
1489
1490 u8 mac_id;
1491 u8 tx_retry;
1492
1493 u32 bcn_period;
1494 u32 busy_t;
1495 u32 tx_time;
1496 u32 client_cnt;
1497 u32 rx_rate_drop_cnt;
1498 u32 noa_duration;
1499
1500 u32 active: 1;
1501 u32 noa: 1;
1502 u32 client_ps: 1;
1503 u32 connected: 2;
1504 };
1505
1506 union rtw89_btc_wl_state_map {
1507 u32 val;
1508 struct rtw89_btc_wl_smap map;
1509 };
1510
1511 struct rtw89_btc_bt_hfp_desc {
1512 u32 exist: 1;
1513 u32 type: 2;
1514 u32 rsvd: 29;
1515 };
1516
1517 struct rtw89_btc_bt_hid_desc {
1518 u32 exist: 1;
1519 u32 slot_info: 2;
1520 u32 pair_cnt: 2;
1521 u32 type: 8;
1522 u32 rsvd: 19;
1523 };
1524
1525 struct rtw89_btc_bt_a2dp_desc {
1526 u8 exist: 1;
1527 u8 exist_last: 1;
1528 u8 play_latency: 1;
1529 u8 type: 3;
1530 u8 active: 1;
1531 u8 sink: 1;
1532 u32 handle_update: 1;
1533 u32 devinfo_query: 1;
1534 u32 no_empty_streak_2s: 8;
1535 u32 no_empty_streak_max: 8;
1536 u32 rsvd: 6;
1537
1538 u8 bitpool;
1539 u16 vendor_id;
1540 u32 device_name;
1541 u32 flush_time;
1542 };
1543
1544 struct rtw89_btc_bt_pan_desc {
1545 u32 exist: 1;
1546 u32 type: 1;
1547 u32 active: 1;
1548 u32 rsvd: 29;
1549 };
1550
1551 struct rtw89_btc_bt_rfk_info {
1552 u32 run: 1;
1553 u32 req: 1;
1554 u32 timeout: 1;
1555 u32 rsvd: 29;
1556 };
1557
1558 union rtw89_btc_bt_rfk_info_map {
1559 u32 val;
1560 struct rtw89_btc_bt_rfk_info map;
1561 };
1562
1563 struct rtw89_btc_bt_ver_info {
1564 u32 fw_coex; /* match with which coex_ver */
1565 u32 fw;
1566 };
1567
1568 struct rtw89_btc_bool_sta_chg {
1569 u32 now: 1;
1570 u32 last: 1;
1571 u32 remain: 1;
1572 u32 srvd: 29;
1573 };
1574
1575 struct rtw89_btc_u8_sta_chg {
1576 u8 now;
1577 u8 last;
1578 u8 remain;
1579 u8 rsvd;
1580 };
1581
1582 struct rtw89_btc_wl_scan_info {
1583 u8 band[RTW89_PHY_NUM];
1584 u8 phy_map;
1585 u8 rsvd;
1586 };
1587
1588 struct rtw89_btc_wl_dbcc_info {
1589 u8 op_band[RTW89_PHY_NUM]; /* op band in each phy */
1590 u8 scan_band[RTW89_PHY_NUM]; /* scan band in each phy */
1591 u8 real_band[RTW89_PHY_NUM];
1592 u8 role[RTW89_PHY_NUM]; /* role in each phy */
1593 };
1594
1595 struct rtw89_btc_wl_mlo_info {
1596 u8 wmode[RTW89_PHY_NUM]; /* enum phl_mr_wmode */
1597 u8 ch_type[RTW89_PHY_NUM]; /* enum phl_mr_ch_type */
1598 u8 hwb_rf_band[RTW89_PHY_NUM]; /* enum band_type, RF-band for HW-band */
1599 u8 path_rf_band[RTW89_PHY_NUM]; /* enum band_type, RF-band for PHY0/1 */
1600
1601 u8 wtype; /* enum phl_mr_wtype */
1602 u8 mrcx_mode;
1603 u8 mrcx_act_hwb_map;
1604 u8 mrcx_bt_slot_rsp;
1605
1606 u8 rf_combination; /* enum btc_mlo_rf_combin 0:2+0, 1:0+2, 2:1+1,3:2+2 */
1607 u8 mlo_en; /* MLO enable */
1608 u8 mlo_adie; /* a-die count */
1609 u8 dual_hw_band_en; /* both 2 HW-band link exist */
1610
1611 u32 link_status; /* enum mlo_dbcc_mode_type */
1612 };
1613
1614 struct rtw89_btc_wl_active_role {
1615 u8 connected: 1;
1616 u8 pid: 3;
1617 u8 phy: 1;
1618 u8 noa: 1;
1619 u8 band: 2;
1620
1621 u8 client_ps: 1;
1622 u8 bw: 7;
1623
1624 u8 role;
1625 u8 ch;
1626
1627 u16 tx_lvl;
1628 u16 rx_lvl;
1629 u16 tx_rate;
1630 u16 rx_rate;
1631 };
1632
1633 struct rtw89_btc_wl_active_role_v1 {
1634 u8 connected: 1;
1635 u8 pid: 3;
1636 u8 phy: 1;
1637 u8 noa: 1;
1638 u8 band: 2;
1639
1640 u8 client_ps: 1;
1641 u8 bw: 7;
1642
1643 u8 role;
1644 u8 ch;
1645
1646 u16 tx_lvl;
1647 u16 rx_lvl;
1648 u16 tx_rate;
1649 u16 rx_rate;
1650
1651 u32 noa_duration; /* ms */
1652 };
1653
1654 struct rtw89_btc_wl_active_role_v2 {
1655 u8 connected: 1;
1656 u8 pid: 3;
1657 u8 phy: 1;
1658 u8 noa: 1;
1659 u8 band: 2;
1660
1661 u8 client_ps: 1;
1662 u8 bw: 7;
1663
1664 u8 role;
1665 u8 ch;
1666
1667 u32 noa_duration; /* ms */
1668 };
1669
1670 struct rtw89_btc_wl_active_role_v7 {
1671 u8 connected;
1672 u8 pid;
1673 u8 phy;
1674 u8 noa;
1675
1676 u8 band;
1677 u8 client_ps;
1678 u8 bw;
1679 u8 role;
1680
1681 u8 ch;
1682 u8 noa_dur;
1683 u8 client_cnt;
1684 u8 rsvd2;
1685 } __packed;
1686
1687 struct rtw89_btc_wl_role_info_bpos {
1688 u16 none: 1;
1689 u16 station: 1;
1690 u16 ap: 1;
1691 u16 vap: 1;
1692 u16 adhoc: 1;
1693 u16 adhoc_master: 1;
1694 u16 mesh: 1;
1695 u16 moniter: 1;
1696 u16 p2p_device: 1;
1697 u16 p2p_gc: 1;
1698 u16 p2p_go: 1;
1699 u16 nan: 1;
1700 };
1701
1702 struct rtw89_btc_wl_scc_ctrl {
1703 u8 null_role1;
1704 u8 null_role2;
1705 u8 ebt_null; /* if tx null at EBT slot */
1706 };
1707
1708 union rtw89_btc_wl_role_info_map {
1709 u16 val;
1710 struct rtw89_btc_wl_role_info_bpos role;
1711 };
1712
1713 struct rtw89_btc_wl_role_info { /* struct size must be n*4 bytes */
1714 u8 connect_cnt;
1715 u8 link_mode;
1716 union rtw89_btc_wl_role_info_map role_map;
1717 struct rtw89_btc_wl_active_role active_role[RTW89_PORT_NUM];
1718 };
1719
1720 struct rtw89_btc_wl_role_info_v1 { /* struct size must be n*4 bytes */
1721 u8 connect_cnt;
1722 u8 link_mode;
1723 union rtw89_btc_wl_role_info_map role_map;
1724 struct rtw89_btc_wl_active_role_v1 active_role_v1[RTW89_PORT_NUM];
1725 u32 mrole_type; /* btc_wl_mrole_type */
1726 u32 mrole_noa_duration; /* ms */
1727
1728 u32 dbcc_en: 1;
1729 u32 dbcc_chg: 1;
1730 u32 dbcc_2g_phy: 2; /* which phy operate in 2G, HW_PHY_0 or HW_PHY_1 */
1731 u32 link_mode_chg: 1;
1732 u32 rsvd: 27;
1733 };
1734
1735 struct rtw89_btc_wl_role_info_v2 { /* struct size must be n*4 bytes */
1736 u8 connect_cnt;
1737 u8 link_mode;
1738 union rtw89_btc_wl_role_info_map role_map;
1739 struct rtw89_btc_wl_active_role_v2 active_role_v2[RTW89_PORT_NUM];
1740 u32 mrole_type; /* btc_wl_mrole_type */
1741 u32 mrole_noa_duration; /* ms */
1742
1743 u32 dbcc_en: 1;
1744 u32 dbcc_chg: 1;
1745 u32 dbcc_2g_phy: 2; /* which phy operate in 2G, HW_PHY_0 or HW_PHY_1 */
1746 u32 link_mode_chg: 1;
1747 u32 rsvd: 27;
1748 };
1749
1750 struct rtw89_btc_wl_rlink { /* H2C info, struct size must be n*4 bytes */
1751 u8 connected;
1752 u8 pid;
1753 u8 phy;
1754 u8 noa;
1755
1756 u8 rf_band; /* enum band_type RF band: 2.4G/5G/6G */
1757 u8 active; /* 0:rlink is under doze */
1758 u8 bw; /* enum channel_width */
1759 u8 role; /*enum role_type */
1760
1761 u8 ch;
1762 u8 noa_dur; /* ms */
1763 u8 client_cnt; /* for Role = P2P-Go/AP */
1764 u8 mode; /* wifi protocol */
1765 } __packed;
1766
1767 #define RTW89_BE_BTC_WL_MAX_ROLE_NUMBER 6
1768 struct rtw89_btc_wl_role_info_v7 { /* struct size must be n*4 bytes */
1769 u8 connect_cnt;
1770 u8 link_mode;
1771 u8 link_mode_chg;
1772 u8 p2p_2g;
1773
1774 struct rtw89_btc_wl_active_role_v7 active_role[RTW89_BE_BTC_WL_MAX_ROLE_NUMBER];
1775
1776 u32 role_map;
1777 u32 mrole_type; /* btc_wl_mrole_type */
1778 u32 mrole_noa_duration; /* ms */
1779 u32 dbcc_en;
1780 u32 dbcc_chg;
1781 u32 dbcc_2g_phy; /* which phy operate in 2G, HW_PHY_0 or HW_PHY_1 */
1782 } __packed;
1783
1784 struct rtw89_btc_wl_role_info_v8 { /* H2C info, struct size must be n*4 bytes */
1785 u8 connect_cnt;
1786 u8 link_mode;
1787 u8 link_mode_chg;
1788 u8 p2p_2g;
1789
1790 u8 pta_req_band;
1791 u8 dbcc_en; /* 1+1 and 2.4G-included */
1792 u8 dbcc_chg;
1793 u8 dbcc_2g_phy; /* which phy operate in 2G, HW_PHY_0 or HW_PHY_1 */
1794
1795 struct rtw89_btc_wl_rlink rlink[RTW89_BE_BTC_WL_MAX_ROLE_NUMBER][RTW89_MAC_NUM];
1796
1797 u32 role_map;
1798 u32 mrole_type; /* btc_wl_mrole_type */
1799 u32 mrole_noa_duration; /* ms */
1800 } __packed;
1801
1802 struct rtw89_btc_wl_ver_info {
1803 u32 fw_coex; /* match with which coex_ver */
1804 u32 fw;
1805 u32 mac;
1806 u32 bb;
1807 u32 rf;
1808 };
1809
1810 struct rtw89_btc_wl_afh_info {
1811 u8 en;
1812 u8 ch;
1813 u8 bw;
1814 u8 rsvd;
1815 } __packed;
1816
1817 struct rtw89_btc_wl_rfk_info {
1818 u32 state: 2;
1819 u32 path_map: 4;
1820 u32 phy_map: 2;
1821 u32 band: 2;
1822 u32 type: 8;
1823 u32 con_rfk: 1;
1824 u32 rsvd: 13;
1825
1826 u32 start_time;
1827 u32 proc_time;
1828 };
1829
1830 struct rtw89_btc_bt_smap {
1831 u32 connect: 1;
1832 u32 ble_connect: 1;
1833 u32 acl_busy: 1;
1834 u32 sco_busy: 1;
1835 u32 mesh_busy: 1;
1836 u32 inq_pag: 1;
1837 };
1838
1839 union rtw89_btc_bt_state_map {
1840 u32 val;
1841 struct rtw89_btc_bt_smap map;
1842 };
1843
1844 #define BTC_BT_RSSI_THMAX 4
1845 #define BTC_BT_AFH_GROUP 12
1846 #define BTC_BT_AFH_LE_GROUP 5
1847
1848 struct rtw89_btc_bt_txpwr_desc {
1849 s8 br_dbm;
1850 s8 le_dbm;
1851 u8 br_gain_index;
1852 u8 le_gain_index;
1853 };
1854
1855 struct rtw89_btc_bt_link_info {
1856 struct rtw89_btc_u8_sta_chg profile_cnt;
1857 struct rtw89_btc_bool_sta_chg multi_link;
1858 struct rtw89_btc_bool_sta_chg relink;
1859 struct rtw89_btc_bt_hfp_desc hfp_desc;
1860 struct rtw89_btc_bt_hid_desc hid_desc;
1861 struct rtw89_btc_bt_a2dp_desc a2dp_desc;
1862 struct rtw89_btc_bt_pan_desc pan_desc;
1863 union rtw89_btc_bt_state_map status;
1864 struct rtw89_btc_bt_txpwr_desc bt_txpwr_desc;
1865
1866 u8 sut_pwr_level[BTC_PROFILE_MAX];
1867 u8 golden_rx_shift[BTC_PROFILE_MAX];
1868 u8 rssi_state[BTC_BT_RSSI_THMAX];
1869 u8 afh_map[BTC_BT_AFH_GROUP];
1870 u8 afh_map_le[BTC_BT_AFH_LE_GROUP];
1871
1872 u32 role_sw: 1;
1873 u32 slave_role: 1;
1874 u32 afh_update: 1;
1875 u32 cqddr: 1;
1876 u32 rssi: 8;
1877 u32 tx_3m: 1;
1878 u32 rsvd: 19;
1879 };
1880
1881 struct rtw89_btc_3rdcx_info {
1882 u8 type; /* 0: none, 1:zigbee, 2:LTE */
1883 u8 hw_coex;
1884 u16 rsvd;
1885 };
1886
1887 struct rtw89_btc_dm_emap {
1888 u32 init: 1;
1889 u32 pta_owner: 1;
1890 u32 wl_rfk_timeout: 1;
1891 u32 bt_rfk_timeout: 1;
1892 u32 wl_fw_hang: 1;
1893 u32 cycle_hang: 1;
1894 u32 w1_hang: 1;
1895 u32 b1_hang: 1;
1896 u32 tdma_no_sync: 1;
1897 u32 slot_no_sync: 1;
1898 u32 wl_slot_drift: 1;
1899 u32 bt_slot_drift: 1;
1900 u32 role_num_mismatch: 1;
1901 u32 null1_tx_late: 1;
1902 u32 bt_afh_conflict: 1;
1903 u32 bt_leafh_conflict: 1;
1904 u32 bt_slot_flood: 1;
1905 u32 wl_e2g_hang: 1;
1906 u32 wl_ver_mismatch: 1;
1907 u32 bt_ver_mismatch: 1;
1908 u32 rfe_type0: 1;
1909 u32 h2c_buffer_over: 1;
1910 u32 bt_tx_hang: 1; /* for SNR too low bug, BT has no Tx req*/
1911 u32 wl_no_sta_ntfy: 1;
1912
1913 u32 h2c_bmap_mismatch: 1;
1914 u32 c2h_bmap_mismatch: 1;
1915 u32 h2c_struct_invalid: 1;
1916 u32 c2h_struct_invalid: 1;
1917 u32 h2c_c2h_buffer_mismatch: 1;
1918 };
1919
1920 union rtw89_btc_dm_error_map {
1921 u32 val;
1922 struct rtw89_btc_dm_emap map;
1923 };
1924
1925 struct rtw89_btc_rf_para {
1926 u32 tx_pwr_freerun;
1927 u32 rx_gain_freerun;
1928 u32 tx_pwr_perpkt;
1929 u32 rx_gain_perpkt;
1930 };
1931
1932 struct rtw89_btc_wl_nhm {
1933 u8 instant_wl_nhm_dbm;
1934 u8 instant_wl_nhm_per_mhz;
1935 u16 valid_record_times;
1936 s8 record_pwr[16];
1937 u8 record_ratio[16];
1938 s8 pwr; /* dbm_per_MHz */
1939 u8 ratio;
1940 u8 current_status;
1941 u8 refresh;
1942 bool start_flag;
1943 s8 pwr_max;
1944 s8 pwr_min;
1945 };
1946
1947 struct rtw89_btc_wl_info {
1948 struct rtw89_btc_wl_link_info link_info[RTW89_PORT_NUM];
1949 struct rtw89_btc_wl_link_info rlink_info[RTW89_BE_BTC_WL_MAX_ROLE_NUMBER][RTW89_MAC_NUM];
1950 struct rtw89_btc_wl_rfk_info rfk_info;
1951 struct rtw89_btc_wl_ver_info ver_info;
1952 struct rtw89_btc_wl_afh_info afh_info;
1953 struct rtw89_btc_wl_role_info role_info;
1954 struct rtw89_btc_wl_role_info_v1 role_info_v1;
1955 struct rtw89_btc_wl_role_info_v2 role_info_v2;
1956 struct rtw89_btc_wl_role_info_v7 role_info_v7;
1957 struct rtw89_btc_wl_role_info_v8 role_info_v8;
1958 struct rtw89_btc_wl_scan_info scan_info;
1959 struct rtw89_btc_wl_dbcc_info dbcc_info;
1960 struct rtw89_btc_wl_mlo_info mlo_info;
1961 struct rtw89_btc_rf_para rf_para;
1962 struct rtw89_btc_wl_nhm nhm;
1963 union rtw89_btc_wl_state_map status;
1964
1965 u8 port_id[RTW89_WIFI_ROLE_MLME_MAX];
1966 u8 rssi_level;
1967 u8 cn_report;
1968 u8 coex_mode;
1969 u8 pta_req_mac;
1970 u8 bt_polut_type[RTW89_PHY_NUM]; /* BT polluted WL-Tx type for phy0/1 */
1971
1972 bool is_5g_hi_channel;
1973 bool go_client_exist;
1974 bool noa_exist;
1975 bool pta_reg_mac_chg;
1976 bool bg_mode;
1977 bool he_mode;
1978 bool scbd_change;
1979 bool fw_ver_mismatch;
1980 bool client_cnt_inc_2g;
1981 bool link_mode_chg;
1982 bool dbcc_chg;
1983 u32 scbd;
1984 };
1985
1986 struct rtw89_btc_module {
1987 struct rtw89_btc_ant_info ant;
1988 u8 rfe_type;
1989 u8 cv;
1990
1991 u8 bt_solo: 1;
1992 u8 bt_pos: 1;
1993 u8 switch_type: 1;
1994 u8 wa_type: 3;
1995
1996 u8 kt_ver_adie;
1997 };
1998
1999 struct rtw89_btc_module_v7 {
2000 u8 rfe_type;
2001 u8 kt_ver;
2002 u8 bt_solo;
2003 u8 bt_pos; /* wl-end view: get from efuse, must compare bt.btg_type*/
2004
2005 u8 switch_type; /* WL/BT switch type: 0: internal, 1: external */
2006 u8 wa_type; /* WA type: 0:none, 1: 51B 5G_Hi-Ch_Rx */
2007 u8 kt_ver_adie;
2008 u8 rsvd;
2009
2010 struct rtw89_btc_ant_info_v7 ant;
2011 } __packed;
2012
2013 union rtw89_btc_module_info {
2014 struct rtw89_btc_module md;
2015 struct rtw89_btc_module_v7 md_v7;
2016 };
2017
2018 #define RTW89_BTC_DM_MAXSTEP 30
2019 #define RTW89_BTC_DM_CNT_MAX (RTW89_BTC_DM_MAXSTEP * 8)
2020
2021 struct rtw89_btc_dm_step {
2022 u16 step[RTW89_BTC_DM_MAXSTEP];
2023 u8 step_pos;
2024 bool step_ov;
2025 };
2026
2027 struct rtw89_btc_init_info {
2028 struct rtw89_btc_module module;
2029 u8 wl_guard_ch;
2030
2031 u8 wl_only: 1;
2032 u8 wl_init_ok: 1;
2033 u8 dbcc_en: 1;
2034 u8 cx_other: 1;
2035 u8 bt_only: 1;
2036
2037 u16 rsvd;
2038 };
2039
2040 struct rtw89_btc_init_info_v7 {
2041 u8 wl_guard_ch;
2042 u8 wl_only;
2043 u8 wl_init_ok;
2044 u8 rsvd3;
2045
2046 u8 cx_other;
2047 u8 bt_only;
2048 u8 pta_mode;
2049 u8 pta_direction;
2050
2051 struct rtw89_btc_module_v7 module;
2052 } __packed;
2053
2054 union rtw89_btc_init_info_u {
2055 struct rtw89_btc_init_info init;
2056 struct rtw89_btc_init_info_v7 init_v7;
2057 };
2058
2059 struct rtw89_btc_wl_tx_limit_para {
2060 u16 enable;
2061 u32 tx_time; /* unit: us */
2062 u16 tx_retry;
2063 };
2064
2065 enum rtw89_btc_bt_scan_type {
2066 BTC_SCAN_INQ = 0,
2067 BTC_SCAN_PAGE,
2068 BTC_SCAN_BLE,
2069 BTC_SCAN_INIT,
2070 BTC_SCAN_TV,
2071 BTC_SCAN_ADV,
2072 BTC_SCAN_MAX1,
2073 };
2074
2075 enum rtw89_btc_ble_scan_type {
2076 CXSCAN_BG = 0,
2077 CXSCAN_INIT,
2078 CXSCAN_LE,
2079 CXSCAN_MAX
2080 };
2081
2082 #define RTW89_BTC_BTC_SCAN_V1_FLAG_ENABLE BIT(0)
2083 #define RTW89_BTC_BTC_SCAN_V1_FLAG_INTERLACE BIT(1)
2084
2085 struct rtw89_btc_bt_scan_info_v1 {
2086 __le16 win;
2087 __le16 intvl;
2088 __le32 flags;
2089 } __packed;
2090
2091 struct rtw89_btc_bt_scan_info_v2 {
2092 __le16 win;
2093 __le16 intvl;
2094 } __packed;
2095
2096 struct rtw89_btc_fbtc_btscan_v1 {
2097 u8 fver; /* btc_ver::fcxbtscan */
2098 u8 rsvd;
2099 __le16 rsvd2;
2100 struct rtw89_btc_bt_scan_info_v1 scan[BTC_SCAN_MAX1];
2101 } __packed;
2102
2103 struct rtw89_btc_fbtc_btscan_v2 {
2104 u8 fver; /* btc_ver::fcxbtscan */
2105 u8 type;
2106 __le16 rsvd2;
2107 struct rtw89_btc_bt_scan_info_v2 para[CXSCAN_MAX];
2108 } __packed;
2109
2110 struct rtw89_btc_fbtc_btscan_v7 {
2111 u8 fver; /* btc_ver::fcxbtscan */
2112 u8 type;
2113 u8 rsvd0;
2114 u8 rsvd1;
2115 struct rtw89_btc_bt_scan_info_v2 para[CXSCAN_MAX];
2116 } __packed;
2117
2118 union rtw89_btc_fbtc_btscan {
2119 struct rtw89_btc_fbtc_btscan_v1 v1;
2120 struct rtw89_btc_fbtc_btscan_v2 v2;
2121 struct rtw89_btc_fbtc_btscan_v7 v7;
2122 };
2123
2124 struct rtw89_btc_bt_info {
2125 struct rtw89_btc_bt_link_info link_info;
2126 struct rtw89_btc_bt_scan_info_v1 scan_info_v1[BTC_SCAN_MAX1];
2127 struct rtw89_btc_bt_scan_info_v2 scan_info_v2[CXSCAN_MAX];
2128 struct rtw89_btc_bt_ver_info ver_info;
2129 struct rtw89_btc_bool_sta_chg enable;
2130 struct rtw89_btc_bool_sta_chg inq_pag;
2131 struct rtw89_btc_rf_para rf_para;
2132 union rtw89_btc_bt_rfk_info_map rfk_info;
2133
2134 u8 raw_info[BTC_BTINFO_MAX]; /* raw bt info from mailbox */
2135 u8 txpwr_info[BTC_BTINFO_MAX];
2136 u8 rssi_level;
2137
2138 u32 scbd;
2139 u32 feature;
2140
2141 u32 mbx_avl: 1;
2142 u32 whql_test: 1;
2143 u32 igno_wl: 1;
2144 u32 reinit: 1;
2145 u32 ble_scan_en: 1;
2146 u32 btg_type: 1;
2147 u32 inq: 1;
2148 u32 pag: 1;
2149 u32 run_patch_code: 1;
2150 u32 hi_lna_rx: 1;
2151 u32 scan_rx_low_pri: 1;
2152 u32 scan_info_update: 1;
2153 u32 lna_constrain: 3;
2154 u32 rsvd: 17;
2155 };
2156
2157 struct rtw89_btc_cx {
2158 struct rtw89_btc_wl_info wl;
2159 struct rtw89_btc_bt_info bt;
2160 struct rtw89_btc_3rdcx_info other;
2161 u32 state_map;
2162 u32 cnt_bt[BTC_BCNT_NUM];
2163 u32 cnt_wl[BTC_WCNT_NUM];
2164 };
2165
2166 struct rtw89_btc_fbtc_tdma {
2167 u8 type; /* btc_ver::fcxtdma */
2168 u8 rxflctrl;
2169 u8 txpause;
2170 u8 wtgle_n;
2171 u8 leak_n;
2172 u8 ext_ctrl;
2173 u8 rxflctrl_role;
2174 u8 option_ctrl;
2175 } __packed;
2176
2177 struct rtw89_btc_fbtc_tdma_v3 {
2178 u8 fver; /* btc_ver::fcxtdma */
2179 u8 rsvd;
2180 __le16 rsvd1;
2181 struct rtw89_btc_fbtc_tdma tdma;
2182 } __packed;
2183
2184 union rtw89_btc_fbtc_tdma_le32 {
2185 struct rtw89_btc_fbtc_tdma v1;
2186 struct rtw89_btc_fbtc_tdma_v3 v3;
2187 };
2188
2189 #define CXMREG_MAX 30
2190 #define CXMREG_MAX_V2 20
2191 #define FCXMAX_STEP 255 /*STEP trace record cnt, Max:65535, default:255*/
2192 #define BTC_CYCLE_SLOT_MAX 48 /* must be even number, non-zero */
2193
2194 enum rtw89_btc_bt_sta_counter {
2195 BTC_BCNT_RFK_REQ = 0,
2196 BTC_BCNT_RFK_GO = 1,
2197 BTC_BCNT_RFK_REJECT = 2,
2198 BTC_BCNT_RFK_FAIL = 3,
2199 BTC_BCNT_RFK_TIMEOUT = 4,
2200 BTC_BCNT_HI_TX = 5,
2201 BTC_BCNT_HI_RX = 6,
2202 BTC_BCNT_LO_TX = 7,
2203 BTC_BCNT_LO_RX = 8,
2204 BTC_BCNT_POLLUTED = 9,
2205 BTC_BCNT_STA_MAX
2206 };
2207
2208 enum rtw89_btc_bt_sta_counter_v105 {
2209 BTC_BCNT_RFK_REQ_V105 = 0,
2210 BTC_BCNT_HI_TX_V105 = 1,
2211 BTC_BCNT_HI_RX_V105 = 2,
2212 BTC_BCNT_LO_TX_V105 = 3,
2213 BTC_BCNT_LO_RX_V105 = 4,
2214 BTC_BCNT_POLLUTED_V105 = 5,
2215 BTC_BCNT_STA_MAX_V105
2216 };
2217
2218 struct rtw89_btc_fbtc_rpt_ctrl_v1 {
2219 u16 fver; /* btc_ver::fcxbtcrpt */
2220 u16 rpt_cnt; /* tmr counters */
2221 u32 wl_fw_coex_ver; /* match which driver's coex version */
2222 u32 wl_fw_cx_offload;
2223 u32 wl_fw_ver;
2224 u32 rpt_enable;
2225 u32 rpt_para; /* ms */
2226 u32 mb_send_fail_cnt; /* fw send mailbox fail counter */
2227 u32 mb_send_ok_cnt; /* fw send mailbox ok counter */
2228 u32 mb_recv_cnt; /* fw recv mailbox counter */
2229 u32 mb_a2dp_empty_cnt; /* a2dp empty count */
2230 u32 mb_a2dp_flct_cnt; /* a2dp empty flow control counter */
2231 u32 mb_a2dp_full_cnt; /* a2dp empty full counter */
2232 u32 bt_rfk_cnt[BTC_BCNT_HI_TX];
2233 u32 c2h_cnt; /* fw send c2h counter */
2234 u32 h2c_cnt; /* fw recv h2c counter */
2235 } __packed;
2236
2237 struct rtw89_btc_fbtc_rpt_ctrl_info {
2238 __le32 cnt; /* fw report counter */
2239 __le32 en; /* report map */
2240 __le32 para; /* not used */
2241
2242 __le32 cnt_c2h; /* fw send c2h counter */
2243 __le32 cnt_h2c; /* fw recv h2c counter */
2244 __le32 len_c2h; /* The total length of the last C2H */
2245
2246 __le32 cnt_aoac_rf_on; /* rf-on counter for aoac switch notify */
2247 __le32 cnt_aoac_rf_off; /* rf-off counter for aoac switch notify */
2248 } __packed;
2249
2250 struct rtw89_btc_fbtc_rpt_ctrl_info_v5 {
2251 __le32 cx_ver; /* match which driver's coex version */
2252 __le32 fw_ver;
2253 __le32 en; /* report map */
2254
2255 __le16 cnt; /* fw report counter */
2256 __le16 cnt_c2h; /* fw send c2h counter */
2257 __le16 cnt_h2c; /* fw recv h2c counter */
2258 __le16 len_c2h; /* The total length of the last C2H */
2259
2260 __le16 cnt_aoac_rf_on; /* rf-on counter for aoac switch notify */
2261 __le16 cnt_aoac_rf_off; /* rf-off counter for aoac switch notify */
2262 } __packed;
2263
2264 struct rtw89_btc_fbtc_rpt_ctrl_info_v8 {
2265 __le16 cnt; /* fw report counter */
2266 __le16 cnt_c2h; /* fw send c2h counter */
2267 __le16 cnt_h2c; /* fw recv h2c counter */
2268 __le16 len_c2h; /* The total length of the last C2H */
2269
2270 __le16 cnt_aoac_rf_on; /* rf-on counter for aoac switch notify */
2271 __le16 cnt_aoac_rf_off; /* rf-off counter for aoac switch notify */
2272
2273 __le32 cx_ver; /* match which driver's coex version */
2274 __le32 fw_ver;
2275 __le32 en; /* report map */
2276 } __packed;
2277
2278 struct rtw89_btc_fbtc_rpt_ctrl_wl_fw_info {
2279 __le32 cx_ver; /* match which driver's coex version */
2280 __le32 cx_offload;
2281 __le32 fw_ver;
2282 } __packed;
2283
2284 struct rtw89_btc_fbtc_rpt_ctrl_a2dp_empty {
2285 __le32 cnt_empty; /* a2dp empty count */
2286 __le32 cnt_flowctrl; /* a2dp empty flow control counter */
2287 __le32 cnt_tx;
2288 __le32 cnt_ack;
2289 __le32 cnt_nack;
2290 } __packed;
2291
2292 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox {
2293 __le32 cnt_send_ok; /* fw send mailbox ok counter */
2294 __le32 cnt_send_fail; /* fw send mailbox fail counter */
2295 __le32 cnt_recv; /* fw recv mailbox counter */
2296 struct rtw89_btc_fbtc_rpt_ctrl_a2dp_empty a2dp;
2297 } __packed;
2298
2299 struct rtw89_btc_fbtc_rpt_ctrl_v4 {
2300 u8 fver;
2301 u8 rsvd;
2302 __le16 rsvd1;
2303 struct rtw89_btc_fbtc_rpt_ctrl_info rpt_info;
2304 struct rtw89_btc_fbtc_rpt_ctrl_wl_fw_info wl_fw_info;
2305 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info;
2306 __le32 bt_cnt[BTC_BCNT_STA_MAX];
2307 struct rtw89_mac_ax_gnt gnt_val[RTW89_PHY_NUM];
2308 } __packed;
2309
2310 struct rtw89_btc_fbtc_rpt_ctrl_v5 {
2311 u8 fver;
2312 u8 rsvd;
2313 __le16 rsvd1;
2314
2315 u8 gnt_val[RTW89_PHY_NUM][4];
2316 __le16 bt_cnt[BTC_BCNT_STA_MAX];
2317
2318 struct rtw89_btc_fbtc_rpt_ctrl_info_v5 rpt_info;
2319 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info;
2320 } __packed;
2321
2322 struct rtw89_btc_fbtc_rpt_ctrl_v105 {
2323 u8 fver;
2324 u8 rsvd;
2325 __le16 rsvd1;
2326
2327 u8 gnt_val[RTW89_PHY_NUM][4];
2328 __le16 bt_cnt[BTC_BCNT_STA_MAX_V105];
2329
2330 struct rtw89_btc_fbtc_rpt_ctrl_info_v5 rpt_info;
2331 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info;
2332 } __packed;
2333
2334 struct rtw89_btc_fbtc_rpt_ctrl_v7 {
2335 u8 fver;
2336 u8 rsvd0;
2337 u8 rsvd1;
2338 u8 rsvd2;
2339
2340 u8 gnt_val[RTW89_PHY_NUM][4];
2341 __le16 bt_cnt[BTC_BCNT_STA_MAX_V105];
2342
2343 struct rtw89_btc_fbtc_rpt_ctrl_info_v8 rpt_info;
2344 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info;
2345 } __packed;
2346
2347 struct rtw89_btc_fbtc_rpt_ctrl_v8 {
2348 u8 fver;
2349 u8 rsvd0;
2350 u8 rpt_len_max_l; /* BTC_RPT_MAX bit0~7 */
2351 u8 rpt_len_max_h; /* BTC_RPT_MAX bit8~15 */
2352
2353 u8 gnt_val[RTW89_PHY_NUM][4];
2354 __le16 bt_cnt[BTC_BCNT_STA_MAX_V105];
2355
2356 struct rtw89_btc_fbtc_rpt_ctrl_info_v8 rpt_info;
2357 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info;
2358 } __packed;
2359
2360 union rtw89_btc_fbtc_rpt_ctrl_ver_info {
2361 struct rtw89_btc_fbtc_rpt_ctrl_v1 v1;
2362 struct rtw89_btc_fbtc_rpt_ctrl_v4 v4;
2363 struct rtw89_btc_fbtc_rpt_ctrl_v5 v5;
2364 struct rtw89_btc_fbtc_rpt_ctrl_v105 v105;
2365 struct rtw89_btc_fbtc_rpt_ctrl_v7 v7;
2366 struct rtw89_btc_fbtc_rpt_ctrl_v8 v8;
2367 };
2368
2369 enum rtw89_fbtc_ext_ctrl_type {
2370 CXECTL_OFF = 0x0, /* tdma off */
2371 CXECTL_B2 = 0x1, /* allow B2 (beacon-early) */
2372 CXECTL_EXT = 0x2,
2373 CXECTL_MAX
2374 };
2375
2376 union rtw89_btc_fbtc_rxflct {
2377 u8 val;
2378 u8 type: 3;
2379 u8 tgln_n: 5;
2380 };
2381
2382 enum rtw89_btc_cxst_state {
2383 CXST_OFF = 0x0,
2384 CXST_B2W = 0x1,
2385 CXST_W1 = 0x2,
2386 CXST_W2 = 0x3,
2387 CXST_W2B = 0x4,
2388 CXST_B1 = 0x5,
2389 CXST_B2 = 0x6,
2390 CXST_B3 = 0x7,
2391 CXST_B4 = 0x8,
2392 CXST_LK = 0x9,
2393 CXST_BLK = 0xa,
2394 CXST_E2G = 0xb,
2395 CXST_E5G = 0xc,
2396 CXST_EBT = 0xd,
2397 CXST_ENULL = 0xe,
2398 CXST_WLK = 0xf,
2399 CXST_W1FDD = 0x10,
2400 CXST_B1FDD = 0x11,
2401 CXST_MAX = 0x12,
2402 };
2403
2404 enum rtw89_btc_cxevnt {
2405 CXEVNT_TDMA_ENTRY = 0x0,
2406 CXEVNT_WL_TMR,
2407 CXEVNT_B1_TMR,
2408 CXEVNT_B2_TMR,
2409 CXEVNT_B3_TMR,
2410 CXEVNT_B4_TMR,
2411 CXEVNT_W2B_TMR,
2412 CXEVNT_B2W_TMR,
2413 CXEVNT_BCN_EARLY,
2414 CXEVNT_A2DP_EMPTY,
2415 CXEVNT_LK_END,
2416 CXEVNT_RX_ISR,
2417 CXEVNT_RX_FC0,
2418 CXEVNT_RX_FC1,
2419 CXEVNT_BT_RELINK,
2420 CXEVNT_BT_RETRY,
2421 CXEVNT_E2G,
2422 CXEVNT_E5G,
2423 CXEVNT_EBT,
2424 CXEVNT_ENULL,
2425 CXEVNT_DRV_WLK,
2426 CXEVNT_BCN_OK,
2427 CXEVNT_BT_CHANGE,
2428 CXEVNT_EBT_EXTEND,
2429 CXEVNT_E2G_NULL1,
2430 CXEVNT_B1FDD_TMR,
2431 CXEVNT_MAX
2432 };
2433
2434 enum {
2435 CXBCN_ALL = 0x0,
2436 CXBCN_ALL_OK,
2437 CXBCN_BT_SLOT,
2438 CXBCN_BT_OK,
2439 CXBCN_MAX
2440 };
2441
2442 enum btc_slot_type {
2443 SLOT_MIX = 0x0, /* accept BT Lower-Pri Tx/Rx request 0x778 = 1 */
2444 SLOT_ISO = 0x1, /* no accept BT Lower-Pri Tx/Rx request 0x778 = d*/
2445 CXSTYPE_NUM,
2446 };
2447
2448 enum { /* TIME */
2449 CXT_BT = 0x0,
2450 CXT_WL = 0x1,
2451 CXT_MAX
2452 };
2453
2454 enum { /* TIME-A2DP */
2455 CXT_FLCTRL_OFF = 0x0,
2456 CXT_FLCTRL_ON = 0x1,
2457 CXT_FLCTRL_MAX
2458 };
2459
2460 enum { /* STEP TYPE */
2461 CXSTEP_NONE = 0x0,
2462 CXSTEP_EVNT = 0x1,
2463 CXSTEP_SLOT = 0x2,
2464 CXSTEP_MAX,
2465 };
2466
2467 enum rtw89_btc_afh_map_type { /*AFH MAP TYPE */
2468 RPT_BT_AFH_SEQ_LEGACY = 0x10,
2469 RPT_BT_AFH_SEQ_LE = 0x20
2470 };
2471
2472 #define BTC_DBG_MAX1 32
2473 struct rtw89_btc_fbtc_gpio_dbg_v1 {
2474 u8 fver; /* btc_ver::fcxgpiodbg */
2475 u8 rsvd;
2476 __le16 rsvd2;
2477 __le32 en_map; /* which debug signal (see btc_wl_gpio_debug) is enable */
2478 __le32 pre_state; /* the debug signal is 1 or 0 */
2479 u8 gpio_map[BTC_DBG_MAX1]; /*the debug signals to GPIO-Position */
2480 } __packed;
2481
2482 struct rtw89_btc_fbtc_gpio_dbg_v7 {
2483 u8 fver;
2484 u8 rsvd0;
2485 u8 rsvd1;
2486 u8 rsvd2;
2487
2488 u8 gpio_map[BTC_DBG_MAX1];
2489
2490 __le32 en_map;
2491 __le32 pre_state;
2492 } __packed;
2493
2494 union rtw89_btc_fbtc_gpio_dbg {
2495 struct rtw89_btc_fbtc_gpio_dbg_v1 v1;
2496 struct rtw89_btc_fbtc_gpio_dbg_v7 v7;
2497 };
2498
2499 struct rtw89_btc_fbtc_mreg_val_v1 {
2500 u8 fver; /* btc_ver::fcxmreg */
2501 u8 reg_num;
2502 __le16 rsvd;
2503 __le32 mreg_val[CXMREG_MAX];
2504 } __packed;
2505
2506 struct rtw89_btc_fbtc_mreg_val_v2 {
2507 u8 fver; /* btc_ver::fcxmreg */
2508 u8 reg_num;
2509 __le16 rsvd;
2510 __le32 mreg_val[CXMREG_MAX_V2];
2511 } __packed;
2512
2513 struct rtw89_btc_fbtc_mreg_val_v7 {
2514 u8 fver;
2515 u8 reg_num;
2516 u8 rsvd0;
2517 u8 rsvd1;
2518 __le32 mreg_val[CXMREG_MAX_V2];
2519 } __packed;
2520
2521 union rtw89_btc_fbtc_mreg_val {
2522 struct rtw89_btc_fbtc_mreg_val_v1 v1;
2523 struct rtw89_btc_fbtc_mreg_val_v2 v2;
2524 struct rtw89_btc_fbtc_mreg_val_v7 v7;
2525 };
2526
2527 #define RTW89_DEF_FBTC_MREG(__type, __bytes, __offset) \
2528 { .type = cpu_to_le16(__type), .bytes = cpu_to_le16(__bytes), \
2529 .offset = cpu_to_le32(__offset), }
2530
2531 struct rtw89_btc_fbtc_mreg {
2532 __le16 type;
2533 __le16 bytes;
2534 __le32 offset;
2535 } __packed;
2536
2537 struct rtw89_btc_fbtc_slot {
2538 __le16 dur;
2539 __le32 cxtbl;
2540 __le16 cxtype;
2541 } __packed;
2542
2543 struct rtw89_btc_fbtc_slots {
2544 u8 fver; /* btc_ver::fcxslots */
2545 u8 tbl_num;
2546 __le16 rsvd;
2547 __le32 update_map;
2548 struct rtw89_btc_fbtc_slot slot[CXST_MAX];
2549 } __packed;
2550
2551 struct rtw89_btc_fbtc_slot_v7 {
2552 __le16 dur; /* slot duration */
2553 __le16 cxtype;
2554 __le32 cxtbl;
2555 } __packed;
2556
2557 struct rtw89_btc_fbtc_slot_u16 {
2558 __le16 dur; /* slot duration */
2559 __le16 cxtype;
2560 __le16 cxtbl_l16; /* coex table [15:0] */
2561 __le16 cxtbl_h16; /* coex table [31:16] */
2562 } __packed;
2563
2564 struct rtw89_btc_fbtc_1slot_v7 {
2565 u8 fver;
2566 u8 sid; /* slot id */
2567 __le16 rsvd;
2568 struct rtw89_btc_fbtc_slot_v7 slot;
2569 } __packed;
2570
2571 struct rtw89_btc_fbtc_slots_v7 {
2572 u8 fver;
2573 u8 slot_cnt;
2574 u8 rsvd0;
2575 u8 rsvd1;
2576 struct rtw89_btc_fbtc_slot_u16 slot[CXST_MAX];
2577 __le32 update_map;
2578 } __packed;
2579
2580 union rtw89_btc_fbtc_slots_info {
2581 struct rtw89_btc_fbtc_slots v1;
2582 struct rtw89_btc_fbtc_slots_v7 v7;
2583 } __packed;
2584
2585 struct rtw89_btc_fbtc_step {
2586 u8 type;
2587 u8 val;
2588 __le16 difft;
2589 } __packed;
2590
2591 struct rtw89_btc_fbtc_steps_v2 {
2592 u8 fver; /* btc_ver::fcxstep */
2593 u8 rsvd;
2594 __le16 cnt;
2595 __le16 pos_old;
2596 __le16 pos_new;
2597 struct rtw89_btc_fbtc_step step[FCXMAX_STEP];
2598 } __packed;
2599
2600 struct rtw89_btc_fbtc_steps_v3 {
2601 u8 fver;
2602 u8 en;
2603 __le16 rsvd;
2604 __le32 cnt;
2605 struct rtw89_btc_fbtc_step step[FCXMAX_STEP];
2606 } __packed;
2607
2608 union rtw89_btc_fbtc_steps_info {
2609 struct rtw89_btc_fbtc_steps_v2 v2;
2610 struct rtw89_btc_fbtc_steps_v3 v3;
2611 };
2612
2613 struct rtw89_btc_fbtc_cysta_v2 { /* statistics for cycles */
2614 u8 fver; /* btc_ver::fcxcysta */
2615 u8 rsvd;
2616 __le16 cycles; /* total cycle number */
2617 __le16 cycles_a2dp[CXT_FLCTRL_MAX];
2618 __le16 a2dpept; /* a2dp empty cnt */
2619 __le16 a2dpeptto; /* a2dp empty timeout cnt*/
2620 __le16 tavg_cycle[CXT_MAX]; /* avg wl/bt cycle time */
2621 __le16 tmax_cycle[CXT_MAX]; /* max wl/bt cycle time */
2622 __le16 tmaxdiff_cycle[CXT_MAX]; /* max wl-wl bt-bt cycle diff time */
2623 __le16 tavg_a2dp[CXT_FLCTRL_MAX]; /* avg a2dp PSTDMA/TDMA time */
2624 __le16 tmax_a2dp[CXT_FLCTRL_MAX]; /* max a2dp PSTDMA/TDMA time */
2625 __le16 tavg_a2dpept; /* avg a2dp empty time */
2626 __le16 tmax_a2dpept; /* max a2dp empty time */
2627 __le16 tavg_lk; /* avg leak-slot time */
2628 __le16 tmax_lk; /* max leak-slot time */
2629 __le32 slot_cnt[CXST_MAX]; /* slot count */
2630 __le32 bcn_cnt[CXBCN_MAX];
2631 __le32 leakrx_cnt; /* the rximr occur at leak slot */
2632 __le32 collision_cnt; /* counter for event/timer occur at same time */
2633 __le32 skip_cnt;
2634 __le32 exception;
2635 __le32 except_cnt;
2636 __le16 tslot_cycle[BTC_CYCLE_SLOT_MAX];
2637 } __packed;
2638
2639 struct rtw89_btc_fbtc_fdd_try_info {
2640 __le16 cycles[CXT_FLCTRL_MAX];
2641 __le16 tavg[CXT_FLCTRL_MAX]; /* avg try BT-Slot-TDD/BT-slot-FDD time */
2642 __le16 tmax[CXT_FLCTRL_MAX]; /* max try BT-Slot-TDD/BT-slot-FDD time */
2643 } __packed;
2644
2645 struct rtw89_btc_fbtc_cycle_time_info {
2646 __le16 tavg[CXT_MAX]; /* avg wl/bt cycle time */
2647 __le16 tmax[CXT_MAX]; /* max wl/bt cycle time */
2648 __le16 tmaxdiff[CXT_MAX]; /* max wl-wl bt-bt cycle diff time */
2649 } __packed;
2650
2651 struct rtw89_btc_fbtc_cycle_time_info_v5 {
2652 __le16 tavg[CXT_MAX]; /* avg wl/bt cycle time */
2653 __le16 tmax[CXT_MAX]; /* max wl/bt cycle time */
2654 } __packed;
2655
2656 struct rtw89_btc_fbtc_a2dp_trx_stat {
2657 u8 empty_cnt;
2658 u8 retry_cnt;
2659 u8 tx_rate;
2660 u8 tx_cnt;
2661 u8 ack_cnt;
2662 u8 nack_cnt;
2663 u8 rsvd1;
2664 u8 rsvd2;
2665 } __packed;
2666
2667 struct rtw89_btc_fbtc_a2dp_trx_stat_v4 {
2668 u8 empty_cnt;
2669 u8 retry_cnt;
2670 u8 tx_rate;
2671 u8 tx_cnt;
2672 u8 ack_cnt;
2673 u8 nack_cnt;
2674 u8 no_empty_cnt;
2675 u8 rsvd;
2676 } __packed;
2677
2678 struct rtw89_btc_fbtc_cycle_a2dp_empty_info {
2679 __le16 cnt; /* a2dp empty cnt */
2680 __le16 cnt_timeout; /* a2dp empty timeout cnt*/
2681 __le16 tavg; /* avg a2dp empty time */
2682 __le16 tmax; /* max a2dp empty time */
2683 } __packed;
2684
2685 struct rtw89_btc_fbtc_cycle_leak_info {
2686 __le32 cnt_rximr; /* the rximr occur at leak slot */
2687 __le16 tavg; /* avg leak-slot time */
2688 __le16 tmax; /* max leak-slot time */
2689 } __packed;
2690
2691 struct rtw89_btc_fbtc_cycle_leak_info_v7 {
2692 __le16 tavg;
2693 __le16 tamx;
2694 __le32 cnt_rximr;
2695 } __packed;
2696
2697 #define RTW89_BTC_FDDT_PHASE_CYCLE GENMASK(9, 0)
2698 #define RTW89_BTC_FDDT_TRAIN_STEP GENMASK(15, 10)
2699
2700 struct rtw89_btc_fbtc_cycle_fddt_info {
2701 __le16 train_cycle;
2702 __le16 tp;
2703
2704 s8 tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */
2705 s8 bt_tx_power; /* decrease Tx power (dB) */
2706 s8 bt_rx_gain; /* LNA constrain level */
2707 u8 no_empty_cnt;
2708
2709 u8 rssi; /* [7:4] -> bt_rssi_level, [3:0]-> wl_rssi_level */
2710 u8 cn; /* condition_num */
2711 u8 train_status; /* [7:4]-> train-state, [3:0]-> train-phase */
2712 u8 train_result; /* refer to enum btc_fddt_check_map */
2713 } __packed;
2714
2715 #define RTW89_BTC_FDDT_CELL_TRAIN_STATE GENMASK(3, 0)
2716 #define RTW89_BTC_FDDT_CELL_TRAIN_PHASE GENMASK(7, 4)
2717
2718 struct rtw89_btc_fbtc_cycle_fddt_info_v5 {
2719 __le16 train_cycle;
2720 __le16 tp;
2721
2722 s8 tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */
2723 s8 bt_tx_power; /* decrease Tx power (dB) */
2724 s8 bt_rx_gain; /* LNA constrain level */
2725 u8 no_empty_cnt;
2726
2727 u8 rssi; /* [7:4] -> bt_rssi_level, [3:0]-> wl_rssi_level */
2728 u8 cn; /* condition_num */
2729 u8 train_status; /* [7:4]-> train-state, [3:0]-> train-phase */
2730 u8 train_result; /* refer to enum btc_fddt_check_map */
2731 } __packed;
2732
2733 struct rtw89_btc_fbtc_fddt_cell_status {
2734 s8 wl_tx_pwr;
2735 s8 bt_tx_pwr;
2736 s8 bt_rx_gain;
2737 u8 state_phase; /* [0:3] train state, [4:7] train phase */
2738 } __packed;
2739
2740 struct rtw89_btc_fbtc_cysta_v3 { /* statistics for cycles */
2741 u8 fver;
2742 u8 rsvd;
2743 __le16 cycles; /* total cycle number */
2744 __le16 slot_step_time[BTC_CYCLE_SLOT_MAX];
2745 struct rtw89_btc_fbtc_cycle_time_info cycle_time;
2746 struct rtw89_btc_fbtc_fdd_try_info fdd_try;
2747 struct rtw89_btc_fbtc_cycle_a2dp_empty_info a2dp_ept;
2748 struct rtw89_btc_fbtc_a2dp_trx_stat a2dp_trx[BTC_CYCLE_SLOT_MAX];
2749 struct rtw89_btc_fbtc_cycle_leak_info leak_slot;
2750 __le32 slot_cnt[CXST_MAX]; /* slot count */
2751 __le32 bcn_cnt[CXBCN_MAX];
2752 __le32 collision_cnt; /* counter for event/timer occur at the same time */
2753 __le32 skip_cnt;
2754 __le32 except_cnt;
2755 __le32 except_map;
2756 } __packed;
2757
2758 #define FDD_TRAIN_WL_DIRECTION 2
2759 #define FDD_TRAIN_WL_RSSI_LEVEL 5
2760 #define FDD_TRAIN_BT_RSSI_LEVEL 5
2761
2762 struct rtw89_btc_fbtc_cysta_v4 { /* statistics for cycles */
2763 u8 fver;
2764 u8 rsvd;
2765 u8 collision_cnt; /* counter for event/timer occur at the same time */
2766 u8 except_cnt;
2767
2768 __le16 skip_cnt;
2769 __le16 cycles; /* total cycle number */
2770
2771 __le16 slot_step_time[BTC_CYCLE_SLOT_MAX]; /* record the wl/bt slot time */
2772 __le16 slot_cnt[CXST_MAX]; /* slot count */
2773 __le16 bcn_cnt[CXBCN_MAX];
2774 struct rtw89_btc_fbtc_cycle_time_info cycle_time;
2775 struct rtw89_btc_fbtc_cycle_leak_info leak_slot;
2776 struct rtw89_btc_fbtc_cycle_a2dp_empty_info a2dp_ept;
2777 struct rtw89_btc_fbtc_a2dp_trx_stat_v4 a2dp_trx[BTC_CYCLE_SLOT_MAX];
2778 struct rtw89_btc_fbtc_cycle_fddt_info fddt_trx[BTC_CYCLE_SLOT_MAX];
2779 struct rtw89_btc_fbtc_fddt_cell_status fddt_cells[FDD_TRAIN_WL_DIRECTION]
2780 [FDD_TRAIN_WL_RSSI_LEVEL]
2781 [FDD_TRAIN_BT_RSSI_LEVEL];
2782 __le32 except_map;
2783 } __packed;
2784
2785 struct rtw89_btc_fbtc_cysta_v5 { /* statistics for cycles */
2786 u8 fver;
2787 u8 rsvd;
2788 u8 collision_cnt; /* counter for event/timer occur at the same time */
2789 u8 except_cnt;
2790 u8 wl_rx_err_ratio[BTC_CYCLE_SLOT_MAX];
2791
2792 __le16 skip_cnt;
2793 __le16 cycles; /* total cycle number */
2794
2795 __le16 slot_step_time[BTC_CYCLE_SLOT_MAX]; /* record the wl/bt slot time */
2796 __le16 slot_cnt[CXST_MAX]; /* slot count */
2797 __le16 bcn_cnt[CXBCN_MAX];
2798 struct rtw89_btc_fbtc_cycle_time_info_v5 cycle_time;
2799 struct rtw89_btc_fbtc_cycle_leak_info leak_slot;
2800 struct rtw89_btc_fbtc_cycle_a2dp_empty_info a2dp_ept;
2801 struct rtw89_btc_fbtc_a2dp_trx_stat_v4 a2dp_trx[BTC_CYCLE_SLOT_MAX];
2802 struct rtw89_btc_fbtc_cycle_fddt_info_v5 fddt_trx[BTC_CYCLE_SLOT_MAX];
2803 struct rtw89_btc_fbtc_fddt_cell_status fddt_cells[FDD_TRAIN_WL_DIRECTION]
2804 [FDD_TRAIN_WL_RSSI_LEVEL]
2805 [FDD_TRAIN_BT_RSSI_LEVEL];
2806 __le32 except_map;
2807 } __packed;
2808
2809 struct rtw89_btc_fbtc_cysta_v7 { /* statistics for cycles */
2810 u8 fver;
2811 u8 rsvd;
2812 u8 collision_cnt; /* counter for event/timer occur at the same time */
2813 u8 except_cnt;
2814
2815 u8 wl_rx_err_ratio[BTC_CYCLE_SLOT_MAX];
2816
2817 struct rtw89_btc_fbtc_a2dp_trx_stat_v4 a2dp_trx[BTC_CYCLE_SLOT_MAX];
2818
2819 __le16 skip_cnt;
2820 __le16 cycles; /* total cycle number */
2821
2822 __le16 slot_step_time[BTC_CYCLE_SLOT_MAX]; /* record the wl/bt slot time */
2823 __le16 slot_cnt[CXST_MAX]; /* slot count */
2824 __le16 bcn_cnt[CXBCN_MAX];
2825
2826 struct rtw89_btc_fbtc_cycle_time_info_v5 cycle_time;
2827 struct rtw89_btc_fbtc_cycle_a2dp_empty_info a2dp_ept;
2828 struct rtw89_btc_fbtc_cycle_leak_info_v7 leak_slot;
2829
2830 __le32 except_map;
2831 } __packed;
2832
2833 union rtw89_btc_fbtc_cysta_info {
2834 struct rtw89_btc_fbtc_cysta_v2 v2;
2835 struct rtw89_btc_fbtc_cysta_v3 v3;
2836 struct rtw89_btc_fbtc_cysta_v4 v4;
2837 struct rtw89_btc_fbtc_cysta_v5 v5;
2838 struct rtw89_btc_fbtc_cysta_v7 v7;
2839 };
2840
2841 struct rtw89_btc_fbtc_cynullsta_v1 { /* cycle null statistics */
2842 u8 fver; /* btc_ver::fcxnullsta */
2843 u8 rsvd;
2844 __le16 rsvd2;
2845 __le32 max_t[2]; /* max_t for 0:null0/1:null1 */
2846 __le32 avg_t[2]; /* avg_t for 0:null0/1:null1 */
2847 __le32 result[2][4]; /* 0:fail, 1:ok, 2:on_time, 3:retry */
2848 } __packed;
2849
2850 struct rtw89_btc_fbtc_cynullsta_v2 { /* cycle null statistics */
2851 u8 fver; /* btc_ver::fcxnullsta */
2852 u8 rsvd;
2853 __le16 rsvd2;
2854 __le32 max_t[2]; /* max_t for 0:null0/1:null1 */
2855 __le32 avg_t[2]; /* avg_t for 0:null0/1:null1 */
2856 __le32 result[2][5]; /* 0:fail, 1:ok, 2:on_time, 3:retry, 4:tx */
2857 } __packed;
2858
2859 struct rtw89_btc_fbtc_cynullsta_v7 { /* cycle null statistics */
2860 u8 fver;
2861 u8 rsvd0;
2862 u8 rsvd1;
2863 u8 rsvd2;
2864
2865 __le32 tmax[2];
2866 __le32 tavg[2];
2867 __le32 result[2][5];
2868 } __packed;
2869
2870 union rtw89_btc_fbtc_cynullsta_info {
2871 struct rtw89_btc_fbtc_cynullsta_v1 v1; /* info from fw */
2872 struct rtw89_btc_fbtc_cynullsta_v2 v2;
2873 struct rtw89_btc_fbtc_cynullsta_v7 v7;
2874 };
2875
2876 struct rtw89_btc_fbtc_btver_v1 {
2877 u8 fver; /* btc_ver::fcxbtver */
2878 u8 rsvd;
2879 __le16 rsvd2;
2880 __le32 coex_ver; /*bit[15:8]->shared, bit[7:0]->non-shared */
2881 __le32 fw_ver;
2882 __le32 feature;
2883 } __packed;
2884
2885 struct rtw89_btc_fbtc_btver_v7 {
2886 u8 fver;
2887 u8 rsvd0;
2888 u8 rsvd1;
2889 u8 rsvd2;
2890
2891 __le32 coex_ver; /*bit[15:8]->shared, bit[7:0]->non-shared */
2892 __le32 fw_ver;
2893 __le32 feature;
2894 } __packed;
2895
2896 union rtw89_btc_fbtc_btver {
2897 struct rtw89_btc_fbtc_btver_v1 v1;
2898 struct rtw89_btc_fbtc_btver_v7 v7;
2899 } __packed;
2900
2901 struct rtw89_btc_fbtc_btafh {
2902 u8 fver; /* btc_ver::fcxbtafh */
2903 u8 rsvd;
2904 __le16 rsvd2;
2905 u8 afh_l[4]; /*bit0:2402, bit1: 2403.... bit31:2433 */
2906 u8 afh_m[4]; /*bit0:2434, bit1: 2435.... bit31:2465 */
2907 u8 afh_h[4]; /*bit0:2466, bit1:2467......bit14:2480 */
2908 } __packed;
2909
2910 struct rtw89_btc_fbtc_btafh_v2 {
2911 u8 fver; /* btc_ver::fcxbtafh */
2912 u8 rsvd;
2913 u8 rsvd2;
2914 u8 map_type;
2915 u8 afh_l[4];
2916 u8 afh_m[4];
2917 u8 afh_h[4];
2918 u8 afh_le_a[4];
2919 u8 afh_le_b[4];
2920 } __packed;
2921
2922 struct rtw89_btc_fbtc_btafh_v7 {
2923 u8 fver;
2924 u8 map_type;
2925 u8 rsvd0;
2926 u8 rsvd1;
2927 u8 afh_l[4]; /*bit0:2402, bit1:2403.... bit31:2433 */
2928 u8 afh_m[4]; /*bit0:2434, bit1:2435.... bit31:2465 */
2929 u8 afh_h[4]; /*bit0:2466, bit1:2467.....bit14:2480 */
2930 u8 afh_le_a[4];
2931 u8 afh_le_b[4];
2932 } __packed;
2933
2934 struct rtw89_btc_fbtc_btdevinfo {
2935 u8 fver; /* btc_ver::fcxbtdevinfo */
2936 u8 rsvd;
2937 __le16 vendor_id;
2938 __le32 dev_name; /* only 24 bits valid */
2939 __le32 flush_time;
2940 } __packed;
2941
2942 #define RTW89_BTC_WL_DEF_TX_PWR GENMASK(7, 0)
2943 struct rtw89_btc_rf_trx_para {
2944 u32 wl_tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */
2945 u32 wl_rx_gain; /* rx gain table index (TBD.) */
2946 u8 bt_tx_power; /* decrease Tx power (dB) */
2947 u8 bt_rx_gain; /* LNA constrain level */
2948 };
2949
2950 struct rtw89_btc_trx_info {
2951 u8 tx_lvl;
2952 u8 rx_lvl;
2953 u8 wl_rssi;
2954 u8 bt_rssi;
2955
2956 s8 tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */
2957 s8 rx_gain; /* rx gain table index (TBD.) */
2958 s8 bt_tx_power; /* decrease Tx power (dB) */
2959 s8 bt_rx_gain; /* LNA constrain level */
2960
2961 u8 cn; /* condition_num */
2962 s8 nhm;
2963 u8 bt_profile;
2964 u8 rsvd2;
2965
2966 u16 tx_rate;
2967 u16 rx_rate;
2968
2969 u32 tx_tp;
2970 u32 rx_tp;
2971 u32 rx_err_ratio;
2972 };
2973
2974 enum btc_rf_path {
2975 BTC_RF_S0 = 0,
2976 BTC_RF_S1 = 1,
2977 BTC_RF_NUM,
2978 };
2979
2980 struct rtw89_btc_fbtc_outsrc_set_info {
2981 u8 rf_band[BTC_RF_NUM]; /* 0:2G, 1:non-2G */
2982 u8 btg_rx[BTC_RF_NUM];
2983 u8 nbtg_tx[BTC_RF_NUM];
2984
2985 struct rtw89_mac_ax_gnt gnt_set[BTC_RF_NUM]; /* refer to btc_gnt_ctrl */
2986 struct rtw89_mac_ax_wl_act wlact_set[BTC_RF_NUM]; /* BT0/BT1 */
2987
2988 u8 pta_req_hw_band;
2989 u8 rf_gbt_source;
2990 } __packed;
2991
2992 union rtw89_btc_fbtc_slot_u {
2993 struct rtw89_btc_fbtc_slot v1[CXST_MAX];
2994 struct rtw89_btc_fbtc_slot_v7 v7[CXST_MAX];
2995 };
2996
2997 struct rtw89_btc_dm {
2998 struct rtw89_btc_fbtc_outsrc_set_info ost_info_last; /* outsrc API setup info */
2999 struct rtw89_btc_fbtc_outsrc_set_info ost_info; /* outsrc API setup info */
3000 union rtw89_btc_fbtc_slot_u slot;
3001 union rtw89_btc_fbtc_slot_u slot_now;
3002 struct rtw89_btc_fbtc_tdma tdma;
3003 struct rtw89_btc_fbtc_tdma tdma_now;
3004 struct rtw89_mac_ax_coex_gnt gnt;
3005 union rtw89_btc_init_info_u init_info; /* pass to wl_fw if offload */
3006 struct rtw89_btc_rf_trx_para rf_trx_para;
3007 struct rtw89_btc_wl_tx_limit_para wl_tx_limit;
3008 struct rtw89_btc_dm_step dm_step;
3009 struct rtw89_btc_wl_scc_ctrl wl_scc;
3010 struct rtw89_btc_trx_info trx_info;
3011 union rtw89_btc_dm_error_map error;
3012 u32 cnt_dm[BTC_DCNT_NUM];
3013 u32 cnt_notify[BTC_NCNT_NUM];
3014
3015 u32 update_slot_map;
3016 u32 set_ant_path;
3017 u32 e2g_slot_limit;
3018 u32 e2g_slot_nulltx_time;
3019
3020 u32 wl_only: 1;
3021 u32 wl_fw_cx_offload: 1;
3022 u32 freerun: 1;
3023 u32 fddt_train: 1;
3024 u32 wl_ps_ctrl: 2;
3025 u32 wl_mimo_ps: 1;
3026 u32 leak_ap: 1;
3027 u32 noisy_level: 3;
3028 u32 coex_info_map: 8;
3029 u32 bt_only: 1;
3030 u32 wl_btg_rx: 2;
3031 u32 trx_para_level: 8;
3032 u32 wl_stb_chg: 1;
3033 u32 pta_owner: 1;
3034
3035 u32 tdma_instant_excute: 1;
3036 u32 wl_btg_rx_rb: 2;
3037
3038 u16 slot_dur[CXST_MAX];
3039 u16 bt_slot_flood;
3040
3041 u8 run_reason;
3042 u8 run_action;
3043
3044 u8 wl_pre_agc: 2;
3045 u8 wl_lna2: 1;
3046 u8 freerun_chk: 1;
3047 u8 wl_pre_agc_rb: 2;
3048 u8 bt_select: 2; /* 0:s0, 1:s1, 2:s0 & s1, refer to enum btc_bt_index */
3049 u8 slot_req_more: 1;
3050 };
3051
3052 struct rtw89_btc_ctrl {
3053 u32 manual: 1;
3054 u32 igno_bt: 1;
3055 u32 always_freerun: 1;
3056 u32 trace_step: 16;
3057 u32 rsvd: 12;
3058 };
3059
3060 struct rtw89_btc_ctrl_v7 {
3061 u8 manual;
3062 u8 igno_bt;
3063 u8 always_freerun;
3064 u8 rsvd;
3065 } __packed;
3066
3067 union rtw89_btc_ctrl_list {
3068 struct rtw89_btc_ctrl ctrl;
3069 struct rtw89_btc_ctrl_v7 ctrl_v7;
3070 };
3071
3072 struct rtw89_btc_dbg {
3073 /* cmd "rb" */
3074 bool rb_done;
3075 u32 rb_val;
3076 };
3077
3078 enum rtw89_btc_btf_fw_event {
3079 BTF_EVNT_RPT = 0,
3080 BTF_EVNT_BT_INFO = 1,
3081 BTF_EVNT_BT_SCBD = 2,
3082 BTF_EVNT_BT_REG = 3,
3083 BTF_EVNT_CX_RUNINFO = 4,
3084 BTF_EVNT_BT_PSD = 5,
3085 BTF_EVNT_BT_DEV_INFO = 6, /* fwc2hfunc > 0 */
3086 BTF_EVNT_BT_LEAUDIO_INFO = 7, /* fwc2hfunc > 1 */
3087 BTF_EVNT_BUF_OVERFLOW,
3088 BTF_EVNT_C2H_LOOPBACK,
3089 BTF_EVNT_BT_QUERY_TXPWR, /* fwc2hfunc > 3 */
3090 BTF_EVNT_MAX,
3091 };
3092
3093 enum btf_fw_event_report {
3094 BTC_RPT_TYPE_CTRL = 0x0,
3095 BTC_RPT_TYPE_TDMA,
3096 BTC_RPT_TYPE_SLOT,
3097 BTC_RPT_TYPE_CYSTA,
3098 BTC_RPT_TYPE_STEP,
3099 BTC_RPT_TYPE_NULLSTA,
3100 BTC_RPT_TYPE_FDDT, /* added by ver->fwevntrptl == 1 */
3101 BTC_RPT_TYPE_MREG,
3102 BTC_RPT_TYPE_GPIO_DBG,
3103 BTC_RPT_TYPE_BT_VER,
3104 BTC_RPT_TYPE_BT_SCAN,
3105 BTC_RPT_TYPE_BT_AFH,
3106 BTC_RPT_TYPE_BT_DEVICE,
3107 BTC_RPT_TYPE_TEST,
3108 BTC_RPT_TYPE_MAX = 31,
3109
3110 __BTC_RPT_TYPE_V0_SAME = BTC_RPT_TYPE_NULLSTA,
3111 __BTC_RPT_TYPE_V0_MAX = 12,
3112 };
3113
3114 enum rtw_btc_btf_reg_type {
3115 REG_MAC = 0x0,
3116 REG_BB = 0x1,
3117 REG_RF = 0x2,
3118 REG_BT_RF = 0x3,
3119 REG_BT_MODEM = 0x4,
3120 REG_BT_BLUEWIZE = 0x5,
3121 REG_BT_VENDOR = 0x6,
3122 REG_BT_LE = 0x7,
3123 REG_MAX_TYPE,
3124 };
3125
3126 struct rtw89_btc_rpt_cmn_info {
3127 u32 rx_cnt;
3128 u32 rx_len;
3129 u32 req_len; /* expected rsp len */
3130 u8 req_fver; /* expected rsp fver */
3131 u8 rsp_fver; /* fver from fw */
3132 u8 valid;
3133 } __packed;
3134
3135 union rtw89_btc_fbtc_btafh_info {
3136 struct rtw89_btc_fbtc_btafh v1;
3137 struct rtw89_btc_fbtc_btafh_v2 v2;
3138 struct rtw89_btc_fbtc_btafh_v7 v7;
3139 };
3140
3141 struct rtw89_btc_report_ctrl_state {
3142 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
3143 union rtw89_btc_fbtc_rpt_ctrl_ver_info finfo;
3144 };
3145
3146 struct rtw89_btc_rpt_fbtc_tdma {
3147 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
3148 union rtw89_btc_fbtc_tdma_le32 finfo;
3149 };
3150
3151 struct rtw89_btc_rpt_fbtc_slots {
3152 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
3153 union rtw89_btc_fbtc_slots_info finfo; /* info from fw */
3154 };
3155
3156 struct rtw89_btc_rpt_fbtc_cysta {
3157 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
3158 union rtw89_btc_fbtc_cysta_info finfo;
3159 };
3160
3161 struct rtw89_btc_rpt_fbtc_step {
3162 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
3163 union rtw89_btc_fbtc_steps_info finfo; /* info from fw */
3164 };
3165
3166 struct rtw89_btc_rpt_fbtc_nullsta {
3167 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
3168 union rtw89_btc_fbtc_cynullsta_info finfo;
3169 };
3170
3171 struct rtw89_btc_rpt_fbtc_mreg {
3172 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
3173 union rtw89_btc_fbtc_mreg_val finfo; /* info from fw */
3174 };
3175
3176 struct rtw89_btc_rpt_fbtc_gpio_dbg {
3177 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
3178 union rtw89_btc_fbtc_gpio_dbg finfo; /* info from fw */
3179 };
3180
3181 struct rtw89_btc_rpt_fbtc_btver {
3182 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
3183 union rtw89_btc_fbtc_btver finfo; /* info from fw */
3184 };
3185
3186 struct rtw89_btc_rpt_fbtc_btscan {
3187 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
3188 union rtw89_btc_fbtc_btscan finfo; /* info from fw */
3189 };
3190
3191 struct rtw89_btc_rpt_fbtc_btafh {
3192 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
3193 union rtw89_btc_fbtc_btafh_info finfo;
3194 };
3195
3196 struct rtw89_btc_rpt_fbtc_btdev {
3197 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
3198 struct rtw89_btc_fbtc_btdevinfo finfo; /* info from fw */
3199 };
3200
3201 enum rtw89_btc_btfre_type {
3202 BTFRE_INVALID_INPUT = 0x0, /* invalid input parameters */
3203 BTFRE_UNDEF_TYPE,
3204 BTFRE_EXCEPTION,
3205 BTFRE_MAX,
3206 };
3207
3208 struct rtw89_btc_ver {
3209 enum rtw89_core_chip_id chip_id;
3210 u32 fw_ver_code;
3211
3212 u8 fcxbtcrpt;
3213 u8 fcxtdma;
3214 u8 fcxslots;
3215 u8 fcxcysta;
3216 u8 fcxstep;
3217 u8 fcxnullsta;
3218 u8 fcxmreg;
3219 u8 fcxgpiodbg;
3220 u8 fcxbtver;
3221 u8 fcxbtscan;
3222 u8 fcxbtafh;
3223 u8 fcxbtdevinfo;
3224 u8 fwlrole;
3225 u8 frptmap;
3226 u8 fcxctrl;
3227 u8 fcxinit;
3228
3229 u8 fwevntrptl;
3230 u8 fwc2hfunc;
3231 u8 drvinfo_type;
3232 u16 info_buf;
3233 u8 max_role_num;
3234 u8 fcxosi;
3235 u8 fcxmlo;
3236 u8 bt_desired;
3237 };
3238
3239 struct rtw89_btc_btf_fwinfo {
3240 u32 cnt_c2h;
3241 u32 cnt_h2c;
3242 u32 cnt_h2c_fail;
3243 u32 event[BTF_EVNT_MAX];
3244
3245 u32 err[BTFRE_MAX];
3246 u32 len_mismch;
3247 u32 fver_mismch;
3248 u32 rpt_en_map;
3249
3250 struct rtw89_btc_ver fw_subver;
3251 struct rtw89_btc_report_ctrl_state rpt_ctrl;
3252 struct rtw89_btc_rpt_fbtc_tdma rpt_fbtc_tdma;
3253 struct rtw89_btc_rpt_fbtc_slots rpt_fbtc_slots;
3254 struct rtw89_btc_rpt_fbtc_cysta rpt_fbtc_cysta;
3255 struct rtw89_btc_rpt_fbtc_step rpt_fbtc_step;
3256 struct rtw89_btc_rpt_fbtc_nullsta rpt_fbtc_nullsta;
3257 struct rtw89_btc_rpt_fbtc_mreg rpt_fbtc_mregval;
3258 struct rtw89_btc_rpt_fbtc_gpio_dbg rpt_fbtc_gpio_dbg;
3259 struct rtw89_btc_rpt_fbtc_btver rpt_fbtc_btver;
3260 struct rtw89_btc_rpt_fbtc_btscan rpt_fbtc_btscan;
3261 struct rtw89_btc_rpt_fbtc_btafh rpt_fbtc_btafh;
3262 struct rtw89_btc_rpt_fbtc_btdev rpt_fbtc_btdev;
3263 };
3264
3265 #define RTW89_BTC_POLICY_MAXLEN 512
3266
3267 struct rtw89_btc {
3268 const struct rtw89_btc_ver *ver;
3269
3270 struct rtw89_btc_cx cx;
3271 struct rtw89_btc_dm dm;
3272 union rtw89_btc_ctrl_list ctrl;
3273 union rtw89_btc_module_info mdinfo;
3274 struct rtw89_btc_btf_fwinfo fwinfo;
3275 struct rtw89_btc_dbg dbg;
3276
3277 struct wiphy_work eapol_notify_work;
3278 struct wiphy_work arp_notify_work;
3279 struct wiphy_work dhcp_notify_work;
3280 struct wiphy_work icmp_notify_work;
3281
3282 u32 bt_req_len;
3283
3284 u8 policy[RTW89_BTC_POLICY_MAXLEN];
3285 u8 ant_type;
3286 u8 btg_pos;
3287 u16 policy_len;
3288 u16 policy_type;
3289 u32 hubmsg_cnt;
3290 bool bt_req_en;
3291 bool update_policy_force;
3292 bool lps;
3293 bool manual_ctrl;
3294 };
3295
3296 enum rtw89_btc_hmsg {
3297 RTW89_BTC_HMSG_TMR_EN = 0x0,
3298 RTW89_BTC_HMSG_BT_REG_READBACK = 0x1,
3299 RTW89_BTC_HMSG_SET_BT_REQ_SLOT = 0x2,
3300 RTW89_BTC_HMSG_FW_EV = 0x3,
3301 RTW89_BTC_HMSG_BT_LINK_CHG = 0x4,
3302 RTW89_BTC_HMSG_SET_BT_REQ_STBC = 0x5,
3303
3304 NUM_OF_RTW89_BTC_HMSG,
3305 };
3306
3307 enum rtw89_ra_mode {
3308 RTW89_RA_MODE_CCK = BIT(0),
3309 RTW89_RA_MODE_OFDM = BIT(1),
3310 RTW89_RA_MODE_HT = BIT(2),
3311 RTW89_RA_MODE_VHT = BIT(3),
3312 RTW89_RA_MODE_HE = BIT(4),
3313 RTW89_RA_MODE_EHT = BIT(5),
3314 };
3315
3316 enum rtw89_ra_report_mode {
3317 RTW89_RA_RPT_MODE_LEGACY,
3318 RTW89_RA_RPT_MODE_HT,
3319 RTW89_RA_RPT_MODE_VHT,
3320 RTW89_RA_RPT_MODE_HE,
3321 RTW89_RA_RPT_MODE_EHT,
3322 };
3323
3324 enum rtw89_dig_noisy_level {
3325 RTW89_DIG_NOISY_LEVEL0 = -1,
3326 RTW89_DIG_NOISY_LEVEL1 = 0,
3327 RTW89_DIG_NOISY_LEVEL2 = 1,
3328 RTW89_DIG_NOISY_LEVEL3 = 2,
3329 RTW89_DIG_NOISY_LEVEL_MAX = 3,
3330 };
3331
3332 enum rtw89_gi_ltf {
3333 RTW89_GILTF_LGI_4XHE32 = 0,
3334 RTW89_GILTF_SGI_4XHE08 = 1,
3335 RTW89_GILTF_2XHE16 = 2,
3336 RTW89_GILTF_2XHE08 = 3,
3337 RTW89_GILTF_1XHE16 = 4,
3338 RTW89_GILTF_1XHE08 = 5,
3339 RTW89_GILTF_MAX
3340 };
3341
3342 enum rtw89_rx_frame_type {
3343 RTW89_RX_TYPE_MGNT = 0,
3344 RTW89_RX_TYPE_CTRL = 1,
3345 RTW89_RX_TYPE_DATA = 2,
3346 RTW89_RX_TYPE_RSVD = 3,
3347 };
3348
3349 enum rtw89_efuse_block {
3350 RTW89_EFUSE_BLOCK_SYS = 0,
3351 RTW89_EFUSE_BLOCK_RF = 1,
3352 RTW89_EFUSE_BLOCK_HCI_DIG_PCIE_SDIO = 2,
3353 RTW89_EFUSE_BLOCK_HCI_DIG_USB = 3,
3354 RTW89_EFUSE_BLOCK_HCI_PHY_PCIE = 4,
3355 RTW89_EFUSE_BLOCK_HCI_PHY_USB3 = 5,
3356 RTW89_EFUSE_BLOCK_HCI_PHY_USB2 = 6,
3357 RTW89_EFUSE_BLOCK_ADIE = 7,
3358
3359 RTW89_EFUSE_BLOCK_NUM,
3360 RTW89_EFUSE_BLOCK_IGNORE,
3361 };
3362
3363 struct rtw89_ra_info {
3364 u8 is_dis_ra:1;
3365 /* Bit0 : CCK
3366 * Bit1 : OFDM
3367 * Bit2 : HT
3368 * Bit3 : VHT
3369 * Bit4 : HE
3370 * Bit5 : EHT
3371 */
3372 u8 mode_ctrl:6;
3373 u8 bw_cap:3; /* enum rtw89_bandwidth */
3374 u8 macid;
3375 u8 dcm_cap:1;
3376 u8 er_cap:1;
3377 u8 init_rate_lv:2;
3378 u8 upd_all:1;
3379 u8 en_sgi:1;
3380 u8 ldpc_cap:1;
3381 u8 stbc_cap:1;
3382 u8 ss_num:3;
3383 u8 giltf:3;
3384 u8 upd_bw_nss_mask:1;
3385 u8 upd_mask:1;
3386 u64 ra_mask; /* 63 bits ra_mask + 1 bit CSI ctrl */
3387 /* BFee CSI */
3388 u8 band_num;
3389 u8 ra_csi_rate_en:1;
3390 u8 fixed_csi_rate_en:1;
3391 u8 cr_tbl_sel:1;
3392 u8 fix_giltf_en:1;
3393 u8 fix_giltf:3;
3394 u8 partial_bw_er:1;
3395 u8 csi_mcs_ss_idx;
3396 u8 csi_mode:2;
3397 u8 csi_gi_ltf:3;
3398 u8 csi_bw:3;
3399 /* after v1 */
3400 u8 is_noisy:1;
3401 u8 psra_en:1;
3402 u8 rsvd0:1;
3403 u8 macid_msb:2;
3404 u8 band:2; /* enum rtw89_band */
3405 u8 is_new_dbgreg:1;
3406 };
3407
3408 #define RTW89_PPDU_MAC_INFO_USR_SIZE 4
3409 #define RTW89_PPDU_MAC_INFO_SIZE 8
3410 #define RTW89_PPDU_MAC_RX_CNT_SIZE 96
3411 #define RTW89_PPDU_MAC_RX_CNT_SIZE_V1 128
3412
3413 #define RTW89_MAX_RX_AGG_NUM 64
3414 #define RTW89_MAX_TX_AGG_NUM 128
3415
3416 struct rtw89_ampdu_params {
3417 u16 agg_num;
3418 bool amsdu;
3419 };
3420
3421 struct rtw89_ra_report {
3422 struct rate_info txrate;
3423 u32 bit_rate;
3424 u16 hw_rate;
3425 bool might_fallback_legacy;
3426 };
3427
3428 DECLARE_EWMA(rssi, 10, 16);
3429 DECLARE_EWMA(evm, 10, 16);
3430 DECLARE_EWMA(snr, 10, 16);
3431
3432 struct rtw89_ba_cam_entry {
3433 struct list_head list;
3434 u8 tid;
3435 };
3436
3437 #define RTW89_MAX_ADDR_CAM_NUM 128
3438 #define RTW89_MAX_BSSID_CAM_NUM 20
3439 #define RTW89_MAX_SEC_CAM_NUM 128
3440 #define RTW89_MAX_BA_CAM_NUM 24
3441 #define RTW89_SEC_CAM_IN_ADDR_CAM 7
3442
3443 struct rtw89_addr_cam_entry {
3444 u8 addr_cam_idx;
3445 u8 offset;
3446 u8 len;
3447 u8 valid : 1;
3448 u8 addr_mask : 6;
3449 u8 wapi : 1;
3450 u8 mask_sel : 2;
3451 u8 bssid_cam_idx: 6;
3452
3453 u8 sec_ent_mode;
3454 DECLARE_BITMAP(sec_cam_map, RTW89_SEC_CAM_IN_ADDR_CAM);
3455 u8 sec_ent_keyid[RTW89_SEC_CAM_IN_ADDR_CAM];
3456 u8 sec_ent[RTW89_SEC_CAM_IN_ADDR_CAM];
3457 };
3458
3459 struct rtw89_bssid_cam_entry {
3460 u8 bssid[ETH_ALEN];
3461 u8 phy_idx;
3462 u8 bssid_cam_idx;
3463 u8 offset;
3464 u8 len;
3465 u8 valid : 1;
3466 u8 num;
3467 };
3468
3469 struct rtw89_sec_cam_entry {
3470 u8 sec_cam_idx;
3471 u8 offset;
3472 u8 len;
3473 u8 type : 4;
3474 u8 ext_key : 1;
3475 u8 spp_mode : 1;
3476 /* 256 bits */
3477 u8 key[32];
3478
3479 struct ieee80211_key_conf *key_conf;
3480 };
3481
3482 struct rtw89_sta_link {
3483 struct rtw89_sta *rtwsta;
3484 struct list_head dlink_schd;
3485 unsigned int link_id;
3486
3487 u8 mac_id;
3488 u8 tx_retry;
3489 bool er_cap;
3490 struct rtw89_vif_link *rtwvif_link;
3491 struct rtw89_ra_info ra;
3492 struct rtw89_ra_report ra_report;
3493 int max_agg_wait;
3494 u8 prev_rssi;
3495 struct ewma_rssi avg_rssi;
3496 struct ewma_rssi rssi[RF_PATH_MAX];
3497 struct ewma_snr avg_snr;
3498 struct ewma_evm evm_1ss;
3499 struct ewma_evm evm_min[RF_PATH_MAX];
3500 struct ewma_evm evm_max[RF_PATH_MAX];
3501 struct ieee80211_rx_status rx_status;
3502 u16 rx_hw_rate;
3503 __le32 htc_template;
3504 struct rtw89_addr_cam_entry addr_cam; /* AP mode or TDLS peer only */
3505 struct rtw89_bssid_cam_entry bssid_cam; /* TDLS peer only */
3506 struct list_head ba_cam_list;
3507
3508 bool use_cfg_mask;
3509 struct cfg80211_bitrate_mask mask;
3510
3511 bool cctl_tx_time;
3512 u32 ampdu_max_time:4;
3513 bool cctl_tx_retry_limit;
3514 u32 data_tx_cnt_lmt:6;
3515 };
3516
3517 struct rtw89_efuse {
3518 bool valid;
3519 bool power_k_valid;
3520 u8 xtal_cap;
3521 u8 addr[ETH_ALEN];
3522 u8 rfe_type;
3523 char country_code[2];
3524 u8 adc_td;
3525 };
3526
3527 struct rtw89_phy_rate_pattern {
3528 u64 ra_mask;
3529 u16 rate;
3530 u8 ra_mode;
3531 bool enable;
3532 };
3533
3534 #define RTW89_TX_DONE 0x0
3535 #define RTW89_TX_RETRY_LIMIT 0x1
3536 #define RTW89_TX_LIFE_TIME 0x2
3537 #define RTW89_TX_MACID_DROP 0x3
3538
3539 #define RTW89_MAX_TX_RPTS 16
3540 #define RTW89_MAX_TX_RPTS_MASK (RTW89_MAX_TX_RPTS - 1)
3541 struct rtw89_tx_rpt {
3542 struct sk_buff *skbs[RTW89_MAX_TX_RPTS];
3543 /* protect skbs array access/modification */
3544 spinlock_t skb_lock;
3545 atomic_t sn;
3546 };
3547
3548 #define RTW89_TX_WAIT_WORK_TIMEOUT msecs_to_jiffies(500)
3549 struct rtw89_tx_wait_info {
3550 struct rcu_head rcu_head;
3551 struct list_head list;
3552 struct completion completion;
3553 struct sk_buff *skb;
3554 bool tx_done;
3555 };
3556
3557 struct rtw89_tx_skb_data {
3558 struct rtw89_tx_wait_info __rcu *wait;
3559 u8 tx_rpt_sn;
3560 u8 tx_pkt_cnt_lmt;
3561 u8 hci_priv[];
3562 };
3563
3564 #define RTW89_SCAN_NULL_TIMEOUT 30
3565
3566 #define RTW89_ROC_IDLE_TIMEOUT 500
3567 #define RTW89_ROC_TX_TIMEOUT 30
3568 enum rtw89_roc_state {
3569 RTW89_ROC_IDLE,
3570 RTW89_ROC_NORMAL,
3571 RTW89_ROC_MGMT,
3572 };
3573
3574 struct rtw89_roc {
3575 struct ieee80211_channel chan;
3576 struct wiphy_delayed_work roc_work;
3577 enum ieee80211_roc_type type;
3578 enum rtw89_roc_state state;
3579 int duration;
3580 unsigned int link_id;
3581 };
3582
3583 #define RTW89_P2P_MAX_NOA_NUM 2
3584
3585 struct rtw89_p2p_ie_head {
3586 u8 eid;
3587 u8 ie_len;
3588 u8 oui[3];
3589 u8 oui_type;
3590 } __packed;
3591
3592 struct rtw89_noa_attr_head {
3593 u8 attr_type;
3594 __le16 attr_len;
3595 u8 index;
3596 u8 oppps_ctwindow;
3597 } __packed;
3598
3599 struct rtw89_p2p_noa_ie {
3600 struct rtw89_p2p_ie_head p2p_head;
3601 struct rtw89_noa_attr_head noa_head;
3602 struct ieee80211_p2p_noa_desc noa_desc[RTW89_P2P_MAX_NOA_NUM];
3603 } __packed;
3604
3605 struct rtw89_p2p_noa_setter {
3606 struct rtw89_p2p_noa_ie ie;
3607 u8 noa_count;
3608 u8 noa_index;
3609 };
3610
3611 struct rtw89_ps_noa_once_handler {
3612 bool in_duration;
3613 u64 tsf_begin;
3614 u64 tsf_end;
3615 struct wiphy_delayed_work set_work;
3616 struct wiphy_delayed_work clr_work;
3617 };
3618
3619 struct rtw89_vif_link {
3620 struct rtw89_vif *rtwvif;
3621 struct list_head dlink_schd;
3622 unsigned int link_id;
3623
3624 bool chanctx_assigned; /* only valid when running with chanctx_ops */
3625 enum rtw89_chanctx_idx chanctx_idx;
3626 enum rtw89_reg_6ghz_power reg_6ghz_power;
3627 struct rtw89_reg_6ghz_tpe reg_6ghz_tpe;
3628
3629 u8 mac_id;
3630 u8 port;
3631 u8 mac_addr[ETH_ALEN];
3632 u8 bssid[ETH_ALEN];
3633 u8 phy_idx;
3634 u8 mac_idx;
3635 u8 net_type;
3636 u8 wifi_role;
3637 u8 self_role;
3638 u8 wmm;
3639 u8 bcn_hit_cond;
3640 u8 bcn_bw_idx;
3641 u8 hit_rule;
3642 u8 last_noa_nr;
3643 u64 sync_bcn_tsf;
3644 u64 last_sync_bcn_tsf;
3645 bool rand_tsf_done;
3646 bool trigger;
3647 bool lsig_txop;
3648 u8 tgt_ind;
3649 u8 frm_tgt_ind;
3650 bool wowlan_pattern;
3651 bool wowlan_uc;
3652 bool wowlan_magic;
3653 bool is_hesta;
3654 bool last_a_ctrl;
3655 bool dyn_tb_bedge_en;
3656 bool pre_pwr_diff_en;
3657 bool pwr_diff_en;
3658 u8 def_tri_idx;
3659 struct wiphy_work update_beacon_work;
3660 struct wiphy_delayed_work csa_beacon_work;
3661 struct rtw89_addr_cam_entry addr_cam;
3662 struct rtw89_bssid_cam_entry bssid_cam;
3663 struct ieee80211_tx_queue_params tx_params[IEEE80211_NUM_ACS];
3664 struct rtw89_phy_rate_pattern rate_pattern;
3665 struct list_head general_pkt_list;
3666 struct rtw89_p2p_noa_setter p2p_noa;
3667 struct rtw89_ps_noa_once_handler noa_once;
3668 struct wiphy_delayed_work mcc_gc_detect_beacon_work;
3669 u8 detect_bcn_count;
3670 };
3671
3672 enum rtw89_lv1_rcvy_step {
3673 RTW89_LV1_RCVY_STEP_1,
3674 RTW89_LV1_RCVY_STEP_2,
3675 };
3676
3677 struct rtw89_hci_ops {
3678 int (*tx_write)(struct rtw89_dev *rtwdev, struct rtw89_core_tx_request *tx_req);
3679 void (*tx_kick_off)(struct rtw89_dev *rtwdev, u8 txch);
3680 void (*flush_queues)(struct rtw89_dev *rtwdev, u32 queues, bool drop);
3681 void (*reset)(struct rtw89_dev *rtwdev);
3682 int (*start)(struct rtw89_dev *rtwdev);
3683 void (*stop)(struct rtw89_dev *rtwdev);
3684 void (*pause)(struct rtw89_dev *rtwdev, bool pause);
3685 void (*switch_mode)(struct rtw89_dev *rtwdev, bool low_power);
3686 void (*recalc_int_mit)(struct rtw89_dev *rtwdev);
3687
3688 u8 (*read8)(struct rtw89_dev *rtwdev, u32 addr);
3689 u16 (*read16)(struct rtw89_dev *rtwdev, u32 addr);
3690 u32 (*read32)(struct rtw89_dev *rtwdev, u32 addr);
3691 void (*write8)(struct rtw89_dev *rtwdev, u32 addr, u8 data);
3692 void (*write16)(struct rtw89_dev *rtwdev, u32 addr, u16 data);
3693 void (*write32)(struct rtw89_dev *rtwdev, u32 addr, u32 data);
3694
3695 u32 (*read32_pci_cfg)(struct rtw89_dev *rtwdev, u32 addr);
3696
3697 int (*mac_pre_init)(struct rtw89_dev *rtwdev);
3698 int (*mac_pre_deinit)(struct rtw89_dev *rtwdev);
3699 int (*mac_post_init)(struct rtw89_dev *rtwdev);
3700 int (*deinit)(struct rtw89_dev *rtwdev);
3701
3702 u32 (*check_and_reclaim_tx_resource)(struct rtw89_dev *rtwdev, u8 txch);
3703 int (*mac_lv1_rcvy)(struct rtw89_dev *rtwdev, enum rtw89_lv1_rcvy_step step);
3704 void (*dump_err_status)(struct rtw89_dev *rtwdev);
3705 int (*napi_poll)(struct napi_struct *napi, int budget);
3706
3707 /* Deal with locks inside recovery_start and recovery_complete callbacks
3708 * by hci instance, and handle things which need to consider under SER.
3709 * e.g. turn on/off interrupts except for the one for halt notification.
3710 */
3711 void (*recovery_start)(struct rtw89_dev *rtwdev);
3712 void (*recovery_complete)(struct rtw89_dev *rtwdev);
3713
3714 void (*ctrl_txdma_ch)(struct rtw89_dev *rtwdev, bool enable);
3715 void (*ctrl_txdma_fw_ch)(struct rtw89_dev *rtwdev, bool enable);
3716 void (*ctrl_trxhci)(struct rtw89_dev *rtwdev, bool enable);
3717 int (*poll_txdma_ch_idle)(struct rtw89_dev *rtwdev);
3718 void (*clr_idx_all)(struct rtw89_dev *rtwdev);
3719 void (*clear)(struct rtw89_dev *rtwdev, struct pci_dev *pdev);
3720 void (*disable_intr)(struct rtw89_dev *rtwdev);
3721 void (*enable_intr)(struct rtw89_dev *rtwdev);
3722 int (*rst_bdram)(struct rtw89_dev *rtwdev);
3723 };
3724
3725 struct rtw89_hci_info {
3726 const struct rtw89_hci_ops *ops;
3727 enum rtw89_hci_type type;
3728 enum rtw89_hci_dle_type dle_type;
3729 u32 rpwm_addr;
3730 u32 cpwm_addr;
3731 bool paused;
3732 bool tx_rpt_enabled;
3733 };
3734
3735 struct rtw89_chip_ops {
3736 int (*enable_bb_rf)(struct rtw89_dev *rtwdev);
3737 int (*disable_bb_rf)(struct rtw89_dev *rtwdev);
3738 void (*bb_preinit)(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx);
3739 void (*bb_postinit)(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx);
3740 void (*bb_reset)(struct rtw89_dev *rtwdev,
3741 enum rtw89_phy_idx phy_idx);
3742 void (*bb_sethw)(struct rtw89_dev *rtwdev);
3743 u32 (*read_rf)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
3744 u32 addr, u32 mask);
3745 bool (*write_rf)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
3746 u32 addr, u32 mask, u32 data);
3747 void (*set_channel)(struct rtw89_dev *rtwdev,
3748 const struct rtw89_chan *chan,
3749 enum rtw89_mac_idx mac_idx,
3750 enum rtw89_phy_idx phy_idx);
3751 void (*set_channel_help)(struct rtw89_dev *rtwdev, bool enter,
3752 struct rtw89_channel_help_params *p,
3753 const struct rtw89_chan *chan,
3754 enum rtw89_mac_idx mac_idx,
3755 enum rtw89_phy_idx phy_idx);
3756 int (*read_efuse)(struct rtw89_dev *rtwdev, u8 *log_map,
3757 enum rtw89_efuse_block block);
3758 int (*read_phycap)(struct rtw89_dev *rtwdev, u8 *phycap_map);
3759 void (*fem_setup)(struct rtw89_dev *rtwdev);
3760 void (*rfe_gpio)(struct rtw89_dev *rtwdev);
3761 void (*rfk_hw_init)(struct rtw89_dev *rtwdev);
3762 void (*rfk_init)(struct rtw89_dev *rtwdev);
3763 void (*rfk_init_late)(struct rtw89_dev *rtwdev);
3764 void (*rfk_channel)(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link);
3765 void (*rfk_band_changed)(struct rtw89_dev *rtwdev,
3766 enum rtw89_phy_idx phy_idx,
3767 const struct rtw89_chan *chan);
3768 void (*rfk_scan)(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link,
3769 bool start);
3770 void (*rfk_track)(struct rtw89_dev *rtwdev);
3771 void (*power_trim)(struct rtw89_dev *rtwdev);
3772 void (*set_txpwr)(struct rtw89_dev *rtwdev,
3773 const struct rtw89_chan *chan,
3774 enum rtw89_phy_idx phy_idx);
3775 void (*set_txpwr_ctrl)(struct rtw89_dev *rtwdev,
3776 enum rtw89_phy_idx phy_idx);
3777 int (*init_txpwr_unit)(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx);
3778 u8 (*get_thermal)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path);
3779 u32 (*chan_to_rf18_val)(struct rtw89_dev *rtwdev,
3780 const struct rtw89_chan *chan);
3781 void (*ctrl_btg_bt_rx)(struct rtw89_dev *rtwdev, bool en,
3782 enum rtw89_phy_idx phy_idx);
3783 void (*query_ppdu)(struct rtw89_dev *rtwdev,
3784 struct rtw89_rx_phy_ppdu *phy_ppdu,
3785 struct ieee80211_rx_status *status);
3786 void (*convert_rpl_to_rssi)(struct rtw89_dev *rtwdev,
3787 struct rtw89_rx_phy_ppdu *phy_ppdu);
3788 void (*phy_rpt_to_rssi)(struct rtw89_dev *rtwdev,
3789 struct rtw89_rx_desc_info *desc_info,
3790 struct ieee80211_rx_status *rx_status);
3791 void (*ctrl_nbtg_bt_tx)(struct rtw89_dev *rtwdev, bool en,
3792 enum rtw89_phy_idx phy_idx);
3793 void (*cfg_txrx_path)(struct rtw89_dev *rtwdev);
3794 void (*set_txpwr_ul_tb_offset)(struct rtw89_dev *rtwdev,
3795 s8 pw_ofst, enum rtw89_mac_idx mac_idx);
3796 void (*digital_pwr_comp)(struct rtw89_dev *rtwdev,
3797 enum rtw89_phy_idx phy_idx);
3798 int (*pwr_on_func)(struct rtw89_dev *rtwdev);
3799 int (*pwr_off_func)(struct rtw89_dev *rtwdev);
3800 void (*query_rxdesc)(struct rtw89_dev *rtwdev,
3801 struct rtw89_rx_desc_info *desc_info,
3802 u8 *data, u32 data_offset);
3803 void (*fill_txdesc)(struct rtw89_dev *rtwdev,
3804 struct rtw89_tx_desc_info *desc_info,
3805 void *txdesc);
3806 void (*fill_txdesc_fwcmd)(struct rtw89_dev *rtwdev,
3807 struct rtw89_tx_desc_info *desc_info,
3808 void *txdesc);
3809 u8 (*get_ch_dma[RTW89_HCI_TYPE_NUM])(struct rtw89_dev *rtwdev, u8 qsel);
3810 int (*cfg_ctrl_path)(struct rtw89_dev *rtwdev, bool wl);
3811 int (*mac_cfg_gnt)(struct rtw89_dev *rtwdev,
3812 const struct rtw89_mac_ax_coex_gnt *gnt_cfg);
3813 int (*stop_sch_tx)(struct rtw89_dev *rtwdev, u8 mac_idx,
3814 u32 *tx_en, enum rtw89_sch_tx_sel sel);
3815 int (*resume_sch_tx)(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en);
3816 int (*h2c_dctl_sec_cam)(struct rtw89_dev *rtwdev,
3817 struct rtw89_vif_link *rtwvif_link,
3818 struct rtw89_sta_link *rtwsta_link);
3819 int (*h2c_default_cmac_tbl)(struct rtw89_dev *rtwdev,
3820 struct rtw89_vif_link *rtwvif_link,
3821 struct rtw89_sta_link *rtwsta_link);
3822 int (*h2c_assoc_cmac_tbl)(struct rtw89_dev *rtwdev,
3823 struct rtw89_vif_link *rtwvif_link,
3824 struct rtw89_sta_link *rtwsta_link);
3825 int (*h2c_ampdu_cmac_tbl)(struct rtw89_dev *rtwdev,
3826 struct rtw89_vif_link *rtwvif_link,
3827 struct rtw89_sta_link *rtwsta_link);
3828 int (*h2c_txtime_cmac_tbl)(struct rtw89_dev *rtwdev,
3829 struct rtw89_sta_link *rtwsta_link);
3830 int (*h2c_punctured_cmac_tbl)(struct rtw89_dev *rtwdev,
3831 struct rtw89_vif_link *rtwvif_link,
3832 u16 punctured);
3833 int (*h2c_default_dmac_tbl)(struct rtw89_dev *rtwdev,
3834 struct rtw89_vif_link *rtwvif_link,
3835 struct rtw89_sta_link *rtwsta_link);
3836 int (*h2c_update_beacon)(struct rtw89_dev *rtwdev,
3837 struct rtw89_vif_link *rtwvif_link);
3838 int (*h2c_ba_cam)(struct rtw89_dev *rtwdev,
3839 struct rtw89_vif_link *rtwvif_link,
3840 struct rtw89_sta_link *rtwsta_link,
3841 bool valid, struct ieee80211_ampdu_params *params);
3842
3843 void (*btc_set_rfe)(struct rtw89_dev *rtwdev);
3844 void (*btc_init_cfg)(struct rtw89_dev *rtwdev);
3845 void (*btc_set_wl_pri)(struct rtw89_dev *rtwdev, u8 map, bool state);
3846 void (*btc_set_wl_txpwr_ctrl)(struct rtw89_dev *rtwdev, u32 txpwr_val);
3847 s8 (*btc_get_bt_rssi)(struct rtw89_dev *rtwdev, s8 val);
3848 void (*btc_update_bt_cnt)(struct rtw89_dev *rtwdev);
3849 void (*btc_wl_s1_standby)(struct rtw89_dev *rtwdev, bool state);
3850 void (*btc_set_policy)(struct rtw89_dev *rtwdev, u16 policy_type);
3851 void (*btc_set_wl_rx_gain)(struct rtw89_dev *rtwdev, u32 level);
3852 };
3853
3854 enum rtw89_dma_ch {
3855 RTW89_DMA_ACH0 = 0,
3856 RTW89_DMA_ACH1 = 1,
3857 RTW89_DMA_ACH2 = 2,
3858 RTW89_DMA_ACH3 = 3,
3859 RTW89_DMA_ACH4 = 4,
3860 RTW89_DMA_ACH5 = 5,
3861 RTW89_DMA_ACH6 = 6,
3862 RTW89_DMA_ACH7 = 7,
3863 RTW89_DMA_B0MG = 8,
3864 RTW89_DMA_B0HI = 9,
3865 RTW89_DMA_B1MG = 10,
3866 RTW89_DMA_B1HI = 11,
3867 RTW89_DMA_H2C = 12,
3868 RTW89_DMA_CH_NUM = 13
3869 };
3870
3871 #define MLO_MODE_FOR_BB0_BB1_RF(bb0, bb1, rf) ((rf) << 12 | (bb1) << 4 | (bb0))
3872
3873 enum rtw89_mlo_dbcc_mode {
3874 MLO_DBCC_NOT_SUPPORT = 1,
3875 MLO_0_PLUS_2_1RF = MLO_MODE_FOR_BB0_BB1_RF(0, 2, 1),
3876 MLO_0_PLUS_2_2RF = MLO_MODE_FOR_BB0_BB1_RF(0, 2, 2),
3877 MLO_1_PLUS_1_1RF = MLO_MODE_FOR_BB0_BB1_RF(1, 1, 1),
3878 MLO_1_PLUS_1_2RF = MLO_MODE_FOR_BB0_BB1_RF(1, 1, 2),
3879 MLO_2_PLUS_0_1RF = MLO_MODE_FOR_BB0_BB1_RF(2, 0, 1),
3880 MLO_2_PLUS_0_2RF = MLO_MODE_FOR_BB0_BB1_RF(2, 0, 2),
3881 MLO_2_PLUS_2_2RF = MLO_MODE_FOR_BB0_BB1_RF(2, 2, 2),
3882 DBCC_LEGACY = 0xffffffff,
3883 };
3884
3885 enum rtw89_scan_be_operation {
3886 RTW89_SCAN_OP_STOP,
3887 RTW89_SCAN_OP_START,
3888 RTW89_SCAN_OP_SETPARM,
3889 RTW89_SCAN_OP_GETRPT,
3890 RTW89_SCAN_OP_NUM
3891 };
3892
3893 enum rtw89_scan_be_mode {
3894 RTW89_SCAN_MODE_SA,
3895 RTW89_SCAN_MODE_MACC,
3896 RTW89_SCAN_MODE_NUM
3897 };
3898
3899 enum rtw89_scan_be_opmode {
3900 RTW89_SCAN_OPMODE_NONE,
3901 RTW89_SCAN_OPMODE_TBTT,
3902 RTW89_SCAN_OPMODE_INTV,
3903 RTW89_SCAN_OPMODE_CNT,
3904 RTW89_SCAN_OPMODE_NUM,
3905 };
3906
3907 struct rtw89_scan_option {
3908 bool enable;
3909 bool target_ch_mode;
3910 u8 num_macc_role;
3911 u8 num_opch;
3912 u8 repeat;
3913 u16 norm_pd;
3914 u16 slow_pd;
3915 u16 norm_cy;
3916 u8 opch_end;
3917 u16 delay; /* in unit of ms */
3918 u64 prohib_chan;
3919 enum rtw89_phy_idx band;
3920 enum rtw89_scan_be_operation operation;
3921 enum rtw89_scan_be_mode scan_mode;
3922 enum rtw89_mlo_dbcc_mode mlo_mode;
3923 };
3924
3925 enum rtw89_qta_mode {
3926 RTW89_QTA_SCC,
3927 RTW89_QTA_DBCC,
3928 RTW89_QTA_DLFW,
3929 RTW89_QTA_WOW,
3930
3931 /* keep last */
3932 RTW89_QTA_INVALID,
3933 };
3934
3935 struct rtw89_hfc_ch_cfg {
3936 u16 min;
3937 u16 max;
3938 #define grp_0 0
3939 #define grp_1 1
3940 #define grp_num 2
3941 u8 grp;
3942 };
3943
3944 struct rtw89_hfc_ch_info {
3945 u16 aval;
3946 u16 used;
3947 };
3948
3949 struct rtw89_hfc_pub_cfg {
3950 u16 grp0;
3951 u16 grp1;
3952 u16 pub_max;
3953 u16 wp_thrd;
3954 };
3955
3956 struct rtw89_hfc_pub_info {
3957 u16 g0_used;
3958 u16 g1_used;
3959 u16 g0_aval;
3960 u16 g1_aval;
3961 u16 pub_aval;
3962 u16 wp_aval;
3963 };
3964
3965 struct rtw89_hfc_prec_cfg {
3966 u16 ch011_prec;
3967 u16 h2c_prec;
3968 u16 wp_ch07_prec;
3969 u16 wp_ch811_prec;
3970 u8 ch011_full_cond;
3971 u8 h2c_full_cond;
3972 u8 wp_ch07_full_cond;
3973 u8 wp_ch811_full_cond;
3974 };
3975
3976 struct rtw89_hfc_param {
3977 bool en;
3978 bool h2c_en;
3979 u8 mode;
3980 const struct rtw89_hfc_ch_cfg *ch_cfg;
3981 struct rtw89_hfc_ch_info ch_info[RTW89_DMA_CH_NUM];
3982 struct rtw89_hfc_pub_cfg pub_cfg;
3983 struct rtw89_hfc_pub_info pub_info;
3984 struct rtw89_hfc_prec_cfg prec_cfg;
3985 };
3986
3987 struct rtw89_hfc_param_ini {
3988 const struct rtw89_hfc_ch_cfg *ch_cfg;
3989 const struct rtw89_hfc_pub_cfg *pub_cfg;
3990 const struct rtw89_hfc_prec_cfg *prec_cfg;
3991 u8 mode;
3992 };
3993
3994 struct rtw89_dle_size {
3995 u16 pge_size;
3996 u16 lnk_pge_num;
3997 u16 unlnk_pge_num;
3998 /* for WiFi 7 chips below */
3999 u32 srt_ofst;
4000 };
4001
4002 struct rtw89_wde_quota {
4003 u16 hif;
4004 u16 wcpu;
4005 u16 pkt_in;
4006 u16 cpu_io;
4007 };
4008
4009 struct rtw89_ple_quota {
4010 u16 cma0_tx;
4011 u16 cma1_tx;
4012 u16 c2h;
4013 u16 h2c;
4014 u16 wcpu;
4015 u16 mpdu_proc;
4016 u16 cma0_dma;
4017 u16 cma1_dma;
4018 u16 bb_rpt;
4019 u16 wd_rel;
4020 u16 cpu_io;
4021 u16 tx_rpt;
4022 /* for WiFi 7 chips below */
4023 u16 h2d;
4024 };
4025
4026 struct rtw89_rsvd_quota {
4027 u16 mpdu_info_tbl;
4028 u16 b0_csi;
4029 u16 b1_csi;
4030 u16 b0_lmr;
4031 u16 b1_lmr;
4032 u16 b0_ftm;
4033 u16 b1_ftm;
4034 u16 b0_smr;
4035 u16 b1_smr;
4036 u16 others;
4037 };
4038
4039 struct rtw89_dle_rsvd_size {
4040 u32 srt_ofst;
4041 u32 size;
4042 };
4043
4044 struct rtw89_dle_mem {
4045 enum rtw89_qta_mode mode;
4046 const struct rtw89_dle_size *wde_size;
4047 const struct rtw89_dle_size *ple_size;
4048 const struct rtw89_wde_quota *wde_min_qt;
4049 const struct rtw89_wde_quota *wde_max_qt;
4050 const struct rtw89_ple_quota *ple_min_qt;
4051 const struct rtw89_ple_quota *ple_max_qt;
4052 /* for WiFi 7 chips below */
4053 const struct rtw89_rsvd_quota *rsvd_qt;
4054 const struct rtw89_dle_rsvd_size *rsvd0_size;
4055 const struct rtw89_dle_rsvd_size *rsvd1_size;
4056 };
4057
4058 struct rtw89_reg_def {
4059 u32 addr;
4060 u32 mask;
4061 };
4062
4063 struct rtw89_reg2_def {
4064 u32 addr;
4065 u32 data;
4066 };
4067
4068 struct rtw89_reg3_def {
4069 u32 addr;
4070 u32 mask;
4071 u32 data;
4072 };
4073
4074 struct rtw89_reg5_def {
4075 u8 flag; /* recognized by parsers */
4076 u8 path;
4077 u32 addr;
4078 u32 mask;
4079 u32 data;
4080 };
4081
4082 struct rtw89_reg_imr {
4083 u32 addr;
4084 u32 clr;
4085 u32 set;
4086 };
4087
4088 struct rtw89_phy_table {
4089 const struct rtw89_reg2_def *regs;
4090 u32 n_regs;
4091 enum rtw89_rf_path rf_path;
4092 void (*config)(struct rtw89_dev *rtwdev, const struct rtw89_reg2_def *reg,
4093 enum rtw89_rf_path rf_path, void *data);
4094 };
4095
4096 struct rtw89_txpwr_table {
4097 const void *data;
4098 u32 size;
4099 void (*load)(struct rtw89_dev *rtwdev,
4100 const struct rtw89_txpwr_table *tbl);
4101 };
4102
4103 struct rtw89_txpwr_rule_2ghz {
4104 const s8 (*lmt)[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
4105 [RTW89_RS_LMT_NUM][RTW89_BF_NUM]
4106 [RTW89_REGD_NUM][RTW89_2G_CH_NUM];
4107 const s8 (*lmt_ru)[RTW89_RU_NUM][RTW89_NTX_NUM]
4108 [RTW89_REGD_NUM][RTW89_2G_CH_NUM];
4109 };
4110
4111 struct rtw89_txpwr_rule_5ghz {
4112 const s8 (*lmt)[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
4113 [RTW89_RS_LMT_NUM][RTW89_BF_NUM]
4114 [RTW89_REGD_NUM][RTW89_5G_CH_NUM];
4115 const s8 (*lmt_ru)[RTW89_RU_NUM][RTW89_NTX_NUM]
4116 [RTW89_REGD_NUM][RTW89_5G_CH_NUM];
4117 };
4118
4119 struct rtw89_txpwr_rule_6ghz {
4120 const s8 (*lmt)[RTW89_6G_BW_NUM][RTW89_NTX_NUM]
4121 [RTW89_RS_LMT_NUM][RTW89_BF_NUM]
4122 [RTW89_REGD_NUM][NUM_OF_RTW89_REG_6GHZ_POWER]
4123 [RTW89_6G_CH_NUM];
4124 const s8 (*lmt_ru)[RTW89_RU_NUM][RTW89_NTX_NUM]
4125 [RTW89_REGD_NUM][NUM_OF_RTW89_REG_6GHZ_POWER]
4126 [RTW89_6G_CH_NUM];
4127 };
4128
4129 struct rtw89_tx_shape {
4130 const u8 (*lmt)[RTW89_BAND_NUM][RTW89_RS_TX_SHAPE_NUM][RTW89_REGD_NUM];
4131 const u8 (*lmt_ru)[RTW89_BAND_NUM][RTW89_REGD_NUM];
4132 };
4133
4134 struct rtw89_rfe_parms {
4135 const struct rtw89_txpwr_table *byr_tbl;
4136 struct rtw89_txpwr_rule_2ghz rule_2ghz;
4137 struct rtw89_txpwr_rule_5ghz rule_5ghz;
4138 struct rtw89_txpwr_rule_6ghz rule_6ghz;
4139 struct rtw89_txpwr_rule_2ghz rule_da_2ghz;
4140 struct rtw89_txpwr_rule_5ghz rule_da_5ghz;
4141 struct rtw89_txpwr_rule_6ghz rule_da_6ghz;
4142 struct rtw89_tx_shape tx_shape;
4143 bool has_da;
4144 };
4145
4146 struct rtw89_rfe_parms_conf {
4147 const struct rtw89_rfe_parms *rfe_parms;
4148 u8 rfe_type;
4149 };
4150
4151 #define RTW89_TXPWR_CONF_DFLT_RFE_TYPE 0x0
4152
4153 struct rtw89_txpwr_conf {
4154 u8 rfe_type;
4155 u8 ent_sz;
4156 u32 num_ents;
4157 const void *data;
4158 };
4159
rtw89_txpwr_entcpy(void * entry,const void * cursor,u8 size,const struct rtw89_txpwr_conf * conf)4160 static inline bool rtw89_txpwr_entcpy(void *entry, const void *cursor, u8 size,
4161 const struct rtw89_txpwr_conf *conf)
4162 {
4163 u8 valid_size = min(size, conf->ent_sz);
4164
4165 memcpy(entry, cursor, valid_size);
4166 return true;
4167 }
4168
4169 #define rtw89_txpwr_conf_valid(conf) (!!(conf)->data)
4170
4171 #if defined(__linux__)
4172 #define rtw89_for_each_in_txpwr_conf(entry, cursor, conf) \
4173 for (typecheck(const void *, cursor), (cursor) = (conf)->data; \
4174 (cursor) < (conf)->data + (conf)->num_ents * (conf)->ent_sz; \
4175 (cursor) += (conf)->ent_sz) \
4176 if (rtw89_txpwr_entcpy(&(entry), cursor, sizeof(entry), conf))
4177 #elif defined(__FreeBSD__)
4178 #define rtw89_for_each_in_txpwr_conf(entry, cursor, conf) \
4179 for (typecheck(const u8 *, cursor), (cursor) = (conf)->data, \
4180 memcpy(&(entry), cursor, \
4181 min_t(u8, sizeof(entry), (conf)->ent_sz)); \
4182 (cursor) < (const u8 *)(conf)->data + (conf)->num_ents * (conf)->ent_sz; \
4183 (cursor) += (conf)->ent_sz) \
4184 if (rtw89_txpwr_entcpy(&(entry), cursor, sizeof(entry), conf))
4185 #endif
4186
4187 struct rtw89_txpwr_byrate_data {
4188 struct rtw89_txpwr_conf conf;
4189 struct rtw89_txpwr_table tbl;
4190 };
4191
4192 struct rtw89_txpwr_lmt_2ghz_data {
4193 struct rtw89_txpwr_conf conf;
4194 s8 v[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
4195 [RTW89_RS_LMT_NUM][RTW89_BF_NUM]
4196 [RTW89_REGD_NUM][RTW89_2G_CH_NUM];
4197 };
4198
4199 struct rtw89_txpwr_lmt_5ghz_data {
4200 struct rtw89_txpwr_conf conf;
4201 s8 v[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
4202 [RTW89_RS_LMT_NUM][RTW89_BF_NUM]
4203 [RTW89_REGD_NUM][RTW89_5G_CH_NUM];
4204 };
4205
4206 struct rtw89_txpwr_lmt_6ghz_data {
4207 struct rtw89_txpwr_conf conf;
4208 s8 v[RTW89_6G_BW_NUM][RTW89_NTX_NUM]
4209 [RTW89_RS_LMT_NUM][RTW89_BF_NUM]
4210 [RTW89_REGD_NUM][NUM_OF_RTW89_REG_6GHZ_POWER]
4211 [RTW89_6G_CH_NUM];
4212 };
4213
4214 struct rtw89_txpwr_lmt_ru_2ghz_data {
4215 struct rtw89_txpwr_conf conf;
4216 s8 v[RTW89_RU_NUM][RTW89_NTX_NUM]
4217 [RTW89_REGD_NUM][RTW89_2G_CH_NUM];
4218 };
4219
4220 struct rtw89_txpwr_lmt_ru_5ghz_data {
4221 struct rtw89_txpwr_conf conf;
4222 s8 v[RTW89_RU_NUM][RTW89_NTX_NUM]
4223 [RTW89_REGD_NUM][RTW89_5G_CH_NUM];
4224 };
4225
4226 struct rtw89_txpwr_lmt_ru_6ghz_data {
4227 struct rtw89_txpwr_conf conf;
4228 s8 v[RTW89_RU_NUM][RTW89_NTX_NUM]
4229 [RTW89_REGD_NUM][NUM_OF_RTW89_REG_6GHZ_POWER]
4230 [RTW89_6G_CH_NUM];
4231 };
4232
4233 struct rtw89_tx_shape_lmt_data {
4234 struct rtw89_txpwr_conf conf;
4235 u8 v[RTW89_BAND_NUM][RTW89_RS_TX_SHAPE_NUM][RTW89_REGD_NUM];
4236 };
4237
4238 struct rtw89_tx_shape_lmt_ru_data {
4239 struct rtw89_txpwr_conf conf;
4240 u8 v[RTW89_BAND_NUM][RTW89_REGD_NUM];
4241 };
4242
4243 struct rtw89_rfe_data {
4244 struct rtw89_txpwr_byrate_data byrate;
4245 struct rtw89_txpwr_lmt_2ghz_data lmt_2ghz;
4246 struct rtw89_txpwr_lmt_5ghz_data lmt_5ghz;
4247 struct rtw89_txpwr_lmt_6ghz_data lmt_6ghz;
4248 struct rtw89_txpwr_lmt_2ghz_data da_lmt_2ghz;
4249 struct rtw89_txpwr_lmt_5ghz_data da_lmt_5ghz;
4250 struct rtw89_txpwr_lmt_6ghz_data da_lmt_6ghz;
4251 struct rtw89_txpwr_lmt_ru_2ghz_data lmt_ru_2ghz;
4252 struct rtw89_txpwr_lmt_ru_5ghz_data lmt_ru_5ghz;
4253 struct rtw89_txpwr_lmt_ru_6ghz_data lmt_ru_6ghz;
4254 struct rtw89_txpwr_lmt_ru_2ghz_data da_lmt_ru_2ghz;
4255 struct rtw89_txpwr_lmt_ru_5ghz_data da_lmt_ru_5ghz;
4256 struct rtw89_txpwr_lmt_ru_6ghz_data da_lmt_ru_6ghz;
4257 struct rtw89_tx_shape_lmt_data tx_shape_lmt;
4258 struct rtw89_tx_shape_lmt_ru_data tx_shape_lmt_ru;
4259 struct rtw89_rfe_parms rfe_parms;
4260 };
4261
4262 struct rtw89_page_regs {
4263 u32 hci_fc_ctrl;
4264 u32 ch_page_ctrl;
4265 u32 ach_page_ctrl;
4266 u32 ach_page_info;
4267 u32 pub_page_info3;
4268 u32 pub_page_ctrl1;
4269 u32 pub_page_ctrl2;
4270 u32 pub_page_info1;
4271 u32 pub_page_info2;
4272 u32 wp_page_ctrl1;
4273 u32 wp_page_ctrl2;
4274 u32 wp_page_info1;
4275 };
4276
4277 struct rtw89_imr_info {
4278 u32 wdrls_imr_set;
4279 u32 wsec_imr_reg;
4280 u32 wsec_imr_set;
4281 u32 mpdu_tx_imr_set;
4282 u32 mpdu_rx_imr_set;
4283 u32 sta_sch_imr_set;
4284 u32 txpktctl_imr_b0_reg;
4285 u32 txpktctl_imr_b0_clr;
4286 u32 txpktctl_imr_b0_set;
4287 u32 txpktctl_imr_b1_reg;
4288 u32 txpktctl_imr_b1_clr;
4289 u32 txpktctl_imr_b1_set;
4290 u32 wde_imr_clr;
4291 u32 wde_imr_set;
4292 u32 ple_imr_clr;
4293 u32 ple_imr_set;
4294 u32 host_disp_imr_clr;
4295 u32 host_disp_imr_set;
4296 u32 cpu_disp_imr_clr;
4297 u32 cpu_disp_imr_set;
4298 u32 other_disp_imr_clr;
4299 u32 other_disp_imr_set;
4300 u32 bbrpt_com_err_imr_reg;
4301 u32 bbrpt_chinfo_err_imr_reg;
4302 u32 bbrpt_err_imr_set;
4303 u32 bbrpt_dfs_err_imr_reg;
4304 u32 ptcl_imr_clr;
4305 u32 ptcl_imr_set;
4306 u32 cdma_imr_0_reg;
4307 u32 cdma_imr_0_clr;
4308 u32 cdma_imr_0_set;
4309 u32 cdma_imr_1_reg;
4310 u32 cdma_imr_1_clr;
4311 u32 cdma_imr_1_set;
4312 u32 phy_intf_imr_reg;
4313 u32 phy_intf_imr_clr;
4314 u32 phy_intf_imr_set;
4315 u32 rmac_imr_reg;
4316 u32 rmac_imr_clr;
4317 u32 rmac_imr_set;
4318 u32 tmac_imr_reg;
4319 u32 tmac_imr_clr;
4320 u32 tmac_imr_set;
4321 };
4322
4323 struct rtw89_imr_table {
4324 const struct rtw89_reg_imr *regs;
4325 u32 n_regs;
4326 };
4327
4328 struct rtw89_xtal_info {
4329 u32 xcap_reg;
4330 u32 sc_xo_mask;
4331 u32 sc_xi_mask;
4332 };
4333
4334 struct rtw89_rrsr_cfgs {
4335 struct rtw89_reg3_def ref_rate;
4336 struct rtw89_reg3_def rsc;
4337 };
4338
4339 struct rtw89_rfkill_regs {
4340 struct rtw89_reg3_def pinmux;
4341 struct rtw89_reg3_def mode;
4342 };
4343
4344 struct rtw89_dig_regs {
4345 u32 seg0_pd_reg;
4346 u32 pd_lower_bound_mask;
4347 u32 pd_spatial_reuse_en;
4348 u32 bmode_pd_reg;
4349 u32 bmode_cca_rssi_limit_en;
4350 u32 bmode_pd_lower_bound_reg;
4351 u32 bmode_rssi_nocca_low_th_mask;
4352 struct rtw89_reg_def p0_lna_init;
4353 struct rtw89_reg_def p1_lna_init;
4354 struct rtw89_reg_def p0_tia_init;
4355 struct rtw89_reg_def p1_tia_init;
4356 struct rtw89_reg_def p0_rxb_init;
4357 struct rtw89_reg_def p1_rxb_init;
4358 struct rtw89_reg_def p0_p20_pagcugc_en;
4359 struct rtw89_reg_def p0_s20_pagcugc_en;
4360 struct rtw89_reg_def p1_p20_pagcugc_en;
4361 struct rtw89_reg_def p1_s20_pagcugc_en;
4362 };
4363
4364 struct rtw89_edcca_regs {
4365 u32 edcca_level;
4366 u32 edcca_mask;
4367 u32 edcca_p_mask;
4368 u32 ppdu_level;
4369 u32 ppdu_mask;
4370 struct rtw89_edcca_p_regs {
4371 u32 rpt_a;
4372 u32 rpt_b;
4373 u32 rpt_sel;
4374 u32 rpt_sel_mask;
4375 } p[RTW89_PHY_NUM];
4376 u32 rpt_sel_be;
4377 u32 rpt_sel_be_mask;
4378 u32 tx_collision_t2r_st;
4379 u32 tx_collision_t2r_st_mask;
4380 };
4381
4382 struct rtw89_phy_ul_tb_info {
4383 bool dyn_tb_tri_en;
4384 u8 def_if_bandedge;
4385 };
4386
4387 struct rtw89_antdiv_stats {
4388 struct ewma_rssi cck_rssi_avg;
4389 struct ewma_rssi ofdm_rssi_avg;
4390 struct ewma_rssi non_legacy_rssi_avg;
4391 u16 pkt_cnt_cck;
4392 u16 pkt_cnt_ofdm;
4393 u16 pkt_cnt_non_legacy;
4394 u32 evm;
4395 };
4396
4397 struct rtw89_antdiv_info {
4398 struct rtw89_antdiv_stats target_stats;
4399 struct rtw89_antdiv_stats main_stats;
4400 struct rtw89_antdiv_stats aux_stats;
4401 u8 training_count;
4402 u8 rssi_pre;
4403 bool get_stats;
4404 };
4405
4406 enum rtw89_chanctx_state {
4407 RTW89_CHANCTX_STATE_MCC_START,
4408 RTW89_CHANCTX_STATE_MCC_STOP,
4409 };
4410
4411 enum rtw89_chanctx_callbacks {
4412 RTW89_CHANCTX_CALLBACK_PLACEHOLDER,
4413 RTW89_CHANCTX_CALLBACK_RFK,
4414 RTW89_CHANCTX_CALLBACK_TAS,
4415
4416 NUM_OF_RTW89_CHANCTX_CALLBACKS,
4417 };
4418
4419 struct rtw89_chanctx_listener {
4420 void (*callbacks[NUM_OF_RTW89_CHANCTX_CALLBACKS])
4421 (struct rtw89_dev *rtwdev, enum rtw89_chanctx_state state);
4422 };
4423
4424 #define RTW89_NHM_TH_NUM 11
4425 #define RTW89_NHM_RPT_NUM 12
4426
4427 struct rtw89_chip_info {
4428 enum rtw89_core_chip_id chip_id;
4429 enum rtw89_chip_gen chip_gen;
4430 const struct rtw89_chip_ops *ops;
4431 const struct rtw89_mac_gen_def *mac_def;
4432 const struct rtw89_phy_gen_def *phy_def;
4433 const char *fw_basename;
4434 u8 fw_format_max;
4435 bool try_ce_fw;
4436 u8 bbmcu_nr;
4437 u32 needed_fw_elms;
4438 const struct rtw89_fw_blacklist *fw_blacklist;
4439 u32 fifo_size;
4440 bool small_fifo_size;
4441 u32 dle_scc_rsvd_size;
4442 u16 max_amsdu_limit;
4443 bool dis_2g_40m_ul_ofdma;
4444 u32 rsvd_ple_ofst;
4445 const struct rtw89_hfc_param_ini *hfc_param_ini[RTW89_HCI_TYPE_NUM];
4446 const struct rtw89_dle_mem *dle_mem[RTW89_HCI_DLE_TYPE_NUM];
4447 u8 wde_qempty_acq_grpnum;
4448 u8 wde_qempty_mgq_grpsel;
4449 u32 rf_base_addr[2];
4450 u8 thermal_th[2];
4451 u8 support_macid_num;
4452 u8 support_link_num;
4453 u8 support_chanctx_num;
4454 u8 support_bands;
4455 u16 support_bandwidths;
4456 bool support_unii4;
4457 bool support_rnr;
4458 bool support_ant_gain;
4459 bool support_tas;
4460 bool support_sar_by_ant;
4461 bool support_noise;
4462 bool ul_tb_waveform_ctrl;
4463 bool ul_tb_pwr_diff;
4464 bool rx_freq_frome_ie;
4465 bool hw_sec_hdr;
4466 bool hw_mgmt_tx_encrypt;
4467 bool hw_tkip_crypto;
4468 bool hw_mlo_bmc_crypto;
4469 u8 rf_path_num;
4470 u8 tx_nss;
4471 u8 rx_nss;
4472 u8 acam_num;
4473 u8 bcam_num;
4474 u8 scam_num;
4475 u8 bacam_num;
4476 u8 bacam_dynamic_num;
4477 enum rtw89_bacam_ver bacam_ver;
4478 u8 addrcam_ver;
4479 u8 ppdu_max_usr;
4480
4481 u8 sec_ctrl_efuse_size;
4482 u32 physical_efuse_size;
4483 u32 logical_efuse_size;
4484 u32 limit_efuse_size;
4485 u32 dav_phy_efuse_size;
4486 u32 dav_log_efuse_size;
4487 u32 phycap_addr;
4488 u32 phycap_size;
4489 const struct rtw89_efuse_block_cfg *efuse_blocks;
4490
4491 const struct rtw89_pwr_cfg * const *pwr_on_seq;
4492 const struct rtw89_pwr_cfg * const *pwr_off_seq;
4493 const struct rtw89_phy_table *bb_table;
4494 const struct rtw89_phy_table *bb_gain_table;
4495 const struct rtw89_phy_table *rf_table[RF_PATH_MAX];
4496 const struct rtw89_phy_table *nctl_table;
4497 const struct rtw89_rfk_tbl *nctl_post_table;
4498 const struct rtw89_phy_dig_gain_table *dig_table;
4499 const struct rtw89_dig_regs *dig_regs;
4500 const struct rtw89_phy_tssi_dbw_table *tssi_dbw_table;
4501
4502 /* NULL if no rfe-specific, or a null-terminated array by rfe_parms */
4503 const struct rtw89_rfe_parms_conf *rfe_parms_conf;
4504 const struct rtw89_rfe_parms *dflt_parms;
4505 const struct rtw89_chanctx_listener *chanctx_listener;
4506
4507 u8 txpwr_factor_bb;
4508 u8 txpwr_factor_rf;
4509 u8 txpwr_factor_mac;
4510
4511 u32 para_ver;
4512 u32 wlcx_desired;
4513 u8 scbd;
4514 u8 mailbox;
4515
4516 u8 afh_guard_ch;
4517 const u8 *wl_rssi_thres;
4518 const u8 *bt_rssi_thres;
4519 u8 rssi_tol;
4520
4521 u8 mon_reg_num;
4522 const struct rtw89_btc_fbtc_mreg *mon_reg;
4523 u8 rf_para_ulink_num;
4524 const struct rtw89_btc_rf_trx_para *rf_para_ulink;
4525 u8 rf_para_dlink_num;
4526 const struct rtw89_btc_rf_trx_para *rf_para_dlink;
4527 u8 ps_mode_supported;
4528 u8 low_power_hci_modes;
4529
4530 u32 h2c_cctl_func_id;
4531 u32 hci_func_en_addr;
4532 u32 h2c_desc_size;
4533 u32 txwd_body_size;
4534 u32 txwd_info_size;
4535 u32 h2c_ctrl_reg;
4536 const u32 *h2c_regs;
4537 struct rtw89_reg_def h2c_counter_reg;
4538 u32 c2h_ctrl_reg;
4539 const u32 *c2h_regs;
4540 struct rtw89_reg_def c2h_counter_reg;
4541 const struct rtw89_page_regs *page_regs;
4542 const u32 *wow_reason_reg;
4543 bool cfo_src_fd;
4544 bool cfo_hw_comp;
4545 const struct rtw89_reg_def *dcfo_comp;
4546 u8 dcfo_comp_sft;
4547 const struct rtw89_reg_def (*nhm_report)[RTW89_NHM_RPT_NUM];
4548 const struct rtw89_reg_def (*nhm_th)[RTW89_NHM_TH_NUM];
4549 const struct rtw89_imr_info *imr_info;
4550 const struct rtw89_imr_table *imr_dmac_table;
4551 const struct rtw89_imr_table *imr_cmac_table;
4552 const struct rtw89_rrsr_cfgs *rrsr_cfgs;
4553 struct rtw89_reg_def bss_clr_vld;
4554 u32 bss_clr_map_reg;
4555 const struct rtw89_rfkill_regs *rfkill_init;
4556 struct rtw89_reg_def rfkill_get;
4557 u32 dma_ch_mask;
4558 const struct rtw89_edcca_regs *edcca_regs;
4559 const struct wiphy_wowlan_support *wowlan_stub;
4560 const struct rtw89_xtal_info *xtal_info;
4561 };
4562
4563 struct rtw89_chip_variant {
4564 bool no_mcs_12_13: 1;
4565 u32 fw_min_ver_code;
4566 };
4567
4568 union rtw89_bus_info {
4569 const struct rtw89_pci_info *pci;
4570 const struct rtw89_usb_info *usb;
4571 };
4572
4573 struct rtw89_driver_info {
4574 const struct rtw89_chip_info *chip;
4575 const struct rtw89_chip_variant *variant;
4576 const struct dmi_system_id *quirks;
4577 union rtw89_bus_info bus;
4578 };
4579
4580 enum rtw89_hcifc_mode {
4581 RTW89_HCIFC_POH = 0,
4582 RTW89_HCIFC_STF = 1,
4583 RTW89_HCIFC_SDIO = 2,
4584
4585 /* keep last */
4586 RTW89_HCIFC_MODE_INVALID,
4587 };
4588
4589 struct rtw89_dle_info {
4590 const struct rtw89_rsvd_quota *rsvd_qt;
4591 enum rtw89_qta_mode qta_mode;
4592 u16 ple_pg_size;
4593 u16 ple_free_pg;
4594 u16 c0_rx_qta;
4595 u16 c1_rx_qta;
4596 };
4597
4598 enum rtw89_host_rpr_mode {
4599 RTW89_RPR_MODE_POH = 0,
4600 RTW89_RPR_MODE_STF
4601 };
4602
4603 #define RTW89_COMPLETION_BUF_SIZE 40
4604 #define RTW89_WAIT_COND_IDLE UINT_MAX
4605
4606 struct rtw89_completion_data {
4607 bool err;
4608 u8 buf[RTW89_COMPLETION_BUF_SIZE];
4609 };
4610
4611 struct rtw89_wait_response {
4612 struct rcu_head rcu_head;
4613 struct completion completion;
4614 struct rtw89_completion_data data;
4615 };
4616
4617 struct rtw89_wait_info {
4618 atomic_t cond;
4619 struct rtw89_completion_data data;
4620 struct rtw89_wait_response __rcu *resp;
4621 };
4622
4623 #define RTW89_WAIT_FOR_COND_TIMEOUT msecs_to_jiffies(100)
4624
rtw89_init_wait(struct rtw89_wait_info * wait)4625 static inline void rtw89_init_wait(struct rtw89_wait_info *wait)
4626 {
4627 rcu_assign_pointer(wait->resp, NULL);
4628 atomic_set(&wait->cond, RTW89_WAIT_COND_IDLE);
4629 }
4630
4631 struct rtw89_mac_info {
4632 struct rtw89_dle_info dle_info;
4633 struct rtw89_hfc_param hfc_param;
4634 enum rtw89_qta_mode qta_mode;
4635 u8 rpwm_seq_num;
4636 u8 cpwm_seq_num;
4637
4638 /* see RTW89_FW_OFLD_WAIT_COND series for wait condition */
4639 struct rtw89_wait_info fw_ofld_wait;
4640 /* see RTW89_PS_WAIT_COND series for wait condition */
4641 struct rtw89_wait_info ps_wait;
4642 };
4643
4644 enum rtw89_fwdl_check_type {
4645 RTW89_FWDL_CHECK_FREERTOS_DONE,
4646 RTW89_FWDL_CHECK_WCPU_FWDL_DONE,
4647 RTW89_FWDL_CHECK_DCPU_FWDL_DONE,
4648 RTW89_FWDL_CHECK_BB0_FWDL_DONE,
4649 RTW89_FWDL_CHECK_BB1_FWDL_DONE,
4650 };
4651
4652 enum rtw89_fw_type {
4653 RTW89_FW_NORMAL = 1,
4654 RTW89_FW_WOWLAN = 3,
4655 RTW89_FW_NORMAL_CE = 5,
4656 RTW89_FW_BBMCU0 = 64,
4657 RTW89_FW_BBMCU1 = 65,
4658 RTW89_FW_LOGFMT = 255,
4659 };
4660
4661 #define RTW89_FW_FEATURE_GROUP(_grp, _features...) \
4662 RTW89_FW_FEATURE_##_grp##_MIN, \
4663 __RTW89_FW_FEATURE_##_grp##_S = RTW89_FW_FEATURE_##_grp##_MIN - 1, \
4664 _features \
4665 __RTW89_FW_FEATURE_##_grp##_E, \
4666 RTW89_FW_FEATURE_##_grp##_MAX = __RTW89_FW_FEATURE_##_grp##_E - 1
4667
4668 enum rtw89_fw_feature {
4669 RTW89_FW_FEATURE_OLD_HT_RA_FORMAT,
4670 RTW89_FW_FEATURE_SCAN_OFFLOAD,
4671 RTW89_FW_FEATURE_TX_WAKE,
4672 RTW89_FW_FEATURE_GROUP(CRASH_TRIGGER,
4673 RTW89_FW_FEATURE_CRASH_TRIGGER_TYPE_0,
4674 RTW89_FW_FEATURE_CRASH_TRIGGER_TYPE_1,
4675 ),
4676 RTW89_FW_FEATURE_NO_PACKET_DROP,
4677 RTW89_FW_FEATURE_NO_DEEP_PS,
4678 RTW89_FW_FEATURE_NO_LPS_PG,
4679 RTW89_FW_FEATURE_BEACON_FILTER,
4680 RTW89_FW_FEATURE_MACID_PAUSE_SLEEP,
4681 RTW89_FW_FEATURE_SCAN_OFFLOAD_BE_V0,
4682 RTW89_FW_FEATURE_WOW_REASON_V1,
4683 RTW89_FW_FEATURE_RFK_PRE_NOTIFY_V0,
4684 RTW89_FW_FEATURE_RFK_PRE_NOTIFY_V1,
4685 RTW89_FW_FEATURE_RFK_RXDCK_V0,
4686 RTW89_FW_FEATURE_RFK_IQK_V0,
4687 RTW89_FW_FEATURE_NO_WOW_CPU_IO_RX,
4688 RTW89_FW_FEATURE_NOTIFY_AP_INFO,
4689 RTW89_FW_FEATURE_CH_INFO_BE_V0,
4690 RTW89_FW_FEATURE_LPS_CH_INFO,
4691 RTW89_FW_FEATURE_NO_PHYCAP_P1,
4692 RTW89_FW_FEATURE_NO_POWER_DIFFERENCE,
4693 RTW89_FW_FEATURE_BEACON_LOSS_COUNT_V1,
4694 RTW89_FW_FEATURE_SCAN_OFFLOAD_EXTRA_OP,
4695 RTW89_FW_FEATURE_RFK_NTFY_MCC_V0,
4696 RTW89_FW_FEATURE_LPS_DACK_BY_C2H_REG,
4697 RTW89_FW_FEATURE_BEACON_TRACKING,
4698 RTW89_FW_FEATURE_ADDR_CAM_V0,
4699 };
4700
4701 struct rtw89_fw_suit {
4702 enum rtw89_fw_type type;
4703 const u8 *data;
4704 u32 size;
4705 u8 major_ver;
4706 u8 minor_ver;
4707 u8 sub_ver;
4708 u8 sub_idex;
4709 u16 build_year;
4710 u16 build_mon;
4711 u16 build_date;
4712 u16 build_hour;
4713 u16 build_min;
4714 u8 cmd_ver;
4715 u8 hdr_ver;
4716 u32 commitid;
4717 };
4718
4719 #define RTW89_FW_VER_CODE(major, minor, sub, idx) \
4720 (((major) << 24) | ((minor) << 16) | ((sub) << 8) | (idx))
4721 #define RTW89_FW_SUIT_VER_CODE(s) \
4722 RTW89_FW_VER_CODE((s)->major_ver, (s)->minor_ver, (s)->sub_ver, (s)->sub_idex)
4723
4724 #define RTW89_MFW_HDR_VER_CODE(mfw_hdr) \
4725 RTW89_FW_VER_CODE((mfw_hdr)->ver.major, \
4726 (mfw_hdr)->ver.minor, \
4727 (mfw_hdr)->ver.sub, \
4728 (mfw_hdr)->ver.idx)
4729
4730 #define RTW89_FW_HDR_VER_CODE(fw_hdr) \
4731 RTW89_FW_VER_CODE(le32_get_bits((fw_hdr)->w1, FW_HDR_W1_MAJOR_VERSION), \
4732 le32_get_bits((fw_hdr)->w1, FW_HDR_W1_MINOR_VERSION), \
4733 le32_get_bits((fw_hdr)->w1, FW_HDR_W1_SUBVERSION), \
4734 le32_get_bits((fw_hdr)->w1, FW_HDR_W1_SUBINDEX))
4735
4736 struct rtw89_fw_req_info {
4737 const struct firmware *firmware;
4738 struct completion completion;
4739 };
4740
4741 struct rtw89_fw_log {
4742 struct rtw89_fw_suit suit;
4743 bool enable;
4744 u32 last_fmt_id;
4745 u32 fmt_count;
4746 const __le32 *fmt_ids;
4747 const char *(*fmts)[];
4748 };
4749
4750 struct rtw89_fw_elm_info {
4751 struct rtw89_phy_table *bb_tbl;
4752 struct rtw89_phy_table *bb_gain;
4753 struct rtw89_phy_table *rf_radio[RF_PATH_MAX];
4754 struct rtw89_phy_table *rf_nctl;
4755 struct rtw89_fw_txpwr_track_cfg *txpwr_trk;
4756 struct rtw89_phy_rfk_log_fmt *rfk_log_fmt;
4757 const struct rtw89_regd_data *regd;
4758 const struct rtw89_fw_element_hdr *afe;
4759 const struct rtw89_fw_element_hdr *diag_mac;
4760 };
4761
4762 enum rtw89_fw_mss_dev_type {
4763 RTW89_FW_MSS_DEV_TYPE_FWSEC_DEF = 0xF,
4764 RTW89_FW_MSS_DEV_TYPE_FWSEC_INV = 0xFF,
4765 };
4766
4767 struct rtw89_fw_secure {
4768 bool secure_boot: 1;
4769 bool can_mss_v1: 1;
4770 bool can_mss_v0: 1;
4771 u32 sb_sel_mgn;
4772 u8 mss_dev_type;
4773 u8 mss_cust_idx;
4774 u8 mss_key_num;
4775 u8 mss_idx; /* v0 */
4776 };
4777
4778 struct rtw89_fw_info {
4779 struct rtw89_fw_req_info req;
4780 int fw_format;
4781 u8 h2c_seq;
4782 u8 rec_seq;
4783 u8 h2c_counter;
4784 u8 c2h_counter;
4785 struct rtw89_fw_suit normal;
4786 struct rtw89_fw_suit wowlan;
4787 struct rtw89_fw_suit bbmcu0;
4788 struct rtw89_fw_suit bbmcu1;
4789 struct rtw89_fw_log log;
4790 u32 feature_map;
4791 struct rtw89_fw_elm_info elm_info;
4792 struct rtw89_fw_secure sec;
4793 };
4794
4795 #define RTW89_CHK_FW_FEATURE(_feat, _fw) \
4796 (!!((_fw)->feature_map & BIT(RTW89_FW_FEATURE_ ## _feat)))
4797
4798 #define RTW89_CHK_FW_FEATURE_GROUP(_grp, _fw) \
4799 (!!((_fw)->feature_map & GENMASK(RTW89_FW_FEATURE_ ## _grp ## _MAX, \
4800 RTW89_FW_FEATURE_ ## _grp ## _MIN)))
4801
4802 #define RTW89_SET_FW_FEATURE(_fw_feature, _fw) \
4803 ((_fw)->feature_map |= BIT(_fw_feature))
4804
4805 struct rtw89_cam_info {
4806 DECLARE_BITMAP(addr_cam_map, RTW89_MAX_ADDR_CAM_NUM);
4807 DECLARE_BITMAP(bssid_cam_map, RTW89_MAX_BSSID_CAM_NUM);
4808 DECLARE_BITMAP(sec_cam_map, RTW89_MAX_SEC_CAM_NUM);
4809 DECLARE_BITMAP(ba_cam_map, RTW89_MAX_BA_CAM_NUM);
4810 struct rtw89_ba_cam_entry ba_cam_entry[RTW89_MAX_BA_CAM_NUM];
4811 const struct rtw89_sec_cam_entry *sec_entries[RTW89_MAX_SEC_CAM_NUM];
4812 };
4813
4814 enum rtw89_sar_sources {
4815 RTW89_SAR_SOURCE_NONE,
4816 RTW89_SAR_SOURCE_COMMON,
4817 RTW89_SAR_SOURCE_ACPI,
4818
4819 RTW89_SAR_SOURCE_NR,
4820 };
4821
4822 enum rtw89_sar_subband {
4823 RTW89_SAR_2GHZ_SUBBAND,
4824 RTW89_SAR_5GHZ_SUBBAND_1_2, /* U-NII-1 and U-NII-2 */
4825 RTW89_SAR_5GHZ_SUBBAND_2_E, /* U-NII-2-Extended */
4826 RTW89_SAR_5GHZ_SUBBAND_3_4, /* U-NII-3 and U-NII-4 */
4827 RTW89_SAR_6GHZ_SUBBAND_5_L, /* U-NII-5 lower part */
4828 RTW89_SAR_6GHZ_SUBBAND_5_H, /* U-NII-5 higher part */
4829 RTW89_SAR_6GHZ_SUBBAND_6, /* U-NII-6 */
4830 RTW89_SAR_6GHZ_SUBBAND_7_L, /* U-NII-7 lower part */
4831 RTW89_SAR_6GHZ_SUBBAND_7_H, /* U-NII-7 higher part */
4832 RTW89_SAR_6GHZ_SUBBAND_8, /* U-NII-8 */
4833
4834 RTW89_SAR_SUBBAND_NR,
4835 };
4836
4837 struct rtw89_sar_cfg_common {
4838 bool set[RTW89_SAR_SUBBAND_NR];
4839 s32 cfg[RTW89_SAR_SUBBAND_NR];
4840 };
4841
4842 enum rtw89_acpi_sar_subband {
4843 RTW89_ACPI_SAR_2GHZ_SUBBAND,
4844 RTW89_ACPI_SAR_5GHZ_SUBBAND_1, /* U-NII-1 */
4845 RTW89_ACPI_SAR_5GHZ_SUBBAND_2, /* U-NII-2 */
4846 RTW89_ACPI_SAR_5GHZ_SUBBAND_2E, /* U-NII-2-Extended */
4847 RTW89_ACPI_SAR_5GHZ_SUBBAND_3_4, /* U-NII-3 and U-NII-4 */
4848 RTW89_ACPI_SAR_6GHZ_SUBBAND_5_L, /* U-NII-5 lower part */
4849 RTW89_ACPI_SAR_6GHZ_SUBBAND_5_H, /* U-NII-5 higher part */
4850 RTW89_ACPI_SAR_6GHZ_SUBBAND_6, /* U-NII-6 */
4851 RTW89_ACPI_SAR_6GHZ_SUBBAND_7_L, /* U-NII-7 lower part */
4852 RTW89_ACPI_SAR_6GHZ_SUBBAND_7_H, /* U-NII-7 higher part */
4853 RTW89_ACPI_SAR_6GHZ_SUBBAND_8, /* U-NII-8 */
4854
4855 NUM_OF_RTW89_ACPI_SAR_SUBBAND,
4856 RTW89_ACPI_SAR_SUBBAND_NR_LEGACY = RTW89_ACPI_SAR_5GHZ_SUBBAND_3_4 + 1,
4857 RTW89_ACPI_SAR_SUBBAND_NR_HAS_6GHZ = RTW89_ACPI_SAR_6GHZ_SUBBAND_8 + 1,
4858 };
4859
4860 #define TXPWR_FACTOR_OF_RTW89_ACPI_SAR 3 /* unit: 0.125 dBm */
4861 #define MAX_VAL_OF_RTW89_ACPI_SAR S16_MAX
4862 #define MIN_VAL_OF_RTW89_ACPI_SAR S16_MIN
4863 #define MAX_NUM_OF_RTW89_ACPI_SAR_TBL 6
4864 #define NUM_OF_RTW89_ACPI_SAR_RF_PATH (RF_PATH_B + 1)
4865
4866 struct rtw89_sar_entry_from_acpi {
4867 s16 v[NUM_OF_RTW89_ACPI_SAR_SUBBAND][NUM_OF_RTW89_ACPI_SAR_RF_PATH];
4868 };
4869
4870 struct rtw89_sar_table_from_acpi {
4871 /* If this table is active, must fill all fields according to either
4872 * configuration in BIOS or some default values for SAR to work well.
4873 */
4874 struct rtw89_sar_entry_from_acpi entries[RTW89_REGD_NUM];
4875 };
4876
4877 struct rtw89_sar_indicator_from_acpi {
4878 bool enable_sync;
4879 unsigned int fields;
4880 u8 (*rfpath_to_antidx)(enum rtw89_rf_path rfpath);
4881
4882 /* Select among @tables of container, rtw89_sar_cfg_acpi, by path.
4883 * Not design with pointers since addresses will be invalid after
4884 * sync content with local container instance.
4885 */
4886 u8 tblsel[NUM_OF_RTW89_ACPI_SAR_RF_PATH];
4887 };
4888
4889 struct rtw89_sar_cfg_acpi {
4890 u8 downgrade_2tx;
4891 unsigned int valid_num;
4892 struct rtw89_sar_table_from_acpi tables[MAX_NUM_OF_RTW89_ACPI_SAR_TBL];
4893 struct rtw89_sar_indicator_from_acpi indicator;
4894 };
4895
4896 struct rtw89_sar_info {
4897 /* used to decide how to access SAR cfg union */
4898 enum rtw89_sar_sources src;
4899
4900 /* reserved for different knids of SAR cfg struct.
4901 * supposed that a single cfg struct cannot handle various SAR sources.
4902 */
4903 union {
4904 struct rtw89_sar_cfg_common cfg_common;
4905 struct rtw89_sar_cfg_acpi cfg_acpi;
4906 };
4907 };
4908
4909 enum rtw89_ant_gain_subband {
4910 RTW89_ANT_GAIN_2GHZ_SUBBAND,
4911 RTW89_ANT_GAIN_5GHZ_SUBBAND_1, /* U-NII-1 */
4912 RTW89_ANT_GAIN_5GHZ_SUBBAND_2, /* U-NII-2 */
4913 RTW89_ANT_GAIN_5GHZ_SUBBAND_2E, /* U-NII-2-Extended */
4914 RTW89_ANT_GAIN_5GHZ_SUBBAND_3_4, /* U-NII-3 and U-NII-4 */
4915 RTW89_ANT_GAIN_6GHZ_SUBBAND_5_L, /* U-NII-5 lower part */
4916 RTW89_ANT_GAIN_6GHZ_SUBBAND_5_H, /* U-NII-5 higher part */
4917 RTW89_ANT_GAIN_6GHZ_SUBBAND_6, /* U-NII-6 */
4918 RTW89_ANT_GAIN_6GHZ_SUBBAND_7_L, /* U-NII-7 lower part */
4919 RTW89_ANT_GAIN_6GHZ_SUBBAND_7_H, /* U-NII-7 higher part */
4920 RTW89_ANT_GAIN_6GHZ_SUBBAND_8, /* U-NII-8 */
4921
4922 RTW89_ANT_GAIN_SUBBAND_NR,
4923 };
4924
4925 enum rtw89_ant_gain_domain_type {
4926 RTW89_ANT_GAIN_ETSI = 0,
4927
4928 RTW89_ANT_GAIN_DOMAIN_NUM,
4929 };
4930
4931 #define RTW89_ANT_GAIN_CHAIN_NUM 2
4932 struct rtw89_ant_gain_info {
4933 s8 offset[RTW89_ANT_GAIN_CHAIN_NUM][RTW89_ANT_GAIN_SUBBAND_NR];
4934 u32 regd_enabled;
4935 bool block_country;
4936 };
4937
4938 struct rtw89_6ghz_span {
4939 enum rtw89_sar_subband sar_subband_low;
4940 enum rtw89_sar_subband sar_subband_high;
4941 enum rtw89_acpi_sar_subband acpi_sar_subband_low;
4942 enum rtw89_acpi_sar_subband acpi_sar_subband_high;
4943 enum rtw89_ant_gain_subband ant_gain_subband_low;
4944 enum rtw89_ant_gain_subband ant_gain_subband_high;
4945 };
4946
4947 #define RTW89_SAR_SPAN_VALID(span) ((span)->sar_subband_high)
4948 #define RTW89_ACPI_SAR_SPAN_VALID(span) ((span)->acpi_sar_subband_high)
4949 #define RTW89_ANT_GAIN_SPAN_VALID(span) ((span)->ant_gain_subband_high)
4950
4951 enum rtw89_tas_state {
4952 RTW89_TAS_STATE_DPR_OFF,
4953 RTW89_TAS_STATE_DPR_ON,
4954 RTW89_TAS_STATE_STATIC_SAR,
4955 };
4956
4957 #define RTW89_TAS_TX_RATIO_WINDOW 6
4958 #define RTW89_TAS_TXPWR_WINDOW 180
4959 struct rtw89_tas_info {
4960 u16 tx_ratio_history[RTW89_TAS_TX_RATIO_WINDOW];
4961 u64 txpwr_history[RTW89_TAS_TXPWR_WINDOW];
4962 u8 enabled_countries;
4963 u8 txpwr_head_idx;
4964 u8 txpwr_tail_idx;
4965 u8 tx_ratio_idx;
4966 u16 total_tx_ratio;
4967 u64 total_txpwr;
4968 u64 instant_txpwr;
4969 u32 window_size;
4970 s8 dpr_on_threshold;
4971 s8 dpr_off_threshold;
4972 enum rtw89_tas_state backup_state;
4973 enum rtw89_tas_state state;
4974 bool keep_history;
4975 bool block_regd;
4976 bool enable;
4977 bool pause;
4978 };
4979
4980 struct rtw89_chanctx_cfg {
4981 enum rtw89_chanctx_idx idx;
4982 int ref_count;
4983 };
4984
4985 enum rtw89_chanctx_changes {
4986 RTW89_CHANCTX_REMOTE_STA_CHANGE,
4987 RTW89_CHANCTX_BCN_OFFSET_CHANGE,
4988 RTW89_CHANCTX_P2P_PS_CHANGE,
4989 RTW89_CHANCTX_BT_SLOT_CHANGE,
4990 RTW89_CHANCTX_TSF32_TOGGLE_CHANGE,
4991
4992 NUM_OF_RTW89_CHANCTX_CHANGES,
4993 RTW89_CHANCTX_CHANGE_DFLT = NUM_OF_RTW89_CHANCTX_CHANGES,
4994 };
4995
4996 enum rtw89_entity_mode {
4997 RTW89_ENTITY_MODE_SCC_OR_SMLD,
4998 RTW89_ENTITY_MODE_MCC_PREPARE,
4999 RTW89_ENTITY_MODE_MCC,
5000
5001 NUM_OF_RTW89_ENTITY_MODE,
5002 RTW89_ENTITY_MODE_INVALID = -EINVAL,
5003 RTW89_ENTITY_MODE_UNHANDLED = -ESRCH,
5004 };
5005
5006 #define RTW89_MAX_INTERFACE_NUM 2
5007
5008 /* only valid when running with chanctx_ops */
5009 struct rtw89_entity_mgnt {
5010 struct list_head active_list;
5011 struct rtw89_vif *active_roles[RTW89_MAX_INTERFACE_NUM];
5012 enum rtw89_chanctx_idx chanctx_tbl[RTW89_MAX_INTERFACE_NUM]
5013 [__RTW89_MLD_MAX_LINK_NUM];
5014 };
5015
5016 struct rtw89_chanctx {
5017 struct cfg80211_chan_def chandef;
5018 struct rtw89_chan chan;
5019 struct rtw89_chan_rcd rcd;
5020
5021 /* only assigned when running with chanctx_ops */
5022 struct rtw89_chanctx_cfg *cfg;
5023 };
5024
5025 struct rtw89_edcca_bak {
5026 u8 a;
5027 u8 p;
5028 u8 ppdu;
5029 u8 th_old;
5030 };
5031
5032 enum rtw89_dm_type {
5033 RTW89_DM_DYNAMIC_EDCCA,
5034 RTW89_DM_THERMAL_PROTECT,
5035 RTW89_DM_TAS,
5036 RTW89_DM_MLO,
5037 };
5038
5039 #define RTW89_THERMAL_PROT_LV_MAX 5
5040 #define RTW89_THERMAL_PROT_STEP 5 /* -5% for each level */
5041
5042 struct rtw89_hal {
5043 u32 rx_fltr;
5044 u8 cv;
5045 u8 acv;
5046 u32 antenna_tx;
5047 u32 antenna_rx;
5048 u8 tx_nss;
5049 u8 rx_nss;
5050 bool tx_path_diversity;
5051 bool ant_diversity;
5052 bool ant_diversity_fixed;
5053 bool support_cckpd;
5054 bool support_igi;
5055 bool no_mcs_12_13;
5056
5057 atomic_t roc_chanctx_idx;
5058 u8 roc_link_index;
5059
5060 DECLARE_BITMAP(changes, NUM_OF_RTW89_CHANCTX_CHANGES);
5061 DECLARE_BITMAP(entity_map, NUM_OF_RTW89_CHANCTX);
5062 struct rtw89_chanctx chanctx[NUM_OF_RTW89_CHANCTX];
5063 struct cfg80211_chan_def roc_chandef;
5064
5065 bool entity_active[RTW89_PHY_NUM];
5066 bool entity_pause;
5067 enum rtw89_entity_mode entity_mode;
5068 struct rtw89_entity_mgnt entity_mgnt;
5069
5070 u32 disabled_dm_bitmap; /* bitmap of enum rtw89_dm_type */
5071
5072 u8 thermal_prot_th;
5073 u8 thermal_prot_lv; /* 0 ~ RTW89_THERMAL_PROT_LV_MAX */
5074 };
5075
5076 #define RTW89_MAX_MAC_ID_NUM 128
5077 #define RTW89_MAX_PKT_OFLD_NUM 255
5078
5079 enum rtw89_flags {
5080 RTW89_FLAG_POWERON,
5081 RTW89_FLAG_DMAC_FUNC,
5082 RTW89_FLAG_CMAC0_FUNC,
5083 RTW89_FLAG_CMAC1_FUNC,
5084 RTW89_FLAG_FW_RDY,
5085 RTW89_FLAG_RUNNING,
5086 RTW89_FLAG_PROBE_DONE,
5087 RTW89_FLAG_BFEE_MON,
5088 RTW89_FLAG_BFEE_EN,
5089 RTW89_FLAG_BFEE_TIMER_KEEP,
5090 RTW89_FLAG_NAPI_RUNNING,
5091 RTW89_FLAG_LEISURE_PS,
5092 RTW89_FLAG_LOW_POWER_MODE,
5093 RTW89_FLAG_INACTIVE_PS,
5094 RTW89_FLAG_CRASH_SIMULATING,
5095 RTW89_FLAG_SER_HANDLING,
5096 RTW89_FLAG_WOWLAN,
5097 RTW89_FLAG_FORBIDDEN_TRACK_WORK,
5098 RTW89_FLAG_CHANGING_INTERFACE,
5099 RTW89_FLAG_HW_RFKILL_STATE,
5100 RTW89_FLAG_UNPLUGGED,
5101
5102 NUM_OF_RTW89_FLAGS,
5103 };
5104
5105 enum rtw89_quirks {
5106 RTW89_QUIRK_PCI_BER,
5107 RTW89_QUIRK_THERMAL_PROT_120C,
5108 RTW89_QUIRK_THERMAL_PROT_110C,
5109
5110 NUM_OF_RTW89_QUIRKS,
5111 };
5112
5113 enum rtw89_custid {
5114 RTW89_CUSTID_NONE,
5115 RTW89_CUSTID_ACER,
5116 RTW89_CUSTID_AMD,
5117 RTW89_CUSTID_ASUS,
5118 RTW89_CUSTID_DELL,
5119 RTW89_CUSTID_HP,
5120 RTW89_CUSTID_LENOVO,
5121 };
5122
5123 enum rtw89_pkt_drop_sel {
5124 RTW89_PKT_DROP_SEL_MACID_BE_ONCE,
5125 RTW89_PKT_DROP_SEL_MACID_BK_ONCE,
5126 RTW89_PKT_DROP_SEL_MACID_VI_ONCE,
5127 RTW89_PKT_DROP_SEL_MACID_VO_ONCE,
5128 RTW89_PKT_DROP_SEL_MACID_ALL,
5129 RTW89_PKT_DROP_SEL_MG0_ONCE,
5130 RTW89_PKT_DROP_SEL_HIQ_ONCE,
5131 RTW89_PKT_DROP_SEL_HIQ_PORT,
5132 RTW89_PKT_DROP_SEL_HIQ_MBSSID,
5133 RTW89_PKT_DROP_SEL_BAND,
5134 RTW89_PKT_DROP_SEL_BAND_ONCE,
5135 RTW89_PKT_DROP_SEL_REL_MACID,
5136 RTW89_PKT_DROP_SEL_REL_HIQ_PORT,
5137 RTW89_PKT_DROP_SEL_REL_HIQ_MBSSID,
5138 };
5139
5140 struct rtw89_pkt_drop_params {
5141 enum rtw89_pkt_drop_sel sel;
5142 enum rtw89_mac_idx mac_band;
5143 u8 macid;
5144 u8 port;
5145 u8 mbssid;
5146 bool tf_trs;
5147 u32 macid_band_sel[4];
5148 };
5149
5150 struct rtw89_pkt_stat {
5151 u16 beacon_nr;
5152 u8 beacon_rate;
5153 u32 beacon_len;
5154 u32 rx_rate_cnt[RTW89_HW_RATE_NR];
5155 };
5156
5157 #define RTW89_BCN_TRACK_STAT_NR 32
5158 #define RTW89_BCN_TRACK_SCALE_FACTOR 10
5159 #define RTW89_BCN_TRACK_MAX_BIN_NUM 6
5160 #define RTW89_BCN_TRACK_BIN_WIDTH 5
5161 #define RTW89_BCN_TRACK_TARGET_BCN 80
5162
5163 struct rtw89_beacon_dist {
5164 u16 min;
5165 u16 max;
5166 u16 outlier_count;
5167 u16 lower_bound;
5168 u16 upper_bound;
5169 u16 bins[RTW89_BCN_TRACK_MAX_BIN_NUM];
5170 };
5171
5172 struct rtw89_beacon_stat {
5173 u8 num;
5174 u8 wp;
5175 u16 tbtt_tu_min;
5176 u16 tbtt_tu_max;
5177 u16 drift[RTW89_BCN_TRACK_STAT_NR];
5178 u32 tbtt_us[RTW89_BCN_TRACK_STAT_NR];
5179 u16 tbtt_tu[RTW89_BCN_TRACK_STAT_NR];
5180 struct rtw89_beacon_dist bcn_dist;
5181 };
5182
5183 DECLARE_EWMA(thermal, 4, 4);
5184
5185 struct rtw89_phy_stat {
5186 struct ewma_thermal avg_thermal[RF_PATH_MAX];
5187 u8 last_thermal_max;
5188 struct ewma_rssi bcn_rssi;
5189 struct rtw89_pkt_stat cur_pkt_stat;
5190 struct rtw89_pkt_stat last_pkt_stat;
5191 struct rtw89_beacon_stat bcn_stat;
5192 };
5193
5194 enum rtw89_rfk_report_state {
5195 RTW89_RFK_STATE_START = 0x0,
5196 RTW89_RFK_STATE_OK = 0x1,
5197 RTW89_RFK_STATE_FAIL = 0x2,
5198 RTW89_RFK_STATE_TIMEOUT = 0x3,
5199 RTW89_RFK_STATE_H2C_CMD_ERR = 0x4,
5200 };
5201
5202 struct rtw89_rfk_wait_info {
5203 struct completion completion;
5204 ktime_t start_time;
5205 enum rtw89_rfk_report_state state;
5206 u8 version;
5207 };
5208
5209 #define RTW89_DACK_PATH_NR 2
5210 #define RTW89_DACK_IDX_NR 2
5211 #define RTW89_DACK_MSBK_NR 16
5212 struct rtw89_dack_info {
5213 bool dack_done;
5214 u8 msbk_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR][RTW89_DACK_MSBK_NR];
5215 u8 dadck_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR];
5216 u16 addck_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR];
5217 u16 biask_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR];
5218 u32 dack_cnt;
5219 bool addck_timeout[RTW89_DACK_PATH_NR];
5220 bool dadck_timeout[RTW89_DACK_PATH_NR];
5221 bool msbk_timeout[RTW89_DACK_PATH_NR];
5222 };
5223
5224 enum rtw89_rfk_chs_nrs {
5225 __RTW89_RFK_CHS_NR_V0 = 2,
5226 __RTW89_RFK_CHS_NR_V1 = 3,
5227
5228 RTW89_RFK_CHS_NR = __RTW89_RFK_CHS_NR_V1,
5229 };
5230
5231 struct rtw89_rfk_mcc_info_data {
5232 u8 ch[RTW89_RFK_CHS_NR];
5233 u8 band[RTW89_RFK_CHS_NR];
5234 u8 bw[RTW89_RFK_CHS_NR];
5235 u8 table_idx;
5236 };
5237
5238 struct rtw89_rfk_mcc_info {
5239 struct rtw89_rfk_mcc_info_data data[2];
5240 };
5241
5242 #define RTW89_IQK_CHS_NR 2
5243 #define RTW89_IQK_PATH_NR 4
5244
5245 struct rtw89_lck_info {
5246 u8 thermal[RF_PATH_MAX];
5247 };
5248
5249 struct rtw89_rx_dck_info {
5250 u8 thermal[RF_PATH_MAX];
5251 };
5252
5253 struct rtw89_iqk_info {
5254 bool lok_cor_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR];
5255 bool lok_fin_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR];
5256 bool lok_fail[RTW89_IQK_PATH_NR];
5257 bool iqk_tx_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR];
5258 bool iqk_rx_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR];
5259 u32 iqk_fail_cnt;
5260 bool is_iqk_init;
5261 u32 iqk_channel[RTW89_IQK_CHS_NR];
5262 u8 iqk_band[RTW89_IQK_PATH_NR];
5263 u8 iqk_ch[RTW89_IQK_PATH_NR];
5264 u8 iqk_bw[RTW89_IQK_PATH_NR];
5265 u8 iqk_times;
5266 u8 version;
5267 u32 nb_txcfir[RTW89_IQK_PATH_NR];
5268 u32 nb_rxcfir[RTW89_IQK_PATH_NR];
5269 u32 bp_txkresult[RTW89_IQK_PATH_NR];
5270 u32 bp_rxkresult[RTW89_IQK_PATH_NR];
5271 u32 bp_iqkenable[RTW89_IQK_PATH_NR];
5272 bool is_wb_txiqk[RTW89_IQK_PATH_NR];
5273 bool is_wb_rxiqk[RTW89_IQK_PATH_NR];
5274 bool is_nbiqk;
5275 bool iqk_fft_en;
5276 bool iqk_xym_en;
5277 bool iqk_sram_en;
5278 bool iqk_cfir_en;
5279 u32 syn1to2;
5280 u8 iqk_mcc_ch[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR];
5281 u8 iqk_table_idx[RTW89_IQK_PATH_NR];
5282 u32 lok_idac[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR];
5283 u32 lok_vbuf[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR];
5284 };
5285
5286 #define RTW89_DPK_RF_PATH 2
5287 #define RTW89_DPK_AVG_THERMAL_NUM 8
5288 #define RTW89_DPK_BKUP_NUM 2
5289 struct rtw89_dpk_bkup_para {
5290 enum rtw89_band band;
5291 enum rtw89_bandwidth bw;
5292 u8 ch;
5293 u8 path_ok;
5294 u8 mdpd_en;
5295 u8 txagc_dpk;
5296 u8 ther_dpk;
5297 u8 gs;
5298 u16 pwsf;
5299 };
5300
5301 struct rtw89_dpk_info {
5302 bool is_dpk_enable;
5303 bool is_dpk_reload_en;
5304 u8 dpk_gs[RTW89_PHY_NUM];
5305 u16 dc_i[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM];
5306 u16 dc_q[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM];
5307 u8 corr_val[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM];
5308 u8 corr_idx[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM];
5309 u8 cur_idx[RTW89_DPK_RF_PATH];
5310 u8 cur_k_set;
5311 struct rtw89_dpk_bkup_para bp[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM];
5312 u8 max_dpk_txagc[RTW89_DPK_RF_PATH];
5313 u32 dpk_order[RTW89_DPK_RF_PATH];
5314 };
5315
5316 struct rtw89_fem_info {
5317 bool elna_2g;
5318 bool elna_5g;
5319 bool epa_2g;
5320 bool epa_5g;
5321 bool epa_6g;
5322 };
5323
5324 struct rtw89_phy_ch_info {
5325 u8 rssi_min;
5326 u16 rssi_min_macid;
5327 u8 pre_rssi_min;
5328 u8 rssi_max;
5329 u16 rssi_max_macid;
5330 u8 rxsc_160;
5331 u8 rxsc_80;
5332 u8 rxsc_40;
5333 u8 rxsc_20;
5334 u8 rxsc_l;
5335 u8 is_noisy;
5336 };
5337
5338 struct rtw89_agc_gaincode_set {
5339 u8 lna_idx;
5340 u8 tia_idx;
5341 u8 rxb_idx;
5342 };
5343
5344 #define IGI_RSSI_TH_NUM 5
5345 #define FA_TH_NUM 4
5346 #define TIA_LNA_OP1DB_NUM 8
5347 #define LNA_GAIN_NUM 7
5348 #define TIA_GAIN_NUM 2
5349 struct rtw89_dig_info {
5350 struct rtw89_agc_gaincode_set cur_gaincode;
5351 bool force_gaincode_idx_en;
5352 struct rtw89_agc_gaincode_set force_gaincode;
5353 u8 igi_rssi_th[IGI_RSSI_TH_NUM];
5354 u16 fa_th[FA_TH_NUM];
5355 u8 igi_rssi;
5356 u8 igi_fa_rssi;
5357 u8 fa_rssi_ofst;
5358 u8 dyn_igi_max;
5359 u8 dyn_igi_min;
5360 bool dyn_pd_th_en;
5361 u8 dyn_pd_th_max;
5362 u8 pd_low_th_ofst;
5363 u8 ib_pbk;
5364 s8 ib_pkpwr;
5365 s8 lna_gain_a[LNA_GAIN_NUM];
5366 s8 lna_gain_g[LNA_GAIN_NUM];
5367 s8 *lna_gain;
5368 s8 tia_gain_a[TIA_GAIN_NUM];
5369 s8 tia_gain_g[TIA_GAIN_NUM];
5370 s8 *tia_gain;
5371 u32 bak_dig;
5372 bool is_linked_pre;
5373 bool bypass_dig;
5374 bool pause_dig;
5375 };
5376
5377 enum rtw89_multi_cfo_mode {
5378 RTW89_PKT_BASED_AVG_MODE = 0,
5379 RTW89_ENTRY_BASED_AVG_MODE = 1,
5380 RTW89_TP_BASED_AVG_MODE = 2,
5381 };
5382
5383 enum rtw89_phy_cfo_status {
5384 RTW89_PHY_DCFO_STATE_NORMAL = 0,
5385 RTW89_PHY_DCFO_STATE_ENHANCE = 1,
5386 RTW89_PHY_DCFO_STATE_HOLD = 2,
5387 RTW89_PHY_DCFO_STATE_MAX
5388 };
5389
5390 enum rtw89_phy_cfo_ul_ofdma_acc_mode {
5391 RTW89_CFO_UL_OFDMA_ACC_DISABLE = 0,
5392 RTW89_CFO_UL_OFDMA_ACC_ENABLE = 1
5393 };
5394
5395 struct rtw89_cfo_tracking_info {
5396 u16 cfo_timer_ms;
5397 bool cfo_trig_by_timer_en;
5398 enum rtw89_phy_cfo_status phy_cfo_status;
5399 enum rtw89_phy_cfo_ul_ofdma_acc_mode cfo_ul_ofdma_acc_mode;
5400 u8 phy_cfo_trk_cnt;
5401 bool is_adjust;
5402 enum rtw89_multi_cfo_mode rtw89_multi_cfo_mode;
5403 bool apply_compensation;
5404 u8 crystal_cap;
5405 u8 crystal_cap_default;
5406 u8 def_x_cap;
5407 s8 x_cap_ofst;
5408 u32 sta_cfo_tolerance;
5409 s32 cfo_tail[CFO_TRACK_MAX_USER];
5410 u16 cfo_cnt[CFO_TRACK_MAX_USER];
5411 s32 cfo_avg_pre;
5412 s32 cfo_avg[CFO_TRACK_MAX_USER];
5413 s32 pre_cfo_avg[CFO_TRACK_MAX_USER];
5414 s32 dcfo_avg;
5415 s32 dcfo_avg_pre;
5416 u32 packet_count;
5417 u32 packet_count_pre;
5418 s32 residual_cfo_acc;
5419 u8 phy_cfotrk_state;
5420 u8 phy_cfotrk_cnt;
5421 bool divergence_lock_en;
5422 u8 x_cap_lb;
5423 u8 x_cap_ub;
5424 u8 lock_cnt;
5425 };
5426
5427 enum rtw89_tssi_mode {
5428 RTW89_TSSI_NORMAL = 0,
5429 RTW89_TSSI_SCAN = 1,
5430 };
5431
5432 enum rtw89_tssi_alimk_band {
5433 TSSI_ALIMK_2G = 0,
5434 TSSI_ALIMK_5GL,
5435 TSSI_ALIMK_5GM,
5436 TSSI_ALIMK_5GH,
5437 TSSI_ALIMK_MAX
5438 };
5439
5440 /* 2GL, 2GH, 5GL1, 5GH1, 5GM1, 5GM2, 5GH1, 5GH2 */
5441 #define TSSI_TRIM_CH_GROUP_NUM 8
5442 #define TSSI_TRIM_CH_GROUP_NUM_6G 16
5443
5444 #define TSSI_CCK_CH_GROUP_NUM 6
5445 #define TSSI_MCS_2G_CH_GROUP_NUM 5
5446 #define TSSI_MCS_5G_CH_GROUP_NUM 14
5447 #define TSSI_MCS_6G_CH_GROUP_NUM 32
5448 #define TSSI_MCS_CH_GROUP_NUM \
5449 (TSSI_MCS_2G_CH_GROUP_NUM + TSSI_MCS_5G_CH_GROUP_NUM)
5450 #define TSSI_MAX_CH_NUM 67
5451 #define TSSI_ALIMK_VALUE_NUM 8
5452
5453 struct rtw89_tssi_info {
5454 u8 thermal[RF_PATH_MAX];
5455 s8 tssi_trim[RF_PATH_MAX][TSSI_TRIM_CH_GROUP_NUM];
5456 s8 tssi_trim_6g[RF_PATH_MAX][TSSI_TRIM_CH_GROUP_NUM_6G];
5457 s8 tssi_cck[RF_PATH_MAX][TSSI_CCK_CH_GROUP_NUM];
5458 s8 tssi_mcs[RF_PATH_MAX][TSSI_MCS_CH_GROUP_NUM];
5459 s8 tssi_6g_mcs[RF_PATH_MAX][TSSI_MCS_6G_CH_GROUP_NUM];
5460 s8 extra_ofst[RF_PATH_MAX];
5461 bool tssi_tracking_check[RF_PATH_MAX];
5462 u8 default_txagc_offset[RF_PATH_MAX];
5463 u32 base_thermal[RF_PATH_MAX];
5464 bool check_backup_aligmk[RF_PATH_MAX][TSSI_MAX_CH_NUM];
5465 u32 alignment_backup_by_ch[RF_PATH_MAX][TSSI_MAX_CH_NUM][TSSI_ALIMK_VALUE_NUM];
5466 u32 alignment_value[RF_PATH_MAX][TSSI_ALIMK_MAX][TSSI_ALIMK_VALUE_NUM];
5467 bool alignment_done[RF_PATH_MAX][TSSI_ALIMK_MAX];
5468 u64 tssi_alimk_time;
5469 };
5470
5471 struct rtw89_power_trim_info {
5472 bool pg_thermal_trim;
5473 bool pg_pa_bias_trim;
5474 u8 thermal_trim[RF_PATH_MAX];
5475 u8 pa_bias_trim[RF_PATH_MAX];
5476 u8 pad_bias_trim[RF_PATH_MAX];
5477 };
5478
5479 enum rtw89_regd_func {
5480 RTW89_REGD_FUNC_TAS = 0, /* TAS (Time Average SAR) */
5481 RTW89_REGD_FUNC_DAG = 1, /* DAG (Dynamic Antenna Gain) */
5482
5483 NUM_OF_RTW89_REGD_FUNC,
5484 };
5485
5486 struct rtw89_regd {
5487 char alpha2[3];
5488 u8 txpwr_regd[RTW89_BAND_NUM];
5489 DECLARE_BITMAP(func_bitmap, NUM_OF_RTW89_REGD_FUNC);
5490 };
5491
5492 struct rtw89_regd_data {
5493 unsigned int nr;
5494 struct rtw89_regd map[] __counted_by(nr);
5495 };
5496
5497 struct rtw89_regd_ctrl {
5498 unsigned int nr;
5499 const struct rtw89_regd *map;
5500 };
5501
5502 #define RTW89_REGD_MAX_COUNTRY_NUM U8_MAX
5503 #define RTW89_5GHZ_UNII4_CHANNEL_NUM 3
5504 #define RTW89_5GHZ_UNII4_START_INDEX 25
5505
5506 struct rtw89_regulatory_info {
5507 struct rtw89_regd_ctrl ctrl;
5508 const struct rtw89_regd *regd;
5509 bool programmed;
5510
5511 enum rtw89_reg_6ghz_power reg_6ghz_power;
5512 struct rtw89_reg_6ghz_tpe reg_6ghz_tpe;
5513 bool txpwr_uk_follow_etsi;
5514
5515 DECLARE_BITMAP(block_unii4, RTW89_REGD_MAX_COUNTRY_NUM);
5516 DECLARE_BITMAP(block_6ghz, RTW89_REGD_MAX_COUNTRY_NUM);
5517 DECLARE_BITMAP(block_6ghz_sp, RTW89_REGD_MAX_COUNTRY_NUM);
5518 DECLARE_BITMAP(block_6ghz_vlp, RTW89_REGD_MAX_COUNTRY_NUM);
5519 };
5520
5521 enum rtw89_ifs_clm_application {
5522 RTW89_IFS_CLM_INIT = 0,
5523 RTW89_IFS_CLM_BACKGROUND = 1,
5524 RTW89_IFS_CLM_ACS = 2,
5525 RTW89_IFS_CLM_DIG = 3,
5526 RTW89_IFS_CLM_TDMA_DIG = 4,
5527 RTW89_IFS_CLM_DBG = 5,
5528 RTW89_IFS_CLM_DBG_MANUAL = 6
5529 };
5530
5531 enum rtw89_env_racing_lv {
5532 RTW89_RAC_RELEASE = 0,
5533 RTW89_RAC_LV_1 = 1,
5534 RTW89_RAC_LV_2 = 2,
5535 RTW89_RAC_LV_3 = 3,
5536 RTW89_RAC_LV_4 = 4,
5537 RTW89_RAC_MAX_NUM = 5
5538 };
5539
5540 struct rtw89_ccx_para_info {
5541 enum rtw89_env_racing_lv rac_lv;
5542 u16 mntr_time;
5543 bool nhm_incld_cca;
5544 u8 nhm_manual_th_ofst;
5545 u8 nhm_manual_th0;
5546 enum rtw89_ifs_clm_application ifs_clm_app;
5547 u32 ifs_clm_manual_th_times;
5548 u32 ifs_clm_manual_th0;
5549 u8 fahm_manual_th_ofst;
5550 u8 fahm_manual_th0;
5551 u8 fahm_numer_opt;
5552 u8 fahm_denom_opt;
5553 };
5554
5555 enum rtw89_ccx_edcca_opt_sc_idx {
5556 RTW89_CCX_EDCCA_SEG0_P0 = 0,
5557 RTW89_CCX_EDCCA_SEG0_S1 = 1,
5558 RTW89_CCX_EDCCA_SEG0_S2 = 2,
5559 RTW89_CCX_EDCCA_SEG0_S3 = 3,
5560 RTW89_CCX_EDCCA_SEG1_P0 = 4,
5561 RTW89_CCX_EDCCA_SEG1_S1 = 5,
5562 RTW89_CCX_EDCCA_SEG1_S2 = 6,
5563 RTW89_CCX_EDCCA_SEG1_S3 = 7
5564 };
5565
5566 enum rtw89_ccx_edcca_opt_bw_idx {
5567 RTW89_CCX_EDCCA_BW20_0 = 0,
5568 RTW89_CCX_EDCCA_BW20_1 = 1,
5569 RTW89_CCX_EDCCA_BW20_2 = 2,
5570 RTW89_CCX_EDCCA_BW20_3 = 3,
5571 RTW89_CCX_EDCCA_BW20_4 = 4,
5572 RTW89_CCX_EDCCA_BW20_5 = 5,
5573 RTW89_CCX_EDCCA_BW20_6 = 6,
5574 RTW89_CCX_EDCCA_BW20_7 = 7
5575 };
5576
5577 struct rtw89_nhm_report {
5578 struct list_head list;
5579 struct ieee80211_channel *channel;
5580 u8 noise;
5581 };
5582
5583 #define RTW89_FAHM_TH_NUM 11
5584 #define RTW89_FAHM_RPT_NUM 12
5585 #define RTW89_IFS_CLM_NUM 4
5586 struct rtw89_env_monitor_info {
5587 u8 ccx_watchdog_result;
5588 bool ccx_ongoing;
5589 u8 ccx_rac_lv;
5590 bool ccx_manual_ctrl;
5591 u16 ifs_clm_mntr_time;
5592 enum rtw89_ifs_clm_application ifs_clm_app;
5593 u16 ccx_period;
5594 u8 ccx_unit_idx;
5595 u16 ifs_clm_th_l[RTW89_IFS_CLM_NUM];
5596 u16 ifs_clm_th_h[RTW89_IFS_CLM_NUM];
5597 u16 ifs_clm_tx;
5598 u16 ifs_clm_edcca_excl_cca;
5599 u16 ifs_clm_ofdmfa;
5600 u16 ifs_clm_ofdmcca_excl_fa;
5601 u16 ifs_clm_cckfa;
5602 u16 ifs_clm_cckcca_excl_fa;
5603 u16 ifs_clm_total_ifs;
5604 u8 ifs_clm_his[RTW89_IFS_CLM_NUM];
5605 u16 ifs_clm_avg[RTW89_IFS_CLM_NUM];
5606 u16 ifs_clm_cca[RTW89_IFS_CLM_NUM];
5607 u8 ifs_clm_tx_ratio;
5608 u8 ifs_clm_edcca_excl_cca_ratio;
5609 u8 ifs_clm_cck_fa_ratio;
5610 u8 ifs_clm_ofdm_fa_ratio;
5611 u8 ifs_clm_cck_cca_excl_fa_ratio;
5612 u8 ifs_clm_ofdm_cca_excl_fa_ratio;
5613 u16 ifs_clm_cck_fa_permil;
5614 u16 ifs_clm_ofdm_fa_permil;
5615 u32 ifs_clm_ifs_avg[RTW89_IFS_CLM_NUM];
5616 u32 ifs_clm_cca_avg[RTW89_IFS_CLM_NUM];
5617 bool nhm_include_cca;
5618 u32 nhm_sum;
5619 u32 nhm_mntr_time;
5620 u16 nhm_result[RTW89_NHM_RPT_NUM];
5621 u8 nhm_th[RTW89_NHM_RPT_NUM];
5622 struct rtw89_nhm_report *nhm_his[RTW89_BAND_NUM];
5623 struct list_head nhm_rpt_list;
5624 };
5625
5626 enum rtw89_ser_rcvy_step {
5627 RTW89_SER_DRV_STOP_TX,
5628 RTW89_SER_DRV_STOP_RX,
5629 RTW89_SER_DRV_STOP_RUN,
5630 RTW89_SER_HAL_STOP_DMA,
5631 RTW89_SER_SUPPRESS_LOG,
5632 RTW89_NUM_OF_SER_FLAGS
5633 };
5634
5635 struct rtw89_ser {
5636 u8 state;
5637 u8 alarm_event;
5638 bool prehandle_l1;
5639
5640 struct work_struct ser_hdl_work;
5641 struct delayed_work ser_alarm_work;
5642 const struct state_ent *st_tbl;
5643 const struct event_ent *ev_tbl;
5644 struct list_head msg_q;
5645 spinlock_t msg_q_lock; /* lock when read/write ser msg */
5646 DECLARE_BITMAP(flags, RTW89_NUM_OF_SER_FLAGS);
5647 };
5648
5649 enum rtw89_mac_ax_ps_mode {
5650 RTW89_MAC_AX_PS_MODE_ACTIVE = 0,
5651 RTW89_MAC_AX_PS_MODE_LEGACY = 1,
5652 RTW89_MAC_AX_PS_MODE_WMMPS = 2,
5653 RTW89_MAC_AX_PS_MODE_MAX = 3,
5654 };
5655
5656 enum rtw89_last_rpwm_mode {
5657 RTW89_LAST_RPWM_PS = 0x0,
5658 RTW89_LAST_RPWM_ACTIVE = 0x6,
5659 };
5660
5661 struct rtw89_lps_parm {
5662 u8 macid;
5663 u8 psmode; /* enum rtw89_mac_ax_ps_mode */
5664 u8 lastrpwm; /* enum rtw89_last_rpwm_mode */
5665 };
5666
5667 struct rtw89_ppdu_sts_info {
5668 struct sk_buff_head rx_queue[RTW89_PHY_NUM];
5669 u8 curr_rx_ppdu_cnt[RTW89_PHY_NUM];
5670 };
5671
5672 struct rtw89_early_h2c {
5673 struct list_head list;
5674 u8 *h2c;
5675 u16 h2c_len;
5676 };
5677
5678 struct rtw89_hw_scan_extra_op {
5679 bool set;
5680 u8 macid;
5681 u8 port;
5682 struct rtw89_chan chan;
5683 struct rtw89_vif_link *rtwvif_link;
5684 };
5685
5686 struct rtw89_hw_scan_info {
5687 struct rtw89_vif_link *scanning_vif;
5688 struct list_head pkt_list[NUM_NL80211_BANDS];
5689 struct list_head chan_list;
5690 struct rtw89_chan op_chan;
5691 struct rtw89_hw_scan_extra_op extra_op;
5692 bool connected;
5693 bool abort;
5694 u16 delay; /* in unit of ms */
5695 u8 seq: 2;
5696 };
5697
5698 enum rtw89_phy_bb_gain_band {
5699 RTW89_BB_GAIN_BAND_2G = 0,
5700 RTW89_BB_GAIN_BAND_5G_L = 1,
5701 RTW89_BB_GAIN_BAND_5G_M = 2,
5702 RTW89_BB_GAIN_BAND_5G_H = 3,
5703 RTW89_BB_GAIN_BAND_6G_L = 4,
5704 RTW89_BB_GAIN_BAND_6G_M = 5,
5705 RTW89_BB_GAIN_BAND_6G_H = 6,
5706 RTW89_BB_GAIN_BAND_6G_UH = 7,
5707
5708 RTW89_BB_GAIN_BAND_NR,
5709 };
5710
5711 enum rtw89_phy_gain_band_be {
5712 RTW89_BB_GAIN_BAND_2G_BE = 0,
5713 RTW89_BB_GAIN_BAND_5G_L_BE = 1,
5714 RTW89_BB_GAIN_BAND_5G_M_BE = 2,
5715 RTW89_BB_GAIN_BAND_5G_H_BE = 3,
5716 RTW89_BB_GAIN_BAND_6G_L0_BE = 4,
5717 RTW89_BB_GAIN_BAND_6G_L1_BE = 5,
5718 RTW89_BB_GAIN_BAND_6G_M0_BE = 6,
5719 RTW89_BB_GAIN_BAND_6G_M1_BE = 7,
5720 RTW89_BB_GAIN_BAND_6G_H0_BE = 8,
5721 RTW89_BB_GAIN_BAND_6G_H1_BE = 9,
5722 RTW89_BB_GAIN_BAND_6G_UH0_BE = 10,
5723 RTW89_BB_GAIN_BAND_6G_UH1_BE = 11,
5724
5725 RTW89_BB_GAIN_BAND_NR_BE,
5726 };
5727
5728 enum rtw89_phy_bb_bw_be {
5729 RTW89_BB_BW_20_40 = 0,
5730 RTW89_BB_BW_80_160_320 = 1,
5731
5732 RTW89_BB_BW_NR_BE,
5733 };
5734
5735 enum rtw89_bw20_sc {
5736 RTW89_BW20_SC_20M = 1,
5737 RTW89_BW20_SC_40M = 2,
5738 RTW89_BW20_SC_80M = 4,
5739 RTW89_BW20_SC_160M = 8,
5740 RTW89_BW20_SC_320M = 16,
5741 };
5742
5743 enum rtw89_cmac_table_bw {
5744 RTW89_CMAC_BW_20M = 0,
5745 RTW89_CMAC_BW_40M = 1,
5746 RTW89_CMAC_BW_80M = 2,
5747 RTW89_CMAC_BW_160M = 3,
5748 RTW89_CMAC_BW_320M = 4,
5749
5750 RTW89_CMAC_BW_NR,
5751 };
5752
5753 enum rtw89_phy_bb_rxsc_num {
5754 RTW89_BB_RXSC_NUM_40 = 9, /* SC: 0, 1~8 */
5755 RTW89_BB_RXSC_NUM_80 = 13, /* SC: 0, 1~8, 9~12 */
5756 RTW89_BB_RXSC_NUM_160 = 15, /* SC: 0, 1~8, 9~12, 13~14 */
5757 };
5758
5759 struct rtw89_phy_bb_gain_info {
5760 s8 lna_gain[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][LNA_GAIN_NUM];
5761 s8 tia_gain[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][TIA_GAIN_NUM];
5762 s8 lna_gain_bypass[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][LNA_GAIN_NUM];
5763 s8 lna_op1db[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][LNA_GAIN_NUM];
5764 s8 tia_lna_op1db[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX]
5765 [LNA_GAIN_NUM + 1]; /* TIA0_LNA0~6 + TIA1_LNA6 */
5766 s8 rpl_ofst_20[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX];
5767 s8 rpl_ofst_40[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX]
5768 [RTW89_BB_RXSC_NUM_40];
5769 s8 rpl_ofst_80[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX]
5770 [RTW89_BB_RXSC_NUM_80];
5771 s8 rpl_ofst_160[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX]
5772 [RTW89_BB_RXSC_NUM_160];
5773 };
5774
5775 struct rtw89_phy_bb_gain_info_be {
5776 s8 lna_gain[RTW89_BB_GAIN_BAND_NR_BE][RTW89_BB_BW_NR_BE][RF_PATH_MAX]
5777 [LNA_GAIN_NUM];
5778 s8 tia_gain[RTW89_BB_GAIN_BAND_NR_BE][RTW89_BB_BW_NR_BE][RF_PATH_MAX]
5779 [TIA_GAIN_NUM];
5780 s8 lna_gain_bypass[RTW89_BB_GAIN_BAND_NR_BE][RTW89_BB_BW_NR_BE]
5781 [RF_PATH_MAX][LNA_GAIN_NUM];
5782 s8 lna_op1db[RTW89_BB_GAIN_BAND_NR_BE][RTW89_BB_BW_NR_BE]
5783 [RF_PATH_MAX][LNA_GAIN_NUM];
5784 s8 tia_lna_op1db[RTW89_BB_GAIN_BAND_NR_BE][RTW89_BB_BW_NR_BE]
5785 [RF_PATH_MAX][LNA_GAIN_NUM + 1];
5786 s8 rpl_ofst_20[RTW89_BB_GAIN_BAND_NR_BE][RF_PATH_MAX]
5787 [RTW89_BW20_SC_20M];
5788 s8 rpl_ofst_40[RTW89_BB_GAIN_BAND_NR_BE][RF_PATH_MAX]
5789 [RTW89_BW20_SC_40M];
5790 s8 rpl_ofst_80[RTW89_BB_GAIN_BAND_NR_BE][RF_PATH_MAX]
5791 [RTW89_BW20_SC_80M];
5792 s8 rpl_ofst_160[RTW89_BB_GAIN_BAND_NR_BE][RF_PATH_MAX]
5793 [RTW89_BW20_SC_160M];
5794 };
5795
5796 struct rtw89_phy_efuse_gain {
5797 bool offset_valid;
5798 bool comp_valid;
5799 s8 offset[RF_PATH_MAX][RTW89_GAIN_OFFSET_NR]; /* S(8, 0) */
5800 s8 offset_base[RTW89_PHY_NUM]; /* S(8, 4) */
5801 s8 rssi_base[RTW89_PHY_NUM]; /* S(8, 4) */
5802 s8 comp[RF_PATH_MAX][RTW89_SUBBAND_NR]; /* S(8, 0) */
5803 };
5804
5805 #define RTW89_MAX_PATTERN_NUM 18
5806 #define RTW89_MAX_PATTERN_MASK_SIZE 4
5807 #define RTW89_MAX_PATTERN_SIZE 128
5808
5809 struct rtw89_wow_cam_info {
5810 bool r_w;
5811 u8 idx;
5812 u32 mask[RTW89_MAX_PATTERN_MASK_SIZE];
5813 u16 crc;
5814 bool negative_pattern_match;
5815 bool skip_mac_hdr;
5816 bool uc;
5817 bool mc;
5818 bool bc;
5819 bool valid;
5820 };
5821
5822 struct rtw89_wow_key_info {
5823 u8 ptk_tx_iv[8];
5824 u8 valid_check;
5825 u8 symbol_check_en;
5826 u8 gtk_keyidx;
5827 u8 rsvd[5];
5828 u8 ptk_rx_iv[8];
5829 u8 gtk_rx_iv[4][8];
5830 } __packed;
5831
5832 struct rtw89_wow_gtk_info {
5833 u8 kck[32];
5834 u8 kek[32];
5835 u8 tk1[16];
5836 u8 rxmickey[8];
5837 u8 txmickey[8];
5838 __le32 igtk_keyid;
5839 __le64 ipn;
5840 u8 igtk[2][32];
5841 u8 psk[32];
5842 } __packed;
5843
5844 struct rtw89_wow_aoac_report {
5845 u8 rpt_ver;
5846 u8 sec_type;
5847 u8 key_idx;
5848 u8 pattern_idx;
5849 u8 rekey_ok;
5850 u8 ptk_tx_iv[8];
5851 u8 eapol_key_replay_count[8];
5852 u8 gtk[32];
5853 u8 ptk_rx_iv[8];
5854 u8 gtk_rx_iv[4][8];
5855 u64 igtk_key_id;
5856 u64 igtk_ipn;
5857 u8 igtk[32];
5858 u8 csa_pri_ch;
5859 u8 csa_bw;
5860 u8 csa_ch_offset;
5861 u8 csa_chsw_failed;
5862 u8 csa_ch_band;
5863 };
5864
5865 struct rtw89_wow_param {
5866 struct rtw89_vif_link *rtwvif_link;
5867 DECLARE_BITMAP(flags, RTW89_WOW_FLAG_NUM);
5868 struct rtw89_wow_cam_info patterns[RTW89_MAX_PATTERN_NUM];
5869 struct rtw89_wow_key_info key_info;
5870 struct rtw89_wow_gtk_info gtk_info;
5871 struct rtw89_wow_aoac_report aoac_rpt;
5872 u8 pattern_cnt;
5873 u8 ptk_alg;
5874 u8 gtk_alg;
5875 u8 ptk_keyidx;
5876 u8 akm;
5877
5878 /* see RTW89_WOW_WAIT_COND series for wait condition */
5879 struct rtw89_wait_info wait;
5880
5881 bool pno_inited;
5882 struct list_head pno_pkt_list;
5883 struct cfg80211_sched_scan_request *nd_config;
5884 };
5885
5886 struct rtw89_mcc_limit {
5887 bool enable;
5888 u16 max_tob; /* TU; max time offset behind */
5889 u16 max_toa; /* TU; max time offset ahead */
5890 u16 max_dur; /* TU */
5891 };
5892
5893 struct rtw89_mcc_policy {
5894 u8 c2h_rpt;
5895 u8 tx_null_early;
5896 u8 dis_tx_null;
5897 u8 in_curr_ch;
5898 u8 dis_sw_retry;
5899 u8 sw_retry_count;
5900 };
5901
5902 struct rtw89_mcc_role {
5903 struct rtw89_vif_link *rtwvif_link;
5904 struct rtw89_mcc_policy policy;
5905 struct rtw89_mcc_limit limit;
5906
5907 const struct rtw89_mcc_courtesy_cfg *crtz;
5908
5909 /* only valid when running with FW MRC mechanism */
5910 u8 slot_idx;
5911
5912 /* byte-array in LE order for FW */
5913 u8 macid_bitmap[BITS_TO_BYTES(RTW89_MAX_MAC_ID_NUM)];
5914 u8 probe_count;
5915
5916 u16 duration; /* TU */
5917 u16 beacon_interval; /* TU */
5918 bool is_2ghz;
5919 bool is_go;
5920 bool is_gc;
5921 bool ignore_bcn;
5922 };
5923
5924 struct rtw89_mcc_bt_role {
5925 u16 duration; /* TU */
5926 };
5927
5928 struct rtw89_mcc_courtesy_cfg {
5929 u8 slot_num;
5930 u8 macid_tgt;
5931 };
5932
5933 struct rtw89_mcc_courtesy {
5934 struct rtw89_mcc_courtesy_cfg ref;
5935 struct rtw89_mcc_courtesy_cfg aux;
5936 };
5937
5938 enum rtw89_mcc_plan {
5939 RTW89_MCC_PLAN_TAIL_BT,
5940 RTW89_MCC_PLAN_MID_BT,
5941 RTW89_MCC_PLAN_NO_BT,
5942
5943 NUM_OF_RTW89_MCC_PLAN,
5944 };
5945
5946 struct rtw89_mcc_pattern {
5947 s16 tob_ref; /* TU; time offset behind of reference role */
5948 s16 toa_ref; /* TU; time offset ahead of reference role */
5949 s16 tob_aux; /* TU; time offset behind of auxiliary role */
5950 s16 toa_aux; /* TU; time offset ahead of auxiliary role */
5951
5952 enum rtw89_mcc_plan plan;
5953 struct rtw89_mcc_courtesy courtesy;
5954 };
5955
5956 struct rtw89_mcc_sync {
5957 bool enable;
5958 u16 offset; /* TU */
5959 u8 macid_src;
5960 u8 band_src;
5961 u8 port_src;
5962 u8 macid_tgt;
5963 u8 band_tgt;
5964 u8 port_tgt;
5965 };
5966
5967 struct rtw89_mcc_config {
5968 struct rtw89_mcc_pattern pattern;
5969 struct rtw89_mcc_sync sync;
5970 u64 start_tsf;
5971 u64 start_tsf_in_aux_domain;
5972 u64 prepare_delay;
5973 u16 mcc_interval; /* TU */
5974 u16 beacon_offset; /* TU */
5975 };
5976
5977 enum rtw89_mcc_mode {
5978 RTW89_MCC_MODE_GO_STA,
5979 RTW89_MCC_MODE_GC_STA,
5980 };
5981
5982 struct rtw89_mcc_info {
5983 struct rtw89_wait_info wait;
5984
5985 u8 group;
5986 enum rtw89_mcc_mode mode;
5987 struct rtw89_mcc_role role_ref; /* reference role */
5988 struct rtw89_mcc_role role_aux; /* auxiliary role */
5989 struct rtw89_mcc_bt_role bt_role;
5990 struct rtw89_mcc_config config;
5991 };
5992
5993 enum rtw89_mlo_mode {
5994 RTW89_MLO_MODE_MLSR = 0,
5995 RTW89_MLO_MODE_EMLSR = 1,
5996
5997 NUM_OF_RTW89_MLO_MODE,
5998 };
5999
6000 struct rtw89_mlo_info {
6001 struct rtw89_wait_info wait;
6002 };
6003
6004 struct rtw89_beacon_track_info {
6005 bool is_data_ready;
6006 u32 tbtt_offset; /* in unit of microsecond */
6007 u16 bcn_timeout; /* in unit of millisecond */
6008
6009 /* The following are constant and set at association. */
6010 u8 dtim;
6011 u16 beacon_int;
6012 u16 low_bcn_th;
6013 u16 med_bcn_th;
6014 u16 high_bcn_th;
6015 u16 target_bcn_th;
6016 u16 outlier_low_bcn_th;
6017 u16 outlier_high_bcn_th;
6018 u32 close_bcn_intvl_th;
6019 u32 tbtt_diff_th;
6020 };
6021
6022 struct rtw89_dev {
6023 struct ieee80211_hw *hw;
6024 struct device *dev;
6025 const struct ieee80211_ops *ops;
6026
6027 bool dbcc_en;
6028 bool support_mlo;
6029 enum rtw89_mlo_dbcc_mode mlo_dbcc_mode;
6030 struct rtw89_hw_scan_info scan_info;
6031 const struct rtw89_chip_info *chip;
6032 const struct rtw89_chip_variant *variant;
6033 const struct rtw89_pci_info *pci_info;
6034 const struct rtw89_rfe_parms *rfe_parms;
6035 struct rtw89_hal hal;
6036 struct rtw89_beacon_track_info bcn_track;
6037 struct rtw89_mcc_info mcc;
6038 struct rtw89_mlo_info mlo;
6039 struct rtw89_mac_info mac;
6040 struct rtw89_fw_info fw;
6041 struct rtw89_hci_info hci;
6042 struct rtw89_efuse efuse;
6043 struct rtw89_traffic_stats stats;
6044 struct rtw89_rfe_data *rfe_data;
6045 enum rtw89_custid custid;
6046
6047 struct rtw89_sta_link __rcu *assoc_link_on_macid[RTW89_MAX_MAC_ID_NUM];
6048 refcount_t refcount_ap_info;
6049
6050 struct list_head rtwvifs_list;
6051 /* used to protect rf read write */
6052 struct mutex rf_mutex;
6053 struct workqueue_struct *txq_wq;
6054 struct work_struct txq_work;
6055 struct delayed_work txq_reinvoke_work;
6056 /* used to protect ba_list and forbid_ba_list */
6057 spinlock_t ba_lock;
6058 /* txqs to setup ba session */
6059 struct list_head ba_list;
6060 /* txqs to forbid ba session */
6061 struct list_head forbid_ba_list;
6062 struct work_struct ba_work;
6063 /* used to protect rpwm */
6064 spinlock_t rpwm_lock;
6065
6066 struct list_head tx_waits;
6067 struct wiphy_delayed_work tx_wait_work;
6068
6069 struct rtw89_tx_rpt tx_rpt;
6070
6071 struct rtw89_cam_info cam_info;
6072
6073 struct sk_buff_head c2h_queue;
6074 struct wiphy_work c2h_work;
6075 struct wiphy_work ips_work;
6076 struct wiphy_work cancel_6ghz_probe_work;
6077 struct work_struct load_firmware_work;
6078
6079 struct list_head early_h2c_list;
6080
6081 struct rtw89_ser ser;
6082
6083 DECLARE_BITMAP(hw_port, RTW89_PORT_NUM);
6084 DECLARE_BITMAP(mac_id_map, RTW89_MAX_MAC_ID_NUM);
6085 DECLARE_BITMAP(flags, NUM_OF_RTW89_FLAGS);
6086 DECLARE_BITMAP(pkt_offload, RTW89_MAX_PKT_OFLD_NUM);
6087 DECLARE_BITMAP(quirks, NUM_OF_RTW89_QUIRKS);
6088
6089 struct rtw89_phy_stat phystat;
6090 struct rtw89_rfk_wait_info rfk_wait;
6091 struct rtw89_dack_info dack;
6092 struct rtw89_iqk_info iqk;
6093 struct rtw89_dpk_info dpk;
6094 struct rtw89_rfk_mcc_info rfk_mcc;
6095 struct rtw89_lck_info lck;
6096 struct rtw89_rx_dck_info rx_dck;
6097 bool is_tssi_mode[RF_PATH_MAX];
6098 bool is_bt_iqk_timeout;
6099
6100 struct rtw89_fem_info fem;
6101 struct rtw89_txpwr_byrate byr[RTW89_BAND_NUM][RTW89_BYR_BW_NUM];
6102 struct rtw89_tssi_info tssi;
6103 struct rtw89_power_trim_info pwr_trim;
6104
6105 struct rtw89_cfo_tracking_info cfo_tracking;
6106 union {
6107 struct rtw89_phy_bb_gain_info ax;
6108 struct rtw89_phy_bb_gain_info_be be;
6109 } bb_gain;
6110 struct rtw89_phy_efuse_gain efuse_gain;
6111 struct rtw89_phy_ul_tb_info ul_tb_info;
6112 struct rtw89_antdiv_info antdiv;
6113
6114 struct rtw89_bb_ctx {
6115 enum rtw89_phy_idx phy_idx;
6116 struct rtw89_env_monitor_info env_monitor;
6117 struct rtw89_dig_info dig;
6118 struct rtw89_phy_ch_info ch_info;
6119 struct rtw89_edcca_bak edcca_bak;
6120 } bbs[RTW89_PHY_NUM];
6121
6122 struct wiphy_delayed_work track_work;
6123 struct wiphy_delayed_work track_ps_work;
6124 struct wiphy_delayed_work chanctx_work;
6125 struct wiphy_delayed_work coex_act1_work;
6126 struct wiphy_delayed_work coex_bt_devinfo_work;
6127 struct wiphy_delayed_work coex_rfk_chk_work;
6128 struct wiphy_delayed_work cfo_track_work;
6129 struct wiphy_delayed_work mcc_prepare_done_work;
6130 struct delayed_work forbid_ba_work;
6131 struct wiphy_delayed_work antdiv_work;
6132 struct rtw89_ppdu_sts_info ppdu_sts;
6133 u8 total_sta_assoc;
6134 bool scanning;
6135
6136 struct rtw89_regulatory_info regulatory;
6137 struct rtw89_sar_info sar;
6138 struct rtw89_tas_info tas;
6139 struct rtw89_ant_gain_info ant_gain;
6140
6141 struct rtw89_btc btc;
6142 enum rtw89_ps_mode ps_mode;
6143 bool lps_enabled;
6144 u8 ps_hang_cnt;
6145
6146 struct rtw89_wow_param wow;
6147
6148 /* napi structure */
6149 struct net_device *netdev;
6150 struct napi_struct napi;
6151 int napi_budget_countdown;
6152
6153 struct rtw89_debugfs *debugfs;
6154 struct rtw89_vif *pure_monitor_mode_vif;
6155
6156 /* HCI related data, keep last */
6157 u8 priv[] __aligned(sizeof(void *));
6158 };
6159
6160 struct rtw89_link_conf_container {
6161 struct ieee80211_bss_conf *link_conf[IEEE80211_MLD_MAX_NUM_LINKS];
6162 };
6163
6164 struct rtw89_vif_ml_trans {
6165 u16 mediate_links;
6166 u16 links_to_del;
6167 u16 links_to_add;
6168 };
6169
6170 #define RTW89_VIF_IDLE_LINK_ID 0
6171
6172 struct rtw89_vif {
6173 struct rtw89_dev *rtwdev;
6174 struct list_head list;
6175 struct list_head mgnt_entry;
6176 struct rtw89_link_conf_container __rcu *snap_link_confs;
6177
6178 u8 mac_addr[ETH_ALEN];
6179 __be32 ip_addr;
6180
6181 struct rtw89_traffic_stats stats;
6182 struct rtw89_traffic_stats stats_ps;
6183 u32 tdls_peer;
6184
6185 struct ieee80211_scan_ies *scan_ies;
6186 struct cfg80211_scan_request *scan_req;
6187
6188 struct rtw89_roc roc;
6189 bool offchan;
6190
6191 enum rtw89_mlo_mode mlo_mode;
6192 struct rtw89_vif_ml_trans ml_trans;
6193
6194 struct list_head dlink_pool;
6195 u8 links_inst_valid_num;
6196 DECLARE_BITMAP(links_inst_map, __RTW89_MLD_MAX_LINK_NUM);
6197 struct rtw89_vif_link *links[IEEE80211_MLD_MAX_NUM_LINKS];
6198 struct rtw89_vif_link links_inst[] __counted_by(links_inst_valid_num);
6199 };
6200
rtw89_vif_assign_link_is_valid(struct rtw89_vif_link ** rtwvif_link,const struct rtw89_vif * rtwvif,unsigned int link_id)6201 static inline bool rtw89_vif_assign_link_is_valid(struct rtw89_vif_link **rtwvif_link,
6202 const struct rtw89_vif *rtwvif,
6203 unsigned int link_id)
6204 {
6205 *rtwvif_link = rtwvif->links[link_id];
6206 return !!*rtwvif_link;
6207 }
6208
6209 #define rtw89_vif_for_each_link(rtwvif, rtwvif_link, link_id) \
6210 for (link_id = 0; link_id < IEEE80211_MLD_MAX_NUM_LINKS; link_id++) \
6211 if (rtw89_vif_assign_link_is_valid(&(rtwvif_link), rtwvif, link_id))
6212
6213 enum rtw89_sta_flags {
6214 RTW89_REMOTE_STA_IN_PS,
6215
6216 NUM_OF_RTW89_STA_FLAGS,
6217 };
6218
6219 struct rtw89_sta {
6220 struct rtw89_dev *rtwdev;
6221 struct rtw89_vif *rtwvif;
6222
6223 DECLARE_BITMAP(flags, NUM_OF_RTW89_STA_FLAGS);
6224
6225 bool disassoc;
6226
6227 struct sk_buff_head roc_queue;
6228
6229 struct rtw89_ampdu_params ampdu_params[IEEE80211_NUM_TIDS];
6230 DECLARE_BITMAP(ampdu_map, IEEE80211_NUM_TIDS);
6231
6232 DECLARE_BITMAP(pairwise_sec_cam_map, RTW89_MAX_SEC_CAM_NUM);
6233
6234 struct list_head dlink_pool;
6235 u8 links_inst_valid_num;
6236 DECLARE_BITMAP(links_inst_map, __RTW89_MLD_MAX_LINK_NUM);
6237 struct rtw89_sta_link *links[IEEE80211_MLD_MAX_NUM_LINKS];
6238 struct rtw89_sta_link links_inst[] __counted_by(links_inst_valid_num);
6239 };
6240
rtw89_sta_assign_link_is_valid(struct rtw89_sta_link ** rtwsta_link,const struct rtw89_sta * rtwsta,unsigned int link_id)6241 static inline bool rtw89_sta_assign_link_is_valid(struct rtw89_sta_link **rtwsta_link,
6242 const struct rtw89_sta *rtwsta,
6243 unsigned int link_id)
6244 {
6245 *rtwsta_link = rtwsta->links[link_id];
6246 return !!*rtwsta_link;
6247 }
6248
6249 #define rtw89_sta_for_each_link(rtwsta, rtwsta_link, link_id) \
6250 for (link_id = 0; link_id < IEEE80211_MLD_MAX_NUM_LINKS; link_id++) \
6251 if (rtw89_sta_assign_link_is_valid(&(rtwsta_link), rtwsta, link_id))
6252
rtw89_vif_get_main_macid(struct rtw89_vif * rtwvif)6253 static inline u8 rtw89_vif_get_main_macid(struct rtw89_vif *rtwvif)
6254 {
6255 /* const after init, so no need to check if active first */
6256 return rtwvif->links_inst[0].mac_id;
6257 }
6258
rtw89_vif_get_main_port(struct rtw89_vif * rtwvif)6259 static inline u8 rtw89_vif_get_main_port(struct rtw89_vif *rtwvif)
6260 {
6261 /* const after init, so no need to check if active first */
6262 return rtwvif->links_inst[0].port;
6263 }
6264
6265 static inline struct rtw89_vif_link *
rtw89_vif_get_link_inst(struct rtw89_vif * rtwvif,u8 index)6266 rtw89_vif_get_link_inst(struct rtw89_vif *rtwvif, u8 index)
6267 {
6268 if (index >= rtwvif->links_inst_valid_num ||
6269 !test_bit(index, rtwvif->links_inst_map))
6270 return NULL;
6271 return &rtwvif->links_inst[index];
6272 }
6273
6274 static inline
rtw89_vif_link_inst_get_index(struct rtw89_vif_link * rtwvif_link)6275 u8 rtw89_vif_link_inst_get_index(struct rtw89_vif_link *rtwvif_link)
6276 {
6277 struct rtw89_vif *rtwvif = rtwvif_link->rtwvif;
6278
6279 return rtwvif_link - rtwvif->links_inst;
6280 }
6281
rtw89_sta_get_main_macid(struct rtw89_sta * rtwsta)6282 static inline u8 rtw89_sta_get_main_macid(struct rtw89_sta *rtwsta)
6283 {
6284 /* const after init, so no need to check if active first */
6285 return rtwsta->links_inst[0].mac_id;
6286 }
6287
6288 static inline struct rtw89_sta_link *
rtw89_sta_get_link_inst(struct rtw89_sta * rtwsta,u8 index)6289 rtw89_sta_get_link_inst(struct rtw89_sta *rtwsta, u8 index)
6290 {
6291 if (index >= rtwsta->links_inst_valid_num ||
6292 !test_bit(index, rtwsta->links_inst_map))
6293 return NULL;
6294 return &rtwsta->links_inst[index];
6295 }
6296
6297 static inline
rtw89_sta_link_inst_get_index(struct rtw89_sta_link * rtwsta_link)6298 u8 rtw89_sta_link_inst_get_index(struct rtw89_sta_link *rtwsta_link)
6299 {
6300 struct rtw89_sta *rtwsta = rtwsta_link->rtwsta;
6301
6302 return rtwsta_link - rtwsta->links_inst;
6303 }
6304
rtw89_assoc_link_set(struct rtw89_sta_link * rtwsta_link)6305 static inline void rtw89_assoc_link_set(struct rtw89_sta_link *rtwsta_link)
6306 {
6307 struct rtw89_sta *rtwsta = rtwsta_link->rtwsta;
6308 struct rtw89_dev *rtwdev = rtwsta->rtwdev;
6309
6310 rcu_assign_pointer(rtwdev->assoc_link_on_macid[rtwsta_link->mac_id],
6311 rtwsta_link);
6312 }
6313
rtw89_assoc_link_clr(struct rtw89_sta_link * rtwsta_link)6314 static inline void rtw89_assoc_link_clr(struct rtw89_sta_link *rtwsta_link)
6315 {
6316 struct rtw89_sta *rtwsta = rtwsta_link->rtwsta;
6317 struct rtw89_dev *rtwdev = rtwsta->rtwdev;
6318
6319 rcu_assign_pointer(rtwdev->assoc_link_on_macid[rtwsta_link->mac_id],
6320 NULL);
6321 synchronize_rcu();
6322 }
6323
6324 static inline struct rtw89_sta_link *
rtw89_assoc_link_rcu_dereference(struct rtw89_dev * rtwdev,u8 macid)6325 rtw89_assoc_link_rcu_dereference(struct rtw89_dev *rtwdev, u8 macid)
6326 {
6327 return rcu_dereference(rtwdev->assoc_link_on_macid[macid]);
6328 }
6329
6330 #define rtw89_get_designated_link(links_holder) \
6331 ({ \
6332 typeof(links_holder) p = links_holder; \
6333 list_first_entry_or_null(&p->dlink_pool, typeof(*p->links_inst), dlink_schd); \
6334 })
6335
rtw89_tx_wait_release(struct rtw89_tx_wait_info * wait)6336 static inline void rtw89_tx_wait_release(struct rtw89_tx_wait_info *wait)
6337 {
6338 dev_kfree_skb_any(wait->skb);
6339 kfree_rcu(wait, rcu_head);
6340 }
6341
rtw89_tx_wait_list_clear(struct rtw89_dev * rtwdev)6342 static inline void rtw89_tx_wait_list_clear(struct rtw89_dev *rtwdev)
6343 {
6344 struct rtw89_tx_wait_info *wait, *tmp;
6345
6346 lockdep_assert_wiphy(rtwdev->hw->wiphy);
6347
6348 list_for_each_entry_safe(wait, tmp, &rtwdev->tx_waits, list) {
6349 if (!completion_done(&wait->completion))
6350 continue;
6351 list_del(&wait->list);
6352 rtw89_tx_wait_release(wait);
6353 }
6354 }
6355
rtw89_hci_tx_write(struct rtw89_dev * rtwdev,struct rtw89_core_tx_request * tx_req)6356 static inline int rtw89_hci_tx_write(struct rtw89_dev *rtwdev,
6357 struct rtw89_core_tx_request *tx_req)
6358 {
6359 return rtwdev->hci.ops->tx_write(rtwdev, tx_req);
6360 }
6361
rtw89_hci_reset(struct rtw89_dev * rtwdev)6362 static inline void rtw89_hci_reset(struct rtw89_dev *rtwdev)
6363 {
6364 rtwdev->hci.ops->reset(rtwdev);
6365 /* hci.ops->reset must complete all pending TX wait SKBs */
6366 rtw89_tx_wait_list_clear(rtwdev);
6367 }
6368
rtw89_hci_start(struct rtw89_dev * rtwdev)6369 static inline int rtw89_hci_start(struct rtw89_dev *rtwdev)
6370 {
6371 return rtwdev->hci.ops->start(rtwdev);
6372 }
6373
rtw89_hci_stop(struct rtw89_dev * rtwdev)6374 static inline void rtw89_hci_stop(struct rtw89_dev *rtwdev)
6375 {
6376 rtwdev->hci.ops->stop(rtwdev);
6377 }
6378
rtw89_hci_deinit(struct rtw89_dev * rtwdev)6379 static inline int rtw89_hci_deinit(struct rtw89_dev *rtwdev)
6380 {
6381 return rtwdev->hci.ops->deinit(rtwdev);
6382 }
6383
rtw89_hci_pause(struct rtw89_dev * rtwdev,bool pause)6384 static inline void rtw89_hci_pause(struct rtw89_dev *rtwdev, bool pause)
6385 {
6386 rtwdev->hci.ops->pause(rtwdev, pause);
6387 }
6388
rtw89_hci_switch_mode(struct rtw89_dev * rtwdev,bool low_power)6389 static inline void rtw89_hci_switch_mode(struct rtw89_dev *rtwdev, bool low_power)
6390 {
6391 rtwdev->hci.ops->switch_mode(rtwdev, low_power);
6392 }
6393
rtw89_hci_recalc_int_mit(struct rtw89_dev * rtwdev)6394 static inline void rtw89_hci_recalc_int_mit(struct rtw89_dev *rtwdev)
6395 {
6396 rtwdev->hci.ops->recalc_int_mit(rtwdev);
6397 }
6398
rtw89_hci_check_and_reclaim_tx_resource(struct rtw89_dev * rtwdev,u8 txch)6399 static inline u32 rtw89_hci_check_and_reclaim_tx_resource(struct rtw89_dev *rtwdev, u8 txch)
6400 {
6401 return rtwdev->hci.ops->check_and_reclaim_tx_resource(rtwdev, txch);
6402 }
6403
rtw89_hci_tx_kick_off(struct rtw89_dev * rtwdev,u8 txch)6404 static inline void rtw89_hci_tx_kick_off(struct rtw89_dev *rtwdev, u8 txch)
6405 {
6406 return rtwdev->hci.ops->tx_kick_off(rtwdev, txch);
6407 }
6408
rtw89_hci_mac_pre_deinit(struct rtw89_dev * rtwdev)6409 static inline int rtw89_hci_mac_pre_deinit(struct rtw89_dev *rtwdev)
6410 {
6411 return rtwdev->hci.ops->mac_pre_deinit(rtwdev);
6412 }
6413
rtw89_hci_flush_queues(struct rtw89_dev * rtwdev,u32 queues,bool drop)6414 static inline void rtw89_hci_flush_queues(struct rtw89_dev *rtwdev, u32 queues,
6415 bool drop)
6416 {
6417 if (!test_bit(RTW89_FLAG_POWERON, rtwdev->flags))
6418 return;
6419
6420 if (rtwdev->hci.ops->flush_queues)
6421 return rtwdev->hci.ops->flush_queues(rtwdev, queues, drop);
6422 }
6423
rtw89_hci_recovery_start(struct rtw89_dev * rtwdev)6424 static inline void rtw89_hci_recovery_start(struct rtw89_dev *rtwdev)
6425 {
6426 if (rtwdev->hci.ops->recovery_start)
6427 rtwdev->hci.ops->recovery_start(rtwdev);
6428 }
6429
rtw89_hci_recovery_complete(struct rtw89_dev * rtwdev)6430 static inline void rtw89_hci_recovery_complete(struct rtw89_dev *rtwdev)
6431 {
6432 if (rtwdev->hci.ops->recovery_complete)
6433 rtwdev->hci.ops->recovery_complete(rtwdev);
6434 }
6435
rtw89_hci_enable_intr(struct rtw89_dev * rtwdev)6436 static inline void rtw89_hci_enable_intr(struct rtw89_dev *rtwdev)
6437 {
6438 if (rtwdev->hci.ops->enable_intr)
6439 rtwdev->hci.ops->enable_intr(rtwdev);
6440 }
6441
rtw89_hci_disable_intr(struct rtw89_dev * rtwdev)6442 static inline void rtw89_hci_disable_intr(struct rtw89_dev *rtwdev)
6443 {
6444 if (rtwdev->hci.ops->disable_intr)
6445 rtwdev->hci.ops->disable_intr(rtwdev);
6446 }
6447
rtw89_hci_ctrl_txdma_ch(struct rtw89_dev * rtwdev,bool enable)6448 static inline void rtw89_hci_ctrl_txdma_ch(struct rtw89_dev *rtwdev, bool enable)
6449 {
6450 if (rtwdev->hci.ops->ctrl_txdma_ch)
6451 rtwdev->hci.ops->ctrl_txdma_ch(rtwdev, enable);
6452 }
6453
rtw89_hci_ctrl_txdma_fw_ch(struct rtw89_dev * rtwdev,bool enable)6454 static inline void rtw89_hci_ctrl_txdma_fw_ch(struct rtw89_dev *rtwdev, bool enable)
6455 {
6456 if (rtwdev->hci.ops->ctrl_txdma_fw_ch)
6457 rtwdev->hci.ops->ctrl_txdma_fw_ch(rtwdev, enable);
6458 }
6459
rtw89_hci_ctrl_trxhci(struct rtw89_dev * rtwdev,bool enable)6460 static inline void rtw89_hci_ctrl_trxhci(struct rtw89_dev *rtwdev, bool enable)
6461 {
6462 if (rtwdev->hci.ops->ctrl_trxhci)
6463 rtwdev->hci.ops->ctrl_trxhci(rtwdev, enable);
6464 }
6465
rtw89_hci_poll_txdma_ch_idle(struct rtw89_dev * rtwdev)6466 static inline int rtw89_hci_poll_txdma_ch_idle(struct rtw89_dev *rtwdev)
6467 {
6468 int ret = 0;
6469
6470 if (rtwdev->hci.ops->poll_txdma_ch_idle)
6471 ret = rtwdev->hci.ops->poll_txdma_ch_idle(rtwdev);
6472 return ret;
6473 }
6474
rtw89_hci_clr_idx_all(struct rtw89_dev * rtwdev)6475 static inline void rtw89_hci_clr_idx_all(struct rtw89_dev *rtwdev)
6476 {
6477 if (rtwdev->hci.ops->clr_idx_all)
6478 rtwdev->hci.ops->clr_idx_all(rtwdev);
6479 }
6480
rtw89_hci_rst_bdram(struct rtw89_dev * rtwdev)6481 static inline int rtw89_hci_rst_bdram(struct rtw89_dev *rtwdev)
6482 {
6483 int ret = 0;
6484
6485 if (rtwdev->hci.ops->rst_bdram)
6486 ret = rtwdev->hci.ops->rst_bdram(rtwdev);
6487 return ret;
6488 }
6489
rtw89_hci_clear(struct rtw89_dev * rtwdev,struct pci_dev * pdev)6490 static inline void rtw89_hci_clear(struct rtw89_dev *rtwdev, struct pci_dev *pdev)
6491 {
6492 if (rtwdev->hci.ops->clear)
6493 rtwdev->hci.ops->clear(rtwdev, pdev);
6494 }
6495
6496 static inline
RTW89_TX_SKB_CB(struct sk_buff * skb)6497 struct rtw89_tx_skb_data *RTW89_TX_SKB_CB(struct sk_buff *skb)
6498 {
6499 /*
6500 * This should be used by/after rtw89_hci_tx_write() and before doing
6501 * ieee80211_tx_info_clear_status().
6502 */
6503 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
6504
6505 return (struct rtw89_tx_skb_data *)info->driver_data;
6506 }
6507
rtw89_read8(struct rtw89_dev * rtwdev,u32 addr)6508 static inline u8 rtw89_read8(struct rtw89_dev *rtwdev, u32 addr)
6509 {
6510 return rtwdev->hci.ops->read8(rtwdev, addr);
6511 }
6512
rtw89_read16(struct rtw89_dev * rtwdev,u32 addr)6513 static inline u16 rtw89_read16(struct rtw89_dev *rtwdev, u32 addr)
6514 {
6515 return rtwdev->hci.ops->read16(rtwdev, addr);
6516 }
6517
rtw89_read32(struct rtw89_dev * rtwdev,u32 addr)6518 static inline u32 rtw89_read32(struct rtw89_dev *rtwdev, u32 addr)
6519 {
6520 return rtwdev->hci.ops->read32(rtwdev, addr);
6521 }
6522
rtw89_write8(struct rtw89_dev * rtwdev,u32 addr,u8 data)6523 static inline void rtw89_write8(struct rtw89_dev *rtwdev, u32 addr, u8 data)
6524 {
6525 rtwdev->hci.ops->write8(rtwdev, addr, data);
6526 }
6527
rtw89_write16(struct rtw89_dev * rtwdev,u32 addr,u16 data)6528 static inline void rtw89_write16(struct rtw89_dev *rtwdev, u32 addr, u16 data)
6529 {
6530 rtwdev->hci.ops->write16(rtwdev, addr, data);
6531 }
6532
rtw89_write32(struct rtw89_dev * rtwdev,u32 addr,u32 data)6533 static inline void rtw89_write32(struct rtw89_dev *rtwdev, u32 addr, u32 data)
6534 {
6535 rtwdev->hci.ops->write32(rtwdev, addr, data);
6536 }
6537
6538 static inline void
rtw89_write8_set(struct rtw89_dev * rtwdev,u32 addr,u8 bit)6539 rtw89_write8_set(struct rtw89_dev *rtwdev, u32 addr, u8 bit)
6540 {
6541 u8 val;
6542
6543 val = rtw89_read8(rtwdev, addr);
6544 rtw89_write8(rtwdev, addr, val | bit);
6545 }
6546
6547 static inline void
rtw89_write16_set(struct rtw89_dev * rtwdev,u32 addr,u16 bit)6548 rtw89_write16_set(struct rtw89_dev *rtwdev, u32 addr, u16 bit)
6549 {
6550 u16 val;
6551
6552 val = rtw89_read16(rtwdev, addr);
6553 rtw89_write16(rtwdev, addr, val | bit);
6554 }
6555
6556 static inline void
rtw89_write32_set(struct rtw89_dev * rtwdev,u32 addr,u32 bit)6557 rtw89_write32_set(struct rtw89_dev *rtwdev, u32 addr, u32 bit)
6558 {
6559 u32 val;
6560
6561 val = rtw89_read32(rtwdev, addr);
6562 rtw89_write32(rtwdev, addr, val | bit);
6563 }
6564
6565 static inline void
rtw89_write8_clr(struct rtw89_dev * rtwdev,u32 addr,u8 bit)6566 rtw89_write8_clr(struct rtw89_dev *rtwdev, u32 addr, u8 bit)
6567 {
6568 u8 val;
6569
6570 val = rtw89_read8(rtwdev, addr);
6571 rtw89_write8(rtwdev, addr, val & ~bit);
6572 }
6573
6574 static inline void
rtw89_write16_clr(struct rtw89_dev * rtwdev,u32 addr,u16 bit)6575 rtw89_write16_clr(struct rtw89_dev *rtwdev, u32 addr, u16 bit)
6576 {
6577 u16 val;
6578
6579 val = rtw89_read16(rtwdev, addr);
6580 rtw89_write16(rtwdev, addr, val & ~bit);
6581 }
6582
6583 static inline void
rtw89_write32_clr(struct rtw89_dev * rtwdev,u32 addr,u32 bit)6584 rtw89_write32_clr(struct rtw89_dev *rtwdev, u32 addr, u32 bit)
6585 {
6586 u32 val;
6587
6588 val = rtw89_read32(rtwdev, addr);
6589 rtw89_write32(rtwdev, addr, val & ~bit);
6590 }
6591
6592 static inline u32
rtw89_read32_mask(struct rtw89_dev * rtwdev,u32 addr,u32 mask)6593 rtw89_read32_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask)
6594 {
6595 u32 shift = __ffs(mask);
6596 u32 orig;
6597 u32 ret;
6598
6599 orig = rtw89_read32(rtwdev, addr);
6600 ret = (orig & mask) >> shift;
6601
6602 return ret;
6603 }
6604
6605 static inline u16
rtw89_read16_mask(struct rtw89_dev * rtwdev,u32 addr,u32 mask)6606 rtw89_read16_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask)
6607 {
6608 u32 shift = __ffs(mask);
6609 u32 orig;
6610 u32 ret;
6611
6612 orig = rtw89_read16(rtwdev, addr);
6613 ret = (orig & mask) >> shift;
6614
6615 return ret;
6616 }
6617
6618 static inline u8
rtw89_read8_mask(struct rtw89_dev * rtwdev,u32 addr,u32 mask)6619 rtw89_read8_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask)
6620 {
6621 u32 shift = __ffs(mask);
6622 u32 orig;
6623 u32 ret;
6624
6625 orig = rtw89_read8(rtwdev, addr);
6626 ret = (orig & mask) >> shift;
6627
6628 return ret;
6629 }
6630
6631 static inline void
rtw89_write32_mask(struct rtw89_dev * rtwdev,u32 addr,u32 mask,u32 data)6632 rtw89_write32_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u32 data)
6633 {
6634 u32 shift = __ffs(mask);
6635 u32 orig;
6636 u32 set;
6637
6638 WARN(addr & 0x3, "should be 4-byte aligned, addr = 0x%08x\n", addr);
6639
6640 orig = rtw89_read32(rtwdev, addr);
6641 set = (orig & ~mask) | ((data << shift) & mask);
6642 rtw89_write32(rtwdev, addr, set);
6643 }
6644
6645 static inline void
rtw89_write16_mask(struct rtw89_dev * rtwdev,u32 addr,u32 mask,u16 data)6646 rtw89_write16_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u16 data)
6647 {
6648 u32 shift;
6649 u16 orig, set;
6650
6651 mask &= 0xffff;
6652 shift = __ffs(mask);
6653
6654 orig = rtw89_read16(rtwdev, addr);
6655 set = (orig & ~mask) | ((data << shift) & mask);
6656 rtw89_write16(rtwdev, addr, set);
6657 }
6658
6659 static inline void
rtw89_write8_mask(struct rtw89_dev * rtwdev,u32 addr,u32 mask,u8 data)6660 rtw89_write8_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u8 data)
6661 {
6662 u32 shift;
6663 u8 orig, set;
6664
6665 mask &= 0xff;
6666 shift = __ffs(mask);
6667
6668 orig = rtw89_read8(rtwdev, addr);
6669 set = (orig & ~mask) | ((data << shift) & mask);
6670 rtw89_write8(rtwdev, addr, set);
6671 }
6672
6673 static inline u32
rtw89_read_rf(struct rtw89_dev * rtwdev,enum rtw89_rf_path rf_path,u32 addr,u32 mask)6674 rtw89_read_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
6675 u32 addr, u32 mask)
6676 {
6677 u32 val;
6678
6679 mutex_lock(&rtwdev->rf_mutex);
6680 val = rtwdev->chip->ops->read_rf(rtwdev, rf_path, addr, mask);
6681 mutex_unlock(&rtwdev->rf_mutex);
6682
6683 return val;
6684 }
6685
6686 static inline void
rtw89_write_rf(struct rtw89_dev * rtwdev,enum rtw89_rf_path rf_path,u32 addr,u32 mask,u32 data)6687 rtw89_write_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
6688 u32 addr, u32 mask, u32 data)
6689 {
6690 mutex_lock(&rtwdev->rf_mutex);
6691 rtwdev->chip->ops->write_rf(rtwdev, rf_path, addr, mask, data);
6692 mutex_unlock(&rtwdev->rf_mutex);
6693 }
6694
rtw89_read32_pci_cfg(struct rtw89_dev * rtwdev,u32 addr)6695 static inline u32 rtw89_read32_pci_cfg(struct rtw89_dev *rtwdev, u32 addr)
6696 {
6697 if (rtwdev->hci.type != RTW89_HCI_TYPE_PCIE ||
6698 !rtwdev->hci.ops->read32_pci_cfg)
6699 return RTW89_R32_EA;
6700
6701 return rtwdev->hci.ops->read32_pci_cfg(rtwdev, addr);
6702 }
6703
rtw89_txq_to_txq(struct rtw89_txq * rtwtxq)6704 static inline struct ieee80211_txq *rtw89_txq_to_txq(struct rtw89_txq *rtwtxq)
6705 {
6706 void *p = rtwtxq;
6707
6708 return container_of(p, struct ieee80211_txq, drv_priv);
6709 }
6710
rtw89_core_txq_init(struct rtw89_dev * rtwdev,struct ieee80211_txq * txq)6711 static inline void rtw89_core_txq_init(struct rtw89_dev *rtwdev,
6712 struct ieee80211_txq *txq)
6713 {
6714 struct rtw89_txq *rtwtxq;
6715
6716 if (!txq)
6717 return;
6718
6719 rtwtxq = (struct rtw89_txq *)txq->drv_priv;
6720 INIT_LIST_HEAD(&rtwtxq->list);
6721 }
6722
rtwvif_to_vif(struct rtw89_vif * rtwvif)6723 static inline struct ieee80211_vif *rtwvif_to_vif(struct rtw89_vif *rtwvif)
6724 {
6725 void *p = rtwvif;
6726
6727 return container_of(p, struct ieee80211_vif, drv_priv);
6728 }
6729
rtwvif_to_vif_safe(struct rtw89_vif * rtwvif)6730 static inline struct ieee80211_vif *rtwvif_to_vif_safe(struct rtw89_vif *rtwvif)
6731 {
6732 return rtwvif ? rtwvif_to_vif(rtwvif) : NULL;
6733 }
6734
6735 static inline
rtwvif_link_to_vif(struct rtw89_vif_link * rtwvif_link)6736 struct ieee80211_vif *rtwvif_link_to_vif(struct rtw89_vif_link *rtwvif_link)
6737 {
6738 return rtwvif_to_vif(rtwvif_link->rtwvif);
6739 }
6740
6741 static inline
rtwvif_link_to_vif_safe(struct rtw89_vif_link * rtwvif_link)6742 struct ieee80211_vif *rtwvif_link_to_vif_safe(struct rtw89_vif_link *rtwvif_link)
6743 {
6744 return rtwvif_link ? rtwvif_link_to_vif(rtwvif_link) : NULL;
6745 }
6746
vif_to_rtwvif(struct ieee80211_vif * vif)6747 static inline struct rtw89_vif *vif_to_rtwvif(struct ieee80211_vif *vif)
6748 {
6749 return (struct rtw89_vif *)vif->drv_priv;
6750 }
6751
vif_to_rtwvif_safe(struct ieee80211_vif * vif)6752 static inline struct rtw89_vif *vif_to_rtwvif_safe(struct ieee80211_vif *vif)
6753 {
6754 return vif ? vif_to_rtwvif(vif) : NULL;
6755 }
6756
rtwsta_to_sta(struct rtw89_sta * rtwsta)6757 static inline struct ieee80211_sta *rtwsta_to_sta(struct rtw89_sta *rtwsta)
6758 {
6759 void *p = rtwsta;
6760
6761 return container_of(p, struct ieee80211_sta, drv_priv);
6762 }
6763
rtwsta_to_sta_safe(struct rtw89_sta * rtwsta)6764 static inline struct ieee80211_sta *rtwsta_to_sta_safe(struct rtw89_sta *rtwsta)
6765 {
6766 return rtwsta ? rtwsta_to_sta(rtwsta) : NULL;
6767 }
6768
6769 static inline
rtwsta_link_to_sta(struct rtw89_sta_link * rtwsta_link)6770 struct ieee80211_sta *rtwsta_link_to_sta(struct rtw89_sta_link *rtwsta_link)
6771 {
6772 return rtwsta_to_sta(rtwsta_link->rtwsta);
6773 }
6774
6775 static inline
rtwsta_link_to_sta_safe(struct rtw89_sta_link * rtwsta_link)6776 struct ieee80211_sta *rtwsta_link_to_sta_safe(struct rtw89_sta_link *rtwsta_link)
6777 {
6778 return rtwsta_link ? rtwsta_link_to_sta(rtwsta_link) : NULL;
6779 }
6780
sta_to_rtwsta(struct ieee80211_sta * sta)6781 static inline struct rtw89_sta *sta_to_rtwsta(struct ieee80211_sta *sta)
6782 {
6783 return (struct rtw89_sta *)sta->drv_priv;
6784 }
6785
sta_to_rtwsta_safe(struct ieee80211_sta * sta)6786 static inline struct rtw89_sta *sta_to_rtwsta_safe(struct ieee80211_sta *sta)
6787 {
6788 return sta ? sta_to_rtwsta(sta) : NULL;
6789 }
6790
6791 static inline struct ieee80211_bss_conf *
__rtw89_vif_rcu_dereference_link(struct rtw89_vif_link * rtwvif_link,bool * nolink)6792 __rtw89_vif_rcu_dereference_link(struct rtw89_vif_link *rtwvif_link, bool *nolink)
6793 {
6794 struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link);
6795 struct rtw89_vif *rtwvif = rtwvif_link->rtwvif;
6796 struct rtw89_link_conf_container *snap;
6797 struct ieee80211_bss_conf *bss_conf;
6798
6799 snap = rcu_dereference(rtwvif->snap_link_confs);
6800 if (snap) {
6801 bss_conf = snap->link_conf[rtwvif_link->link_id];
6802 goto out;
6803 }
6804
6805 bss_conf = rcu_dereference(vif->link_conf[rtwvif_link->link_id]);
6806
6807 out:
6808 if (unlikely(!bss_conf)) {
6809 *nolink = true;
6810 return &vif->bss_conf;
6811 }
6812
6813 *nolink = false;
6814 return bss_conf;
6815 }
6816
6817 #define rtw89_vif_rcu_dereference_link(rtwvif_link, assert) \
6818 ({ \
6819 typeof(rtwvif_link) p = rtwvif_link; \
6820 struct ieee80211_bss_conf *bss_conf; \
6821 bool nolink; \
6822 \
6823 bss_conf = __rtw89_vif_rcu_dereference_link(p, &nolink); \
6824 if (unlikely(nolink) && (assert)) \
6825 rtw89_err(p->rtwvif->rtwdev, \
6826 "%s: cannot find exact bss_conf for link_id %u\n",\
6827 __func__, p->link_id); \
6828 bss_conf; \
6829 })
6830
6831 static inline struct ieee80211_link_sta *
__rtw89_sta_rcu_dereference_link(struct rtw89_sta_link * rtwsta_link,bool * nolink)6832 __rtw89_sta_rcu_dereference_link(struct rtw89_sta_link *rtwsta_link, bool *nolink)
6833 {
6834 struct ieee80211_sta *sta = rtwsta_link_to_sta(rtwsta_link);
6835 struct ieee80211_link_sta *link_sta;
6836
6837 link_sta = rcu_dereference(sta->link[rtwsta_link->link_id]);
6838 if (unlikely(!link_sta)) {
6839 *nolink = true;
6840 return &sta->deflink;
6841 }
6842
6843 *nolink = false;
6844 return link_sta;
6845 }
6846
6847 #define rtw89_sta_rcu_dereference_link(rtwsta_link, assert) \
6848 ({ \
6849 typeof(rtwsta_link) p = rtwsta_link; \
6850 struct ieee80211_link_sta *link_sta; \
6851 bool nolink; \
6852 \
6853 link_sta = __rtw89_sta_rcu_dereference_link(p, &nolink); \
6854 if (unlikely(nolink) && (assert)) \
6855 rtw89_err(p->rtwsta->rtwdev, \
6856 "%s: cannot find exact link_sta for link_id %u\n",\
6857 __func__, p->link_id); \
6858 link_sta; \
6859 })
6860
rtw89_hw_to_rate_info_bw(enum rtw89_bandwidth hw_bw)6861 static inline u8 rtw89_hw_to_rate_info_bw(enum rtw89_bandwidth hw_bw)
6862 {
6863 if (hw_bw == RTW89_CHANNEL_WIDTH_160)
6864 return RATE_INFO_BW_160;
6865 else if (hw_bw == RTW89_CHANNEL_WIDTH_80)
6866 return RATE_INFO_BW_80;
6867 else if (hw_bw == RTW89_CHANNEL_WIDTH_40)
6868 return RATE_INFO_BW_40;
6869 else
6870 return RATE_INFO_BW_20;
6871 }
6872
6873 static inline
rtw89_hw_to_nl80211_band(enum rtw89_band hw_band)6874 enum nl80211_band rtw89_hw_to_nl80211_band(enum rtw89_band hw_band)
6875 {
6876 switch (hw_band) {
6877 default:
6878 case RTW89_BAND_2G:
6879 return NL80211_BAND_2GHZ;
6880 case RTW89_BAND_5G:
6881 return NL80211_BAND_5GHZ;
6882 case RTW89_BAND_6G:
6883 return NL80211_BAND_6GHZ;
6884 }
6885 }
6886
6887 static inline
rtw89_nl80211_to_hw_band(enum nl80211_band nl_band)6888 enum rtw89_band rtw89_nl80211_to_hw_band(enum nl80211_band nl_band)
6889 {
6890 switch (nl_band) {
6891 default:
6892 case NL80211_BAND_2GHZ:
6893 return RTW89_BAND_2G;
6894 case NL80211_BAND_5GHZ:
6895 return RTW89_BAND_5G;
6896 case NL80211_BAND_6GHZ:
6897 return RTW89_BAND_6G;
6898 }
6899 }
6900
6901 static inline
nl_to_rtw89_bandwidth(enum nl80211_chan_width width)6902 enum rtw89_bandwidth nl_to_rtw89_bandwidth(enum nl80211_chan_width width)
6903 {
6904 switch (width) {
6905 default:
6906 WARN(1, "Not support bandwidth %d\n", width);
6907 fallthrough;
6908 case NL80211_CHAN_WIDTH_20_NOHT:
6909 case NL80211_CHAN_WIDTH_20:
6910 return RTW89_CHANNEL_WIDTH_20;
6911 case NL80211_CHAN_WIDTH_40:
6912 return RTW89_CHANNEL_WIDTH_40;
6913 case NL80211_CHAN_WIDTH_80:
6914 return RTW89_CHANNEL_WIDTH_80;
6915 case NL80211_CHAN_WIDTH_160:
6916 return RTW89_CHANNEL_WIDTH_160;
6917 }
6918 }
6919
6920 static inline
rtw89_he_rua_to_ru_alloc(u16 rua)6921 enum nl80211_he_ru_alloc rtw89_he_rua_to_ru_alloc(u16 rua)
6922 {
6923 switch (rua) {
6924 default:
6925 WARN(1, "Invalid RU allocation: %d\n", rua);
6926 fallthrough;
6927 case 0 ... 36:
6928 return NL80211_RATE_INFO_HE_RU_ALLOC_26;
6929 case 37 ... 52:
6930 return NL80211_RATE_INFO_HE_RU_ALLOC_52;
6931 case 53 ... 60:
6932 return NL80211_RATE_INFO_HE_RU_ALLOC_106;
6933 case 61 ... 64:
6934 return NL80211_RATE_INFO_HE_RU_ALLOC_242;
6935 case 65 ... 66:
6936 return NL80211_RATE_INFO_HE_RU_ALLOC_484;
6937 case 67:
6938 return NL80211_RATE_INFO_HE_RU_ALLOC_996;
6939 case 68:
6940 return NL80211_RATE_INFO_HE_RU_ALLOC_2x996;
6941 }
6942 }
6943
6944 static inline
rtw89_get_addr_cam_of(struct rtw89_vif_link * rtwvif_link,struct rtw89_sta_link * rtwsta_link)6945 struct rtw89_addr_cam_entry *rtw89_get_addr_cam_of(struct rtw89_vif_link *rtwvif_link,
6946 struct rtw89_sta_link *rtwsta_link)
6947 {
6948 if (rtwsta_link) {
6949 struct ieee80211_sta *sta = rtwsta_link_to_sta(rtwsta_link);
6950
6951 if (rtwvif_link->net_type == RTW89_NET_TYPE_AP_MODE || sta->tdls)
6952 return &rtwsta_link->addr_cam;
6953 }
6954 return &rtwvif_link->addr_cam;
6955 }
6956
6957 static inline
rtw89_get_bssid_cam_of(struct rtw89_vif_link * rtwvif_link,struct rtw89_sta_link * rtwsta_link)6958 struct rtw89_bssid_cam_entry *rtw89_get_bssid_cam_of(struct rtw89_vif_link *rtwvif_link,
6959 struct rtw89_sta_link *rtwsta_link)
6960 {
6961 if (rtwsta_link) {
6962 struct ieee80211_sta *sta = rtwsta_link_to_sta(rtwsta_link);
6963
6964 if (sta->tdls)
6965 return &rtwsta_link->bssid_cam;
6966 }
6967 return &rtwvif_link->bssid_cam;
6968 }
6969
6970 static inline
rtw89_chip_set_channel_prepare(struct rtw89_dev * rtwdev,struct rtw89_channel_help_params * p,const struct rtw89_chan * chan,enum rtw89_mac_idx mac_idx,enum rtw89_phy_idx phy_idx)6971 void rtw89_chip_set_channel_prepare(struct rtw89_dev *rtwdev,
6972 struct rtw89_channel_help_params *p,
6973 const struct rtw89_chan *chan,
6974 enum rtw89_mac_idx mac_idx,
6975 enum rtw89_phy_idx phy_idx)
6976 {
6977 rtwdev->chip->ops->set_channel_help(rtwdev, true, p, chan,
6978 mac_idx, phy_idx);
6979 }
6980
6981 static inline
rtw89_chip_set_channel_done(struct rtw89_dev * rtwdev,struct rtw89_channel_help_params * p,const struct rtw89_chan * chan,enum rtw89_mac_idx mac_idx,enum rtw89_phy_idx phy_idx)6982 void rtw89_chip_set_channel_done(struct rtw89_dev *rtwdev,
6983 struct rtw89_channel_help_params *p,
6984 const struct rtw89_chan *chan,
6985 enum rtw89_mac_idx mac_idx,
6986 enum rtw89_phy_idx phy_idx)
6987 {
6988 rtwdev->chip->ops->set_channel_help(rtwdev, false, p, chan,
6989 mac_idx, phy_idx);
6990 }
6991
6992 static inline
rtw89_chandef_get(struct rtw89_dev * rtwdev,enum rtw89_chanctx_idx idx)6993 const struct cfg80211_chan_def *rtw89_chandef_get(struct rtw89_dev *rtwdev,
6994 enum rtw89_chanctx_idx idx)
6995 {
6996 struct rtw89_hal *hal = &rtwdev->hal;
6997 enum rtw89_chanctx_idx roc_idx = atomic_read(&hal->roc_chanctx_idx);
6998
6999 if (roc_idx == idx)
7000 return &hal->roc_chandef;
7001
7002 return &hal->chanctx[idx].chandef;
7003 }
7004
7005 static inline
rtw89_chan_get(struct rtw89_dev * rtwdev,enum rtw89_chanctx_idx idx)7006 const struct rtw89_chan *rtw89_chan_get(struct rtw89_dev *rtwdev,
7007 enum rtw89_chanctx_idx idx)
7008 {
7009 struct rtw89_hal *hal = &rtwdev->hal;
7010
7011 return &hal->chanctx[idx].chan;
7012 }
7013
7014 static inline
rtw89_chan_rcd_get(struct rtw89_dev * rtwdev,enum rtw89_chanctx_idx idx)7015 const struct rtw89_chan_rcd *rtw89_chan_rcd_get(struct rtw89_dev *rtwdev,
7016 enum rtw89_chanctx_idx idx)
7017 {
7018 struct rtw89_hal *hal = &rtwdev->hal;
7019
7020 return &hal->chanctx[idx].rcd;
7021 }
7022
7023 static inline
rtw89_chan_rcd_get_by_chan(const struct rtw89_chan * chan)7024 const struct rtw89_chan_rcd *rtw89_chan_rcd_get_by_chan(const struct rtw89_chan *chan)
7025 {
7026 const struct rtw89_chanctx *chanctx =
7027 container_of_const(chan, struct rtw89_chanctx, chan);
7028
7029 return &chanctx->rcd;
7030 }
7031
7032 static inline
rtw89_scan_chan_get(struct rtw89_dev * rtwdev)7033 const struct rtw89_chan *rtw89_scan_chan_get(struct rtw89_dev *rtwdev)
7034 {
7035 struct rtw89_vif_link *rtwvif_link = rtwdev->scan_info.scanning_vif;
7036
7037 if (rtwvif_link)
7038 return rtw89_chan_get(rtwdev, rtwvif_link->chanctx_idx);
7039 else
7040 return rtw89_chan_get(rtwdev, RTW89_CHANCTX_0);
7041 }
7042
rtw89_chip_fem_setup(struct rtw89_dev * rtwdev)7043 static inline void rtw89_chip_fem_setup(struct rtw89_dev *rtwdev)
7044 {
7045 const struct rtw89_chip_info *chip = rtwdev->chip;
7046
7047 if (chip->ops->fem_setup)
7048 chip->ops->fem_setup(rtwdev);
7049 }
7050
rtw89_chip_rfe_gpio(struct rtw89_dev * rtwdev)7051 static inline void rtw89_chip_rfe_gpio(struct rtw89_dev *rtwdev)
7052 {
7053 const struct rtw89_chip_info *chip = rtwdev->chip;
7054
7055 if (chip->ops->rfe_gpio)
7056 chip->ops->rfe_gpio(rtwdev);
7057 }
7058
rtw89_chip_rfk_hw_init(struct rtw89_dev * rtwdev)7059 static inline void rtw89_chip_rfk_hw_init(struct rtw89_dev *rtwdev)
7060 {
7061 const struct rtw89_chip_info *chip = rtwdev->chip;
7062
7063 if (chip->ops->rfk_hw_init)
7064 chip->ops->rfk_hw_init(rtwdev);
7065 }
7066
7067 static inline
rtw89_chip_bb_preinit(struct rtw89_dev * rtwdev)7068 void rtw89_chip_bb_preinit(struct rtw89_dev *rtwdev)
7069 {
7070 const struct rtw89_chip_info *chip = rtwdev->chip;
7071
7072 if (!chip->ops->bb_preinit)
7073 return;
7074
7075 chip->ops->bb_preinit(rtwdev, RTW89_PHY_0);
7076
7077 if (rtwdev->dbcc_en)
7078 chip->ops->bb_preinit(rtwdev, RTW89_PHY_1);
7079 }
7080
7081 static inline
rtw89_chip_bb_postinit(struct rtw89_dev * rtwdev)7082 void rtw89_chip_bb_postinit(struct rtw89_dev *rtwdev)
7083 {
7084 const struct rtw89_chip_info *chip = rtwdev->chip;
7085
7086 if (!chip->ops->bb_postinit)
7087 return;
7088
7089 chip->ops->bb_postinit(rtwdev, RTW89_PHY_0);
7090
7091 if (rtwdev->dbcc_en)
7092 chip->ops->bb_postinit(rtwdev, RTW89_PHY_1);
7093 }
7094
rtw89_chip_bb_sethw(struct rtw89_dev * rtwdev)7095 static inline void rtw89_chip_bb_sethw(struct rtw89_dev *rtwdev)
7096 {
7097 const struct rtw89_chip_info *chip = rtwdev->chip;
7098
7099 if (chip->ops->bb_sethw)
7100 chip->ops->bb_sethw(rtwdev);
7101 }
7102
rtw89_chip_rfk_init(struct rtw89_dev * rtwdev)7103 static inline void rtw89_chip_rfk_init(struct rtw89_dev *rtwdev)
7104 {
7105 const struct rtw89_chip_info *chip = rtwdev->chip;
7106
7107 if (chip->ops->rfk_init)
7108 chip->ops->rfk_init(rtwdev);
7109 }
7110
rtw89_chip_rfk_init_late(struct rtw89_dev * rtwdev)7111 static inline void rtw89_chip_rfk_init_late(struct rtw89_dev *rtwdev)
7112 {
7113 const struct rtw89_chip_info *chip = rtwdev->chip;
7114
7115 if (chip->ops->rfk_init_late)
7116 chip->ops->rfk_init_late(rtwdev);
7117 }
7118
rtw89_chip_rfk_channel(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link)7119 static inline void rtw89_chip_rfk_channel(struct rtw89_dev *rtwdev,
7120 struct rtw89_vif_link *rtwvif_link)
7121 {
7122 const struct rtw89_chip_info *chip = rtwdev->chip;
7123
7124 if (chip->ops->rfk_channel)
7125 chip->ops->rfk_channel(rtwdev, rtwvif_link);
7126 }
7127
rtw89_chip_rfk_band_changed(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx,const struct rtw89_chan * chan)7128 static inline void rtw89_chip_rfk_band_changed(struct rtw89_dev *rtwdev,
7129 enum rtw89_phy_idx phy_idx,
7130 const struct rtw89_chan *chan)
7131 {
7132 const struct rtw89_chip_info *chip = rtwdev->chip;
7133
7134 if (chip->ops->rfk_band_changed)
7135 chip->ops->rfk_band_changed(rtwdev, phy_idx, chan);
7136 }
7137
rtw89_chip_rfk_scan(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link,bool start)7138 static inline void rtw89_chip_rfk_scan(struct rtw89_dev *rtwdev,
7139 struct rtw89_vif_link *rtwvif_link, bool start)
7140 {
7141 const struct rtw89_chip_info *chip = rtwdev->chip;
7142
7143 if (chip->ops->rfk_scan)
7144 chip->ops->rfk_scan(rtwdev, rtwvif_link, start);
7145 }
7146
rtw89_chip_rfk_track(struct rtw89_dev * rtwdev)7147 static inline void rtw89_chip_rfk_track(struct rtw89_dev *rtwdev)
7148 {
7149 const struct rtw89_chip_info *chip = rtwdev->chip;
7150
7151 if (chip->ops->rfk_track)
7152 chip->ops->rfk_track(rtwdev);
7153 }
7154
rtw89_chip_set_txpwr_ctrl(struct rtw89_dev * rtwdev)7155 static inline void rtw89_chip_set_txpwr_ctrl(struct rtw89_dev *rtwdev)
7156 {
7157 const struct rtw89_chip_info *chip = rtwdev->chip;
7158
7159 if (!chip->ops->set_txpwr_ctrl)
7160 return;
7161
7162 chip->ops->set_txpwr_ctrl(rtwdev, RTW89_PHY_0);
7163 if (rtwdev->dbcc_en)
7164 chip->ops->set_txpwr_ctrl(rtwdev, RTW89_PHY_1);
7165 }
7166
rtw89_chip_power_trim(struct rtw89_dev * rtwdev)7167 static inline void rtw89_chip_power_trim(struct rtw89_dev *rtwdev)
7168 {
7169 const struct rtw89_chip_info *chip = rtwdev->chip;
7170
7171 if (chip->ops->power_trim)
7172 chip->ops->power_trim(rtwdev);
7173 }
7174
__rtw89_chip_init_txpwr_unit(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx)7175 static inline void __rtw89_chip_init_txpwr_unit(struct rtw89_dev *rtwdev,
7176 enum rtw89_phy_idx phy_idx)
7177 {
7178 const struct rtw89_chip_info *chip = rtwdev->chip;
7179
7180 if (chip->ops->init_txpwr_unit)
7181 chip->ops->init_txpwr_unit(rtwdev, phy_idx);
7182 }
7183
rtw89_chip_init_txpwr_unit(struct rtw89_dev * rtwdev)7184 static inline void rtw89_chip_init_txpwr_unit(struct rtw89_dev *rtwdev)
7185 {
7186 __rtw89_chip_init_txpwr_unit(rtwdev, RTW89_PHY_0);
7187 if (rtwdev->dbcc_en)
7188 __rtw89_chip_init_txpwr_unit(rtwdev, RTW89_PHY_1);
7189 }
7190
rtw89_chip_get_thermal(struct rtw89_dev * rtwdev,enum rtw89_rf_path rf_path)7191 static inline u8 rtw89_chip_get_thermal(struct rtw89_dev *rtwdev,
7192 enum rtw89_rf_path rf_path)
7193 {
7194 const struct rtw89_chip_info *chip = rtwdev->chip;
7195
7196 if (!chip->ops->get_thermal)
7197 return 0x10;
7198
7199 return chip->ops->get_thermal(rtwdev, rf_path);
7200 }
7201
rtw89_chip_chan_to_rf18_val(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan)7202 static inline u32 rtw89_chip_chan_to_rf18_val(struct rtw89_dev *rtwdev,
7203 const struct rtw89_chan *chan)
7204 {
7205 const struct rtw89_chip_info *chip = rtwdev->chip;
7206
7207 if (!chip->ops->chan_to_rf18_val)
7208 return 0;
7209
7210 return chip->ops->chan_to_rf18_val(rtwdev, chan);
7211 }
7212
rtw89_chip_query_ppdu(struct rtw89_dev * rtwdev,struct rtw89_rx_phy_ppdu * phy_ppdu,struct ieee80211_rx_status * status)7213 static inline void rtw89_chip_query_ppdu(struct rtw89_dev *rtwdev,
7214 struct rtw89_rx_phy_ppdu *phy_ppdu,
7215 struct ieee80211_rx_status *status)
7216 {
7217 const struct rtw89_chip_info *chip = rtwdev->chip;
7218
7219 if (chip->ops->query_ppdu)
7220 chip->ops->query_ppdu(rtwdev, phy_ppdu, status);
7221 }
7222
rtw89_chip_convert_rpl_to_rssi(struct rtw89_dev * rtwdev,struct rtw89_rx_phy_ppdu * phy_ppdu)7223 static inline void rtw89_chip_convert_rpl_to_rssi(struct rtw89_dev *rtwdev,
7224 struct rtw89_rx_phy_ppdu *phy_ppdu)
7225 {
7226 const struct rtw89_chip_info *chip = rtwdev->chip;
7227
7228 if (chip->ops->convert_rpl_to_rssi)
7229 chip->ops->convert_rpl_to_rssi(rtwdev, phy_ppdu);
7230 }
7231
rtw89_chip_phy_rpt_to_rssi(struct rtw89_dev * rtwdev,struct rtw89_rx_desc_info * desc_info,struct ieee80211_rx_status * rx_status)7232 static inline void rtw89_chip_phy_rpt_to_rssi(struct rtw89_dev *rtwdev,
7233 struct rtw89_rx_desc_info *desc_info,
7234 struct ieee80211_rx_status *rx_status)
7235 {
7236 const struct rtw89_chip_info *chip = rtwdev->chip;
7237
7238 if (chip->ops->phy_rpt_to_rssi)
7239 chip->ops->phy_rpt_to_rssi(rtwdev, desc_info, rx_status);
7240 }
7241
rtw89_ctrl_nbtg_bt_tx(struct rtw89_dev * rtwdev,bool en,enum rtw89_phy_idx phy_idx)7242 static inline void rtw89_ctrl_nbtg_bt_tx(struct rtw89_dev *rtwdev, bool en,
7243 enum rtw89_phy_idx phy_idx)
7244 {
7245 const struct rtw89_chip_info *chip = rtwdev->chip;
7246
7247 if (chip->ops->ctrl_nbtg_bt_tx)
7248 chip->ops->ctrl_nbtg_bt_tx(rtwdev, en, phy_idx);
7249 }
7250
rtw89_chip_cfg_txrx_path(struct rtw89_dev * rtwdev)7251 static inline void rtw89_chip_cfg_txrx_path(struct rtw89_dev *rtwdev)
7252 {
7253 const struct rtw89_chip_info *chip = rtwdev->chip;
7254
7255 if (chip->ops->cfg_txrx_path)
7256 chip->ops->cfg_txrx_path(rtwdev);
7257 }
7258
rtw89_chip_digital_pwr_comp(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx)7259 static inline void rtw89_chip_digital_pwr_comp(struct rtw89_dev *rtwdev,
7260 enum rtw89_phy_idx phy_idx)
7261 {
7262 const struct rtw89_chip_info *chip = rtwdev->chip;
7263
7264 if (chip->ops->digital_pwr_comp)
7265 chip->ops->digital_pwr_comp(rtwdev, phy_idx);
7266 }
7267
rtw89_load_txpwr_table(struct rtw89_dev * rtwdev,const struct rtw89_txpwr_table * tbl)7268 static inline void rtw89_load_txpwr_table(struct rtw89_dev *rtwdev,
7269 const struct rtw89_txpwr_table *tbl)
7270 {
7271 tbl->load(rtwdev, tbl);
7272 }
7273
rtw89_regd_get(struct rtw89_dev * rtwdev,u8 band)7274 static inline u8 rtw89_regd_get(struct rtw89_dev *rtwdev, u8 band)
7275 {
7276 const struct rtw89_regulatory_info *regulatory = &rtwdev->regulatory;
7277 const struct rtw89_regd *regd = regulatory->regd;
7278 u8 txpwr_regd = regd->txpwr_regd[band];
7279
7280 if (regulatory->txpwr_uk_follow_etsi && txpwr_regd == RTW89_UK)
7281 return RTW89_ETSI;
7282
7283 return txpwr_regd;
7284 }
7285
rtw89_ctrl_btg_bt_rx(struct rtw89_dev * rtwdev,bool en,enum rtw89_phy_idx phy_idx)7286 static inline void rtw89_ctrl_btg_bt_rx(struct rtw89_dev *rtwdev, bool en,
7287 enum rtw89_phy_idx phy_idx)
7288 {
7289 const struct rtw89_chip_info *chip = rtwdev->chip;
7290
7291 if (chip->ops->ctrl_btg_bt_rx)
7292 chip->ops->ctrl_btg_bt_rx(rtwdev, en, phy_idx);
7293 }
7294
7295 static inline
rtw89_chip_query_rxdesc(struct rtw89_dev * rtwdev,struct rtw89_rx_desc_info * desc_info,u8 * data,u32 data_offset)7296 void rtw89_chip_query_rxdesc(struct rtw89_dev *rtwdev,
7297 struct rtw89_rx_desc_info *desc_info,
7298 u8 *data, u32 data_offset)
7299 {
7300 const struct rtw89_chip_info *chip = rtwdev->chip;
7301
7302 chip->ops->query_rxdesc(rtwdev, desc_info, data, data_offset);
7303 }
7304
7305 static inline
rtw89_chip_fill_txdesc(struct rtw89_dev * rtwdev,struct rtw89_tx_desc_info * desc_info,void * txdesc)7306 void rtw89_chip_fill_txdesc(struct rtw89_dev *rtwdev,
7307 struct rtw89_tx_desc_info *desc_info,
7308 void *txdesc)
7309 {
7310 const struct rtw89_chip_info *chip = rtwdev->chip;
7311
7312 chip->ops->fill_txdesc(rtwdev, desc_info, txdesc);
7313 }
7314
7315 static inline
rtw89_chip_fill_txdesc_fwcmd(struct rtw89_dev * rtwdev,struct rtw89_tx_desc_info * desc_info,void * txdesc)7316 void rtw89_chip_fill_txdesc_fwcmd(struct rtw89_dev *rtwdev,
7317 struct rtw89_tx_desc_info *desc_info,
7318 void *txdesc)
7319 {
7320 const struct rtw89_chip_info *chip = rtwdev->chip;
7321
7322 chip->ops->fill_txdesc_fwcmd(rtwdev, desc_info, txdesc);
7323 }
7324
7325 static inline
rtw89_chip_get_ch_dma(struct rtw89_dev * rtwdev,u8 qsel)7326 u8 rtw89_chip_get_ch_dma(struct rtw89_dev *rtwdev, u8 qsel)
7327 {
7328 const struct rtw89_chip_info *chip = rtwdev->chip;
7329
7330 return chip->ops->get_ch_dma[rtwdev->hci.type](rtwdev, qsel);
7331 }
7332
7333 static inline
rtw89_chip_mac_cfg_gnt(struct rtw89_dev * rtwdev,const struct rtw89_mac_ax_coex_gnt * gnt_cfg)7334 void rtw89_chip_mac_cfg_gnt(struct rtw89_dev *rtwdev,
7335 const struct rtw89_mac_ax_coex_gnt *gnt_cfg)
7336 {
7337 const struct rtw89_chip_info *chip = rtwdev->chip;
7338
7339 chip->ops->mac_cfg_gnt(rtwdev, gnt_cfg);
7340 }
7341
rtw89_chip_cfg_ctrl_path(struct rtw89_dev * rtwdev,bool wl)7342 static inline void rtw89_chip_cfg_ctrl_path(struct rtw89_dev *rtwdev, bool wl)
7343 {
7344 const struct rtw89_chip_info *chip = rtwdev->chip;
7345
7346 chip->ops->cfg_ctrl_path(rtwdev, wl);
7347 }
7348
7349 static inline
rtw89_chip_stop_sch_tx(struct rtw89_dev * rtwdev,u8 mac_idx,u32 * tx_en,enum rtw89_sch_tx_sel sel)7350 int rtw89_chip_stop_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx,
7351 u32 *tx_en, enum rtw89_sch_tx_sel sel)
7352 {
7353 const struct rtw89_chip_info *chip = rtwdev->chip;
7354
7355 return chip->ops->stop_sch_tx(rtwdev, mac_idx, tx_en, sel);
7356 }
7357
7358 static inline
rtw89_chip_resume_sch_tx(struct rtw89_dev * rtwdev,u8 mac_idx,u32 tx_en)7359 int rtw89_chip_resume_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en)
7360 {
7361 const struct rtw89_chip_info *chip = rtwdev->chip;
7362
7363 return chip->ops->resume_sch_tx(rtwdev, mac_idx, tx_en);
7364 }
7365
7366 static inline
rtw89_chip_h2c_dctl_sec_cam(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link,struct rtw89_sta_link * rtwsta_link)7367 int rtw89_chip_h2c_dctl_sec_cam(struct rtw89_dev *rtwdev,
7368 struct rtw89_vif_link *rtwvif_link,
7369 struct rtw89_sta_link *rtwsta_link)
7370 {
7371 const struct rtw89_chip_info *chip = rtwdev->chip;
7372
7373 if (!chip->ops->h2c_dctl_sec_cam)
7374 return 0;
7375 return chip->ops->h2c_dctl_sec_cam(rtwdev, rtwvif_link, rtwsta_link);
7376 }
7377
get_hdr_bssid(struct ieee80211_hdr * hdr)7378 static inline u8 *get_hdr_bssid(struct ieee80211_hdr *hdr)
7379 {
7380 __le16 fc = hdr->frame_control;
7381
7382 if (ieee80211_has_tods(fc))
7383 return hdr->addr1;
7384 else if (ieee80211_has_fromds(fc))
7385 return hdr->addr2;
7386 else
7387 return hdr->addr3;
7388 }
7389
7390 static inline
rtw89_sta_has_beamformer_cap(struct ieee80211_link_sta * link_sta)7391 bool rtw89_sta_has_beamformer_cap(struct ieee80211_link_sta *link_sta)
7392 {
7393 if ((link_sta->vht_cap.cap & IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE) ||
7394 (link_sta->vht_cap.cap & IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE) ||
7395 (link_sta->he_cap.he_cap_elem.phy_cap_info[3] &
7396 IEEE80211_HE_PHY_CAP3_SU_BEAMFORMER) ||
7397 (link_sta->he_cap.he_cap_elem.phy_cap_info[4] &
7398 IEEE80211_HE_PHY_CAP4_MU_BEAMFORMER))
7399 return true;
7400 return false;
7401 }
7402
7403 static inline
rtw89_sta_link_has_su_mu_4xhe08(struct ieee80211_link_sta * link_sta)7404 bool rtw89_sta_link_has_su_mu_4xhe08(struct ieee80211_link_sta *link_sta)
7405 {
7406 if (link_sta->he_cap.he_cap_elem.phy_cap_info[7] &
7407 IEEE80211_HE_PHY_CAP7_HE_SU_MU_PPDU_4XLTF_AND_08_US_GI)
7408 return true;
7409
7410 return false;
7411 }
7412
7413 static inline
rtw89_sta_link_has_er_su_4xhe08(struct ieee80211_link_sta * link_sta)7414 bool rtw89_sta_link_has_er_su_4xhe08(struct ieee80211_link_sta *link_sta)
7415 {
7416 if (link_sta->he_cap.he_cap_elem.phy_cap_info[8] &
7417 IEEE80211_HE_PHY_CAP8_HE_ER_SU_PPDU_4XLTF_AND_08_US_GI)
7418 return true;
7419
7420 return false;
7421 }
7422
rtw89_fw_suit_get(struct rtw89_dev * rtwdev,enum rtw89_fw_type type)7423 static inline struct rtw89_fw_suit *rtw89_fw_suit_get(struct rtw89_dev *rtwdev,
7424 #if defined(__linux__)
7425 enum rtw89_fw_type type)
7426 #elif defined(__FreeBSD__)
7427 const enum rtw89_fw_type type)
7428 #endif
7429 {
7430 struct rtw89_fw_info *fw_info = &rtwdev->fw;
7431
7432 switch (type) {
7433 case RTW89_FW_WOWLAN:
7434 return &fw_info->wowlan;
7435 case RTW89_FW_LOGFMT:
7436 return &fw_info->log.suit;
7437 case RTW89_FW_BBMCU0:
7438 return &fw_info->bbmcu0;
7439 case RTW89_FW_BBMCU1:
7440 return &fw_info->bbmcu1;
7441 default:
7442 break;
7443 }
7444
7445 return &fw_info->normal;
7446 }
7447
rtw89_alloc_skb_for_rx(struct rtw89_dev * rtwdev,unsigned int length)7448 static inline struct sk_buff *rtw89_alloc_skb_for_rx(struct rtw89_dev *rtwdev,
7449 unsigned int length)
7450 {
7451 struct sk_buff *skb;
7452
7453 if (rtwdev->hw->conf.flags & IEEE80211_CONF_MONITOR) {
7454 skb = dev_alloc_skb(length + RTW89_RADIOTAP_ROOM);
7455 if (!skb)
7456 return NULL;
7457
7458 skb_reserve(skb, RTW89_RADIOTAP_ROOM);
7459 return skb;
7460 }
7461
7462 return dev_alloc_skb(length);
7463 }
7464
rtw89_core_is_tx_wait(struct rtw89_dev * rtwdev,struct rtw89_tx_skb_data * skb_data)7465 static inline bool rtw89_core_is_tx_wait(struct rtw89_dev *rtwdev,
7466 struct rtw89_tx_skb_data *skb_data)
7467 {
7468 return rcu_access_pointer(skb_data->wait);
7469 }
7470
rtw89_core_tx_wait_complete(struct rtw89_dev * rtwdev,struct rtw89_tx_skb_data * skb_data,u8 tx_status)7471 static inline bool rtw89_core_tx_wait_complete(struct rtw89_dev *rtwdev,
7472 struct rtw89_tx_skb_data *skb_data,
7473 u8 tx_status)
7474 {
7475 struct rtw89_tx_wait_info *wait;
7476
7477 guard(rcu)();
7478
7479 wait = rcu_dereference(skb_data->wait);
7480 if (!wait)
7481 return false;
7482
7483 wait->tx_done = tx_status == RTW89_TX_DONE;
7484 /* Don't access skb anymore after completion */
7485 complete_all(&wait->completion);
7486 return true;
7487 }
7488
rtw89_is_mlo_1_1(struct rtw89_dev * rtwdev)7489 static inline bool rtw89_is_mlo_1_1(struct rtw89_dev *rtwdev)
7490 {
7491 switch (rtwdev->mlo_dbcc_mode) {
7492 case MLO_1_PLUS_1_1RF:
7493 case MLO_1_PLUS_1_2RF:
7494 case DBCC_LEGACY:
7495 return true;
7496 default:
7497 return false;
7498 }
7499 }
7500
rtw89_get_active_phy_bitmap(struct rtw89_dev * rtwdev)7501 static inline u8 rtw89_get_active_phy_bitmap(struct rtw89_dev *rtwdev)
7502 {
7503 if (!rtwdev->dbcc_en)
7504 return BIT(RTW89_PHY_0);
7505
7506 switch (rtwdev->mlo_dbcc_mode) {
7507 case MLO_0_PLUS_2_1RF:
7508 case MLO_0_PLUS_2_2RF:
7509 return BIT(RTW89_PHY_1);
7510 case MLO_1_PLUS_1_1RF:
7511 case MLO_1_PLUS_1_2RF:
7512 case MLO_2_PLUS_2_2RF:
7513 case DBCC_LEGACY:
7514 return BIT(RTW89_PHY_0) | BIT(RTW89_PHY_1);
7515 case MLO_2_PLUS_0_1RF:
7516 case MLO_2_PLUS_0_2RF:
7517 default:
7518 return BIT(RTW89_PHY_0);
7519 }
7520 }
7521
7522 #define rtw89_for_each_active_bb(rtwdev, bb) \
7523 for (u8 __active_bb_bitmap = rtw89_get_active_phy_bitmap(rtwdev), \
7524 __phy_idx = 0; __phy_idx < RTW89_PHY_NUM; __phy_idx++) \
7525 if (__active_bb_bitmap & BIT(__phy_idx) && \
7526 (bb = &rtwdev->bbs[__phy_idx]))
7527
7528 #define rtw89_for_each_capab_bb(rtwdev, bb) \
7529 for (u8 __phy_idx_max = rtwdev->dbcc_en ? RTW89_PHY_1 : RTW89_PHY_0, \
7530 __phy_idx = 0; __phy_idx <= __phy_idx_max; __phy_idx++) \
7531 if ((bb = &rtwdev->bbs[__phy_idx]))
7532
7533 static inline
rtw89_get_bb_ctx(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx)7534 struct rtw89_bb_ctx *rtw89_get_bb_ctx(struct rtw89_dev *rtwdev,
7535 enum rtw89_phy_idx phy_idx)
7536 {
7537 if (phy_idx >= RTW89_PHY_NUM)
7538 return &rtwdev->bbs[RTW89_PHY_0];
7539
7540 return &rtwdev->bbs[phy_idx];
7541 }
7542
rtw89_is_rtl885xb(struct rtw89_dev * rtwdev)7543 static inline bool rtw89_is_rtl885xb(struct rtw89_dev *rtwdev)
7544 {
7545 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;
7546
7547 if (chip_id == RTL8852B || chip_id == RTL8851B || chip_id == RTL8852BT)
7548 return true;
7549
7550 return false;
7551 }
7552
rtw89_bytes_to_mbps(u64 bytes,enum rtw89_tfc_interval interval)7553 static inline u32 rtw89_bytes_to_mbps(u64 bytes, enum rtw89_tfc_interval interval)
7554 {
7555 switch (interval) {
7556 default:
7557 case RTW89_TFC_INTERVAL_2SEC:
7558 return bytes >> 18; /* bytes/2s --> Mbps */;
7559 case RTW89_TFC_INTERVAL_100MS:
7560 return (bytes * 10) >> 17; /* bytes/100ms --> Mbps */
7561 }
7562 }
7563
7564 int rtw89_core_tx_write(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif,
7565 struct ieee80211_sta *sta, struct sk_buff *skb, int *qsel);
7566 int rtw89_h2c_tx(struct rtw89_dev *rtwdev,
7567 struct sk_buff *skb, bool fwdl);
7568 void rtw89_core_tx_kick_off(struct rtw89_dev *rtwdev, u8 qsel);
7569 int rtw89_core_tx_kick_off_and_wait(struct rtw89_dev *rtwdev, struct sk_buff *skb,
7570 struct rtw89_tx_wait_info *wait, int qsel,
7571 unsigned int timeout);
7572 void rtw89_core_fill_txdesc(struct rtw89_dev *rtwdev,
7573 struct rtw89_tx_desc_info *desc_info,
7574 void *txdesc);
7575 void rtw89_core_fill_txdesc_v1(struct rtw89_dev *rtwdev,
7576 struct rtw89_tx_desc_info *desc_info,
7577 void *txdesc);
7578 void rtw89_core_fill_txdesc_v2(struct rtw89_dev *rtwdev,
7579 struct rtw89_tx_desc_info *desc_info,
7580 void *txdesc);
7581 void rtw89_core_fill_txdesc_fwcmd_v1(struct rtw89_dev *rtwdev,
7582 struct rtw89_tx_desc_info *desc_info,
7583 void *txdesc);
7584 void rtw89_core_fill_txdesc_fwcmd_v2(struct rtw89_dev *rtwdev,
7585 struct rtw89_tx_desc_info *desc_info,
7586 void *txdesc);
7587 u8 rtw89_core_get_ch_dma(struct rtw89_dev *rtwdev, u8 qsel);
7588 u8 rtw89_core_get_ch_dma_v1(struct rtw89_dev *rtwdev, u8 qsel);
7589 u8 rtw89_core_get_ch_dma_v2(struct rtw89_dev *rtwdev, u8 qsel);
7590 void rtw89_core_rx(struct rtw89_dev *rtwdev,
7591 struct rtw89_rx_desc_info *desc_info,
7592 struct sk_buff *skb);
7593 void rtw89_core_query_rxdesc(struct rtw89_dev *rtwdev,
7594 struct rtw89_rx_desc_info *desc_info,
7595 u8 *data, u32 data_offset);
7596 void rtw89_core_query_rxdesc_v2(struct rtw89_dev *rtwdev,
7597 struct rtw89_rx_desc_info *desc_info,
7598 u8 *data, u32 data_offset);
7599 void rtw89_core_napi_start(struct rtw89_dev *rtwdev);
7600 void rtw89_core_napi_stop(struct rtw89_dev *rtwdev);
7601 int rtw89_core_napi_init(struct rtw89_dev *rtwdev);
7602 void rtw89_core_napi_deinit(struct rtw89_dev *rtwdev);
7603 int rtw89_core_sta_link_add(struct rtw89_dev *rtwdev,
7604 struct rtw89_vif_link *rtwvif_link,
7605 struct rtw89_sta_link *rtwsta_link);
7606 int rtw89_core_sta_link_assoc(struct rtw89_dev *rtwdev,
7607 struct rtw89_vif_link *rtwvif_link,
7608 struct rtw89_sta_link *rtwsta_link);
7609 int rtw89_core_sta_link_disassoc(struct rtw89_dev *rtwdev,
7610 struct rtw89_vif_link *rtwvif_link,
7611 struct rtw89_sta_link *rtwsta_link);
7612 int rtw89_core_sta_link_disconnect(struct rtw89_dev *rtwdev,
7613 struct rtw89_vif_link *rtwvif_link,
7614 struct rtw89_sta_link *rtwsta_link);
7615 int rtw89_core_sta_link_remove(struct rtw89_dev *rtwdev,
7616 struct rtw89_vif_link *rtwvif_link,
7617 struct rtw89_sta_link *rtwsta_link);
7618 void rtw89_core_set_tid_config(struct rtw89_dev *rtwdev,
7619 struct ieee80211_sta *sta,
7620 struct cfg80211_tid_config *tid_config);
7621 void rtw89_core_rfkill_poll(struct rtw89_dev *rtwdev, bool force);
7622 void rtw89_check_quirks(struct rtw89_dev *rtwdev, const struct dmi_system_id *quirks);
7623 int rtw89_core_init(struct rtw89_dev *rtwdev);
7624 void rtw89_core_deinit(struct rtw89_dev *rtwdev);
7625 int rtw89_core_register(struct rtw89_dev *rtwdev);
7626 void rtw89_core_unregister(struct rtw89_dev *rtwdev);
7627 struct rtw89_dev *rtw89_alloc_ieee80211_hw(struct device *device,
7628 u32 bus_data_size,
7629 const struct rtw89_chip_info *chip,
7630 const struct rtw89_chip_variant *variant);
7631 void rtw89_free_ieee80211_hw(struct rtw89_dev *rtwdev);
7632 u8 rtw89_acquire_mac_id(struct rtw89_dev *rtwdev);
7633 void rtw89_release_mac_id(struct rtw89_dev *rtwdev, u8 mac_id);
7634 void rtw89_init_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
7635 u8 mac_id, u8 port);
7636 void rtw89_init_sta(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
7637 struct rtw89_sta *rtwsta, u8 mac_id);
7638 struct rtw89_vif_link *rtw89_vif_set_link(struct rtw89_vif *rtwvif,
7639 unsigned int link_id);
7640 void rtw89_vif_unset_link(struct rtw89_vif *rtwvif, unsigned int link_id);
7641 struct rtw89_sta_link *rtw89_sta_set_link(struct rtw89_sta *rtwsta,
7642 unsigned int link_id);
7643 void rtw89_sta_unset_link(struct rtw89_sta *rtwsta, unsigned int link_id);
7644 void rtw89_core_set_chip_txpwr(struct rtw89_dev *rtwdev);
7645 const struct rtw89_6ghz_span *
7646 rtw89_get_6ghz_span(struct rtw89_dev *rtwdev, u32 center_freq);
7647 void rtw89_get_default_chandef(struct cfg80211_chan_def *chandef);
7648 void rtw89_get_channel_params(const struct cfg80211_chan_def *chandef,
7649 struct rtw89_chan *chan);
7650 int rtw89_set_channel(struct rtw89_dev *rtwdev);
7651 u8 rtw89_core_acquire_bit_map(unsigned long *addr, unsigned long size);
7652 void rtw89_core_release_bit_map(unsigned long *addr, u8 bit);
7653 void rtw89_core_release_all_bits_map(unsigned long *addr, unsigned int nbits);
7654 int rtw89_core_acquire_sta_ba_entry(struct rtw89_dev *rtwdev,
7655 struct rtw89_sta_link *rtwsta_link, u8 tid,
7656 u8 *cam_idx);
7657 int rtw89_core_release_sta_ba_entry(struct rtw89_dev *rtwdev,
7658 struct rtw89_sta_link *rtwsta_link, u8 tid,
7659 u8 *cam_idx);
7660 void rtw89_core_free_sta_pending_ba(struct rtw89_dev *rtwdev,
7661 struct ieee80211_sta *sta);
7662 void rtw89_core_free_sta_pending_forbid_ba(struct rtw89_dev *rtwdev,
7663 struct ieee80211_sta *sta);
7664 void rtw89_core_free_sta_pending_roc_tx(struct rtw89_dev *rtwdev,
7665 struct ieee80211_sta *sta);
7666 void rtw89_vif_type_mapping(struct rtw89_vif_link *rtwvif_link, bool assoc);
7667 int rtw89_chip_info_setup(struct rtw89_dev *rtwdev);
7668 void rtw89_chip_cfg_txpwr_ul_tb_offset(struct rtw89_dev *rtwdev,
7669 struct rtw89_vif_link *rtwvif_link);
7670 bool rtw89_legacy_rate_to_bitrate(struct rtw89_dev *rtwdev, u8 legacy_rate, u16 *bitrate);
7671 int rtw89_regd_setup(struct rtw89_dev *rtwdev);
7672 int rtw89_regd_init_hint(struct rtw89_dev *rtwdev);
7673 const char *rtw89_regd_get_string(enum rtw89_regulation_type regd);
7674 void rtw89_traffic_stats_init(struct rtw89_dev *rtwdev,
7675 struct rtw89_traffic_stats *stats);
7676 struct rtw89_wait_response *
7677 rtw89_wait_for_cond_prep(struct rtw89_wait_info *wait, unsigned int cond)
7678 __acquires(rtw89_wait);
7679 int rtw89_wait_for_cond_eval(struct rtw89_wait_info *wait,
7680 struct rtw89_wait_response *prep, int err)
7681 __releases(rtw89_wait);
7682 void rtw89_complete_cond(struct rtw89_wait_info *wait, unsigned int cond,
7683 const struct rtw89_completion_data *data);
7684 int rtw89_core_start(struct rtw89_dev *rtwdev);
7685 void rtw89_core_stop(struct rtw89_dev *rtwdev);
7686 void rtw89_core_update_beacon_work(struct wiphy *wiphy, struct wiphy_work *work);
7687 void rtw89_core_csa_beacon_work(struct wiphy *wiphy, struct wiphy_work *work);
7688 int rtw89_core_send_nullfunc(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link,
7689 bool qos, bool ps, int timeout);
7690 void rtw89_roc_work(struct wiphy *wiphy, struct wiphy_work *work);
7691 void rtw89_roc_start(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif);
7692 void rtw89_roc_end(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif);
7693 void rtw89_core_scan_start(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link,
7694 const u8 *mac_addr, bool hw_scan);
7695 void rtw89_core_scan_complete(struct rtw89_dev *rtwdev,
7696 struct rtw89_vif_link *rtwvif_link, bool hw_scan);
7697 int rtw89_reg_6ghz_recalc(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link,
7698 bool active);
7699 void rtw89_core_update_p2p_ps(struct rtw89_dev *rtwdev,
7700 struct rtw89_vif_link *rtwvif_link,
7701 struct ieee80211_bss_conf *bss_conf);
7702 void rtw89_core_ntfy_btc_event(struct rtw89_dev *rtwdev, enum rtw89_btc_hmsg event);
7703 int rtw89_core_mlsr_switch(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
7704 unsigned int link_id);
7705
7706 #endif
7707