xref: /linux/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi (revision 0cac5ce06e524755b3dac1e0a060b05992076d93)
1// SPDX-License-Identifier: GPL-2.0
2/dts-v1/;
3
4#include <dt-bindings/interrupt-controller/arm-gic.h>
5#include <dt-bindings/clock/qcom,gcc-msm8960.h>
6#include <dt-bindings/reset/qcom,gcc-msm8960.h>
7#include <dt-bindings/clock/qcom,lcc-msm8960.h>
8#include <dt-bindings/mfd/qcom-rpm.h>
9#include <dt-bindings/soc/qcom,gsbi.h>
10
11/ {
12	#address-cells = <1>;
13	#size-cells = <1>;
14	model = "Qualcomm MSM8960";
15	compatible = "qcom,msm8960";
16	interrupt-parent = <&intc>;
17
18	clocks {
19		cxo_board: cxo_board {
20			compatible = "fixed-clock";
21			#clock-cells = <0>;
22			clock-frequency = <19200000>;
23			clock-output-names = "cxo_board";
24		};
25
26		pxo_board: pxo_board {
27			compatible = "fixed-clock";
28			#clock-cells = <0>;
29			clock-frequency = <27000000>;
30			clock-output-names = "pxo_board";
31		};
32
33		sleep_clk: sleep_clk {
34			compatible = "fixed-clock";
35			#clock-cells = <0>;
36			clock-frequency = <32768>;
37			clock-output-names = "sleep_clk";
38		};
39	};
40
41	cpu-pmu {
42		compatible = "qcom,krait-pmu";
43		interrupts = <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
44		qcom,no-pc-write;
45	};
46
47	cpus {
48		#address-cells = <1>;
49		#size-cells = <0>;
50		interrupts = <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
51
52		cpu@0 {
53			compatible = "qcom,krait";
54			reg = <0>;
55			enable-method = "qcom,kpss-acc-v1";
56			device_type = "cpu";
57			next-level-cache = <&l2>;
58			qcom,acc = <&acc0>;
59			qcom,saw = <&saw0>;
60		};
61
62		cpu@1 {
63			compatible = "qcom,krait";
64			reg = <1>;
65			enable-method = "qcom,kpss-acc-v1";
66			device_type = "cpu";
67			next-level-cache = <&l2>;
68			qcom,acc = <&acc1>;
69			qcom,saw = <&saw1>;
70		};
71
72		l2: l2-cache {
73			compatible = "cache";
74			cache-level = <2>;
75			cache-unified;
76		};
77	};
78
79	memory@80000000 {
80		device_type = "memory";
81		reg = <0x80000000 0>;
82	};
83
84	soc: soc {
85		compatible = "simple-bus";
86		ranges;
87		#address-cells = <1>;
88		#size-cells = <1>;
89
90		rpm: rpm@108000 {
91			compatible = "qcom,rpm-msm8960";
92			reg = <0x108000 0x1000>;
93			qcom,ipc = <&l2cc 0x8 2>;
94
95			interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>,
96				     <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
97				     <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>;
98			interrupt-names = "ack",
99					  "err",
100					  "wakeup";
101		};
102
103		ssbi: ssbi@500000 {
104			compatible = "qcom,ssbi";
105			reg = <0x500000 0x1000>;
106			qcom,controller-type = "pmic-arbiter";
107		};
108
109		qfprom: efuse@700000 {
110			compatible = "qcom,msm8960-qfprom", "qcom,qfprom";
111			reg = <0x00700000 0x1000>;
112			#address-cells = <1>;
113			#size-cells = <1>;
114
115			tsens_calib: calib@404 {
116				reg = <0x404 0x10>;
117			};
118
119			tsens_backup: backup-calib@414 {
120				reg = <0x414 0x10>;
121			};
122		};
123
124		tlmm: pinctrl@800000 {
125			compatible = "qcom,msm8960-pinctrl";
126			reg = <0x800000 0x4000>;
127			gpio-controller;
128			gpio-ranges = <&tlmm 0 0 152>;
129			#gpio-cells = <2>;
130			interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
131			interrupt-controller;
132			#interrupt-cells = <2>;
133
134			i2c1_default_state: i2c1-default-state {
135				i2c1-pins {
136					pins = "gpio8", "gpio9";
137					function = "gsbi1";
138					drive-strength = <8>;
139					bias-disable;
140				};
141			};
142
143			i2c1_sleep_state: i2c1-sleep-state {
144				i2c1-pins {
145					pins = "gpio8", "gpio9";
146					function = "gpio";
147					drive-strength = <2>;
148					bias-bus-hold;
149				};
150			};
151
152			i2c3_default_state: i2c3-default-state {
153				i2c3-pins {
154					pins = "gpio16", "gpio17";
155					function = "gsbi3";
156					drive-strength = <8>;
157					bias-disable;
158				};
159			};
160
161			i2c3_sleep_state: i2c3-sleep-state {
162				i2c3-pins {
163					pins = "gpio16", "gpio17";
164					function = "gpio";
165					drive-strength = <2>;
166					bias-bus-hold;
167				};
168			};
169
170			i2c8_default_state: i2c8-default-state {
171				i2c8-pins {
172					pins = "gpio36", "gpio37";
173					function = "gsbi8";
174					drive-strength = <8>;
175					bias-disable;
176				};
177			};
178
179			i2c8_sleep_state: i2c8-sleep-state {
180				i2c8-pins {
181					pins = "gpio36", "gpio37";
182					function = "gpio";
183					drive-strength = <2>;
184					bias-bus-hold;
185				};
186			};
187
188			i2c10_default_state: i2c10-default-state {
189				i2c10-pins {
190					pins = "gpio73", "gpio74";
191					function = "gsbi10";
192					drive-strength = <8>;
193					bias-disable;
194				};
195			};
196
197			i2c10_sleep_state: i2c10-sleep-state {
198				i2c10-pins {
199					pins = "gpio73", "gpio74";
200					function = "gpio";
201					drive-strength = <2>;
202					bias-bus-hold;
203				};
204			};
205
206			i2c12_default_state: i2c12-default-state {
207				i2c12-pins {
208					pins = "gpio44", "gpio45";
209					function = "gsbi12";
210					drive-strength = <8>;
211					bias-disable;
212				};
213			};
214
215			i2c12_sleep_state: i2c12-sleep-state {
216				i2c12-pins {
217					pins = "gpio44", "gpio45";
218					function = "gpio";
219					drive-strength = <2>;
220					bias-bus-hold;
221				};
222			};
223
224			sdcc3_default_state: sdcc3-default-state {
225				clk-pins {
226					pins = "sdc3_clk";
227					drive-strength = <8>;
228					bias-disable;
229				};
230
231				cmd-pins {
232					pins = "sdc3_cmd";
233					drive-strength = <8>;
234					bias-pull-up;
235				};
236
237				data-pins {
238					pins = "sdc3_data";
239					drive-strength = <8>;
240					bias-pull-up;
241				};
242			};
243
244			sdcc3_sleep_state: sdcc3-sleep-state {
245				clk-pins {
246					pins = "sdc3_clk";
247					drive-strength = <2>;
248					bias-disable;
249				};
250
251				cmd-pins {
252					pins = "sdc3_cmd";
253					drive-strength = <2>;
254					bias-pull-up;
255				};
256
257				data-pins {
258					pins = "sdc3_data";
259					drive-strength = <2>;
260					bias-pull-up;
261				};
262			};
263		};
264
265		gcc: clock-controller@900000 {
266			compatible = "qcom,gcc-msm8960", "syscon";
267			reg = <0x900000 0x4000>;
268			#clock-cells = <1>;
269			#reset-cells = <1>;
270			clocks = <&cxo_board>,
271				 <&pxo_board>,
272				 <&lcc PLL4>;
273			clock-names = "cxo",
274				      "pxo",
275				      "pll4";
276
277			tsens: thermal-sensor {
278				compatible = "qcom,msm8960-tsens";
279
280				nvmem-cells = <&tsens_calib>, <&tsens_backup>;
281				nvmem-cell-names = "calib", "calib_backup";
282				interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
283				interrupt-names = "uplow";
284
285				#qcom,sensors = <5>;
286				#thermal-sensor-cells = <1>;
287			};
288		};
289
290		intc: interrupt-controller@2000000 {
291			compatible = "qcom,msm-qgic2";
292			reg = <0x02000000 0x1000>,
293			      <0x02002000 0x1000>;
294			interrupt-controller;
295			#interrupt-cells = <3>;
296		};
297
298		timer@200a000 {
299			compatible = "qcom,kpss-wdt-msm8960", "qcom,kpss-timer",
300				     "qcom,msm-timer";
301			reg = <0x0200a000 0x100>;
302			interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>,
303				     <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>,
304				     <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>;
305			clock-frequency = <27000000>;
306			clocks = <&sleep_clk>;
307			clock-names = "sleep";
308			cpu-offset = <0x80000>;
309		};
310
311		l2cc: clock-controller@2011000 {
312			compatible = "qcom,kpss-gcc-msm8960", "qcom,kpss-gcc", "syscon";
313			reg = <0x2011000 0x1000>;
314			clocks = <&gcc PLL8_VOTE>, <&pxo_board>;
315			clock-names = "pll8_vote", "pxo";
316			#clock-cells = <0>;
317		};
318
319		acc0: clock-controller@2088000 {
320			compatible = "qcom,kpss-acc-v1";
321			reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
322			clocks = <&gcc PLL8_VOTE>, <&pxo_board>;
323			clock-names = "pll8_vote", "pxo";
324			clock-output-names = "acpu0_aux";
325			#clock-cells = <0>;
326		};
327
328		saw0: power-manager@2089000 {
329			compatible = "qcom,msm8960-saw2-cpu", "qcom,saw2";
330			reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
331
332			saw0_vreg: regulator {
333				regulator-min-microvolt = <850000>;
334				regulator-max-microvolt = <1300000>;
335			};
336		};
337
338		acc1: clock-controller@2098000 {
339			compatible = "qcom,kpss-acc-v1";
340			reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
341			clocks = <&gcc PLL8_VOTE>, <&pxo_board>;
342			clock-names = "pll8_vote", "pxo";
343			clock-output-names = "acpu1_aux";
344			#clock-cells = <0>;
345		};
346
347		saw1: power-manager@2099000 {
348			compatible = "qcom,msm8960-saw2-cpu", "qcom,saw2";
349			reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
350
351			saw1_vreg: regulator {
352				regulator-min-microvolt = <850000>;
353				regulator-max-microvolt = <1300000>;
354			};
355		};
356
357		clock-controller@4000000 {
358			compatible = "qcom,mmcc-msm8960";
359			reg = <0x4000000 0x1000>;
360			#clock-cells = <1>;
361			#power-domain-cells = <1>;
362			#reset-cells = <1>;
363			clocks = <&pxo_board>,
364				 <&gcc PLL3>,
365				 <&gcc PLL8_VOTE>,
366				 <0>,
367				 <0>,
368				 <0>,
369				 <0>,
370				 <0>;
371			clock-names = "pxo",
372				      "pll3",
373				      "pll8_vote",
374				      "dsi1pll",
375				      "dsi1pllbyte",
376				      "dsi2pll",
377				      "dsi2pllbyte",
378				      "hdmipll";
379		};
380
381		sdcc3: mmc@12180000 {
382			compatible = "arm,pl18x", "arm,primecell";
383			reg = <0x12180000 0x2000>;
384			arm,primecell-periphid = <0x00051180>;
385			interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
386			clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
387			clock-names = "mclk", "apb_pclk";
388			bus-width = <4>;
389			cap-sd-highspeed;
390			cap-mmc-highspeed;
391			max-frequency = <192000000>;
392			no-1-8-v;
393			vmmc-supply = <&vsdcc_fixed>;
394			dmas = <&sdcc3bam 2>, <&sdcc3bam 1>;
395			dma-names = "tx", "rx";
396
397			status = "disabled";
398		};
399
400		sdcc3bam: dma-controller@12182000 {
401			compatible = "qcom,bam-v1.3.0";
402			reg = <0x12182000 0x4000>;
403			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
404			clocks = <&gcc SDC3_H_CLK>;
405			clock-names = "bam_clk";
406			#dma-cells = <1>;
407			qcom,ee = <0>;
408		};
409
410		sdcc1: mmc@12400000 {
411			compatible = "arm,pl18x", "arm,primecell";
412			reg = <0x12400000 0x2000>;
413			arm,primecell-periphid = <0x00051180>;
414			interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
415			clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
416			clock-names = "mclk", "apb_pclk";
417			bus-width = <8>;
418			max-frequency = <96000000>;
419			non-removable;
420			cap-sd-highspeed;
421			cap-mmc-highspeed;
422			vmmc-supply = <&vsdcc_fixed>;
423			dmas = <&sdcc1bam 2>, <&sdcc1bam 1>;
424			dma-names = "tx", "rx";
425
426			status = "disabled";
427		};
428
429		sdcc1bam: dma-controller@12402000 {
430			compatible = "qcom,bam-v1.3.0";
431			reg = <0x12402000 0x4000>;
432			interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
433			clocks = <&gcc SDC1_H_CLK>;
434			clock-names = "bam_clk";
435			#dma-cells = <1>;
436			qcom,ee = <0>;
437		};
438
439		gsbi12: gsbi@12480000 {
440			compatible = "qcom,gsbi-v1.0.0";
441			reg = <0x12480000 0x100>;
442			ranges;
443			cell-index = <12>;
444			clocks = <&gcc GSBI12_H_CLK>;
445			clock-names = "iface";
446			#address-cells = <1>;
447			#size-cells = <1>;
448
449			status = "disabled";
450
451			gsbi12_i2c: i2c@124a0000 {
452				compatible = "qcom,i2c-qup-v1.1.1";
453				reg = <0x124a0000 0x1000>;
454				pinctrl-0 = <&i2c12_default_state>;
455				pinctrl-1 = <&i2c12_sleep_state>;
456				pinctrl-names = "default", "sleep";
457				interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
458				clocks = <&gcc GSBI12_QUP_CLK>,
459					 <&gcc GSBI12_H_CLK>;
460				clock-names = "core",
461					      "iface";
462				#address-cells = <1>;
463				#size-cells = <0>;
464
465				status = "disabled";
466			};
467		};
468
469		usb1: usb@12500000 {
470			compatible = "qcom,ci-hdrc";
471			reg = <0x12500000 0x200>,
472			      <0x12500200 0x200>;
473			interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
474			clocks = <&gcc USB_HS1_XCVR_CLK>, <&gcc USB_HS1_H_CLK>;
475			clock-names = "core", "iface";
476			assigned-clocks = <&gcc USB_HS1_XCVR_CLK>;
477			assigned-clock-rates = <60000000>;
478			resets = <&gcc USB_HS1_RESET>;
479			reset-names = "core";
480			phy_type = "ulpi";
481			ahb-burst-config = <0>;
482			phys = <&usb_hs1_phy>;
483			phy-names = "usb-phy";
484			#reset-cells = <1>;
485
486			status = "disabled";
487
488			ulpi {
489				usb_hs1_phy: phy {
490					compatible = "qcom,usb-hs-phy-msm8960",
491						     "qcom,usb-hs-phy";
492					clocks = <&sleep_clk>, <&cxo_board>;
493					clock-names = "sleep", "ref";
494					resets = <&usb1 0>;
495					reset-names = "por";
496					#phy-cells = <0>;
497				};
498			};
499		};
500
501		gsbi1: gsbi@16000000 {
502			compatible = "qcom,gsbi-v1.0.0";
503			reg = <0x16000000 0x100>;
504			ranges;
505			cell-index = <1>;
506			clocks = <&gcc GSBI1_H_CLK>;
507			clock-names = "iface";
508			#address-cells = <1>;
509			#size-cells = <1>;
510
511			status = "disabled";
512
513			gsbi1_i2c: i2c@16080000 {
514				compatible = "qcom,i2c-qup-v1.1.1";
515				reg = <0x16080000 0x1000>;
516				pinctrl-0 = <&i2c1_default_state>;
517				pinctrl-1 = <&i2c1_sleep_state>;
518				pinctrl-names = "default", "sleep";
519				interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
520				clocks = <&gcc GSBI1_QUP_CLK>,
521					 <&gcc GSBI1_H_CLK>;
522				clock-names = "core",
523					      "iface";
524				#address-cells = <1>;
525				#size-cells = <0>;
526
527				status = "disabled";
528			};
529
530			gsbi1_spi: spi@16080000 {
531				compatible = "qcom,spi-qup-v1.1.1";
532				reg = <0x16080000 0x1000>;
533				#address-cells = <1>;
534				#size-cells = <0>;
535				interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
536				cs-gpios = <&tlmm 8 0>;
537				clocks = <&gcc GSBI1_QUP_CLK>,
538					 <&gcc GSBI1_H_CLK>;
539				clock-names = "core",
540					      "iface";
541
542				status = "disabled";
543			};
544		};
545
546		gsbi3: gsbi@16200000 {
547			compatible = "qcom,gsbi-v1.0.0";
548			reg = <0x16200000 0x100>;
549			ranges;
550			cell-index = <3>;
551			clocks = <&gcc GSBI3_H_CLK>;
552			clock-names = "iface";
553			#address-cells = <1>;
554			#size-cells = <1>;
555
556			status = "disabled";
557
558			gsbi3_i2c: i2c@16280000 {
559				compatible = "qcom,i2c-qup-v1.1.1";
560				reg = <0x16280000 0x1000>;
561				pinctrl-0 = <&i2c3_default_state>;
562				pinctrl-1 = <&i2c3_sleep_state>;
563				pinctrl-names = "default", "sleep";
564				interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
565				clocks = <&gcc GSBI3_QUP_CLK>,
566					 <&gcc GSBI3_H_CLK>;
567				clock-names = "core",
568					      "iface";
569				#address-cells = <1>;
570				#size-cells = <0>;
571
572				status = "disabled";
573			};
574		};
575
576		gsbi5: gsbi@16400000 {
577			compatible = "qcom,gsbi-v1.0.0";
578			reg = <0x16400000 0x100>;
579			ranges;
580			cell-index = <5>;
581			clocks = <&gcc GSBI5_H_CLK>;
582			clock-names = "iface";
583			#address-cells = <1>;
584			#size-cells = <1>;
585			syscon-tcsr = <&tcsr>;
586
587			status = "disabled";
588
589			gsbi5_serial: serial@16440000 {
590				compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
591				reg = <0x16440000 0x1000>,
592				      <0x16400000 0x1000>;
593				interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
594				clocks = <&gcc GSBI5_UART_CLK>,
595					 <&gcc GSBI5_H_CLK>;
596				clock-names = "core",
597					      "iface";
598
599				status = "disabled";
600			};
601		};
602
603		gsbi8: gsbi@1a000000 {
604			compatible = "qcom,gsbi-v1.0.0";
605			reg = <0x1a000000 0x100>;
606			ranges;
607			cell-index = <8>;
608			clocks = <&gcc GSBI8_H_CLK>;
609			clock-names = "iface";
610			#address-cells = <1>;
611			#size-cells = <1>;
612			syscon-tcsr = <&tcsr>;
613
614			status = "disabled";
615
616			gsbi8_serial: serial@1a040000 {
617				compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
618				reg = <0x1a040000 0x1000>,
619				      <0x1a000000 0x1000>;
620				interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
621				clocks = <&gcc GSBI8_UART_CLK>,
622					 <&gcc GSBI8_H_CLK>;
623				clock-names = "core",
624					      "iface";
625
626				status = "disabled";
627			};
628
629			gsbi8_i2c: i2c@1a080000 {
630				compatible = "qcom,i2c-qup-v1.1.1";
631				reg = <0x1a080000 0x1000>;
632				pinctrl-0 = <&i2c8_default_state>;
633				pinctrl-1 = <&i2c8_sleep_state>;
634				pinctrl-names = "default", "sleep";
635				interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
636				clocks = <&gcc GSBI8_QUP_CLK>,
637					 <&gcc GSBI8_H_CLK>;
638				clock-names = "core",
639					      "iface";
640				#address-cells = <1>;
641				#size-cells = <0>;
642
643				status = "disabled";
644			};
645		};
646
647		gsbi10: gsbi@1a200000 {
648			compatible = "qcom,gsbi-v1.0.0";
649			reg = <0x1a200000 0x100>;
650			ranges;
651			cell-index = <10>;
652			clocks = <&gcc GSBI10_H_CLK>;
653			clock-names = "iface";
654			#address-cells = <1>;
655			#size-cells = <1>;
656
657			status = "disabled";
658
659			gsbi10_i2c: i2c@1a280000 {
660				compatible = "qcom,i2c-qup-v1.1.1";
661				reg = <0x1a280000 0x1000>;
662				pinctrl-0 = <&i2c10_default_state>;
663				pinctrl-1 = <&i2c10_sleep_state>;
664				pinctrl-names = "default", "sleep";
665				interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
666				clocks = <&gcc GSBI10_QUP_CLK>,
667					 <&gcc GSBI10_H_CLK>;
668				clock-names = "core",
669					      "iface";
670				#address-cells = <1>;
671				#size-cells = <0>;
672
673				status = "disabled";
674			};
675		};
676
677		tcsr: syscon@1a400000 {
678			compatible = "qcom,tcsr-msm8960", "syscon";
679			reg = <0x1a400000 0x100>;
680		};
681
682		rng@1a500000 {
683			compatible = "qcom,prng";
684			reg = <0x1a500000 0x200>;
685			clocks = <&gcc PRNG_CLK>;
686			clock-names = "core";
687		};
688
689		lcc: clock-controller@28000000 {
690			compatible = "qcom,lcc-msm8960";
691			reg = <0x28000000 0x1000>;
692			#clock-cells = <1>;
693			#reset-cells = <1>;
694			clocks = <&pxo_board>,
695				 <&gcc PLL4_VOTE>,
696				 <0>,
697				 <0>,
698				 <0>,
699				 <0>,
700				 <0>,
701				 <0>;
702			clock-names = "pxo",
703				      "pll4_vote",
704				      "mi2s_codec_clk",
705				      "codec_i2s_mic_codec_clk",
706				      "spare_i2s_mic_codec_clk",
707				      "codec_i2s_spkr_codec_clk",
708				      "spare_i2s_spkr_codec_clk",
709				      "pcm_codec_clk";
710		};
711	};
712
713	thermal-zones {
714		cpu0-thermal {
715			polling-delay-passive = <250>;
716			polling-delay = <1000>;
717			thermal-sensors = <&tsens 0>;
718
719			trips {
720				cpu_alert0: trip0 {
721					temperature = <60000>;
722					hysteresis = <10000>;
723					type = "passive";
724				};
725
726				cpu_crit0: trip1 {
727					temperature = <95000>;
728					hysteresis = <10000>;
729					type = "critical";
730				};
731			};
732		};
733
734		cpu1-thermal {
735			polling-delay-passive = <250>;
736			polling-delay = <1000>;
737			thermal-sensors = <&tsens 1>;
738
739			trips {
740				cpu_alert1: trip0 {
741					temperature = <60000>;
742					hysteresis = <10000>;
743					type = "passive";
744				};
745
746				cpu_crit1: trip1 {
747					temperature = <95000>;
748					hysteresis = <10000>;
749					type = "critical";
750				};
751			};
752		};
753	};
754
755	/* Temporary fixed regulator */
756	vsdcc_fixed: vsdcc-regulator {
757		compatible = "regulator-fixed";
758		regulator-name = "SDCC Power";
759		regulator-min-microvolt = <2700000>;
760		regulator-max-microvolt = <2700000>;
761		regulator-always-on;
762	};
763};
764