1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2015 Prevas A/S
4 */
5
6 #include <linux/device.h>
7 #include <linux/kernel.h>
8 #include <linux/slab.h>
9 #include <linux/spi/spi.h>
10 #include <linux/regulator/consumer.h>
11 #include <linux/err.h>
12 #include <linux/module.h>
13
14 #include <linux/iio/iio.h>
15 #include <linux/iio/buffer.h>
16 #include <linux/iio/trigger_consumer.h>
17 #include <linux/iio/triggered_buffer.h>
18
19 #define ADS8688_CMD_REG(x) (x << 8)
20 #define ADS8688_CMD_REG_NOOP 0x00
21 #define ADS8688_CMD_REG_RST 0x85
22 #define ADS8688_CMD_REG_MAN_CH(chan) (0xC0 | (4 * chan))
23 #define ADS8688_CMD_DONT_CARE_BITS 16
24
25 #define ADS8688_PROG_REG(x) (x << 9)
26 #define ADS8688_PROG_REG_RANGE_CH(chan) (0x05 + chan)
27 #define ADS8688_PROG_WR_BIT BIT(8)
28 #define ADS8688_PROG_DONT_CARE_BITS 8
29
30 #define ADS8688_REG_PLUSMINUS25VREF 0
31 #define ADS8688_REG_PLUSMINUS125VREF 1
32 #define ADS8688_REG_PLUSMINUS0625VREF 2
33 #define ADS8688_REG_PLUS25VREF 5
34 #define ADS8688_REG_PLUS125VREF 6
35
36 #define ADS8688_VREF_MV 4096
37 #define ADS8688_REALBITS 16
38 #define ADS8688_MAX_CHANNELS 8
39
40 /*
41 * enum ads8688_range - ADS8688 reference voltage range
42 * @ADS8688_PLUSMINUS25VREF: Device is configured for input range ±2.5 * VREF
43 * @ADS8688_PLUSMINUS125VREF: Device is configured for input range ±1.25 * VREF
44 * @ADS8688_PLUSMINUS0625VREF: Device is configured for input range ±0.625 * VREF
45 * @ADS8688_PLUS25VREF: Device is configured for input range 0 - 2.5 * VREF
46 * @ADS8688_PLUS125VREF: Device is configured for input range 0 - 1.25 * VREF
47 */
48 enum ads8688_range {
49 ADS8688_PLUSMINUS25VREF,
50 ADS8688_PLUSMINUS125VREF,
51 ADS8688_PLUSMINUS0625VREF,
52 ADS8688_PLUS25VREF,
53 ADS8688_PLUS125VREF,
54 };
55
56 struct ads8688_chip_info {
57 const struct iio_chan_spec *channels;
58 unsigned int num_channels;
59 };
60
61 struct ads8688_state {
62 struct mutex lock;
63 const struct ads8688_chip_info *chip_info;
64 struct spi_device *spi;
65 unsigned int vref_mv;
66 int scale_avail[3][2];
67 enum ads8688_range range[8];
68 union {
69 __be32 d32;
70 u8 d8[4];
71 } data[2] __aligned(IIO_DMA_MINALIGN);
72 };
73
74 enum ads8688_id {
75 ID_ADS8684,
76 ID_ADS8688,
77 };
78
79 struct ads8688_ranges {
80 enum ads8688_range range;
81 unsigned int scale;
82 int offset;
83 u8 reg;
84 };
85
86 static const struct ads8688_ranges ads8688_range_def[5] = {
87 {
88 .range = ADS8688_PLUSMINUS25VREF,
89 .scale = 76295,
90 .offset = -(1 << (ADS8688_REALBITS - 1)),
91 .reg = ADS8688_REG_PLUSMINUS25VREF,
92 }, {
93 .range = ADS8688_PLUSMINUS125VREF,
94 .scale = 38148,
95 .offset = -(1 << (ADS8688_REALBITS - 1)),
96 .reg = ADS8688_REG_PLUSMINUS125VREF,
97 }, {
98 .range = ADS8688_PLUSMINUS0625VREF,
99 .scale = 19074,
100 .offset = -(1 << (ADS8688_REALBITS - 1)),
101 .reg = ADS8688_REG_PLUSMINUS0625VREF,
102 }, {
103 .range = ADS8688_PLUS25VREF,
104 .scale = 38148,
105 .offset = 0,
106 .reg = ADS8688_REG_PLUS25VREF,
107 }, {
108 .range = ADS8688_PLUS125VREF,
109 .scale = 19074,
110 .offset = 0,
111 .reg = ADS8688_REG_PLUS125VREF,
112 }
113 };
114
115 static const int ads8688_offset_avail[] = {
116 -(1 << (ADS8688_REALBITS - 1)),
117 0
118 };
119
120 #define ADS8688_CHAN(index) \
121 { \
122 .type = IIO_VOLTAGE, \
123 .indexed = 1, \
124 .channel = index, \
125 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) \
126 | BIT(IIO_CHAN_INFO_SCALE) \
127 | BIT(IIO_CHAN_INFO_OFFSET), \
128 .info_mask_shared_by_type_available = \
129 BIT(IIO_CHAN_INFO_SCALE) \
130 | BIT(IIO_CHAN_INFO_OFFSET), \
131 .scan_index = index, \
132 .scan_type = { \
133 .sign = 'u', \
134 .realbits = 16, \
135 .storagebits = 16, \
136 .endianness = IIO_BE, \
137 }, \
138 }
139
140 static const struct iio_chan_spec ads8684_channels[] = {
141 ADS8688_CHAN(0),
142 ADS8688_CHAN(1),
143 ADS8688_CHAN(2),
144 ADS8688_CHAN(3),
145 };
146
147 static const struct iio_chan_spec ads8688_channels[] = {
148 ADS8688_CHAN(0),
149 ADS8688_CHAN(1),
150 ADS8688_CHAN(2),
151 ADS8688_CHAN(3),
152 ADS8688_CHAN(4),
153 ADS8688_CHAN(5),
154 ADS8688_CHAN(6),
155 ADS8688_CHAN(7),
156 };
157
ads8688_prog_write(struct iio_dev * indio_dev,unsigned int addr,unsigned int val)158 static int ads8688_prog_write(struct iio_dev *indio_dev, unsigned int addr,
159 unsigned int val)
160 {
161 struct ads8688_state *st = iio_priv(indio_dev);
162 u32 tmp;
163
164 tmp = ADS8688_PROG_REG(addr) | ADS8688_PROG_WR_BIT | val;
165 tmp <<= ADS8688_PROG_DONT_CARE_BITS;
166 st->data[0].d32 = cpu_to_be32(tmp);
167
168 return spi_write(st->spi, &st->data[0].d8[1], 3);
169 }
170
ads8688_reset(struct iio_dev * indio_dev)171 static int ads8688_reset(struct iio_dev *indio_dev)
172 {
173 struct ads8688_state *st = iio_priv(indio_dev);
174 u32 tmp;
175
176 tmp = ADS8688_CMD_REG(ADS8688_CMD_REG_RST);
177 tmp <<= ADS8688_CMD_DONT_CARE_BITS;
178 st->data[0].d32 = cpu_to_be32(tmp);
179
180 return spi_write(st->spi, &st->data[0].d8[0], 4);
181 }
182
ads8688_read(struct iio_dev * indio_dev,unsigned int chan)183 static int ads8688_read(struct iio_dev *indio_dev, unsigned int chan)
184 {
185 struct ads8688_state *st = iio_priv(indio_dev);
186 int ret;
187 u32 tmp;
188 struct spi_transfer t[] = {
189 {
190 .tx_buf = &st->data[0].d8[0],
191 .len = 4,
192 .cs_change = 1,
193 }, {
194 .tx_buf = &st->data[1].d8[0],
195 .rx_buf = &st->data[1].d8[0],
196 .len = 4,
197 },
198 };
199
200 tmp = ADS8688_CMD_REG(ADS8688_CMD_REG_MAN_CH(chan));
201 tmp <<= ADS8688_CMD_DONT_CARE_BITS;
202 st->data[0].d32 = cpu_to_be32(tmp);
203
204 tmp = ADS8688_CMD_REG(ADS8688_CMD_REG_NOOP);
205 tmp <<= ADS8688_CMD_DONT_CARE_BITS;
206 st->data[1].d32 = cpu_to_be32(tmp);
207
208 ret = spi_sync_transfer(st->spi, t, ARRAY_SIZE(t));
209 if (ret < 0)
210 return ret;
211
212 return be32_to_cpu(st->data[1].d32) & 0xffff;
213 }
214
ads8688_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long m)215 static int ads8688_read_raw(struct iio_dev *indio_dev,
216 struct iio_chan_spec const *chan,
217 int *val, int *val2, long m)
218 {
219 int ret, offset;
220 unsigned long scale_mv;
221
222 struct ads8688_state *st = iio_priv(indio_dev);
223
224 mutex_lock(&st->lock);
225 switch (m) {
226 case IIO_CHAN_INFO_RAW:
227 ret = ads8688_read(indio_dev, chan->channel);
228 mutex_unlock(&st->lock);
229 if (ret < 0)
230 return ret;
231 *val = ret;
232 return IIO_VAL_INT;
233 case IIO_CHAN_INFO_SCALE:
234 scale_mv = st->vref_mv;
235 scale_mv *= ads8688_range_def[st->range[chan->channel]].scale;
236 *val = 0;
237 *val2 = scale_mv;
238 mutex_unlock(&st->lock);
239 return IIO_VAL_INT_PLUS_NANO;
240 case IIO_CHAN_INFO_OFFSET:
241 offset = ads8688_range_def[st->range[chan->channel]].offset;
242 *val = offset;
243 mutex_unlock(&st->lock);
244 return IIO_VAL_INT;
245 }
246 mutex_unlock(&st->lock);
247
248 return -EINVAL;
249 }
250
ads8688_write_reg_range(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,enum ads8688_range range)251 static int ads8688_write_reg_range(struct iio_dev *indio_dev,
252 struct iio_chan_spec const *chan,
253 enum ads8688_range range)
254 {
255 unsigned int tmp;
256
257 tmp = ADS8688_PROG_REG_RANGE_CH(chan->channel);
258
259 return ads8688_prog_write(indio_dev, tmp, range);
260 }
261
ads8688_write_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int val,int val2,long mask)262 static int ads8688_write_raw(struct iio_dev *indio_dev,
263 struct iio_chan_spec const *chan,
264 int val, int val2, long mask)
265 {
266 struct ads8688_state *st = iio_priv(indio_dev);
267 unsigned int scale = 0;
268 int ret = -EINVAL, i, offset = 0;
269
270 mutex_lock(&st->lock);
271 switch (mask) {
272 case IIO_CHAN_INFO_SCALE:
273 /* If the offset is 0 the ±2.5 * VREF mode is not available */
274 offset = ads8688_range_def[st->range[chan->channel]].offset;
275 if (offset == 0 && val2 == ads8688_range_def[0].scale * st->vref_mv) {
276 mutex_unlock(&st->lock);
277 return -EINVAL;
278 }
279
280 /* Lookup new mode */
281 for (i = 0; i < ARRAY_SIZE(ads8688_range_def); i++)
282 if (val2 == ads8688_range_def[i].scale * st->vref_mv &&
283 offset == ads8688_range_def[i].offset) {
284 ret = ads8688_write_reg_range(indio_dev, chan,
285 ads8688_range_def[i].reg);
286 break;
287 }
288 break;
289 case IIO_CHAN_INFO_OFFSET:
290 /*
291 * There are only two available offsets:
292 * 0 and -(1 << (ADS8688_REALBITS - 1))
293 */
294 if (!(ads8688_range_def[0].offset == val ||
295 ads8688_range_def[3].offset == val)) {
296 mutex_unlock(&st->lock);
297 return -EINVAL;
298 }
299
300 /*
301 * If the device are in ±2.5 * VREF mode, it's not allowed to
302 * switch to a mode where the offset is 0
303 */
304 if (val == 0 &&
305 st->range[chan->channel] == ADS8688_PLUSMINUS25VREF) {
306 mutex_unlock(&st->lock);
307 return -EINVAL;
308 }
309
310 scale = ads8688_range_def[st->range[chan->channel]].scale;
311
312 /* Lookup new mode */
313 for (i = 0; i < ARRAY_SIZE(ads8688_range_def); i++)
314 if (val == ads8688_range_def[i].offset &&
315 scale == ads8688_range_def[i].scale) {
316 ret = ads8688_write_reg_range(indio_dev, chan,
317 ads8688_range_def[i].reg);
318 break;
319 }
320 break;
321 }
322
323 if (!ret)
324 st->range[chan->channel] = ads8688_range_def[i].range;
325
326 mutex_unlock(&st->lock);
327
328 return ret;
329 }
330
ads8688_write_raw_get_fmt(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,long mask)331 static int ads8688_write_raw_get_fmt(struct iio_dev *indio_dev,
332 struct iio_chan_spec const *chan,
333 long mask)
334 {
335 switch (mask) {
336 case IIO_CHAN_INFO_SCALE:
337 return IIO_VAL_INT_PLUS_NANO;
338 case IIO_CHAN_INFO_OFFSET:
339 return IIO_VAL_INT;
340 }
341
342 return -EINVAL;
343 }
344
ads8688_read_avail(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,const int ** vals,int * type,int * length,long mask)345 static int ads8688_read_avail(struct iio_dev *indio_dev,
346 struct iio_chan_spec const *chan,
347 const int **vals, int *type, int *length,
348 long mask)
349 {
350 struct ads8688_state *st = iio_priv(indio_dev);
351
352 switch (mask) {
353 case IIO_CHAN_INFO_SCALE:
354 *vals = (const int *)st->scale_avail;
355 *type = IIO_VAL_INT_PLUS_NANO;
356 *length = ARRAY_SIZE(st->scale_avail) * 2;
357 return IIO_AVAIL_LIST;
358 case IIO_CHAN_INFO_OFFSET:
359 *vals = ads8688_offset_avail;
360 *type = IIO_VAL_INT;
361 *length = ARRAY_SIZE(ads8688_offset_avail);
362 return IIO_AVAIL_LIST;
363 default:
364 return -EINVAL;
365 }
366 }
367
368 static const struct iio_info ads8688_info = {
369 .read_raw = &ads8688_read_raw,
370 .read_avail = &ads8688_read_avail,
371 .write_raw = &ads8688_write_raw,
372 .write_raw_get_fmt = &ads8688_write_raw_get_fmt,
373 };
374
ads8688_trigger_handler(int irq,void * p)375 static irqreturn_t ads8688_trigger_handler(int irq, void *p)
376 {
377 struct iio_poll_func *pf = p;
378 struct iio_dev *indio_dev = pf->indio_dev;
379 /* Ensure naturally aligned timestamp */
380 u16 buffer[ADS8688_MAX_CHANNELS + sizeof(s64)/sizeof(u16)] __aligned(8) = { };
381 int i, j = 0;
382
383 iio_for_each_active_channel(indio_dev, i) {
384 buffer[j] = ads8688_read(indio_dev, i);
385 j++;
386 }
387
388 iio_push_to_buffers_with_ts(indio_dev, buffer, sizeof(buffer),
389 iio_get_time_ns(indio_dev));
390
391 iio_trigger_notify_done(indio_dev->trig);
392
393 return IRQ_HANDLED;
394 }
395
396 static const struct ads8688_chip_info ads8688_chip_info_tbl[] = {
397 [ID_ADS8684] = {
398 .channels = ads8684_channels,
399 .num_channels = ARRAY_SIZE(ads8684_channels),
400 },
401 [ID_ADS8688] = {
402 .channels = ads8688_channels,
403 .num_channels = ARRAY_SIZE(ads8688_channels),
404 },
405 };
406
ads8688_probe(struct spi_device * spi)407 static int ads8688_probe(struct spi_device *spi)
408 {
409 struct ads8688_state *st;
410 struct iio_dev *indio_dev;
411 int ret;
412
413 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
414 if (indio_dev == NULL)
415 return -ENOMEM;
416
417 st = iio_priv(indio_dev);
418
419 ret = devm_regulator_get_enable_read_voltage(&spi->dev, "vref");
420 if (ret < 0 && ret != -ENODEV)
421 return ret;
422
423 st->vref_mv = ret == -ENODEV ? ADS8688_VREF_MV : ret / 1000;
424
425 for (unsigned int i = 0; i < ARRAY_SIZE(st->scale_avail); i++) {
426 st->scale_avail[i][0] = 0;
427 st->scale_avail[i][1] = ads8688_range_def[i].scale * st->vref_mv;
428 }
429
430 st->chip_info = &ads8688_chip_info_tbl[spi_get_device_id(spi)->driver_data];
431
432 spi->mode = SPI_MODE_1;
433
434 st->spi = spi;
435
436 indio_dev->name = spi_get_device_id(spi)->name;
437 indio_dev->modes = INDIO_DIRECT_MODE;
438 indio_dev->channels = st->chip_info->channels;
439 indio_dev->num_channels = st->chip_info->num_channels;
440 indio_dev->info = &ads8688_info;
441
442 ads8688_reset(indio_dev);
443
444 mutex_init(&st->lock);
445
446 ret = devm_iio_triggered_buffer_setup(&spi->dev, indio_dev, NULL,
447 ads8688_trigger_handler, NULL);
448 if (ret < 0)
449 return dev_err_probe(&spi->dev, ret,
450 "iio triggered buffer setup failed\n");
451
452 return devm_iio_device_register(&spi->dev, indio_dev);
453 }
454
455 static const struct spi_device_id ads8688_id[] = {
456 { .name = "ads8684", .driver_data = ID_ADS8684 },
457 { .name = "ads8688", .driver_data = ID_ADS8688 },
458 { }
459 };
460 MODULE_DEVICE_TABLE(spi, ads8688_id);
461
462 static const struct of_device_id ads8688_of_match[] = {
463 { .compatible = "ti,ads8684" },
464 { .compatible = "ti,ads8688" },
465 { }
466 };
467 MODULE_DEVICE_TABLE(of, ads8688_of_match);
468
469 static struct spi_driver ads8688_driver = {
470 .driver = {
471 .name = "ads8688",
472 .of_match_table = ads8688_of_match,
473 },
474 .probe = ads8688_probe,
475 .id_table = ads8688_id,
476 };
477 module_spi_driver(ads8688_driver);
478
479 MODULE_AUTHOR("Sean Nyekjaer <sean@geanix.dk>");
480 MODULE_DESCRIPTION("Texas Instruments ADS8688 driver");
481 MODULE_LICENSE("GPL v2");
482