1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright 2025 Cix Technology Group Co., Ltd. 4 * 5 */ 6 7#include <dt-bindings/interrupt-controller/arm-gic.h> 8#include <dt-bindings/clock/cix,sky1.h> 9#include "sky1-power.h" 10 11/ { 12 interrupt-parent = <&gic>; 13 #address-cells = <2>; 14 #size-cells = <2>; 15 16 cpus { 17 #address-cells = <2>; 18 #size-cells = <0>; 19 20 cpu0: cpu@0 { 21 compatible = "arm,cortex-a520"; 22 enable-method = "psci"; 23 reg = <0x0 0x0>; 24 device_type = "cpu"; 25 capacity-dmips-mhz = <403>; 26 }; 27 28 cpu1: cpu@100 { 29 compatible = "arm,cortex-a520"; 30 enable-method = "psci"; 31 reg = <0x0 0x100>; 32 device_type = "cpu"; 33 capacity-dmips-mhz = <403>; 34 }; 35 36 cpu2: cpu@200 { 37 compatible = "arm,cortex-a520"; 38 enable-method = "psci"; 39 reg = <0x0 0x200>; 40 device_type = "cpu"; 41 capacity-dmips-mhz = <403>; 42 }; 43 44 cpu3: cpu@300 { 45 compatible = "arm,cortex-a520"; 46 enable-method = "psci"; 47 reg = <0x0 0x300>; 48 device_type = "cpu"; 49 capacity-dmips-mhz = <403>; 50 }; 51 52 cpu4: cpu@400 { 53 compatible = "arm,cortex-a720"; 54 enable-method = "psci"; 55 reg = <0x0 0x400>; 56 device_type = "cpu"; 57 capacity-dmips-mhz = <1024>; 58 }; 59 60 cpu5: cpu@500 { 61 compatible = "arm,cortex-a720"; 62 enable-method = "psci"; 63 reg = <0x0 0x500>; 64 device_type = "cpu"; 65 capacity-dmips-mhz = <1024>; 66 }; 67 68 cpu6: cpu@600 { 69 compatible = "arm,cortex-a720"; 70 enable-method = "psci"; 71 reg = <0x0 0x600>; 72 device_type = "cpu"; 73 capacity-dmips-mhz = <1024>; 74 }; 75 76 cpu7: cpu@700 { 77 compatible = "arm,cortex-a720"; 78 enable-method = "psci"; 79 reg = <0x0 0x700>; 80 device_type = "cpu"; 81 capacity-dmips-mhz = <1024>; 82 }; 83 84 cpu8: cpu@800 { 85 compatible = "arm,cortex-a720"; 86 enable-method = "psci"; 87 reg = <0x0 0x800>; 88 device_type = "cpu"; 89 capacity-dmips-mhz = <1024>; 90 }; 91 92 cpu9: cpu@900 { 93 compatible = "arm,cortex-a720"; 94 enable-method = "psci"; 95 reg = <0x0 0x900>; 96 device_type = "cpu"; 97 capacity-dmips-mhz = <1024>; 98 }; 99 100 cpu10: cpu@a00 { 101 compatible = "arm,cortex-a720"; 102 enable-method = "psci"; 103 reg = <0x0 0xa00>; 104 device_type = "cpu"; 105 capacity-dmips-mhz = <1024>; 106 }; 107 108 cpu11: cpu@b00 { 109 compatible = "arm,cortex-a720"; 110 enable-method = "psci"; 111 reg = <0x0 0xb00>; 112 device_type = "cpu"; 113 capacity-dmips-mhz = <1024>; 114 }; 115 116 cpu-map { 117 cluster0 { 118 core0 { 119 cpu = <&cpu0>; 120 }; 121 core1 { 122 cpu = <&cpu1>; 123 }; 124 core2 { 125 cpu = <&cpu2>; 126 }; 127 core3 { 128 cpu = <&cpu3>; 129 }; 130 core4 { 131 cpu = <&cpu4>; 132 }; 133 core5 { 134 cpu = <&cpu5>; 135 }; 136 core6 { 137 cpu = <&cpu6>; 138 }; 139 core7 { 140 cpu = <&cpu7>; 141 }; 142 core8 { 143 cpu = <&cpu8>; 144 }; 145 core9 { 146 cpu = <&cpu9>; 147 }; 148 core10 { 149 cpu = <&cpu10>; 150 }; 151 core11 { 152 cpu = <&cpu11>; 153 }; 154 }; 155 }; 156 }; 157 158 firmware { 159 ap_to_pm_scmi: scmi { 160 compatible = "arm,scmi"; 161 mbox-names = "tx", "rx"; 162 mboxes = <&mbox_ap2pm 8>, <&mbox_pm2ap 8>; 163 shmem = <&ap2pm_scmi_mem>, <&pm2ap_scmi_mem>; 164 #address-cells = <1>; 165 #size-cells = <0>; 166 167 scmi_clk: protocol@14 { 168 reg = <0x14>; 169 #clock-cells = <1>; 170 }; 171 }; 172 173 ap_to_tfa_scmi: scmi-1 { 174 compatible = "arm,scmi-smc"; 175 arm,smc-id = <0xc2000001>; 176 #address-cells = <1>; 177 #size-cells = <0>; 178 shmem = <&ap_tfa_scmi_mem>; 179 180 smc_devpd: protocol@11 { 181 reg = <0x11>; 182 #power-domain-cells = <1>; 183 }; 184 }; 185 }; 186 187 pmu-a520 { 188 compatible = "arm,cortex-a520-pmu"; 189 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_partition0>; 190 }; 191 192 pmu-a720 { 193 compatible = "arm,cortex-a720-pmu"; 194 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_partition1>; 195 }; 196 197 psci { 198 compatible = "arm,psci-1.0"; 199 method = "smc"; 200 }; 201 202 s5_gpio_apb_clk: clock-100000000 { 203 compatible = "fixed-clock"; 204 #clock-cells = <0>; 205 clock-frequency = <100000000>; 206 clock-output-names = "s5_gpio_apb_clk"; 207 }; 208 209 soc@0 { 210 compatible = "simple-bus"; 211 ranges = <0 0 0 0 0x20 0>; 212 dma-ranges; 213 #address-cells = <2>; 214 #size-cells = <2>; 215 216 i2c0: i2c@4010000 { 217 compatible = "cdns,i2c-r1p14"; 218 reg = <0x0 0x04010000 0x0 0x10000>; 219 clock-frequency = <400000>; 220 clocks = <&scmi_clk CLK_TREE_FCH_I2C0_APB>; 221 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH 0>; 222 status = "disabled"; 223 }; 224 225 i2c1: i2c@4020000 { 226 compatible = "cdns,i2c-r1p14"; 227 reg = <0x0 0x04020000 0x0 0x10000>; 228 clock-frequency = <400000>; 229 clocks = <&scmi_clk CLK_TREE_FCH_I2C1_APB>; 230 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH 0>; 231 status = "disabled"; 232 }; 233 234 i2c2: i2c@4030000 { 235 compatible = "cdns,i2c-r1p14"; 236 reg = <0x0 0x04030000 0x0 0x10000>; 237 clock-frequency = <400000>; 238 clocks = <&scmi_clk CLK_TREE_FCH_I2C2_APB>; 239 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH 0>; 240 status = "disabled"; 241 }; 242 243 i2c3: i2c@4040000 { 244 compatible = "cdns,i2c-r1p14"; 245 reg = <0x0 0x04040000 0x0 0x10000>; 246 clock-frequency = <400000>; 247 clocks = <&scmi_clk CLK_TREE_FCH_I2C3_APB>; 248 interrupts = <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH 0>; 249 status = "disabled"; 250 }; 251 252 i2c4: i2c@4050000 { 253 compatible = "cdns,i2c-r1p14"; 254 reg = <0x0 0x04050000 0x0 0x10000>; 255 clock-frequency = <400000>; 256 clocks = <&scmi_clk CLK_TREE_FCH_I2C4_APB>; 257 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH 0>; 258 status = "disabled"; 259 }; 260 261 i2c5: i2c@4060000 { 262 compatible = "cdns,i2c-r1p14"; 263 reg = <0x0 0x04060000 0x0 0x10000>; 264 clock-frequency = <400000>; 265 clocks = <&scmi_clk CLK_TREE_FCH_I2C5_APB>; 266 interrupts = <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH 0>; 267 status = "disabled"; 268 }; 269 270 i2c6: i2c@4070000 { 271 compatible = "cdns,i2c-r1p14"; 272 reg = <0x0 0x04070000 0x0 0x10000>; 273 clock-frequency = <400000>; 274 clocks = <&scmi_clk CLK_TREE_FCH_I2C6_APB>; 275 interrupts = <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH 0>; 276 status = "disabled"; 277 }; 278 279 i2c7: i2c@4080000 { 280 compatible = "cdns,i2c-r1p14"; 281 reg = <0x0 0x04080000 0x0 0x10000>; 282 clock-frequency = <400000>; 283 clocks = <&scmi_clk CLK_TREE_FCH_I2C7_APB>; 284 interrupts = <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH 0>; 285 status = "disabled"; 286 }; 287 288 spi0: spi@4090000 { 289 compatible = "cix,sky1-spi-r1p6", "cdns,spi-r1p6"; 290 reg = <0x0 0x04090000 0x0 0x10000>; 291 clocks = <&scmi_clk CLK_TREE_FCH_SPI0_APB>, 292 <&scmi_clk CLK_TREE_FCH_SPI0_APB>; 293 clock-names = "ref_clk", "pclk"; 294 interrupts = <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH 0>; 295 status = "disabled"; 296 }; 297 298 spi1: spi@40a0000 { 299 compatible = "cix,sky1-spi-r1p6", "cdns,spi-r1p6"; 300 reg = <0x0 0x040a0000 0x0 0x10000>; 301 clocks = <&scmi_clk CLK_TREE_FCH_SPI1_APB>, 302 <&scmi_clk CLK_TREE_FCH_SPI1_APB>; 303 clock-names = "ref_clk", "pclk"; 304 interrupts = <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH 0>; 305 status = "disabled"; 306 }; 307 308 uart0: serial@40b0000 { 309 compatible = "arm,pl011", "arm,primecell"; 310 reg = <0x0 0x040b0000 0x0 0x1000>; 311 interrupts = <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH 0>; 312 clocks = <&scmi_clk CLK_TREE_FCH_UART0_FUNC>, <&scmi_clk CLK_TREE_FCH_UART0_APB>; 313 clock-names = "uartclk", "apb_pclk"; 314 status = "disabled"; 315 }; 316 317 uart1: serial@40c0000 { 318 compatible = "arm,pl011", "arm,primecell"; 319 reg = <0x0 0x040c0000 0x0 0x1000>; 320 interrupts = <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH 0>; 321 clocks = <&scmi_clk CLK_TREE_FCH_UART1_FUNC>, <&scmi_clk CLK_TREE_FCH_UART1_APB>; 322 clock-names = "uartclk", "apb_pclk"; 323 status = "disabled"; 324 }; 325 326 uart2: serial@40d0000 { 327 compatible = "arm,pl011", "arm,primecell"; 328 reg = <0x0 0x040d0000 0x0 0x1000>; 329 interrupts = <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH 0>; 330 clocks = <&scmi_clk CLK_TREE_FCH_UART2_FUNC>, <&scmi_clk CLK_TREE_FCH_UART2_APB>; 331 clock-names = "uartclk", "apb_pclk"; 332 status = "disabled"; 333 }; 334 335 uart3: serial@40e0000 { 336 compatible = "arm,pl011", "arm,primecell"; 337 reg = <0x0 0x040e0000 0x0 0x1000>; 338 interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH 0>; 339 clocks = <&scmi_clk CLK_TREE_FCH_UART3_FUNC>, <&scmi_clk CLK_TREE_FCH_UART3_APB>; 340 clock-names = "uartclk", "apb_pclk"; 341 status = "disabled"; 342 }; 343 344 i3c0: i3c@40f0000 { 345 compatible = "cdns,i3c-master"; 346 reg = <0x0 0x040f0000 0x0 0x10000>; 347 #address-cells = <3>; 348 #size-cells = <0>; 349 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH 0>; 350 clocks = <&scmi_clk CLK_TREE_FCH_I3C0_APB>, 351 <&scmi_clk CLK_TREE_FCH_I3C0_FUNC>; 352 clock-names = "pclk", "sysclk"; 353 i3c-scl-hz = <400000>; 354 i2c-scl-hz = <100000>; 355 status = "disabled"; 356 }; 357 358 i3c1: i3c@4100000 { 359 compatible = "cdns,i3c-master"; 360 reg = <0x0 0x04100000 0x0 0x10000>; 361 #address-cells = <3>; 362 #size-cells = <0>; 363 interrupts = <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH 0>; 364 clocks = <&scmi_clk CLK_TREE_FCH_I3C1_APB>, 365 <&scmi_clk CLK_TREE_FCH_I3C1_FUNC>; 366 clock-names = "pclk", "sysclk"; 367 i3c-scl-hz = <400000>; 368 i2c-scl-hz = <100000>; 369 status = "disabled"; 370 }; 371 372 fch_gpio0: gpio-controller@4120000 { 373 compatible = "cdns,gpio-r1p02"; 374 reg = <0x0 0x4120000 0x0 0x1000>; 375 clocks = <&scmi_clk CLK_TREE_FCH_GPIO_APB>; 376 377 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH 0>; 378 379 gpio-controller; 380 #gpio-cells = <2>; 381 ngpios = <32>; 382 383 interrupt-controller; 384 #interrupt-cells = <2>; 385 status = "disabled"; 386 }; 387 388 fch_gpio1: gpio-controller@4130000 { 389 compatible = "cdns,gpio-r1p02"; 390 reg = <0x0 0x4130000 0x0 0x1000>; 391 clocks = <&scmi_clk CLK_TREE_FCH_GPIO_APB>; 392 393 interrupts = <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH 0>; 394 395 gpio-controller; 396 #gpio-cells = <2>; 397 ngpios = <32>; 398 399 interrupt-controller; 400 #interrupt-cells = <2>; 401 status = "disabled"; 402 }; 403 404 fch_gpio2: gpio-controller@4140000 { 405 compatible = "cdns,gpio-r1p02"; 406 reg = <0x0 0x4140000 0x0 0x1000>; 407 clocks = <&scmi_clk CLK_TREE_FCH_GPIO_APB>; 408 409 interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH 0>; 410 411 gpio-controller; 412 #gpio-cells = <2>; 413 ngpios = <32>; 414 415 interrupt-controller; 416 #interrupt-cells = <2>; 417 status = "disabled"; 418 }; 419 420 fch_gpio3: gpio-controller@4150000 { 421 compatible = "cdns,gpio-r1p02"; 422 reg = <0x0 0x4150000 0x0 0x1000>; 423 clocks = <&scmi_clk CLK_TREE_FCH_GPIO_APB>; 424 425 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH 0>; 426 427 gpio-controller; 428 #gpio-cells = <2>; 429 ngpios = <17>; 430 431 interrupt-controller; 432 #interrupt-cells = <2>; 433 status = "disabled"; 434 }; 435 436 syscon: syscon@4160000 { 437 compatible = "cix,sky1-system-control", "syscon"; 438 reg = <0x0 0x4160000 0x0 0x100>; 439 #reset-cells = <1>; 440 }; 441 442 iomuxc: pinctrl@4170000 { 443 compatible = "cix,sky1-pinctrl"; 444 reg = <0x0 0x04170000 0x0 0x1000>; 445 }; 446 447 mbox_ap2se: mailbox@5060000 { 448 compatible = "cix,sky1-mbox"; 449 reg = <0x0 0x05060000 0x0 0x10000>; 450 interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH 0>; 451 #mbox-cells = <1>; 452 cix,mbox-dir = "tx"; 453 }; 454 455 mbox_se2ap: mailbox@5070000 { 456 compatible = "cix,sky1-mbox"; 457 reg = <0x0 0x05070000 0x0 0x10000>; 458 interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH 0>; 459 #mbox-cells = <1>; 460 cix,mbox-dir = "rx"; 461 }; 462 463 ap2pm_scmi_mem: shmem@6590000 { 464 compatible = "arm,scmi-shmem"; 465 reg = <0x0 0x06590000 0x0 0x80>; 466 reg-io-width = <4>; 467 }; 468 469 mbox_ap2pm: mailbox@6590080 { 470 compatible = "cix,sky1-mbox"; 471 reg = <0x0 0x06590080 0x0 0xff80>; 472 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH 0>; 473 #mbox-cells = <1>; 474 cix,mbox-dir = "tx"; 475 }; 476 477 pm2ap_scmi_mem: shmem@65a0000 { 478 compatible = "arm,scmi-shmem"; 479 reg = <0x0 0x065a0000 0x0 0x80>; 480 reg-io-width = <4>; 481 }; 482 483 mbox_pm2ap: mailbox@65a0080 { 484 compatible = "cix,sky1-mbox"; 485 reg = <0x0 0x065a0080 0x0 0xff80>; 486 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH 0>; 487 #mbox-cells = <1>; 488 cix,mbox-dir = "rx"; 489 }; 490 491 mbox_sfh2ap: mailbox@8090000 { 492 compatible = "cix,sky1-mbox"; 493 reg = <0x0 0x08090000 0x0 0x10000>; 494 interrupts = <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH 0>; 495 #mbox-cells = <1>; 496 cix,mbox-dir = "rx"; 497 }; 498 499 mbox_ap2sfh: mailbox@80a0000 { 500 compatible = "cix,sky1-mbox"; 501 reg = <0x0 0x080a0000 0x0 0x10000>; 502 interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH 0>; 503 #mbox-cells = <1>; 504 cix,mbox-dir = "tx"; 505 }; 506 507 pcie_x8_rc: pcie@a010000 { 508 compatible = "cix,sky1-pcie-host"; 509 reg = <0x00 0x0a010000 0x00 0x10000>, 510 <0x00 0x2c000000 0x00 0x4000000>, 511 <0x00 0x0a000300 0x00 0x100>, 512 <0x00 0x0a000400 0x00 0x100>, 513 <0x00 0x60000000 0x00 0x00100000>; 514 reg-names = "reg", "cfg", "rcsu_strap", "rcsu_status", "msg"; 515 ranges = <0x01000000 0x0 0x60100000 0x0 0x60100000 0x0 0x00100000>, 516 <0x02000000 0x0 0x60200000 0x0 0x60200000 0x0 0x1fe00000>, 517 <0x43000000 0x18 0x00000000 0x18 0x00000000 0x04 0x00000000>; 518 #address-cells = <3>; 519 #size-cells = <2>; 520 bus-range = <0xc0 0xff>; 521 device_type = "pci"; 522 power-domains = <&smc_devpd SKY1_PD_PCIE_CTRL0>; 523 #interrupt-cells = <1>; 524 interrupt-map-mask = <0 0 0 0x7>; 525 interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH 0>, 526 <0 0 0 2 &gic 0 0 GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH 0>, 527 <0 0 0 3 &gic 0 0 GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH 0>, 528 <0 0 0 4 &gic 0 0 GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH 0>; 529 msi-map = <0xc000 &gic_its 0xc000 0x4000>; 530 status = "disabled"; 531 }; 532 533 pcie_x4_rc: pcie@a070000 { 534 compatible = "cix,sky1-pcie-host"; 535 reg = <0x00 0x0a070000 0x00 0x10000>, 536 <0x00 0x29000000 0x00 0x3000000>, 537 <0x00 0x0a060300 0x00 0x40>, 538 <0x00 0x0a060400 0x00 0x40>, 539 <0x00 0x50000000 0x00 0x00100000>; 540 reg-names = "reg", "cfg", "rcsu_strap", "rcsu_status", "msg"; 541 ranges = <0x01000000 0x00 0x50100000 0x00 0x50100000 0x00 0x00100000>, 542 <0x02000000 0x00 0x50200000 0x00 0x50200000 0x00 0x0fe00000>, 543 <0x43000000 0x14 0x00000000 0x14 0x00000000 0x04 0x00000000>; 544 #address-cells = <3>; 545 #size-cells = <2>; 546 bus-range = <0x90 0xbf>; 547 device_type = "pci"; 548 #interrupt-cells = <1>; 549 interrupt-map-mask = <0 0 0 0x7>; 550 interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH 0>, 551 <0 0 0 2 &gic 0 0 GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH 0>, 552 <0 0 0 3 &gic 0 0 GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH 0>, 553 <0 0 0 4 &gic 0 0 GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH 0>; 554 msi-map = <0x9000 &gic_its 0x9000 0x3000>; 555 status = "disabled"; 556 }; 557 558 pcie_x2_rc: pcie@a0c0000 { 559 compatible = "cix,sky1-pcie-host"; 560 reg = <0x00 0x0a0c0000 0x00 0x10000>, 561 <0x00 0x26000000 0x00 0x3000000>, 562 <0x00 0x0a0600340 0x00 0x20>, 563 <0x00 0x0a0600440 0x00 0x20>, 564 <0x00 0x40000000 0x00 0x00100000>; 565 reg-names = "reg", "cfg", "rcsu_strap", "rcsu_status", "msg"; 566 ranges = <0x01000000 0x0 0x40100000 0x0 0x40100000 0x0 0x00100000>, 567 <0x02000000 0x0 0x40200000 0x0 0x40200000 0x0 0x0fe00000>, 568 <0x43000000 0x10 0x00000000 0x10 0x00000000 0x04 0x00000000>; 569 #address-cells = <3>; 570 #size-cells = <2>; 571 bus-range = <0x60 0x8f>; 572 device_type = "pci"; 573 #interrupt-cells = <1>; 574 interrupt-map-mask = <0 0 0 0x7>; 575 interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH 0>, 576 <0 0 0 2 &gic 0 0 GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH 0>, 577 <0 0 0 3 &gic 0 0 GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH 0>, 578 <0 0 0 4 &gic 0 0 GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH 0>; 579 msi-map = <0x6000 &gic_its 0x6000 0x3000>; 580 status = "disabled"; 581 }; 582 583 pcie_x1_0_rc: pcie@a0d0000 { 584 compatible = "cix,sky1-pcie-host"; 585 reg = <0x00 0x0a0d0000 0x00 0x10000>, 586 <0x00 0x20000000 0x00 0x3000000>, 587 <0x00 0x0a060360 0x00 0x20>, 588 <0x00 0x0a060460 0x00 0x20>, 589 <0x00 0x30000000 0x00 0x00100000>; 590 reg-names = "reg", "cfg", "rcsu_strap", "rcsu_status", "msg"; 591 ranges = <0x01000000 0x0 0x30100000 0x0 0x30100000 0x0 0x00100000>, 592 <0x02000000 0x0 0x30200000 0x0 0x30200000 0x0 0x07e00000>, 593 <0x43000000 0x08 0x00000000 0x08 0x00000000 0x04 0x00000000>; 594 #address-cells = <3>; 595 #size-cells = <2>; 596 bus-range = <0x00 0x2f>; 597 device_type = "pci"; 598 #interrupt-cells = <1>; 599 interrupt-map-mask = <0 0 0 0x7>; 600 interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH 0>, 601 <0 0 0 2 &gic 0 0 GIC_SPI 437 IRQ_TYPE_LEVEL_HIGH 0>, 602 <0 0 0 3 &gic 0 0 GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH 0>, 603 <0 0 0 4 &gic 0 0 GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH 0>; 604 msi-map = <0x0000 &gic_its 0x0000 0x3000>; 605 status = "disabled"; 606 }; 607 608 pcie_x1_1_rc: pcie@a0e0000 { 609 compatible = "cix,sky1-pcie-host"; 610 reg = <0x00 0x0a0e0000 0x00 0x10000>, 611 <0x00 0x23000000 0x00 0x3000000>, 612 <0x00 0x0a060380 0x00 0x20>, 613 <0x00 0x0a060480 0x00 0x20>, 614 <0x00 0x38000000 0x00 0x00100000>; 615 reg-names = "reg", "cfg", "rcsu_strap", "rcsu_status", "msg"; 616 ranges = <0x01000000 0x0 0x38100000 0x0 0x38100000 0x0 0x00100000>, 617 <0x02000000 0x0 0x38200000 0x0 0x38200000 0x0 0x07e00000>, 618 <0x43000000 0x0c 0x00000000 0x0c 0x00000000 0x04 0x00000000>; 619 #address-cells = <3>; 620 #size-cells = <2>; 621 bus-range = <0x30 0x5f>; 622 device_type = "pci"; 623 624 #interrupt-cells = <1>; 625 interrupt-map-mask = <0 0 0 0x7>; 626 interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH 0>, 627 <0 0 0 2 &gic 0 0 GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH 0>, 628 <0 0 0 3 &gic 0 0 GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH 0>, 629 <0 0 0 4 &gic 0 0 GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH 0>; 630 msi-map = <0x3000 &gic_its 0x3000 0x3000>; 631 status = "disabled"; 632 }; 633 634 gic: interrupt-controller@e010000 { 635 compatible = "arm,gic-v3"; 636 reg = <0x0 0x0e010000 0 0x10000>, /* GICD */ 637 <0x0 0x0e090000 0 0x300000>; /* GICR * 12 */ 638 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW 0>; 639 #interrupt-cells = <4>; 640 interrupt-controller; 641 #address-cells = <2>; 642 #size-cells = <2>; 643 ranges; 644 645 gic_its: msi-controller@e050000 { 646 compatible = "arm,gic-v3-its"; 647 reg = <0x0 0x0e050000 0x0 0x30000>; 648 msi-controller; 649 #msi-cells = <1>; 650 }; 651 652 ppi-partitions { 653 ppi_partition0: interrupt-partition-0 { 654 affinity = <&cpu0 &cpu1 &cpu2 &cpu3>; 655 }; 656 657 ppi_partition1: interrupt-partition-1 { 658 affinity = <&cpu4 &cpu5 &cpu6 &cpu7 &cpu8 &cpu9 &cpu10 &cpu11>; 659 }; 660 }; 661 }; 662 663 s5_syscon: syscon@16000000 { 664 compatible = "cix,sky1-s5-system-control", "syscon"; 665 reg = <0x0 0x16000000 0x0 0x1000>; 666 #reset-cells = <1>; 667 }; 668 669 s5_gpio0: gpio-controller@16004000 { 670 compatible = "cdns,gpio-r1p02"; 671 reg = <0x0 0x16004000 0x0 0x1000>; 672 clocks = <&s5_gpio_apb_clk>; 673 674 interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH 0>; 675 676 gpio-controller; 677 #gpio-cells = <2>; 678 ngpios = <32>; 679 680 interrupt-controller; 681 #interrupt-cells = <2>; 682 status = "disabled"; 683 }; 684 685 s5_gpio1: gpio-controller@16005000 { 686 compatible = "cdns,gpio-r1p02"; 687 reg = <0x0 0x16005000 0x0 0x1000>; 688 clocks = <&s5_gpio_apb_clk>; 689 690 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH 0>; 691 692 gpio-controller; 693 #gpio-cells = <2>; 694 ngpios = <10>; 695 696 interrupt-controller; 697 #interrupt-cells = <2>; 698 status = "disabled"; 699 }; 700 701 s5_gpio2: gpio-controller@16006000 { 702 compatible = "cdns,gpio-r1p02"; 703 reg = <0x0 0x16006000 0x0 0x1000>; 704 clocks = <&s5_gpio_apb_clk>; 705 706 interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH 0>; 707 708 gpio-controller; 709 #gpio-cells = <2>; 710 ngpios = <10>; 711 712 interrupt-controller; 713 #interrupt-cells = <2>; 714 status = "disabled"; 715 }; 716 717 iomuxc_s5: pinctrl@16007000 { 718 compatible = "cix,sky1-pinctrl-s5"; 719 reg = <0x0 0x16007000 0x0 0x1000>; 720 }; 721 722 ap_tfa_scmi_mem: shmem@84380000 { 723 compatible = "arm,scmi-shmem"; 724 reg = <0x0 0x84380000 0x0 0x80>; 725 reg-io-width = <4>; 726 }; 727 }; 728 729 timer { 730 compatible = "arm,armv8-timer"; 731 interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt"; 732 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>, 733 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>, 734 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>, 735 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>, 736 <GIC_PPI 12 IRQ_TYPE_LEVEL_LOW 0>; 737 }; 738}; 739