1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Renesas RZ/G2L Pin Control and GPIO driver core
4 *
5 * Copyright (C) 2021 Renesas Electronics Corporation.
6 */
7
8 #include <linux/bitfield.h>
9 #include <linux/bitops.h>
10 #include <linux/clk.h>
11 #include <linux/gpio/driver.h>
12 #include <linux/interrupt.h>
13 #include <linux/io.h>
14 #include <linux/module.h>
15 #include <linux/mutex.h>
16 #include <linux/of.h>
17 #include <linux/of_irq.h>
18 #include <linux/platform_device.h>
19 #include <linux/property.h>
20 #include <linux/seq_file.h>
21 #include <linux/spinlock.h>
22
23 #include <linux/pinctrl/consumer.h>
24 #include <linux/pinctrl/pinconf-generic.h>
25 #include <linux/pinctrl/pinconf.h>
26 #include <linux/pinctrl/pinctrl.h>
27 #include <linux/pinctrl/pinmux.h>
28
29 #include <dt-bindings/pinctrl/renesas,r9a09g047-pinctrl.h>
30 #include <dt-bindings/pinctrl/renesas,r9a09g057-pinctrl.h>
31 #include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
32
33 #include "../core.h"
34 #include "../pinconf.h"
35 #include "../pinmux.h"
36
37 #define DRV_NAME "pinctrl-rzg2l"
38
39 /*
40 * Use 16 lower bits [15:0] for pin identifier
41 * Use 16 higher bits [31:16] for pin mux function
42 */
43 #define MUX_PIN_ID_MASK GENMASK(15, 0)
44 #define MUX_FUNC_MASK GENMASK(31, 16)
45
46 /* PIN capabilities */
47 #define PIN_CFG_IOLH_A BIT(0)
48 #define PIN_CFG_IOLH_B BIT(1)
49 #define PIN_CFG_SR BIT(2)
50 #define PIN_CFG_IEN BIT(3)
51 #define PIN_CFG_PUPD BIT(4)
52 #define PIN_CFG_IO_VMC_SD0 BIT(5)
53 #define PIN_CFG_IO_VMC_SD1 BIT(6)
54 #define PIN_CFG_IO_VMC_QSPI BIT(7)
55 #define PIN_CFG_IO_VMC_ETH0 BIT(8)
56 #define PIN_CFG_IO_VMC_ETH1 BIT(9)
57 #define PIN_CFG_NF BIT(10) /* Digital noise filter */
58 #define PIN_CFG_IOLH_C BIT(11)
59 #define PIN_CFG_SOFT_PS BIT(12)
60 #define PIN_CFG_OEN BIT(13)
61 #define PIN_CFG_NOGPIO_INT BIT(14)
62 #define PIN_CFG_NOD BIT(15) /* N-ch Open Drain */
63 #define PIN_CFG_SMT BIT(16) /* Schmitt-trigger input control */
64 #define PIN_CFG_ELC BIT(17)
65 #define PIN_CFG_IOLH_RZV2H BIT(18)
66
67 #define RZG2L_SINGLE_PIN BIT_ULL(63) /* Dedicated pin */
68 #define RZG2L_VARIABLE_CFG BIT_ULL(62) /* Variable cfg for port pins */
69
70 #define RZG2L_MPXED_COMMON_PIN_FUNCS(group) \
71 (PIN_CFG_IOLH_##group | \
72 PIN_CFG_PUPD | \
73 PIN_CFG_NF)
74
75 #define RZG2L_MPXED_PIN_FUNCS (RZG2L_MPXED_COMMON_PIN_FUNCS(A) | \
76 PIN_CFG_SR)
77
78 #define RZG3S_MPXED_PIN_FUNCS(group) (RZG2L_MPXED_COMMON_PIN_FUNCS(group) | \
79 PIN_CFG_SOFT_PS)
80
81 #define RZV2H_MPXED_PIN_FUNCS (RZG2L_MPXED_COMMON_PIN_FUNCS(RZV2H) | \
82 PIN_CFG_NOD | \
83 PIN_CFG_SR | \
84 PIN_CFG_SMT)
85
86 #define RZG2L_MPXED_ETH_PIN_FUNCS(x) ((x) | PIN_CFG_NF)
87
88 #define PIN_CFG_PIN_MAP_MASK GENMASK_ULL(61, 54)
89 #define PIN_CFG_PIN_REG_MASK GENMASK_ULL(53, 46)
90 #define PIN_CFG_MASK GENMASK_ULL(31, 0)
91
92 /*
93 * m indicates the bitmap of supported pins, a is the register index
94 * and f is pin configuration capabilities supported.
95 */
96 #define RZG2L_GPIO_PORT_SPARSE_PACK(m, a, f) (FIELD_PREP_CONST(PIN_CFG_PIN_MAP_MASK, (m)) | \
97 FIELD_PREP_CONST(PIN_CFG_PIN_REG_MASK, (a)) | \
98 FIELD_PREP_CONST(PIN_CFG_MASK, (f)))
99 #define RZG2L_GPIO_PORT_SPARSE_PACK_VARIABLE(m, a) \
100 (RZG2L_VARIABLE_CFG | \
101 RZG2L_GPIO_PORT_SPARSE_PACK(m, a, 0))
102
103 /*
104 * n indicates number of pins in the port, a is the register index
105 * and f is pin configuration capabilities supported.
106 */
107 #define RZG2L_GPIO_PORT_PACK(n, a, f) RZG2L_GPIO_PORT_SPARSE_PACK((1ULL << (n)) - 1, (a), (f))
108 #define RZG2L_GPIO_PORT_PACK_VARIABLE(n, a) (RZG2L_VARIABLE_CFG | \
109 RZG2L_GPIO_PORT_PACK(n, a, 0))
110
111 #define RZG2L_SINGLE_PIN_INDEX_MASK GENMASK_ULL(62, 56)
112 #define RZG2L_SINGLE_PIN_BITS_MASK GENMASK_ULL(55, 53)
113 /*
114 * p is the register index while referencing to SR/IEN/IOLH/FILxx
115 * registers, b is the register bits (b * 8) and f is the pin
116 * configuration capabilities supported.
117 */
118 #define RZG2L_SINGLE_PIN_PACK(p, b, f) (RZG2L_SINGLE_PIN | \
119 FIELD_PREP_CONST(RZG2L_SINGLE_PIN_INDEX_MASK, (p)) | \
120 FIELD_PREP_CONST(RZG2L_SINGLE_PIN_BITS_MASK, (b)) | \
121 FIELD_PREP_CONST(PIN_CFG_MASK, (f)))
122
123 #define RZG2L_PIN_CFG_TO_PORT_OFFSET(cfg) ((cfg) & RZG2L_SINGLE_PIN ? \
124 FIELD_GET(RZG2L_SINGLE_PIN_INDEX_MASK, (cfg)) : \
125 FIELD_GET(PIN_CFG_PIN_REG_MASK, (cfg)))
126
127 #define VARIABLE_PIN_CFG_PIN_MASK GENMASK_ULL(54, 52)
128 #define VARIABLE_PIN_CFG_PORT_MASK GENMASK_ULL(51, 47)
129 #define RZG2L_VARIABLE_PIN_CFG_PACK(port, pin, cfg) \
130 (FIELD_PREP_CONST(VARIABLE_PIN_CFG_PIN_MASK, (pin)) | \
131 FIELD_PREP_CONST(VARIABLE_PIN_CFG_PORT_MASK, (port)) | \
132 FIELD_PREP_CONST(PIN_CFG_MASK, (cfg)))
133
134 #define P(off) (0x0000 + (off))
135 #define PM(off) (0x0100 + (off) * 2)
136 #define PMC(off) (0x0200 + (off))
137 #define PFC(off) (0x0400 + (off) * 4)
138 #define PIN(off) (0x0800 + (off))
139 #define IOLH(off) (0x1000 + (off) * 8)
140 #define SR(off) (0x1400 + (off) * 8)
141 #define IEN(off) (0x1800 + (off) * 8)
142 #define PUPD(off) (0x1C00 + (off) * 8)
143 #define ISEL(off) (0x2C00 + (off) * 8)
144 #define NOD(off) (0x3000 + (off) * 8)
145 #define SMT(off) (0x3400 + (off) * 8)
146 #define SD_CH(off, ch) ((off) + (ch) * 4)
147 #define ETH_POC(off, ch) ((off) + (ch) * 4)
148 #define QSPI (0x3008)
149 #define ETH_MODE (0x3018)
150 #define PFC_OEN (0x3C40) /* known on RZ/V2H(P) only */
151
152 #define PVDD_2500 2 /* I/O domain voltage 2.5V */
153 #define PVDD_1800 1 /* I/O domain voltage <= 1.8V */
154 #define PVDD_3300 0 /* I/O domain voltage >= 3.3V */
155
156 #define PWPR_B0WI BIT(7) /* Bit Write Disable */
157 #define PWPR_PFCWE BIT(6) /* PFC Register Write Enable */
158 #define PWPR_REGWE_A BIT(6) /* PFC and PMC Register Write Enable on RZ/V2H(P) */
159 #define PWPR_REGWE_B BIT(5) /* OEN Register Write Enable, known only in RZ/V2H(P) */
160
161 #define PM_MASK 0x03
162 #define PFC_MASK 0x0f
163 #define IEN_MASK 0x01
164 #define IOLH_MASK 0x03
165 #define SR_MASK 0x01
166 #define PUPD_MASK 0x03
167 #define NOD_MASK 0x01
168 #define SMT_MASK 0x01
169
170 #define PM_INPUT 0x1
171 #define PM_OUTPUT 0x2
172
173 #define RZG2L_PIN_ID_TO_PORT(id) ((id) / RZG2L_PINS_PER_PORT)
174 #define RZG2L_PIN_ID_TO_PIN(id) ((id) % RZG2L_PINS_PER_PORT)
175
176 #define RZG2L_TINT_MAX_INTERRUPT 32
177 #define RZG2L_PACK_HWIRQ(t, i) (((t) << 16) | (i))
178
179 /* Custom pinconf parameters */
180 #define RENESAS_RZV2H_PIN_CONFIG_OUTPUT_IMPEDANCE (PIN_CONFIG_END + 1)
181
182 static const struct pinconf_generic_params renesas_rzv2h_custom_bindings[] = {
183 { "renesas,output-impedance", RENESAS_RZV2H_PIN_CONFIG_OUTPUT_IMPEDANCE, 1 },
184 };
185
186 #ifdef CONFIG_DEBUG_FS
187 static const struct pin_config_item renesas_rzv2h_conf_items[] = {
188 PCONFDUMP(RENESAS_RZV2H_PIN_CONFIG_OUTPUT_IMPEDANCE, "output-impedance", "x", true),
189 };
190 #endif
191
192 /* Read/write 8 bits register */
193 #define RZG2L_PCTRL_REG_ACCESS8(_read, _addr, _val) \
194 do { \
195 if (_read) \
196 _val = readb(_addr); \
197 else \
198 writeb(_val, _addr); \
199 } while (0)
200
201 /* Read/write 16 bits register */
202 #define RZG2L_PCTRL_REG_ACCESS16(_read, _addr, _val) \
203 do { \
204 if (_read) \
205 _val = readw(_addr); \
206 else \
207 writew(_val, _addr); \
208 } while (0)
209
210 /* Read/write 32 bits register */
211 #define RZG2L_PCTRL_REG_ACCESS32(_read, _addr, _val) \
212 do { \
213 if (_read) \
214 _val = readl(_addr); \
215 else \
216 writel(_val, _addr); \
217 } while (0)
218
219 /**
220 * struct rzg2l_register_offsets - specific register offsets
221 * @pwpr: PWPR register offset
222 * @sd_ch: SD_CH register offset
223 * @eth_poc: ETH_POC register offset
224 */
225 struct rzg2l_register_offsets {
226 u16 pwpr;
227 u16 sd_ch;
228 u16 eth_poc;
229 };
230
231 /**
232 * enum rzg2l_iolh_index - starting indices in IOLH specific arrays
233 * @RZG2L_IOLH_IDX_1V8: starting index for 1V8 power source
234 * @RZG2L_IOLH_IDX_2V5: starting index for 2V5 power source
235 * @RZG2L_IOLH_IDX_3V3: starting index for 3V3 power source
236 * @RZG2L_IOLH_IDX_MAX: maximum index
237 */
238 enum rzg2l_iolh_index {
239 RZG2L_IOLH_IDX_1V8 = 0,
240 RZG2L_IOLH_IDX_2V5 = 4,
241 RZG2L_IOLH_IDX_3V3 = 8,
242 RZG2L_IOLH_IDX_MAX = 12,
243 };
244
245 /* Maximum number of driver strength entries per power source. */
246 #define RZG2L_IOLH_MAX_DS_ENTRIES (4)
247
248 /**
249 * struct rzg2l_hwcfg - hardware configuration data structure
250 * @regs: hardware specific register offsets
251 * @iolh_groupa_ua: IOLH group A uA specific values
252 * @iolh_groupb_ua: IOLH group B uA specific values
253 * @iolh_groupc_ua: IOLH group C uA specific values
254 * @iolh_groupb_oi: IOLH group B output impedance specific values
255 * @tint_start_index: the start index for the TINT interrupts
256 * @drive_strength_ua: drive strength in uA is supported (otherwise mA is supported)
257 * @func_base: base number for port function (see register PFC)
258 * @oen_max_pin: the maximum pin number supporting output enable
259 * @oen_max_port: the maximum port number supporting output enable
260 */
261 struct rzg2l_hwcfg {
262 const struct rzg2l_register_offsets regs;
263 u16 iolh_groupa_ua[RZG2L_IOLH_IDX_MAX];
264 u16 iolh_groupb_ua[RZG2L_IOLH_IDX_MAX];
265 u16 iolh_groupc_ua[RZG2L_IOLH_IDX_MAX];
266 u16 iolh_groupb_oi[4];
267 u16 tint_start_index;
268 bool drive_strength_ua;
269 u8 func_base;
270 u8 oen_max_pin;
271 u8 oen_max_port;
272 };
273
274 struct rzg2l_dedicated_configs {
275 const char *name;
276 u64 config;
277 };
278
279 struct rzg2l_pinctrl;
280
281 struct rzg2l_pinctrl_data {
282 const char * const *port_pins;
283 const u64 *port_pin_configs;
284 unsigned int n_ports;
285 const struct rzg2l_dedicated_configs *dedicated_pins;
286 unsigned int n_port_pins;
287 unsigned int n_dedicated_pins;
288 const struct rzg2l_hwcfg *hwcfg;
289 const u64 *variable_pin_cfg;
290 unsigned int n_variable_pin_cfg;
291 unsigned int num_custom_params;
292 const struct pinconf_generic_params *custom_params;
293 #ifdef CONFIG_DEBUG_FS
294 const struct pin_config_item *custom_conf_items;
295 #endif
296 void (*pwpr_pfc_lock_unlock)(struct rzg2l_pinctrl *pctrl, bool lock);
297 void (*pmc_writeb)(struct rzg2l_pinctrl *pctrl, u8 val, u16 offset);
298 u32 (*oen_read)(struct rzg2l_pinctrl *pctrl, unsigned int _pin);
299 int (*oen_write)(struct rzg2l_pinctrl *pctrl, unsigned int _pin, u8 oen);
300 int (*hw_to_bias_param)(unsigned int val);
301 int (*bias_param_to_hw)(enum pin_config_param param);
302 };
303
304 /**
305 * struct rzg2l_pinctrl_pin_settings - pin data
306 * @power_source: power source
307 * @drive_strength_ua: drive strength (in micro amps)
308 */
309 struct rzg2l_pinctrl_pin_settings {
310 u16 power_source;
311 u16 drive_strength_ua;
312 };
313
314 /**
315 * struct rzg2l_pinctrl_reg_cache - register cache structure (to be used in suspend/resume)
316 * @p: P registers cache
317 * @pm: PM registers cache
318 * @pmc: PMC registers cache
319 * @pfc: PFC registers cache
320 * @iolh: IOLH registers cache
321 * @pupd: PUPD registers cache
322 * @ien: IEN registers cache
323 * @sd_ch: SD_CH registers cache
324 * @eth_poc: ET_POC registers cache
325 * @eth_mode: ETH_MODE register cache
326 * @qspi: QSPI registers cache
327 */
328 struct rzg2l_pinctrl_reg_cache {
329 u8 *p;
330 u16 *pm;
331 u8 *pmc;
332 u32 *pfc;
333 u32 *iolh[2];
334 u32 *ien[2];
335 u32 *pupd[2];
336 u8 sd_ch[2];
337 u8 eth_poc[2];
338 u8 eth_mode;
339 u8 qspi;
340 };
341
342 struct rzg2l_pinctrl {
343 struct pinctrl_dev *pctl;
344 struct pinctrl_desc desc;
345 struct pinctrl_pin_desc *pins;
346
347 const struct rzg2l_pinctrl_data *data;
348 void __iomem *base;
349 struct device *dev;
350
351 struct clk *clk;
352
353 struct gpio_chip gpio_chip;
354 struct pinctrl_gpio_range gpio_range;
355 DECLARE_BITMAP(tint_slot, RZG2L_TINT_MAX_INTERRUPT);
356 spinlock_t bitmap_lock; /* protect tint_slot bitmap */
357 unsigned int hwirq[RZG2L_TINT_MAX_INTERRUPT];
358
359 spinlock_t lock; /* lock read/write registers */
360 struct mutex mutex; /* serialize adding groups and functions */
361
362 struct rzg2l_pinctrl_pin_settings *settings;
363 struct rzg2l_pinctrl_reg_cache *cache;
364 struct rzg2l_pinctrl_reg_cache *dedicated_cache;
365 atomic_t wakeup_path;
366 };
367
368 static const u16 available_ps[] = { 1800, 2500, 3300 };
369
rzg2l_pinctrl_get_variable_pin_cfg(struct rzg2l_pinctrl * pctrl,u64 pincfg,unsigned int port,u8 pin)370 static u64 rzg2l_pinctrl_get_variable_pin_cfg(struct rzg2l_pinctrl *pctrl,
371 u64 pincfg,
372 unsigned int port,
373 u8 pin)
374 {
375 unsigned int i;
376
377 for (i = 0; i < pctrl->data->n_variable_pin_cfg; i++) {
378 u64 cfg = pctrl->data->variable_pin_cfg[i];
379
380 if (FIELD_GET(VARIABLE_PIN_CFG_PORT_MASK, cfg) == port &&
381 FIELD_GET(VARIABLE_PIN_CFG_PIN_MASK, cfg) == pin)
382 return (pincfg & ~RZG2L_VARIABLE_CFG) | FIELD_GET(PIN_CFG_MASK, cfg);
383 }
384
385 return 0;
386 }
387
388 static const u64 r9a09g047_variable_pin_cfg[] = {
389 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PA, 0, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),
390 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PA, 1, RZV2H_MPXED_PIN_FUNCS),
391 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PA, 2, RZV2H_MPXED_PIN_FUNCS),
392 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PA, 3, RZV2H_MPXED_PIN_FUNCS),
393 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PA, 4, RZV2H_MPXED_PIN_FUNCS),
394 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PA, 5, RZV2H_MPXED_PIN_FUNCS),
395 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PA, 6, RZV2H_MPXED_PIN_FUNCS),
396 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PA, 7, RZV2H_MPXED_PIN_FUNCS),
397 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PD, 0, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),
398 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PD, 1, RZV2H_MPXED_PIN_FUNCS),
399 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PD, 2, RZV2H_MPXED_PIN_FUNCS),
400 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PD, 3, RZV2H_MPXED_PIN_FUNCS),
401 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PD, 4, RZV2H_MPXED_PIN_FUNCS),
402 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PD, 5, RZV2H_MPXED_PIN_FUNCS),
403 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PD, 6, RZV2H_MPXED_PIN_FUNCS),
404 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PD, 7, RZV2H_MPXED_PIN_FUNCS),
405 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PG, 0, RZV2H_MPXED_PIN_FUNCS),
406 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PG, 1, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),
407 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PG, 2, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),
408 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PG, 3, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),
409 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PG, 4, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),
410 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PG, 5, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),
411 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PG, 6, RZV2H_MPXED_PIN_FUNCS),
412 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PG, 7, RZV2H_MPXED_PIN_FUNCS),
413 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PH, 0, RZV2H_MPXED_PIN_FUNCS),
414 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PH, 1, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),
415 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PH, 2, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),
416 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PH, 3, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),
417 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PH, 4, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),
418 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PH, 5, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),
419 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PJ, 0, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),
420 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PJ, 1, RZV2H_MPXED_PIN_FUNCS),
421 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PJ, 2, RZV2H_MPXED_PIN_FUNCS),
422 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PJ, 3, RZV2H_MPXED_PIN_FUNCS),
423 RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PJ, 4, RZV2H_MPXED_PIN_FUNCS),
424 };
425
426 static const u64 r9a09g057_variable_pin_cfg[] = {
427 RZG2L_VARIABLE_PIN_CFG_PACK(RZV2H_PB, 0, RZV2H_MPXED_PIN_FUNCS),
428 RZG2L_VARIABLE_PIN_CFG_PACK(RZV2H_PB, 1, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),
429 RZG2L_VARIABLE_PIN_CFG_PACK(RZV2H_PB, 2, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),
430 RZG2L_VARIABLE_PIN_CFG_PACK(RZV2H_PB, 3, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),
431 RZG2L_VARIABLE_PIN_CFG_PACK(RZV2H_PB, 4, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),
432 RZG2L_VARIABLE_PIN_CFG_PACK(RZV2H_PB, 5, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),
433 };
434
435 #ifdef CONFIG_RISCV
436 static const u64 r9a07g043f_variable_pin_cfg[] = {
437 RZG2L_VARIABLE_PIN_CFG_PACK(20, 0, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
438 PIN_CFG_NF |
439 PIN_CFG_IEN | PIN_CFG_NOGPIO_INT),
440 RZG2L_VARIABLE_PIN_CFG_PACK(20, 1, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
441 PIN_CFG_NF |
442 PIN_CFG_IEN | PIN_CFG_NOGPIO_INT),
443 RZG2L_VARIABLE_PIN_CFG_PACK(20, 2, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
444 PIN_CFG_NF |
445 PIN_CFG_IEN | PIN_CFG_NOGPIO_INT),
446 RZG2L_VARIABLE_PIN_CFG_PACK(20, 3, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
447 PIN_CFG_IEN | PIN_CFG_NOGPIO_INT),
448 RZG2L_VARIABLE_PIN_CFG_PACK(20, 4, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
449 PIN_CFG_IEN | PIN_CFG_NOGPIO_INT),
450 RZG2L_VARIABLE_PIN_CFG_PACK(20, 5, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
451 PIN_CFG_IEN | PIN_CFG_NOGPIO_INT),
452 RZG2L_VARIABLE_PIN_CFG_PACK(20, 6, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
453 PIN_CFG_IEN | PIN_CFG_NOGPIO_INT),
454 RZG2L_VARIABLE_PIN_CFG_PACK(20, 7, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
455 PIN_CFG_IEN | PIN_CFG_NOGPIO_INT),
456 RZG2L_VARIABLE_PIN_CFG_PACK(23, 1, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
457 PIN_CFG_NOGPIO_INT),
458 RZG2L_VARIABLE_PIN_CFG_PACK(23, 2, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
459 PIN_CFG_NOGPIO_INT),
460 RZG2L_VARIABLE_PIN_CFG_PACK(23, 3, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
461 PIN_CFG_NOGPIO_INT),
462 RZG2L_VARIABLE_PIN_CFG_PACK(23, 4, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
463 PIN_CFG_NOGPIO_INT),
464 RZG2L_VARIABLE_PIN_CFG_PACK(23, 5, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_NOGPIO_INT),
465 RZG2L_VARIABLE_PIN_CFG_PACK(24, 0, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_NOGPIO_INT),
466 RZG2L_VARIABLE_PIN_CFG_PACK(24, 1, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
467 PIN_CFG_NOGPIO_INT),
468 RZG2L_VARIABLE_PIN_CFG_PACK(24, 2, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
469 PIN_CFG_NOGPIO_INT),
470 RZG2L_VARIABLE_PIN_CFG_PACK(24, 3, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
471 PIN_CFG_NOGPIO_INT),
472 RZG2L_VARIABLE_PIN_CFG_PACK(24, 4, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
473 PIN_CFG_NOGPIO_INT),
474 RZG2L_VARIABLE_PIN_CFG_PACK(24, 5, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
475 PIN_CFG_NF |
476 PIN_CFG_NOGPIO_INT),
477 };
478 #endif
479
rzg2l_pmc_writeb(struct rzg2l_pinctrl * pctrl,u8 val,u16 offset)480 static void rzg2l_pmc_writeb(struct rzg2l_pinctrl *pctrl, u8 val, u16 offset)
481 {
482 writeb(val, pctrl->base + offset);
483 }
484
rzv2h_pmc_writeb(struct rzg2l_pinctrl * pctrl,u8 val,u16 offset)485 static void rzv2h_pmc_writeb(struct rzg2l_pinctrl *pctrl, u8 val, u16 offset)
486 {
487 const struct rzg2l_register_offsets *regs = &pctrl->data->hwcfg->regs;
488 u8 pwpr;
489
490 pwpr = readb(pctrl->base + regs->pwpr);
491 writeb(pwpr | PWPR_REGWE_A, pctrl->base + regs->pwpr);
492 writeb(val, pctrl->base + offset);
493 writeb(pwpr & ~PWPR_REGWE_A, pctrl->base + regs->pwpr);
494 }
495
rzg2l_validate_pin(struct rzg2l_pinctrl * pctrl,u64 cfg,u32 port,u8 bit)496 static int rzg2l_validate_pin(struct rzg2l_pinctrl *pctrl,
497 u64 cfg, u32 port, u8 bit)
498 {
499 u8 pinmap = FIELD_GET(PIN_CFG_PIN_MAP_MASK, cfg);
500 u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(cfg);
501 u64 data;
502
503 if (!(pinmap & BIT(bit)) || port >= pctrl->data->n_port_pins)
504 return -EINVAL;
505
506 data = pctrl->data->port_pin_configs[port];
507 if (off != RZG2L_PIN_CFG_TO_PORT_OFFSET(data))
508 return -EINVAL;
509
510 return 0;
511 }
512
rzg2l_pinctrl_set_pfc_mode(struct rzg2l_pinctrl * pctrl,u8 pin,u8 off,u8 func)513 static void rzg2l_pinctrl_set_pfc_mode(struct rzg2l_pinctrl *pctrl,
514 u8 pin, u8 off, u8 func)
515 {
516 unsigned long flags;
517 u32 reg;
518
519 spin_lock_irqsave(&pctrl->lock, flags);
520
521 /* Set pin to 'Non-use (Hi-Z input protection)' */
522 reg = readw(pctrl->base + PM(off));
523 reg &= ~(PM_MASK << (pin * 2));
524 writew(reg, pctrl->base + PM(off));
525
526 pctrl->data->pwpr_pfc_lock_unlock(pctrl, false);
527
528 /* Temporarily switch to GPIO mode with PMC register */
529 reg = readb(pctrl->base + PMC(off));
530 writeb(reg & ~BIT(pin), pctrl->base + PMC(off));
531
532 /* Select Pin function mode with PFC register */
533 reg = readl(pctrl->base + PFC(off));
534 reg &= ~(PFC_MASK << (pin * 4));
535 writel(reg | (func << (pin * 4)), pctrl->base + PFC(off));
536
537 /* Switch to Peripheral pin function with PMC register */
538 reg = readb(pctrl->base + PMC(off));
539 writeb(reg | BIT(pin), pctrl->base + PMC(off));
540
541 pctrl->data->pwpr_pfc_lock_unlock(pctrl, true);
542
543 spin_unlock_irqrestore(&pctrl->lock, flags);
544 };
545
rzg2l_pinctrl_set_mux(struct pinctrl_dev * pctldev,unsigned int func_selector,unsigned int group_selector)546 static int rzg2l_pinctrl_set_mux(struct pinctrl_dev *pctldev,
547 unsigned int func_selector,
548 unsigned int group_selector)
549 {
550 struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
551 const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg;
552 struct function_desc *func;
553 unsigned int i, *psel_val;
554 struct group_desc *group;
555 const unsigned int *pins;
556 int ret;
557
558 func = pinmux_generic_get_function(pctldev, func_selector);
559 if (!func)
560 return -EINVAL;
561 group = pinctrl_generic_get_group(pctldev, group_selector);
562 if (!group)
563 return -EINVAL;
564
565 psel_val = func->data;
566 pins = group->grp.pins;
567
568 for (i = 0; i < group->grp.npins; i++) {
569 u64 *pin_data = pctrl->desc.pins[pins[i]].drv_data;
570 u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data);
571 u32 pin = RZG2L_PIN_ID_TO_PIN(pins[i]);
572
573 ret = rzg2l_validate_pin(pctrl, *pin_data, RZG2L_PIN_ID_TO_PORT(pins[i]), pin);
574 if (ret)
575 return ret;
576
577 dev_dbg(pctrl->dev, "port:%u pin: %u off:%x PSEL:%u\n",
578 RZG2L_PIN_ID_TO_PORT(pins[i]), pin, off, psel_val[i] - hwcfg->func_base);
579
580 rzg2l_pinctrl_set_pfc_mode(pctrl, pin, off, psel_val[i] - hwcfg->func_base);
581 }
582
583 return 0;
584 };
585
rzg2l_map_add_config(struct pinctrl_map * map,const char * group_or_pin,enum pinctrl_map_type type,unsigned long * configs,unsigned int num_configs)586 static int rzg2l_map_add_config(struct pinctrl_map *map,
587 const char *group_or_pin,
588 enum pinctrl_map_type type,
589 unsigned long *configs,
590 unsigned int num_configs)
591 {
592 unsigned long *cfgs;
593
594 cfgs = kmemdup_array(configs, num_configs, sizeof(*cfgs), GFP_KERNEL);
595 if (!cfgs)
596 return -ENOMEM;
597
598 map->type = type;
599 map->data.configs.group_or_pin = group_or_pin;
600 map->data.configs.configs = cfgs;
601 map->data.configs.num_configs = num_configs;
602
603 return 0;
604 }
605
rzg2l_dt_subnode_to_map(struct pinctrl_dev * pctldev,struct device_node * np,struct device_node * parent,struct pinctrl_map ** map,unsigned int * num_maps,unsigned int * index)606 static int rzg2l_dt_subnode_to_map(struct pinctrl_dev *pctldev,
607 struct device_node *np,
608 struct device_node *parent,
609 struct pinctrl_map **map,
610 unsigned int *num_maps,
611 unsigned int *index)
612 {
613 struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
614 struct pinctrl_map *maps = *map;
615 unsigned int nmaps = *num_maps;
616 unsigned long *configs = NULL;
617 unsigned int *pins, *psel_val;
618 unsigned int num_pinmux = 0;
619 unsigned int idx = *index;
620 unsigned int num_pins, i;
621 unsigned int num_configs;
622 struct property *pinmux;
623 struct property *prop;
624 int ret, gsel, fsel;
625 const char **pin_fn;
626 const char *name;
627 const char *pin;
628
629 pinmux = of_find_property(np, "pinmux", NULL);
630 if (pinmux)
631 num_pinmux = pinmux->length / sizeof(u32);
632
633 ret = of_property_count_strings(np, "pins");
634 if (ret == -EINVAL) {
635 num_pins = 0;
636 } else if (ret < 0) {
637 dev_err(pctrl->dev, "Invalid pins list in DT\n");
638 return ret;
639 } else {
640 num_pins = ret;
641 }
642
643 if (!num_pinmux && !num_pins)
644 return 0;
645
646 if (num_pinmux && num_pins) {
647 dev_err(pctrl->dev,
648 "DT node must contain either a pinmux or pins and not both\n");
649 return -EINVAL;
650 }
651
652 ret = pinconf_generic_parse_dt_config(np, pctldev, &configs, &num_configs);
653 if (ret < 0)
654 return ret;
655
656 if (num_pins && !num_configs) {
657 dev_err(pctrl->dev, "DT node must contain a config\n");
658 ret = -ENODEV;
659 goto done;
660 }
661
662 if (num_pinmux) {
663 nmaps += 1;
664 if (num_configs)
665 nmaps += 1;
666 }
667
668 if (num_pins)
669 nmaps += num_pins;
670
671 maps = krealloc_array(maps, nmaps, sizeof(*maps), GFP_KERNEL);
672 if (!maps) {
673 ret = -ENOMEM;
674 goto done;
675 }
676
677 *map = maps;
678 *num_maps = nmaps;
679 if (num_pins) {
680 of_property_for_each_string(np, "pins", prop, pin) {
681 ret = rzg2l_map_add_config(&maps[idx], pin,
682 PIN_MAP_TYPE_CONFIGS_PIN,
683 configs, num_configs);
684 if (ret < 0)
685 goto done;
686
687 idx++;
688 }
689 ret = 0;
690 goto done;
691 }
692
693 pins = devm_kcalloc(pctrl->dev, num_pinmux, sizeof(*pins), GFP_KERNEL);
694 psel_val = devm_kcalloc(pctrl->dev, num_pinmux, sizeof(*psel_val),
695 GFP_KERNEL);
696 pin_fn = devm_kzalloc(pctrl->dev, sizeof(*pin_fn), GFP_KERNEL);
697 if (!pins || !psel_val || !pin_fn) {
698 ret = -ENOMEM;
699 goto done;
700 }
701
702 /* Collect pin locations and mux settings from DT properties */
703 for (i = 0; i < num_pinmux; ++i) {
704 u32 value;
705
706 ret = of_property_read_u32_index(np, "pinmux", i, &value);
707 if (ret)
708 goto done;
709 pins[i] = FIELD_GET(MUX_PIN_ID_MASK, value);
710 psel_val[i] = FIELD_GET(MUX_FUNC_MASK, value);
711 }
712
713 if (parent) {
714 name = devm_kasprintf(pctrl->dev, GFP_KERNEL, "%pOFn.%pOFn",
715 parent, np);
716 if (!name) {
717 ret = -ENOMEM;
718 goto done;
719 }
720 } else {
721 name = np->name;
722 }
723
724 if (num_configs) {
725 ret = rzg2l_map_add_config(&maps[idx], name,
726 PIN_MAP_TYPE_CONFIGS_GROUP,
727 configs, num_configs);
728 if (ret < 0)
729 goto done;
730
731 idx++;
732 }
733
734 mutex_lock(&pctrl->mutex);
735
736 /* Register a single pin group listing all the pins we read from DT */
737 gsel = pinctrl_generic_add_group(pctldev, name, pins, num_pinmux, NULL);
738 if (gsel < 0) {
739 ret = gsel;
740 goto unlock;
741 }
742
743 /*
744 * Register a single group function where the 'data' is an array PSEL
745 * register values read from DT.
746 */
747 pin_fn[0] = name;
748 fsel = pinmux_generic_add_function(pctldev, name, pin_fn, 1, psel_val);
749 if (fsel < 0) {
750 ret = fsel;
751 goto remove_group;
752 }
753
754 mutex_unlock(&pctrl->mutex);
755
756 maps[idx].type = PIN_MAP_TYPE_MUX_GROUP;
757 maps[idx].data.mux.group = name;
758 maps[idx].data.mux.function = name;
759 idx++;
760
761 dev_dbg(pctrl->dev, "Parsed %pOF with %d pins\n", np, num_pinmux);
762 ret = 0;
763 goto done;
764
765 remove_group:
766 pinctrl_generic_remove_group(pctldev, gsel);
767 unlock:
768 mutex_unlock(&pctrl->mutex);
769 done:
770 *index = idx;
771 kfree(configs);
772 return ret;
773 }
774
rzg2l_dt_free_map(struct pinctrl_dev * pctldev,struct pinctrl_map * map,unsigned int num_maps)775 static void rzg2l_dt_free_map(struct pinctrl_dev *pctldev,
776 struct pinctrl_map *map,
777 unsigned int num_maps)
778 {
779 unsigned int i;
780
781 if (!map)
782 return;
783
784 for (i = 0; i < num_maps; ++i) {
785 if (map[i].type == PIN_MAP_TYPE_CONFIGS_GROUP ||
786 map[i].type == PIN_MAP_TYPE_CONFIGS_PIN)
787 kfree(map[i].data.configs.configs);
788 }
789 kfree(map);
790 }
791
rzg2l_dt_node_to_map(struct pinctrl_dev * pctldev,struct device_node * np,struct pinctrl_map ** map,unsigned int * num_maps)792 static int rzg2l_dt_node_to_map(struct pinctrl_dev *pctldev,
793 struct device_node *np,
794 struct pinctrl_map **map,
795 unsigned int *num_maps)
796 {
797 struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
798 unsigned int index;
799 int ret;
800
801 *map = NULL;
802 *num_maps = 0;
803 index = 0;
804
805 for_each_child_of_node_scoped(np, child) {
806 ret = rzg2l_dt_subnode_to_map(pctldev, child, np, map,
807 num_maps, &index);
808 if (ret < 0)
809 goto done;
810 }
811
812 if (*num_maps == 0) {
813 ret = rzg2l_dt_subnode_to_map(pctldev, np, NULL, map,
814 num_maps, &index);
815 if (ret < 0)
816 goto done;
817 }
818
819 if (*num_maps)
820 return 0;
821
822 dev_err(pctrl->dev, "no mapping found in node %pOF\n", np);
823 ret = -EINVAL;
824
825 done:
826 rzg2l_dt_free_map(pctldev, *map, *num_maps);
827
828 return ret;
829 }
830
rzg2l_read_pin_config(struct rzg2l_pinctrl * pctrl,u32 offset,u8 bit,u32 mask)831 static u32 rzg2l_read_pin_config(struct rzg2l_pinctrl *pctrl, u32 offset,
832 u8 bit, u32 mask)
833 {
834 void __iomem *addr = pctrl->base + offset;
835
836 /* handle _L/_H for 32-bit register read/write */
837 if (bit >= 4) {
838 bit -= 4;
839 addr += 4;
840 }
841
842 return (readl(addr) >> (bit * 8)) & mask;
843 }
844
rzg2l_rmw_pin_config(struct rzg2l_pinctrl * pctrl,u32 offset,u8 bit,u32 mask,u32 val)845 static void rzg2l_rmw_pin_config(struct rzg2l_pinctrl *pctrl, u32 offset,
846 u8 bit, u32 mask, u32 val)
847 {
848 void __iomem *addr = pctrl->base + offset;
849 unsigned long flags;
850 u32 reg;
851
852 /* handle _L/_H for 32-bit register read/write */
853 if (bit >= 4) {
854 bit -= 4;
855 addr += 4;
856 }
857
858 spin_lock_irqsave(&pctrl->lock, flags);
859 reg = readl(addr) & ~(mask << (bit * 8));
860 writel(reg | (val << (bit * 8)), addr);
861 spin_unlock_irqrestore(&pctrl->lock, flags);
862 }
863
rzg2l_caps_to_pwr_reg(const struct rzg2l_register_offsets * regs,u32 caps)864 static int rzg2l_caps_to_pwr_reg(const struct rzg2l_register_offsets *regs, u32 caps)
865 {
866 if (caps & PIN_CFG_IO_VMC_SD0)
867 return SD_CH(regs->sd_ch, 0);
868 if (caps & PIN_CFG_IO_VMC_SD1)
869 return SD_CH(regs->sd_ch, 1);
870 if (caps & PIN_CFG_IO_VMC_ETH0)
871 return ETH_POC(regs->eth_poc, 0);
872 if (caps & PIN_CFG_IO_VMC_ETH1)
873 return ETH_POC(regs->eth_poc, 1);
874 if (caps & PIN_CFG_IO_VMC_QSPI)
875 return QSPI;
876
877 return -EINVAL;
878 }
879
rzg2l_get_power_source(struct rzg2l_pinctrl * pctrl,u32 pin,u32 caps)880 static int rzg2l_get_power_source(struct rzg2l_pinctrl *pctrl, u32 pin, u32 caps)
881 {
882 const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg;
883 const struct rzg2l_register_offsets *regs = &hwcfg->regs;
884 int pwr_reg;
885 u8 val;
886
887 if (caps & PIN_CFG_SOFT_PS)
888 return pctrl->settings[pin].power_source;
889
890 pwr_reg = rzg2l_caps_to_pwr_reg(regs, caps);
891 if (pwr_reg < 0)
892 return pwr_reg;
893
894 val = readb(pctrl->base + pwr_reg);
895 switch (val) {
896 case PVDD_1800:
897 return 1800;
898 case PVDD_2500:
899 return 2500;
900 case PVDD_3300:
901 return 3300;
902 default:
903 /* Should not happen. */
904 return -EINVAL;
905 }
906 }
907
rzg2l_set_power_source(struct rzg2l_pinctrl * pctrl,u32 pin,u32 caps,u32 ps)908 static int rzg2l_set_power_source(struct rzg2l_pinctrl *pctrl, u32 pin, u32 caps, u32 ps)
909 {
910 const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg;
911 const struct rzg2l_register_offsets *regs = &hwcfg->regs;
912 int pwr_reg;
913 u8 val;
914
915 if (caps & PIN_CFG_SOFT_PS) {
916 pctrl->settings[pin].power_source = ps;
917 return 0;
918 }
919
920 switch (ps) {
921 case 1800:
922 val = PVDD_1800;
923 break;
924 case 2500:
925 if (!(caps & (PIN_CFG_IO_VMC_ETH0 | PIN_CFG_IO_VMC_ETH1)))
926 return -EINVAL;
927 val = PVDD_2500;
928 break;
929 case 3300:
930 val = PVDD_3300;
931 break;
932 default:
933 return -EINVAL;
934 }
935
936 pwr_reg = rzg2l_caps_to_pwr_reg(regs, caps);
937 if (pwr_reg < 0)
938 return pwr_reg;
939
940 writeb(val, pctrl->base + pwr_reg);
941 pctrl->settings[pin].power_source = ps;
942
943 return 0;
944 }
945
rzg2l_ps_is_supported(u16 ps)946 static bool rzg2l_ps_is_supported(u16 ps)
947 {
948 unsigned int i;
949
950 for (i = 0; i < ARRAY_SIZE(available_ps); i++) {
951 if (available_ps[i] == ps)
952 return true;
953 }
954
955 return false;
956 }
957
rzg2l_ps_to_iolh_idx(u16 ps)958 static enum rzg2l_iolh_index rzg2l_ps_to_iolh_idx(u16 ps)
959 {
960 unsigned int i;
961
962 for (i = 0; i < ARRAY_SIZE(available_ps); i++) {
963 if (available_ps[i] == ps)
964 break;
965 }
966
967 /*
968 * We multiply with RZG2L_IOLH_MAX_DS_ENTRIES as we have
969 * RZG2L_IOLH_MAX_DS_ENTRIES DS values per power source
970 */
971 return i * RZG2L_IOLH_MAX_DS_ENTRIES;
972 }
973
rzg2l_iolh_val_to_ua(const struct rzg2l_hwcfg * hwcfg,u32 caps,u8 val)974 static u16 rzg2l_iolh_val_to_ua(const struct rzg2l_hwcfg *hwcfg, u32 caps, u8 val)
975 {
976 if (caps & PIN_CFG_IOLH_A)
977 return hwcfg->iolh_groupa_ua[val];
978
979 if (caps & PIN_CFG_IOLH_B)
980 return hwcfg->iolh_groupb_ua[val];
981
982 if (caps & PIN_CFG_IOLH_C)
983 return hwcfg->iolh_groupc_ua[val];
984
985 /* Should not happen. */
986 return 0;
987 }
988
rzg2l_iolh_ua_to_val(const struct rzg2l_hwcfg * hwcfg,u32 caps,enum rzg2l_iolh_index ps_index,u16 ua)989 static int rzg2l_iolh_ua_to_val(const struct rzg2l_hwcfg *hwcfg, u32 caps,
990 enum rzg2l_iolh_index ps_index, u16 ua)
991 {
992 const u16 *array = NULL;
993 unsigned int i;
994
995 if (caps & PIN_CFG_IOLH_A)
996 array = &hwcfg->iolh_groupa_ua[ps_index];
997
998 if (caps & PIN_CFG_IOLH_B)
999 array = &hwcfg->iolh_groupb_ua[ps_index];
1000
1001 if (caps & PIN_CFG_IOLH_C)
1002 array = &hwcfg->iolh_groupc_ua[ps_index];
1003
1004 if (!array)
1005 return -EINVAL;
1006
1007 for (i = 0; i < RZG2L_IOLH_MAX_DS_ENTRIES; i++) {
1008 if (array[i] == ua)
1009 return i;
1010 }
1011
1012 return -EINVAL;
1013 }
1014
rzg2l_ds_is_supported(struct rzg2l_pinctrl * pctrl,u32 caps,enum rzg2l_iolh_index iolh_idx,u16 ds)1015 static bool rzg2l_ds_is_supported(struct rzg2l_pinctrl *pctrl, u32 caps,
1016 enum rzg2l_iolh_index iolh_idx,
1017 u16 ds)
1018 {
1019 const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg;
1020 const u16 *array = NULL;
1021 unsigned int i;
1022
1023 if (caps & PIN_CFG_IOLH_A)
1024 array = hwcfg->iolh_groupa_ua;
1025
1026 if (caps & PIN_CFG_IOLH_B)
1027 array = hwcfg->iolh_groupb_ua;
1028
1029 if (caps & PIN_CFG_IOLH_C)
1030 array = hwcfg->iolh_groupc_ua;
1031
1032 /* Should not happen. */
1033 if (!array)
1034 return false;
1035
1036 if (!array[iolh_idx])
1037 return false;
1038
1039 for (i = 0; i < RZG2L_IOLH_MAX_DS_ENTRIES; i++) {
1040 if (array[iolh_idx + i] == ds)
1041 return true;
1042 }
1043
1044 return false;
1045 }
1046
rzg2l_pin_to_oen_bit(struct rzg2l_pinctrl * pctrl,unsigned int _pin)1047 static int rzg2l_pin_to_oen_bit(struct rzg2l_pinctrl *pctrl, unsigned int _pin)
1048 {
1049 u64 *pin_data = pctrl->desc.pins[_pin].drv_data;
1050 u64 caps = FIELD_GET(PIN_CFG_MASK, *pin_data);
1051 u8 pin = RZG2L_PIN_ID_TO_PIN(_pin);
1052
1053 if (pin > pctrl->data->hwcfg->oen_max_pin)
1054 return -EINVAL;
1055
1056 /*
1057 * We can determine which Ethernet interface we're dealing with from
1058 * the caps.
1059 */
1060 if (caps & PIN_CFG_IO_VMC_ETH0)
1061 return 0;
1062 if (caps & PIN_CFG_IO_VMC_ETH1)
1063 return 1;
1064
1065 return -EINVAL;
1066 }
1067
rzg2l_read_oen(struct rzg2l_pinctrl * pctrl,unsigned int _pin)1068 static u32 rzg2l_read_oen(struct rzg2l_pinctrl *pctrl, unsigned int _pin)
1069 {
1070 int bit;
1071
1072 bit = rzg2l_pin_to_oen_bit(pctrl, _pin);
1073 if (bit < 0)
1074 return 0;
1075
1076 return !(readb(pctrl->base + ETH_MODE) & BIT(bit));
1077 }
1078
rzg2l_write_oen(struct rzg2l_pinctrl * pctrl,unsigned int _pin,u8 oen)1079 static int rzg2l_write_oen(struct rzg2l_pinctrl *pctrl, unsigned int _pin, u8 oen)
1080 {
1081 unsigned long flags;
1082 int bit;
1083 u8 val;
1084
1085 bit = rzg2l_pin_to_oen_bit(pctrl, _pin);
1086 if (bit < 0)
1087 return bit;
1088
1089 spin_lock_irqsave(&pctrl->lock, flags);
1090 val = readb(pctrl->base + ETH_MODE);
1091 if (oen)
1092 val &= ~BIT(bit);
1093 else
1094 val |= BIT(bit);
1095 writeb(val, pctrl->base + ETH_MODE);
1096 spin_unlock_irqrestore(&pctrl->lock, flags);
1097
1098 return 0;
1099 }
1100
rzg3s_pin_to_oen_bit(struct rzg2l_pinctrl * pctrl,unsigned int _pin)1101 static int rzg3s_pin_to_oen_bit(struct rzg2l_pinctrl *pctrl, unsigned int _pin)
1102 {
1103 u64 *pin_data = pctrl->desc.pins[_pin].drv_data;
1104 u8 port, pin, bit;
1105
1106 if (*pin_data & RZG2L_SINGLE_PIN)
1107 return -EINVAL;
1108
1109 port = RZG2L_PIN_ID_TO_PORT(_pin);
1110 pin = RZG2L_PIN_ID_TO_PIN(_pin);
1111 if (pin > pctrl->data->hwcfg->oen_max_pin)
1112 return -EINVAL;
1113
1114 bit = pin * 2;
1115 if (port == pctrl->data->hwcfg->oen_max_port)
1116 bit += 1;
1117
1118 return bit;
1119 }
1120
rzg3s_oen_read(struct rzg2l_pinctrl * pctrl,unsigned int _pin)1121 static u32 rzg3s_oen_read(struct rzg2l_pinctrl *pctrl, unsigned int _pin)
1122 {
1123 int bit;
1124
1125 bit = rzg3s_pin_to_oen_bit(pctrl, _pin);
1126 if (bit < 0)
1127 return bit;
1128
1129 return !(readb(pctrl->base + ETH_MODE) & BIT(bit));
1130 }
1131
rzg3s_oen_write(struct rzg2l_pinctrl * pctrl,unsigned int _pin,u8 oen)1132 static int rzg3s_oen_write(struct rzg2l_pinctrl *pctrl, unsigned int _pin, u8 oen)
1133 {
1134 unsigned long flags;
1135 int bit;
1136 u8 val;
1137
1138 bit = rzg3s_pin_to_oen_bit(pctrl, _pin);
1139 if (bit < 0)
1140 return bit;
1141
1142 spin_lock_irqsave(&pctrl->lock, flags);
1143 val = readb(pctrl->base + ETH_MODE);
1144 if (oen)
1145 val &= ~BIT(bit);
1146 else
1147 val |= BIT(bit);
1148 writeb(val, pctrl->base + ETH_MODE);
1149 spin_unlock_irqrestore(&pctrl->lock, flags);
1150
1151 return 0;
1152 }
1153
rzg2l_hw_to_bias_param(unsigned int bias)1154 static int rzg2l_hw_to_bias_param(unsigned int bias)
1155 {
1156 switch (bias) {
1157 case 0:
1158 return PIN_CONFIG_BIAS_DISABLE;
1159 case 1:
1160 return PIN_CONFIG_BIAS_PULL_UP;
1161 case 2:
1162 return PIN_CONFIG_BIAS_PULL_DOWN;
1163 default:
1164 break;
1165 }
1166
1167 return -EINVAL;
1168 }
1169
rzg2l_bias_param_to_hw(enum pin_config_param param)1170 static int rzg2l_bias_param_to_hw(enum pin_config_param param)
1171 {
1172 switch (param) {
1173 case PIN_CONFIG_BIAS_DISABLE:
1174 return 0;
1175 case PIN_CONFIG_BIAS_PULL_UP:
1176 return 1;
1177 case PIN_CONFIG_BIAS_PULL_DOWN:
1178 return 2;
1179 default:
1180 break;
1181 }
1182
1183 return -EINVAL;
1184 }
1185
rzv2h_hw_to_bias_param(unsigned int bias)1186 static int rzv2h_hw_to_bias_param(unsigned int bias)
1187 {
1188 switch (bias) {
1189 case 0:
1190 case 1:
1191 return PIN_CONFIG_BIAS_DISABLE;
1192 case 2:
1193 return PIN_CONFIG_BIAS_PULL_DOWN;
1194 case 3:
1195 return PIN_CONFIG_BIAS_PULL_UP;
1196 default:
1197 break;
1198 }
1199
1200 return -EINVAL;
1201 }
1202
rzv2h_bias_param_to_hw(enum pin_config_param param)1203 static int rzv2h_bias_param_to_hw(enum pin_config_param param)
1204 {
1205 switch (param) {
1206 case PIN_CONFIG_BIAS_DISABLE:
1207 return 0;
1208 case PIN_CONFIG_BIAS_PULL_DOWN:
1209 return 2;
1210 case PIN_CONFIG_BIAS_PULL_UP:
1211 return 3;
1212 default:
1213 break;
1214 }
1215
1216 return -EINVAL;
1217 }
1218
rzv2h_pin_to_oen_bit(struct rzg2l_pinctrl * pctrl,unsigned int _pin)1219 static u8 rzv2h_pin_to_oen_bit(struct rzg2l_pinctrl *pctrl, unsigned int _pin)
1220 {
1221 static const char * const pin_names[] = { "ET0_TXC_TXCLK", "ET1_TXC_TXCLK",
1222 "XSPI0_RESET0N", "XSPI0_CS0N",
1223 "XSPI0_CKN", "XSPI0_CKP" };
1224 const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[_pin];
1225 unsigned int i;
1226
1227 for (i = 0; i < ARRAY_SIZE(pin_names); i++) {
1228 if (!strcmp(pin_desc->name, pin_names[i]))
1229 return i;
1230 }
1231
1232 /* Should not happen. */
1233 return 0;
1234 }
1235
rzv2h_oen_read(struct rzg2l_pinctrl * pctrl,unsigned int _pin)1236 static u32 rzv2h_oen_read(struct rzg2l_pinctrl *pctrl, unsigned int _pin)
1237 {
1238 u8 bit;
1239
1240 bit = rzv2h_pin_to_oen_bit(pctrl, _pin);
1241
1242 return !(readb(pctrl->base + PFC_OEN) & BIT(bit));
1243 }
1244
rzv2h_oen_write(struct rzg2l_pinctrl * pctrl,unsigned int _pin,u8 oen)1245 static int rzv2h_oen_write(struct rzg2l_pinctrl *pctrl, unsigned int _pin, u8 oen)
1246 {
1247 const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg;
1248 const struct rzg2l_register_offsets *regs = &hwcfg->regs;
1249 unsigned long flags;
1250 u8 val, bit;
1251 u8 pwpr;
1252
1253 bit = rzv2h_pin_to_oen_bit(pctrl, _pin);
1254 spin_lock_irqsave(&pctrl->lock, flags);
1255 val = readb(pctrl->base + PFC_OEN);
1256 if (oen)
1257 val &= ~BIT(bit);
1258 else
1259 val |= BIT(bit);
1260
1261 pwpr = readb(pctrl->base + regs->pwpr);
1262 writeb(pwpr | PWPR_REGWE_B, pctrl->base + regs->pwpr);
1263 writeb(val, pctrl->base + PFC_OEN);
1264 writeb(pwpr & ~PWPR_REGWE_B, pctrl->base + regs->pwpr);
1265 spin_unlock_irqrestore(&pctrl->lock, flags);
1266
1267 return 0;
1268 }
1269
rzg2l_pinctrl_pinconf_get(struct pinctrl_dev * pctldev,unsigned int _pin,unsigned long * config)1270 static int rzg2l_pinctrl_pinconf_get(struct pinctrl_dev *pctldev,
1271 unsigned int _pin,
1272 unsigned long *config)
1273 {
1274 struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
1275 const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg;
1276 const struct pinctrl_pin_desc *pin = &pctrl->desc.pins[_pin];
1277 u32 param = pinconf_to_config_param(*config);
1278 u64 *pin_data = pin->drv_data;
1279 unsigned int arg = 0;
1280 u32 off;
1281 u32 cfg;
1282 int ret;
1283 u8 bit;
1284
1285 if (!pin_data)
1286 return -EINVAL;
1287
1288 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data);
1289 cfg = FIELD_GET(PIN_CFG_MASK, *pin_data);
1290 if (*pin_data & RZG2L_SINGLE_PIN) {
1291 bit = FIELD_GET(RZG2L_SINGLE_PIN_BITS_MASK, *pin_data);
1292 } else {
1293 bit = RZG2L_PIN_ID_TO_PIN(_pin);
1294
1295 if (rzg2l_validate_pin(pctrl, *pin_data, RZG2L_PIN_ID_TO_PORT(_pin), bit))
1296 return -EINVAL;
1297 }
1298
1299 switch (param) {
1300 case PIN_CONFIG_INPUT_ENABLE:
1301 if (!(cfg & PIN_CFG_IEN))
1302 return -EINVAL;
1303 arg = rzg2l_read_pin_config(pctrl, IEN(off), bit, IEN_MASK);
1304 if (!arg)
1305 return -EINVAL;
1306 break;
1307
1308 case PIN_CONFIG_OUTPUT_ENABLE:
1309 if (!(cfg & PIN_CFG_OEN))
1310 return -EINVAL;
1311 if (!pctrl->data->oen_read)
1312 return -EOPNOTSUPP;
1313 arg = pctrl->data->oen_read(pctrl, _pin);
1314 if (!arg)
1315 return -EINVAL;
1316 break;
1317
1318 case PIN_CONFIG_POWER_SOURCE:
1319 ret = rzg2l_get_power_source(pctrl, _pin, cfg);
1320 if (ret < 0)
1321 return ret;
1322 arg = ret;
1323 break;
1324
1325 case PIN_CONFIG_SLEW_RATE:
1326 if (!(cfg & PIN_CFG_SR))
1327 return -EINVAL;
1328
1329 arg = rzg2l_read_pin_config(pctrl, SR(off), bit, SR_MASK);
1330 break;
1331
1332 case PIN_CONFIG_BIAS_DISABLE:
1333 case PIN_CONFIG_BIAS_PULL_UP:
1334 case PIN_CONFIG_BIAS_PULL_DOWN:
1335 if (!(cfg & PIN_CFG_PUPD))
1336 return -EINVAL;
1337
1338 arg = rzg2l_read_pin_config(pctrl, PUPD(off), bit, PUPD_MASK);
1339 ret = pctrl->data->hw_to_bias_param(arg);
1340 if (ret < 0)
1341 return ret;
1342
1343 if (ret != param)
1344 return -EINVAL;
1345 /* for PIN_CONFIG_BIAS_PULL_UP/DOWN when enabled we just return 1 */
1346 arg = 1;
1347 break;
1348
1349 case PIN_CONFIG_DRIVE_STRENGTH: {
1350 unsigned int index;
1351
1352 if (!(cfg & PIN_CFG_IOLH_A) || hwcfg->drive_strength_ua)
1353 return -EINVAL;
1354
1355 index = rzg2l_read_pin_config(pctrl, IOLH(off), bit, IOLH_MASK);
1356 /*
1357 * Drive strenght mA is supported only by group A and only
1358 * for 3V3 port source.
1359 */
1360 arg = hwcfg->iolh_groupa_ua[index + RZG2L_IOLH_IDX_3V3] / 1000;
1361 break;
1362 }
1363
1364 case PIN_CONFIG_DRIVE_STRENGTH_UA: {
1365 enum rzg2l_iolh_index iolh_idx;
1366 u8 val;
1367
1368 if (!(cfg & (PIN_CFG_IOLH_A | PIN_CFG_IOLH_B | PIN_CFG_IOLH_C)) ||
1369 !hwcfg->drive_strength_ua)
1370 return -EINVAL;
1371
1372 ret = rzg2l_get_power_source(pctrl, _pin, cfg);
1373 if (ret < 0)
1374 return ret;
1375 iolh_idx = rzg2l_ps_to_iolh_idx(ret);
1376 val = rzg2l_read_pin_config(pctrl, IOLH(off), bit, IOLH_MASK);
1377 arg = rzg2l_iolh_val_to_ua(hwcfg, cfg, iolh_idx + val);
1378 break;
1379 }
1380
1381 case PIN_CONFIG_OUTPUT_IMPEDANCE_OHMS: {
1382 unsigned int index;
1383
1384 if (!(cfg & PIN_CFG_IOLH_B) || !hwcfg->iolh_groupb_oi[0])
1385 return -EINVAL;
1386
1387 index = rzg2l_read_pin_config(pctrl, IOLH(off), bit, IOLH_MASK);
1388 arg = hwcfg->iolh_groupb_oi[index];
1389 break;
1390 }
1391
1392 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
1393 case PIN_CONFIG_DRIVE_PUSH_PULL:
1394 if (!(cfg & PIN_CFG_NOD))
1395 return -EINVAL;
1396
1397 arg = rzg2l_read_pin_config(pctrl, NOD(off), bit, NOD_MASK);
1398 if (!arg && param != PIN_CONFIG_DRIVE_PUSH_PULL)
1399 return -EINVAL;
1400 if (arg && param != PIN_CONFIG_DRIVE_OPEN_DRAIN)
1401 return -EINVAL;
1402 break;
1403
1404 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
1405 if (!(cfg & PIN_CFG_SMT))
1406 return -EINVAL;
1407
1408 arg = rzg2l_read_pin_config(pctrl, SMT(off), bit, SMT_MASK);
1409 if (!arg)
1410 return -EINVAL;
1411 break;
1412
1413 case RENESAS_RZV2H_PIN_CONFIG_OUTPUT_IMPEDANCE:
1414 if (!(cfg & PIN_CFG_IOLH_RZV2H))
1415 return -EINVAL;
1416
1417 arg = rzg2l_read_pin_config(pctrl, IOLH(off), bit, IOLH_MASK);
1418 break;
1419
1420 default:
1421 return -ENOTSUPP;
1422 }
1423
1424 *config = pinconf_to_config_packed(param, arg);
1425
1426 return 0;
1427 };
1428
rzg2l_pinctrl_pinconf_set(struct pinctrl_dev * pctldev,unsigned int _pin,unsigned long * _configs,unsigned int num_configs)1429 static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev,
1430 unsigned int _pin,
1431 unsigned long *_configs,
1432 unsigned int num_configs)
1433 {
1434 struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
1435 const struct pinctrl_pin_desc *pin = &pctrl->desc.pins[_pin];
1436 const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg;
1437 struct rzg2l_pinctrl_pin_settings settings = pctrl->settings[_pin];
1438 u64 *pin_data = pin->drv_data;
1439 unsigned int i, arg, index;
1440 u32 off, param;
1441 u32 cfg;
1442 int ret;
1443 u8 bit;
1444
1445 if (!pin_data)
1446 return -EINVAL;
1447
1448 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data);
1449 cfg = FIELD_GET(PIN_CFG_MASK, *pin_data);
1450 if (*pin_data & RZG2L_SINGLE_PIN) {
1451 bit = FIELD_GET(RZG2L_SINGLE_PIN_BITS_MASK, *pin_data);
1452 } else {
1453 bit = RZG2L_PIN_ID_TO_PIN(_pin);
1454
1455 if (rzg2l_validate_pin(pctrl, *pin_data, RZG2L_PIN_ID_TO_PORT(_pin), bit))
1456 return -EINVAL;
1457 }
1458
1459 for (i = 0; i < num_configs; i++) {
1460 param = pinconf_to_config_param(_configs[i]);
1461 arg = pinconf_to_config_argument(_configs[i]);
1462 switch (param) {
1463 case PIN_CONFIG_INPUT_ENABLE:
1464
1465 if (!(cfg & PIN_CFG_IEN))
1466 return -EINVAL;
1467
1468 rzg2l_rmw_pin_config(pctrl, IEN(off), bit, IEN_MASK, !!arg);
1469 break;
1470
1471 case PIN_CONFIG_OUTPUT_ENABLE:
1472 if (!(cfg & PIN_CFG_OEN))
1473 return -EINVAL;
1474 if (!pctrl->data->oen_write)
1475 return -EOPNOTSUPP;
1476 ret = pctrl->data->oen_write(pctrl, _pin, !!arg);
1477 if (ret)
1478 return ret;
1479 break;
1480
1481 case PIN_CONFIG_POWER_SOURCE:
1482 settings.power_source = arg;
1483 break;
1484
1485 case PIN_CONFIG_SLEW_RATE:
1486 if (!(cfg & PIN_CFG_SR) || arg > 1)
1487 return -EINVAL;
1488
1489 rzg2l_rmw_pin_config(pctrl, SR(off), bit, SR_MASK, arg);
1490 break;
1491
1492 case PIN_CONFIG_BIAS_DISABLE:
1493 case PIN_CONFIG_BIAS_PULL_UP:
1494 case PIN_CONFIG_BIAS_PULL_DOWN:
1495 if (!(cfg & PIN_CFG_PUPD))
1496 return -EINVAL;
1497
1498 ret = pctrl->data->bias_param_to_hw(param);
1499 if (ret < 0)
1500 return ret;
1501
1502 rzg2l_rmw_pin_config(pctrl, PUPD(off), bit, PUPD_MASK, ret);
1503 break;
1504
1505 case PIN_CONFIG_DRIVE_STRENGTH:
1506 if (!(cfg & PIN_CFG_IOLH_A) || hwcfg->drive_strength_ua)
1507 return -EINVAL;
1508
1509 for (index = RZG2L_IOLH_IDX_3V3;
1510 index < RZG2L_IOLH_IDX_3V3 + RZG2L_IOLH_MAX_DS_ENTRIES; index++) {
1511 if (arg == (hwcfg->iolh_groupa_ua[index] / 1000))
1512 break;
1513 }
1514 if (index == (RZG2L_IOLH_IDX_3V3 + RZG2L_IOLH_MAX_DS_ENTRIES))
1515 return -EINVAL;
1516
1517 rzg2l_rmw_pin_config(pctrl, IOLH(off), bit, IOLH_MASK, index);
1518 break;
1519
1520 case PIN_CONFIG_DRIVE_STRENGTH_UA:
1521 if (!(cfg & (PIN_CFG_IOLH_A | PIN_CFG_IOLH_B | PIN_CFG_IOLH_C)) ||
1522 !hwcfg->drive_strength_ua)
1523 return -EINVAL;
1524
1525 settings.drive_strength_ua = arg;
1526 break;
1527
1528 case PIN_CONFIG_OUTPUT_IMPEDANCE_OHMS:
1529 if (!(cfg & PIN_CFG_IOLH_B) || !hwcfg->iolh_groupb_oi[0])
1530 return -EINVAL;
1531
1532 for (index = 0; index < ARRAY_SIZE(hwcfg->iolh_groupb_oi); index++) {
1533 if (arg == hwcfg->iolh_groupb_oi[index])
1534 break;
1535 }
1536 if (index == ARRAY_SIZE(hwcfg->iolh_groupb_oi))
1537 return -EINVAL;
1538
1539 rzg2l_rmw_pin_config(pctrl, IOLH(off), bit, IOLH_MASK, index);
1540 break;
1541
1542 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
1543 case PIN_CONFIG_DRIVE_PUSH_PULL:
1544 if (!(cfg & PIN_CFG_NOD))
1545 return -EINVAL;
1546
1547 rzg2l_rmw_pin_config(pctrl, NOD(off), bit, NOD_MASK,
1548 param == PIN_CONFIG_DRIVE_OPEN_DRAIN ? 1 : 0);
1549 break;
1550
1551 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
1552 if (!(cfg & PIN_CFG_SMT))
1553 return -EINVAL;
1554
1555 rzg2l_rmw_pin_config(pctrl, SMT(off), bit, SMT_MASK, arg);
1556 break;
1557
1558 case RENESAS_RZV2H_PIN_CONFIG_OUTPUT_IMPEDANCE:
1559 if (!(cfg & PIN_CFG_IOLH_RZV2H))
1560 return -EINVAL;
1561
1562 if (arg > 3)
1563 return -EINVAL;
1564 rzg2l_rmw_pin_config(pctrl, IOLH(off), bit, IOLH_MASK, arg);
1565 break;
1566
1567 default:
1568 return -EOPNOTSUPP;
1569 }
1570 }
1571
1572 /* Apply power source. */
1573 if (settings.power_source != pctrl->settings[_pin].power_source) {
1574 ret = rzg2l_ps_is_supported(settings.power_source);
1575 if (!ret)
1576 return -EINVAL;
1577
1578 /* Apply power source. */
1579 ret = rzg2l_set_power_source(pctrl, _pin, cfg, settings.power_source);
1580 if (ret)
1581 return ret;
1582 }
1583
1584 /* Apply drive strength. */
1585 if (settings.drive_strength_ua != pctrl->settings[_pin].drive_strength_ua) {
1586 enum rzg2l_iolh_index iolh_idx;
1587 int val;
1588
1589 iolh_idx = rzg2l_ps_to_iolh_idx(settings.power_source);
1590 ret = rzg2l_ds_is_supported(pctrl, cfg, iolh_idx,
1591 settings.drive_strength_ua);
1592 if (!ret)
1593 return -EINVAL;
1594
1595 /* Get register value for this PS/DS tuple. */
1596 val = rzg2l_iolh_ua_to_val(hwcfg, cfg, iolh_idx, settings.drive_strength_ua);
1597 if (val < 0)
1598 return val;
1599
1600 /* Apply drive strength. */
1601 rzg2l_rmw_pin_config(pctrl, IOLH(off), bit, IOLH_MASK, val);
1602 pctrl->settings[_pin].drive_strength_ua = settings.drive_strength_ua;
1603 }
1604
1605 return 0;
1606 }
1607
rzg2l_pinctrl_pinconf_group_set(struct pinctrl_dev * pctldev,unsigned int group,unsigned long * configs,unsigned int num_configs)1608 static int rzg2l_pinctrl_pinconf_group_set(struct pinctrl_dev *pctldev,
1609 unsigned int group,
1610 unsigned long *configs,
1611 unsigned int num_configs)
1612 {
1613 const unsigned int *pins;
1614 unsigned int i, npins;
1615 int ret;
1616
1617 ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins);
1618 if (ret)
1619 return ret;
1620
1621 for (i = 0; i < npins; i++) {
1622 ret = rzg2l_pinctrl_pinconf_set(pctldev, pins[i], configs,
1623 num_configs);
1624 if (ret)
1625 return ret;
1626 }
1627
1628 return 0;
1629 };
1630
rzg2l_pinctrl_pinconf_group_get(struct pinctrl_dev * pctldev,unsigned int group,unsigned long * config)1631 static int rzg2l_pinctrl_pinconf_group_get(struct pinctrl_dev *pctldev,
1632 unsigned int group,
1633 unsigned long *config)
1634 {
1635 const unsigned int *pins;
1636 unsigned int i, npins, prev_config = 0;
1637 int ret;
1638
1639 ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins);
1640 if (ret)
1641 return ret;
1642
1643 for (i = 0; i < npins; i++) {
1644 ret = rzg2l_pinctrl_pinconf_get(pctldev, pins[i], config);
1645 if (ret)
1646 return ret;
1647
1648 /* Check config matching between to pin */
1649 if (i && prev_config != *config)
1650 return -EOPNOTSUPP;
1651
1652 prev_config = *config;
1653 }
1654
1655 return 0;
1656 };
1657
1658 static const struct pinctrl_ops rzg2l_pinctrl_pctlops = {
1659 .get_groups_count = pinctrl_generic_get_group_count,
1660 .get_group_name = pinctrl_generic_get_group_name,
1661 .get_group_pins = pinctrl_generic_get_group_pins,
1662 .dt_node_to_map = rzg2l_dt_node_to_map,
1663 .dt_free_map = rzg2l_dt_free_map,
1664 };
1665
1666 static const struct pinmux_ops rzg2l_pinctrl_pmxops = {
1667 .get_functions_count = pinmux_generic_get_function_count,
1668 .get_function_name = pinmux_generic_get_function_name,
1669 .get_function_groups = pinmux_generic_get_function_groups,
1670 .set_mux = rzg2l_pinctrl_set_mux,
1671 .strict = true,
1672 };
1673
1674 static const struct pinconf_ops rzg2l_pinctrl_confops = {
1675 .is_generic = true,
1676 .pin_config_get = rzg2l_pinctrl_pinconf_get,
1677 .pin_config_set = rzg2l_pinctrl_pinconf_set,
1678 .pin_config_group_set = rzg2l_pinctrl_pinconf_group_set,
1679 .pin_config_group_get = rzg2l_pinctrl_pinconf_group_get,
1680 .pin_config_config_dbg_show = pinconf_generic_dump_config,
1681 };
1682
rzg2l_gpio_request(struct gpio_chip * chip,unsigned int offset)1683 static int rzg2l_gpio_request(struct gpio_chip *chip, unsigned int offset)
1684 {
1685 struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip);
1686 const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[offset];
1687 u64 *pin_data = pin_desc->drv_data;
1688 u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data);
1689 u32 port = RZG2L_PIN_ID_TO_PORT(offset);
1690 u8 bit = RZG2L_PIN_ID_TO_PIN(offset);
1691 unsigned long flags;
1692 u8 reg8;
1693 int ret;
1694
1695 ret = rzg2l_validate_pin(pctrl, *pin_data, port, bit);
1696 if (ret)
1697 return ret;
1698
1699 ret = pinctrl_gpio_request(chip, offset);
1700 if (ret)
1701 return ret;
1702
1703 spin_lock_irqsave(&pctrl->lock, flags);
1704
1705 /* Select GPIO mode in PMC Register */
1706 reg8 = readb(pctrl->base + PMC(off));
1707 reg8 &= ~BIT(bit);
1708 pctrl->data->pmc_writeb(pctrl, reg8, PMC(off));
1709
1710 spin_unlock_irqrestore(&pctrl->lock, flags);
1711
1712 return 0;
1713 }
1714
rzg2l_gpio_set_direction(struct rzg2l_pinctrl * pctrl,u32 offset,bool output)1715 static void rzg2l_gpio_set_direction(struct rzg2l_pinctrl *pctrl, u32 offset,
1716 bool output)
1717 {
1718 const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[offset];
1719 u64 *pin_data = pin_desc->drv_data;
1720 u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data);
1721 u8 bit = RZG2L_PIN_ID_TO_PIN(offset);
1722 unsigned long flags;
1723 u16 reg16;
1724
1725 spin_lock_irqsave(&pctrl->lock, flags);
1726
1727 reg16 = readw(pctrl->base + PM(off));
1728 reg16 &= ~(PM_MASK << (bit * 2));
1729
1730 reg16 |= (output ? PM_OUTPUT : PM_INPUT) << (bit * 2);
1731 writew(reg16, pctrl->base + PM(off));
1732
1733 spin_unlock_irqrestore(&pctrl->lock, flags);
1734 }
1735
rzg2l_gpio_get_direction(struct gpio_chip * chip,unsigned int offset)1736 static int rzg2l_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
1737 {
1738 struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip);
1739 const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[offset];
1740 u64 *pin_data = pin_desc->drv_data;
1741 u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data);
1742 u8 bit = RZG2L_PIN_ID_TO_PIN(offset);
1743
1744 if (!(readb(pctrl->base + PMC(off)) & BIT(bit))) {
1745 u16 reg16;
1746
1747 reg16 = readw(pctrl->base + PM(off));
1748 reg16 = (reg16 >> (bit * 2)) & PM_MASK;
1749 if (reg16 == PM_OUTPUT)
1750 return GPIO_LINE_DIRECTION_OUT;
1751 }
1752
1753 return GPIO_LINE_DIRECTION_IN;
1754 }
1755
rzg2l_gpio_direction_input(struct gpio_chip * chip,unsigned int offset)1756 static int rzg2l_gpio_direction_input(struct gpio_chip *chip,
1757 unsigned int offset)
1758 {
1759 struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip);
1760
1761 rzg2l_gpio_set_direction(pctrl, offset, false);
1762
1763 return 0;
1764 }
1765
rzg2l_gpio_set(struct gpio_chip * chip,unsigned int offset,int value)1766 static int rzg2l_gpio_set(struct gpio_chip *chip, unsigned int offset,
1767 int value)
1768 {
1769 struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip);
1770 const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[offset];
1771 u64 *pin_data = pin_desc->drv_data;
1772 u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data);
1773 u8 bit = RZG2L_PIN_ID_TO_PIN(offset);
1774 unsigned long flags;
1775 u8 reg8;
1776
1777 spin_lock_irqsave(&pctrl->lock, flags);
1778
1779 reg8 = readb(pctrl->base + P(off));
1780
1781 if (value)
1782 writeb(reg8 | BIT(bit), pctrl->base + P(off));
1783 else
1784 writeb(reg8 & ~BIT(bit), pctrl->base + P(off));
1785
1786 spin_unlock_irqrestore(&pctrl->lock, flags);
1787
1788 return 0;
1789 }
1790
rzg2l_gpio_direction_output(struct gpio_chip * chip,unsigned int offset,int value)1791 static int rzg2l_gpio_direction_output(struct gpio_chip *chip,
1792 unsigned int offset, int value)
1793 {
1794 struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip);
1795
1796 rzg2l_gpio_set(chip, offset, value);
1797 rzg2l_gpio_set_direction(pctrl, offset, true);
1798
1799 return 0;
1800 }
1801
rzg2l_gpio_get(struct gpio_chip * chip,unsigned int offset)1802 static int rzg2l_gpio_get(struct gpio_chip *chip, unsigned int offset)
1803 {
1804 struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip);
1805 const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[offset];
1806 u64 *pin_data = pin_desc->drv_data;
1807 u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data);
1808 u8 bit = RZG2L_PIN_ID_TO_PIN(offset);
1809 u16 reg16;
1810
1811 reg16 = readw(pctrl->base + PM(off));
1812 reg16 = (reg16 >> (bit * 2)) & PM_MASK;
1813
1814 if (reg16 == PM_INPUT)
1815 return !!(readb(pctrl->base + PIN(off)) & BIT(bit));
1816 else if (reg16 == PM_OUTPUT)
1817 return !!(readb(pctrl->base + P(off)) & BIT(bit));
1818 else
1819 return -EINVAL;
1820 }
1821
rzg2l_gpio_free(struct gpio_chip * chip,unsigned int offset)1822 static void rzg2l_gpio_free(struct gpio_chip *chip, unsigned int offset)
1823 {
1824 unsigned int virq;
1825
1826 pinctrl_gpio_free(chip, offset);
1827
1828 virq = irq_find_mapping(chip->irq.domain, offset);
1829 if (virq)
1830 irq_dispose_mapping(virq);
1831
1832 /*
1833 * Set the GPIO as an input to ensure that the next GPIO request won't
1834 * drive the GPIO pin as an output.
1835 */
1836 rzg2l_gpio_direction_input(chip, offset);
1837 }
1838
1839 static const char * const rzg2l_gpio_names[] = {
1840 "P0_0", "P0_1", "P0_2", "P0_3", "P0_4", "P0_5", "P0_6", "P0_7",
1841 "P1_0", "P1_1", "P1_2", "P1_3", "P1_4", "P1_5", "P1_6", "P1_7",
1842 "P2_0", "P2_1", "P2_2", "P2_3", "P2_4", "P2_5", "P2_6", "P2_7",
1843 "P3_0", "P3_1", "P3_2", "P3_3", "P3_4", "P3_5", "P3_6", "P3_7",
1844 "P4_0", "P4_1", "P4_2", "P4_3", "P4_4", "P4_5", "P4_6", "P4_7",
1845 "P5_0", "P5_1", "P5_2", "P5_3", "P5_4", "P5_5", "P5_6", "P5_7",
1846 "P6_0", "P6_1", "P6_2", "P6_3", "P6_4", "P6_5", "P6_6", "P6_7",
1847 "P7_0", "P7_1", "P7_2", "P7_3", "P7_4", "P7_5", "P7_6", "P7_7",
1848 "P8_0", "P8_1", "P8_2", "P8_3", "P8_4", "P8_5", "P8_6", "P8_7",
1849 "P9_0", "P9_1", "P9_2", "P9_3", "P9_4", "P9_5", "P9_6", "P9_7",
1850 "P10_0", "P10_1", "P10_2", "P10_3", "P10_4", "P10_5", "P10_6", "P10_7",
1851 "P11_0", "P11_1", "P11_2", "P11_3", "P11_4", "P11_5", "P11_6", "P11_7",
1852 "P12_0", "P12_1", "P12_2", "P12_3", "P12_4", "P12_5", "P12_6", "P12_7",
1853 "P13_0", "P13_1", "P13_2", "P13_3", "P13_4", "P13_5", "P13_6", "P13_7",
1854 "P14_0", "P14_1", "P14_2", "P14_3", "P14_4", "P14_5", "P14_6", "P14_7",
1855 "P15_0", "P15_1", "P15_2", "P15_3", "P15_4", "P15_5", "P15_6", "P15_7",
1856 "P16_0", "P16_1", "P16_2", "P16_3", "P16_4", "P16_5", "P16_6", "P16_7",
1857 "P17_0", "P17_1", "P17_2", "P17_3", "P17_4", "P17_5", "P17_6", "P17_7",
1858 "P18_0", "P18_1", "P18_2", "P18_3", "P18_4", "P18_5", "P18_6", "P18_7",
1859 "P19_0", "P19_1", "P19_2", "P19_3", "P19_4", "P19_5", "P19_6", "P19_7",
1860 "P20_0", "P20_1", "P20_2", "P20_3", "P20_4", "P20_5", "P20_6", "P20_7",
1861 "P21_0", "P21_1", "P21_2", "P21_3", "P21_4", "P21_5", "P21_6", "P21_7",
1862 "P22_0", "P22_1", "P22_2", "P22_3", "P22_4", "P22_5", "P22_6", "P22_7",
1863 "P23_0", "P23_1", "P23_2", "P23_3", "P23_4", "P23_5", "P23_6", "P23_7",
1864 "P24_0", "P24_1", "P24_2", "P24_3", "P24_4", "P24_5", "P24_6", "P24_7",
1865 "P25_0", "P25_1", "P25_2", "P25_3", "P25_4", "P25_5", "P25_6", "P25_7",
1866 "P26_0", "P26_1", "P26_2", "P26_3", "P26_4", "P26_5", "P26_6", "P26_7",
1867 "P27_0", "P27_1", "P27_2", "P27_3", "P27_4", "P27_5", "P27_6", "P27_7",
1868 "P28_0", "P28_1", "P28_2", "P28_3", "P28_4", "P28_5", "P28_6", "P28_7",
1869 "P29_0", "P29_1", "P29_2", "P29_3", "P29_4", "P29_5", "P29_6", "P29_7",
1870 "P30_0", "P30_1", "P30_2", "P30_3", "P30_4", "P30_5", "P30_6", "P30_7",
1871 "P31_0", "P31_1", "P31_2", "P31_3", "P31_4", "P31_5", "P31_6", "P31_7",
1872 "P32_0", "P32_1", "P32_2", "P32_3", "P32_4", "P32_5", "P32_6", "P32_7",
1873 "P33_0", "P33_1", "P33_2", "P33_3", "P33_4", "P33_5", "P33_6", "P33_7",
1874 "P34_0", "P34_1", "P34_2", "P34_3", "P34_4", "P34_5", "P34_6", "P34_7",
1875 "P35_0", "P35_1", "P35_2", "P35_3", "P35_4", "P35_5", "P35_6", "P35_7",
1876 "P36_0", "P36_1", "P36_2", "P36_3", "P36_4", "P36_5", "P36_6", "P36_7",
1877 "P37_0", "P37_1", "P37_2", "P37_3", "P37_4", "P37_5", "P37_6", "P37_7",
1878 "P38_0", "P38_1", "P38_2", "P38_3", "P38_4", "P38_5", "P38_6", "P38_7",
1879 "P39_0", "P39_1", "P39_2", "P39_3", "P39_4", "P39_5", "P39_6", "P39_7",
1880 "P40_0", "P40_1", "P40_2", "P40_3", "P40_4", "P40_5", "P40_6", "P40_7",
1881 "P41_0", "P41_1", "P41_2", "P41_3", "P41_4", "P41_5", "P41_6", "P41_7",
1882 "P42_0", "P42_1", "P42_2", "P42_3", "P42_4", "P42_5", "P42_6", "P42_7",
1883 "P43_0", "P43_1", "P43_2", "P43_3", "P43_4", "P43_5", "P43_6", "P43_7",
1884 "P44_0", "P44_1", "P44_2", "P44_3", "P44_4", "P44_5", "P44_6", "P44_7",
1885 "P45_0", "P45_1", "P45_2", "P45_3", "P45_4", "P45_5", "P45_6", "P45_7",
1886 "P46_0", "P46_1", "P46_2", "P46_3", "P46_4", "P46_5", "P46_6", "P46_7",
1887 "P47_0", "P47_1", "P47_2", "P47_3", "P47_4", "P47_5", "P47_6", "P47_7",
1888 "P48_0", "P48_1", "P48_2", "P48_3", "P48_4", "P48_5", "P48_6", "P48_7",
1889 };
1890
1891 static const u64 r9a07g044_gpio_configs[] = {
1892 RZG2L_GPIO_PORT_PACK(2, 0x10, RZG2L_MPXED_PIN_FUNCS),
1893 RZG2L_GPIO_PORT_PACK(2, 0x11, RZG2L_MPXED_PIN_FUNCS),
1894 RZG2L_GPIO_PORT_PACK(2, 0x12, RZG2L_MPXED_PIN_FUNCS),
1895 RZG2L_GPIO_PORT_PACK(2, 0x13, RZG2L_MPXED_PIN_FUNCS),
1896 RZG2L_GPIO_PORT_PACK(2, 0x14, RZG2L_MPXED_PIN_FUNCS),
1897 RZG2L_GPIO_PORT_PACK(3, 0x15, RZG2L_MPXED_PIN_FUNCS),
1898 RZG2L_GPIO_PORT_PACK(2, 0x16, RZG2L_MPXED_PIN_FUNCS),
1899 RZG2L_GPIO_PORT_PACK(3, 0x17, RZG2L_MPXED_PIN_FUNCS),
1900 RZG2L_GPIO_PORT_PACK(3, 0x18, RZG2L_MPXED_PIN_FUNCS),
1901 RZG2L_GPIO_PORT_PACK(2, 0x19, RZG2L_MPXED_PIN_FUNCS),
1902 RZG2L_GPIO_PORT_PACK(2, 0x1a, RZG2L_MPXED_PIN_FUNCS),
1903 RZG2L_GPIO_PORT_PACK(2, 0x1b, RZG2L_MPXED_PIN_FUNCS),
1904 RZG2L_GPIO_PORT_PACK(2, 0x1c, RZG2L_MPXED_PIN_FUNCS),
1905 RZG2L_GPIO_PORT_PACK(3, 0x1d, RZG2L_MPXED_PIN_FUNCS),
1906 RZG2L_GPIO_PORT_PACK(2, 0x1e, RZG2L_MPXED_PIN_FUNCS),
1907 RZG2L_GPIO_PORT_PACK(2, 0x1f, RZG2L_MPXED_PIN_FUNCS),
1908 RZG2L_GPIO_PORT_PACK(2, 0x20, RZG2L_MPXED_PIN_FUNCS),
1909 RZG2L_GPIO_PORT_PACK(3, 0x21, RZG2L_MPXED_PIN_FUNCS),
1910 RZG2L_GPIO_PORT_PACK(2, 0x22, RZG2L_MPXED_PIN_FUNCS),
1911 RZG2L_GPIO_PORT_PACK(2, 0x23, RZG2L_MPXED_PIN_FUNCS),
1912 RZG2L_GPIO_PORT_PACK(3, 0x24, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0) | PIN_CFG_OEN),
1913 RZG2L_GPIO_PORT_PACK(2, 0x25, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
1914 RZG2L_GPIO_PORT_PACK(2, 0x26, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
1915 RZG2L_GPIO_PORT_PACK(2, 0x27, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
1916 RZG2L_GPIO_PORT_PACK(2, 0x28, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
1917 RZG2L_GPIO_PORT_PACK(2, 0x29, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
1918 RZG2L_GPIO_PORT_PACK(2, 0x2a, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
1919 RZG2L_GPIO_PORT_PACK(2, 0x2b, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
1920 RZG2L_GPIO_PORT_PACK(2, 0x2c, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
1921 RZG2L_GPIO_PORT_PACK(2, 0x2d, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1) | PIN_CFG_OEN),
1922 RZG2L_GPIO_PORT_PACK(2, 0x2e, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
1923 RZG2L_GPIO_PORT_PACK(2, 0x2f, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
1924 RZG2L_GPIO_PORT_PACK(2, 0x30, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
1925 RZG2L_GPIO_PORT_PACK(2, 0x31, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
1926 RZG2L_GPIO_PORT_PACK(2, 0x32, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
1927 RZG2L_GPIO_PORT_PACK(2, 0x33, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
1928 RZG2L_GPIO_PORT_PACK(2, 0x34, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
1929 RZG2L_GPIO_PORT_PACK(3, 0x35, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
1930 RZG2L_GPIO_PORT_PACK(2, 0x36, RZG2L_MPXED_PIN_FUNCS),
1931 RZG2L_GPIO_PORT_PACK(3, 0x37, RZG2L_MPXED_PIN_FUNCS),
1932 RZG2L_GPIO_PORT_PACK(3, 0x38, RZG2L_MPXED_PIN_FUNCS),
1933 RZG2L_GPIO_PORT_PACK(2, 0x39, RZG2L_MPXED_PIN_FUNCS),
1934 RZG2L_GPIO_PORT_PACK(5, 0x3a, RZG2L_MPXED_PIN_FUNCS),
1935 RZG2L_GPIO_PORT_PACK(4, 0x3b, RZG2L_MPXED_PIN_FUNCS),
1936 RZG2L_GPIO_PORT_PACK(4, 0x3c, RZG2L_MPXED_PIN_FUNCS),
1937 RZG2L_GPIO_PORT_PACK(4, 0x3d, RZG2L_MPXED_PIN_FUNCS),
1938 RZG2L_GPIO_PORT_PACK(4, 0x3e, RZG2L_MPXED_PIN_FUNCS),
1939 RZG2L_GPIO_PORT_PACK(4, 0x3f, RZG2L_MPXED_PIN_FUNCS),
1940 RZG2L_GPIO_PORT_PACK(5, 0x40, RZG2L_MPXED_PIN_FUNCS),
1941 };
1942
1943 static const u64 r9a07g043_gpio_configs[] = {
1944 RZG2L_GPIO_PORT_PACK(4, 0x10, RZG2L_MPXED_PIN_FUNCS),
1945 RZG2L_GPIO_PORT_PACK(5, 0x11, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0) | PIN_CFG_OEN),
1946 RZG2L_GPIO_PORT_PACK(4, 0x12, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
1947 RZG2L_GPIO_PORT_PACK(4, 0x13, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
1948 RZG2L_GPIO_PORT_PACK(6, 0x14, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
1949 RZG2L_GPIO_PORT_PACK(5, 0x15, RZG2L_MPXED_PIN_FUNCS),
1950 RZG2L_GPIO_PORT_PACK(5, 0x16, RZG2L_MPXED_PIN_FUNCS),
1951 RZG2L_GPIO_PORT_PACK(5, 0x17, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1) | PIN_CFG_OEN),
1952 RZG2L_GPIO_PORT_PACK(5, 0x18, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
1953 RZG2L_GPIO_PORT_PACK(4, 0x19, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
1954 RZG2L_GPIO_PORT_PACK(5, 0x1a, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
1955 RZG2L_GPIO_PORT_PACK(4, 0x1b, RZG2L_MPXED_PIN_FUNCS),
1956 RZG2L_GPIO_PORT_PACK(2, 0x1c, RZG2L_MPXED_PIN_FUNCS),
1957 RZG2L_GPIO_PORT_PACK(5, 0x1d, RZG2L_MPXED_PIN_FUNCS),
1958 RZG2L_GPIO_PORT_PACK(3, 0x1e, RZG2L_MPXED_PIN_FUNCS),
1959 RZG2L_GPIO_PORT_PACK(4, 0x1f, RZG2L_MPXED_PIN_FUNCS),
1960 RZG2L_GPIO_PORT_PACK(2, 0x20, RZG2L_MPXED_PIN_FUNCS),
1961 RZG2L_GPIO_PORT_PACK(4, 0x21, RZG2L_MPXED_PIN_FUNCS),
1962 RZG2L_GPIO_PORT_PACK(6, 0x22, RZG2L_MPXED_PIN_FUNCS),
1963 #ifdef CONFIG_RISCV
1964 /* Below additional port pins (P19 - P28) are exclusively available on RZ/Five SoC only */
1965 RZG2L_GPIO_PORT_SPARSE_PACK(0x2, 0x06, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
1966 PIN_CFG_NF | PIN_CFG_IEN | PIN_CFG_NOGPIO_INT), /* P19 */
1967 RZG2L_GPIO_PORT_PACK_VARIABLE(8, 0x07), /* P20 */
1968 RZG2L_GPIO_PORT_SPARSE_PACK(0x2, 0x08, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
1969 PIN_CFG_IEN | PIN_CFG_NOGPIO_INT), /* P21 */
1970 RZG2L_GPIO_PORT_PACK(4, 0x09, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |
1971 PIN_CFG_IEN | PIN_CFG_NOGPIO_INT), /* P22 */
1972 RZG2L_GPIO_PORT_SPARSE_PACK_VARIABLE(0x3e, 0x0a), /* P23 */
1973 RZG2L_GPIO_PORT_PACK_VARIABLE(6, 0x0b), /* P24 */
1974 RZG2L_GPIO_PORT_SPARSE_PACK(0x2, 0x0c, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_NF |
1975 PIN_CFG_NOGPIO_INT), /* P25 */
1976 0x0, /* P26 */
1977 0x0, /* P27 */
1978 RZG2L_GPIO_PORT_PACK(6, 0x0f, RZG2L_MPXED_PIN_FUNCS | PIN_CFG_NOGPIO_INT), /* P28 */
1979 #endif
1980 };
1981
1982 static const u64 r9a08g045_gpio_configs[] = {
1983 RZG2L_GPIO_PORT_PACK(4, 0x20, RZG3S_MPXED_PIN_FUNCS(A)), /* P0 */
1984 RZG2L_GPIO_PORT_PACK(5, 0x30, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C |
1985 PIN_CFG_IO_VMC_ETH0)) |
1986 PIN_CFG_OEN | PIN_CFG_IEN, /* P1 */
1987 RZG2L_GPIO_PORT_PACK(4, 0x31, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C |
1988 PIN_CFG_IO_VMC_ETH0)), /* P2 */
1989 RZG2L_GPIO_PORT_PACK(4, 0x32, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C |
1990 PIN_CFG_IO_VMC_ETH0)), /* P3 */
1991 RZG2L_GPIO_PORT_PACK(6, 0x33, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C |
1992 PIN_CFG_IO_VMC_ETH0)), /* P4 */
1993 RZG2L_GPIO_PORT_PACK(5, 0x21, RZG3S_MPXED_PIN_FUNCS(A)), /* P5 */
1994 RZG2L_GPIO_PORT_PACK(5, 0x22, RZG3S_MPXED_PIN_FUNCS(A)), /* P6 */
1995 RZG2L_GPIO_PORT_PACK(5, 0x34, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C |
1996 PIN_CFG_IO_VMC_ETH1)) |
1997 PIN_CFG_OEN | PIN_CFG_IEN, /* P7 */
1998 RZG2L_GPIO_PORT_PACK(5, 0x35, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C |
1999 PIN_CFG_IO_VMC_ETH1)), /* P8 */
2000 RZG2L_GPIO_PORT_PACK(4, 0x36, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C |
2001 PIN_CFG_IO_VMC_ETH1)), /* P9 */
2002 RZG2L_GPIO_PORT_PACK(5, 0x37, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C |
2003 PIN_CFG_IO_VMC_ETH1)), /* P10 */
2004 RZG2L_GPIO_PORT_PACK(4, 0x23, RZG3S_MPXED_PIN_FUNCS(B) | PIN_CFG_IEN), /* P11 */
2005 RZG2L_GPIO_PORT_PACK(2, 0x24, RZG3S_MPXED_PIN_FUNCS(B) | PIN_CFG_IEN), /* P12 */
2006 RZG2L_GPIO_PORT_PACK(5, 0x25, RZG3S_MPXED_PIN_FUNCS(A)), /* P13 */
2007 RZG2L_GPIO_PORT_PACK(3, 0x26, RZG3S_MPXED_PIN_FUNCS(A)), /* P14 */
2008 RZG2L_GPIO_PORT_PACK(4, 0x27, RZG3S_MPXED_PIN_FUNCS(A)), /* P15 */
2009 RZG2L_GPIO_PORT_PACK(2, 0x28, RZG3S_MPXED_PIN_FUNCS(A)), /* P16 */
2010 RZG2L_GPIO_PORT_PACK(4, 0x29, RZG3S_MPXED_PIN_FUNCS(A)), /* P17 */
2011 RZG2L_GPIO_PORT_PACK(6, 0x2a, RZG3S_MPXED_PIN_FUNCS(A)), /* P18 */
2012 };
2013
2014 static const char * const rzg3e_gpio_names[] = {
2015 "P00", "P01", "P02", "P03", "P04", "P05", "P06", "P07",
2016 "P10", "P11", "P12", "P13", "P14", "P15", "P16", "P17",
2017 "P20", "P21", "P22", "P23", "P24", "P25", "P26", "P27",
2018 "P30", "P31", "P32", "P33", "P34", "P35", "P36", "P37",
2019 "P40", "P41", "P42", "P43", "P44", "P45", "P46", "P47",
2020 "P50", "P51", "P52", "P53", "P54", "P55", "P56", "P57",
2021 "P60", "P61", "P62", "P63", "P64", "P65", "P66", "P67",
2022 "P70", "P71", "P72", "P73", "P74", "P75", "P76", "P77",
2023 "P80", "P81", "P82", "P83", "P84", "P85", "P86", "P87",
2024 "", "", "", "", "", "", "", "",
2025 "PA0", "PA1", "PA2", "PA3", "PA4", "PA5", "PA6", "PA7",
2026 "PB0", "PB1", "PB2", "PB3", "PB4", "PB5", "PB6", "PB7",
2027 "PC0", "PC1", "PC2", "PC3", "PC4", "PC5", "PC6", "PC7",
2028 "PD0", "PD1", "PD2", "PD3", "PD4", "PD5", "PD6", "PD7",
2029 "PE0", "PE1", "PE2", "PE3", "PE4", "PE5", "PE6", "PE7",
2030 "PF0", "PF1", "PF2", "PF3", "PF4", "PF5", "PF6", "PF7",
2031 "PG0", "PG1", "PG2", "PG3", "PG4", "PG5", "PG6", "PG7",
2032 "PH0", "PH1", "PH2", "PH3", "PH4", "PH5", "PH6", "PH7",
2033 "", "", "", "", "", "", "", "",
2034 "PJ0", "PJ1", "PJ2", "PJ3", "PJ4", "PJ5", "PJ6", "PJ7",
2035 "PK0", "PK1", "PK2", "PK3", "PK4", "PK5", "PK6", "PK7",
2036 "PL0", "PL1", "PL2", "PL3", "PL4", "PL5", "PL6", "PL7",
2037 "PM0", "PM1", "PM2", "PM3", "PM4", "PM5", "PM6", "PM7",
2038 "", "", "", "", "", "", "", "",
2039 "", "", "", "", "", "", "", "",
2040 "", "", "", "", "", "", "", "",
2041 "", "", "", "", "", "", "", "",
2042 "", "", "", "", "", "", "", "",
2043 "PS0", "PS1", "PS2", "PS3", "PS4", "PS5", "PS6", "PS7",
2044 };
2045
2046 static const u64 r9a09g047_gpio_configs[] = {
2047 RZG2L_GPIO_PORT_PACK(8, 0x20, RZV2H_MPXED_PIN_FUNCS), /* P0 */
2048 RZG2L_GPIO_PORT_PACK(8, 0x21, RZV2H_MPXED_PIN_FUNCS |
2049 PIN_CFG_ELC), /* P1 */
2050 RZG2L_GPIO_PORT_PACK(2, 0x22, RZG2L_MPXED_COMMON_PIN_FUNCS(RZV2H) |
2051 PIN_CFG_NOD), /* P2 */
2052 RZG2L_GPIO_PORT_PACK(8, 0x23, RZV2H_MPXED_PIN_FUNCS), /* P3 */
2053 RZG2L_GPIO_PORT_PACK(6, 0x24, RZV2H_MPXED_PIN_FUNCS), /* P4 */
2054 RZG2L_GPIO_PORT_PACK(7, 0x25, RZV2H_MPXED_PIN_FUNCS), /* P5 */
2055 RZG2L_GPIO_PORT_PACK(7, 0x26, RZV2H_MPXED_PIN_FUNCS), /* P6 */
2056 RZG2L_GPIO_PORT_PACK(8, 0x27, RZV2H_MPXED_PIN_FUNCS |
2057 PIN_CFG_ELC), /* P7 */
2058 RZG2L_GPIO_PORT_PACK(6, 0x28, RZV2H_MPXED_PIN_FUNCS), /* P8 */
2059 0x0,
2060 RZG2L_GPIO_PORT_PACK_VARIABLE(8, 0x2a), /* PA */
2061 RZG2L_GPIO_PORT_PACK(8, 0x2b, RZV2H_MPXED_PIN_FUNCS), /* PB */
2062 RZG2L_GPIO_PORT_PACK(3, 0x2c, RZV2H_MPXED_PIN_FUNCS), /* PC */
2063 RZG2L_GPIO_PORT_PACK_VARIABLE(8, 0x2d), /* PD */
2064 RZG2L_GPIO_PORT_PACK(8, 0x2e, RZV2H_MPXED_PIN_FUNCS), /* PE */
2065 RZG2L_GPIO_PORT_PACK(3, 0x2f, RZV2H_MPXED_PIN_FUNCS), /* PF */
2066 RZG2L_GPIO_PORT_PACK_VARIABLE(8, 0x30), /* PG */
2067 RZG2L_GPIO_PORT_PACK_VARIABLE(6, 0x31), /* PH */
2068 0x0,
2069 RZG2L_GPIO_PORT_PACK_VARIABLE(5, 0x33), /* PJ */
2070 RZG2L_GPIO_PORT_PACK(4, 0x34, RZV2H_MPXED_PIN_FUNCS), /* PK */
2071 RZG2L_GPIO_PORT_PACK(8, 0x35, RZV2H_MPXED_PIN_FUNCS), /* PL */
2072 RZG2L_GPIO_PORT_PACK(8, 0x36, RZV2H_MPXED_PIN_FUNCS), /* PM */
2073 0x0,
2074 0x0,
2075 0x0,
2076 0x0,
2077 0x0,
2078 RZG2L_GPIO_PORT_PACK(4, 0x3c, RZV2H_MPXED_PIN_FUNCS), /* PS */
2079 };
2080
2081 static const char * const rzv2h_gpio_names[] = {
2082 "P00", "P01", "P02", "P03", "P04", "P05", "P06", "P07",
2083 "P10", "P11", "P12", "P13", "P14", "P15", "P16", "P17",
2084 "P20", "P21", "P22", "P23", "P24", "P25", "P26", "P27",
2085 "P30", "P31", "P32", "P33", "P34", "P35", "P36", "P37",
2086 "P40", "P41", "P42", "P43", "P44", "P45", "P46", "P47",
2087 "P50", "P51", "P52", "P53", "P54", "P55", "P56", "P57",
2088 "P60", "P61", "P62", "P63", "P64", "P65", "P66", "P67",
2089 "P70", "P71", "P72", "P73", "P74", "P75", "P76", "P77",
2090 "P80", "P81", "P82", "P83", "P84", "P85", "P86", "P87",
2091 "P90", "P91", "P92", "P93", "P94", "P95", "P96", "P97",
2092 "PA0", "PA1", "PA2", "PA3", "PA4", "PA5", "PA6", "PA7",
2093 "PB0", "PB1", "PB2", "PB3", "PB4", "PB5", "PB6", "PB7",
2094 };
2095
2096 static const u64 r9a09g057_gpio_configs[] = {
2097 RZG2L_GPIO_PORT_PACK(8, 0x20, RZV2H_MPXED_PIN_FUNCS), /* P0 */
2098 RZG2L_GPIO_PORT_PACK(6, 0x21, RZV2H_MPXED_PIN_FUNCS), /* P1 */
2099 RZG2L_GPIO_PORT_PACK(2, 0x22, RZG2L_MPXED_COMMON_PIN_FUNCS(RZV2H) |
2100 PIN_CFG_NOD), /* P2 */
2101 RZG2L_GPIO_PORT_PACK(8, 0x23, RZV2H_MPXED_PIN_FUNCS), /* P3 */
2102 RZG2L_GPIO_PORT_PACK(8, 0x24, RZV2H_MPXED_PIN_FUNCS), /* P4 */
2103 RZG2L_GPIO_PORT_PACK(8, 0x25, RZV2H_MPXED_PIN_FUNCS), /* P5 */
2104 RZG2L_GPIO_PORT_PACK(8, 0x26, RZV2H_MPXED_PIN_FUNCS |
2105 PIN_CFG_ELC), /* P6 */
2106 RZG2L_GPIO_PORT_PACK(8, 0x27, RZV2H_MPXED_PIN_FUNCS), /* P7 */
2107 RZG2L_GPIO_PORT_PACK(8, 0x28, RZV2H_MPXED_PIN_FUNCS |
2108 PIN_CFG_ELC), /* P8 */
2109 RZG2L_GPIO_PORT_PACK(8, 0x29, RZV2H_MPXED_PIN_FUNCS), /* P9 */
2110 RZG2L_GPIO_PORT_PACK(8, 0x2a, RZV2H_MPXED_PIN_FUNCS), /* PA */
2111 RZG2L_GPIO_PORT_PACK_VARIABLE(6, 0x2b), /* PB */
2112 };
2113
2114 static const struct {
2115 struct rzg2l_dedicated_configs common[35];
2116 struct rzg2l_dedicated_configs rzg2l_pins[7];
2117 } rzg2l_dedicated_pins = {
2118 .common = {
2119 { "NMI", RZG2L_SINGLE_PIN_PACK(0x1, 0, PIN_CFG_NF) },
2120 { "TMS/SWDIO", RZG2L_SINGLE_PIN_PACK(0x2, 0,
2121 (PIN_CFG_IOLH_A | PIN_CFG_SR | PIN_CFG_IEN)) },
2122 { "TDO", RZG2L_SINGLE_PIN_PACK(0x3, 0,
2123 (PIN_CFG_IOLH_A | PIN_CFG_SR | PIN_CFG_IEN)) },
2124 { "AUDIO_CLK1", RZG2L_SINGLE_PIN_PACK(0x4, 0, PIN_CFG_IEN) },
2125 { "AUDIO_CLK2", RZG2L_SINGLE_PIN_PACK(0x4, 1, PIN_CFG_IEN) },
2126 { "SD0_CLK", RZG2L_SINGLE_PIN_PACK(0x6, 0,
2127 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_SD0)) },
2128 { "SD0_CMD", RZG2L_SINGLE_PIN_PACK(0x6, 1,
2129 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) },
2130 { "SD0_RST#", RZG2L_SINGLE_PIN_PACK(0x6, 2,
2131 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_SD0)) },
2132 { "SD0_DATA0", RZG2L_SINGLE_PIN_PACK(0x7, 0,
2133 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) },
2134 { "SD0_DATA1", RZG2L_SINGLE_PIN_PACK(0x7, 1,
2135 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) },
2136 { "SD0_DATA2", RZG2L_SINGLE_PIN_PACK(0x7, 2,
2137 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) },
2138 { "SD0_DATA3", RZG2L_SINGLE_PIN_PACK(0x7, 3,
2139 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) },
2140 { "SD0_DATA4", RZG2L_SINGLE_PIN_PACK(0x7, 4,
2141 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) },
2142 { "SD0_DATA5", RZG2L_SINGLE_PIN_PACK(0x7, 5,
2143 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) },
2144 { "SD0_DATA6", RZG2L_SINGLE_PIN_PACK(0x7, 6,
2145 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) },
2146 { "SD0_DATA7", RZG2L_SINGLE_PIN_PACK(0x7, 7,
2147 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) },
2148 { "SD1_CLK", RZG2L_SINGLE_PIN_PACK(0x8, 0,
2149 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_SD1)) },
2150 { "SD1_CMD", RZG2L_SINGLE_PIN_PACK(0x8, 1,
2151 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1)) },
2152 { "SD1_DATA0", RZG2L_SINGLE_PIN_PACK(0x9, 0,
2153 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1)) },
2154 { "SD1_DATA1", RZG2L_SINGLE_PIN_PACK(0x9, 1,
2155 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1)) },
2156 { "SD1_DATA2", RZG2L_SINGLE_PIN_PACK(0x9, 2,
2157 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1)) },
2158 { "SD1_DATA3", RZG2L_SINGLE_PIN_PACK(0x9, 3,
2159 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1)) },
2160 { "QSPI0_SPCLK", RZG2L_SINGLE_PIN_PACK(0xa, 0,
2161 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
2162 { "QSPI0_IO0", RZG2L_SINGLE_PIN_PACK(0xa, 1,
2163 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
2164 { "QSPI0_IO1", RZG2L_SINGLE_PIN_PACK(0xa, 2,
2165 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
2166 { "QSPI0_IO2", RZG2L_SINGLE_PIN_PACK(0xa, 3,
2167 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
2168 { "QSPI0_IO3", RZG2L_SINGLE_PIN_PACK(0xa, 4,
2169 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
2170 { "QSPI0_SSL", RZG2L_SINGLE_PIN_PACK(0xa, 5,
2171 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
2172 { "QSPI_RESET#", RZG2L_SINGLE_PIN_PACK(0xc, 0,
2173 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
2174 { "QSPI_WP#", RZG2L_SINGLE_PIN_PACK(0xc, 1,
2175 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
2176 { "WDTOVF_PERROUT#", RZG2L_SINGLE_PIN_PACK(0xd, 0, (PIN_CFG_IOLH_A | PIN_CFG_SR)) },
2177 { "RIIC0_SDA", RZG2L_SINGLE_PIN_PACK(0xe, 0, PIN_CFG_IEN) },
2178 { "RIIC0_SCL", RZG2L_SINGLE_PIN_PACK(0xe, 1, PIN_CFG_IEN) },
2179 { "RIIC1_SDA", RZG2L_SINGLE_PIN_PACK(0xe, 2, PIN_CFG_IEN) },
2180 { "RIIC1_SCL", RZG2L_SINGLE_PIN_PACK(0xe, 3, PIN_CFG_IEN) },
2181 },
2182 .rzg2l_pins = {
2183 { "QSPI_INT#", RZG2L_SINGLE_PIN_PACK(0xc, 2, (PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
2184 { "QSPI1_SPCLK", RZG2L_SINGLE_PIN_PACK(0xb, 0,
2185 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
2186 { "QSPI1_IO0", RZG2L_SINGLE_PIN_PACK(0xb, 1,
2187 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
2188 { "QSPI1_IO1", RZG2L_SINGLE_PIN_PACK(0xb, 2,
2189 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
2190 { "QSPI1_IO2", RZG2L_SINGLE_PIN_PACK(0xb, 3,
2191 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
2192 { "QSPI1_IO3", RZG2L_SINGLE_PIN_PACK(0xb, 4,
2193 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
2194 { "QSPI1_SSL", RZG2L_SINGLE_PIN_PACK(0xb, 5,
2195 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) },
2196 }
2197 };
2198
2199 static const struct rzg2l_dedicated_configs rzg3s_dedicated_pins[] = {
2200 { "NMI", RZG2L_SINGLE_PIN_PACK(0x0, 0, PIN_CFG_NF) },
2201 { "TMS/SWDIO", RZG2L_SINGLE_PIN_PACK(0x1, 0, (PIN_CFG_IOLH_A | PIN_CFG_IEN |
2202 PIN_CFG_SOFT_PS)) },
2203 { "TDO", RZG2L_SINGLE_PIN_PACK(0x1, 1, (PIN_CFG_IOLH_A | PIN_CFG_SOFT_PS)) },
2204 { "AUDIO_CLK1", RZG2L_SINGLE_PIN_PACK(0x2, 0, PIN_CFG_IEN) },
2205 { "AUDIO_CLK2", RZG2L_SINGLE_PIN_PACK(0x2, 1, PIN_CFG_IEN) },
2206 { "WDTOVF_PERROUT#", RZG2L_SINGLE_PIN_PACK(0x6, 0, PIN_CFG_IOLH_A | PIN_CFG_SOFT_PS) },
2207 { "SD0_CLK", RZG2L_SINGLE_PIN_PACK(0x10, 0, (PIN_CFG_IOLH_B | PIN_CFG_IO_VMC_SD0)) },
2208 { "SD0_CMD", RZG2L_SINGLE_PIN_PACK(0x10, 1, (PIN_CFG_IOLH_B | PIN_CFG_IEN |
2209 PIN_CFG_IO_VMC_SD0)) },
2210 { "SD0_RST#", RZG2L_SINGLE_PIN_PACK(0x10, 2, (PIN_CFG_IOLH_B | PIN_CFG_IO_VMC_SD0)) },
2211 { "SD0_DATA0", RZG2L_SINGLE_PIN_PACK(0x11, 0, (PIN_CFG_IOLH_B | PIN_CFG_IEN |
2212 PIN_CFG_IO_VMC_SD0)) },
2213 { "SD0_DATA1", RZG2L_SINGLE_PIN_PACK(0x11, 1, (PIN_CFG_IOLH_B | PIN_CFG_IEN |
2214 PIN_CFG_IO_VMC_SD0)) },
2215 { "SD0_DATA2", RZG2L_SINGLE_PIN_PACK(0x11, 2, (PIN_CFG_IOLH_B | PIN_CFG_IEN |
2216 PIN_CFG_IO_VMC_SD0)) },
2217 { "SD0_DATA3", RZG2L_SINGLE_PIN_PACK(0x11, 3, (PIN_CFG_IOLH_B | PIN_CFG_IEN |
2218 PIN_CFG_IO_VMC_SD0)) },
2219 { "SD0_DATA4", RZG2L_SINGLE_PIN_PACK(0x11, 4, (PIN_CFG_IOLH_B | PIN_CFG_IEN |
2220 PIN_CFG_IO_VMC_SD0)) },
2221 { "SD0_DATA5", RZG2L_SINGLE_PIN_PACK(0x11, 5, (PIN_CFG_IOLH_B | PIN_CFG_IEN |
2222 PIN_CFG_IO_VMC_SD0)) },
2223 { "SD0_DATA6", RZG2L_SINGLE_PIN_PACK(0x11, 6, (PIN_CFG_IOLH_B | PIN_CFG_IEN |
2224 PIN_CFG_IO_VMC_SD0)) },
2225 { "SD0_DATA7", RZG2L_SINGLE_PIN_PACK(0x11, 7, (PIN_CFG_IOLH_B | PIN_CFG_IEN |
2226 PIN_CFG_IO_VMC_SD0)) },
2227 { "SD1_CLK", RZG2L_SINGLE_PIN_PACK(0x12, 0, (PIN_CFG_IOLH_B | PIN_CFG_IO_VMC_SD1)) },
2228 { "SD1_CMD", RZG2L_SINGLE_PIN_PACK(0x12, 1, (PIN_CFG_IOLH_B | PIN_CFG_IEN |
2229 PIN_CFG_IO_VMC_SD1)) },
2230 { "SD1_DATA0", RZG2L_SINGLE_PIN_PACK(0x13, 0, (PIN_CFG_IOLH_B | PIN_CFG_IEN |
2231 PIN_CFG_IO_VMC_SD1)) },
2232 { "SD1_DATA1", RZG2L_SINGLE_PIN_PACK(0x13, 1, (PIN_CFG_IOLH_B | PIN_CFG_IEN |
2233 PIN_CFG_IO_VMC_SD1)) },
2234 { "SD1_DATA2", RZG2L_SINGLE_PIN_PACK(0x13, 2, (PIN_CFG_IOLH_B | PIN_CFG_IEN |
2235 PIN_CFG_IO_VMC_SD1)) },
2236 { "SD1_DATA3", RZG2L_SINGLE_PIN_PACK(0x13, 3, (PIN_CFG_IOLH_B | PIN_CFG_IEN |
2237 PIN_CFG_IO_VMC_SD1)) },
2238 };
2239
2240 static const struct {
2241 struct rzg2l_dedicated_configs common[77];
2242 struct rzg2l_dedicated_configs pcie1[1];
2243 } rzv2h_dedicated_pins = {
2244 .common = {
2245 { "NMI", RZG2L_SINGLE_PIN_PACK(0x1, 0, PIN_CFG_NF) },
2246 { "TMS_SWDIO", RZG2L_SINGLE_PIN_PACK(0x3, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2247 PIN_CFG_IEN)) },
2248 { "TDO", RZG2L_SINGLE_PIN_PACK(0x3, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR)) },
2249 { "WDTUDFCA", RZG2L_SINGLE_PIN_PACK(0x5, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2250 PIN_CFG_PUPD | PIN_CFG_NOD)) },
2251 { "WDTUDFCM", RZG2L_SINGLE_PIN_PACK(0x5, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2252 PIN_CFG_PUPD | PIN_CFG_NOD)) },
2253 { "SCIF_RXD", RZG2L_SINGLE_PIN_PACK(0x6, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2254 PIN_CFG_PUPD)) },
2255 { "SCIF_TXD", RZG2L_SINGLE_PIN_PACK(0x6, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2256 PIN_CFG_PUPD)) },
2257 { "XSPI0_CKP", RZG2L_SINGLE_PIN_PACK(0x7, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2258 PIN_CFG_PUPD | PIN_CFG_OEN)) },
2259 { "XSPI0_CKN", RZG2L_SINGLE_PIN_PACK(0x7, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2260 PIN_CFG_PUPD | PIN_CFG_OEN)) },
2261 { "XSPI0_CS0N", RZG2L_SINGLE_PIN_PACK(0x7, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2262 PIN_CFG_PUPD | PIN_CFG_OEN)) },
2263 { "XSPI0_DS", RZG2L_SINGLE_PIN_PACK(0x7, 3, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2264 PIN_CFG_PUPD)) },
2265 { "XSPI0_RESET0N", RZG2L_SINGLE_PIN_PACK(0x7, 4, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2266 PIN_CFG_PUPD | PIN_CFG_OEN)) },
2267 { "XSPI0_RSTO0N", RZG2L_SINGLE_PIN_PACK(0x7, 5, (PIN_CFG_PUPD)) },
2268 { "XSPI0_INT0N", RZG2L_SINGLE_PIN_PACK(0x7, 6, (PIN_CFG_PUPD)) },
2269 { "XSPI0_ECS0N", RZG2L_SINGLE_PIN_PACK(0x7, 7, (PIN_CFG_PUPD)) },
2270 { "XSPI0_IO0", RZG2L_SINGLE_PIN_PACK(0x8, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2271 PIN_CFG_PUPD)) },
2272 { "XSPI0_IO1", RZG2L_SINGLE_PIN_PACK(0x8, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2273 PIN_CFG_PUPD)) },
2274 { "XSPI0_IO2", RZG2L_SINGLE_PIN_PACK(0x8, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2275 PIN_CFG_PUPD)) },
2276 { "XSPI0_IO3", RZG2L_SINGLE_PIN_PACK(0x8, 3, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2277 PIN_CFG_PUPD)) },
2278 { "XSPI0_IO4", RZG2L_SINGLE_PIN_PACK(0x8, 4, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2279 PIN_CFG_PUPD)) },
2280 { "XSPI0_IO5", RZG2L_SINGLE_PIN_PACK(0x8, 5, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2281 PIN_CFG_PUPD)) },
2282 { "XSPI0_IO6", RZG2L_SINGLE_PIN_PACK(0x8, 6, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2283 PIN_CFG_PUPD)) },
2284 { "XSPI0_IO7", RZG2L_SINGLE_PIN_PACK(0x8, 7, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2285 PIN_CFG_PUPD)) },
2286 { "SD0CLK", RZG2L_SINGLE_PIN_PACK(0x9, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR)) },
2287 { "SD0CMD", RZG2L_SINGLE_PIN_PACK(0x9, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2288 PIN_CFG_IEN | PIN_CFG_PUPD)) },
2289 { "SD0RSTN", RZG2L_SINGLE_PIN_PACK(0x9, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR)) },
2290 { "SD0DAT0", RZG2L_SINGLE_PIN_PACK(0xa, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2291 PIN_CFG_IEN | PIN_CFG_PUPD)) },
2292 { "SD0DAT1", RZG2L_SINGLE_PIN_PACK(0xa, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2293 PIN_CFG_IEN | PIN_CFG_PUPD)) },
2294 { "SD0DAT2", RZG2L_SINGLE_PIN_PACK(0xa, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2295 PIN_CFG_IEN | PIN_CFG_PUPD)) },
2296 { "SD0DAT3", RZG2L_SINGLE_PIN_PACK(0xa, 3, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2297 PIN_CFG_IEN | PIN_CFG_PUPD)) },
2298 { "SD0DAT4", RZG2L_SINGLE_PIN_PACK(0xa, 4, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2299 PIN_CFG_IEN | PIN_CFG_PUPD)) },
2300 { "SD0DAT5", RZG2L_SINGLE_PIN_PACK(0xa, 5, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2301 PIN_CFG_IEN | PIN_CFG_PUPD)) },
2302 { "SD0DAT6", RZG2L_SINGLE_PIN_PACK(0xa, 6, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2303 PIN_CFG_IEN | PIN_CFG_PUPD)) },
2304 { "SD0DAT7", RZG2L_SINGLE_PIN_PACK(0xa, 7, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2305 PIN_CFG_IEN | PIN_CFG_PUPD)) },
2306 { "SD1CLK", RZG2L_SINGLE_PIN_PACK(0xb, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR)) },
2307 { "SD1CMD", RZG2L_SINGLE_PIN_PACK(0xb, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2308 PIN_CFG_IEN | PIN_CFG_PUPD)) },
2309 { "SD1DAT0", RZG2L_SINGLE_PIN_PACK(0xc, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2310 PIN_CFG_IEN | PIN_CFG_PUPD)) },
2311 { "SD1DAT1", RZG2L_SINGLE_PIN_PACK(0xc, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2312 PIN_CFG_IEN | PIN_CFG_PUPD)) },
2313 { "SD1DAT2", RZG2L_SINGLE_PIN_PACK(0xc, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2314 PIN_CFG_IEN | PIN_CFG_PUPD)) },
2315 { "SD1DAT3", RZG2L_SINGLE_PIN_PACK(0xc, 3, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2316 PIN_CFG_IEN | PIN_CFG_PUPD)) },
2317 { "PCIE0_RSTOUTB", RZG2L_SINGLE_PIN_PACK(0xe, 0, (PIN_CFG_IOLH_RZV2H |
2318 PIN_CFG_SR)) },
2319 { "ET0_MDIO", RZG2L_SINGLE_PIN_PACK(0xf, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2320 PIN_CFG_IEN | PIN_CFG_PUPD)) },
2321 { "ET0_MDC", RZG2L_SINGLE_PIN_PACK(0xf, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2322 PIN_CFG_PUPD)) },
2323 { "ET0_RXCTL_RXDV", RZG2L_SINGLE_PIN_PACK(0x10, 0, (PIN_CFG_PUPD)) },
2324 { "ET0_TXCTL_TXEN", RZG2L_SINGLE_PIN_PACK(0x10, 1, (PIN_CFG_IOLH_RZV2H |
2325 PIN_CFG_SR |
2326 PIN_CFG_PUPD)) },
2327 { "ET0_TXER", RZG2L_SINGLE_PIN_PACK(0x10, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2328 PIN_CFG_PUPD)) },
2329 { "ET0_RXER", RZG2L_SINGLE_PIN_PACK(0x10, 3, (PIN_CFG_PUPD)) },
2330 { "ET0_RXC_RXCLK", RZG2L_SINGLE_PIN_PACK(0x10, 4, (PIN_CFG_PUPD)) },
2331 { "ET0_TXC_TXCLK", RZG2L_SINGLE_PIN_PACK(0x10, 5, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2332 PIN_CFG_PUPD | PIN_CFG_OEN)) },
2333 { "ET0_CRS", RZG2L_SINGLE_PIN_PACK(0x10, 6, (PIN_CFG_PUPD)) },
2334 { "ET0_COL", RZG2L_SINGLE_PIN_PACK(0x10, 7, (PIN_CFG_PUPD)) },
2335 { "ET0_TXD0", RZG2L_SINGLE_PIN_PACK(0x11, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2336 PIN_CFG_PUPD)) },
2337 { "ET0_TXD1", RZG2L_SINGLE_PIN_PACK(0x11, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2338 PIN_CFG_PUPD)) },
2339 { "ET0_TXD2", RZG2L_SINGLE_PIN_PACK(0x11, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2340 PIN_CFG_PUPD)) },
2341 { "ET0_TXD3", RZG2L_SINGLE_PIN_PACK(0x11, 3, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2342 PIN_CFG_PUPD)) },
2343 { "ET0_RXD0", RZG2L_SINGLE_PIN_PACK(0x11, 4, (PIN_CFG_PUPD)) },
2344 { "ET0_RXD1", RZG2L_SINGLE_PIN_PACK(0x11, 5, (PIN_CFG_PUPD)) },
2345 { "ET0_RXD2", RZG2L_SINGLE_PIN_PACK(0x11, 6, (PIN_CFG_PUPD)) },
2346 { "ET0_RXD3", RZG2L_SINGLE_PIN_PACK(0x11, 7, (PIN_CFG_PUPD)) },
2347 { "ET1_MDIO", RZG2L_SINGLE_PIN_PACK(0x12, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2348 PIN_CFG_IEN | PIN_CFG_PUPD)) },
2349 { "ET1_MDC", RZG2L_SINGLE_PIN_PACK(0x12, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2350 PIN_CFG_PUPD)) },
2351 { "ET1_RXCTL_RXDV", RZG2L_SINGLE_PIN_PACK(0x13, 0, (PIN_CFG_PUPD)) },
2352 { "ET1_TXCTL_TXEN", RZG2L_SINGLE_PIN_PACK(0x13, 1, (PIN_CFG_IOLH_RZV2H |
2353 PIN_CFG_SR |
2354 PIN_CFG_PUPD)) },
2355 { "ET1_TXER", RZG2L_SINGLE_PIN_PACK(0x13, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2356 PIN_CFG_PUPD)) },
2357 { "ET1_RXER", RZG2L_SINGLE_PIN_PACK(0x13, 3, (PIN_CFG_PUPD)) },
2358 { "ET1_RXC_RXCLK", RZG2L_SINGLE_PIN_PACK(0x13, 4, (PIN_CFG_PUPD)) },
2359 { "ET1_TXC_TXCLK", RZG2L_SINGLE_PIN_PACK(0x13, 5, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2360 PIN_CFG_PUPD | PIN_CFG_OEN)) },
2361 { "ET1_CRS", RZG2L_SINGLE_PIN_PACK(0x13, 6, (PIN_CFG_PUPD)) },
2362 { "ET1_COL", RZG2L_SINGLE_PIN_PACK(0x13, 7, (PIN_CFG_PUPD)) },
2363 { "ET1_TXD0", RZG2L_SINGLE_PIN_PACK(0x14, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2364 PIN_CFG_PUPD)) },
2365 { "ET1_TXD1", RZG2L_SINGLE_PIN_PACK(0x14, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2366 PIN_CFG_PUPD)) },
2367 { "ET1_TXD2", RZG2L_SINGLE_PIN_PACK(0x14, 2, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2368 PIN_CFG_PUPD)) },
2369 { "ET1_TXD3", RZG2L_SINGLE_PIN_PACK(0x14, 3, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
2370 PIN_CFG_PUPD)) },
2371 { "ET1_RXD0", RZG2L_SINGLE_PIN_PACK(0x14, 4, (PIN_CFG_PUPD)) },
2372 { "ET1_RXD1", RZG2L_SINGLE_PIN_PACK(0x14, 5, (PIN_CFG_PUPD)) },
2373 { "ET1_RXD2", RZG2L_SINGLE_PIN_PACK(0x14, 6, (PIN_CFG_PUPD)) },
2374 { "ET1_RXD3", RZG2L_SINGLE_PIN_PACK(0x14, 7, (PIN_CFG_PUPD)) },
2375 },
2376 .pcie1 = {
2377 { "PCIE1_RSTOUTB", RZG2L_SINGLE_PIN_PACK(0xe, 1, (PIN_CFG_IOLH_RZV2H |
2378 PIN_CFG_SR)) },
2379 },
2380 };
2381
2382 static struct rzg2l_dedicated_configs rzg3e_dedicated_pins[] = {
2383 { "WDTUDFCA", RZG2L_SINGLE_PIN_PACK(0x5, 0,
2384 (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | PIN_CFG_PUPD | PIN_CFG_NOD)) },
2385 { "WDTUDFCM", RZG2L_SINGLE_PIN_PACK(0x5, 1,
2386 (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | PIN_CFG_PUPD | PIN_CFG_NOD)) },
2387 { "SCIF_RXD", RZG2L_SINGLE_PIN_PACK(0x6, 0,
2388 (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | PIN_CFG_PUPD)) },
2389 { "SCIF_TXD", RZG2L_SINGLE_PIN_PACK(0x6, 1,
2390 (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | PIN_CFG_PUPD)) },
2391 { "SD0CLK", RZG2L_SINGLE_PIN_PACK(0x9, 0,
2392 (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR)) },
2393 { "SD0CMD", RZG2L_SINGLE_PIN_PACK(0x9, 1,
2394 (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_PUPD)) },
2395 { "SD0RSTN", RZG2L_SINGLE_PIN_PACK(0x9, 2,
2396 (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR)) },
2397 { "SD0PWEN", RZG2L_SINGLE_PIN_PACK(0x9, 3,
2398 (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR)) },
2399 { "SD0IOVS", RZG2L_SINGLE_PIN_PACK(0x9, 4,
2400 (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR)) },
2401 { "SD0DAT0", RZG2L_SINGLE_PIN_PACK(0xa, 0,
2402 (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_PUPD)) },
2403 { "SD0DAT1", RZG2L_SINGLE_PIN_PACK(0xa, 1,
2404 (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_PUPD)) },
2405 { "SD0DAT2", RZG2L_SINGLE_PIN_PACK(0xa, 2,
2406 (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_PUPD)) },
2407 { "SD0DAT3", RZG2L_SINGLE_PIN_PACK(0xa, 3,
2408 (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_PUPD)) },
2409 { "SD0DAT4", RZG2L_SINGLE_PIN_PACK(0xa, 4,
2410 (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_PUPD)) },
2411 { "SD0DAT5", RZG2L_SINGLE_PIN_PACK(0xa, 5,
2412 (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_PUPD)) },
2413 { "SD0DAT6", RZG2L_SINGLE_PIN_PACK(0xa, 6,
2414 (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_PUPD)) },
2415 { "SD0DAT7", RZG2L_SINGLE_PIN_PACK(0xa, 7,
2416 (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_PUPD)) },
2417 };
2418
rzg2l_gpio_get_gpioint(unsigned int virq,struct rzg2l_pinctrl * pctrl)2419 static int rzg2l_gpio_get_gpioint(unsigned int virq, struct rzg2l_pinctrl *pctrl)
2420 {
2421 const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[virq];
2422 const struct rzg2l_pinctrl_data *data = pctrl->data;
2423 u64 *pin_data = pin_desc->drv_data;
2424 unsigned int gpioint;
2425 unsigned int i;
2426 u32 port, bit;
2427
2428 if (*pin_data & PIN_CFG_NOGPIO_INT)
2429 return -EINVAL;
2430
2431 port = virq / 8;
2432 bit = virq % 8;
2433
2434 if (port >= data->n_ports ||
2435 bit >= hweight8(FIELD_GET(PIN_CFG_PIN_MAP_MASK, data->port_pin_configs[port])))
2436 return -EINVAL;
2437
2438 gpioint = bit;
2439 for (i = 0; i < port; i++)
2440 gpioint += hweight8(FIELD_GET(PIN_CFG_PIN_MAP_MASK, data->port_pin_configs[i]));
2441
2442 return gpioint;
2443 }
2444
rzg2l_gpio_irq_endisable(struct rzg2l_pinctrl * pctrl,unsigned int hwirq,bool enable)2445 static void rzg2l_gpio_irq_endisable(struct rzg2l_pinctrl *pctrl,
2446 unsigned int hwirq, bool enable)
2447 {
2448 const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[hwirq];
2449 u64 *pin_data = pin_desc->drv_data;
2450 u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data);
2451 u8 bit = RZG2L_PIN_ID_TO_PIN(hwirq);
2452 unsigned long flags;
2453 void __iomem *addr;
2454
2455 addr = pctrl->base + ISEL(off);
2456 if (bit >= 4) {
2457 bit -= 4;
2458 addr += 4;
2459 }
2460
2461 spin_lock_irqsave(&pctrl->lock, flags);
2462 if (enable)
2463 writel(readl(addr) | BIT(bit * 8), addr);
2464 else
2465 writel(readl(addr) & ~BIT(bit * 8), addr);
2466 spin_unlock_irqrestore(&pctrl->lock, flags);
2467 }
2468
rzg2l_gpio_irq_disable(struct irq_data * d)2469 static void rzg2l_gpio_irq_disable(struct irq_data *d)
2470 {
2471 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
2472 unsigned int hwirq = irqd_to_hwirq(d);
2473
2474 irq_chip_disable_parent(d);
2475 gpiochip_disable_irq(gc, hwirq);
2476 }
2477
rzg2l_gpio_irq_enable(struct irq_data * d)2478 static void rzg2l_gpio_irq_enable(struct irq_data *d)
2479 {
2480 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
2481 unsigned int hwirq = irqd_to_hwirq(d);
2482
2483 gpiochip_enable_irq(gc, hwirq);
2484 irq_chip_enable_parent(d);
2485 }
2486
rzg2l_gpio_irq_set_type(struct irq_data * d,unsigned int type)2487 static int rzg2l_gpio_irq_set_type(struct irq_data *d, unsigned int type)
2488 {
2489 return irq_chip_set_type_parent(d, type);
2490 }
2491
rzg2l_gpio_irqc_eoi(struct irq_data * d)2492 static void rzg2l_gpio_irqc_eoi(struct irq_data *d)
2493 {
2494 irq_chip_eoi_parent(d);
2495 }
2496
rzg2l_gpio_irq_print_chip(struct irq_data * data,struct seq_file * p)2497 static void rzg2l_gpio_irq_print_chip(struct irq_data *data, struct seq_file *p)
2498 {
2499 struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
2500
2501 seq_puts(p, dev_name(gc->parent));
2502 }
2503
rzg2l_gpio_irq_set_wake(struct irq_data * data,unsigned int on)2504 static int rzg2l_gpio_irq_set_wake(struct irq_data *data, unsigned int on)
2505 {
2506 struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
2507 struct rzg2l_pinctrl *pctrl = container_of(gc, struct rzg2l_pinctrl, gpio_chip);
2508 int ret;
2509
2510 /* It should not happen. */
2511 if (!data->parent_data)
2512 return -EOPNOTSUPP;
2513
2514 ret = irq_chip_set_wake_parent(data, on);
2515 if (ret)
2516 return ret;
2517
2518 if (on)
2519 atomic_inc(&pctrl->wakeup_path);
2520 else
2521 atomic_dec(&pctrl->wakeup_path);
2522
2523 return 0;
2524 }
2525
2526 static const struct irq_chip rzg2l_gpio_irqchip = {
2527 .name = "rzg2l-gpio",
2528 .irq_disable = rzg2l_gpio_irq_disable,
2529 .irq_enable = rzg2l_gpio_irq_enable,
2530 .irq_mask = irq_chip_mask_parent,
2531 .irq_unmask = irq_chip_unmask_parent,
2532 .irq_set_type = rzg2l_gpio_irq_set_type,
2533 .irq_eoi = rzg2l_gpio_irqc_eoi,
2534 .irq_print_chip = rzg2l_gpio_irq_print_chip,
2535 .irq_set_affinity = irq_chip_set_affinity_parent,
2536 .irq_set_wake = rzg2l_gpio_irq_set_wake,
2537 .flags = IRQCHIP_IMMUTABLE,
2538 GPIOCHIP_IRQ_RESOURCE_HELPERS,
2539 };
2540
rzg2l_gpio_interrupt_input_mode(struct gpio_chip * chip,unsigned int offset)2541 static int rzg2l_gpio_interrupt_input_mode(struct gpio_chip *chip, unsigned int offset)
2542 {
2543 struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip);
2544 const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[offset];
2545 u64 *pin_data = pin_desc->drv_data;
2546 u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data);
2547 u8 bit = RZG2L_PIN_ID_TO_PIN(offset);
2548 u8 reg8;
2549 int ret;
2550
2551 reg8 = readb(pctrl->base + PMC(off));
2552 if (reg8 & BIT(bit)) {
2553 ret = rzg2l_gpio_request(chip, offset);
2554 if (ret)
2555 return ret;
2556 }
2557
2558 return rzg2l_gpio_direction_input(chip, offset);
2559 }
2560
rzg2l_gpio_child_to_parent_hwirq(struct gpio_chip * gc,unsigned int child,unsigned int child_type,unsigned int * parent,unsigned int * parent_type)2561 static int rzg2l_gpio_child_to_parent_hwirq(struct gpio_chip *gc,
2562 unsigned int child,
2563 unsigned int child_type,
2564 unsigned int *parent,
2565 unsigned int *parent_type)
2566 {
2567 struct rzg2l_pinctrl *pctrl = gpiochip_get_data(gc);
2568 unsigned long flags;
2569 int gpioint, irq;
2570 int ret;
2571
2572 gpioint = rzg2l_gpio_get_gpioint(child, pctrl);
2573 if (gpioint < 0)
2574 return gpioint;
2575
2576 ret = rzg2l_gpio_interrupt_input_mode(gc, child);
2577 if (ret)
2578 return ret;
2579
2580 spin_lock_irqsave(&pctrl->bitmap_lock, flags);
2581 irq = bitmap_find_free_region(pctrl->tint_slot, RZG2L_TINT_MAX_INTERRUPT, get_order(1));
2582 spin_unlock_irqrestore(&pctrl->bitmap_lock, flags);
2583 if (irq < 0) {
2584 ret = -ENOSPC;
2585 goto err;
2586 }
2587
2588 rzg2l_gpio_irq_endisable(pctrl, child, true);
2589 pctrl->hwirq[irq] = child;
2590 irq += pctrl->data->hwcfg->tint_start_index;
2591
2592 /* All these interrupts are level high in the CPU */
2593 *parent_type = IRQ_TYPE_LEVEL_HIGH;
2594 *parent = RZG2L_PACK_HWIRQ(gpioint, irq);
2595 return 0;
2596
2597 err:
2598 rzg2l_gpio_free(gc, child);
2599 return ret;
2600 }
2601
rzg2l_gpio_irq_restore(struct rzg2l_pinctrl * pctrl)2602 static void rzg2l_gpio_irq_restore(struct rzg2l_pinctrl *pctrl)
2603 {
2604 struct irq_domain *domain = pctrl->gpio_chip.irq.domain;
2605
2606 for (unsigned int i = 0; i < RZG2L_TINT_MAX_INTERRUPT; i++) {
2607 struct irq_data *data;
2608 unsigned long flags;
2609 unsigned int virq;
2610 int ret;
2611
2612 if (!pctrl->hwirq[i])
2613 continue;
2614
2615 virq = irq_find_mapping(domain, pctrl->hwirq[i]);
2616 if (!virq) {
2617 dev_crit(pctrl->dev, "Failed to find IRQ mapping for hwirq %u\n",
2618 pctrl->hwirq[i]);
2619 continue;
2620 }
2621
2622 data = irq_domain_get_irq_data(domain, virq);
2623 if (!data) {
2624 dev_crit(pctrl->dev, "Failed to get IRQ data for virq=%u\n", virq);
2625 continue;
2626 }
2627
2628 /*
2629 * This has to be atomically executed to protect against a concurrent
2630 * interrupt.
2631 */
2632 spin_lock_irqsave(&pctrl->lock, flags);
2633 ret = rzg2l_gpio_irq_set_type(data, irqd_get_trigger_type(data));
2634 if (!ret && !irqd_irq_disabled(data))
2635 rzg2l_gpio_irq_enable(data);
2636 spin_unlock_irqrestore(&pctrl->lock, flags);
2637
2638 if (ret)
2639 dev_crit(pctrl->dev, "Failed to set IRQ type for virq=%u\n", virq);
2640 }
2641 }
2642
rzg2l_gpio_irq_domain_free(struct irq_domain * domain,unsigned int virq,unsigned int nr_irqs)2643 static void rzg2l_gpio_irq_domain_free(struct irq_domain *domain, unsigned int virq,
2644 unsigned int nr_irqs)
2645 {
2646 struct irq_data *d;
2647
2648 d = irq_domain_get_irq_data(domain, virq);
2649 if (d) {
2650 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
2651 struct rzg2l_pinctrl *pctrl = container_of(gc, struct rzg2l_pinctrl, gpio_chip);
2652 irq_hw_number_t hwirq = irqd_to_hwirq(d);
2653 unsigned long flags;
2654 unsigned int i;
2655
2656 for (i = 0; i < RZG2L_TINT_MAX_INTERRUPT; i++) {
2657 if (pctrl->hwirq[i] == hwirq) {
2658 rzg2l_gpio_irq_endisable(pctrl, hwirq, false);
2659 rzg2l_gpio_free(gc, hwirq);
2660 spin_lock_irqsave(&pctrl->bitmap_lock, flags);
2661 bitmap_release_region(pctrl->tint_slot, i, get_order(1));
2662 spin_unlock_irqrestore(&pctrl->bitmap_lock, flags);
2663 pctrl->hwirq[i] = 0;
2664 break;
2665 }
2666 }
2667 }
2668 irq_domain_free_irqs_common(domain, virq, nr_irqs);
2669 }
2670
rzg2l_init_irq_valid_mask(struct gpio_chip * gc,unsigned long * valid_mask,unsigned int ngpios)2671 static void rzg2l_init_irq_valid_mask(struct gpio_chip *gc,
2672 unsigned long *valid_mask,
2673 unsigned int ngpios)
2674 {
2675 struct rzg2l_pinctrl *pctrl = gpiochip_get_data(gc);
2676 struct gpio_chip *chip = &pctrl->gpio_chip;
2677 unsigned int offset;
2678
2679 /* Forbid unused lines to be mapped as IRQs */
2680 for (offset = 0; offset < chip->ngpio; offset++) {
2681 u32 port, bit;
2682
2683 port = offset / 8;
2684 bit = offset % 8;
2685
2686 if (port >= pctrl->data->n_ports ||
2687 bit >= hweight8(FIELD_GET(PIN_CFG_PIN_MAP_MASK,
2688 pctrl->data->port_pin_configs[port])))
2689 clear_bit(offset, valid_mask);
2690 }
2691 }
2692
rzg2l_pinctrl_reg_cache_alloc(struct rzg2l_pinctrl * pctrl)2693 static int rzg2l_pinctrl_reg_cache_alloc(struct rzg2l_pinctrl *pctrl)
2694 {
2695 u32 nports = pctrl->data->n_port_pins / RZG2L_PINS_PER_PORT;
2696 struct rzg2l_pinctrl_reg_cache *cache, *dedicated_cache;
2697
2698 cache = devm_kzalloc(pctrl->dev, sizeof(*cache), GFP_KERNEL);
2699 if (!cache)
2700 return -ENOMEM;
2701
2702 dedicated_cache = devm_kzalloc(pctrl->dev, sizeof(*dedicated_cache), GFP_KERNEL);
2703 if (!dedicated_cache)
2704 return -ENOMEM;
2705
2706 cache->p = devm_kcalloc(pctrl->dev, nports, sizeof(*cache->p), GFP_KERNEL);
2707 if (!cache->p)
2708 return -ENOMEM;
2709
2710 cache->pm = devm_kcalloc(pctrl->dev, nports, sizeof(*cache->pm), GFP_KERNEL);
2711 if (!cache->pm)
2712 return -ENOMEM;
2713
2714 cache->pmc = devm_kcalloc(pctrl->dev, nports, sizeof(*cache->pmc), GFP_KERNEL);
2715 if (!cache->pmc)
2716 return -ENOMEM;
2717
2718 cache->pfc = devm_kcalloc(pctrl->dev, nports, sizeof(*cache->pfc), GFP_KERNEL);
2719 if (!cache->pfc)
2720 return -ENOMEM;
2721
2722 for (u8 i = 0; i < 2; i++) {
2723 u32 n_dedicated_pins = pctrl->data->n_dedicated_pins;
2724
2725 cache->iolh[i] = devm_kcalloc(pctrl->dev, nports, sizeof(*cache->iolh[i]),
2726 GFP_KERNEL);
2727 if (!cache->iolh[i])
2728 return -ENOMEM;
2729
2730 cache->ien[i] = devm_kcalloc(pctrl->dev, nports, sizeof(*cache->ien[i]),
2731 GFP_KERNEL);
2732 if (!cache->ien[i])
2733 return -ENOMEM;
2734
2735 cache->pupd[i] = devm_kcalloc(pctrl->dev, nports, sizeof(*cache->pupd[i]),
2736 GFP_KERNEL);
2737 if (!cache->pupd[i])
2738 return -ENOMEM;
2739
2740 /* Allocate dedicated cache. */
2741 dedicated_cache->iolh[i] = devm_kcalloc(pctrl->dev, n_dedicated_pins,
2742 sizeof(*dedicated_cache->iolh[i]),
2743 GFP_KERNEL);
2744 if (!dedicated_cache->iolh[i])
2745 return -ENOMEM;
2746
2747 dedicated_cache->ien[i] = devm_kcalloc(pctrl->dev, n_dedicated_pins,
2748 sizeof(*dedicated_cache->ien[i]),
2749 GFP_KERNEL);
2750 if (!dedicated_cache->ien[i])
2751 return -ENOMEM;
2752 }
2753
2754 pctrl->cache = cache;
2755 pctrl->dedicated_cache = dedicated_cache;
2756
2757 return 0;
2758 }
2759
rzg2l_gpio_register(struct rzg2l_pinctrl * pctrl)2760 static int rzg2l_gpio_register(struct rzg2l_pinctrl *pctrl)
2761 {
2762 struct device_node *np = pctrl->dev->of_node;
2763 struct gpio_chip *chip = &pctrl->gpio_chip;
2764 const char *name = dev_name(pctrl->dev);
2765 struct irq_domain *parent_domain;
2766 struct of_phandle_args of_args;
2767 struct device_node *parent_np;
2768 struct gpio_irq_chip *girq;
2769 int ret;
2770
2771 parent_np = of_irq_find_parent(np);
2772 if (!parent_np)
2773 return -ENXIO;
2774
2775 parent_domain = irq_find_host(parent_np);
2776 of_node_put(parent_np);
2777 if (!parent_domain)
2778 return -EPROBE_DEFER;
2779
2780 ret = of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 0, &of_args);
2781 if (ret)
2782 return dev_err_probe(pctrl->dev, ret, "Unable to parse gpio-ranges\n");
2783
2784 of_node_put(of_args.np);
2785
2786 if (of_args.args[0] != 0 || of_args.args[1] != 0 ||
2787 of_args.args[2] != pctrl->data->n_port_pins)
2788 return dev_err_probe(pctrl->dev, -EINVAL,
2789 "gpio-ranges does not match selected SOC\n");
2790
2791 chip->names = pctrl->data->port_pins;
2792 chip->request = rzg2l_gpio_request;
2793 chip->free = rzg2l_gpio_free;
2794 chip->get_direction = rzg2l_gpio_get_direction;
2795 chip->direction_input = rzg2l_gpio_direction_input;
2796 chip->direction_output = rzg2l_gpio_direction_output;
2797 chip->get = rzg2l_gpio_get;
2798 chip->set_rv = rzg2l_gpio_set;
2799 chip->label = name;
2800 chip->parent = pctrl->dev;
2801 chip->owner = THIS_MODULE;
2802 chip->base = -1;
2803 chip->ngpio = of_args.args[2];
2804
2805 girq = &chip->irq;
2806 gpio_irq_chip_set_chip(girq, &rzg2l_gpio_irqchip);
2807 girq->fwnode = dev_fwnode(pctrl->dev);
2808 girq->parent_domain = parent_domain;
2809 girq->child_to_parent_hwirq = rzg2l_gpio_child_to_parent_hwirq;
2810 girq->populate_parent_alloc_arg = gpiochip_populate_parent_fwspec_twocell;
2811 girq->child_irq_domain_ops.free = rzg2l_gpio_irq_domain_free;
2812 girq->init_valid_mask = rzg2l_init_irq_valid_mask;
2813
2814 pctrl->gpio_range.id = 0;
2815 pctrl->gpio_range.pin_base = 0;
2816 pctrl->gpio_range.base = 0;
2817 pctrl->gpio_range.npins = chip->ngpio;
2818 pctrl->gpio_range.name = chip->label;
2819 pctrl->gpio_range.gc = chip;
2820 ret = devm_gpiochip_add_data(pctrl->dev, chip, pctrl);
2821 if (ret)
2822 return dev_err_probe(pctrl->dev, ret, "failed to add GPIO controller\n");
2823
2824 dev_dbg(pctrl->dev, "Registered gpio controller\n");
2825
2826 return 0;
2827 }
2828
rzg2l_pinctrl_register(struct rzg2l_pinctrl * pctrl)2829 static int rzg2l_pinctrl_register(struct rzg2l_pinctrl *pctrl)
2830 {
2831 const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg;
2832 struct pinctrl_pin_desc *pins;
2833 unsigned int i, j;
2834 u64 *pin_data;
2835 int ret;
2836
2837 pctrl->desc.name = DRV_NAME;
2838 pctrl->desc.npins = pctrl->data->n_port_pins + pctrl->data->n_dedicated_pins;
2839 pctrl->desc.pctlops = &rzg2l_pinctrl_pctlops;
2840 pctrl->desc.pmxops = &rzg2l_pinctrl_pmxops;
2841 pctrl->desc.confops = &rzg2l_pinctrl_confops;
2842 pctrl->desc.owner = THIS_MODULE;
2843 if (pctrl->data->num_custom_params) {
2844 pctrl->desc.num_custom_params = pctrl->data->num_custom_params;
2845 pctrl->desc.custom_params = pctrl->data->custom_params;
2846 #ifdef CONFIG_DEBUG_FS
2847 pctrl->desc.custom_conf_items = pctrl->data->custom_conf_items;
2848 #endif
2849 }
2850
2851 pins = devm_kcalloc(pctrl->dev, pctrl->desc.npins, sizeof(*pins), GFP_KERNEL);
2852 if (!pins)
2853 return -ENOMEM;
2854
2855 pin_data = devm_kcalloc(pctrl->dev, pctrl->desc.npins,
2856 sizeof(*pin_data), GFP_KERNEL);
2857 if (!pin_data)
2858 return -ENOMEM;
2859
2860 pctrl->pins = pins;
2861 pctrl->desc.pins = pins;
2862
2863 for (i = 0, j = 0; i < pctrl->data->n_port_pins; i++) {
2864 pins[i].number = i;
2865 pins[i].name = pctrl->data->port_pins[i];
2866 if (i && !(i % RZG2L_PINS_PER_PORT))
2867 j++;
2868 pin_data[i] = pctrl->data->port_pin_configs[j];
2869 if (pin_data[i] & RZG2L_VARIABLE_CFG)
2870 pin_data[i] = rzg2l_pinctrl_get_variable_pin_cfg(pctrl,
2871 pin_data[i],
2872 j,
2873 i % RZG2L_PINS_PER_PORT);
2874 pins[i].drv_data = &pin_data[i];
2875 }
2876
2877 for (i = 0; i < pctrl->data->n_dedicated_pins; i++) {
2878 unsigned int index = pctrl->data->n_port_pins + i;
2879
2880 pins[index].number = index;
2881 pins[index].name = pctrl->data->dedicated_pins[i].name;
2882 pin_data[index] = pctrl->data->dedicated_pins[i].config;
2883 pins[index].drv_data = &pin_data[index];
2884 }
2885
2886 pctrl->settings = devm_kcalloc(pctrl->dev, pctrl->desc.npins, sizeof(*pctrl->settings),
2887 GFP_KERNEL);
2888 if (!pctrl->settings)
2889 return -ENOMEM;
2890
2891 for (i = 0; hwcfg->drive_strength_ua && i < pctrl->desc.npins; i++) {
2892 if (pin_data[i] & PIN_CFG_SOFT_PS) {
2893 pctrl->settings[i].power_source = 3300;
2894 } else {
2895 ret = rzg2l_get_power_source(pctrl, i, pin_data[i]);
2896 if (ret < 0)
2897 continue;
2898 pctrl->settings[i].power_source = ret;
2899 }
2900 }
2901
2902 ret = rzg2l_pinctrl_reg_cache_alloc(pctrl);
2903 if (ret)
2904 return ret;
2905
2906 ret = devm_pinctrl_register_and_init(pctrl->dev, &pctrl->desc, pctrl,
2907 &pctrl->pctl);
2908 if (ret)
2909 return dev_err_probe(pctrl->dev, ret, "pinctrl registration failed\n");
2910
2911 ret = pinctrl_enable(pctrl->pctl);
2912 if (ret)
2913 return dev_err_probe(pctrl->dev, ret, "pinctrl enable failed\n");
2914
2915 ret = rzg2l_gpio_register(pctrl);
2916 if (ret)
2917 return dev_err_probe(pctrl->dev, ret, "failed to add GPIO chip\n");
2918
2919 return 0;
2920 }
2921
rzg2l_pinctrl_probe(struct platform_device * pdev)2922 static int rzg2l_pinctrl_probe(struct platform_device *pdev)
2923 {
2924 struct rzg2l_pinctrl *pctrl;
2925 int ret;
2926
2927 BUILD_BUG_ON(ARRAY_SIZE(r9a07g044_gpio_configs) * RZG2L_PINS_PER_PORT >
2928 ARRAY_SIZE(rzg2l_gpio_names));
2929
2930 BUILD_BUG_ON(ARRAY_SIZE(r9a07g043_gpio_configs) * RZG2L_PINS_PER_PORT >
2931 ARRAY_SIZE(rzg2l_gpio_names));
2932
2933 BUILD_BUG_ON(ARRAY_SIZE(r9a08g045_gpio_configs) * RZG2L_PINS_PER_PORT >
2934 ARRAY_SIZE(rzg2l_gpio_names));
2935
2936 BUILD_BUG_ON(ARRAY_SIZE(r9a09g047_gpio_configs) * RZG2L_PINS_PER_PORT >
2937 ARRAY_SIZE(rzg3e_gpio_names));
2938
2939 BUILD_BUG_ON(ARRAY_SIZE(r9a09g057_gpio_configs) * RZG2L_PINS_PER_PORT >
2940 ARRAY_SIZE(rzv2h_gpio_names));
2941
2942 pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);
2943 if (!pctrl)
2944 return -ENOMEM;
2945
2946 pctrl->dev = &pdev->dev;
2947
2948 pctrl->data = of_device_get_match_data(&pdev->dev);
2949 if (!pctrl->data)
2950 return -EINVAL;
2951
2952 pctrl->base = devm_platform_ioremap_resource(pdev, 0);
2953 if (IS_ERR(pctrl->base))
2954 return PTR_ERR(pctrl->base);
2955
2956 pctrl->clk = devm_clk_get_enabled(pctrl->dev, NULL);
2957 if (IS_ERR(pctrl->clk)) {
2958 return dev_err_probe(pctrl->dev, PTR_ERR(pctrl->clk),
2959 "failed to enable GPIO clk\n");
2960 }
2961
2962 spin_lock_init(&pctrl->lock);
2963 spin_lock_init(&pctrl->bitmap_lock);
2964 mutex_init(&pctrl->mutex);
2965 atomic_set(&pctrl->wakeup_path, 0);
2966
2967 platform_set_drvdata(pdev, pctrl);
2968
2969 ret = rzg2l_pinctrl_register(pctrl);
2970 if (ret)
2971 return ret;
2972
2973 dev_info(pctrl->dev, "%s support registered\n", DRV_NAME);
2974 return 0;
2975 }
2976
rzg2l_pinctrl_pm_setup_regs(struct rzg2l_pinctrl * pctrl,bool suspend)2977 static void rzg2l_pinctrl_pm_setup_regs(struct rzg2l_pinctrl *pctrl, bool suspend)
2978 {
2979 u32 nports = pctrl->data->n_port_pins / RZG2L_PINS_PER_PORT;
2980 struct rzg2l_pinctrl_reg_cache *cache = pctrl->cache;
2981
2982 for (u32 port = 0; port < nports; port++) {
2983 bool has_iolh, has_ien, has_pupd;
2984 u32 off, caps;
2985 u8 pincnt;
2986 u64 cfg;
2987
2988 cfg = pctrl->data->port_pin_configs[port];
2989 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(cfg);
2990 pincnt = hweight8(FIELD_GET(PIN_CFG_PIN_MAP_MASK, cfg));
2991
2992 caps = FIELD_GET(PIN_CFG_MASK, cfg);
2993 has_iolh = !!(caps & (PIN_CFG_IOLH_A | PIN_CFG_IOLH_B | PIN_CFG_IOLH_C));
2994 has_ien = !!(caps & PIN_CFG_IEN);
2995 has_pupd = !!(caps & PIN_CFG_PUPD);
2996
2997 if (suspend)
2998 RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + PFC(off), cache->pfc[port]);
2999
3000 /*
3001 * Now cache the registers or set them in the order suggested by
3002 * HW manual (section "Operation for GPIO Function").
3003 */
3004 RZG2L_PCTRL_REG_ACCESS8(suspend, pctrl->base + PMC(off), cache->pmc[port]);
3005 if (has_iolh) {
3006 RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + IOLH(off),
3007 cache->iolh[0][port]);
3008 if (pincnt >= 4) {
3009 RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + IOLH(off) + 4,
3010 cache->iolh[1][port]);
3011 }
3012 }
3013
3014 if (has_pupd) {
3015 RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + PUPD(off),
3016 cache->pupd[0][port]);
3017 if (pincnt >= 4) {
3018 RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + PUPD(off),
3019 cache->pupd[1][port]);
3020 }
3021 }
3022
3023 RZG2L_PCTRL_REG_ACCESS16(suspend, pctrl->base + PM(off), cache->pm[port]);
3024 RZG2L_PCTRL_REG_ACCESS8(suspend, pctrl->base + P(off), cache->p[port]);
3025
3026 if (has_ien) {
3027 RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + IEN(off),
3028 cache->ien[0][port]);
3029 if (pincnt >= 4) {
3030 RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + IEN(off) + 4,
3031 cache->ien[1][port]);
3032 }
3033 }
3034 }
3035 }
3036
rzg2l_pinctrl_pm_setup_dedicated_regs(struct rzg2l_pinctrl * pctrl,bool suspend)3037 static void rzg2l_pinctrl_pm_setup_dedicated_regs(struct rzg2l_pinctrl *pctrl, bool suspend)
3038 {
3039 struct rzg2l_pinctrl_reg_cache *cache = pctrl->dedicated_cache;
3040 u32 caps;
3041 u32 i;
3042
3043 /*
3044 * Make sure entries in pctrl->data->n_dedicated_pins[] having the same
3045 * port offset are close together.
3046 */
3047 for (i = 0, caps = 0; i < pctrl->data->n_dedicated_pins; i++) {
3048 bool has_iolh, has_ien;
3049 u32 off, next_off = 0;
3050 u64 cfg, next_cfg;
3051 u8 pincnt;
3052
3053 cfg = pctrl->data->dedicated_pins[i].config;
3054 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(cfg);
3055 if (i + 1 < pctrl->data->n_dedicated_pins) {
3056 next_cfg = pctrl->data->dedicated_pins[i + 1].config;
3057 next_off = RZG2L_PIN_CFG_TO_PORT_OFFSET(next_cfg);
3058 }
3059
3060 if (off == next_off) {
3061 /* Gather caps of all port pins. */
3062 caps |= FIELD_GET(PIN_CFG_MASK, cfg);
3063 continue;
3064 }
3065
3066 /* And apply them in a single shot. */
3067 has_iolh = !!(caps & (PIN_CFG_IOLH_A | PIN_CFG_IOLH_B | PIN_CFG_IOLH_C));
3068 has_ien = !!(caps & PIN_CFG_IEN);
3069 pincnt = hweight8(FIELD_GET(RZG2L_SINGLE_PIN_BITS_MASK, cfg));
3070
3071 if (has_iolh) {
3072 RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + IOLH(off),
3073 cache->iolh[0][i]);
3074 }
3075 if (has_ien) {
3076 RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + IEN(off),
3077 cache->ien[0][i]);
3078 }
3079
3080 if (pincnt >= 4) {
3081 if (has_iolh) {
3082 RZG2L_PCTRL_REG_ACCESS32(suspend,
3083 pctrl->base + IOLH(off) + 4,
3084 cache->iolh[1][i]);
3085 }
3086 if (has_ien) {
3087 RZG2L_PCTRL_REG_ACCESS32(suspend,
3088 pctrl->base + IEN(off) + 4,
3089 cache->ien[1][i]);
3090 }
3091 }
3092 caps = 0;
3093 }
3094 }
3095
rzg2l_pinctrl_pm_setup_pfc(struct rzg2l_pinctrl * pctrl)3096 static void rzg2l_pinctrl_pm_setup_pfc(struct rzg2l_pinctrl *pctrl)
3097 {
3098 u32 nports = pctrl->data->n_port_pins / RZG2L_PINS_PER_PORT;
3099 unsigned long flags;
3100
3101 spin_lock_irqsave(&pctrl->lock, flags);
3102 pctrl->data->pwpr_pfc_lock_unlock(pctrl, false);
3103
3104 /* Restore port registers. */
3105 for (u32 port = 0; port < nports; port++) {
3106 unsigned long pinmap;
3107 u8 pmc = 0, max_pin;
3108 u32 off, pfc = 0;
3109 u64 cfg;
3110 u16 pm;
3111 u8 pin;
3112
3113 cfg = pctrl->data->port_pin_configs[port];
3114 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(cfg);
3115 pinmap = FIELD_GET(PIN_CFG_PIN_MAP_MASK, cfg);
3116 max_pin = fls(pinmap);
3117
3118 pm = readw(pctrl->base + PM(off));
3119 for_each_set_bit(pin, &pinmap, max_pin) {
3120 struct rzg2l_pinctrl_reg_cache *cache = pctrl->cache;
3121
3122 /* Nothing to do if PFC was not configured before. */
3123 if (!(cache->pmc[port] & BIT(pin)))
3124 continue;
3125
3126 /* Set pin to 'Non-use (Hi-Z input protection)' */
3127 pm &= ~(PM_MASK << (pin * 2));
3128 writew(pm, pctrl->base + PM(off));
3129
3130 /* Temporarily switch to GPIO mode with PMC register */
3131 pmc &= ~BIT(pin);
3132 writeb(pmc, pctrl->base + PMC(off));
3133
3134 /* Select Pin function mode. */
3135 pfc &= ~(PFC_MASK << (pin * 4));
3136 pfc |= (cache->pfc[port] & (PFC_MASK << (pin * 4)));
3137 writel(pfc, pctrl->base + PFC(off));
3138
3139 /* Switch to Peripheral pin function. */
3140 pmc |= BIT(pin);
3141 writeb(pmc, pctrl->base + PMC(off));
3142 }
3143 }
3144
3145 pctrl->data->pwpr_pfc_lock_unlock(pctrl, true);
3146 spin_unlock_irqrestore(&pctrl->lock, flags);
3147 }
3148
rzg2l_pinctrl_suspend_noirq(struct device * dev)3149 static int rzg2l_pinctrl_suspend_noirq(struct device *dev)
3150 {
3151 struct rzg2l_pinctrl *pctrl = dev_get_drvdata(dev);
3152 const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg;
3153 const struct rzg2l_register_offsets *regs = &hwcfg->regs;
3154 struct rzg2l_pinctrl_reg_cache *cache = pctrl->cache;
3155
3156 rzg2l_pinctrl_pm_setup_regs(pctrl, true);
3157 rzg2l_pinctrl_pm_setup_dedicated_regs(pctrl, true);
3158
3159 for (u8 i = 0; i < 2; i++) {
3160 if (regs->sd_ch)
3161 cache->sd_ch[i] = readb(pctrl->base + SD_CH(regs->sd_ch, i));
3162 if (regs->eth_poc)
3163 cache->eth_poc[i] = readb(pctrl->base + ETH_POC(regs->eth_poc, i));
3164 }
3165
3166 cache->qspi = readb(pctrl->base + QSPI);
3167 cache->eth_mode = readb(pctrl->base + ETH_MODE);
3168
3169 if (!atomic_read(&pctrl->wakeup_path))
3170 clk_disable_unprepare(pctrl->clk);
3171 else
3172 device_set_wakeup_path(dev);
3173
3174 return 0;
3175 }
3176
rzg2l_pinctrl_resume_noirq(struct device * dev)3177 static int rzg2l_pinctrl_resume_noirq(struct device *dev)
3178 {
3179 struct rzg2l_pinctrl *pctrl = dev_get_drvdata(dev);
3180 const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg;
3181 const struct rzg2l_register_offsets *regs = &hwcfg->regs;
3182 struct rzg2l_pinctrl_reg_cache *cache = pctrl->cache;
3183 int ret;
3184
3185 if (!atomic_read(&pctrl->wakeup_path)) {
3186 ret = clk_prepare_enable(pctrl->clk);
3187 if (ret)
3188 return ret;
3189 }
3190
3191 writeb(cache->qspi, pctrl->base + QSPI);
3192 writeb(cache->eth_mode, pctrl->base + ETH_MODE);
3193 for (u8 i = 0; i < 2; i++) {
3194 if (regs->sd_ch)
3195 writeb(cache->sd_ch[i], pctrl->base + SD_CH(regs->sd_ch, i));
3196 if (regs->eth_poc)
3197 writeb(cache->eth_poc[i], pctrl->base + ETH_POC(regs->eth_poc, i));
3198 }
3199
3200 rzg2l_pinctrl_pm_setup_pfc(pctrl);
3201 rzg2l_pinctrl_pm_setup_regs(pctrl, false);
3202 rzg2l_pinctrl_pm_setup_dedicated_regs(pctrl, false);
3203 rzg2l_gpio_irq_restore(pctrl);
3204
3205 return 0;
3206 }
3207
rzg2l_pwpr_pfc_lock_unlock(struct rzg2l_pinctrl * pctrl,bool lock)3208 static void rzg2l_pwpr_pfc_lock_unlock(struct rzg2l_pinctrl *pctrl, bool lock)
3209 {
3210 const struct rzg2l_register_offsets *regs = &pctrl->data->hwcfg->regs;
3211
3212 if (lock) {
3213 /* Set the PWPR register to be write-protected */
3214 writel(0x0, pctrl->base + regs->pwpr); /* B0WI=0, PFCWE=0 */
3215 writel(PWPR_B0WI, pctrl->base + regs->pwpr); /* B0WI=1, PFCWE=0 */
3216 } else {
3217 /* Set the PWPR register to allow PFC register to write */
3218 writel(0x0, pctrl->base + regs->pwpr); /* B0WI=0, PFCWE=0 */
3219 writel(PWPR_PFCWE, pctrl->base + regs->pwpr); /* B0WI=0, PFCWE=1 */
3220 }
3221 }
3222
rzv2h_pwpr_pfc_lock_unlock(struct rzg2l_pinctrl * pctrl,bool lock)3223 static void rzv2h_pwpr_pfc_lock_unlock(struct rzg2l_pinctrl *pctrl, bool lock)
3224 {
3225 const struct rzg2l_register_offsets *regs = &pctrl->data->hwcfg->regs;
3226 u8 pwpr;
3227
3228 if (lock) {
3229 /* Set the PWPR register to be write-protected */
3230 pwpr = readb(pctrl->base + regs->pwpr);
3231 writeb(pwpr & ~PWPR_REGWE_A, pctrl->base + regs->pwpr);
3232 } else {
3233 /* Set the PWPR register to allow PFC and PMC register to write */
3234 pwpr = readb(pctrl->base + regs->pwpr);
3235 writeb(PWPR_REGWE_A | pwpr, pctrl->base + regs->pwpr);
3236 }
3237 }
3238
3239 static const struct rzg2l_hwcfg rzg2l_hwcfg = {
3240 .regs = {
3241 .pwpr = 0x3014,
3242 .sd_ch = 0x3000,
3243 .eth_poc = 0x300c,
3244 },
3245 .iolh_groupa_ua = {
3246 /* 3v3 power source */
3247 [RZG2L_IOLH_IDX_3V3] = 2000, 4000, 8000, 12000,
3248 },
3249 .iolh_groupb_oi = { 100, 66, 50, 33, },
3250 .tint_start_index = 9,
3251 .oen_max_pin = 0,
3252 };
3253
3254 static const struct rzg2l_hwcfg rzg3s_hwcfg = {
3255 .regs = {
3256 .pwpr = 0x3000,
3257 .sd_ch = 0x3004,
3258 .eth_poc = 0x3010,
3259 },
3260 .iolh_groupa_ua = {
3261 /* 1v8 power source */
3262 [RZG2L_IOLH_IDX_1V8] = 2200, 4400, 9000, 10000,
3263 /* 3v3 power source */
3264 [RZG2L_IOLH_IDX_3V3] = 1900, 4000, 8000, 9000,
3265 },
3266 .iolh_groupb_ua = {
3267 /* 1v8 power source */
3268 [RZG2L_IOLH_IDX_1V8] = 7000, 8000, 9000, 10000,
3269 /* 3v3 power source */
3270 [RZG2L_IOLH_IDX_3V3] = 4000, 6000, 8000, 9000,
3271 },
3272 .iolh_groupc_ua = {
3273 /* 1v8 power source */
3274 [RZG2L_IOLH_IDX_1V8] = 5200, 6000, 6550, 6800,
3275 /* 2v5 source */
3276 [RZG2L_IOLH_IDX_2V5] = 4700, 5300, 5800, 6100,
3277 /* 3v3 power source */
3278 [RZG2L_IOLH_IDX_3V3] = 4500, 5200, 5700, 6050,
3279 },
3280 .tint_start_index = 9,
3281 .drive_strength_ua = true,
3282 .func_base = 1,
3283 .oen_max_pin = 1, /* Pin 1 of P0 and P7 is the maximum OEN pin. */
3284 .oen_max_port = 7, /* P7_1 is the maximum OEN port. */
3285 };
3286
3287 static const struct rzg2l_hwcfg rzv2h_hwcfg = {
3288 .regs = {
3289 .pwpr = 0x3c04,
3290 },
3291 .tint_start_index = 17,
3292 };
3293
3294 static struct rzg2l_pinctrl_data r9a07g043_data = {
3295 .port_pins = rzg2l_gpio_names,
3296 .port_pin_configs = r9a07g043_gpio_configs,
3297 .n_ports = ARRAY_SIZE(r9a07g043_gpio_configs),
3298 .dedicated_pins = rzg2l_dedicated_pins.common,
3299 .n_port_pins = ARRAY_SIZE(r9a07g043_gpio_configs) * RZG2L_PINS_PER_PORT,
3300 .n_dedicated_pins = ARRAY_SIZE(rzg2l_dedicated_pins.common),
3301 .hwcfg = &rzg2l_hwcfg,
3302 #ifdef CONFIG_RISCV
3303 .variable_pin_cfg = r9a07g043f_variable_pin_cfg,
3304 .n_variable_pin_cfg = ARRAY_SIZE(r9a07g043f_variable_pin_cfg),
3305 #endif
3306 .pwpr_pfc_lock_unlock = &rzg2l_pwpr_pfc_lock_unlock,
3307 .pmc_writeb = &rzg2l_pmc_writeb,
3308 .oen_read = &rzg2l_read_oen,
3309 .oen_write = &rzg2l_write_oen,
3310 .hw_to_bias_param = &rzg2l_hw_to_bias_param,
3311 .bias_param_to_hw = &rzg2l_bias_param_to_hw,
3312 };
3313
3314 static struct rzg2l_pinctrl_data r9a07g044_data = {
3315 .port_pins = rzg2l_gpio_names,
3316 .port_pin_configs = r9a07g044_gpio_configs,
3317 .n_ports = ARRAY_SIZE(r9a07g044_gpio_configs),
3318 .dedicated_pins = rzg2l_dedicated_pins.common,
3319 .n_port_pins = ARRAY_SIZE(r9a07g044_gpio_configs) * RZG2L_PINS_PER_PORT,
3320 .n_dedicated_pins = ARRAY_SIZE(rzg2l_dedicated_pins.common) +
3321 ARRAY_SIZE(rzg2l_dedicated_pins.rzg2l_pins),
3322 .hwcfg = &rzg2l_hwcfg,
3323 .pwpr_pfc_lock_unlock = &rzg2l_pwpr_pfc_lock_unlock,
3324 .pmc_writeb = &rzg2l_pmc_writeb,
3325 .oen_read = &rzg2l_read_oen,
3326 .oen_write = &rzg2l_write_oen,
3327 .hw_to_bias_param = &rzg2l_hw_to_bias_param,
3328 .bias_param_to_hw = &rzg2l_bias_param_to_hw,
3329 };
3330
3331 static struct rzg2l_pinctrl_data r9a08g045_data = {
3332 .port_pins = rzg2l_gpio_names,
3333 .port_pin_configs = r9a08g045_gpio_configs,
3334 .n_ports = ARRAY_SIZE(r9a08g045_gpio_configs),
3335 .dedicated_pins = rzg3s_dedicated_pins,
3336 .n_port_pins = ARRAY_SIZE(r9a08g045_gpio_configs) * RZG2L_PINS_PER_PORT,
3337 .n_dedicated_pins = ARRAY_SIZE(rzg3s_dedicated_pins),
3338 .hwcfg = &rzg3s_hwcfg,
3339 .pwpr_pfc_lock_unlock = &rzg2l_pwpr_pfc_lock_unlock,
3340 .pmc_writeb = &rzg2l_pmc_writeb,
3341 .oen_read = &rzg3s_oen_read,
3342 .oen_write = &rzg3s_oen_write,
3343 .hw_to_bias_param = &rzg2l_hw_to_bias_param,
3344 .bias_param_to_hw = &rzg2l_bias_param_to_hw,
3345 };
3346
3347 static struct rzg2l_pinctrl_data r9a09g047_data = {
3348 .port_pins = rzg3e_gpio_names,
3349 .port_pin_configs = r9a09g047_gpio_configs,
3350 .n_ports = ARRAY_SIZE(r9a09g047_gpio_configs),
3351 .dedicated_pins = rzg3e_dedicated_pins,
3352 .n_port_pins = ARRAY_SIZE(r9a09g047_gpio_configs) * RZG2L_PINS_PER_PORT,
3353 .n_dedicated_pins = ARRAY_SIZE(rzg3e_dedicated_pins),
3354 .hwcfg = &rzv2h_hwcfg,
3355 .variable_pin_cfg = r9a09g047_variable_pin_cfg,
3356 .n_variable_pin_cfg = ARRAY_SIZE(r9a09g047_variable_pin_cfg),
3357 .num_custom_params = ARRAY_SIZE(renesas_rzv2h_custom_bindings),
3358 .custom_params = renesas_rzv2h_custom_bindings,
3359 #ifdef CONFIG_DEBUG_FS
3360 .custom_conf_items = renesas_rzv2h_conf_items,
3361 #endif
3362 .pwpr_pfc_lock_unlock = &rzv2h_pwpr_pfc_lock_unlock,
3363 .pmc_writeb = &rzv2h_pmc_writeb,
3364 .oen_read = &rzv2h_oen_read,
3365 .oen_write = &rzv2h_oen_write,
3366 .hw_to_bias_param = &rzv2h_hw_to_bias_param,
3367 .bias_param_to_hw = &rzv2h_bias_param_to_hw,
3368 };
3369
3370 static struct rzg2l_pinctrl_data r9a09g056_data = {
3371 .port_pins = rzv2h_gpio_names,
3372 .port_pin_configs = r9a09g057_gpio_configs,
3373 .n_ports = ARRAY_SIZE(r9a09g057_gpio_configs),
3374 .dedicated_pins = rzv2h_dedicated_pins.common,
3375 .n_port_pins = ARRAY_SIZE(r9a09g057_gpio_configs) * RZG2L_PINS_PER_PORT,
3376 .n_dedicated_pins = ARRAY_SIZE(rzv2h_dedicated_pins.common),
3377 .hwcfg = &rzv2h_hwcfg,
3378 .variable_pin_cfg = r9a09g057_variable_pin_cfg,
3379 .n_variable_pin_cfg = ARRAY_SIZE(r9a09g057_variable_pin_cfg),
3380 .num_custom_params = ARRAY_SIZE(renesas_rzv2h_custom_bindings),
3381 .custom_params = renesas_rzv2h_custom_bindings,
3382 #ifdef CONFIG_DEBUG_FS
3383 .custom_conf_items = renesas_rzv2h_conf_items,
3384 #endif
3385 .pwpr_pfc_lock_unlock = &rzv2h_pwpr_pfc_lock_unlock,
3386 .pmc_writeb = &rzv2h_pmc_writeb,
3387 .oen_read = &rzv2h_oen_read,
3388 .oen_write = &rzv2h_oen_write,
3389 .hw_to_bias_param = &rzv2h_hw_to_bias_param,
3390 .bias_param_to_hw = &rzv2h_bias_param_to_hw,
3391 };
3392
3393 static struct rzg2l_pinctrl_data r9a09g057_data = {
3394 .port_pins = rzv2h_gpio_names,
3395 .port_pin_configs = r9a09g057_gpio_configs,
3396 .n_ports = ARRAY_SIZE(r9a09g057_gpio_configs),
3397 .dedicated_pins = rzv2h_dedicated_pins.common,
3398 .n_port_pins = ARRAY_SIZE(r9a09g057_gpio_configs) * RZG2L_PINS_PER_PORT,
3399 .n_dedicated_pins = ARRAY_SIZE(rzv2h_dedicated_pins.common) +
3400 ARRAY_SIZE(rzv2h_dedicated_pins.pcie1),
3401 .hwcfg = &rzv2h_hwcfg,
3402 .variable_pin_cfg = r9a09g057_variable_pin_cfg,
3403 .n_variable_pin_cfg = ARRAY_SIZE(r9a09g057_variable_pin_cfg),
3404 .num_custom_params = ARRAY_SIZE(renesas_rzv2h_custom_bindings),
3405 .custom_params = renesas_rzv2h_custom_bindings,
3406 #ifdef CONFIG_DEBUG_FS
3407 .custom_conf_items = renesas_rzv2h_conf_items,
3408 #endif
3409 .pwpr_pfc_lock_unlock = &rzv2h_pwpr_pfc_lock_unlock,
3410 .pmc_writeb = &rzv2h_pmc_writeb,
3411 .oen_read = &rzv2h_oen_read,
3412 .oen_write = &rzv2h_oen_write,
3413 .hw_to_bias_param = &rzv2h_hw_to_bias_param,
3414 .bias_param_to_hw = &rzv2h_bias_param_to_hw,
3415 };
3416
3417 static const struct of_device_id rzg2l_pinctrl_of_table[] = {
3418 {
3419 .compatible = "renesas,r9a07g043-pinctrl",
3420 .data = &r9a07g043_data,
3421 },
3422 {
3423 .compatible = "renesas,r9a07g044-pinctrl",
3424 .data = &r9a07g044_data,
3425 },
3426 {
3427 .compatible = "renesas,r9a08g045-pinctrl",
3428 .data = &r9a08g045_data,
3429 },
3430 {
3431 .compatible = "renesas,r9a09g047-pinctrl",
3432 .data = &r9a09g047_data,
3433 },
3434 {
3435 .compatible = "renesas,r9a09g056-pinctrl",
3436 .data = &r9a09g056_data,
3437 },
3438 {
3439 .compatible = "renesas,r9a09g057-pinctrl",
3440 .data = &r9a09g057_data,
3441 },
3442 { /* sentinel */ }
3443 };
3444
3445 static const struct dev_pm_ops rzg2l_pinctrl_pm_ops = {
3446 NOIRQ_SYSTEM_SLEEP_PM_OPS(rzg2l_pinctrl_suspend_noirq, rzg2l_pinctrl_resume_noirq)
3447 };
3448
3449 static struct platform_driver rzg2l_pinctrl_driver = {
3450 .driver = {
3451 .name = DRV_NAME,
3452 .of_match_table = of_match_ptr(rzg2l_pinctrl_of_table),
3453 .pm = pm_sleep_ptr(&rzg2l_pinctrl_pm_ops),
3454 .suppress_bind_attrs = true,
3455 },
3456 .probe = rzg2l_pinctrl_probe,
3457 };
3458
rzg2l_pinctrl_init(void)3459 static int __init rzg2l_pinctrl_init(void)
3460 {
3461 return platform_driver_register(&rzg2l_pinctrl_driver);
3462 }
3463 core_initcall(rzg2l_pinctrl_init);
3464
3465 MODULE_AUTHOR("Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>");
3466 MODULE_DESCRIPTION("Pin and gpio controller driver for RZ/G2L family");
3467