1 /* $NetBSD: uchcom.c,v 1.1 2007/09/03 17:57:37 tshiozak Exp $ */
2
3 /*-
4 * SPDX-License-Identifier: BSD-2-Clause
5 *
6 * Copyright (c) 2007, Takanori Watanabe
7 * All rights reserved.
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * SUCH DAMAGE.
29 */
30
31 /*
32 * Copyright (c) 2007 The NetBSD Foundation, Inc.
33 * All rights reserved.
34 *
35 * This code is derived from software contributed to The NetBSD Foundation
36 * by Takuya SHIOZAKI (tshiozak@netbsd.org).
37 *
38 * Redistribution and use in source and binary forms, with or without
39 * modification, are permitted provided that the following conditions
40 * are met:
41 * 1. Redistributions of source code must retain the above copyright
42 * notice, this list of conditions and the following disclaimer.
43 * 2. Redistributions in binary form must reproduce the above copyright
44 * notice, this list of conditions and the following disclaimer in the
45 * documentation and/or other materials provided with the distribution.
46 *
47 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
48 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
49 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
50 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
51 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
52 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
53 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
54 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
55 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
56 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
57 * POSSIBILITY OF SUCH DAMAGE.
58 */
59
60 /*
61 * Driver for WinChipHead CH9102/343/341/340.
62 */
63
64 #include <sys/stdint.h>
65 #include <sys/stddef.h>
66 #include <sys/param.h>
67 #include <sys/queue.h>
68 #include <sys/types.h>
69 #include <sys/systm.h>
70 #include <sys/kernel.h>
71 #include <sys/bus.h>
72 #include <sys/module.h>
73 #include <sys/lock.h>
74 #include <sys/mutex.h>
75 #include <sys/condvar.h>
76 #include <sys/sysctl.h>
77 #include <sys/sx.h>
78 #include <sys/unistd.h>
79 #include <sys/callout.h>
80 #include <sys/malloc.h>
81 #include <sys/priv.h>
82
83 #include <dev/usb/usb.h>
84 #include <dev/usb/usbdi.h>
85 #include <dev/usb/usbdi_util.h>
86 #include "usbdevs.h"
87
88 #define USB_DEBUG_VAR uchcom_debug
89 #include <dev/usb/usb_debug.h>
90 #include <dev/usb/usb_process.h>
91
92 #include <dev/usb/serial/usb_serial.h>
93
94 #ifdef USB_DEBUG
95 static int uchcom_debug = 0;
96
97 static SYSCTL_NODE(_hw_usb, OID_AUTO, uchcom, CTLFLAG_RW | CTLFLAG_MPSAFE, 0,
98 "USB uchcom");
99 SYSCTL_INT(_hw_usb_uchcom, OID_AUTO, debug, CTLFLAG_RWTUN,
100 &uchcom_debug, 0, "uchcom debug level");
101 #endif
102
103 #define UCHCOM_IFACE_INDEX 0
104 #define UCHCOM_CONFIG_INDEX 0
105 #define UCHCOM_SECOND_IFACE_INDEX 1
106
107 #define UCHCOM_REV_CH340 0x0250
108 #define UCHCOM_INPUT_BUF_SIZE 8
109
110 #define UCHCOM_REQ_GET_VERSION 0x5F
111 #define UCHCOM_REQ_READ_REG 0x95
112 #define UCHCOM_REQ_WRITE_REG 0x9A
113 #define UCHCOM_REQ_RESET 0xA1
114 #define UCHCOM_REQ_SET_DTRRTS 0xA4
115 #define UCHCOM_REQ_CH343_WRITE_REG 0xA8
116
117 #define UCHCOM_REG_STAT1 0x06
118 #define UCHCOM_REG_STAT2 0x07
119 #define UCHCOM_REG_BPS_PRE 0x12
120 #define UCHCOM_REG_BPS_DIV 0x13
121 #define UCHCOM_REG_BPS_MOD 0x14
122 #define UCHCOM_REG_BPS_PAD 0x0F
123 #define UCHCOM_REG_BREAK1 0x05
124 #define UCHCOM_REG_LCR1 0x18
125 #define UCHCOM_REG_LCR2 0x25
126
127 #define UCHCOM_VER_20 0x20
128 #define UCHCOM_VER_30 0x30
129
130 #define UCHCOM_BASE_UNKNOWN 0
131 #define UCHCOM_BPS_MOD_BASE 20000000
132 #define UCHCOM_BPS_MOD_BASE_OFS 1100
133
134 #define UCHCOM_DTR_MASK 0x20
135 #define UCHCOM_RTS_MASK 0x40
136
137 #define UCHCOM_BRK_MASK 0x01
138 #define UCHCOM_ABRK_MASK 0x10
139 #define UCHCOM_CH343_BRK_MASK 0x80
140
141 #define UCHCOM_LCR1_MASK 0xAF
142 #define UCHCOM_LCR2_MASK 0x07
143 #define UCHCOM_LCR1_RX 0x80
144 #define UCHCOM_LCR1_TX 0x40
145 #define UCHCOM_LCR1_PARENB 0x08
146 #define UCHCOM_LCR1_CS5 0x00
147 #define UCHCOM_LCR1_CS6 0x01
148 #define UCHCOM_LCR1_CS7 0x02
149 #define UCHCOM_LCR1_CS8 0x03
150 #define UCHCOM_LCR1_STOPB 0x04
151 #define UCHCOM_LCR1_PARODD 0x00
152 #define UCHCOM_LCR1_PAREVEN 0x10
153 #define UCHCOM_LCR2_PAREVEN 0x07
154 #define UCHCOM_LCR2_PARODD 0x06
155 #define UCHCOM_LCR2_PARMARK 0x05
156 #define UCHCOM_LCR2_PARSPACE 0x04
157
158 #define UCHCOM_INTR_STAT1 0x02
159 #define UCHCOM_INTR_STAT2 0x03
160 #define UCHCOM_INTR_LEAST 4
161
162 #define UCHCOM_T 0x08
163 #define UCHCOM_CL 0x04
164 #define UCHCOM_CH343_CT 0x80
165 #define UCHCOM_CT 0x90
166
167 #define UCHCOM_BULK_BUF_SIZE 1024 /* bytes */
168
169 #define TYPE_CH343 1
170
171 enum {
172 UCHCOM_BULK_DT_WR,
173 UCHCOM_BULK_DT_RD,
174 UCHCOM_N_TRANSFER,
175 };
176
177 struct uchcom_softc {
178 struct ucom_super_softc sc_super_ucom;
179 struct ucom_softc sc_ucom;
180
181 struct usb_xfer *sc_xfer[UCHCOM_N_TRANSFER];
182 struct usb_xfer *sc_intr_xfer; /* Interrupt endpoint */
183 struct usb_device *sc_udev;
184 struct mtx sc_mtx;
185
186 uint8_t sc_dtr; /* local copy */
187 uint8_t sc_rts; /* local copy */
188 uint8_t sc_version;
189 uint8_t sc_msr;
190 uint8_t sc_lsr; /* local status register */
191 uint8_t sc_chiptype; /* type of chip */
192 uint8_t sc_ctrl_iface_no;
193 uint8_t sc_iface_index;
194 };
195
196 static const STRUCT_USB_HOST_ID uchcom_devs[] = {
197 {USB_VPI(USB_VENDOR_WCH, USB_PRODUCT_WCH_CH341SER, 0)},
198 {USB_VPI(USB_VENDOR_WCH2, USB_PRODUCT_WCH2_CH341SER, 0)},
199 {USB_VPI(USB_VENDOR_WCH2, USB_PRODUCT_WCH2_CH341SER_2, 0)},
200 {USB_VPI(USB_VENDOR_WCH2, USB_PRODUCT_WCH2_CH341SER_3, 0)},
201 {USB_VPI(USB_VENDOR_WCH2, USB_PRODUCT_WCH2_CH343SER, 0)},
202 {USB_VPI(USB_VENDOR_WCH2, USB_PRODUCT_WCH2_CH9102SER, 0)},
203 };
204
205 /* protypes */
206
207 static void uchcom_free(struct ucom_softc *);
208 static int uchcom_pre_param(struct ucom_softc *, struct termios *);
209 static void uchcom_cfg_get_status(struct ucom_softc *, uint8_t *,
210 uint8_t *);
211 static void uchcom_cfg_open(struct ucom_softc *ucom);
212 static void uchcom_cfg_param(struct ucom_softc *, struct termios *);
213 static void uchcom_cfg_set_break(struct ucom_softc *, uint8_t);
214 static void uchcom_cfg_set_dtr(struct ucom_softc *, uint8_t);
215 static void uchcom_cfg_set_rts(struct ucom_softc *, uint8_t);
216 static void uchcom_start_read(struct ucom_softc *);
217 static void uchcom_start_write(struct ucom_softc *);
218 static void uchcom_stop_read(struct ucom_softc *);
219 static void uchcom_stop_write(struct ucom_softc *);
220 static void uchcom_update_version(struct uchcom_softc *);
221 static void uchcom_convert_status(struct uchcom_softc *, uint8_t);
222 static void uchcom_update_status(struct uchcom_softc *);
223 static void uchcom_set_dtr_rts(struct uchcom_softc *);
224 static void uchcom_calc_baudrate(struct uchcom_softc *, uint32_t, uint8_t *,
225 uint8_t *);
226 static void uchcom_set_baudrate(struct uchcom_softc *, uint32_t, uint16_t);
227 static void uchcom_poll(struct ucom_softc *ucom);
228
229 static device_probe_t uchcom_probe;
230 static device_attach_t uchcom_attach;
231 static device_detach_t uchcom_detach;
232 static void uchcom_free_softc(struct uchcom_softc *);
233
234 static usb_callback_t uchcom_intr_callback;
235 static usb_callback_t uchcom_write_callback;
236 static usb_callback_t uchcom_read_callback;
237
238 static const struct usb_config uchcom_config_data[UCHCOM_N_TRANSFER] = {
239 [UCHCOM_BULK_DT_WR] = {
240 .type = UE_BULK,
241 .endpoint = UE_ADDR_ANY,
242 .direction = UE_DIR_OUT,
243 .bufsize = UCHCOM_BULK_BUF_SIZE,
244 .flags = {.pipe_bof = 1,},
245 .callback = &uchcom_write_callback,
246 },
247
248 [UCHCOM_BULK_DT_RD] = {
249 .type = UE_BULK,
250 .endpoint = UE_ADDR_ANY,
251 .direction = UE_DIR_IN,
252 .bufsize = UCHCOM_BULK_BUF_SIZE,
253 .flags = {.pipe_bof = 1,.short_xfer_ok = 1,},
254 .callback = &uchcom_read_callback,
255 },
256 };
257
258 static const struct usb_config uchcom_intr_config_data[1] = {
259 [0] = {
260 .type = UE_INTERRUPT,
261 .endpoint = UE_ADDR_ANY,
262 .direction = UE_DIR_IN,
263 .flags = {.pipe_bof = 1,.short_xfer_ok = 1,},
264 .bufsize = 0, /* use wMaxPacketSize */
265 .callback = &uchcom_intr_callback,
266 },
267 };
268
269 static struct ucom_callback uchcom_callback = {
270 .ucom_cfg_get_status = &uchcom_cfg_get_status,
271 .ucom_cfg_set_dtr = &uchcom_cfg_set_dtr,
272 .ucom_cfg_set_rts = &uchcom_cfg_set_rts,
273 .ucom_cfg_set_break = &uchcom_cfg_set_break,
274 .ucom_cfg_open = &uchcom_cfg_open,
275 .ucom_cfg_param = &uchcom_cfg_param,
276 .ucom_pre_param = &uchcom_pre_param,
277 .ucom_start_read = &uchcom_start_read,
278 .ucom_stop_read = &uchcom_stop_read,
279 .ucom_start_write = &uchcom_start_write,
280 .ucom_stop_write = &uchcom_stop_write,
281 .ucom_poll = &uchcom_poll,
282 .ucom_free = &uchcom_free,
283 };
284
285 /* ----------------------------------------------------------------------
286 * driver entry points
287 */
288
289 static int
uchcom_probe(device_t dev)290 uchcom_probe(device_t dev)
291 {
292 struct usb_attach_arg *uaa = device_get_ivars(dev);
293
294 DPRINTFN(11, "\n");
295
296 if (uaa->usb_mode != USB_MODE_HOST) {
297 return (ENXIO);
298 }
299 if (uaa->info.bConfigIndex != UCHCOM_CONFIG_INDEX) {
300 return (ENXIO);
301 }
302 if (uaa->info.bIfaceIndex != UCHCOM_IFACE_INDEX) {
303 return (ENXIO);
304 }
305 return (usbd_lookup_id_by_uaa(uchcom_devs, sizeof(uchcom_devs), uaa));
306 }
307
308 static int
uchcom_attach(device_t dev)309 uchcom_attach(device_t dev)
310 {
311 struct uchcom_softc *sc = device_get_softc(dev);
312 struct usb_attach_arg *uaa = device_get_ivars(dev);
313 struct usb_interface *iface;
314 struct usb_interface_descriptor *id;
315 int error;
316
317 DPRINTFN(11, "\n");
318
319 device_set_usb_desc(dev);
320 mtx_init(&sc->sc_mtx, "uchcom", NULL, MTX_DEF);
321 ucom_ref(&sc->sc_super_ucom);
322
323 sc->sc_udev = uaa->device;
324
325 switch (uaa->info.idProduct) {
326 case USB_PRODUCT_WCH2_CH341SER:
327 device_printf(dev, "CH340 detected\n");
328 break;
329 case USB_PRODUCT_WCH2_CH341SER_2:
330 case USB_PRODUCT_WCH2_CH341SER_3:
331 device_printf(dev, "CH341 detected\n");
332 break;
333 case USB_PRODUCT_WCH2_CH343SER:
334 device_printf(dev, "CH343 detected\n");
335 break;
336 case USB_PRODUCT_WCH2_CH9102SER:
337 device_printf(dev, "CH9102 detected\n");
338 break;
339 default:
340 device_printf(dev, "New CH340/CH341/CH343/CH9102 product "
341 "0x%04x detected\n", uaa->info.idProduct);
342 break;
343 }
344
345 /* CH343/CH9102 has two interfaces. */
346 sc->sc_ctrl_iface_no = uaa->info.bIfaceNum;
347
348 iface = usbd_get_iface(uaa->device, UCHCOM_SECOND_IFACE_INDEX);
349 if (iface) {
350 id = usbd_get_interface_descriptor(iface);
351 if (id == NULL) {
352 device_printf(dev, "no interface descriptor\n");
353 goto detach;
354 }
355 sc->sc_iface_index = UCHCOM_SECOND_IFACE_INDEX;
356 usbd_set_parent_iface(uaa->device, UCHCOM_SECOND_IFACE_INDEX,
357 uaa->info.bIfaceIndex);
358 sc->sc_chiptype = TYPE_CH343;
359 } else {
360 sc->sc_iface_index = UCHCOM_IFACE_INDEX;
361 }
362
363 /* Setup all transfers. */
364 error = usbd_transfer_setup(uaa->device, &sc->sc_iface_index,
365 sc->sc_xfer, uchcom_config_data, UCHCOM_N_TRANSFER, sc,
366 &sc->sc_mtx);
367 if (error) {
368 device_printf(dev, "could not allocate all pipes\n");
369 goto detach;
370 }
371 error = usbd_transfer_setup(uaa->device, &sc->sc_ctrl_iface_no,
372 &sc->sc_intr_xfer, uchcom_intr_config_data, 1, sc, &sc->sc_mtx);
373 if (error) {
374 device_printf(dev, "allocating USB transfers failed for "
375 "interrupt\n");
376 goto detach;
377 }
378
379 /* clear stall at first run */
380 mtx_lock(&sc->sc_mtx);
381 usbd_xfer_set_stall(sc->sc_xfer[UCHCOM_BULK_DT_WR]);
382 usbd_xfer_set_stall(sc->sc_xfer[UCHCOM_BULK_DT_RD]);
383 mtx_unlock(&sc->sc_mtx);
384
385 error = ucom_attach(&sc->sc_super_ucom, &sc->sc_ucom, 1, sc,
386 &uchcom_callback, &sc->sc_mtx);
387 if (error) {
388 goto detach;
389 }
390 ucom_set_pnpinfo_usb(&sc->sc_super_ucom, dev);
391
392 return (0);
393
394 detach:
395 uchcom_detach(dev);
396 return (ENXIO);
397 }
398
399 static int
uchcom_detach(device_t dev)400 uchcom_detach(device_t dev)
401 {
402 struct uchcom_softc *sc = device_get_softc(dev);
403
404 DPRINTFN(11, "\n");
405
406 ucom_detach(&sc->sc_super_ucom, &sc->sc_ucom);
407 usbd_transfer_unsetup(&sc->sc_intr_xfer, 1);
408 usbd_transfer_unsetup(sc->sc_xfer, UCHCOM_N_TRANSFER);
409
410 device_claim_softc(dev);
411
412 uchcom_free_softc(sc);
413
414 return (0);
415 }
416
417 UCOM_UNLOAD_DRAIN(uchcom);
418
419 static void
uchcom_free_softc(struct uchcom_softc * sc)420 uchcom_free_softc(struct uchcom_softc *sc)
421 {
422 if (ucom_unref(&sc->sc_super_ucom)) {
423 mtx_destroy(&sc->sc_mtx);
424 device_free_softc(sc);
425 }
426 }
427
428 static void
uchcom_free(struct ucom_softc * ucom)429 uchcom_free(struct ucom_softc *ucom)
430 {
431 uchcom_free_softc(ucom->sc_parent);
432 }
433
434 /* ----------------------------------------------------------------------
435 * low level i/o
436 */
437
438 static void
uchcom_ctrl_write(struct uchcom_softc * sc,uint8_t reqno,uint16_t value,uint16_t index)439 uchcom_ctrl_write(struct uchcom_softc *sc, uint8_t reqno,
440 uint16_t value, uint16_t index)
441 {
442 struct usb_device_request req;
443
444 req.bmRequestType = UT_WRITE_VENDOR_DEVICE;
445 req.bRequest = reqno;
446 USETW(req.wValue, value);
447 USETW(req.wIndex, index);
448 USETW(req.wLength, 0);
449
450 DPRINTF("WR REQ 0x%02X VAL 0x%04X IDX 0x%04X\n",
451 reqno, value, index);
452 ucom_cfg_do_request(sc->sc_udev,
453 &sc->sc_ucom, &req, NULL, 0, 1000);
454 }
455
456 static void
uchcom_ctrl_read(struct uchcom_softc * sc,uint8_t reqno,uint16_t value,uint16_t index,void * buf,uint16_t buflen)457 uchcom_ctrl_read(struct uchcom_softc *sc, uint8_t reqno,
458 uint16_t value, uint16_t index, void *buf, uint16_t buflen)
459 {
460 struct usb_device_request req;
461
462 req.bmRequestType = UT_READ_VENDOR_DEVICE;
463 req.bRequest = reqno;
464 USETW(req.wValue, value);
465 USETW(req.wIndex, index);
466 USETW(req.wLength, buflen);
467
468 DPRINTF("RD REQ 0x%02X VAL 0x%04X IDX 0x%04X LEN %d\n",
469 reqno, value, index, buflen);
470 ucom_cfg_do_request(sc->sc_udev,
471 &sc->sc_ucom, &req, buf, USB_SHORT_XFER_OK, 1000);
472 }
473
474 static void
uchcom_write_reg(struct uchcom_softc * sc,uint8_t reg1,uint8_t val1,uint8_t reg2,uint8_t val2)475 uchcom_write_reg(struct uchcom_softc *sc,
476 uint8_t reg1, uint8_t val1, uint8_t reg2, uint8_t val2)
477 {
478 DPRINTF("0x%02X<-0x%02X, 0x%02X<-0x%02X\n",
479 (unsigned)reg1, (unsigned)val1,
480 (unsigned)reg2, (unsigned)val2);
481 uchcom_ctrl_write(
482 sc,
483 (sc->sc_chiptype != TYPE_CH343) ?
484 UCHCOM_REQ_WRITE_REG : UCHCOM_REQ_CH343_WRITE_REG,
485 reg1 | ((uint16_t)reg2 << 8), val1 | ((uint16_t)val2 << 8));
486 }
487
488 static void
uchcom_read_reg(struct uchcom_softc * sc,uint8_t reg1,uint8_t * rval1,uint8_t reg2,uint8_t * rval2)489 uchcom_read_reg(struct uchcom_softc *sc,
490 uint8_t reg1, uint8_t *rval1, uint8_t reg2, uint8_t *rval2)
491 {
492 uint8_t buf[UCHCOM_INPUT_BUF_SIZE];
493
494 uchcom_ctrl_read(
495 sc, UCHCOM_REQ_READ_REG,
496 reg1 | ((uint16_t)reg2 << 8), 0, buf, sizeof(buf));
497
498 DPRINTF("0x%02X->0x%02X, 0x%02X->0x%02X\n",
499 (unsigned)reg1, (unsigned)buf[0],
500 (unsigned)reg2, (unsigned)buf[1]);
501
502 if (rval1)
503 *rval1 = buf[0];
504 if (rval2)
505 *rval2 = buf[1];
506 }
507
508 static void
uchcom_get_version(struct uchcom_softc * sc,uint8_t * rver)509 uchcom_get_version(struct uchcom_softc *sc, uint8_t *rver)
510 {
511 uint8_t buf[UCHCOM_INPUT_BUF_SIZE];
512
513 uchcom_ctrl_read(sc, UCHCOM_REQ_GET_VERSION, 0, 0, buf, sizeof(buf));
514
515 if (rver)
516 *rver = buf[0];
517 }
518
519 static void
uchcom_get_status(struct uchcom_softc * sc,uint8_t * rval)520 uchcom_get_status(struct uchcom_softc *sc, uint8_t *rval)
521 {
522 uchcom_read_reg(sc, UCHCOM_REG_STAT1, rval, UCHCOM_REG_STAT2, NULL);
523 }
524
525 static void
uchcom_set_dtr_rts_10(struct uchcom_softc * sc,uint8_t val)526 uchcom_set_dtr_rts_10(struct uchcom_softc *sc, uint8_t val)
527 {
528 uchcom_write_reg(sc, UCHCOM_REG_STAT1, val, UCHCOM_REG_STAT1, val);
529 }
530
531 static void
uchcom_set_dtr_rts_20(struct uchcom_softc * sc,uint8_t val)532 uchcom_set_dtr_rts_20(struct uchcom_softc *sc, uint8_t val)
533 {
534 uchcom_ctrl_write(sc, UCHCOM_REQ_SET_DTRRTS, val, 0);
535 }
536
537 /* ----------------------------------------------------------------------
538 * middle layer
539 */
540
541 static void
uchcom_update_version(struct uchcom_softc * sc)542 uchcom_update_version(struct uchcom_softc *sc)
543 {
544 uchcom_get_version(sc, &sc->sc_version);
545 DPRINTF("Chip version: 0x%02x\n", sc->sc_version);
546 }
547
548 static void
uchcom_convert_status(struct uchcom_softc * sc,uint8_t cur)549 uchcom_convert_status(struct uchcom_softc *sc, uint8_t cur)
550 {
551 cur = ~cur & 0x0F;
552 sc->sc_msr = (cur << 4) | ((sc->sc_msr >> 4) ^ cur);
553 }
554
555 static void
uchcom_update_status(struct uchcom_softc * sc)556 uchcom_update_status(struct uchcom_softc *sc)
557 {
558 uint8_t cur;
559
560 uchcom_get_status(sc, &cur);
561 uchcom_convert_status(sc, cur);
562 }
563
564 static void
uchcom_set_dtr_rts(struct uchcom_softc * sc)565 uchcom_set_dtr_rts(struct uchcom_softc *sc)
566 {
567 uint8_t val = 0;
568
569 if (sc->sc_dtr)
570 val |= UCHCOM_DTR_MASK;
571 if (sc->sc_rts)
572 val |= UCHCOM_RTS_MASK;
573
574 if (sc->sc_version < UCHCOM_VER_20)
575 uchcom_set_dtr_rts_10(sc, ~val);
576 else
577 uchcom_set_dtr_rts_20(sc, ~val);
578 }
579
580 static void
uchcom_cfg_set_break(struct ucom_softc * ucom,uint8_t onoff)581 uchcom_cfg_set_break(struct ucom_softc *ucom, uint8_t onoff)
582 {
583 struct uchcom_softc *sc = ucom->sc_parent;
584 uint8_t brk1;
585 uint8_t brk2;
586
587 if (sc->sc_chiptype == TYPE_CH343) {
588 brk1 = UCHCOM_CH343_BRK_MASK;
589 if (!onoff)
590 brk1 |= UCHCOM_ABRK_MASK;
591 uchcom_write_reg(sc, brk1, 0, 0, 0);
592 } else {
593 uchcom_read_reg(sc, UCHCOM_REG_BREAK1, &brk1, UCHCOM_REG_LCR1,
594 &brk2);
595 if (onoff) {
596 /* on - clear bits */
597 brk1 &= ~UCHCOM_BRK_MASK;
598 brk2 &= ~UCHCOM_LCR1_TX;
599 } else {
600 /* off - set bits */
601 brk1 |= UCHCOM_BRK_MASK;
602 brk2 |= UCHCOM_LCR1_TX;
603 }
604 uchcom_write_reg(sc, UCHCOM_REG_BREAK1, brk1, UCHCOM_REG_LCR1,
605 brk2);
606 }
607 }
608
609 static void
uchcom_calc_baudrate(struct uchcom_softc * sc,uint32_t rate,uint8_t * divisor,uint8_t * factor)610 uchcom_calc_baudrate(struct uchcom_softc *sc, uint32_t rate, uint8_t *divisor,
611 uint8_t *factor)
612 {
613 uint32_t clk = 12000000;
614
615 if (rate >= 256000 && sc->sc_chiptype == TYPE_CH343)
616 *divisor = 7;
617 else if (rate > 23529) {
618 clk /= 2;
619 *divisor = 3;
620 } else if (rate > 2941) {
621 clk /= 16;
622 *divisor = 2;
623 } else if (rate > 367) {
624 clk /= 128;
625 *divisor = 1;
626 } else {
627 clk = 11719;
628 *divisor = 0;
629 }
630
631 *factor = 256 - clk / rate;
632
633 if (rate == 921600 && sc->sc_chiptype != TYPE_CH343) {
634 *divisor = 7;
635 *factor = 243;
636 }
637 }
638
639 static void
uchcom_set_baudrate(struct uchcom_softc * sc,uint32_t rate,uint16_t lcr)640 uchcom_set_baudrate(struct uchcom_softc *sc, uint32_t rate, uint16_t lcr)
641 {
642 uint16_t idx;
643 uint8_t factor, div;
644
645 uchcom_calc_baudrate(sc, rate, &div, &factor);
646 div |= (sc->sc_chiptype != TYPE_CH343) ? 0x80 : 0x00;
647 idx = (factor << 8) | div;
648
649 uchcom_ctrl_write(sc, UCHCOM_REQ_RESET, lcr, idx);
650 }
651
652 /* ----------------------------------------------------------------------
653 * methods for ucom
654 */
655 static void
uchcom_cfg_get_status(struct ucom_softc * ucom,uint8_t * lsr,uint8_t * msr)656 uchcom_cfg_get_status(struct ucom_softc *ucom, uint8_t *lsr, uint8_t *msr)
657 {
658 struct uchcom_softc *sc = ucom->sc_parent;
659
660 DPRINTF("\n");
661
662 /* XXX Note: sc_lsr is always zero */
663 *lsr = sc->sc_lsr;
664 *msr = sc->sc_msr;
665 }
666
667 static void
uchcom_cfg_set_dtr(struct ucom_softc * ucom,uint8_t onoff)668 uchcom_cfg_set_dtr(struct ucom_softc *ucom, uint8_t onoff)
669 {
670 struct uchcom_softc *sc = ucom->sc_parent;
671
672 DPRINTF("onoff = %d\n", onoff);
673
674 sc->sc_dtr = onoff;
675 uchcom_set_dtr_rts(sc);
676 }
677
678 static void
uchcom_cfg_set_rts(struct ucom_softc * ucom,uint8_t onoff)679 uchcom_cfg_set_rts(struct ucom_softc *ucom, uint8_t onoff)
680 {
681 struct uchcom_softc *sc = ucom->sc_parent;
682
683 DPRINTF("onoff = %d\n", onoff);
684
685 sc->sc_rts = onoff;
686 uchcom_set_dtr_rts(sc);
687 }
688
689 static void
uchcom_cfg_open(struct ucom_softc * ucom)690 uchcom_cfg_open(struct ucom_softc *ucom)
691 {
692 struct uchcom_softc *sc = ucom->sc_parent;
693
694 DPRINTF("\n");
695
696 if (sc->sc_chiptype != TYPE_CH343) {
697 /* Set default configuration. */
698 uchcom_get_version(sc, NULL);
699 uchcom_ctrl_write(sc, UCHCOM_REQ_RESET, 0, 0);
700 uchcom_write_reg(sc, UCHCOM_REG_BPS_PRE, 0x82,
701 UCHCOM_REG_BPS_DIV, 0xd9);
702 uchcom_write_reg(sc, 0x2c, 0x07, UCHCOM_REG_BPS_PAD, 0);
703 }
704 uchcom_update_version(sc);
705 uchcom_update_status(sc);
706 }
707
708 static int
uchcom_pre_param(struct ucom_softc * ucom,struct termios * t)709 uchcom_pre_param(struct ucom_softc *ucom, struct termios *t)
710 {
711 struct uchcom_softc *sc = ucom->sc_parent;
712
713 /*
714 * Check requested baud rate.
715 * The CH340/CH341 can set any baud rate up to 2Mb.
716 * The CH9102/CH343 can set any baud rate up to 6Mb.
717 */
718 switch (sc->sc_chiptype) {
719 case TYPE_CH343:
720 if (t->c_ospeed <= 6000000)
721 return (0);
722 break;
723 default:
724 if (t->c_ospeed <= 2000000)
725 return (0);
726 break;
727 }
728
729 return (EIO);
730 }
731
732 static void
uchcom_cfg_param(struct ucom_softc * ucom,struct termios * t)733 uchcom_cfg_param(struct ucom_softc *ucom, struct termios *t)
734 {
735 struct uchcom_softc *sc = ucom->sc_parent;
736 uint8_t lcr;
737
738 lcr = UCHCOM_LCR1_RX | UCHCOM_LCR1_TX;
739
740 if (t->c_cflag & CSTOPB)
741 lcr |= UCHCOM_LCR1_STOPB;
742
743 if (t->c_cflag & PARENB) {
744 lcr |= UCHCOM_LCR1_PARENB;
745 if (t->c_cflag & PARODD)
746 lcr |= UCHCOM_LCR1_PARODD;
747 else
748 lcr |= UCHCOM_LCR1_PAREVEN;
749 }
750
751 switch (t->c_cflag & CSIZE) {
752 case CS5:
753 lcr |= UCHCOM_LCR1_CS5;
754 break;
755 case CS6:
756 lcr |= UCHCOM_LCR1_CS6;
757 break;
758 case CS7:
759 lcr |= UCHCOM_LCR1_CS7;
760 break;
761 case CS8:
762 default:
763 lcr |= UCHCOM_LCR1_CS8;
764 break;
765 }
766
767 if (sc->sc_chiptype == TYPE_CH343)
768 uchcom_set_baudrate(sc, t->c_ospeed,
769 UCHCOM_T | UCHCOM_CL | UCHCOM_CH343_CT | lcr << 8);
770 else
771 uchcom_set_baudrate(sc, t->c_ospeed,
772 UCHCOM_T | UCHCOM_CL | UCHCOM_CT | lcr << 8);
773
774 uchcom_set_dtr_rts(sc);
775 uchcom_update_status(sc);
776 }
777
778 static void
uchcom_start_read(struct ucom_softc * ucom)779 uchcom_start_read(struct ucom_softc *ucom)
780 {
781 struct uchcom_softc *sc = ucom->sc_parent;
782
783 /* start interrupt endpoint */
784 usbd_transfer_start(sc->sc_intr_xfer);
785
786 /* start read endpoint */
787 usbd_transfer_start(sc->sc_xfer[UCHCOM_BULK_DT_RD]);
788 }
789
790 static void
uchcom_stop_read(struct ucom_softc * ucom)791 uchcom_stop_read(struct ucom_softc *ucom)
792 {
793 struct uchcom_softc *sc = ucom->sc_parent;
794
795 /* stop interrupt endpoint */
796 usbd_transfer_stop(sc->sc_intr_xfer);
797
798 /* stop read endpoint */
799 usbd_transfer_stop(sc->sc_xfer[UCHCOM_BULK_DT_RD]);
800 }
801
802 static void
uchcom_start_write(struct ucom_softc * ucom)803 uchcom_start_write(struct ucom_softc *ucom)
804 {
805 struct uchcom_softc *sc = ucom->sc_parent;
806
807 usbd_transfer_start(sc->sc_xfer[UCHCOM_BULK_DT_WR]);
808 }
809
810 static void
uchcom_stop_write(struct ucom_softc * ucom)811 uchcom_stop_write(struct ucom_softc *ucom)
812 {
813 struct uchcom_softc *sc = ucom->sc_parent;
814
815 usbd_transfer_stop(sc->sc_xfer[UCHCOM_BULK_DT_WR]);
816 }
817
818 /* ----------------------------------------------------------------------
819 * callback when the modem status is changed.
820 */
821 static void
uchcom_intr_callback(struct usb_xfer * xfer,usb_error_t error)822 uchcom_intr_callback(struct usb_xfer *xfer, usb_error_t error)
823 {
824 struct uchcom_softc *sc = usbd_xfer_softc(xfer);
825 struct usb_page_cache *pc;
826 uint32_t intrstat;
827 uint8_t buf[16];
828 int actlen;
829
830 usbd_xfer_status(xfer, &actlen, NULL, NULL, NULL);
831
832 switch (USB_GET_STATE(xfer)) {
833 case USB_ST_TRANSFERRED:
834
835 DPRINTF("actlen = %u\n", actlen);
836
837 if (actlen >= UCHCOM_INTR_LEAST) {
838 pc = usbd_xfer_get_frame(xfer, 0);
839 usbd_copy_out(pc, 0, buf, sizeof(buf));
840
841 intrstat = (sc->sc_chiptype == TYPE_CH343) ?
842 actlen - 1 : UCHCOM_INTR_STAT1;
843
844 uchcom_convert_status(sc, buf[intrstat]);
845 ucom_status_change(&sc->sc_ucom);
846 }
847 case USB_ST_SETUP:
848 tr_setup:
849 usbd_xfer_set_frame_len(xfer, 0, usbd_xfer_max_len(xfer));
850 usbd_transfer_submit(xfer);
851 break;
852
853 default: /* Error */
854 if (error != USB_ERR_CANCELLED) {
855 /* try to clear stall first */
856 usbd_xfer_set_stall(xfer);
857 goto tr_setup;
858 }
859 break;
860 }
861 }
862
863 static void
uchcom_write_callback(struct usb_xfer * xfer,usb_error_t error)864 uchcom_write_callback(struct usb_xfer *xfer, usb_error_t error)
865 {
866 struct uchcom_softc *sc = usbd_xfer_softc(xfer);
867 struct usb_page_cache *pc;
868 uint32_t actlen;
869
870 switch (USB_GET_STATE(xfer)) {
871 case USB_ST_SETUP:
872 case USB_ST_TRANSFERRED:
873 tr_setup:
874 pc = usbd_xfer_get_frame(xfer, 0);
875 if (ucom_get_data(&sc->sc_ucom, pc, 0,
876 usbd_xfer_max_len(xfer), &actlen)) {
877 DPRINTF("actlen = %d\n", actlen);
878
879 usbd_xfer_set_frame_len(xfer, 0, actlen);
880 usbd_transfer_submit(xfer);
881 }
882 break;
883
884 default: /* Error */
885 if (error != USB_ERR_CANCELLED) {
886 /* try to clear stall first */
887 usbd_xfer_set_stall(xfer);
888 goto tr_setup;
889 }
890 break;
891 }
892 }
893
894 static void
uchcom_read_callback(struct usb_xfer * xfer,usb_error_t error)895 uchcom_read_callback(struct usb_xfer *xfer, usb_error_t error)
896 {
897 struct uchcom_softc *sc = usbd_xfer_softc(xfer);
898 struct usb_page_cache *pc;
899 int actlen;
900
901 usbd_xfer_status(xfer, &actlen, NULL, NULL, NULL);
902
903 switch (USB_GET_STATE(xfer)) {
904 case USB_ST_TRANSFERRED:
905
906 if (actlen > 0) {
907 pc = usbd_xfer_get_frame(xfer, 0);
908 ucom_put_data(&sc->sc_ucom, pc, 0, actlen);
909 }
910
911 case USB_ST_SETUP:
912 tr_setup:
913 usbd_xfer_set_frame_len(xfer, 0, usbd_xfer_max_len(xfer));
914 usbd_transfer_submit(xfer);
915 break;
916
917 default: /* Error */
918 if (error != USB_ERR_CANCELLED) {
919 /* try to clear stall first */
920 usbd_xfer_set_stall(xfer);
921 goto tr_setup;
922 }
923 break;
924 }
925 }
926
927 static void
uchcom_poll(struct ucom_softc * ucom)928 uchcom_poll(struct ucom_softc *ucom)
929 {
930 struct uchcom_softc *sc = ucom->sc_parent;
931 usbd_transfer_poll(sc->sc_xfer, UCHCOM_N_TRANSFER);
932 }
933
934 static device_method_t uchcom_methods[] = {
935 /* Device interface */
936 DEVMETHOD(device_probe, uchcom_probe),
937 DEVMETHOD(device_attach, uchcom_attach),
938 DEVMETHOD(device_detach, uchcom_detach),
939 DEVMETHOD_END
940 };
941
942 static driver_t uchcom_driver = {
943 .name = "uchcom",
944 .methods = uchcom_methods,
945 .size = sizeof(struct uchcom_softc)
946 };
947
948 DRIVER_MODULE(uchcom, uhub, uchcom_driver, NULL, NULL);
949 MODULE_DEPEND(uchcom, ucom, 1, 1, 1);
950 MODULE_DEPEND(uchcom, usb, 1, 1, 1);
951 MODULE_VERSION(uchcom, 1);
952 USB_PNP_HOST_INFO(uchcom_devs);
953