1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /* Copyright(c) 2019-2020 Realtek Corporation
3 */
4
5 #include "acpi.h"
6 #include "debug.h"
7 #include "phy.h"
8 #include "reg.h"
9 #include "sar.h"
10 #include "util.h"
11
12 #define RTW89_TAS_FACTOR 2 /* unit: 0.25 dBm */
13 #define RTW89_TAS_SAR_GAP (1 << RTW89_TAS_FACTOR)
14 #define RTW89_TAS_DPR_GAP (1 << RTW89_TAS_FACTOR)
15 #define RTW89_TAS_DELTA (2 << RTW89_TAS_FACTOR)
16 #define RTW89_TAS_TX_RATIO_THRESHOLD 70
17 #define RTW89_TAS_DFLT_TX_RATIO 80
18 #define RTW89_TAS_DPR_ON_OFFSET (RTW89_TAS_DELTA + RTW89_TAS_SAR_GAP)
19 #define RTW89_TAS_DPR_OFF_OFFSET (4 << RTW89_TAS_FACTOR)
20
rtw89_sar_get_subband(struct rtw89_dev * rtwdev,u32 center_freq)21 static enum rtw89_sar_subband rtw89_sar_get_subband(struct rtw89_dev *rtwdev,
22 u32 center_freq)
23 {
24 switch (center_freq) {
25 default:
26 rtw89_debug(rtwdev, RTW89_DBG_SAR,
27 "center freq: %u to SAR subband is unhandled\n",
28 center_freq);
29 fallthrough;
30 case 2412 ... 2484:
31 return RTW89_SAR_2GHZ_SUBBAND;
32 case 5180 ... 5320:
33 return RTW89_SAR_5GHZ_SUBBAND_1_2;
34 case 5500 ... 5720:
35 return RTW89_SAR_5GHZ_SUBBAND_2_E;
36 case 5745 ... 5885:
37 return RTW89_SAR_5GHZ_SUBBAND_3_4;
38 case 5955 ... 6155:
39 return RTW89_SAR_6GHZ_SUBBAND_5_L;
40 case 6175 ... 6415:
41 return RTW89_SAR_6GHZ_SUBBAND_5_H;
42 case 6435 ... 6515:
43 return RTW89_SAR_6GHZ_SUBBAND_6;
44 case 6535 ... 6695:
45 return RTW89_SAR_6GHZ_SUBBAND_7_L;
46 case 6715 ... 6855:
47 return RTW89_SAR_6GHZ_SUBBAND_7_H;
48
49 /* freq 6875 (ch 185, 20MHz) spans RTW89_SAR_6GHZ_SUBBAND_7_H
50 * and RTW89_SAR_6GHZ_SUBBAND_8, so directly describe it with
51 * struct rtw89_6ghz_span.
52 */
53
54 case 6895 ... 7115:
55 return RTW89_SAR_6GHZ_SUBBAND_8;
56 }
57 }
58
rtw89_query_sar_config_common(struct rtw89_dev * rtwdev,const struct rtw89_sar_parm * sar_parm,s32 * cfg)59 static int rtw89_query_sar_config_common(struct rtw89_dev *rtwdev,
60 const struct rtw89_sar_parm *sar_parm,
61 s32 *cfg)
62 {
63 struct rtw89_sar_cfg_common *rtwsar = &rtwdev->sar.cfg_common;
64 enum rtw89_sar_subband subband_l, subband_h;
65 u32 center_freq = sar_parm->center_freq;
66 const struct rtw89_6ghz_span *span;
67
68 span = rtw89_get_6ghz_span(rtwdev, center_freq);
69
70 if (span && RTW89_SAR_SPAN_VALID(span)) {
71 subband_l = span->sar_subband_low;
72 subband_h = span->sar_subband_high;
73 } else {
74 subband_l = rtw89_sar_get_subband(rtwdev, center_freq);
75 subband_h = subband_l;
76 }
77
78 rtw89_debug(rtwdev, RTW89_DBG_SAR,
79 "center_freq %u: SAR subband {%u, %u}\n",
80 center_freq, subband_l, subband_h);
81
82 if (!rtwsar->set[subband_l] && !rtwsar->set[subband_h])
83 return -ENODATA;
84
85 if (!rtwsar->set[subband_l])
86 *cfg = rtwsar->cfg[subband_h];
87 else if (!rtwsar->set[subband_h])
88 *cfg = rtwsar->cfg[subband_l];
89 else
90 *cfg = min(rtwsar->cfg[subband_l], rtwsar->cfg[subband_h]);
91
92 return 0;
93 }
94
95 static const struct rtw89_sar_entry_from_acpi *
rtw89_sar_cfg_acpi_get_ent(const struct rtw89_sar_cfg_acpi * rtwsar,enum rtw89_rf_path path,enum rtw89_regulation_type regd)96 rtw89_sar_cfg_acpi_get_ent(const struct rtw89_sar_cfg_acpi *rtwsar,
97 enum rtw89_rf_path path,
98 enum rtw89_regulation_type regd)
99 {
100 const struct rtw89_sar_indicator_from_acpi *ind = &rtwsar->indicator;
101 const struct rtw89_sar_table_from_acpi *tbl;
102 u8 sel;
103
104 sel = ind->tblsel[path];
105 tbl = &rtwsar->tables[sel];
106
107 return &tbl->entries[regd];
108 }
109
110 static
rtw89_sar_cfg_acpi_get_min(const struct rtw89_sar_entry_from_acpi * ent,enum rtw89_rf_path path,enum rtw89_acpi_sar_subband subband_low,enum rtw89_acpi_sar_subband subband_high)111 s32 rtw89_sar_cfg_acpi_get_min(const struct rtw89_sar_entry_from_acpi *ent,
112 enum rtw89_rf_path path,
113 enum rtw89_acpi_sar_subband subband_low,
114 enum rtw89_acpi_sar_subband subband_high)
115 {
116 return min(ent->v[subband_low][path], ent->v[subband_high][path]);
117 }
118
rtw89_query_sar_config_acpi(struct rtw89_dev * rtwdev,const struct rtw89_sar_parm * sar_parm,s32 * cfg)119 static int rtw89_query_sar_config_acpi(struct rtw89_dev *rtwdev,
120 const struct rtw89_sar_parm *sar_parm,
121 s32 *cfg)
122 {
123 const struct rtw89_chip_info *chip = rtwdev->chip;
124 const struct rtw89_sar_cfg_acpi *rtwsar = &rtwdev->sar.cfg_acpi;
125 const struct rtw89_sar_entry_from_acpi *ent_a, *ent_b;
126 enum rtw89_acpi_sar_subband subband_l, subband_h;
127 u32 center_freq = sar_parm->center_freq;
128 const struct rtw89_6ghz_span *span;
129 enum rtw89_regulation_type regd;
130 enum rtw89_band band;
131 s32 cfg_a, cfg_b;
132
133 span = rtw89_get_6ghz_span(rtwdev, center_freq);
134
135 if (span && RTW89_ACPI_SAR_SPAN_VALID(span)) {
136 subband_l = span->acpi_sar_subband_low;
137 subband_h = span->acpi_sar_subband_high;
138 } else {
139 subband_l = rtw89_acpi_sar_get_subband(rtwdev, center_freq);
140 subband_h = subband_l;
141 }
142
143 band = rtw89_acpi_sar_subband_to_band(rtwdev, subband_l);
144 regd = rtw89_regd_get(rtwdev, band);
145
146 ent_a = rtw89_sar_cfg_acpi_get_ent(rtwsar, RF_PATH_A, regd);
147 ent_b = rtw89_sar_cfg_acpi_get_ent(rtwsar, RF_PATH_B, regd);
148
149 cfg_a = rtw89_sar_cfg_acpi_get_min(ent_a, RF_PATH_A, subband_l, subband_h);
150 cfg_b = rtw89_sar_cfg_acpi_get_min(ent_b, RF_PATH_B, subband_l, subband_h);
151
152 if (chip->support_sar_by_ant) {
153 /* With declaration of support_sar_by_ant, relax the general
154 * SAR querying to return the maximum between paths. However,
155 * expect chip has dealt with the corresponding SAR settings
156 * by path. (To get SAR for a given path, chip can then query
157 * with force_path.)
158 */
159 if (sar_parm->force_path) {
160 switch (sar_parm->path) {
161 default:
162 case RF_PATH_A:
163 *cfg = cfg_a;
164 break;
165 case RF_PATH_B:
166 *cfg = cfg_b;
167 break;
168 }
169 } else {
170 *cfg = max(cfg_a, cfg_b);
171 }
172 } else {
173 *cfg = min(cfg_a, cfg_b);
174 }
175
176 if (sar_parm->ntx == RTW89_2TX)
177 *cfg -= rtwsar->downgrade_2tx;
178
179 return 0;
180 }
181
182 static const
183 struct rtw89_sar_handler rtw89_sar_handlers[RTW89_SAR_SOURCE_NR] = {
184 [RTW89_SAR_SOURCE_COMMON] = {
185 .descr_sar_source = "RTW89_SAR_SOURCE_COMMON",
186 .txpwr_factor_sar = 2,
187 .query_sar_config = rtw89_query_sar_config_common,
188 },
189 [RTW89_SAR_SOURCE_ACPI] = {
190 .descr_sar_source = "RTW89_SAR_SOURCE_ACPI",
191 .txpwr_factor_sar = TXPWR_FACTOR_OF_RTW89_ACPI_SAR,
192 .query_sar_config = rtw89_query_sar_config_acpi,
193 },
194 };
195
196 #define rtw89_sar_set_src(_dev, _src, _cfg_name, _cfg_data) \
197 do { \
198 typeof(_src) _s = (_src); \
199 typeof(_dev) _d = (_dev); \
200 BUILD_BUG_ON(!rtw89_sar_handlers[_s].descr_sar_source); \
201 BUILD_BUG_ON(!rtw89_sar_handlers[_s].query_sar_config); \
202 if (test_bit(RTW89_FLAG_PROBE_DONE, _d->flags)) \
203 lockdep_assert_wiphy(_d->hw->wiphy); \
204 _d->sar._cfg_name = *(_cfg_data); \
205 _d->sar.src = _s; \
206 } while (0)
207
rtw89_txpwr_sar_to_mac(struct rtw89_dev * rtwdev,u8 fct,s32 cfg)208 static s8 rtw89_txpwr_sar_to_mac(struct rtw89_dev *rtwdev, u8 fct, s32 cfg)
209 {
210 const u8 fct_mac = rtwdev->chip->txpwr_factor_mac;
211 s32 cfg_mac;
212
213 cfg_mac = fct > fct_mac ?
214 cfg >> (fct - fct_mac) : cfg << (fct_mac - fct);
215
216 return (s8)clamp_t(s32, cfg_mac,
217 RTW89_SAR_TXPWR_MAC_MIN,
218 RTW89_SAR_TXPWR_MAC_MAX);
219 }
220
rtw89_txpwr_tas_to_sar(const struct rtw89_sar_handler * sar_hdl,s32 cfg)221 static s32 rtw89_txpwr_tas_to_sar(const struct rtw89_sar_handler *sar_hdl,
222 s32 cfg)
223 {
224 const u8 fct = sar_hdl->txpwr_factor_sar;
225
226 if (fct > RTW89_TAS_FACTOR)
227 return cfg << (fct - RTW89_TAS_FACTOR);
228 else
229 return cfg >> (RTW89_TAS_FACTOR - fct);
230 }
231
rtw89_txpwr_sar_to_tas(const struct rtw89_sar_handler * sar_hdl,s32 cfg)232 static s32 rtw89_txpwr_sar_to_tas(const struct rtw89_sar_handler *sar_hdl,
233 s32 cfg)
234 {
235 const u8 fct = sar_hdl->txpwr_factor_sar;
236
237 if (fct > RTW89_TAS_FACTOR)
238 return cfg >> (fct - RTW89_TAS_FACTOR);
239 else
240 return cfg << (RTW89_TAS_FACTOR - fct);
241 }
242
rtw89_tas_is_active(struct rtw89_dev * rtwdev)243 static bool rtw89_tas_is_active(struct rtw89_dev *rtwdev)
244 {
245 struct rtw89_tas_info *tas = &rtwdev->tas;
246 struct rtw89_vif *rtwvif;
247
248 if (!tas->enable)
249 return false;
250
251 rtw89_for_each_rtwvif(rtwdev, rtwvif) {
252 if (ieee80211_vif_is_mld(rtwvif_to_vif(rtwvif)))
253 return false;
254 }
255
256 return true;
257 }
258
rtw89_tas_state_str(enum rtw89_tas_state state)259 static const char *rtw89_tas_state_str(enum rtw89_tas_state state)
260 {
261 switch (state) {
262 case RTW89_TAS_STATE_DPR_OFF:
263 return "DPR OFF";
264 case RTW89_TAS_STATE_DPR_ON:
265 return "DPR ON";
266 case RTW89_TAS_STATE_STATIC_SAR:
267 return "STATIC SAR";
268 default:
269 return NULL;
270 }
271 }
272
rtw89_query_sar(struct rtw89_dev * rtwdev,const struct rtw89_sar_parm * sar_parm)273 s8 rtw89_query_sar(struct rtw89_dev *rtwdev, const struct rtw89_sar_parm *sar_parm)
274 {
275 const enum rtw89_sar_sources src = rtwdev->sar.src;
276 /* its members are protected by rtw89_sar_set_src() */
277 const struct rtw89_sar_handler *sar_hdl = &rtw89_sar_handlers[src];
278 struct rtw89_tas_info *tas = &rtwdev->tas;
279 s32 offset;
280 int ret;
281 s32 cfg;
282 u8 fct;
283
284 lockdep_assert_wiphy(rtwdev->hw->wiphy);
285
286 if (src == RTW89_SAR_SOURCE_NONE)
287 return RTW89_SAR_TXPWR_MAC_MAX;
288
289 ret = sar_hdl->query_sar_config(rtwdev, sar_parm, &cfg);
290 if (ret)
291 return RTW89_SAR_TXPWR_MAC_MAX;
292
293 if (rtw89_tas_is_active(rtwdev)) {
294 switch (tas->state) {
295 case RTW89_TAS_STATE_DPR_OFF:
296 offset = rtw89_txpwr_tas_to_sar(sar_hdl, RTW89_TAS_DPR_OFF_OFFSET);
297 cfg += offset;
298 break;
299 case RTW89_TAS_STATE_DPR_ON:
300 offset = rtw89_txpwr_tas_to_sar(sar_hdl, RTW89_TAS_DPR_ON_OFFSET);
301 cfg -= offset;
302 break;
303 case RTW89_TAS_STATE_STATIC_SAR:
304 default:
305 break;
306 }
307 }
308
309 fct = sar_hdl->txpwr_factor_sar;
310
311 return rtw89_txpwr_sar_to_mac(rtwdev, fct, cfg);
312 }
313 EXPORT_SYMBOL(rtw89_query_sar);
314
rtw89_print_sar(struct rtw89_dev * rtwdev,char * buf,size_t bufsz,const struct rtw89_sar_parm * sar_parm)315 int rtw89_print_sar(struct rtw89_dev *rtwdev, char *buf, size_t bufsz,
316 const struct rtw89_sar_parm *sar_parm)
317 {
318 const enum rtw89_sar_sources src = rtwdev->sar.src;
319 /* its members are protected by rtw89_sar_set_src() */
320 const struct rtw89_sar_handler *sar_hdl = &rtw89_sar_handlers[src];
321 const u8 fct_mac = rtwdev->chip->txpwr_factor_mac;
322 char *p = buf, *end = buf + bufsz;
323 int ret;
324 s32 cfg;
325 u8 fct;
326
327 lockdep_assert_wiphy(rtwdev->hw->wiphy);
328
329 if (src == RTW89_SAR_SOURCE_NONE) {
330 p += scnprintf(p, end - p, "no SAR is applied\n");
331 goto out;
332 }
333
334 p += scnprintf(p, end - p, "source: %d (%s)\n", src,
335 sar_hdl->descr_sar_source);
336
337 ret = sar_hdl->query_sar_config(rtwdev, sar_parm, &cfg);
338 if (ret) {
339 p += scnprintf(p, end - p, "config: return code: %d\n", ret);
340 p += scnprintf(p, end - p,
341 "assign: max setting: %d (unit: 1/%lu dBm)\n",
342 RTW89_SAR_TXPWR_MAC_MAX, BIT(fct_mac));
343 goto out;
344 }
345
346 fct = sar_hdl->txpwr_factor_sar;
347
348 p += scnprintf(p, end - p, "config: %d (unit: 1/%lu dBm)\n", cfg,
349 BIT(fct));
350
351 p += scnprintf(p, end - p, "support different configs by antenna: %s\n",
352 str_yes_no(rtwdev->chip->support_sar_by_ant));
353 out:
354 return p - buf;
355 }
356
rtw89_print_tas(struct rtw89_dev * rtwdev,char * buf,size_t bufsz)357 int rtw89_print_tas(struct rtw89_dev *rtwdev, char *buf, size_t bufsz)
358 {
359 struct rtw89_tas_info *tas = &rtwdev->tas;
360 char *p = buf, *end = buf + bufsz;
361
362 if (!rtw89_tas_is_active(rtwdev)) {
363 p += scnprintf(p, end - p, "no TAS is applied\n");
364 goto out;
365 }
366
367 p += scnprintf(p, end - p, "State: %s\n",
368 rtw89_tas_state_str(tas->state));
369 p += scnprintf(p, end - p, "Average time: %d\n",
370 tas->window_size * 2);
371 p += scnprintf(p, end - p, "SAR gap: %d dBm\n",
372 RTW89_TAS_SAR_GAP >> RTW89_TAS_FACTOR);
373 p += scnprintf(p, end - p, "DPR gap: %d dBm\n",
374 RTW89_TAS_DPR_GAP >> RTW89_TAS_FACTOR);
375 p += scnprintf(p, end - p, "DPR ON offset: %d dBm\n",
376 RTW89_TAS_DPR_ON_OFFSET >> RTW89_TAS_FACTOR);
377 p += scnprintf(p, end - p, "DPR OFF offset: %d dBm\n",
378 RTW89_TAS_DPR_OFF_OFFSET >> RTW89_TAS_FACTOR);
379
380 out:
381 return p - buf;
382 }
383
rtw89_apply_sar_common(struct rtw89_dev * rtwdev,const struct rtw89_sar_cfg_common * sar)384 static int rtw89_apply_sar_common(struct rtw89_dev *rtwdev,
385 const struct rtw89_sar_cfg_common *sar)
386 {
387 /* let common SAR have the highest priority; always apply it */
388 rtw89_sar_set_src(rtwdev, RTW89_SAR_SOURCE_COMMON, cfg_common, sar);
389 rtw89_core_set_chip_txpwr(rtwdev);
390 rtw89_tas_reset(rtwdev, false);
391
392 return 0;
393 }
394
395 static const struct cfg80211_sar_freq_ranges rtw89_common_sar_freq_ranges[] = {
396 { .start_freq = 2412, .end_freq = 2484, },
397 { .start_freq = 5180, .end_freq = 5320, },
398 { .start_freq = 5500, .end_freq = 5720, },
399 { .start_freq = 5745, .end_freq = 5885, },
400 { .start_freq = 5955, .end_freq = 6155, },
401 { .start_freq = 6175, .end_freq = 6415, },
402 { .start_freq = 6435, .end_freq = 6515, },
403 { .start_freq = 6535, .end_freq = 6695, },
404 { .start_freq = 6715, .end_freq = 6875, },
405 { .start_freq = 6875, .end_freq = 7115, },
406 };
407
408 static_assert(RTW89_SAR_SUBBAND_NR ==
409 ARRAY_SIZE(rtw89_common_sar_freq_ranges));
410
411 const struct cfg80211_sar_capa rtw89_sar_capa = {
412 .type = NL80211_SAR_TYPE_POWER,
413 .num_freq_ranges = ARRAY_SIZE(rtw89_common_sar_freq_ranges),
414 .freq_ranges = rtw89_common_sar_freq_ranges,
415 };
416
rtw89_ops_set_sar_specs(struct ieee80211_hw * hw,const struct cfg80211_sar_specs * sar)417 int rtw89_ops_set_sar_specs(struct ieee80211_hw *hw,
418 const struct cfg80211_sar_specs *sar)
419 {
420 struct rtw89_dev *rtwdev = hw->priv;
421 struct rtw89_sar_cfg_common sar_common = {0};
422 u8 fct;
423 u32 freq_start;
424 u32 freq_end;
425 s32 power;
426 u32 i, idx;
427
428 lockdep_assert_wiphy(rtwdev->hw->wiphy);
429
430 if (sar->type != NL80211_SAR_TYPE_POWER)
431 return -EINVAL;
432
433 fct = rtw89_sar_handlers[RTW89_SAR_SOURCE_COMMON].txpwr_factor_sar;
434
435 for (i = 0; i < sar->num_sub_specs; i++) {
436 idx = sar->sub_specs[i].freq_range_index;
437 if (idx >= ARRAY_SIZE(rtw89_common_sar_freq_ranges))
438 return -EINVAL;
439
440 freq_start = rtw89_common_sar_freq_ranges[idx].start_freq;
441 freq_end = rtw89_common_sar_freq_ranges[idx].end_freq;
442 power = sar->sub_specs[i].power;
443
444 rtw89_debug(rtwdev, RTW89_DBG_SAR,
445 "On freq %u to %u, set SAR limit %d (unit: 1/%lu dBm)\n",
446 freq_start, freq_end, power, BIT(fct));
447
448 sar_common.set[idx] = true;
449 sar_common.cfg[idx] = power;
450 }
451
452 return rtw89_apply_sar_common(rtwdev, &sar_common);
453 }
454
rtw89_apply_sar_acpi(struct rtw89_dev * rtwdev,const struct rtw89_sar_cfg_acpi * sar)455 static void rtw89_apply_sar_acpi(struct rtw89_dev *rtwdev,
456 const struct rtw89_sar_cfg_acpi *sar)
457 {
458 const struct rtw89_sar_table_from_acpi *tbl;
459 const struct rtw89_sar_entry_from_acpi *ent;
460 enum rtw89_sar_sources src;
461 unsigned int i, j, k;
462
463 src = rtwdev->sar.src;
464 if (src != RTW89_SAR_SOURCE_NONE) {
465 rtw89_warn(rtwdev, "SAR source: %d is in use", src);
466 return;
467 }
468
469 rtw89_debug(rtwdev, RTW89_DBG_SAR,
470 "SAR-ACPI downgrade 2TX: %u (unit: 1/%lu dBm)\n",
471 sar->downgrade_2tx, BIT(TXPWR_FACTOR_OF_RTW89_ACPI_SAR));
472
473 for (i = 0; i < sar->valid_num; i++) {
474 tbl = &sar->tables[i];
475
476 for (j = 0; j < RTW89_REGD_NUM; j++) {
477 ent = &tbl->entries[j];
478
479 rtw89_debug(rtwdev, RTW89_DBG_SAR,
480 "SAR-ACPI-[%u] REGD-%s (unit: 1/%lu dBm)\n",
481 i, rtw89_regd_get_string(j),
482 BIT(TXPWR_FACTOR_OF_RTW89_ACPI_SAR));
483
484 for (k = 0; k < NUM_OF_RTW89_ACPI_SAR_SUBBAND; k++)
485 rtw89_debug(rtwdev, RTW89_DBG_SAR,
486 "On subband %u, { %d, %d }\n", k,
487 ent->v[k][RF_PATH_A], ent->v[k][RF_PATH_B]);
488 }
489 }
490
491 rtw89_sar_set_src(rtwdev, RTW89_SAR_SOURCE_ACPI, cfg_acpi, sar);
492
493 /* SAR via ACPI is only configured in the early initial phase, so
494 * it does not seem necessary to reset txpwr related things here.
495 */
496 }
497
rtw89_set_sar_from_acpi(struct rtw89_dev * rtwdev)498 static void rtw89_set_sar_from_acpi(struct rtw89_dev *rtwdev)
499 {
500 struct rtw89_sar_cfg_acpi *cfg;
501 int ret;
502
503 cfg = kzalloc(sizeof(*cfg), GFP_KERNEL);
504 if (!cfg)
505 return;
506
507 ret = rtw89_acpi_evaluate_sar(rtwdev, cfg);
508 if (ret) {
509 rtw89_debug(rtwdev, RTW89_DBG_SAR,
510 "evaluating ACPI SAR returns %d\n", ret);
511 goto out;
512 }
513
514 if (unlikely(!cfg->valid_num)) {
515 rtw89_debug(rtwdev, RTW89_DBG_SAR, "no valid SAR table from ACPI\n");
516 goto out;
517 }
518
519 rtw89_apply_sar_acpi(rtwdev, cfg);
520
521 out:
522 kfree(cfg);
523 }
524
rtw89_tas_query_sar_config(struct rtw89_dev * rtwdev,s32 * cfg)525 static bool rtw89_tas_query_sar_config(struct rtw89_dev *rtwdev, s32 *cfg)
526 {
527 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_CHANCTX_0);
528 const enum rtw89_sar_sources src = rtwdev->sar.src;
529 /* its members are protected by rtw89_sar_set_src() */
530 const struct rtw89_sar_handler *sar_hdl = &rtw89_sar_handlers[src];
531 struct rtw89_sar_parm sar_parm = {};
532 int ret;
533
534 if (src == RTW89_SAR_SOURCE_NONE)
535 return false;
536
537 sar_parm.center_freq = chan->freq;
538 ret = sar_hdl->query_sar_config(rtwdev, &sar_parm, cfg);
539 if (ret)
540 return false;
541
542 *cfg = rtw89_txpwr_sar_to_tas(sar_hdl, *cfg);
543
544 return true;
545 }
546
__rtw89_tas_state_update(struct rtw89_dev * rtwdev,enum rtw89_tas_state state)547 static bool __rtw89_tas_state_update(struct rtw89_dev *rtwdev,
548 enum rtw89_tas_state state)
549 {
550 struct rtw89_tas_info *tas = &rtwdev->tas;
551
552 if (tas->state == state)
553 return false;
554
555 rtw89_debug(rtwdev, RTW89_DBG_SAR, "tas: switch state: %s -> %s\n",
556 rtw89_tas_state_str(tas->state), rtw89_tas_state_str(state));
557
558 tas->state = state;
559 return true;
560 }
561
rtw89_tas_state_update(struct rtw89_dev * rtwdev,enum rtw89_tas_state state)562 static void rtw89_tas_state_update(struct rtw89_dev *rtwdev,
563 enum rtw89_tas_state state)
564 {
565 if (!__rtw89_tas_state_update(rtwdev, state))
566 return;
567
568 rtw89_core_set_chip_txpwr(rtwdev);
569 }
570
rtw89_tas_get_window_size(struct rtw89_dev * rtwdev)571 static u32 rtw89_tas_get_window_size(struct rtw89_dev *rtwdev)
572 {
573 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_CHANCTX_0);
574 u8 band = chan->band_type;
575 u8 regd = rtw89_regd_get(rtwdev, band);
576
577 switch (regd) {
578 default:
579 rtw89_debug(rtwdev, RTW89_DBG_SAR,
580 "tas: regd: %u is unhandled\n", regd);
581 fallthrough;
582 case RTW89_IC:
583 case RTW89_KCC:
584 return 180;
585 case RTW89_FCC:
586 switch (band) {
587 case RTW89_BAND_2G:
588 return 50;
589 case RTW89_BAND_5G:
590 return 30;
591 case RTW89_BAND_6G:
592 default:
593 return 15;
594 }
595 break;
596 }
597 }
598
rtw89_tas_window_update(struct rtw89_dev * rtwdev)599 static void rtw89_tas_window_update(struct rtw89_dev *rtwdev)
600 {
601 u32 window_size = rtw89_tas_get_window_size(rtwdev);
602 struct rtw89_tas_info *tas = &rtwdev->tas;
603 u64 total_txpwr = 0;
604 u8 head_idx;
605 u32 i, j;
606
607 WARN_ON_ONCE(tas->window_size > RTW89_TAS_TXPWR_WINDOW);
608
609 if (tas->window_size == window_size)
610 return;
611
612 rtw89_debug(rtwdev, RTW89_DBG_SAR, "tas: window update: %u -> %u\n",
613 tas->window_size, window_size);
614
615 head_idx = (tas->txpwr_tail_idx - window_size + 1 + RTW89_TAS_TXPWR_WINDOW) %
616 RTW89_TAS_TXPWR_WINDOW;
617 for (i = 0; i < window_size; i++) {
618 j = (head_idx + i) % RTW89_TAS_TXPWR_WINDOW;
619 total_txpwr += tas->txpwr_history[j];
620 }
621
622 tas->window_size = window_size;
623 tas->total_txpwr = total_txpwr;
624 tas->txpwr_head_idx = head_idx;
625 }
626
rtw89_tas_history_update(struct rtw89_dev * rtwdev)627 static void rtw89_tas_history_update(struct rtw89_dev *rtwdev)
628 {
629 struct rtw89_bb_ctx *bb = rtw89_get_bb_ctx(rtwdev, RTW89_PHY_0);
630 struct rtw89_env_monitor_info *env = &bb->env_monitor;
631 struct rtw89_tas_info *tas = &rtwdev->tas;
632 u8 tx_ratio = env->ifs_clm_tx_ratio;
633 u64 instant_txpwr, txpwr;
634
635 /* txpwr in unit of linear(mW) multiply by percentage */
636 if (tx_ratio == 0) {
637 /* special case: idle tx power
638 * use -40 dBm * 100 tx ratio
639 */
640 instant_txpwr = rtw89_db_to_linear(-40);
641 txpwr = instant_txpwr * 100;
642 } else {
643 instant_txpwr = tas->instant_txpwr;
644 txpwr = instant_txpwr * tx_ratio;
645 }
646
647 tas->total_txpwr += txpwr - tas->txpwr_history[tas->txpwr_head_idx];
648 tas->total_tx_ratio += tx_ratio - tas->tx_ratio_history[tas->tx_ratio_idx];
649 tas->tx_ratio_history[tas->tx_ratio_idx] = tx_ratio;
650
651 tas->txpwr_head_idx = (tas->txpwr_head_idx + 1) % RTW89_TAS_TXPWR_WINDOW;
652 tas->txpwr_tail_idx = (tas->txpwr_tail_idx + 1) % RTW89_TAS_TXPWR_WINDOW;
653 tas->tx_ratio_idx = (tas->tx_ratio_idx + 1) % RTW89_TAS_TX_RATIO_WINDOW;
654 tas->txpwr_history[tas->txpwr_tail_idx] = txpwr;
655
656 rtw89_debug(rtwdev, RTW89_DBG_SAR,
657 "tas: instant_txpwr: %d, tx_ratio: %u, txpwr: %d\n",
658 rtw89_linear_to_db_quarter(instant_txpwr), tx_ratio,
659 rtw89_linear_to_db_quarter(div_u64(txpwr, PERCENT)));
660 }
661
rtw89_tas_rolling_average(struct rtw89_dev * rtwdev)662 static bool rtw89_tas_rolling_average(struct rtw89_dev *rtwdev)
663 {
664 struct rtw89_tas_info *tas = &rtwdev->tas;
665 s32 dpr_on_threshold, dpr_off_threshold;
666 enum rtw89_tas_state state;
667 u16 tx_ratio_avg;
668 s32 txpwr_avg;
669 u64 linear;
670
671 linear = DIV_ROUND_DOWN_ULL(tas->total_txpwr, tas->window_size * PERCENT);
672 txpwr_avg = rtw89_linear_to_db_quarter(linear);
673 tx_ratio_avg = tas->total_tx_ratio / RTW89_TAS_TX_RATIO_WINDOW;
674 dpr_on_threshold = tas->dpr_on_threshold;
675 dpr_off_threshold = tas->dpr_off_threshold;
676
677 rtw89_debug(rtwdev, RTW89_DBG_SAR,
678 "tas: DPR_ON: %d, DPR_OFF: %d, txpwr_avg: %d, tx_ratio_avg: %u\n",
679 dpr_on_threshold, dpr_off_threshold, txpwr_avg, tx_ratio_avg);
680
681 if (tx_ratio_avg >= RTW89_TAS_TX_RATIO_THRESHOLD)
682 state = RTW89_TAS_STATE_STATIC_SAR;
683 else if (txpwr_avg >= dpr_on_threshold)
684 state = RTW89_TAS_STATE_DPR_ON;
685 else if (txpwr_avg < dpr_off_threshold)
686 state = RTW89_TAS_STATE_DPR_OFF;
687 else
688 return false;
689
690 return __rtw89_tas_state_update(rtwdev, state);
691 }
692
rtw89_tas_init(struct rtw89_dev * rtwdev)693 static void rtw89_tas_init(struct rtw89_dev *rtwdev)
694 {
695 const struct rtw89_chip_info *chip = rtwdev->chip;
696 struct rtw89_tas_info *tas = &rtwdev->tas;
697 const struct rtw89_acpi_policy_tas *ptr;
698 struct rtw89_acpi_dsm_result res = {};
699 int ret;
700
701 if (!chip->support_tas)
702 return;
703
704 ret = rtw89_acpi_evaluate_dsm(rtwdev, RTW89_ACPI_DSM_FUNC_TAS_EN, &res);
705 if (ret) {
706 rtw89_debug(rtwdev, RTW89_DBG_SAR,
707 "acpi: cannot get TAS: %d\n", ret);
708 return;
709 }
710
711 ptr = res.u.policy_tas;
712
713 switch (ptr->enable) {
714 case 0:
715 tas->enable = false;
716 break;
717 case 1:
718 tas->enable = true;
719 break;
720 default:
721 break;
722 }
723
724 if (!tas->enable) {
725 rtw89_debug(rtwdev, RTW89_DBG_SAR, "TAS not enable\n");
726 goto out;
727 }
728
729 tas->enabled_countries = ptr->enabled_countries;
730
731 out:
732 kfree(ptr);
733 }
734
rtw89_tas_reset(struct rtw89_dev * rtwdev,bool force)735 void rtw89_tas_reset(struct rtw89_dev *rtwdev, bool force)
736 {
737 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_CHANCTX_0);
738 struct rtw89_tas_info *tas = &rtwdev->tas;
739 u64 linear;
740 s32 cfg;
741 int i;
742
743 if (!rtw89_tas_is_active(rtwdev))
744 return;
745
746 if (!rtw89_tas_query_sar_config(rtwdev, &cfg))
747 return;
748
749 tas->dpr_on_threshold = cfg - RTW89_TAS_SAR_GAP;
750 tas->dpr_off_threshold = cfg - RTW89_TAS_SAR_GAP - RTW89_TAS_DPR_GAP;
751
752 /* avoid history reset after new SAR apply */
753 if (!force && tas->keep_history)
754 return;
755
756 linear = rtw89_db_quarter_to_linear(cfg) * RTW89_TAS_DFLT_TX_RATIO;
757 for (i = 0; i < RTW89_TAS_TXPWR_WINDOW; i++)
758 tas->txpwr_history[i] = linear;
759
760 for (i = 0; i < RTW89_TAS_TX_RATIO_WINDOW; i++)
761 tas->tx_ratio_history[i] = RTW89_TAS_DFLT_TX_RATIO;
762
763 tas->total_tx_ratio = RTW89_TAS_DFLT_TX_RATIO * RTW89_TAS_TX_RATIO_WINDOW;
764 tas->total_txpwr = linear * RTW89_TAS_TXPWR_WINDOW;
765 tas->window_size = RTW89_TAS_TXPWR_WINDOW;
766 tas->txpwr_head_idx = 0;
767 tas->txpwr_tail_idx = RTW89_TAS_TXPWR_WINDOW - 1;
768 tas->tx_ratio_idx = 0;
769 tas->state = RTW89_TAS_STATE_DPR_OFF;
770 tas->backup_state = RTW89_TAS_STATE_DPR_OFF;
771 tas->keep_history = true;
772
773 rtw89_debug(rtwdev, RTW89_DBG_SAR,
774 "tas: band: %u, freq: %u\n", chan->band_type, chan->freq);
775 }
776
rtw89_tas_track(struct rtw89_dev * rtwdev)777 static bool rtw89_tas_track(struct rtw89_dev *rtwdev)
778 {
779 struct rtw89_tas_info *tas = &rtwdev->tas;
780 struct rtw89_hal *hal = &rtwdev->hal;
781 s32 cfg;
782
783 if (hal->disabled_dm_bitmap & BIT(RTW89_DM_TAS))
784 return false;
785
786 if (!rtw89_tas_is_active(rtwdev))
787 return false;
788
789 if (!rtw89_tas_query_sar_config(rtwdev, &cfg) || tas->block_regd)
790 return __rtw89_tas_state_update(rtwdev, RTW89_TAS_STATE_STATIC_SAR);
791
792 if (tas->pause)
793 return false;
794
795 rtw89_tas_window_update(rtwdev);
796 rtw89_tas_history_update(rtwdev);
797
798 return rtw89_tas_rolling_average(rtwdev);
799 }
800
rtw89_tas_scan(struct rtw89_dev * rtwdev,bool start)801 void rtw89_tas_scan(struct rtw89_dev *rtwdev, bool start)
802 {
803 struct rtw89_tas_info *tas = &rtwdev->tas;
804 s32 cfg;
805
806 if (!rtw89_tas_is_active(rtwdev))
807 return;
808
809 if (!rtw89_tas_query_sar_config(rtwdev, &cfg))
810 return;
811
812 if (start) {
813 tas->backup_state = tas->state;
814 rtw89_tas_state_update(rtwdev, RTW89_TAS_STATE_STATIC_SAR);
815 } else {
816 rtw89_tas_state_update(rtwdev, tas->backup_state);
817 }
818 }
819
rtw89_tas_chanctx_cb(struct rtw89_dev * rtwdev,enum rtw89_chanctx_state state)820 void rtw89_tas_chanctx_cb(struct rtw89_dev *rtwdev,
821 enum rtw89_chanctx_state state)
822 {
823 struct rtw89_tas_info *tas = &rtwdev->tas;
824 s32 cfg;
825
826 if (!rtw89_tas_is_active(rtwdev))
827 return;
828
829 if (!rtw89_tas_query_sar_config(rtwdev, &cfg))
830 return;
831
832 switch (state) {
833 case RTW89_CHANCTX_STATE_MCC_START:
834 tas->pause = true;
835 rtw89_tas_state_update(rtwdev, RTW89_TAS_STATE_STATIC_SAR);
836 break;
837 case RTW89_CHANCTX_STATE_MCC_STOP:
838 tas->pause = false;
839 break;
840 default:
841 break;
842 }
843 }
844 EXPORT_SYMBOL(rtw89_tas_chanctx_cb);
845
rtw89_sar_init(struct rtw89_dev * rtwdev)846 void rtw89_sar_init(struct rtw89_dev *rtwdev)
847 {
848 rtw89_set_sar_from_acpi(rtwdev);
849 rtw89_tas_init(rtwdev);
850 }
851
rtw89_sar_track_acpi(struct rtw89_dev * rtwdev)852 static bool rtw89_sar_track_acpi(struct rtw89_dev *rtwdev)
853 {
854 struct rtw89_sar_cfg_acpi *cfg = &rtwdev->sar.cfg_acpi;
855 struct rtw89_sar_indicator_from_acpi *ind = &cfg->indicator;
856 const enum rtw89_sar_sources src = rtwdev->sar.src;
857 bool changed;
858 int ret;
859
860 lockdep_assert_wiphy(rtwdev->hw->wiphy);
861
862 if (src != RTW89_SAR_SOURCE_ACPI)
863 return false;
864
865 if (!ind->enable_sync)
866 return false;
867
868 ret = rtw89_acpi_evaluate_dynamic_sar_indicator(rtwdev, cfg, &changed);
869 if (likely(!ret))
870 return changed;
871
872 rtw89_debug(rtwdev, RTW89_DBG_SAR,
873 "%s: failed to track indicator: %d; reset and disable\n",
874 __func__, ret);
875
876 memset(ind->tblsel, 0, sizeof(ind->tblsel));
877 ind->enable_sync = false;
878 return true;
879 }
880
rtw89_sar_track(struct rtw89_dev * rtwdev)881 void rtw89_sar_track(struct rtw89_dev *rtwdev)
882 {
883 unsigned int changes = 0;
884
885 changes += rtw89_sar_track_acpi(rtwdev);
886 changes += rtw89_tas_track(rtwdev);
887
888 if (!changes)
889 return;
890
891 rtw89_core_set_chip_txpwr(rtwdev);
892 }
893