1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /* Copyright(c) 2022-2023 Realtek Corporation
3 */
4
5 #include "coex.h"
6 #include "debug.h"
7 #include "mac.h"
8 #include "phy.h"
9 #include "reg.h"
10 #include "rtw8851b.h"
11 #include "rtw8851b_rfk.h"
12 #include "rtw8851b_rfk_table.h"
13 #include "rtw8851b_table.h"
14
15 #define DPK_VER_8851B 0x11
16 #define DPK_KIP_REG_NUM_8851B 8
17 #define DPK_RF_REG_NUM_8851B 4
18 #define DPK_KSET_NUM 4
19 #define RTW8851B_RXK_GROUP_NR 4
20 #define RTW8851B_RXK_GROUP_IDX_NR 2
21 #define RTW8851B_TXK_GROUP_NR 1
22 #define RTW8851B_IQK_VER 0x14
23 #define RTW8851B_IQK_SS 1
24 #define RTW8851B_LOK_GRAM 10
25 #define RTW8851B_TSSI_PATH_NR 1
26
27 #define _TSSI_DE_MASK GENMASK(21, 12)
28
29 enum dpk_id {
30 LBK_RXIQK = 0x06,
31 SYNC = 0x10,
32 MDPK_IDL = 0x11,
33 MDPK_MPA = 0x12,
34 GAIN_LOSS = 0x13,
35 GAIN_CAL = 0x14,
36 DPK_RXAGC = 0x15,
37 KIP_PRESET = 0x16,
38 KIP_RESTORE = 0x17,
39 DPK_TXAGC = 0x19,
40 D_KIP_PRESET = 0x28,
41 D_TXAGC = 0x29,
42 D_RXAGC = 0x2a,
43 D_SYNC = 0x2b,
44 D_GAIN_LOSS = 0x2c,
45 D_MDPK_IDL = 0x2d,
46 D_MDPK_LDL = 0x2e,
47 D_GAIN_NORM = 0x2f,
48 D_KIP_THERMAL = 0x30,
49 D_KIP_RESTORE = 0x31
50 };
51
52 enum dpk_agc_step {
53 DPK_AGC_STEP_SYNC_DGAIN,
54 DPK_AGC_STEP_GAIN_LOSS_IDX,
55 DPK_AGC_STEP_GL_GT_CRITERION,
56 DPK_AGC_STEP_GL_LT_CRITERION,
57 DPK_AGC_STEP_SET_TX_GAIN,
58 };
59
60 enum rtw8851b_iqk_type {
61 ID_TXAGC = 0x0,
62 ID_FLOK_COARSE = 0x1,
63 ID_FLOK_FINE = 0x2,
64 ID_TXK = 0x3,
65 ID_RXAGC = 0x4,
66 ID_RXK = 0x5,
67 ID_NBTXK = 0x6,
68 ID_NBRXK = 0x7,
69 ID_FLOK_VBUFFER = 0x8,
70 ID_A_FLOK_COARSE = 0x9,
71 ID_G_FLOK_COARSE = 0xa,
72 ID_A_FLOK_FINE = 0xb,
73 ID_G_FLOK_FINE = 0xc,
74 ID_IQK_RESTORE = 0x10,
75 };
76
77 enum rf_mode {
78 RF_SHUT_DOWN = 0x0,
79 RF_STANDBY = 0x1,
80 RF_TX = 0x2,
81 RF_RX = 0x3,
82 RF_TXIQK = 0x4,
83 RF_DPK = 0x5,
84 RF_RXK1 = 0x6,
85 RF_RXK2 = 0x7,
86 };
87
88 enum adc_ck {
89 ADC_NA = 0,
90 ADC_480M = 1,
91 ADC_960M = 2,
92 ADC_1920M = 3,
93 };
94
95 enum dac_ck {
96 DAC_40M = 0,
97 DAC_80M = 1,
98 DAC_120M = 2,
99 DAC_160M = 3,
100 DAC_240M = 4,
101 DAC_320M = 5,
102 DAC_480M = 6,
103 DAC_960M = 7,
104 };
105
106 static const u32 _tssi_de_cck_long[RF_PATH_NUM_8851B] = {0x5858};
107 static const u32 _tssi_de_cck_short[RF_PATH_NUM_8851B] = {0x5860};
108 static const u32 _tssi_de_mcs_20m[RF_PATH_NUM_8851B] = {0x5838};
109 static const u32 _tssi_de_mcs_40m[RF_PATH_NUM_8851B] = {0x5840};
110 static const u32 _tssi_de_mcs_80m[RF_PATH_NUM_8851B] = {0x5848};
111 static const u32 _tssi_de_mcs_80m_80m[RF_PATH_NUM_8851B] = {0x5850};
112 static const u32 _tssi_de_mcs_5m[RF_PATH_NUM_8851B] = {0x5828};
113 static const u32 _tssi_de_mcs_10m[RF_PATH_NUM_8851B] = {0x5830};
114 static const u32 g_idxrxgain[RTW8851B_RXK_GROUP_NR] = {0x10e, 0x116, 0x28e, 0x296};
115 static const u32 g_idxattc2[RTW8851B_RXK_GROUP_NR] = {0x0, 0xf, 0x0, 0xf};
116 static const u32 g_idxrxagc[RTW8851B_RXK_GROUP_NR] = {0x0, 0x1, 0x2, 0x3};
117 static const u32 a_idxrxgain[RTW8851B_RXK_GROUP_IDX_NR] = {0x10C, 0x28c};
118 static const u32 a_idxattc2[RTW8851B_RXK_GROUP_IDX_NR] = {0xf, 0xf};
119 static const u32 a_idxrxagc[RTW8851B_RXK_GROUP_IDX_NR] = {0x4, 0x6};
120 static const u32 a_power_range[RTW8851B_TXK_GROUP_NR] = {0x0};
121 static const u32 a_track_range[RTW8851B_TXK_GROUP_NR] = {0x6};
122 static const u32 a_gain_bb[RTW8851B_TXK_GROUP_NR] = {0x0a};
123 static const u32 a_itqt[RTW8851B_TXK_GROUP_NR] = {0x12};
124 static const u32 g_power_range[RTW8851B_TXK_GROUP_NR] = {0x0};
125 static const u32 g_track_range[RTW8851B_TXK_GROUP_NR] = {0x6};
126 static const u32 g_gain_bb[RTW8851B_TXK_GROUP_NR] = {0x10};
127 static const u32 g_itqt[RTW8851B_TXK_GROUP_NR] = {0x12};
128
129 static const u32 rtw8851b_backup_bb_regs[] = {0xc0d4, 0xc0d8, 0xc0c4, 0xc0ec, 0xc0e8};
130 static const u32 rtw8851b_backup_rf_regs[] = {
131 0xef, 0xde, 0x0, 0x1e, 0x2, 0x85, 0x90, 0x5};
132
133 #define BACKUP_BB_REGS_NR ARRAY_SIZE(rtw8851b_backup_bb_regs)
134 #define BACKUP_RF_REGS_NR ARRAY_SIZE(rtw8851b_backup_rf_regs)
135
136 static const u32 dpk_kip_reg[DPK_KIP_REG_NUM_8851B] = {
137 0x813c, 0x8124, 0xc0ec, 0xc0e8, 0xc0c4, 0xc0d4, 0xc0d8, 0x12a0};
138 static const u32 dpk_rf_reg[DPK_RF_REG_NUM_8851B] = {0xde, 0x8f, 0x5, 0x10005};
139
140 static void _set_ch(struct rtw89_dev *rtwdev, u32 val);
141
_rxk_5ghz_group_from_idx(u8 idx)142 static u8 _rxk_5ghz_group_from_idx(u8 idx)
143 {
144 /* There are four RXK groups (RTW8851B_RXK_GROUP_NR), but only group 0
145 * and 2 are used in 5 GHz band, so reduce elements to 2.
146 */
147 if (idx < RTW8851B_RXK_GROUP_IDX_NR)
148 return idx * 2;
149
150 return 0;
151 }
152
_kpath(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx)153 static u8 _kpath(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx)
154 {
155 return RF_A;
156 }
157
_adc_fifo_rst(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx,u8 path)158 static void _adc_fifo_rst(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx,
159 u8 path)
160 {
161 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_RXK, 0x0101);
162 fsleep(10);
163 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_RXK, 0x1111);
164 }
165
_rfk_rf_direct_cntrl(struct rtw89_dev * rtwdev,enum rtw89_rf_path path,bool is_bybb)166 static void _rfk_rf_direct_cntrl(struct rtw89_dev *rtwdev,
167 enum rtw89_rf_path path, bool is_bybb)
168 {
169 if (is_bybb)
170 rtw89_write_rf(rtwdev, path, RR_RSV1, RR_RSV1_RST, 0x1);
171 else
172 rtw89_write_rf(rtwdev, path, RR_RSV1, RR_RSV1_RST, 0x0);
173 }
174
_rfk_drf_direct_cntrl(struct rtw89_dev * rtwdev,enum rtw89_rf_path path,bool is_bybb)175 static void _rfk_drf_direct_cntrl(struct rtw89_dev *rtwdev,
176 enum rtw89_rf_path path, bool is_bybb)
177 {
178 if (is_bybb)
179 rtw89_write_rf(rtwdev, path, RR_BBDC, RR_BBDC_SEL, 0x1);
180 else
181 rtw89_write_rf(rtwdev, path, RR_BBDC, RR_BBDC_SEL, 0x0);
182 }
183
_txck_force(struct rtw89_dev * rtwdev,enum rtw89_rf_path path,bool force,enum dac_ck ck)184 static void _txck_force(struct rtw89_dev *rtwdev, enum rtw89_rf_path path,
185 bool force, enum dac_ck ck)
186 {
187 rtw89_phy_write32_mask(rtwdev, R_P0_RXCK | (path << 13), B_P0_TXCK_ON, 0x0);
188
189 if (!force)
190 return;
191
192 rtw89_phy_write32_mask(rtwdev, R_P0_RXCK | (path << 13), B_P0_TXCK_VAL, ck);
193 rtw89_phy_write32_mask(rtwdev, R_P0_RXCK | (path << 13), B_P0_TXCK_ON, 0x1);
194 }
195
_rxck_force(struct rtw89_dev * rtwdev,enum rtw89_rf_path path,bool force,enum adc_ck ck)196 static void _rxck_force(struct rtw89_dev *rtwdev, enum rtw89_rf_path path,
197 bool force, enum adc_ck ck)
198 {
199 static const u32 ck960_8851b[] = {0x8, 0x2, 0x2, 0x4, 0xf, 0xa, 0x93};
200 static const u32 ck1920_8851b[] = {0x9, 0x0, 0x0, 0x3, 0xf, 0xa, 0x49};
201 const u32 *data;
202
203 rtw89_phy_write32_mask(rtwdev, R_P0_RXCK | (path << 13), B_P0_RXCK_ON, 0x0);
204 if (!force)
205 return;
206
207 rtw89_phy_write32_mask(rtwdev, R_P0_RXCK | (path << 13), B_P0_RXCK_VAL, ck);
208 rtw89_phy_write32_mask(rtwdev, R_P0_RXCK | (path << 13), B_P0_RXCK_ON, 0x1);
209
210 switch (ck) {
211 case ADC_960M:
212 data = ck960_8851b;
213 break;
214 case ADC_1920M:
215 default:
216 data = ck1920_8851b;
217 break;
218 }
219
220 rtw89_phy_write32_mask(rtwdev, R_P0_CFCH_BW0 | (path << 8), B_P0_CFCH_CTL, data[0]);
221 rtw89_phy_write32_mask(rtwdev, R_P0_CFCH_BW0 | (path << 8), B_P0_CFCH_EN, data[1]);
222 rtw89_phy_write32_mask(rtwdev, R_P0_CFCH_BW0 | (path << 8), B_P0_CFCH_BW0, data[2]);
223 rtw89_phy_write32_mask(rtwdev, R_P0_CFCH_BW1 | (path << 8), B_P0_CFCH_BW1, data[3]);
224 rtw89_phy_write32_mask(rtwdev, R_DRCK | (path << 8), B_DRCK_MUL, data[4]);
225 rtw89_phy_write32_mask(rtwdev, R_ADCMOD | (path << 8), B_ADCMOD_LP, data[5]);
226 rtw89_phy_write32_mask(rtwdev, R_P0_RXCK | (path << 8), B_P0_RXCK_ADJ, data[6]);
227 }
228
_wait_rx_mode(struct rtw89_dev * rtwdev,u8 kpath)229 static void _wait_rx_mode(struct rtw89_dev *rtwdev, u8 kpath)
230 {
231 u32 rf_mode;
232 u8 path;
233 int ret;
234
235 for (path = 0; path < RF_PATH_MAX; path++) {
236 if (!(kpath & BIT(path)))
237 continue;
238
239 ret = read_poll_timeout_atomic(rtw89_read_rf, rf_mode,
240 rf_mode != 2, 2, 5000, false,
241 rtwdev, path, 0x00, RR_MOD_MASK);
242 rtw89_debug(rtwdev, RTW89_DBG_RFK,
243 "[RFK] Wait S%d to Rx mode!! (ret = %d)\n",
244 path, ret);
245 }
246 }
247
_dack_reset(struct rtw89_dev * rtwdev,enum rtw89_rf_path path)248 static void _dack_reset(struct rtw89_dev *rtwdev, enum rtw89_rf_path path)
249 {
250 rtw89_phy_write32_mask(rtwdev, R_DCOF0, B_DCOF0_RST, 0x0);
251 rtw89_phy_write32_mask(rtwdev, R_DCOF0, B_DCOF0_RST, 0x1);
252 }
253
_drck(struct rtw89_dev * rtwdev)254 static void _drck(struct rtw89_dev *rtwdev)
255 {
256 u32 rck_d;
257 u32 val;
258 int ret;
259
260 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]Ddie RCK start!!!\n");
261
262 rtw89_phy_write32_mask(rtwdev, R_DRCK, B_DRCK_IDLE, 0x1);
263 rtw89_phy_write32_mask(rtwdev, R_DRCK, B_DRCK_EN, 0x1);
264
265 ret = read_poll_timeout_atomic(rtw89_phy_read32_mask, val, val,
266 1, 10000, false,
267 rtwdev, R_DRCK_RES, B_DRCK_POL);
268 if (ret)
269 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]DRCK timeout\n");
270
271 rtw89_phy_write32_mask(rtwdev, R_DRCK, B_DRCK_EN, 0x0);
272 rtw89_phy_write32_mask(rtwdev, R_DRCK_FH, B_DRCK_LAT, 0x1);
273 udelay(1);
274 rtw89_phy_write32_mask(rtwdev, R_DRCK_FH, B_DRCK_LAT, 0x0);
275
276 rck_d = rtw89_phy_read32_mask(rtwdev, R_DRCK_RES, 0x7c00);
277 rtw89_phy_write32_mask(rtwdev, R_DRCK, B_DRCK_IDLE, 0x0);
278 rtw89_phy_write32_mask(rtwdev, R_DRCK, B_DRCK_VAL, rck_d);
279
280 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]0xc0c4 = 0x%x\n",
281 rtw89_phy_read32_mask(rtwdev, R_DRCK, MASKDWORD));
282 }
283
_addck_backup(struct rtw89_dev * rtwdev)284 static void _addck_backup(struct rtw89_dev *rtwdev)
285 {
286 struct rtw89_dack_info *dack = &rtwdev->dack;
287
288 rtw89_phy_write32_mask(rtwdev, R_ADDCK0, B_ADDCK0, 0x0);
289
290 dack->addck_d[0][0] = rtw89_phy_read32_mask(rtwdev, R_ADDCKR0, B_ADDCKR0_A0);
291 dack->addck_d[0][1] = rtw89_phy_read32_mask(rtwdev, R_ADDCKR0, B_ADDCKR0_A1);
292 }
293
_addck_reload(struct rtw89_dev * rtwdev)294 static void _addck_reload(struct rtw89_dev *rtwdev)
295 {
296 struct rtw89_dack_info *dack = &rtwdev->dack;
297
298 rtw89_phy_write32_mask(rtwdev, R_ADDCK0_RL, B_ADDCK0_RL1, dack->addck_d[0][0]);
299 rtw89_phy_write32_mask(rtwdev, R_ADDCK0_RL, B_ADDCK0_RL0, dack->addck_d[0][1]);
300 rtw89_phy_write32_mask(rtwdev, R_ADDCK0_RL, B_ADDCK0_RLS, 0x3);
301 }
302
_dack_backup_s0(struct rtw89_dev * rtwdev)303 static void _dack_backup_s0(struct rtw89_dev *rtwdev)
304 {
305 struct rtw89_dack_info *dack = &rtwdev->dack;
306 u8 i;
307
308 rtw89_phy_write32_mask(rtwdev, R_P0_NRBW, B_P0_NRBW_DBG, 0x1);
309
310 for (i = 0; i < RTW89_DACK_MSBK_NR; i++) {
311 rtw89_phy_write32_mask(rtwdev, R_DCOF0, B_DCOF0_V, i);
312 dack->msbk_d[0][0][i] =
313 rtw89_phy_read32_mask(rtwdev, R_DACK_S0P2, B_DACK_S0M0);
314
315 rtw89_phy_write32_mask(rtwdev, R_DCOF8, B_DCOF8_V, i);
316 dack->msbk_d[0][1][i] =
317 rtw89_phy_read32_mask(rtwdev, R_DACK_S0P3, B_DACK_S0M1);
318 }
319
320 dack->biask_d[0][0] =
321 rtw89_phy_read32_mask(rtwdev, R_DACK_BIAS00, B_DACK_BIAS00);
322 dack->biask_d[0][1] =
323 rtw89_phy_read32_mask(rtwdev, R_DACK_BIAS01, B_DACK_BIAS01);
324 dack->dadck_d[0][0] =
325 rtw89_phy_read32_mask(rtwdev, R_DACK_DADCK00, B_DACK_DADCK00) + 24;
326 dack->dadck_d[0][1] =
327 rtw89_phy_read32_mask(rtwdev, R_DACK_DADCK01, B_DACK_DADCK01) + 24;
328 }
329
_dack_reload_by_path(struct rtw89_dev * rtwdev,enum rtw89_rf_path path,u8 index)330 static void _dack_reload_by_path(struct rtw89_dev *rtwdev,
331 enum rtw89_rf_path path, u8 index)
332 {
333 struct rtw89_dack_info *dack = &rtwdev->dack;
334 u32 idx_offset, path_offset;
335 u32 offset, reg;
336 u32 tmp;
337 u8 i;
338
339 if (index == 0)
340 idx_offset = 0;
341 else
342 idx_offset = 0x14;
343
344 if (path == RF_PATH_A)
345 path_offset = 0;
346 else
347 path_offset = 0x28;
348
349 offset = idx_offset + path_offset;
350
351 rtw89_phy_write32_mask(rtwdev, R_DCOF1, B_DCOF1_RST, 0x1);
352 rtw89_phy_write32_mask(rtwdev, R_DCOF9, B_DCOF9_RST, 0x1);
353
354 /* msbk_d: 15/14/13/12 */
355 tmp = 0x0;
356 for (i = 0; i < 4; i++)
357 tmp |= dack->msbk_d[path][index][i + 12] << (i * 8);
358 reg = 0xc200 + offset;
359 rtw89_phy_write32(rtwdev, reg, tmp);
360 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]0x%x=0x%x\n", reg,
361 rtw89_phy_read32_mask(rtwdev, reg, MASKDWORD));
362
363 /* msbk_d: 11/10/9/8 */
364 tmp = 0x0;
365 for (i = 0; i < 4; i++)
366 tmp |= dack->msbk_d[path][index][i + 8] << (i * 8);
367 reg = 0xc204 + offset;
368 rtw89_phy_write32(rtwdev, reg, tmp);
369 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]0x%x=0x%x\n", reg,
370 rtw89_phy_read32_mask(rtwdev, reg, MASKDWORD));
371
372 /* msbk_d: 7/6/5/4 */
373 tmp = 0x0;
374 for (i = 0; i < 4; i++)
375 tmp |= dack->msbk_d[path][index][i + 4] << (i * 8);
376 reg = 0xc208 + offset;
377 rtw89_phy_write32(rtwdev, reg, tmp);
378 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]0x%x=0x%x\n", reg,
379 rtw89_phy_read32_mask(rtwdev, reg, MASKDWORD));
380
381 /* msbk_d: 3/2/1/0 */
382 tmp = 0x0;
383 for (i = 0; i < 4; i++)
384 tmp |= dack->msbk_d[path][index][i] << (i * 8);
385 reg = 0xc20c + offset;
386 rtw89_phy_write32(rtwdev, reg, tmp);
387 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]0x%x=0x%x\n", reg,
388 rtw89_phy_read32_mask(rtwdev, reg, MASKDWORD));
389
390 /* dadak_d/biask_d */
391 tmp = 0x0;
392 tmp = (dack->biask_d[path][index] << 22) |
393 (dack->dadck_d[path][index] << 14);
394 reg = 0xc210 + offset;
395 rtw89_phy_write32(rtwdev, reg, tmp);
396 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]0x%x=0x%x\n", reg,
397 rtw89_phy_read32_mask(rtwdev, reg, MASKDWORD));
398
399 rtw89_phy_write32_mask(rtwdev, R_DACKN0_CTL + offset, B_DACKN0_EN, 0x1);
400 }
401
_dack_reload(struct rtw89_dev * rtwdev,enum rtw89_rf_path path)402 static void _dack_reload(struct rtw89_dev *rtwdev, enum rtw89_rf_path path)
403 {
404 u8 index;
405
406 for (index = 0; index < 2; index++)
407 _dack_reload_by_path(rtwdev, path, index);
408 }
409
_addck(struct rtw89_dev * rtwdev)410 static void _addck(struct rtw89_dev *rtwdev)
411 {
412 struct rtw89_dack_info *dack = &rtwdev->dack;
413 u32 val;
414 int ret;
415
416 rtw89_phy_write32_mask(rtwdev, R_ADDCK0, B_ADDCK0_RST, 0x1);
417 rtw89_phy_write32_mask(rtwdev, R_ADDCK0, B_ADDCK0_EN, 0x1);
418 rtw89_phy_write32_mask(rtwdev, R_ADDCK0, B_ADDCK0_EN, 0x0);
419 udelay(1);
420 rtw89_phy_write32_mask(rtwdev, R_ADDCK0, B_ADDCK0, 0x1);
421
422 ret = read_poll_timeout_atomic(rtw89_phy_read32_mask, val, val,
423 1, 10000, false,
424 rtwdev, R_ADDCKR0, BIT(0));
425 if (ret) {
426 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S0 ADDCK timeout\n");
427 dack->addck_timeout[0] = true;
428 }
429
430 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]ADDCK ret = %d\n", ret);
431
432 rtw89_phy_write32_mask(rtwdev, R_ADDCK0, B_ADDCK0_RST, 0x0);
433 }
434
_new_dadck(struct rtw89_dev * rtwdev)435 static void _new_dadck(struct rtw89_dev *rtwdev)
436 {
437 struct rtw89_dack_info *dack = &rtwdev->dack;
438 u32 i_dc, q_dc, ic, qc;
439 u32 val;
440 int ret;
441
442 rtw89_rfk_parser(rtwdev, &rtw8851b_dadck_setup_defs_tbl);
443
444 ret = read_poll_timeout_atomic(rtw89_phy_read32_mask, val, val,
445 1, 10000, false,
446 rtwdev, R_ADDCKR0, BIT(0));
447 if (ret) {
448 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S0 DADCK timeout\n");
449 dack->addck_timeout[0] = true;
450 }
451
452 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]DADCK ret = %d\n", ret);
453
454 rtw89_phy_write32_mask(rtwdev, R_ADDCK0, B_ADDCK0_IQ, 0x0);
455 i_dc = rtw89_phy_read32_mask(rtwdev, R_ADDCKR0, B_ADDCKR0_DC);
456 rtw89_phy_write32_mask(rtwdev, R_ADDCK0, B_ADDCK0_IQ, 0x1);
457 q_dc = rtw89_phy_read32_mask(rtwdev, R_ADDCKR0, B_ADDCKR0_DC);
458
459 ic = 0x80 - sign_extend32(i_dc, 11) * 6;
460 qc = 0x80 - sign_extend32(q_dc, 11) * 6;
461
462 rtw89_debug(rtwdev, RTW89_DBG_RFK,
463 "[DACK]before DADCK, i_dc=0x%x, q_dc=0x%x\n", i_dc, q_dc);
464
465 dack->dadck_d[0][0] = ic;
466 dack->dadck_d[0][1] = qc;
467
468 rtw89_phy_write32_mask(rtwdev, R_DACKN0_CTL, B_DACKN0_V, dack->dadck_d[0][0]);
469 rtw89_phy_write32_mask(rtwdev, R_DACKN1_CTL, B_DACKN1_V, dack->dadck_d[0][1]);
470 rtw89_debug(rtwdev, RTW89_DBG_RFK,
471 "[DACK]after DADCK, 0xc210=0x%x, 0xc224=0x%x\n",
472 rtw89_phy_read32_mask(rtwdev, R_DACKN0_CTL, MASKDWORD),
473 rtw89_phy_read32_mask(rtwdev, R_DACKN1_CTL, MASKDWORD));
474
475 rtw89_rfk_parser(rtwdev, &rtw8851b_dadck_post_defs_tbl);
476 }
477
_dack_s0_poll(struct rtw89_dev * rtwdev)478 static bool _dack_s0_poll(struct rtw89_dev *rtwdev)
479 {
480 if (rtw89_phy_read32_mask(rtwdev, R_DACK_S0P0, B_DACK_S0P0_OK) == 0 ||
481 rtw89_phy_read32_mask(rtwdev, R_DACK_S0P1, B_DACK_S0P1_OK) == 0 ||
482 rtw89_phy_read32_mask(rtwdev, R_DACK_S0P2, B_DACK_S0P2_OK) == 0 ||
483 rtw89_phy_read32_mask(rtwdev, R_DACK_S0P3, B_DACK_S0P3_OK) == 0)
484 return false;
485
486 return true;
487 }
488
_dack_s0(struct rtw89_dev * rtwdev)489 static void _dack_s0(struct rtw89_dev *rtwdev)
490 {
491 struct rtw89_dack_info *dack = &rtwdev->dack;
492 bool done;
493 int ret;
494
495 rtw89_rfk_parser(rtwdev, &rtw8851b_dack_s0_1_defs_tbl);
496 _dack_reset(rtwdev, RF_PATH_A);
497 rtw89_phy_write32_mask(rtwdev, R_DCOF1, B_DCOF1_S, 0x1);
498
499 ret = read_poll_timeout_atomic(_dack_s0_poll, done, done,
500 1, 10000, false, rtwdev);
501 if (ret) {
502 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S0 DACK timeout\n");
503 dack->msbk_timeout[0] = true;
504 }
505
506 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]DACK ret = %d\n", ret);
507
508 rtw89_rfk_parser(rtwdev, &rtw8851b_dack_s0_2_defs_tbl);
509
510 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]after S0 DADCK\n");
511
512 _dack_backup_s0(rtwdev);
513 _dack_reload(rtwdev, RF_PATH_A);
514
515 rtw89_phy_write32_mask(rtwdev, R_P0_NRBW, B_P0_NRBW_DBG, 0x0);
516 }
517
_dack(struct rtw89_dev * rtwdev)518 static void _dack(struct rtw89_dev *rtwdev)
519 {
520 _dack_s0(rtwdev);
521 }
522
_dack_dump(struct rtw89_dev * rtwdev)523 static void _dack_dump(struct rtw89_dev *rtwdev)
524 {
525 struct rtw89_dack_info *dack = &rtwdev->dack;
526 u8 i;
527 u8 t;
528
529 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S0 ADC_DCK ic = 0x%x, qc = 0x%x\n",
530 dack->addck_d[0][0], dack->addck_d[0][1]);
531 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S0 DAC_DCK ic = 0x%x, qc = 0x%x\n",
532 dack->dadck_d[0][0], dack->dadck_d[0][1]);
533 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S0 biask ic = 0x%x, qc = 0x%x\n",
534 dack->biask_d[0][0], dack->biask_d[0][1]);
535
536 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S0 MSBK ic:\n");
537 for (i = 0; i < RTW89_DACK_MSBK_NR; i++) {
538 t = dack->msbk_d[0][0][i];
539 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]0x%x\n", t);
540 }
541
542 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S0 MSBK qc:\n");
543 for (i = 0; i < RTW89_DACK_MSBK_NR; i++) {
544 t = dack->msbk_d[0][1][i];
545 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]0x%x\n", t);
546 }
547 }
548
_dack_manual_off(struct rtw89_dev * rtwdev)549 static void _dack_manual_off(struct rtw89_dev *rtwdev)
550 {
551 rtw89_rfk_parser(rtwdev, &rtw8851b_dack_manual_off_defs_tbl);
552 }
553
_dac_cal(struct rtw89_dev * rtwdev,bool force)554 static void _dac_cal(struct rtw89_dev *rtwdev, bool force)
555 {
556 struct rtw89_dack_info *dack = &rtwdev->dack;
557 u32 rf0_0;
558
559 dack->dack_done = false;
560
561 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]DACK 0x2\n");
562 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]DACK start!!!\n");
563 rf0_0 = rtw89_read_rf(rtwdev, RF_PATH_A, RR_MOD, RFREG_MASK);
564 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]RF0=0x%x\n", rf0_0);
565
566 _drck(rtwdev);
567 _dack_manual_off(rtwdev);
568 rtw89_write_rf(rtwdev, RF_PATH_A, RR_MOD, RFREG_MASK, 0x337e1);
569 rtw89_write_rf(rtwdev, RF_PATH_A, RR_RSV1, RR_RSV1_RST, 0x0);
570
571 _addck(rtwdev);
572 _addck_backup(rtwdev);
573 _addck_reload(rtwdev);
574 rtw89_write_rf(rtwdev, RF_PATH_A, RR_MOD, RFREG_MASK, 0x40001);
575
576 _dack(rtwdev);
577 _new_dadck(rtwdev);
578 _dack_dump(rtwdev);
579 rtw89_write_rf(rtwdev, RF_PATH_A, RR_RSV1, RR_RSV1_RST, 0x1);
580
581 dack->dack_done = true;
582 dack->dack_cnt++;
583 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]DACK finish!!!\n");
584 }
585
_rx_dck_info(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy,enum rtw89_rf_path path,bool is_afe,enum rtw89_chanctx_idx chanctx_idx)586 static void _rx_dck_info(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
587 enum rtw89_rf_path path, bool is_afe,
588 enum rtw89_chanctx_idx chanctx_idx)
589 {
590 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, chanctx_idx);
591
592 rtw89_debug(rtwdev, RTW89_DBG_RFK,
593 "[RX_DCK] ==== S%d RX DCK (%s / CH%d / %s / by %s)====\n", path,
594 chan->band_type == RTW89_BAND_2G ? "2G" :
595 chan->band_type == RTW89_BAND_5G ? "5G" : "6G",
596 chan->channel,
597 chan->band_width == RTW89_CHANNEL_WIDTH_20 ? "20M" :
598 chan->band_width == RTW89_CHANNEL_WIDTH_40 ? "40M" : "80M",
599 is_afe ? "AFE" : "RFC");
600 }
601
_rxbb_ofst_swap(struct rtw89_dev * rtwdev,enum rtw89_rf_path path,u8 rf_mode)602 static void _rxbb_ofst_swap(struct rtw89_dev *rtwdev, enum rtw89_rf_path path, u8 rf_mode)
603 {
604 u32 val, val_i, val_q;
605
606 val_i = rtw89_read_rf(rtwdev, path, RR_DCK, RR_DCK_S1);
607 val_q = rtw89_read_rf(rtwdev, path, RR_DCK1, RR_DCK1_S1);
608
609 val = val_q << 4 | val_i;
610
611 rtw89_write_rf(rtwdev, path, RR_LUTWE2, RR_LUTWE2_DIS, 0x1);
612 rtw89_write_rf(rtwdev, path, RR_LUTWA, RFREG_MASK, rf_mode);
613 rtw89_write_rf(rtwdev, path, RR_LUTWD0, RFREG_MASK, val);
614 rtw89_write_rf(rtwdev, path, RR_LUTWE2, RR_LUTWE2_DIS, 0x0);
615
616 rtw89_debug(rtwdev, RTW89_DBG_RFK,
617 "[RX_DCK] val_i = 0x%x, val_q = 0x%x, 0x3F = 0x%x\n",
618 val_i, val_q, val);
619 }
620
_set_rx_dck(struct rtw89_dev * rtwdev,enum rtw89_rf_path path,u8 rf_mode)621 static void _set_rx_dck(struct rtw89_dev *rtwdev, enum rtw89_rf_path path, u8 rf_mode)
622 {
623 u32 val;
624 int ret;
625
626 rtw89_write_rf(rtwdev, path, RR_DCK, RR_DCK_LV, 0x0);
627 rtw89_write_rf(rtwdev, path, RR_DCK, RR_DCK_LV, 0x1);
628
629 ret = read_poll_timeout_atomic(rtw89_read_rf, val, val,
630 2, 2000, false,
631 rtwdev, path, RR_DCK, BIT(8));
632
633 rtw89_write_rf(rtwdev, path, RR_DCK, RR_DCK_LV, 0x0);
634
635 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[RX_DCK] S%d RXDCK finish (ret = %d)\n",
636 path, ret);
637
638 _rxbb_ofst_swap(rtwdev, path, rf_mode);
639 }
640
_rx_dck(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy,bool is_afe,enum rtw89_chanctx_idx chanctx_idx)641 static void _rx_dck(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy, bool is_afe,
642 enum rtw89_chanctx_idx chanctx_idx)
643 {
644 u32 rf_reg5;
645 u8 path;
646
647 rtw89_debug(rtwdev, RTW89_DBG_RFK,
648 "[RX_DCK] ****** RXDCK Start (Ver: 0x%x, Cv: %d) ******\n",
649 0x2, rtwdev->hal.cv);
650
651 for (path = 0; path < RF_PATH_NUM_8851B; path++) {
652 _rx_dck_info(rtwdev, phy, path, is_afe, chanctx_idx);
653
654 rf_reg5 = rtw89_read_rf(rtwdev, path, RR_RSV1, RFREG_MASK);
655
656 if (rtwdev->is_tssi_mode[path])
657 rtw89_phy_write32_mask(rtwdev,
658 R_P0_TSSI_TRK + (path << 13),
659 B_P0_TSSI_TRK_EN, 0x1);
660
661 rtw89_write_rf(rtwdev, path, RR_RSV1, RR_RSV1_RST, 0x0);
662 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_MASK, RF_RX);
663 _set_rx_dck(rtwdev, path, RF_RX);
664 rtw89_write_rf(rtwdev, path, RR_RSV1, RFREG_MASK, rf_reg5);
665
666 if (rtwdev->is_tssi_mode[path])
667 rtw89_phy_write32_mask(rtwdev,
668 R_P0_TSSI_TRK + (path << 13),
669 B_P0_TSSI_TRK_EN, 0x0);
670 }
671 }
672
_iqk_sram(struct rtw89_dev * rtwdev,u8 path)673 static void _iqk_sram(struct rtw89_dev *rtwdev, u8 path)
674 {
675 u32 i;
676
677 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]===>%s\n", __func__);
678
679 rtw89_phy_write32_mask(rtwdev, R_KIP_RPT1, MASKDWORD, 0x00020000);
680 rtw89_phy_write32_mask(rtwdev, R_MDPK_RX_DCK, MASKDWORD, 0x80000000);
681 rtw89_phy_write32_mask(rtwdev, R_SRAM_IQRX2, MASKDWORD, 0x00000080);
682 rtw89_phy_write32_mask(rtwdev, R_SRAM_IQRX, MASKDWORD, 0x00010000);
683 rtw89_phy_write32_mask(rtwdev, R_IQK_DIF4, B_IQK_DIF4_TXT, 0x009);
684
685 for (i = 0; i <= 0x9f; i++) {
686 rtw89_phy_write32_mask(rtwdev, R_SRAM_IQRX, MASKDWORD,
687 0x00010000 + i);
688 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]0x%x\n",
689 rtw89_phy_read32_mask(rtwdev, R_RPT_COM, B_PRT_COM_DCI));
690 }
691
692 for (i = 0; i <= 0x9f; i++) {
693 rtw89_phy_write32_mask(rtwdev, R_SRAM_IQRX, MASKDWORD,
694 0x00010000 + i);
695 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]0x%x\n",
696 rtw89_phy_read32_mask(rtwdev, R_RPT_COM, B_PRT_COM_DCQ));
697 }
698
699 rtw89_phy_write32_mask(rtwdev, R_SRAM_IQRX2, MASKDWORD, 0x00000000);
700 rtw89_phy_write32_mask(rtwdev, R_SRAM_IQRX, MASKDWORD, 0x00000000);
701 }
702
_iqk_rxk_setting(struct rtw89_dev * rtwdev,u8 path)703 static void _iqk_rxk_setting(struct rtw89_dev *rtwdev, u8 path)
704 {
705 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_MASK, 0xc);
706 rtw89_write_rf(rtwdev, path, RR_RXKPLL, RR_RXKPLL_POW, 0x0);
707 rtw89_write_rf(rtwdev, path, RR_RXKPLL, RR_RXKPLL_POW, 0x1);
708 }
709
_iqk_check_cal(struct rtw89_dev * rtwdev,u8 path)710 static bool _iqk_check_cal(struct rtw89_dev *rtwdev, u8 path)
711 {
712 bool fail1 = false, fail2 = false;
713 u32 val;
714 int ret;
715
716 ret = read_poll_timeout_atomic(rtw89_phy_read32_mask, val, val == 0x55,
717 10, 8200, false,
718 rtwdev, 0xbff8, MASKBYTE0);
719 if (ret) {
720 fail1 = true;
721 rtw89_debug(rtwdev, RTW89_DBG_RFK,
722 "[IQK]NCTL1 IQK timeout!!!\n");
723 }
724
725 fsleep(10);
726
727 ret = read_poll_timeout_atomic(rtw89_phy_read32_mask, val, val == 0x8000,
728 10, 200, false,
729 rtwdev, R_RPT_COM, B_RPT_COM_RDY);
730 if (ret) {
731 fail2 = true;
732 rtw89_debug(rtwdev, RTW89_DBG_RFK,
733 "[IQK]NCTL2 IQK timeout!!!\n");
734 }
735
736 fsleep(10);
737 rtw89_phy_write32_mask(rtwdev, R_NCTL_N1, MASKBYTE0, 0x0);
738
739 rtw89_debug(rtwdev, RTW89_DBG_RFK,
740 "[IQK]S%x, ret = %d, notready = %x fail=%d,%d\n",
741 path, ret, fail1 || fail2, fail1, fail2);
742
743 return fail1 || fail2;
744 }
745
_iqk_one_shot(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx,u8 path,u8 ktype)746 static bool _iqk_one_shot(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx,
747 u8 path, u8 ktype)
748 {
749 struct rtw89_iqk_info *iqk_info = &rtwdev->iqk;
750 bool notready;
751 u32 iqk_cmd;
752
753 switch (ktype) {
754 case ID_A_FLOK_COARSE:
755 rtw89_debug(rtwdev, RTW89_DBG_RFK,
756 "[IQK]============ S%d ID_A_FLOK_COARSE ============\n", path);
757 rtw89_phy_write32_mask(rtwdev, R_UPD_CLK, B_IQK_RFC_ON, 0x1);
758 iqk_cmd = 0x108 | (1 << (4 + path));
759 break;
760 case ID_G_FLOK_COARSE:
761 rtw89_debug(rtwdev, RTW89_DBG_RFK,
762 "[IQK]============ S%d ID_G_FLOK_COARSE ============\n", path);
763 rtw89_phy_write32_mask(rtwdev, R_UPD_CLK, B_IQK_RFC_ON, 0x1);
764 iqk_cmd = 0x108 | (1 << (4 + path));
765 break;
766 case ID_A_FLOK_FINE:
767 rtw89_debug(rtwdev, RTW89_DBG_RFK,
768 "[IQK]============ S%d ID_A_FLOK_FINE ============\n", path);
769 rtw89_phy_write32_mask(rtwdev, R_UPD_CLK, B_IQK_RFC_ON, 0x1);
770 iqk_cmd = 0x308 | (1 << (4 + path));
771 break;
772 case ID_G_FLOK_FINE:
773 rtw89_debug(rtwdev, RTW89_DBG_RFK,
774 "[IQK]============ S%d ID_G_FLOK_FINE ============\n", path);
775 rtw89_phy_write32_mask(rtwdev, R_UPD_CLK, B_IQK_RFC_ON, 0x1);
776 iqk_cmd = 0x308 | (1 << (4 + path));
777 break;
778 case ID_TXK:
779 rtw89_debug(rtwdev, RTW89_DBG_RFK,
780 "[IQK]============ S%d ID_TXK ============\n", path);
781 rtw89_phy_write32_mask(rtwdev, R_UPD_CLK, B_IQK_RFC_ON, 0x0);
782 iqk_cmd = 0x008 | (1 << (path + 4)) |
783 (((0x8 + iqk_info->iqk_bw[path]) & 0xf) << 8);
784 break;
785 case ID_RXAGC:
786 rtw89_debug(rtwdev, RTW89_DBG_RFK,
787 "[IQK]============ S%d ID_RXAGC ============\n", path);
788 rtw89_phy_write32_mask(rtwdev, R_UPD_CLK, B_IQK_RFC_ON, 0x1);
789 iqk_cmd = 0x708 | (1 << (4 + path)) | (path << 1);
790 break;
791 case ID_RXK:
792 rtw89_debug(rtwdev, RTW89_DBG_RFK,
793 "[IQK]============ S%d ID_RXK ============\n", path);
794 rtw89_phy_write32_mask(rtwdev, R_UPD_CLK, B_IQK_RFC_ON, 0x1);
795 iqk_cmd = 0x008 | (1 << (path + 4)) |
796 (((0xc + iqk_info->iqk_bw[path]) & 0xf) << 8);
797 break;
798 case ID_NBTXK:
799 rtw89_debug(rtwdev, RTW89_DBG_RFK,
800 "[IQK]============ S%d ID_NBTXK ============\n", path);
801 rtw89_phy_write32_mask(rtwdev, R_UPD_CLK, B_IQK_RFC_ON, 0x0);
802 rtw89_phy_write32_mask(rtwdev, R_IQK_DIF4, B_IQK_DIF4_TXT,
803 0x00b);
804 iqk_cmd = 0x408 | (1 << (4 + path));
805 break;
806 case ID_NBRXK:
807 rtw89_debug(rtwdev, RTW89_DBG_RFK,
808 "[IQK]============ S%d ID_NBRXK ============\n", path);
809 rtw89_phy_write32_mask(rtwdev, R_UPD_CLK, B_IQK_RFC_ON, 0x1);
810 rtw89_phy_write32_mask(rtwdev, R_IQK_DIF4, B_IQK_DIF4_RXT,
811 0x011);
812 iqk_cmd = 0x608 | (1 << (4 + path));
813 break;
814 default:
815 return false;
816 }
817
818 rtw89_phy_write32_mask(rtwdev, R_NCTL_CFG, MASKDWORD, iqk_cmd + 1);
819 notready = _iqk_check_cal(rtwdev, path);
820 if (iqk_info->iqk_sram_en &&
821 (ktype == ID_NBRXK || ktype == ID_RXK))
822 _iqk_sram(rtwdev, path);
823
824 rtw89_phy_write32_mask(rtwdev, R_UPD_CLK, B_IQK_RFC_ON, 0x0);
825 rtw89_debug(rtwdev, RTW89_DBG_RFK,
826 "[IQK]S%x, ktype= %x, id = %x, notready = %x\n",
827 path, ktype, iqk_cmd + 1, notready);
828
829 return notready;
830 }
831
_rxk_2g_group_sel(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx,u8 path)832 static bool _rxk_2g_group_sel(struct rtw89_dev *rtwdev,
833 enum rtw89_phy_idx phy_idx, u8 path)
834 {
835 struct rtw89_iqk_info *iqk_info = &rtwdev->iqk;
836 bool kfail = false;
837 bool notready;
838 u32 rf_0;
839 u8 gp;
840
841 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]===>%s\n", __func__);
842
843 for (gp = 0; gp < RTW8851B_RXK_GROUP_NR; gp++) {
844 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%x, gp = %x\n", path, gp);
845
846 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_RGM, g_idxrxgain[gp]);
847 rtw89_write_rf(rtwdev, path, RR_RXBB, RR_RXBB_C2, g_idxattc2[gp]);
848 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT, B_CFIR_LUT_SEL, 0x1);
849 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT, B_CFIR_LUT_G3, 0x0);
850 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT, B_CFIR_LUT_GP_V1, gp);
851
852 rtw89_write_rf(rtwdev, path, RR_RXKPLL, RFREG_MASK, 0x80013);
853 fsleep(10);
854 rf_0 = rtw89_read_rf(rtwdev, path, RR_MOD, RFREG_MASK);
855 rtw89_phy_write32_mask(rtwdev, R_IQK_DIF2, B_IQK_DIF2_RXPI, rf_0);
856 rtw89_phy_write32_mask(rtwdev, R_IQK_RXA, B_IQK_RXAGC, g_idxrxagc[gp]);
857 rtw89_phy_write32_mask(rtwdev, R_IQK_DIF4, B_IQK_DIF4_RXT, 0x11);
858
859 notready = _iqk_one_shot(rtwdev, phy_idx, path, ID_RXAGC);
860
861 rtw89_debug(rtwdev, RTW89_DBG_RFK,
862 "[IQK]S%x, RXAGC 0x8008 = 0x%x, rxbb = %x\n", path,
863 rtw89_phy_read32_mask(rtwdev, R_NCTL_RPT, MASKDWORD),
864 rtw89_read_rf(rtwdev, path, RR_MOD, 0x003e0));
865
866 rtw89_write_rf(rtwdev, path, RR_RXKPLL, RR_RXKPLL_OFF, 0x13);
867 rtw89_phy_write32_mask(rtwdev, R_IQK_DIF4, B_IQK_DIF4_RXT, 0x011);
868 notready = _iqk_one_shot(rtwdev, phy_idx, path, ID_NBRXK);
869 iqk_info->nb_rxcfir[path] =
870 rtw89_phy_read32_mask(rtwdev, R_RXIQC, MASKDWORD) | 0x2;
871
872 notready = _iqk_one_shot(rtwdev, phy_idx, path, ID_RXK);
873
874 rtw89_debug(rtwdev, RTW89_DBG_RFK,
875 "[IQK]S%x, WBRXK 0x8008 = 0x%x\n", path,
876 rtw89_phy_read32_mask(rtwdev, R_NCTL_RPT, MASKDWORD));
877 }
878
879 if (!notready)
880 kfail = !!rtw89_phy_read32_mask(rtwdev, R_NCTL_RPT, B_NCTL_RPT_FLG);
881
882 if (kfail)
883 _iqk_sram(rtwdev, path);
884
885 if (kfail) {
886 rtw89_phy_write32_mask(rtwdev, R_RXIQC + (path << 8),
887 MASKDWORD, iqk_info->nb_rxcfir[path] | 0x2);
888 iqk_info->is_wb_txiqk[path] = false;
889 } else {
890 rtw89_phy_write32_mask(rtwdev, R_RXIQC + (path << 8),
891 MASKDWORD, 0x40000000);
892 iqk_info->is_wb_txiqk[path] = true;
893 }
894
895 rtw89_debug(rtwdev, RTW89_DBG_RFK,
896 "[IQK]S%x, kfail = 0x%x, 0x8%x3c = 0x%x\n", path, kfail,
897 1 << path, iqk_info->nb_rxcfir[path]);
898 return kfail;
899 }
900
_rxk_5g_group_sel(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx,u8 path)901 static bool _rxk_5g_group_sel(struct rtw89_dev *rtwdev,
902 enum rtw89_phy_idx phy_idx, u8 path)
903 {
904 struct rtw89_iqk_info *iqk_info = &rtwdev->iqk;
905 bool kfail = false;
906 bool notready;
907 u32 rf_0;
908 u8 idx;
909 u8 gp;
910
911 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]===>%s\n", __func__);
912
913 for (idx = 0; idx < RTW8851B_RXK_GROUP_IDX_NR; idx++) {
914 gp = _rxk_5ghz_group_from_idx(idx);
915
916 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%x, gp = %x\n", path, gp);
917
918 rtw89_write_rf(rtwdev, RF_PATH_A, RR_MOD, RR_MOD_RGM, a_idxrxgain[idx]);
919 rtw89_write_rf(rtwdev, RF_PATH_A, RR_RXA2, RR_RXA2_ATT, a_idxattc2[idx]);
920
921 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT, B_CFIR_LUT_SEL, 0x1);
922 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT, B_CFIR_LUT_G3, 0x0);
923 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT, B_CFIR_LUT_GP_V1, gp);
924
925 rtw89_write_rf(rtwdev, path, RR_RXKPLL, RFREG_MASK, 0x80013);
926 fsleep(100);
927 rf_0 = rtw89_read_rf(rtwdev, path, RR_MOD, RFREG_MASK);
928 rtw89_phy_write32_mask(rtwdev, R_IQK_DIF2, B_IQK_DIF2_RXPI, rf_0);
929 rtw89_phy_write32_mask(rtwdev, R_IQK_RXA, B_IQK_RXAGC, a_idxrxagc[idx]);
930 rtw89_phy_write32_mask(rtwdev, R_IQK_DIF4, B_IQK_DIF4_RXT, 0x11);
931 notready = _iqk_one_shot(rtwdev, phy_idx, path, ID_RXAGC);
932
933 rtw89_debug(rtwdev, RTW89_DBG_RFK,
934 "[IQK]S%x, RXAGC 0x8008 = 0x%x, rxbb = %x\n", path,
935 rtw89_phy_read32_mask(rtwdev, R_NCTL_RPT, MASKDWORD),
936 rtw89_read_rf(rtwdev, path, RR_MOD, RR_MOD_RXB));
937
938 rtw89_write_rf(rtwdev, path, RR_RXKPLL, RR_RXKPLL_OFF, 0x13);
939 rtw89_phy_write32_mask(rtwdev, R_IQK_DIF4, B_IQK_DIF4_RXT, 0x011);
940 notready = _iqk_one_shot(rtwdev, phy_idx, path, ID_NBRXK);
941 iqk_info->nb_rxcfir[path] =
942 rtw89_phy_read32_mask(rtwdev, R_RXIQC, MASKDWORD) | 0x2;
943
944 rtw89_debug(rtwdev, RTW89_DBG_RFK,
945 "[IQK]S%x, NBRXK 0x8008 = 0x%x\n", path,
946 rtw89_phy_read32_mask(rtwdev, R_NCTL_RPT, MASKDWORD));
947
948 notready = _iqk_one_shot(rtwdev, phy_idx, path, ID_RXK);
949
950 rtw89_debug(rtwdev, RTW89_DBG_RFK,
951 "[IQK]S%x, WBRXK 0x8008 = 0x%x\n", path,
952 rtw89_phy_read32_mask(rtwdev, R_NCTL_RPT, MASKDWORD));
953 }
954
955 if (!notready)
956 kfail = !!rtw89_phy_read32_mask(rtwdev, R_NCTL_RPT, B_NCTL_RPT_FLG);
957
958 if (kfail)
959 _iqk_sram(rtwdev, path);
960
961 if (kfail) {
962 rtw89_phy_write32_mask(rtwdev, R_RXIQC + (path << 8), MASKDWORD,
963 iqk_info->nb_rxcfir[path] | 0x2);
964 iqk_info->is_wb_txiqk[path] = false;
965 } else {
966 rtw89_phy_write32_mask(rtwdev, R_RXIQC + (path << 8), MASKDWORD,
967 0x40000000);
968 iqk_info->is_wb_txiqk[path] = true;
969 }
970
971 rtw89_debug(rtwdev, RTW89_DBG_RFK,
972 "[IQK]S%x, kfail = 0x%x, 0x8%x3c = 0x%x\n", path, kfail,
973 1 << path, iqk_info->nb_rxcfir[path]);
974 return kfail;
975 }
976
_iqk_5g_nbrxk(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx,u8 path)977 static bool _iqk_5g_nbrxk(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx,
978 u8 path)
979 {
980 struct rtw89_iqk_info *iqk_info = &rtwdev->iqk;
981 bool kfail = false;
982 bool notready;
983 u8 idx = 0x1;
984 u32 rf_0;
985 u8 gp;
986
987 gp = _rxk_5ghz_group_from_idx(idx);
988
989 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]===>%s\n", __func__);
990 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%x, gp = %x\n", path, gp);
991
992 rtw89_write_rf(rtwdev, RF_PATH_A, RR_MOD, RR_MOD_RGM, a_idxrxgain[idx]);
993 rtw89_write_rf(rtwdev, RF_PATH_A, RR_RXA2, RR_RXA2_ATT, a_idxattc2[idx]);
994
995 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT, B_CFIR_LUT_SEL, 0x1);
996 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT, B_CFIR_LUT_G3, 0x0);
997 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT, B_CFIR_LUT_GP_V1, gp);
998
999 rtw89_write_rf(rtwdev, path, RR_RXKPLL, RFREG_MASK, 0x80013);
1000 fsleep(100);
1001 rf_0 = rtw89_read_rf(rtwdev, path, RR_MOD, RFREG_MASK);
1002 rtw89_phy_write32_mask(rtwdev, R_IQK_DIF2, B_IQK_DIF2_RXPI, rf_0);
1003 rtw89_phy_write32_mask(rtwdev, R_IQK_RXA, B_IQK_RXAGC, a_idxrxagc[idx]);
1004 rtw89_phy_write32_mask(rtwdev, R_IQK_DIF4, B_IQK_DIF4_RXT, 0x11);
1005 notready = _iqk_one_shot(rtwdev, phy_idx, path, ID_RXAGC);
1006
1007 rtw89_debug(rtwdev, RTW89_DBG_RFK,
1008 "[IQK]S%x, RXAGC 0x8008 = 0x%x, rxbb = %x\n", path,
1009 rtw89_phy_read32_mask(rtwdev, R_NCTL_RPT, MASKDWORD),
1010 rtw89_read_rf(rtwdev, path, RR_MOD, 0x003e0));
1011
1012 rtw89_write_rf(rtwdev, path, RR_RXKPLL, RR_RXKPLL_OFF, 0x13);
1013 rtw89_phy_write32_mask(rtwdev, R_IQK_DIF4, B_IQK_DIF4_RXT, 0x011);
1014 notready = _iqk_one_shot(rtwdev, phy_idx, path, ID_NBRXK);
1015 iqk_info->nb_rxcfir[path] =
1016 rtw89_phy_read32_mask(rtwdev, R_RXIQC, MASKDWORD) | 0x2;
1017
1018 rtw89_debug(rtwdev, RTW89_DBG_RFK,
1019 "[IQK]S%x, NBRXK 0x8008 = 0x%x\n", path,
1020 rtw89_phy_read32_mask(rtwdev, R_NCTL_RPT, MASKDWORD));
1021
1022 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%x, WBRXK 0x8008 = 0x%x\n",
1023 path, rtw89_phy_read32_mask(rtwdev, R_NCTL_RPT, MASKDWORD));
1024
1025 if (!notready)
1026 kfail = !!rtw89_phy_read32_mask(rtwdev, R_NCTL_RPT, B_NCTL_RPT_FLG);
1027
1028 if (kfail) {
1029 rtw89_phy_write32_mask(rtwdev, R_RXIQC + (path << 8),
1030 MASKDWORD, 0x40000002);
1031 iqk_info->is_wb_rxiqk[path] = false;
1032 } else {
1033 iqk_info->is_wb_rxiqk[path] = false;
1034 }
1035
1036 rtw89_debug(rtwdev, RTW89_DBG_RFK,
1037 "[IQK]S%x, kfail = 0x%x, 0x8%x3c = 0x%x\n", path, kfail,
1038 1 << path, iqk_info->nb_rxcfir[path]);
1039
1040 return kfail;
1041 }
1042
_iqk_2g_nbrxk(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx,u8 path)1043 static bool _iqk_2g_nbrxk(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx,
1044 u8 path)
1045 {
1046 struct rtw89_iqk_info *iqk_info = &rtwdev->iqk;
1047 bool kfail = false;
1048 bool notready;
1049 u8 gp = 0x3;
1050 u32 rf_0;
1051
1052 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]===>%s\n", __func__);
1053 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%x, gp = %x\n", path, gp);
1054
1055 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_RGM, g_idxrxgain[gp]);
1056 rtw89_write_rf(rtwdev, path, RR_RXBB, RR_RXBB_C2, g_idxattc2[gp]);
1057 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT, B_CFIR_LUT_SEL, 0x1);
1058 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT, B_CFIR_LUT_G3, 0x0);
1059 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT, B_CFIR_LUT_GP_V1, gp);
1060
1061 rtw89_write_rf(rtwdev, path, RR_RXKPLL, RFREG_MASK, 0x80013);
1062 fsleep(10);
1063 rf_0 = rtw89_read_rf(rtwdev, path, RR_MOD, RFREG_MASK);
1064 rtw89_phy_write32_mask(rtwdev, R_IQK_DIF2, B_IQK_DIF2_RXPI, rf_0);
1065 rtw89_phy_write32_mask(rtwdev, R_IQK_RXA, B_IQK_RXAGC, g_idxrxagc[gp]);
1066 rtw89_phy_write32_mask(rtwdev, R_IQK_DIF4, B_IQK_DIF4_RXT, 0x11);
1067 notready = _iqk_one_shot(rtwdev, phy_idx, path, ID_RXAGC);
1068
1069 rtw89_debug(rtwdev, RTW89_DBG_RFK,
1070 "[IQK]S%x, RXAGC 0x8008 = 0x%x, rxbb = %x\n",
1071 path, rtw89_phy_read32_mask(rtwdev, R_NCTL_RPT, MASKDWORD),
1072 rtw89_read_rf(rtwdev, path, RR_MOD, 0x003e0));
1073
1074 rtw89_write_rf(rtwdev, path, RR_RXKPLL, RR_RXKPLL_OFF, 0x13);
1075 rtw89_phy_write32_mask(rtwdev, R_IQK_DIF4, B_IQK_DIF4_RXT, 0x011);
1076 notready = _iqk_one_shot(rtwdev, phy_idx, path, ID_NBRXK);
1077 iqk_info->nb_rxcfir[path] =
1078 rtw89_phy_read32_mask(rtwdev, R_RXIQC, MASKDWORD) | 0x2;
1079
1080 rtw89_debug(rtwdev, RTW89_DBG_RFK,
1081 "[IQK]S%x, NBRXK 0x8008 = 0x%x\n", path,
1082 rtw89_phy_read32_mask(rtwdev, R_NCTL_RPT, MASKDWORD));
1083
1084 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%x, WBRXK 0x8008 = 0x%x\n",
1085 path, rtw89_phy_read32_mask(rtwdev, R_NCTL_RPT, MASKDWORD));
1086
1087 if (!notready)
1088 kfail = !!rtw89_phy_read32_mask(rtwdev, R_NCTL_RPT, B_NCTL_RPT_FLG);
1089
1090 if (kfail) {
1091 rtw89_phy_write32_mask(rtwdev, R_RXIQC + (path << 8),
1092 MASKDWORD, 0x40000002);
1093 iqk_info->is_wb_rxiqk[path] = false;
1094 } else {
1095 iqk_info->is_wb_rxiqk[path] = false;
1096 }
1097
1098 rtw89_debug(rtwdev, RTW89_DBG_RFK,
1099 "[IQK]S%x, kfail = 0x%x, 0x8%x3c = 0x%x\n", path, kfail,
1100 1 << path, iqk_info->nb_rxcfir[path]);
1101 return kfail;
1102 }
1103
_iqk_rxclk_setting(struct rtw89_dev * rtwdev,u8 path)1104 static void _iqk_rxclk_setting(struct rtw89_dev *rtwdev, u8 path)
1105 {
1106 struct rtw89_iqk_info *iqk_info = &rtwdev->iqk;
1107
1108 rtw89_write_rf(rtwdev, path, RR_RXBB2, RR_RXBB2_CKT, 0x1);
1109
1110 if (iqk_info->iqk_bw[path] == RTW89_CHANNEL_WIDTH_80) {
1111 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_RXK, 0x0101);
1112 rtw89_phy_write32_mask(rtwdev, R_UPD_CLK, B_DPD_GDIS, 0x1);
1113
1114 _rxck_force(rtwdev, path, true, ADC_960M);
1115
1116 rtw89_rfk_parser(rtwdev, &rtw8851b_iqk_rxclk_80_defs_tbl);
1117 } else {
1118 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_RXK, 0x0101);
1119 rtw89_phy_write32_mask(rtwdev, R_UPD_CLK, B_DPD_GDIS, 0x1);
1120
1121 _rxck_force(rtwdev, path, true, ADC_960M);
1122
1123 rtw89_rfk_parser(rtwdev, &rtw8851b_iqk_rxclk_others_defs_tbl);
1124 }
1125
1126 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%x, (2)before RXK IQK\n", path);
1127 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%x, 0x%x[07:10] = 0x%x\n", path,
1128 0xc0d4, rtw89_phy_read32_mask(rtwdev, 0xc0d4, GENMASK(10, 7)));
1129 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%x, 0x%x[11:14] = 0x%x\n", path,
1130 0xc0d4, rtw89_phy_read32_mask(rtwdev, 0xc0d4, GENMASK(14, 11)));
1131 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%x, 0x%x[26:27] = 0x%x\n", path,
1132 0xc0d4, rtw89_phy_read32_mask(rtwdev, 0xc0d4, GENMASK(27, 26)));
1133 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%x, 0x%x[05:08] = 0x%x\n", path,
1134 0xc0d8, rtw89_phy_read32_mask(rtwdev, 0xc0d8, GENMASK(8, 5)));
1135 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%x, 0x%x[17:21] = 0x%x\n", path,
1136 0xc0c4, rtw89_phy_read32_mask(rtwdev, 0xc0c4, GENMASK(21, 17)));
1137 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%x, 0x%x[16:31] = 0x%x\n", path,
1138 0xc0e8, rtw89_phy_read32_mask(rtwdev, 0xc0e8, GENMASK(31, 16)));
1139 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%x, 0x%x[04:05] = 0x%x\n", path,
1140 0xc0e4, rtw89_phy_read32_mask(rtwdev, 0xc0e4, GENMASK(5, 4)));
1141 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%x, 0x%x[23:31] = 0x%x\n", path,
1142 0x12a0, rtw89_phy_read32_mask(rtwdev, 0x12a0, GENMASK(31, 23)));
1143 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%x, 0x%x[13:14] = 0x%x\n", path,
1144 0xc0ec, rtw89_phy_read32_mask(rtwdev, 0xc0ec, GENMASK(14, 13)));
1145 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%x, 0x%x[16:23] = 0x%x\n", path,
1146 0xc0ec, rtw89_phy_read32_mask(rtwdev, 0xc0ec, GENMASK(23, 16)));
1147 }
1148
_txk_5g_group_sel(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx,u8 path)1149 static bool _txk_5g_group_sel(struct rtw89_dev *rtwdev,
1150 enum rtw89_phy_idx phy_idx, u8 path)
1151 {
1152 struct rtw89_iqk_info *iqk_info = &rtwdev->iqk;
1153 bool kfail = false;
1154 bool notready;
1155 u8 gp;
1156
1157 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]===>%s\n", __func__);
1158
1159 for (gp = 0x0; gp < RTW8851B_TXK_GROUP_NR; gp++) {
1160 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR0, a_power_range[gp]);
1161 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR1, a_track_range[gp]);
1162 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_TG, a_gain_bb[gp]);
1163
1164 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT, B_CFIR_LUT_SEL, 0x1);
1165 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT, B_CFIR_LUT_G3, 0x1);
1166 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT, B_CFIR_LUT_G2, 0x0);
1167 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT, B_CFIR_LUT_GP, gp);
1168 rtw89_phy_write32_mask(rtwdev, R_NCTL_N1, B_NCTL_N1_CIP, 0x00);
1169 rtw89_phy_write32_mask(rtwdev, R_KIP_IQP, MASKDWORD, a_itqt[gp]);
1170
1171 notready = _iqk_one_shot(rtwdev, phy_idx, path, ID_NBTXK);
1172 iqk_info->nb_txcfir[path] =
1173 rtw89_phy_read32_mask(rtwdev, R_TXIQC, MASKDWORD) | 0x2;
1174
1175 rtw89_phy_write32_mask(rtwdev, R_KIP_IQP + (path << 8),
1176 MASKDWORD, a_itqt[gp]);
1177 notready = _iqk_one_shot(rtwdev, phy_idx, path, ID_TXK);
1178 }
1179
1180 if (!notready)
1181 kfail = !!rtw89_phy_read32_mask(rtwdev, R_NCTL_RPT, B_NCTL_RPT_FLG);
1182
1183 if (kfail) {
1184 rtw89_phy_write32_mask(rtwdev, R_TXIQC + (path << 8),
1185 MASKDWORD, iqk_info->nb_txcfir[path] | 0x2);
1186 iqk_info->is_wb_txiqk[path] = false;
1187 } else {
1188 rtw89_phy_write32_mask(rtwdev, R_TXIQC + (path << 8),
1189 MASKDWORD, 0x40000000);
1190 iqk_info->is_wb_txiqk[path] = true;
1191 }
1192
1193 rtw89_debug(rtwdev, RTW89_DBG_RFK,
1194 "[IQK]S%x, kfail = 0x%x, 0x8%x38 = 0x%x\n", path, kfail,
1195 1 << path, iqk_info->nb_txcfir[path]);
1196 return kfail;
1197 }
1198
_txk_2g_group_sel(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx,u8 path)1199 static bool _txk_2g_group_sel(struct rtw89_dev *rtwdev,
1200 enum rtw89_phy_idx phy_idx, u8 path)
1201 {
1202 struct rtw89_iqk_info *iqk_info = &rtwdev->iqk;
1203 bool kfail = false;
1204 bool notready;
1205 u8 gp;
1206
1207 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]===>%s\n", __func__);
1208
1209 for (gp = 0x0; gp < RTW8851B_TXK_GROUP_NR; gp++) {
1210 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR0, g_power_range[gp]);
1211 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR1, g_track_range[gp]);
1212 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_TG, g_gain_bb[gp]);
1213
1214 rtw89_phy_write32_mask(rtwdev, R_KIP_IQP, MASKDWORD, g_itqt[gp]);
1215 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT, B_CFIR_LUT_SEL, 0x1);
1216 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT, B_CFIR_LUT_G3, 0x1);
1217 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT, B_CFIR_LUT_G2, 0x0);
1218 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT, B_CFIR_LUT_GP, gp);
1219 rtw89_phy_write32_mask(rtwdev, R_NCTL_N1, B_NCTL_N1_CIP, 0x00);
1220
1221 notready = _iqk_one_shot(rtwdev, phy_idx, path, ID_NBTXK);
1222 iqk_info->nb_txcfir[path] =
1223 rtw89_phy_read32_mask(rtwdev, R_TXIQC, MASKDWORD) | 0x2;
1224
1225 rtw89_phy_write32_mask(rtwdev, R_KIP_IQP + (path << 8),
1226 MASKDWORD, g_itqt[gp]);
1227 notready = _iqk_one_shot(rtwdev, phy_idx, path, ID_TXK);
1228 }
1229
1230 if (!notready)
1231 kfail = !!rtw89_phy_read32_mask(rtwdev, R_NCTL_RPT, B_NCTL_RPT_FLG);
1232
1233 if (kfail) {
1234 rtw89_phy_write32_mask(rtwdev, R_TXIQC + (path << 8),
1235 MASKDWORD, iqk_info->nb_txcfir[path] | 0x2);
1236 iqk_info->is_wb_txiqk[path] = false;
1237 } else {
1238 rtw89_phy_write32_mask(rtwdev, R_TXIQC + (path << 8),
1239 MASKDWORD, 0x40000000);
1240 iqk_info->is_wb_txiqk[path] = true;
1241 }
1242
1243 rtw89_debug(rtwdev, RTW89_DBG_RFK,
1244 "[IQK]S%x, kfail = 0x%x, 0x8%x38 = 0x%x\n", path, kfail,
1245 1 << path, iqk_info->nb_txcfir[path]);
1246 return kfail;
1247 }
1248
_iqk_5g_nbtxk(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx,u8 path)1249 static bool _iqk_5g_nbtxk(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx,
1250 u8 path)
1251 {
1252 struct rtw89_iqk_info *iqk_info = &rtwdev->iqk;
1253 bool kfail = false;
1254 bool notready;
1255 u8 gp;
1256
1257 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]===>%s\n", __func__);
1258
1259 for (gp = 0x0; gp < RTW8851B_TXK_GROUP_NR; gp++) {
1260 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR0, a_power_range[gp]);
1261 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR1, a_track_range[gp]);
1262 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_TG, a_gain_bb[gp]);
1263
1264 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT, B_CFIR_LUT_SEL, 0x1);
1265 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT, B_CFIR_LUT_G3, 0x1);
1266 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT, B_CFIR_LUT_G2, 0x0);
1267 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT, B_CFIR_LUT_GP, gp);
1268 rtw89_phy_write32_mask(rtwdev, R_NCTL_N1, B_NCTL_N1_CIP, 0x00);
1269 rtw89_phy_write32_mask(rtwdev, R_KIP_IQP, MASKDWORD, a_itqt[gp]);
1270
1271 notready = _iqk_one_shot(rtwdev, phy_idx, path, ID_NBTXK);
1272 iqk_info->nb_txcfir[path] =
1273 rtw89_phy_read32_mask(rtwdev, R_TXIQC, MASKDWORD) | 0x2;
1274 }
1275
1276 if (!notready)
1277 kfail = !!rtw89_phy_read32_mask(rtwdev, R_NCTL_RPT, B_NCTL_RPT_FLG);
1278
1279 if (kfail) {
1280 rtw89_phy_write32_mask(rtwdev, R_TXIQC + (path << 8),
1281 MASKDWORD, 0x40000002);
1282 iqk_info->is_wb_rxiqk[path] = false;
1283 } else {
1284 iqk_info->is_wb_rxiqk[path] = false;
1285 }
1286
1287 rtw89_debug(rtwdev, RTW89_DBG_RFK,
1288 "[IQK]S%x, kfail = 0x%x, 0x8%x38 = 0x%x\n", path, kfail,
1289 1 << path, iqk_info->nb_txcfir[path]);
1290 return kfail;
1291 }
1292
_iqk_2g_nbtxk(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx,u8 path)1293 static bool _iqk_2g_nbtxk(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx,
1294 u8 path)
1295 {
1296 struct rtw89_iqk_info *iqk_info = &rtwdev->iqk;
1297 bool kfail = false;
1298 bool notready;
1299 u8 gp;
1300
1301 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]===>%s\n", __func__);
1302
1303 for (gp = 0x0; gp < RTW8851B_TXK_GROUP_NR; gp++) {
1304 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR0, g_power_range[gp]);
1305 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR1, g_track_range[gp]);
1306 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_TG, g_gain_bb[gp]);
1307
1308 rtw89_phy_write32_mask(rtwdev, R_KIP_IQP, MASKDWORD, g_itqt[gp]);
1309 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT, B_CFIR_LUT_SEL, 0x1);
1310 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT, B_CFIR_LUT_G3, 0x1);
1311 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT, B_CFIR_LUT_G2, 0x0);
1312 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT, B_CFIR_LUT_GP, gp);
1313 rtw89_phy_write32_mask(rtwdev, R_NCTL_N1, B_NCTL_N1_CIP, 0x00);
1314
1315 notready = _iqk_one_shot(rtwdev, phy_idx, path, ID_NBTXK);
1316 iqk_info->nb_txcfir[path] =
1317 rtw89_phy_read32_mask(rtwdev, R_TXIQC + (path << 8),
1318 MASKDWORD) | 0x2;
1319 }
1320
1321 if (!notready)
1322 kfail = !!rtw89_phy_read32_mask(rtwdev, R_NCTL_RPT, B_NCTL_RPT_FLG);
1323
1324 if (kfail) {
1325 rtw89_phy_write32_mask(rtwdev, R_TXIQC + (path << 8),
1326 MASKDWORD, 0x40000002);
1327 iqk_info->is_wb_rxiqk[path] = false;
1328 } else {
1329 iqk_info->is_wb_rxiqk[path] = false;
1330 }
1331
1332 rtw89_debug(rtwdev, RTW89_DBG_RFK,
1333 "[IQK]S%x, kfail = 0x%x, 0x8%x38 = 0x%x\n", path, kfail,
1334 1 << path, iqk_info->nb_txcfir[path]);
1335 return kfail;
1336 }
1337
_iqk_2g_lok(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx,u8 path)1338 static bool _iqk_2g_lok(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx,
1339 u8 path)
1340 {
1341 static const u32 g_txbb[RTW8851B_LOK_GRAM] = {
1342 0x02, 0x06, 0x0a, 0x0c, 0x0e, 0x10, 0x12, 0x14, 0x16, 0x17};
1343 static const u32 g_itqt[RTW8851B_LOK_GRAM] = {
1344 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x12, 0x12, 0x12, 0x1b};
1345 static const u32 g_wa[RTW8851B_LOK_GRAM] = {
1346 0x00, 0x04, 0x08, 0x0c, 0x0e, 0x10, 0x12, 0x14, 0x16, 0x17};
1347 bool fail = false;
1348 u8 i;
1349
1350 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]===>%s\n", __func__);
1351
1352 rtw89_write_rf(rtwdev, RF_PATH_A, RR_LUTDBG, RR_LUTDBG_LOK, 0x0);
1353 rtw89_write_rf(rtwdev, RF_PATH_A, RR_TXIG, RR_TXIG_GR0, 0x0);
1354 rtw89_write_rf(rtwdev, RF_PATH_A, RR_TXIG, RR_TXIG_GR1, 0x6);
1355
1356 for (i = 0; i < RTW8851B_LOK_GRAM; i++) {
1357 rtw89_write_rf(rtwdev, RF_PATH_A, RR_TXIG, RR_TXIG_TG, g_txbb[i]);
1358 rtw89_write_rf(rtwdev, RF_PATH_A, RR_LUTWA, RR_LUTWA_M1, g_wa[i]);
1359 rtw89_phy_write32_mask(rtwdev, R_UPD_CLK, B_IQK_RFC_ON, 0x1);
1360 rtw89_phy_write32_mask(rtwdev, R_KIP_IQP, B_KIP_IQP_IQSW, g_itqt[i]);
1361 rtw89_phy_write32_mask(rtwdev, R_IQK_DIF4, B_IQK_DIF4_TXT, 0x021);
1362 rtw89_phy_write32_mask(rtwdev, R_NCTL_CFG, MASKDWORD,
1363 0x00000109 | (1 << (4 + path)));
1364 fail |= _iqk_check_cal(rtwdev, path);
1365
1366 rtw89_phy_write32_mask(rtwdev, R_NCTL_N1, B_NCTL_N1_CIP, 0x00);
1367 rtw89_phy_write32_mask(rtwdev, R_KIP_IQP, B_KIP_IQP_IQSW, g_itqt[i]);
1368 rtw89_phy_write32_mask(rtwdev, R_NCTL_CFG, MASKDWORD,
1369 0x00000309 | (1 << (4 + path)));
1370 fail |= _iqk_check_cal(rtwdev, path);
1371
1372 rtw89_phy_write32_mask(rtwdev, R_NCTL_N1, B_NCTL_N1_CIP, 0x00);
1373 rtw89_phy_write32_mask(rtwdev, R_UPD_CLK, B_IQK_RFC_ON, 0x0);
1374
1375 rtw89_debug(rtwdev, RTW89_DBG_RFK,
1376 "[IQK]S0, i = %x, 0x8[19:15] = 0x%x,0x8[09:05] = 0x%x\n", i,
1377 rtw89_read_rf(rtwdev, RF_PATH_A, RR_DTXLOK, 0xf8000),
1378 rtw89_read_rf(rtwdev, RF_PATH_A, RR_DTXLOK, 0x003e0));
1379 rtw89_debug(rtwdev, RTW89_DBG_RFK,
1380 "[IQK]S0, i = %x, 0x9[19:16] = 0x%x,0x9[09:06] = 0x%x\n", i,
1381 rtw89_read_rf(rtwdev, RF_PATH_A, RR_RSV2, 0xf0000),
1382 rtw89_read_rf(rtwdev, RF_PATH_A, RR_RSV2, 0x003c0));
1383 rtw89_debug(rtwdev, RTW89_DBG_RFK,
1384 "[IQK]S0, i = %x, 0x58 = %x\n", i,
1385 rtw89_read_rf(rtwdev, RF_PATH_A, RR_TXMO, RFREG_MASK));
1386 }
1387
1388 return fail;
1389 }
1390
_iqk_5g_lok(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx,u8 path)1391 static bool _iqk_5g_lok(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx,
1392 u8 path)
1393 {
1394 static const u32 a_txbb[RTW8851B_LOK_GRAM] = {
1395 0x02, 0x06, 0x0a, 0x0c, 0x0e, 0x10, 0x12, 0x14, 0x16, 0x17};
1396 static const u32 a_itqt[RTW8851B_LOK_GRAM] = {
1397 0x09, 0x09, 0x09, 0x12, 0x12, 0x12, 0x1b, 0x1b, 0x1b, 0x1b};
1398 static const u32 a_wa[RTW8851B_LOK_GRAM] = {
1399 0x80, 0x84, 0x88, 0x8c, 0x8e, 0x90, 0x92, 0x94, 0x96, 0x97};
1400 bool fail = false;
1401 u8 i;
1402
1403 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]===>%s\n", __func__);
1404
1405 rtw89_write_rf(rtwdev, RF_PATH_A, RR_LUTDBG, RR_LUTDBG_LOK, 0x0);
1406 rtw89_write_rf(rtwdev, RF_PATH_A, RR_TXIG, RR_TXIG_GR0, 0x0);
1407 rtw89_write_rf(rtwdev, RF_PATH_A, RR_TXIG, RR_TXIG_GR1, 0x7);
1408
1409 for (i = 0; i < RTW8851B_LOK_GRAM; i++) {
1410 rtw89_write_rf(rtwdev, RF_PATH_A, RR_TXIG, RR_TXIG_TG, a_txbb[i]);
1411 rtw89_write_rf(rtwdev, RF_PATH_A, RR_LUTWA, RR_LUTWA_M1, a_wa[i]);
1412 rtw89_phy_write32_mask(rtwdev, R_UPD_CLK, B_IQK_RFC_ON, 0x1);
1413 rtw89_phy_write32_mask(rtwdev, R_KIP_IQP, B_KIP_IQP_IQSW, a_itqt[i]);
1414 rtw89_phy_write32_mask(rtwdev, R_IQK_DIF4, B_IQK_DIF4_TXT, 0x021);
1415 rtw89_phy_write32_mask(rtwdev, R_NCTL_CFG, MASKDWORD,
1416 0x00000109 | (1 << (4 + path)));
1417 fail |= _iqk_check_cal(rtwdev, path);
1418
1419 rtw89_phy_write32_mask(rtwdev, R_NCTL_N1, B_NCTL_N1_CIP, 0x00);
1420 rtw89_phy_write32_mask(rtwdev, R_KIP_IQP, B_KIP_IQP_IQSW, a_itqt[i]);
1421 rtw89_phy_write32_mask(rtwdev, R_IQK_DIF4, B_IQK_DIF4_TXT, 0x021);
1422 rtw89_phy_write32_mask(rtwdev, R_NCTL_CFG, MASKDWORD,
1423 0x00000309 | (1 << (4 + path)));
1424 fail |= _iqk_check_cal(rtwdev, path);
1425
1426 rtw89_phy_write32_mask(rtwdev, R_NCTL_N1, B_NCTL_N1_CIP, 0x00);
1427 rtw89_phy_write32_mask(rtwdev, R_UPD_CLK, B_IQK_RFC_ON, 0x0);
1428
1429 rtw89_debug(rtwdev, RTW89_DBG_RFK,
1430 "[IQK]S0, i = %x, 0x8[19:15] = 0x%x,0x8[09:05] = 0x%x\n", i,
1431 rtw89_read_rf(rtwdev, RF_PATH_A, RR_DTXLOK, 0xf8000),
1432 rtw89_read_rf(rtwdev, RF_PATH_A, RR_DTXLOK, 0x003e0));
1433 rtw89_debug(rtwdev, RTW89_DBG_RFK,
1434 "[IQK]S0, i = %x, 0x9[19:16] = 0x%x,0x9[09:06] = 0x%x\n", i,
1435 rtw89_read_rf(rtwdev, RF_PATH_A, RR_RSV2, 0xf0000),
1436 rtw89_read_rf(rtwdev, RF_PATH_A, RR_RSV2, 0x003c0));
1437 rtw89_debug(rtwdev, RTW89_DBG_RFK,
1438 "[IQK]S0, i = %x, 0x58 = %x\n", i,
1439 rtw89_read_rf(rtwdev, RF_PATH_A, RR_TXMO, RFREG_MASK));
1440 }
1441
1442 return fail;
1443 }
1444
_iqk_txk_setting(struct rtw89_dev * rtwdev,u8 path)1445 static void _iqk_txk_setting(struct rtw89_dev *rtwdev, u8 path)
1446 {
1447 struct rtw89_iqk_info *iqk_info = &rtwdev->iqk;
1448
1449 switch (iqk_info->iqk_band[path]) {
1450 case RTW89_BAND_2G:
1451 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]RTW89_BAND_2G\n");
1452 rtw89_rfk_parser(rtwdev, &rtw8851b_iqk_txk_2ghz_defs_tbl);
1453 break;
1454 case RTW89_BAND_5G:
1455 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]RTW89_BAND_5G\n");
1456 rtw89_rfk_parser(rtwdev, &rtw8851b_iqk_txk_5ghz_defs_tbl);
1457 break;
1458 default:
1459 break;
1460 }
1461 }
1462
1463 #define IQK_LOK_RETRY 1
1464
_iqk_by_path(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx,u8 path)1465 static void _iqk_by_path(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx,
1466 u8 path)
1467 {
1468 struct rtw89_iqk_info *iqk_info = &rtwdev->iqk;
1469 bool lok_is_fail;
1470 u8 i;
1471
1472 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]===>%s\n", __func__);
1473
1474 for (i = 0; i < IQK_LOK_RETRY; i++) {
1475 _iqk_txk_setting(rtwdev, path);
1476 if (iqk_info->iqk_band[path] == RTW89_BAND_2G)
1477 lok_is_fail = _iqk_2g_lok(rtwdev, phy_idx, path);
1478 else
1479 lok_is_fail = _iqk_5g_lok(rtwdev, phy_idx, path);
1480
1481 if (!lok_is_fail)
1482 break;
1483 }
1484
1485 if (iqk_info->is_nbiqk) {
1486 if (iqk_info->iqk_band[path] == RTW89_BAND_2G)
1487 iqk_info->iqk_tx_fail[0][path] =
1488 _iqk_2g_nbtxk(rtwdev, phy_idx, path);
1489 else
1490 iqk_info->iqk_tx_fail[0][path] =
1491 _iqk_5g_nbtxk(rtwdev, phy_idx, path);
1492 } else {
1493 if (iqk_info->iqk_band[path] == RTW89_BAND_2G)
1494 iqk_info->iqk_tx_fail[0][path] =
1495 _txk_2g_group_sel(rtwdev, phy_idx, path);
1496 else
1497 iqk_info->iqk_tx_fail[0][path] =
1498 _txk_5g_group_sel(rtwdev, phy_idx, path);
1499 }
1500
1501 _iqk_rxclk_setting(rtwdev, path);
1502 _iqk_rxk_setting(rtwdev, path);
1503 _adc_fifo_rst(rtwdev, phy_idx, path);
1504
1505 if (iqk_info->is_nbiqk) {
1506 if (iqk_info->iqk_band[path] == RTW89_BAND_2G)
1507 iqk_info->iqk_rx_fail[0][path] =
1508 _iqk_2g_nbrxk(rtwdev, phy_idx, path);
1509 else
1510 iqk_info->iqk_rx_fail[0][path] =
1511 _iqk_5g_nbrxk(rtwdev, phy_idx, path);
1512 } else {
1513 if (iqk_info->iqk_band[path] == RTW89_BAND_2G)
1514 iqk_info->iqk_rx_fail[0][path] =
1515 _rxk_2g_group_sel(rtwdev, phy_idx, path);
1516 else
1517 iqk_info->iqk_rx_fail[0][path] =
1518 _rxk_5g_group_sel(rtwdev, phy_idx, path);
1519 }
1520 }
1521
_rfk_backup_bb_reg(struct rtw89_dev * rtwdev,u32 backup_bb_reg_val[])1522 static void _rfk_backup_bb_reg(struct rtw89_dev *rtwdev,
1523 u32 backup_bb_reg_val[])
1524 {
1525 u32 i;
1526
1527 for (i = 0; i < BACKUP_BB_REGS_NR; i++) {
1528 backup_bb_reg_val[i] =
1529 rtw89_phy_read32_mask(rtwdev, rtw8851b_backup_bb_regs[i],
1530 MASKDWORD);
1531 rtw89_debug(rtwdev, RTW89_DBG_RFK,
1532 "[RFK]backup bb reg : %x, value =%x\n",
1533 rtw8851b_backup_bb_regs[i], backup_bb_reg_val[i]);
1534 }
1535 }
1536
_rfk_backup_rf_reg(struct rtw89_dev * rtwdev,u32 backup_rf_reg_val[],u8 rf_path)1537 static void _rfk_backup_rf_reg(struct rtw89_dev *rtwdev,
1538 u32 backup_rf_reg_val[], u8 rf_path)
1539 {
1540 u32 i;
1541
1542 for (i = 0; i < BACKUP_RF_REGS_NR; i++) {
1543 backup_rf_reg_val[i] =
1544 rtw89_read_rf(rtwdev, rf_path,
1545 rtw8851b_backup_rf_regs[i], RFREG_MASK);
1546 rtw89_debug(rtwdev, RTW89_DBG_RFK,
1547 "[RFK]backup rf S%d reg : %x, value =%x\n", rf_path,
1548 rtw8851b_backup_rf_regs[i], backup_rf_reg_val[i]);
1549 }
1550 }
1551
_rfk_restore_bb_reg(struct rtw89_dev * rtwdev,const u32 backup_bb_reg_val[])1552 static void _rfk_restore_bb_reg(struct rtw89_dev *rtwdev,
1553 const u32 backup_bb_reg_val[])
1554 {
1555 u32 i;
1556
1557 for (i = 0; i < BACKUP_BB_REGS_NR; i++) {
1558 rtw89_phy_write32_mask(rtwdev, rtw8851b_backup_bb_regs[i],
1559 MASKDWORD, backup_bb_reg_val[i]);
1560 rtw89_debug(rtwdev, RTW89_DBG_RFK,
1561 "[RFK]restore bb reg : %x, value =%x\n",
1562 rtw8851b_backup_bb_regs[i], backup_bb_reg_val[i]);
1563 }
1564 }
1565
_rfk_restore_rf_reg(struct rtw89_dev * rtwdev,const u32 backup_rf_reg_val[],u8 rf_path)1566 static void _rfk_restore_rf_reg(struct rtw89_dev *rtwdev,
1567 const u32 backup_rf_reg_val[], u8 rf_path)
1568 {
1569 u32 i;
1570
1571 for (i = 0; i < BACKUP_RF_REGS_NR; i++) {
1572 rtw89_write_rf(rtwdev, rf_path, rtw8851b_backup_rf_regs[i],
1573 RFREG_MASK, backup_rf_reg_val[i]);
1574
1575 rtw89_debug(rtwdev, RTW89_DBG_RFK,
1576 "[RFK]restore rf S%d reg: %x, value =%x\n", rf_path,
1577 rtw8851b_backup_rf_regs[i], backup_rf_reg_val[i]);
1578 }
1579 }
1580
_iqk_get_ch_info(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy,u8 path,enum rtw89_chanctx_idx chanctx_idx)1581 static void _iqk_get_ch_info(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
1582 u8 path, enum rtw89_chanctx_idx chanctx_idx)
1583 {
1584 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, chanctx_idx);
1585 struct rtw89_iqk_info *iqk_info = &rtwdev->iqk;
1586 u8 idx = 0;
1587
1588 iqk_info->iqk_band[path] = chan->band_type;
1589 iqk_info->iqk_bw[path] = chan->band_width;
1590 iqk_info->iqk_ch[path] = chan->channel;
1591 iqk_info->iqk_table_idx[path] = idx;
1592
1593 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%d (PHY%d): / DBCC %s/ %s/ CH%d/ %s\n",
1594 path, phy, rtwdev->dbcc_en ? "on" : "off",
1595 iqk_info->iqk_band[path] == 0 ? "2G" :
1596 iqk_info->iqk_band[path] == 1 ? "5G" : "6G",
1597 iqk_info->iqk_ch[path],
1598 iqk_info->iqk_bw[path] == 0 ? "20M" :
1599 iqk_info->iqk_bw[path] == 1 ? "40M" : "80M");
1600 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]times = 0x%x, ch =%x\n",
1601 iqk_info->iqk_times, idx);
1602 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%x, iqk_info->syn1to2= 0x%x\n",
1603 path, iqk_info->syn1to2);
1604 }
1605
_iqk_start_iqk(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx,u8 path)1606 static void _iqk_start_iqk(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx,
1607 u8 path)
1608 {
1609 _iqk_by_path(rtwdev, phy_idx, path);
1610 }
1611
_iqk_restore(struct rtw89_dev * rtwdev,u8 path)1612 static void _iqk_restore(struct rtw89_dev *rtwdev, u8 path)
1613 {
1614 bool fail;
1615
1616 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]===>%s\n", __func__);
1617
1618 rtw89_phy_write32_mask(rtwdev, R_NCTL_CFG, MASKDWORD, 0x00001219);
1619 fsleep(10);
1620 fail = _iqk_check_cal(rtwdev, path);
1621 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] restore fail=%d\n", fail);
1622
1623 rtw89_write_rf(rtwdev, RF_PATH_A, RR_LUTWE, RR_LUTWE_LOK, 0x0);
1624 rtw89_write_rf(rtwdev, RF_PATH_A, RR_LUTDBG, RR_LUTDBG_TIA, 0x0);
1625
1626 rtw89_phy_write32_mask(rtwdev, R_NCTL_N1, B_NCTL_N1_CIP, 0x00);
1627 rtw89_phy_write32_mask(rtwdev, R_NCTL_RPT, MASKDWORD, 0x00000000);
1628 rtw89_phy_write32_mask(rtwdev, R_KIP_SYSCFG, MASKDWORD, 0x80000000);
1629 }
1630
_iqk_afebb_restore(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx,u8 path)1631 static void _iqk_afebb_restore(struct rtw89_dev *rtwdev,
1632 enum rtw89_phy_idx phy_idx, u8 path)
1633 {
1634 rtw89_rfk_parser(rtwdev, &rtw8851b_iqk_afebb_restore_defs_tbl);
1635 }
1636
_iqk_preset(struct rtw89_dev * rtwdev,u8 path)1637 static void _iqk_preset(struct rtw89_dev *rtwdev, u8 path)
1638 {
1639 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]===>%s\n", __func__);
1640
1641 rtw89_write_rf(rtwdev, path, RR_RSV1, RR_RSV1_RST, 0x0);
1642 rtw89_phy_write32_mask(rtwdev, R_NCTL_RPT, MASKDWORD, 0x00000080);
1643 rtw89_phy_write32_mask(rtwdev, R_KIP_SYSCFG, MASKDWORD, 0x81ff010a);
1644 }
1645
_iqk_macbb_setting(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx,u8 path)1646 static void _iqk_macbb_setting(struct rtw89_dev *rtwdev,
1647 enum rtw89_phy_idx phy_idx, u8 path)
1648 {
1649 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]===>%s\n", __func__);
1650
1651 rtw89_rfk_parser(rtwdev, &rtw8851b_iqk_macbb_defs_tbl);
1652
1653 _txck_force(rtwdev, path, true, DAC_960M);
1654
1655 rtw89_phy_write32_mask(rtwdev, R_UPD_CLK, B_DPD_GDIS, 0x1);
1656
1657 _rxck_force(rtwdev, path, true, ADC_1920M);
1658
1659 rtw89_rfk_parser(rtwdev, &rtw8851b_iqk_macbb_bh_defs_tbl);
1660 }
1661
_iqk_init(struct rtw89_dev * rtwdev)1662 static void _iqk_init(struct rtw89_dev *rtwdev)
1663 {
1664 struct rtw89_iqk_info *iqk_info = &rtwdev->iqk;
1665 u8 idx, path;
1666
1667 rtw89_phy_write32_mask(rtwdev, R_IQKINF, MASKDWORD, 0x0);
1668
1669 if (iqk_info->is_iqk_init)
1670 return;
1671
1672 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]===>%s\n", __func__);
1673
1674 iqk_info->is_iqk_init = true;
1675 iqk_info->is_nbiqk = false;
1676 iqk_info->iqk_fft_en = false;
1677 iqk_info->iqk_sram_en = false;
1678 iqk_info->iqk_cfir_en = false;
1679 iqk_info->iqk_xym_en = false;
1680 iqk_info->iqk_times = 0x0;
1681
1682 for (idx = 0; idx < RTW89_IQK_CHS_NR; idx++) {
1683 iqk_info->iqk_channel[idx] = 0x0;
1684 for (path = 0; path < RF_PATH_NUM_8851B; path++) {
1685 iqk_info->lok_cor_fail[idx][path] = false;
1686 iqk_info->lok_fin_fail[idx][path] = false;
1687 iqk_info->iqk_tx_fail[idx][path] = false;
1688 iqk_info->iqk_rx_fail[idx][path] = false;
1689 iqk_info->iqk_table_idx[path] = 0x0;
1690 }
1691 }
1692 }
1693
_doiqk(struct rtw89_dev * rtwdev,bool force,enum rtw89_phy_idx phy_idx,u8 path,enum rtw89_chanctx_idx chanctx_idx)1694 static void _doiqk(struct rtw89_dev *rtwdev, bool force,
1695 enum rtw89_phy_idx phy_idx, u8 path,
1696 enum rtw89_chanctx_idx chanctx_idx)
1697 {
1698 struct rtw89_iqk_info *iqk_info = &rtwdev->iqk;
1699 u8 phy_map = rtw89_btc_phymap(rtwdev, phy_idx, RF_AB, chanctx_idx);
1700 u32 backup_rf_val[RTW8851B_IQK_SS][BACKUP_RF_REGS_NR];
1701 u32 backup_bb_val[BACKUP_BB_REGS_NR];
1702
1703 rtw89_btc_ntfy_wl_rfk(rtwdev, phy_map, BTC_WRFKT_IQK,
1704 BTC_WRFK_ONESHOT_START);
1705
1706 rtw89_debug(rtwdev, RTW89_DBG_RFK,
1707 "[IQK]==========IQK start!!!!!==========\n");
1708 iqk_info->iqk_times++;
1709 iqk_info->version = RTW8851B_IQK_VER;
1710
1711 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]Test Ver 0x%x\n", iqk_info->version);
1712 _iqk_get_ch_info(rtwdev, phy_idx, path, chanctx_idx);
1713
1714 _rfk_backup_bb_reg(rtwdev, &backup_bb_val[0]);
1715 _rfk_backup_rf_reg(rtwdev, &backup_rf_val[path][0], path);
1716 _iqk_macbb_setting(rtwdev, phy_idx, path);
1717 _iqk_preset(rtwdev, path);
1718 _iqk_start_iqk(rtwdev, phy_idx, path);
1719 _iqk_restore(rtwdev, path);
1720 _iqk_afebb_restore(rtwdev, phy_idx, path);
1721 _rfk_restore_bb_reg(rtwdev, &backup_bb_val[0]);
1722 _rfk_restore_rf_reg(rtwdev, &backup_rf_val[path][0], path);
1723
1724 rtw89_btc_ntfy_wl_rfk(rtwdev, phy_map, BTC_WRFKT_IQK,
1725 BTC_WRFK_ONESHOT_STOP);
1726 }
1727
_iqk(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx,bool force,enum rtw89_chanctx_idx chanctx_idx)1728 static void _iqk(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx,
1729 bool force, enum rtw89_chanctx_idx chanctx_idx)
1730 {
1731 _doiqk(rtwdev, force, phy_idx, RF_PATH_A, chanctx_idx);
1732 }
1733
_dpk_bkup_kip(struct rtw89_dev * rtwdev,const u32 * reg,u32 reg_bkup[][DPK_KIP_REG_NUM_8851B],u8 path)1734 static void _dpk_bkup_kip(struct rtw89_dev *rtwdev, const u32 *reg,
1735 u32 reg_bkup[][DPK_KIP_REG_NUM_8851B], u8 path)
1736 {
1737 u8 i;
1738
1739 for (i = 0; i < DPK_KIP_REG_NUM_8851B; i++) {
1740 reg_bkup[path][i] =
1741 rtw89_phy_read32_mask(rtwdev, reg[i] + (path << 8), MASKDWORD);
1742
1743 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] Backup 0x%x = %x\n",
1744 reg[i] + (path << 8), reg_bkup[path][i]);
1745 }
1746 }
1747
_dpk_bkup_rf(struct rtw89_dev * rtwdev,const u32 * rf_reg,u32 rf_bkup[][DPK_RF_REG_NUM_8851B],u8 path)1748 static void _dpk_bkup_rf(struct rtw89_dev *rtwdev, const u32 *rf_reg,
1749 u32 rf_bkup[][DPK_RF_REG_NUM_8851B], u8 path)
1750 {
1751 u8 i;
1752
1753 for (i = 0; i < DPK_RF_REG_NUM_8851B; i++) {
1754 rf_bkup[path][i] = rtw89_read_rf(rtwdev, path, rf_reg[i], RFREG_MASK);
1755
1756 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] Backup RF S%d 0x%x = %x\n",
1757 path, rf_reg[i], rf_bkup[path][i]);
1758 }
1759 }
1760
_dpk_reload_kip(struct rtw89_dev * rtwdev,const u32 * reg,u32 reg_bkup[][DPK_KIP_REG_NUM_8851B],u8 path)1761 static void _dpk_reload_kip(struct rtw89_dev *rtwdev, const u32 *reg,
1762 u32 reg_bkup[][DPK_KIP_REG_NUM_8851B], u8 path)
1763 {
1764 u8 i;
1765
1766 for (i = 0; i < DPK_KIP_REG_NUM_8851B; i++) {
1767 rtw89_phy_write32_mask(rtwdev, reg[i] + (path << 8), MASKDWORD,
1768 reg_bkup[path][i]);
1769
1770 rtw89_debug(rtwdev, RTW89_DBG_RFK,
1771 "[DPK] Reload 0x%x = %x\n",
1772 reg[i] + (path << 8), reg_bkup[path][i]);
1773 }
1774 }
1775
_dpk_reload_rf(struct rtw89_dev * rtwdev,const u32 * rf_reg,u32 rf_bkup[][DPK_RF_REG_NUM_8851B],u8 path)1776 static void _dpk_reload_rf(struct rtw89_dev *rtwdev, const u32 *rf_reg,
1777 u32 rf_bkup[][DPK_RF_REG_NUM_8851B], u8 path)
1778 {
1779 u8 i;
1780
1781 for (i = 0; i < DPK_RF_REG_NUM_8851B; i++) {
1782 rtw89_write_rf(rtwdev, path, rf_reg[i], RFREG_MASK, rf_bkup[path][i]);
1783
1784 rtw89_debug(rtwdev, RTW89_DBG_RFK,
1785 "[DPK] Reload RF S%d 0x%x = %x\n", path,
1786 rf_reg[i], rf_bkup[path][i]);
1787 }
1788 }
1789
_dpk_one_shot(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy,enum rtw89_rf_path path,enum dpk_id id)1790 static void _dpk_one_shot(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
1791 enum rtw89_rf_path path, enum dpk_id id)
1792 {
1793 u16 dpk_cmd;
1794 u32 val;
1795 int ret;
1796
1797 dpk_cmd = ((id << 8) | (0x19 + path * 0x12));
1798 rtw89_phy_write32_mask(rtwdev, R_NCTL_CFG, MASKDWORD, dpk_cmd);
1799
1800 ret = read_poll_timeout_atomic(rtw89_phy_read32_mask, val, val == 0x55,
1801 10, 20000, false,
1802 rtwdev, 0xbff8, MASKBYTE0);
1803 if (ret)
1804 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] one-shot 1 timeout\n");
1805
1806 udelay(1);
1807
1808 ret = read_poll_timeout_atomic(rtw89_phy_read32_mask, val, val == 0x8000,
1809 1, 2000, false,
1810 rtwdev, R_RPT_COM, MASKLWORD);
1811 if (ret)
1812 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] one-shot 2 timeout\n");
1813
1814 rtw89_phy_write32_mask(rtwdev, R_NCTL_N1, MASKBYTE0, 0x0);
1815
1816 rtw89_debug(rtwdev, RTW89_DBG_RFK,
1817 "[DPK] one-shot for %s = 0x%04x\n",
1818 id == 0x28 ? "KIP_PRESET" :
1819 id == 0x29 ? "DPK_TXAGC" :
1820 id == 0x2a ? "DPK_RXAGC" :
1821 id == 0x2b ? "SYNC" :
1822 id == 0x2c ? "GAIN_LOSS" :
1823 id == 0x2d ? "MDPK_IDL" :
1824 id == 0x2f ? "DPK_GAIN_NORM" :
1825 id == 0x31 ? "KIP_RESTORE" :
1826 id == 0x6 ? "LBK_RXIQK" : "Unknown id",
1827 dpk_cmd);
1828 }
1829
_dpk_onoff(struct rtw89_dev * rtwdev,enum rtw89_rf_path path,bool off)1830 static void _dpk_onoff(struct rtw89_dev *rtwdev, enum rtw89_rf_path path,
1831 bool off)
1832 {
1833 struct rtw89_dpk_info *dpk = &rtwdev->dpk;
1834 u8 kidx = dpk->cur_idx[path];
1835 u8 off_reverse = off ? 0 : 1;
1836 u8 val;
1837
1838 val = dpk->is_dpk_enable * off_reverse * dpk->bp[path][kidx].path_ok;
1839
1840 rtw89_phy_write32_mask(rtwdev, R_DPD_CH0A + (path << 8) + (kidx << 2),
1841 0xf0000000, val);
1842
1843 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] S%d[%d] DPK %s !!!\n", path,
1844 kidx, val == 0 ? "disable" : "enable");
1845 }
1846
_dpk_init(struct rtw89_dev * rtwdev,enum rtw89_rf_path path)1847 static void _dpk_init(struct rtw89_dev *rtwdev, enum rtw89_rf_path path)
1848 {
1849 struct rtw89_dpk_info *dpk = &rtwdev->dpk;
1850
1851 u8 kidx = dpk->cur_idx[path];
1852
1853 dpk->bp[path][kidx].path_ok = 0;
1854 }
1855
_dpk_information(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy,enum rtw89_rf_path path,enum rtw89_chanctx_idx chanctx_idx)1856 static void _dpk_information(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
1857 enum rtw89_rf_path path, enum rtw89_chanctx_idx chanctx_idx)
1858 {
1859 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, chanctx_idx);
1860 struct rtw89_dpk_info *dpk = &rtwdev->dpk;
1861
1862 u8 kidx = dpk->cur_idx[path];
1863
1864 dpk->bp[path][kidx].band = chan->band_type;
1865 dpk->bp[path][kidx].ch = chan->band_width;
1866 dpk->bp[path][kidx].bw = chan->channel;
1867
1868 rtw89_debug(rtwdev, RTW89_DBG_RFK,
1869 "[DPK] S%d[%d] (PHY%d): TSSI %s/ DBCC %s/ %s/ CH%d/ %s\n",
1870 path, dpk->cur_idx[path], phy,
1871 rtwdev->is_tssi_mode[path] ? "on" : "off",
1872 rtwdev->dbcc_en ? "on" : "off",
1873 dpk->bp[path][kidx].band == 0 ? "2G" :
1874 dpk->bp[path][kidx].band == 1 ? "5G" : "6G",
1875 dpk->bp[path][kidx].ch,
1876 dpk->bp[path][kidx].bw == 0 ? "20M" :
1877 dpk->bp[path][kidx].bw == 1 ? "40M" :
1878 dpk->bp[path][kidx].bw == 2 ? "80M" : "160M");
1879 }
1880
_dpk_rxagc_onoff(struct rtw89_dev * rtwdev,enum rtw89_rf_path path,bool turn_on)1881 static void _dpk_rxagc_onoff(struct rtw89_dev *rtwdev, enum rtw89_rf_path path,
1882 bool turn_on)
1883 {
1884 if (path == RF_PATH_A)
1885 rtw89_phy_write32_mask(rtwdev, R_P0_AGC_CTL, B_P0_AGC_EN, turn_on);
1886 else
1887 rtw89_phy_write32_mask(rtwdev, R_P1_AGC_CTL, B_P1_AGC_EN, turn_on);
1888
1889 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] S%d RXAGC is %s\n", path,
1890 turn_on ? "turn_on" : "turn_off");
1891 }
1892
_dpk_bb_afe_setting(struct rtw89_dev * rtwdev,enum rtw89_rf_path path)1893 static void _dpk_bb_afe_setting(struct rtw89_dev *rtwdev, enum rtw89_rf_path path)
1894 {
1895 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, BIT(16 + path), 0x1);
1896 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, BIT(20 + path), 0x0);
1897 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, BIT(24 + path), 0x1);
1898 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, BIT(28 + path), 0x0);
1899 rtw89_phy_write32_mask(rtwdev, R_UPD_CLK + (path << 13), MASKDWORD, 0xd801dffd);
1900
1901 _txck_force(rtwdev, path, true, DAC_960M);
1902 _rxck_force(rtwdev, path, true, ADC_1920M);
1903
1904 rtw89_phy_write32_mask(rtwdev, R_DCIM, B_DCIM_FR, 0x0);
1905 rtw89_phy_write32_mask(rtwdev, R_ADCMOD, B_ADCMOD_AUTO_RST, 0x1);
1906 rtw89_phy_write32_mask(rtwdev, R_P0_NRBW, B_P0_NRBW_DBG, 0x1);
1907 udelay(1);
1908 rtw89_phy_write32_mask(rtwdev, R_ANAPAR_PW15, B_ANAPAR_PW15, 0x1f);
1909 udelay(10);
1910 rtw89_phy_write32_mask(rtwdev, R_ANAPAR_PW15, B_ANAPAR_PW15, 0x13);
1911 udelay(2);
1912 rtw89_phy_write32_mask(rtwdev, R_ANAPAR, B_ANAPAR_15, 0x0001);
1913 udelay(2);
1914 rtw89_phy_write32_mask(rtwdev, R_ANAPAR, B_ANAPAR_15, 0x0041);
1915 udelay(10);
1916
1917 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, BIT(20 + path), 0x1);
1918 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, BIT(28 + path), 0x1);
1919
1920 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] S%d BB/AFE setting\n", path);
1921 }
1922
_dpk_bb_afe_restore(struct rtw89_dev * rtwdev,enum rtw89_rf_path path)1923 static void _dpk_bb_afe_restore(struct rtw89_dev *rtwdev, enum rtw89_rf_path path)
1924 {
1925 rtw89_phy_write32_mask(rtwdev, R_P0_NRBW + (path << 13), B_P0_NRBW_DBG, 0x0);
1926 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, BIT(16 + path), 0x1);
1927 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, BIT(20 + path), 0x0);
1928 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, BIT(24 + path), 0x1);
1929 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, BIT(28 + path), 0x0);
1930 rtw89_phy_write32_mask(rtwdev, R_UPD_CLK + (path << 13), MASKDWORD, 0x00000000);
1931 rtw89_phy_write32_mask(rtwdev, R_P0_RXCK + (path << 13), B_P0_TXCK_ALL, 0x00);
1932 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, BIT(16 + path), 0x0);
1933 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, BIT(24 + path), 0x0);
1934
1935 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] S%d BB/AFE restore\n", path);
1936 }
1937
_dpk_tssi_pause(struct rtw89_dev * rtwdev,enum rtw89_rf_path path,bool is_pause)1938 static void _dpk_tssi_pause(struct rtw89_dev *rtwdev, enum rtw89_rf_path path,
1939 bool is_pause)
1940 {
1941 rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_TRK + (path << 13),
1942 B_P0_TSSI_TRK_EN, is_pause);
1943
1944 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] S%d TSSI %s\n", path,
1945 is_pause ? "pause" : "resume");
1946 }
1947
1948 static
_dpk_tssi_slope_k_onoff(struct rtw89_dev * rtwdev,enum rtw89_rf_path path,bool is_on)1949 void _dpk_tssi_slope_k_onoff(struct rtw89_dev *rtwdev, enum rtw89_rf_path path,
1950 bool is_on)
1951 {
1952 rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_SLOPE_CAL + (path << 13),
1953 B_P0_TSSI_SLOPE_CAL_EN, is_on);
1954
1955 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] S%d TSSI slpoe_k %s\n", path,
1956 str_on_off(is_on));
1957 }
1958
_dpk_tpg_sel(struct rtw89_dev * rtwdev,enum rtw89_rf_path path,u8 kidx)1959 static void _dpk_tpg_sel(struct rtw89_dev *rtwdev, enum rtw89_rf_path path, u8 kidx)
1960 {
1961 struct rtw89_dpk_info *dpk = &rtwdev->dpk;
1962
1963 if (dpk->bp[path][kidx].bw == RTW89_CHANNEL_WIDTH_80) {
1964 rtw89_phy_write32_mask(rtwdev, R_TPG_MOD, B_TPG_MOD_F, 0x0);
1965 rtw89_phy_write32_mask(rtwdev, R_TPG_SEL, MASKDWORD, 0xffe0fa00);
1966 } else if (dpk->bp[path][kidx].bw == RTW89_CHANNEL_WIDTH_40) {
1967 rtw89_phy_write32_mask(rtwdev, R_TPG_MOD, B_TPG_MOD_F, 0x2);
1968 rtw89_phy_write32_mask(rtwdev, R_TPG_SEL, MASKDWORD, 0xff4009e0);
1969 } else {
1970 rtw89_phy_write32_mask(rtwdev, R_TPG_MOD, B_TPG_MOD_F, 0x1);
1971 rtw89_phy_write32_mask(rtwdev, R_TPG_SEL, MASKDWORD, 0xf9f007d0);
1972 }
1973
1974 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] TPG Select for %s\n",
1975 dpk->bp[path][kidx].bw == RTW89_CHANNEL_WIDTH_80 ? "80M" :
1976 dpk->bp[path][kidx].bw == RTW89_CHANNEL_WIDTH_40 ? "40M" : "20M");
1977 }
1978
_dpk_txpwr_bb_force(struct rtw89_dev * rtwdev,enum rtw89_rf_path path,bool force)1979 static void _dpk_txpwr_bb_force(struct rtw89_dev *rtwdev,
1980 enum rtw89_rf_path path, bool force)
1981 {
1982 rtw89_phy_write32_mask(rtwdev, R_TXPWRB + (path << 13), B_TXPWRB_ON, force);
1983 rtw89_phy_write32_mask(rtwdev, R_TXPWRB_H + (path << 13), B_TXPWRB_RDY, force);
1984
1985 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] S%d txpwr_bb_force %s\n",
1986 path, force ? "on" : "off");
1987 }
1988
_dpk_kip_pwr_clk_onoff(struct rtw89_dev * rtwdev,bool turn_on)1989 static void _dpk_kip_pwr_clk_onoff(struct rtw89_dev *rtwdev, bool turn_on)
1990 {
1991 if (turn_on) {
1992 rtw89_phy_write32_mask(rtwdev, R_NCTL_RPT, MASKDWORD, 0x00000080);
1993 rtw89_phy_write32_mask(rtwdev, R_KIP_SYSCFG, MASKDWORD, 0x807f030a);
1994 } else {
1995 rtw89_phy_write32_mask(rtwdev, R_NCTL_RPT, MASKDWORD, 0x00000000);
1996 rtw89_phy_write32_mask(rtwdev, R_KIP_SYSCFG, MASKDWORD, 0x80000000);
1997 rtw89_phy_write32_mask(rtwdev, R_DPK_WR, BIT(18), 0x1);
1998 }
1999 }
2000
_dpk_kip_control_rfc(struct rtw89_dev * rtwdev,enum rtw89_rf_path path,bool ctrl_by_kip)2001 static void _dpk_kip_control_rfc(struct rtw89_dev *rtwdev,
2002 enum rtw89_rf_path path, bool ctrl_by_kip)
2003 {
2004 rtw89_phy_write32_mask(rtwdev, R_UPD_CLK + (path << 13),
2005 B_IQK_RFC_ON, ctrl_by_kip);
2006 }
2007
_dpk_kip_preset(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy,enum rtw89_rf_path path,u8 kidx)2008 static void _dpk_kip_preset(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
2009 enum rtw89_rf_path path, u8 kidx)
2010 {
2011 rtw89_phy_write32_mask(rtwdev, R_KIP_MOD, B_KIP_MOD,
2012 rtw89_read_rf(rtwdev, path, RR_MOD, RFREG_MASK));
2013 rtw89_phy_write32_mask(rtwdev, R_DPD_CH0A + (path << 8) + (kidx << 2),
2014 B_DPD_SEL, 0x01);
2015
2016 _dpk_kip_control_rfc(rtwdev, path, true);
2017 _dpk_one_shot(rtwdev, phy, path, D_KIP_PRESET);
2018 }
2019
_dpk_kip_restore(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy,enum rtw89_rf_path path)2020 static void _dpk_kip_restore(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
2021 enum rtw89_rf_path path)
2022 {
2023 _dpk_one_shot(rtwdev, phy, path, D_KIP_RESTORE);
2024 _dpk_kip_control_rfc(rtwdev, path, false);
2025 _dpk_txpwr_bb_force(rtwdev, path, false);
2026
2027 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] S%d restore KIP\n", path);
2028 }
2029
_dpk_kset_query(struct rtw89_dev * rtwdev,enum rtw89_rf_path path)2030 static void _dpk_kset_query(struct rtw89_dev *rtwdev, enum rtw89_rf_path path)
2031 {
2032 struct rtw89_dpk_info *dpk = &rtwdev->dpk;
2033
2034 rtw89_phy_write32_mask(rtwdev, R_KIP_RPT + (path << 8), B_KIP_RPT_SEL, 0x10);
2035
2036 dpk->cur_k_set =
2037 rtw89_phy_read32_mask(rtwdev, R_RPT_PER + (path << 8), B_RPT_PER_KSET) - 1;
2038 }
2039
_dpk_para_query(struct rtw89_dev * rtwdev,enum rtw89_rf_path path,u8 kidx)2040 static void _dpk_para_query(struct rtw89_dev *rtwdev, enum rtw89_rf_path path, u8 kidx)
2041 {
2042 static const u32 reg[RTW89_DPK_BKUP_NUM][DPK_KSET_NUM] = {
2043 {0x8190, 0x8194, 0x8198, 0x81a4},
2044 {0x81a8, 0x81c4, 0x81c8, 0x81e8}
2045 };
2046 struct rtw89_dpk_info *dpk = &rtwdev->dpk;
2047 u8 cur_k_set = dpk->cur_k_set;
2048 u32 para;
2049
2050 if (cur_k_set >= DPK_KSET_NUM) {
2051 rtw89_warn(rtwdev, "DPK cur_k_set = %d\n", cur_k_set);
2052 cur_k_set = 2;
2053 }
2054
2055 para = rtw89_phy_read32_mask(rtwdev, reg[kidx][cur_k_set] + (path << 8),
2056 MASKDWORD);
2057
2058 dpk->bp[path][kidx].txagc_dpk = (para >> 10) & 0x3f;
2059 dpk->bp[path][kidx].ther_dpk = (para >> 26) & 0x3f;
2060
2061 rtw89_debug(rtwdev, RTW89_DBG_RFK,
2062 "[DPK] thermal/ txagc_RF (K%d) = 0x%x/ 0x%x\n",
2063 dpk->cur_k_set, dpk->bp[path][kidx].ther_dpk,
2064 dpk->bp[path][kidx].txagc_dpk);
2065 }
2066
_dpk_sync_check(struct rtw89_dev * rtwdev,enum rtw89_rf_path path,u8 kidx)2067 static bool _dpk_sync_check(struct rtw89_dev *rtwdev, enum rtw89_rf_path path, u8 kidx)
2068 {
2069 struct rtw89_dpk_info *dpk = &rtwdev->dpk;
2070 u8 corr_val, corr_idx, rxbb;
2071 u16 dc_i, dc_q;
2072 u8 rxbb_ov;
2073
2074 rtw89_phy_write32_mask(rtwdev, R_KIP_RPT1, B_KIP_RPT1_SEL, 0x0);
2075
2076 corr_idx = rtw89_phy_read32_mask(rtwdev, R_RPT_COM, B_PRT_COM_CORI);
2077 corr_val = rtw89_phy_read32_mask(rtwdev, R_RPT_COM, B_PRT_COM_CORV);
2078 dpk->corr_idx[path][kidx] = corr_idx;
2079 dpk->corr_val[path][kidx] = corr_val;
2080
2081 rtw89_phy_write32_mask(rtwdev, R_KIP_RPT1, B_KIP_RPT1_SEL, 0x9);
2082
2083 dc_i = rtw89_phy_read32_mask(rtwdev, R_RPT_COM, B_PRT_COM_DCI);
2084 dc_q = rtw89_phy_read32_mask(rtwdev, R_RPT_COM, B_PRT_COM_DCQ);
2085
2086 dc_i = abs(sign_extend32(dc_i, 11));
2087 dc_q = abs(sign_extend32(dc_q, 11));
2088
2089 rtw89_debug(rtwdev, RTW89_DBG_RFK,
2090 "[DPK] S%d Corr_idx/ Corr_val /DC I/Q, = %d / %d / %d / %d\n",
2091 path, corr_idx, corr_val, dc_i, dc_q);
2092
2093 dpk->dc_i[path][kidx] = dc_i;
2094 dpk->dc_q[path][kidx] = dc_q;
2095
2096 rtw89_phy_write32_mask(rtwdev, R_KIP_RPT1, B_KIP_RPT1_SEL, 0x8);
2097 rxbb = rtw89_phy_read32_mask(rtwdev, R_RPT_COM, B_PRT_COM_RXBB);
2098
2099 rtw89_phy_write32_mask(rtwdev, R_KIP_RPT1, B_KIP_RPT1_SEL, 0x31);
2100 rxbb_ov = rtw89_phy_read32_mask(rtwdev, R_RPT_COM, B_PRT_COM_RXOV);
2101
2102 rtw89_debug(rtwdev, RTW89_DBG_RFK,
2103 "[DPK] S%d RXBB/ RXAGC_done /RXBB_ovlmt = %d / %d / %d\n",
2104 path, rxbb,
2105 rtw89_phy_read32_mask(rtwdev, R_RPT_COM, B_PRT_COM_DONE),
2106 rxbb_ov);
2107
2108 if (dc_i > 200 || dc_q > 200 || corr_val < 170)
2109 return true;
2110 else
2111 return false;
2112 }
2113
_dpk_kip_set_txagc(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy,enum rtw89_rf_path path,u8 dbm,bool set_from_bb)2114 static void _dpk_kip_set_txagc(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
2115 enum rtw89_rf_path path, u8 dbm,
2116 bool set_from_bb)
2117 {
2118 if (set_from_bb) {
2119 dbm = clamp_t(u8, dbm, 7, 24);
2120
2121 rtw89_debug(rtwdev, RTW89_DBG_RFK,
2122 "[DPK] set S%d txagc to %ddBm\n", path, dbm);
2123 rtw89_phy_write32_mask(rtwdev, R_TXPWRB + (path << 13),
2124 B_TXPWRB_VAL, dbm << 2);
2125 }
2126
2127 _dpk_one_shot(rtwdev, phy, path, D_TXAGC);
2128 _dpk_kset_query(rtwdev, path);
2129 }
2130
_dpk_kip_set_rxagc(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy,enum rtw89_rf_path path,u8 kidx)2131 static bool _dpk_kip_set_rxagc(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
2132 enum rtw89_rf_path path, u8 kidx)
2133 {
2134 _dpk_kip_control_rfc(rtwdev, path, false);
2135 rtw89_phy_write32_mask(rtwdev, R_KIP_MOD, B_KIP_MOD,
2136 rtw89_read_rf(rtwdev, path, RR_MOD, RFREG_MASK));
2137 _dpk_kip_control_rfc(rtwdev, path, true);
2138
2139 _dpk_one_shot(rtwdev, phy, path, D_RXAGC);
2140 return _dpk_sync_check(rtwdev, path, kidx);
2141 }
2142
_dpk_lbk_rxiqk(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy,enum rtw89_rf_path path)2143 static void _dpk_lbk_rxiqk(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
2144 enum rtw89_rf_path path)
2145 {
2146 u32 rf_11, reg_81cc;
2147 u8 cur_rxbb;
2148
2149 rtw89_phy_write32_mask(rtwdev, R_DPD_V1 + (path << 8), B_DPD_LBK, 0x1);
2150 rtw89_phy_write32_mask(rtwdev, R_MDPK_RX_DCK, B_MDPK_RX_DCK_EN, 0x1);
2151
2152 _dpk_kip_control_rfc(rtwdev, path, false);
2153
2154 cur_rxbb = rtw89_read_rf(rtwdev, path, RR_MOD, RR_MOD_RXB);
2155 rf_11 = rtw89_read_rf(rtwdev, path, RR_TXIG, RFREG_MASK);
2156 reg_81cc = rtw89_phy_read32_mask(rtwdev, R_KIP_IQP + (path << 8),
2157 B_KIP_IQP_SW);
2158
2159 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR0, 0x0);
2160 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_GR1, 0x3);
2161 rtw89_write_rf(rtwdev, path, RR_TXIG, RR_TXIG_TG, 0xd);
2162 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_RXB, 0x1f);
2163
2164 rtw89_phy_write32_mask(rtwdev, R_KIP_IQP + (path << 8), B_KIP_IQP_IQSW, 0x12);
2165 rtw89_phy_write32_mask(rtwdev, R_KIP_IQP + (path << 8), B_KIP_IQP_SW, 0x3);
2166
2167 _dpk_kip_control_rfc(rtwdev, path, true);
2168
2169 rtw89_phy_write32_mask(rtwdev, R_IQK_DIF4, MASKDWORD, 0x00250025);
2170
2171 _dpk_one_shot(rtwdev, phy, path, LBK_RXIQK);
2172
2173 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] S%d LBK RXIQC = 0x%x\n", path,
2174 rtw89_phy_read32_mask(rtwdev, R_RXIQC + (path << 8), MASKDWORD));
2175
2176 _dpk_kip_control_rfc(rtwdev, path, false);
2177
2178 rtw89_write_rf(rtwdev, path, RR_TXIG, RFREG_MASK, rf_11);
2179 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_RXB, cur_rxbb);
2180 rtw89_phy_write32_mask(rtwdev, R_KIP_IQP + (path << 8), B_KIP_IQP_SW, reg_81cc);
2181
2182 rtw89_phy_write32_mask(rtwdev, R_MDPK_RX_DCK, B_MDPK_RX_DCK_EN, 0x0);
2183 rtw89_phy_write32_mask(rtwdev, R_KPATH_CFG, B_KPATH_CFG_ED, 0x0);
2184 rtw89_phy_write32_mask(rtwdev, R_LOAD_COEF + (path << 8), B_LOAD_COEF_DI, 0x1);
2185
2186 _dpk_kip_control_rfc(rtwdev, path, true);
2187 }
2188
_dpk_rf_setting(struct rtw89_dev * rtwdev,enum rtw89_rf_path path,u8 kidx)2189 static void _dpk_rf_setting(struct rtw89_dev *rtwdev, enum rtw89_rf_path path, u8 kidx)
2190 {
2191 struct rtw89_dpk_info *dpk = &rtwdev->dpk;
2192
2193 if (dpk->bp[path][kidx].band == RTW89_BAND_2G) {
2194 rtw89_write_rf(rtwdev, path, RR_MOD, RFREG_MASK, 0x50521);
2195 rtw89_write_rf(rtwdev, path, RR_MOD_V1, RR_MOD_MASK, RF_DPK);
2196 rtw89_write_rf(rtwdev, path, RR_RXBB, RR_RXBB_ATTC, 0x0);
2197 rtw89_write_rf(rtwdev, path, RR_RXBB, RR_RXBB_ATTR, 0x7);
2198 } else {
2199 rtw89_write_rf(rtwdev, path, RR_MOD, RFREG_MASK,
2200 0x50521 | BIT(rtwdev->dbcc_en));
2201 rtw89_write_rf(rtwdev, path, RR_MOD_V1, RR_MOD_MASK, RF_DPK);
2202 rtw89_write_rf(rtwdev, path, RR_RXA2, RR_RAA2_SATT, 0x3);
2203 }
2204
2205 rtw89_write_rf(rtwdev, path, RR_RCKD, RR_RCKD_BW, 0x1);
2206 rtw89_write_rf(rtwdev, path, RR_BTC, RR_BTC_TXBB, dpk->bp[path][kidx].bw + 1);
2207 rtw89_write_rf(rtwdev, path, RR_BTC, RR_BTC_RXBB, 0x0);
2208 rtw89_write_rf(rtwdev, path, RR_RXBB2, RR_RXBB2_EBW, 0x0);
2209 }
2210
_dpk_bypass_rxiqc(struct rtw89_dev * rtwdev,enum rtw89_rf_path path)2211 static void _dpk_bypass_rxiqc(struct rtw89_dev *rtwdev, enum rtw89_rf_path path)
2212 {
2213 rtw89_phy_write32_mask(rtwdev, R_DPD_V1 + (path << 8), B_DPD_LBK, 0x1);
2214 rtw89_phy_write32_mask(rtwdev, R_RXIQC + (path << 8), MASKDWORD, 0x40000002);
2215
2216 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] Bypass RXIQC\n");
2217 }
2218
_dpk_dgain_read(struct rtw89_dev * rtwdev)2219 static u16 _dpk_dgain_read(struct rtw89_dev *rtwdev)
2220 {
2221 u16 dgain;
2222
2223 rtw89_phy_write32_mask(rtwdev, R_KIP_RPT1, B_KIP_RPT1_SEL, 0x0);
2224 dgain = rtw89_phy_read32_mask(rtwdev, R_RPT_COM, B_PRT_COM_DCI);
2225
2226 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] DGain = 0x%x\n", dgain);
2227
2228 return dgain;
2229 }
2230
_dpk_gainloss_read(struct rtw89_dev * rtwdev)2231 static u8 _dpk_gainloss_read(struct rtw89_dev *rtwdev)
2232 {
2233 u8 result;
2234
2235 rtw89_phy_write32_mask(rtwdev, R_KIP_RPT1, B_KIP_RPT1_SEL, 0x6);
2236 rtw89_phy_write32_mask(rtwdev, R_DPK_CFG2, B_DPK_CFG2_ST, 0x1);
2237 result = rtw89_phy_read32_mask(rtwdev, R_RPT_COM, B_PRT_COM_GL);
2238
2239 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] tmp GL = %d\n", result);
2240
2241 return result;
2242 }
2243
_dpk_gainloss(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy,enum rtw89_rf_path path,u8 kidx)2244 static u8 _dpk_gainloss(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
2245 enum rtw89_rf_path path, u8 kidx)
2246 {
2247 _dpk_one_shot(rtwdev, phy, path, D_GAIN_LOSS);
2248 _dpk_kip_set_txagc(rtwdev, phy, path, 0xff, false);
2249
2250 rtw89_phy_write32_mask(rtwdev, R_DPK_GL + (path << 8), B_DPK_GL_A1, 0xf078);
2251 rtw89_phy_write32_mask(rtwdev, R_DPK_GL + (path << 8), B_DPK_GL_A0, 0x0);
2252
2253 return _dpk_gainloss_read(rtwdev);
2254 }
2255
_dpk_pas_read(struct rtw89_dev * rtwdev,u8 is_check)2256 static u8 _dpk_pas_read(struct rtw89_dev *rtwdev, u8 is_check)
2257 {
2258 u32 val1_i = 0, val1_q = 0, val2_i = 0, val2_q = 0;
2259 u32 val1_sqrt_sum, val2_sqrt_sum;
2260 u8 i;
2261
2262 rtw89_phy_write32_mask(rtwdev, R_KIP_RPT1, MASKBYTE2, 0x06);
2263 rtw89_phy_write32_mask(rtwdev, R_DPK_CFG2, B_DPK_CFG2_ST, 0x0);
2264 rtw89_phy_write32_mask(rtwdev, R_DPK_CFG3, MASKBYTE2, 0x08);
2265
2266 if (is_check) {
2267 rtw89_phy_write32_mask(rtwdev, R_DPK_CFG3, MASKBYTE3, 0x00);
2268 val1_i = rtw89_phy_read32_mask(rtwdev, R_RPT_COM, MASKHWORD);
2269 val1_i = abs(sign_extend32(val1_i, 11));
2270 val1_q = rtw89_phy_read32_mask(rtwdev, R_RPT_COM, MASKLWORD);
2271 val1_q = abs(sign_extend32(val1_q, 11));
2272
2273 rtw89_phy_write32_mask(rtwdev, R_DPK_CFG3, MASKBYTE3, 0x1f);
2274 val2_i = rtw89_phy_read32_mask(rtwdev, R_RPT_COM, MASKHWORD);
2275 val2_i = abs(sign_extend32(val2_i, 11));
2276 val2_q = rtw89_phy_read32_mask(rtwdev, R_RPT_COM, MASKLWORD);
2277 val2_q = abs(sign_extend32(val2_q, 11));
2278
2279 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] PAS_delta = 0x%x\n",
2280 phy_div(val1_i * val1_i + val1_q * val1_q,
2281 val2_i * val2_i + val2_q * val2_q));
2282 } else {
2283 for (i = 0; i < 32; i++) {
2284 rtw89_phy_write32_mask(rtwdev, R_DPK_CFG3, MASKBYTE3, i);
2285 rtw89_debug(rtwdev, RTW89_DBG_RFK,
2286 "[DPK] PAS_Read[%02d]= 0x%08x\n", i,
2287 rtw89_phy_read32_mask(rtwdev, R_RPT_COM, MASKDWORD));
2288 }
2289 }
2290
2291 val1_sqrt_sum = val1_i * val1_i + val1_q * val1_q;
2292 val2_sqrt_sum = val2_i * val2_i + val2_q * val2_q;
2293
2294 if (val1_sqrt_sum < val2_sqrt_sum)
2295 return 2;
2296 else if (val1_sqrt_sum >= val2_sqrt_sum * 8 / 5)
2297 return 1;
2298 else
2299 return 0;
2300 }
2301
_dpk_agc(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy,enum rtw89_rf_path path,u8 kidx,u8 init_xdbm,u8 loss_only)2302 static u8 _dpk_agc(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
2303 enum rtw89_rf_path path, u8 kidx, u8 init_xdbm, u8 loss_only)
2304 {
2305 struct rtw89_dpk_info *dpk = &rtwdev->dpk;
2306 u8 tmp_dbm = init_xdbm, tmp_gl_idx = 0;
2307 u8 step = DPK_AGC_STEP_SYNC_DGAIN;
2308 u8 goout = 0, agc_cnt = 0;
2309 bool is_fail = false;
2310 int limit = 200;
2311 u8 tmp_rxbb;
2312 u16 dgain;
2313
2314 do {
2315 switch (step) {
2316 case DPK_AGC_STEP_SYNC_DGAIN:
2317 is_fail = _dpk_kip_set_rxagc(rtwdev, phy, path, kidx);
2318
2319 if (is_fail) {
2320 goout = 1;
2321 break;
2322 }
2323
2324 dgain = _dpk_dgain_read(rtwdev);
2325
2326 if (dgain > 0x5fc || dgain < 0x556) {
2327 _dpk_one_shot(rtwdev, phy, path, D_SYNC);
2328 _dpk_dgain_read(rtwdev);
2329 }
2330
2331 if (agc_cnt == 0) {
2332 if (dpk->bp[path][kidx].band == RTW89_BAND_2G)
2333 _dpk_bypass_rxiqc(rtwdev, path);
2334 else
2335 _dpk_lbk_rxiqk(rtwdev, phy, path);
2336 }
2337 step = DPK_AGC_STEP_GAIN_LOSS_IDX;
2338 break;
2339
2340 case DPK_AGC_STEP_GAIN_LOSS_IDX:
2341 tmp_gl_idx = _dpk_gainloss(rtwdev, phy, path, kidx);
2342
2343 if (_dpk_pas_read(rtwdev, true) == 2 && tmp_gl_idx > 0)
2344 step = DPK_AGC_STEP_GL_LT_CRITERION;
2345 else if ((tmp_gl_idx == 0 && _dpk_pas_read(rtwdev, true) == 1) ||
2346 tmp_gl_idx >= 7)
2347 step = DPK_AGC_STEP_GL_GT_CRITERION;
2348 else if (tmp_gl_idx == 0)
2349 step = DPK_AGC_STEP_GL_LT_CRITERION;
2350 else
2351 step = DPK_AGC_STEP_SET_TX_GAIN;
2352 break;
2353
2354 case DPK_AGC_STEP_GL_GT_CRITERION:
2355 if (tmp_dbm <= 7) {
2356 goout = 1;
2357 rtw89_debug(rtwdev, RTW89_DBG_RFK,
2358 "[DPK] Txagc@lower bound!!\n");
2359 } else {
2360 tmp_dbm = max_t(u8, tmp_dbm - 3, 7);
2361 _dpk_kip_set_txagc(rtwdev, phy, path, tmp_dbm, true);
2362 }
2363 step = DPK_AGC_STEP_SYNC_DGAIN;
2364 agc_cnt++;
2365 break;
2366
2367 case DPK_AGC_STEP_GL_LT_CRITERION:
2368 if (tmp_dbm >= 24) {
2369 goout = 1;
2370 rtw89_debug(rtwdev, RTW89_DBG_RFK,
2371 "[DPK] Txagc@upper bound!!\n");
2372 } else {
2373 tmp_dbm = min_t(u8, tmp_dbm + 2, 24);
2374 _dpk_kip_set_txagc(rtwdev, phy, path, tmp_dbm, true);
2375 }
2376 step = DPK_AGC_STEP_SYNC_DGAIN;
2377 agc_cnt++;
2378 break;
2379
2380 case DPK_AGC_STEP_SET_TX_GAIN:
2381 _dpk_kip_control_rfc(rtwdev, path, false);
2382 tmp_rxbb = rtw89_read_rf(rtwdev, path, RR_MOD, RR_MOD_RXB);
2383 tmp_rxbb = min_t(u8, tmp_rxbb + tmp_gl_idx, 0x1f);
2384
2385 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_RXB, tmp_rxbb);
2386
2387 rtw89_debug(rtwdev, RTW89_DBG_RFK,
2388 "[DPK] Adjust RXBB (%+d) = 0x%x\n",
2389 tmp_gl_idx, tmp_rxbb);
2390 _dpk_kip_control_rfc(rtwdev, path, true);
2391 goout = 1;
2392 break;
2393 default:
2394 goout = 1;
2395 break;
2396 }
2397 } while (!goout && agc_cnt < 6 && limit-- > 0);
2398
2399 return is_fail;
2400 }
2401
_dpk_set_mdpd_para(struct rtw89_dev * rtwdev,u8 order)2402 static void _dpk_set_mdpd_para(struct rtw89_dev *rtwdev, u8 order)
2403 {
2404 switch (order) {
2405 case 0: /* (5,3,1) */
2406 rtw89_phy_write32_mask(rtwdev, R_LDL_NORM, B_LDL_NORM_OP, 0x0);
2407 rtw89_phy_write32_mask(rtwdev, R_DPK_IDL, B_DPK_IDL_SEL, 0x2);
2408 rtw89_phy_write32_mask(rtwdev, R_LDL_NORM, B_LDL_NORM_PN, 0x3);
2409 rtw89_phy_write32_mask(rtwdev, R_MDPK_SYNC, B_MDPK_SYNC_DMAN, 0x1);
2410 break;
2411 case 1: /* (5,3,0) */
2412 rtw89_phy_write32_mask(rtwdev, R_LDL_NORM, B_LDL_NORM_OP, 0x1);
2413 rtw89_phy_write32_mask(rtwdev, R_DPK_IDL, B_DPK_IDL_SEL, 0x1);
2414 rtw89_phy_write32_mask(rtwdev, R_LDL_NORM, B_LDL_NORM_PN, 0x0);
2415 rtw89_phy_write32_mask(rtwdev, R_MDPK_SYNC, B_MDPK_SYNC_DMAN, 0x0);
2416 break;
2417 case 2: /* (5,0,0) */
2418 rtw89_phy_write32_mask(rtwdev, R_LDL_NORM, B_LDL_NORM_OP, 0x2);
2419 rtw89_phy_write32_mask(rtwdev, R_DPK_IDL, B_DPK_IDL_SEL, 0x0);
2420 rtw89_phy_write32_mask(rtwdev, R_LDL_NORM, B_LDL_NORM_PN, 0x0);
2421 rtw89_phy_write32_mask(rtwdev, R_MDPK_SYNC, B_MDPK_SYNC_DMAN, 0x0);
2422 break;
2423 case 3: /* (7,3,1) */
2424 rtw89_phy_write32_mask(rtwdev, R_LDL_NORM, B_LDL_NORM_OP, 0x3);
2425 rtw89_phy_write32_mask(rtwdev, R_DPK_IDL, B_DPK_IDL_SEL, 0x3);
2426 rtw89_phy_write32_mask(rtwdev, R_LDL_NORM, B_LDL_NORM_PN, 0x4);
2427 rtw89_phy_write32_mask(rtwdev, R_MDPK_SYNC, B_MDPK_SYNC_DMAN, 0x1);
2428 break;
2429 default:
2430 rtw89_debug(rtwdev, RTW89_DBG_RFK,
2431 "[DPK] Wrong MDPD order!!(0x%x)\n", order);
2432 break;
2433 }
2434
2435 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] Set %s for IDL\n",
2436 order == 0x0 ? "(5,3,1)" :
2437 order == 0x1 ? "(5,3,0)" :
2438 order == 0x2 ? "(5,0,0)" : "(7,3,1)");
2439 }
2440
_dpk_idl_mpa(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy,enum rtw89_rf_path path,u8 kidx)2441 static void _dpk_idl_mpa(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
2442 enum rtw89_rf_path path, u8 kidx)
2443 {
2444 if (rtw89_phy_read32_mask(rtwdev, R_IDL_MPA, B_IDL_MD500) == 0x1)
2445 _dpk_set_mdpd_para(rtwdev, 0x2);
2446 else if (rtw89_phy_read32_mask(rtwdev, R_IDL_MPA, B_IDL_MD530) == 0x1)
2447 _dpk_set_mdpd_para(rtwdev, 0x1);
2448 else
2449 _dpk_set_mdpd_para(rtwdev, 0x0);
2450
2451 rtw89_phy_write32_mask(rtwdev, R_DPK_IDL, B_DPK_IDL, 0x0);
2452 fsleep(1000);
2453
2454 _dpk_one_shot(rtwdev, phy, path, D_MDPK_IDL);
2455 }
2456
_dpk_order_convert(struct rtw89_dev * rtwdev)2457 static u8 _dpk_order_convert(struct rtw89_dev *rtwdev)
2458 {
2459 u32 order;
2460 u8 val;
2461
2462 order = rtw89_phy_read32_mask(rtwdev, R_LDL_NORM, B_LDL_NORM_OP);
2463
2464 switch (order) {
2465 case 0: /* (5,3,1) */
2466 val = 0x6;
2467 break;
2468 case 1: /* (5,3,0) */
2469 val = 0x2;
2470 break;
2471 case 2: /* (5,0,0) */
2472 val = 0x0;
2473 break;
2474 default:
2475 val = 0xff;
2476 break;
2477 }
2478
2479 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] convert MDPD order to 0x%x\n", val);
2480
2481 return val;
2482 }
2483
_dpk_gain_normalize(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy,enum rtw89_rf_path path,u8 kidx,bool is_execute)2484 static void _dpk_gain_normalize(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
2485 enum rtw89_rf_path path, u8 kidx, bool is_execute)
2486 {
2487 static const u32 reg[RTW89_DPK_BKUP_NUM][DPK_KSET_NUM] = {
2488 {0x8190, 0x8194, 0x8198, 0x81a4},
2489 {0x81a8, 0x81c4, 0x81c8, 0x81e8}
2490 };
2491 struct rtw89_dpk_info *dpk = &rtwdev->dpk;
2492 u8 cur_k_set = dpk->cur_k_set;
2493
2494 if (cur_k_set >= DPK_KSET_NUM) {
2495 rtw89_warn(rtwdev, "DPK cur_k_set = %d\n", cur_k_set);
2496 cur_k_set = 2;
2497 }
2498
2499 if (is_execute) {
2500 rtw89_phy_write32_mask(rtwdev, R_DPK_GN + (path << 8),
2501 B_DPK_GN_AG, 0x200);
2502 rtw89_phy_write32_mask(rtwdev, R_DPK_GN + (path << 8),
2503 B_DPK_GN_EN, 0x3);
2504
2505 _dpk_one_shot(rtwdev, phy, path, D_GAIN_NORM);
2506 } else {
2507 rtw89_phy_write32_mask(rtwdev, reg[kidx][cur_k_set] + (path << 8),
2508 0x0000007F, 0x5b);
2509 }
2510
2511 dpk->bp[path][kidx].gs =
2512 rtw89_phy_read32_mask(rtwdev, reg[kidx][cur_k_set] + (path << 8),
2513 0x0000007F);
2514 }
2515
_dpk_on(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy,enum rtw89_rf_path path,u8 kidx)2516 static void _dpk_on(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
2517 enum rtw89_rf_path path, u8 kidx)
2518 {
2519 struct rtw89_dpk_info *dpk = &rtwdev->dpk;
2520
2521 rtw89_phy_write32_mask(rtwdev, R_LOAD_COEF + (path << 8), B_LOAD_COEF_MDPD, 0x1);
2522 rtw89_phy_write32_mask(rtwdev, R_LOAD_COEF + (path << 8), B_LOAD_COEF_MDPD, 0x0);
2523 rtw89_phy_write32_mask(rtwdev, R_DPD_CH0A + (path << 8) + (kidx << 2),
2524 B_DPD_ORDER, _dpk_order_convert(rtwdev));
2525
2526 dpk->bp[path][kidx].path_ok =
2527 dpk->bp[path][kidx].path_ok | BIT(dpk->cur_k_set);
2528
2529 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] S%d[%d] path_ok = 0x%x\n",
2530 path, kidx, dpk->bp[path][kidx].path_ok);
2531
2532 rtw89_phy_write32_mask(rtwdev, R_DPD_CH0A + (path << 8) + (kidx << 2),
2533 B_DPD_MEN, dpk->bp[path][kidx].path_ok);
2534
2535 _dpk_gain_normalize(rtwdev, phy, path, kidx, false);
2536 }
2537
_dpk_main(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy,enum rtw89_rf_path path)2538 static bool _dpk_main(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
2539 enum rtw89_rf_path path)
2540 {
2541 struct rtw89_dpk_info *dpk = &rtwdev->dpk;
2542 u8 kidx = dpk->cur_idx[path];
2543 u8 init_xdbm = 17;
2544 bool is_fail;
2545
2546 _dpk_kip_control_rfc(rtwdev, path, false);
2547 _rfk_rf_direct_cntrl(rtwdev, path, false);
2548 rtw89_write_rf(rtwdev, path, RR_BBDC, RFREG_MASK, 0x03ffd);
2549
2550 _dpk_rf_setting(rtwdev, path, kidx);
2551 _set_rx_dck(rtwdev, path, RF_DPK);
2552
2553 _dpk_kip_pwr_clk_onoff(rtwdev, true);
2554 _dpk_kip_preset(rtwdev, phy, path, kidx);
2555 _dpk_txpwr_bb_force(rtwdev, path, true);
2556 _dpk_kip_set_txagc(rtwdev, phy, path, init_xdbm, true);
2557 _dpk_tpg_sel(rtwdev, path, kidx);
2558 is_fail = _dpk_agc(rtwdev, phy, path, kidx, init_xdbm, false);
2559 if (is_fail)
2560 goto _error;
2561
2562 _dpk_idl_mpa(rtwdev, phy, path, kidx);
2563 _dpk_para_query(rtwdev, path, kidx);
2564
2565 _dpk_on(rtwdev, phy, path, kidx);
2566 _error:
2567 _dpk_kip_control_rfc(rtwdev, path, false);
2568 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_MASK, RF_RX);
2569
2570 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] S%d[%d]_K%d %s\n", path, kidx,
2571 dpk->cur_k_set, is_fail ? "need Check" : "is Success");
2572
2573 return is_fail;
2574 }
2575
_dpk_cal_select(struct rtw89_dev * rtwdev,bool force,enum rtw89_phy_idx phy,u8 kpath,enum rtw89_chanctx_idx chanctx_idx)2576 static void _dpk_cal_select(struct rtw89_dev *rtwdev, bool force,
2577 enum rtw89_phy_idx phy, u8 kpath,
2578 enum rtw89_chanctx_idx chanctx_idx)
2579 {
2580 struct rtw89_dpk_info *dpk = &rtwdev->dpk;
2581 u32 kip_bkup[RF_PATH_NUM_8851B][DPK_KIP_REG_NUM_8851B] = {};
2582 u32 rf_bkup[RF_PATH_NUM_8851B][DPK_RF_REG_NUM_8851B] = {};
2583 bool is_fail;
2584 u8 path;
2585
2586 for (path = 0; path < RF_PATH_NUM_8851B; path++)
2587 dpk->cur_idx[path] = 0;
2588
2589 for (path = 0; path < RF_PATH_NUM_8851B; path++) {
2590 if (!(kpath & BIT(path)))
2591 continue;
2592 _dpk_bkup_kip(rtwdev, dpk_kip_reg, kip_bkup, path);
2593 _dpk_bkup_rf(rtwdev, dpk_rf_reg, rf_bkup, path);
2594 _dpk_information(rtwdev, phy, path, chanctx_idx);
2595 _dpk_init(rtwdev, path);
2596
2597 if (rtwdev->is_tssi_mode[path])
2598 _dpk_tssi_pause(rtwdev, path, true);
2599 }
2600
2601 for (path = 0; path < RF_PATH_NUM_8851B; path++) {
2602 if (!(kpath & BIT(path)))
2603 continue;
2604
2605 rtw89_debug(rtwdev, RTW89_DBG_RFK,
2606 "[DPK] ========= S%d[%d] DPK Start =========\n",
2607 path, dpk->cur_idx[path]);
2608
2609 _dpk_tssi_slope_k_onoff(rtwdev, path, false);
2610 _dpk_rxagc_onoff(rtwdev, path, false);
2611 _rfk_drf_direct_cntrl(rtwdev, path, false);
2612 _dpk_bb_afe_setting(rtwdev, path);
2613
2614 is_fail = _dpk_main(rtwdev, phy, path);
2615 _dpk_onoff(rtwdev, path, is_fail);
2616 }
2617
2618 for (path = 0; path < RF_PATH_NUM_8851B; path++) {
2619 if (!(kpath & BIT(path)))
2620 continue;
2621
2622 _dpk_kip_restore(rtwdev, phy, path);
2623 _dpk_reload_kip(rtwdev, dpk_kip_reg, kip_bkup, path);
2624 _dpk_reload_rf(rtwdev, dpk_rf_reg, rf_bkup, path);
2625 _dpk_bb_afe_restore(rtwdev, path);
2626 _dpk_rxagc_onoff(rtwdev, path, true);
2627 _dpk_tssi_slope_k_onoff(rtwdev, path, true);
2628 if (rtwdev->is_tssi_mode[path])
2629 _dpk_tssi_pause(rtwdev, path, false);
2630 }
2631
2632 _dpk_kip_pwr_clk_onoff(rtwdev, false);
2633 }
2634
_dpk(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy,bool force,enum rtw89_chanctx_idx chanctx_idx)2635 static void _dpk(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy, bool force,
2636 enum rtw89_chanctx_idx chanctx_idx)
2637 {
2638 rtw89_debug(rtwdev, RTW89_DBG_RFK,
2639 "[DPK] ****** 8851B DPK Start (Ver: 0x%x, Cv: %d) ******\n",
2640 DPK_VER_8851B, rtwdev->hal.cv);
2641
2642 _dpk_cal_select(rtwdev, force, phy, _kpath(rtwdev, phy), chanctx_idx);
2643 }
2644
_dpk_track(struct rtw89_dev * rtwdev)2645 static void _dpk_track(struct rtw89_dev *rtwdev)
2646 {
2647 struct rtw89_dpk_info *dpk = &rtwdev->dpk;
2648 s8 txagc_bb, txagc_bb_tp, txagc_ofst;
2649 s16 pwsf_tssi_ofst;
2650 s8 delta_ther = 0;
2651 u8 path, kidx;
2652 u8 txagc_rf;
2653 u8 cur_ther;
2654
2655 for (path = 0; path < RF_PATH_NUM_8851B; path++) {
2656 kidx = dpk->cur_idx[path];
2657
2658 rtw89_debug(rtwdev, RTW89_DBG_RFK_TRACK,
2659 "[DPK_TRK] ================[S%d[%d] (CH %d)]================\n",
2660 path, kidx, dpk->bp[path][kidx].ch);
2661
2662 txagc_rf = rtw89_phy_read32_mask(rtwdev, R_TXAGC_BB + (path << 13),
2663 B_TXAGC_RF);
2664 txagc_bb = rtw89_phy_read32_mask(rtwdev, R_TXAGC_BB + (path << 13),
2665 MASKBYTE2);
2666 txagc_bb_tp = rtw89_phy_read32_mask(rtwdev, R_TXAGC_BTP + (path << 13),
2667 B_TXAGC_BTP);
2668
2669 rtw89_phy_write32_mask(rtwdev, R_KIP_RPT + (path << 8),
2670 B_KIP_RPT_SEL, 0xf);
2671 cur_ther = rtw89_phy_read32_mask(rtwdev, R_RPT_PER + (path << 8),
2672 B_RPT_PER_TH);
2673 txagc_ofst = rtw89_phy_read32_mask(rtwdev, R_RPT_PER + (path << 8),
2674 B_RPT_PER_OF);
2675 pwsf_tssi_ofst = rtw89_phy_read32_mask(rtwdev, R_RPT_PER + (path << 8),
2676 B_RPT_PER_TSSI);
2677 pwsf_tssi_ofst = sign_extend32(pwsf_tssi_ofst, 12);
2678
2679 delta_ther = cur_ther - dpk->bp[path][kidx].ther_dpk;
2680
2681 delta_ther = delta_ther * 2 / 3;
2682
2683 rtw89_debug(rtwdev, RTW89_DBG_RFK_TRACK,
2684 "[DPK_TRK] extra delta_ther = %d (0x%x / 0x%x@k)\n",
2685 delta_ther, cur_ther, dpk->bp[path][kidx].ther_dpk);
2686
2687 rtw89_debug(rtwdev, RTW89_DBG_RFK_TRACK,
2688 "[DPK_TRK] delta_txagc = %d (0x%x / 0x%x@k)\n",
2689 txagc_rf - dpk->bp[path][kidx].txagc_dpk,
2690 txagc_rf, dpk->bp[path][kidx].txagc_dpk);
2691
2692 rtw89_debug(rtwdev, RTW89_DBG_RFK_TRACK,
2693 "[DPK_TRK] txagc_offset / pwsf_tssi_ofst = 0x%x / %+d\n",
2694 txagc_ofst, pwsf_tssi_ofst);
2695
2696 rtw89_debug(rtwdev, RTW89_DBG_RFK_TRACK,
2697 "[DPK_TRK] txagc_bb_tp / txagc_bb = 0x%x / 0x%x\n",
2698 txagc_bb_tp, txagc_bb);
2699
2700 if (rtw89_phy_read32_mask(rtwdev, R_IDL_MPA, B_IDL_DN) == 0x0 &&
2701 txagc_rf != 0) {
2702 rtw89_debug(rtwdev, RTW89_DBG_RFK_TRACK,
2703 "[DPK_TRK] New pwsf = 0x%x\n", 0x78 - delta_ther);
2704
2705 rtw89_phy_write32_mask(rtwdev,
2706 R_DPD_BND + (path << 8) + (kidx << 2),
2707 0x07FC0000, 0x78 - delta_ther);
2708 }
2709 }
2710 }
2711
_rck(struct rtw89_dev * rtwdev,enum rtw89_rf_path path)2712 static void _rck(struct rtw89_dev *rtwdev, enum rtw89_rf_path path)
2713 {
2714 u32 rf_reg5;
2715 u32 rck_val;
2716 u32 val;
2717 int ret;
2718
2719 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[RCK] ====== S%d RCK ======\n", path);
2720
2721 rf_reg5 = rtw89_read_rf(rtwdev, path, RR_RSV1, RFREG_MASK);
2722
2723 rtw89_write_rf(rtwdev, path, RR_RSV1, RR_RSV1_RST, 0x0);
2724 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_MASK, RR_MOD_V_RX);
2725
2726 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[RCK] RF0x00 = 0x%05x\n",
2727 rtw89_read_rf(rtwdev, path, RR_MOD, RFREG_MASK));
2728
2729 /* RCK trigger */
2730 rtw89_write_rf(rtwdev, path, RR_RCKC, RFREG_MASK, 0x00240);
2731
2732 ret = read_poll_timeout_atomic(rtw89_read_rf, val, val, 2, 30,
2733 false, rtwdev, path, RR_RCKS, BIT(3));
2734
2735 rck_val = rtw89_read_rf(rtwdev, path, RR_RCKC, RR_RCKC_CA);
2736
2737 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[RCK] rck_val = 0x%x, ret = %d\n",
2738 rck_val, ret);
2739
2740 rtw89_write_rf(rtwdev, path, RR_RCKC, RFREG_MASK, rck_val);
2741 rtw89_write_rf(rtwdev, path, RR_RSV1, RFREG_MASK, rf_reg5);
2742
2743 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[RCK] RF 0x1b = 0x%x\n",
2744 rtw89_read_rf(rtwdev, path, RR_RCKC, RFREG_MASK));
2745 }
2746
_tssi_set_sys(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy,enum rtw89_rf_path path,const struct rtw89_chan * chan)2747 static void _tssi_set_sys(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
2748 enum rtw89_rf_path path, const struct rtw89_chan *chan)
2749 {
2750 enum rtw89_band band = chan->band_type;
2751
2752 rtw89_rfk_parser(rtwdev, &rtw8851b_tssi_sys_defs_tbl);
2753
2754 rtw89_rfk_parser_by_cond(rtwdev, band == RTW89_BAND_2G,
2755 &rtw8851b_tssi_sys_a_defs_2g_tbl,
2756 &rtw8851b_tssi_sys_a_defs_5g_tbl);
2757 }
2758
_tssi_ini_txpwr_ctrl_bb(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy,enum rtw89_rf_path path)2759 static void _tssi_ini_txpwr_ctrl_bb(struct rtw89_dev *rtwdev,
2760 enum rtw89_phy_idx phy,
2761 enum rtw89_rf_path path)
2762 {
2763 rtw89_rfk_parser(rtwdev, &rtw8851b_tssi_init_txpwr_defs_a_tbl);
2764 }
2765
_tssi_ini_txpwr_ctrl_bb_he_tb(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy,enum rtw89_rf_path path)2766 static void _tssi_ini_txpwr_ctrl_bb_he_tb(struct rtw89_dev *rtwdev,
2767 enum rtw89_phy_idx phy,
2768 enum rtw89_rf_path path)
2769 {
2770 rtw89_rfk_parser(rtwdev, &rtw8851b_tssi_init_txpwr_he_tb_defs_a_tbl);
2771 }
2772
_tssi_set_dck(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy,enum rtw89_rf_path path)2773 static void _tssi_set_dck(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
2774 enum rtw89_rf_path path)
2775 {
2776 rtw89_rfk_parser(rtwdev, &rtw8851b_tssi_dck_defs_a_tbl);
2777 }
2778
_tssi_set_tmeter_tbl(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy,enum rtw89_rf_path path,const struct rtw89_chan * chan)2779 static void _tssi_set_tmeter_tbl(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
2780 enum rtw89_rf_path path, const struct rtw89_chan *chan)
2781 {
2782 #define RTW8851B_TSSI_GET_VAL(ptr, idx) \
2783 ({ \
2784 s8 *__ptr = (ptr); \
2785 u8 __idx = (idx), __i, __v; \
2786 u32 __val = 0; \
2787 for (__i = 0; __i < 4; __i++) { \
2788 __v = (__ptr[__idx + __i]); \
2789 __val |= (__v << (8 * __i)); \
2790 } \
2791 __val; \
2792 })
2793 struct rtw89_tssi_info *tssi_info = &rtwdev->tssi;
2794 u8 ch = chan->channel;
2795 u8 subband = chan->subband_type;
2796 const s8 *thm_up_a = NULL;
2797 const s8 *thm_down_a = NULL;
2798 u8 thermal = 0xff;
2799 s8 thm_ofst[64] = {0};
2800 u32 tmp = 0;
2801 u8 i, j;
2802
2803 switch (subband) {
2804 default:
2805 case RTW89_CH_2G:
2806 thm_up_a = rtw89_8851b_trk_cfg.delta_swingidx_2ga_p;
2807 thm_down_a = rtw89_8851b_trk_cfg.delta_swingidx_2ga_n;
2808 break;
2809 case RTW89_CH_5G_BAND_1:
2810 thm_up_a = rtw89_8851b_trk_cfg.delta_swingidx_5ga_p[0];
2811 thm_down_a = rtw89_8851b_trk_cfg.delta_swingidx_5ga_n[0];
2812 break;
2813 case RTW89_CH_5G_BAND_3:
2814 thm_up_a = rtw89_8851b_trk_cfg.delta_swingidx_5ga_p[1];
2815 thm_down_a = rtw89_8851b_trk_cfg.delta_swingidx_5ga_n[1];
2816 break;
2817 case RTW89_CH_5G_BAND_4:
2818 thm_up_a = rtw89_8851b_trk_cfg.delta_swingidx_5ga_p[2];
2819 thm_down_a = rtw89_8851b_trk_cfg.delta_swingidx_5ga_n[2];
2820 break;
2821 }
2822
2823 if (path == RF_PATH_A) {
2824 thermal = tssi_info->thermal[RF_PATH_A];
2825
2826 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
2827 "[TSSI] ch=%d thermal_pathA=0x%x\n", ch, thermal);
2828
2829 rtw89_phy_write32_mask(rtwdev, R_P0_TMETER, B_P0_TMETER_DIS, 0x0);
2830 rtw89_phy_write32_mask(rtwdev, R_P0_TMETER, B_P0_TMETER_TRK, 0x1);
2831
2832 if (thermal == 0xff) {
2833 rtw89_phy_write32_mask(rtwdev, R_P0_TMETER, B_P0_TMETER, 32);
2834 rtw89_phy_write32_mask(rtwdev, R_P0_RFCTM, B_P0_RFCTM_VAL, 32);
2835
2836 for (i = 0; i < 64; i += 4) {
2837 rtw89_phy_write32(rtwdev, R_P0_TSSI_BASE + i, 0x0);
2838
2839 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
2840 "[TSSI] write 0x%x val=0x%08x\n",
2841 R_P0_TSSI_BASE + i, 0x0);
2842 }
2843
2844 } else {
2845 rtw89_phy_write32_mask(rtwdev, R_P0_TMETER, B_P0_TMETER,
2846 thermal);
2847 rtw89_phy_write32_mask(rtwdev, R_P0_RFCTM, B_P0_RFCTM_VAL,
2848 thermal);
2849
2850 i = 0;
2851 for (j = 0; j < 32; j++)
2852 thm_ofst[j] = i < DELTA_SWINGIDX_SIZE ?
2853 -thm_down_a[i++] :
2854 -thm_down_a[DELTA_SWINGIDX_SIZE - 1];
2855
2856 i = 1;
2857 for (j = 63; j >= 32; j--)
2858 thm_ofst[j] = i < DELTA_SWINGIDX_SIZE ?
2859 thm_up_a[i++] :
2860 thm_up_a[DELTA_SWINGIDX_SIZE - 1];
2861
2862 for (i = 0; i < 64; i += 4) {
2863 tmp = RTW8851B_TSSI_GET_VAL(thm_ofst, i);
2864 rtw89_phy_write32(rtwdev, R_P0_TSSI_BASE + i, tmp);
2865
2866 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
2867 "[TSSI] write 0x%x val=0x%08x\n",
2868 0x5c00 + i, tmp);
2869 }
2870 }
2871 rtw89_phy_write32_mask(rtwdev, R_P0_RFCTM, R_P0_RFCTM_RDY, 0x1);
2872 rtw89_phy_write32_mask(rtwdev, R_P0_RFCTM, R_P0_RFCTM_RDY, 0x0);
2873 }
2874 #undef RTW8851B_TSSI_GET_VAL
2875 }
2876
_tssi_set_dac_gain_tbl(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy,enum rtw89_rf_path path)2877 static void _tssi_set_dac_gain_tbl(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
2878 enum rtw89_rf_path path)
2879 {
2880 rtw89_rfk_parser(rtwdev, &rtw8851b_tssi_dac_gain_defs_a_tbl);
2881 }
2882
_tssi_slope_cal_org(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy,enum rtw89_rf_path path,const struct rtw89_chan * chan)2883 static void _tssi_slope_cal_org(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
2884 enum rtw89_rf_path path, const struct rtw89_chan *chan)
2885 {
2886 enum rtw89_band band = chan->band_type;
2887
2888 rtw89_rfk_parser_by_cond(rtwdev, band == RTW89_BAND_2G,
2889 &rtw8851b_tssi_slope_a_defs_2g_tbl,
2890 &rtw8851b_tssi_slope_a_defs_5g_tbl);
2891 }
2892
_tssi_alignment_default(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy,enum rtw89_rf_path path,bool all,const struct rtw89_chan * chan)2893 static void _tssi_alignment_default(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
2894 enum rtw89_rf_path path, bool all,
2895 const struct rtw89_chan *chan)
2896 {
2897 enum rtw89_band band = chan->band_type;
2898
2899 rtw89_rfk_parser_by_cond(rtwdev, band == RTW89_BAND_2G,
2900 &rtw8851b_tssi_align_a_2g_defs_tbl,
2901 &rtw8851b_tssi_align_a_5g_defs_tbl);
2902 }
2903
_tssi_set_tssi_slope(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy,enum rtw89_rf_path path)2904 static void _tssi_set_tssi_slope(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
2905 enum rtw89_rf_path path)
2906 {
2907 rtw89_rfk_parser(rtwdev, &rtw8851b_tssi_slope_defs_a_tbl);
2908 }
2909
_tssi_set_tssi_track(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy,enum rtw89_rf_path path)2910 static void _tssi_set_tssi_track(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
2911 enum rtw89_rf_path path)
2912 {
2913 rtw89_rfk_parser(rtwdev, &rtw8851b_tssi_track_defs_a_tbl);
2914 }
2915
_tssi_set_txagc_offset_mv_avg(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy,enum rtw89_rf_path path)2916 static void _tssi_set_txagc_offset_mv_avg(struct rtw89_dev *rtwdev,
2917 enum rtw89_phy_idx phy,
2918 enum rtw89_rf_path path)
2919 {
2920 rtw89_rfk_parser(rtwdev, &rtw8851b_tssi_mv_avg_defs_a_tbl);
2921 }
2922
_tssi_enable(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy)2923 static void _tssi_enable(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy)
2924 {
2925 _tssi_set_tssi_track(rtwdev, phy, RF_PATH_A);
2926 _tssi_set_txagc_offset_mv_avg(rtwdev, phy, RF_PATH_A);
2927
2928 rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_MV_AVG, B_P0_TSSI_MV_CLR, 0x0);
2929 rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_AVG, B_P0_TSSI_EN, 0x0);
2930 rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_AVG, B_P0_TSSI_EN, 0x1);
2931 rtw89_write_rf(rtwdev, RF_PATH_A, RR_TXGA_V1, RR_TXGA_V1_TRK_EN, 0x1);
2932
2933 rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_OFT_EN, 0x0);
2934 rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_RFC, 0x3);
2935 rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_OFT, 0xc0);
2936 rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_OFT_EN, 0x0);
2937 rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_OFT_EN, 0x1);
2938
2939 rtwdev->is_tssi_mode[RF_PATH_A] = true;
2940 }
2941
_tssi_disable(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy)2942 static void _tssi_disable(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy)
2943 {
2944 rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_AVG, B_P0_TSSI_EN, 0x0);
2945 rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_OFT_EN, 0x0);
2946 rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_OFT_EN, 0x1);
2947 rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_OFT_EN, 0x0);
2948 rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_MV_AVG, B_P0_TSSI_MV_CLR, 0x1);
2949
2950 rtwdev->is_tssi_mode[RF_PATH_A] = false;
2951 }
2952
_tssi_get_cck_group(struct rtw89_dev * rtwdev,u8 ch)2953 static u32 _tssi_get_cck_group(struct rtw89_dev *rtwdev, u8 ch)
2954 {
2955 switch (ch) {
2956 case 1 ... 2:
2957 return 0;
2958 case 3 ... 5:
2959 return 1;
2960 case 6 ... 8:
2961 return 2;
2962 case 9 ... 11:
2963 return 3;
2964 case 12 ... 13:
2965 return 4;
2966 case 14:
2967 return 5;
2968 }
2969
2970 return 0;
2971 }
2972
2973 #define TSSI_EXTRA_GROUP_BIT (BIT(31))
2974 #define TSSI_EXTRA_GROUP(idx) (TSSI_EXTRA_GROUP_BIT | (idx))
2975 #define IS_TSSI_EXTRA_GROUP(group) ((group) & TSSI_EXTRA_GROUP_BIT)
2976 #define TSSI_EXTRA_GET_GROUP_IDX1(group) ((group) & ~TSSI_EXTRA_GROUP_BIT)
2977 #define TSSI_EXTRA_GET_GROUP_IDX2(group) (TSSI_EXTRA_GET_GROUP_IDX1(group) + 1)
2978
_tssi_get_ofdm_group(struct rtw89_dev * rtwdev,u8 ch)2979 static u32 _tssi_get_ofdm_group(struct rtw89_dev *rtwdev, u8 ch)
2980 {
2981 switch (ch) {
2982 case 1 ... 2:
2983 return 0;
2984 case 3 ... 5:
2985 return 1;
2986 case 6 ... 8:
2987 return 2;
2988 case 9 ... 11:
2989 return 3;
2990 case 12 ... 14:
2991 return 4;
2992 case 36 ... 40:
2993 return 5;
2994 case 41 ... 43:
2995 return TSSI_EXTRA_GROUP(5);
2996 case 44 ... 48:
2997 return 6;
2998 case 49 ... 51:
2999 return TSSI_EXTRA_GROUP(6);
3000 case 52 ... 56:
3001 return 7;
3002 case 57 ... 59:
3003 return TSSI_EXTRA_GROUP(7);
3004 case 60 ... 64:
3005 return 8;
3006 case 100 ... 104:
3007 return 9;
3008 case 105 ... 107:
3009 return TSSI_EXTRA_GROUP(9);
3010 case 108 ... 112:
3011 return 10;
3012 case 113 ... 115:
3013 return TSSI_EXTRA_GROUP(10);
3014 case 116 ... 120:
3015 return 11;
3016 case 121 ... 123:
3017 return TSSI_EXTRA_GROUP(11);
3018 case 124 ... 128:
3019 return 12;
3020 case 129 ... 131:
3021 return TSSI_EXTRA_GROUP(12);
3022 case 132 ... 136:
3023 return 13;
3024 case 137 ... 139:
3025 return TSSI_EXTRA_GROUP(13);
3026 case 140 ... 144:
3027 return 14;
3028 case 149 ... 153:
3029 return 15;
3030 case 154 ... 156:
3031 return TSSI_EXTRA_GROUP(15);
3032 case 157 ... 161:
3033 return 16;
3034 case 162 ... 164:
3035 return TSSI_EXTRA_GROUP(16);
3036 case 165 ... 169:
3037 return 17;
3038 case 170 ... 172:
3039 return TSSI_EXTRA_GROUP(17);
3040 case 173 ... 177:
3041 return 18;
3042 }
3043
3044 return 0;
3045 }
3046
_tssi_get_trim_group(struct rtw89_dev * rtwdev,u8 ch)3047 static u32 _tssi_get_trim_group(struct rtw89_dev *rtwdev, u8 ch)
3048 {
3049 switch (ch) {
3050 case 1 ... 8:
3051 return 0;
3052 case 9 ... 14:
3053 return 1;
3054 case 36 ... 48:
3055 return 2;
3056 case 52 ... 64:
3057 return 3;
3058 case 100 ... 112:
3059 return 4;
3060 case 116 ... 128:
3061 return 5;
3062 case 132 ... 144:
3063 return 6;
3064 case 149 ... 177:
3065 return 7;
3066 }
3067
3068 return 0;
3069 }
3070
_tssi_get_ofdm_de(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy,enum rtw89_rf_path path,const struct rtw89_chan * chan)3071 static s8 _tssi_get_ofdm_de(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
3072 enum rtw89_rf_path path, const struct rtw89_chan *chan)
3073 {
3074 struct rtw89_tssi_info *tssi_info = &rtwdev->tssi;
3075 u32 gidx, gidx_1st, gidx_2nd;
3076 u8 ch = chan->channel;
3077 s8 de_1st;
3078 s8 de_2nd;
3079 s8 val;
3080
3081 gidx = _tssi_get_ofdm_group(rtwdev, ch);
3082
3083 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
3084 "[TSSI][TRIM]: path=%d mcs group_idx=0x%x\n", path, gidx);
3085
3086 if (IS_TSSI_EXTRA_GROUP(gidx)) {
3087 gidx_1st = TSSI_EXTRA_GET_GROUP_IDX1(gidx);
3088 gidx_2nd = TSSI_EXTRA_GET_GROUP_IDX2(gidx);
3089 de_1st = tssi_info->tssi_mcs[path][gidx_1st];
3090 de_2nd = tssi_info->tssi_mcs[path][gidx_2nd];
3091 val = (de_1st + de_2nd) / 2;
3092
3093 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
3094 "[TSSI][TRIM]: path=%d mcs de=%d 1st=%d 2nd=%d\n",
3095 path, val, de_1st, de_2nd);
3096 } else {
3097 val = tssi_info->tssi_mcs[path][gidx];
3098
3099 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
3100 "[TSSI][TRIM]: path=%d mcs de=%d\n", path, val);
3101 }
3102
3103 return val;
3104 }
3105
_tssi_get_ofdm_trim_de(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy,enum rtw89_rf_path path,const struct rtw89_chan * chan)3106 static s8 _tssi_get_ofdm_trim_de(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
3107 enum rtw89_rf_path path, const struct rtw89_chan *chan)
3108 {
3109 struct rtw89_tssi_info *tssi_info = &rtwdev->tssi;
3110 u32 tgidx, tgidx_1st, tgidx_2nd;
3111 u8 ch = chan->channel;
3112 s8 tde_1st;
3113 s8 tde_2nd;
3114 s8 val;
3115
3116 tgidx = _tssi_get_trim_group(rtwdev, ch);
3117
3118 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
3119 "[TSSI][TRIM]: path=%d mcs trim_group_idx=0x%x\n",
3120 path, tgidx);
3121
3122 if (IS_TSSI_EXTRA_GROUP(tgidx)) {
3123 tgidx_1st = TSSI_EXTRA_GET_GROUP_IDX1(tgidx);
3124 tgidx_2nd = TSSI_EXTRA_GET_GROUP_IDX2(tgidx);
3125 tde_1st = tssi_info->tssi_trim[path][tgidx_1st];
3126 tde_2nd = tssi_info->tssi_trim[path][tgidx_2nd];
3127 val = (tde_1st + tde_2nd) / 2;
3128
3129 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
3130 "[TSSI][TRIM]: path=%d mcs trim_de=%d 1st=%d 2nd=%d\n",
3131 path, val, tde_1st, tde_2nd);
3132 } else {
3133 val = tssi_info->tssi_trim[path][tgidx];
3134
3135 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
3136 "[TSSI][TRIM]: path=%d mcs trim_de=%d\n",
3137 path, val);
3138 }
3139
3140 return val;
3141 }
3142
_tssi_set_efuse_to_de(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy,const struct rtw89_chan * chan)3143 static void _tssi_set_efuse_to_de(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
3144 const struct rtw89_chan *chan)
3145 {
3146 struct rtw89_tssi_info *tssi_info = &rtwdev->tssi;
3147 u8 ch = chan->channel;
3148 u8 gidx;
3149 s8 ofdm_de;
3150 s8 trim_de;
3151 s32 val;
3152 u32 i;
3153
3154 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "[TSSI][TRIM]: phy=%d ch=%d\n",
3155 phy, ch);
3156
3157 for (i = RF_PATH_A; i < RTW8851B_TSSI_PATH_NR; i++) {
3158 gidx = _tssi_get_cck_group(rtwdev, ch);
3159 trim_de = _tssi_get_ofdm_trim_de(rtwdev, phy, i, chan);
3160 val = tssi_info->tssi_cck[i][gidx] + trim_de;
3161
3162 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
3163 "[TSSI][TRIM]: path=%d cck[%d]=0x%x trim=0x%x\n",
3164 i, gidx, tssi_info->tssi_cck[i][gidx], trim_de);
3165
3166 rtw89_phy_write32_mask(rtwdev, _tssi_de_cck_long[i], _TSSI_DE_MASK, val);
3167 rtw89_phy_write32_mask(rtwdev, _tssi_de_cck_short[i], _TSSI_DE_MASK, val);
3168
3169 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
3170 "[TSSI] Set TSSI CCK DE 0x%x[21:12]=0x%x\n",
3171 _tssi_de_cck_long[i],
3172 rtw89_phy_read32_mask(rtwdev, _tssi_de_cck_long[i],
3173 _TSSI_DE_MASK));
3174
3175 ofdm_de = _tssi_get_ofdm_de(rtwdev, phy, i, chan);
3176 trim_de = _tssi_get_ofdm_trim_de(rtwdev, phy, i, chan);
3177 val = ofdm_de + trim_de;
3178
3179 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
3180 "[TSSI][TRIM]: path=%d mcs=0x%x trim=0x%x\n",
3181 i, ofdm_de, trim_de);
3182
3183 rtw89_phy_write32_mask(rtwdev, _tssi_de_mcs_20m[i], _TSSI_DE_MASK, val);
3184 rtw89_phy_write32_mask(rtwdev, _tssi_de_mcs_40m[i], _TSSI_DE_MASK, val);
3185 rtw89_phy_write32_mask(rtwdev, _tssi_de_mcs_80m[i], _TSSI_DE_MASK, val);
3186 rtw89_phy_write32_mask(rtwdev, _tssi_de_mcs_80m_80m[i], _TSSI_DE_MASK, val);
3187 rtw89_phy_write32_mask(rtwdev, _tssi_de_mcs_5m[i], _TSSI_DE_MASK, val);
3188 rtw89_phy_write32_mask(rtwdev, _tssi_de_mcs_10m[i], _TSSI_DE_MASK, val);
3189
3190 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
3191 "[TSSI] Set TSSI MCS DE 0x%x[21:12]=0x%x\n",
3192 _tssi_de_mcs_20m[i],
3193 rtw89_phy_read32_mask(rtwdev, _tssi_de_mcs_20m[i],
3194 _TSSI_DE_MASK));
3195 }
3196 }
3197
_tssi_alimentk_dump_result(struct rtw89_dev * rtwdev,enum rtw89_rf_path path)3198 static void _tssi_alimentk_dump_result(struct rtw89_dev *rtwdev, enum rtw89_rf_path path)
3199 {
3200 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3201 "[TSSI PA K]\n0x%x = 0x%08x\n0x%x = 0x%08x\n0x%x = 0x%08x\n0x%x = 0x%08x\n"
3202 "0x%x = 0x%08x\n0x%x = 0x%08x\n0x%x = 0x%08x\n0x%x = 0x%08x\n",
3203 R_TSSI_PA_K1 + (path << 13),
3204 rtw89_phy_read32_mask(rtwdev, R_TSSI_PA_K1 + (path << 13), MASKDWORD),
3205 R_TSSI_PA_K2 + (path << 13),
3206 rtw89_phy_read32_mask(rtwdev, R_TSSI_PA_K2 + (path << 13), MASKDWORD),
3207 R_P0_TSSI_ALIM1 + (path << 13),
3208 rtw89_phy_read32_mask(rtwdev, R_P0_TSSI_ALIM1 + (path << 13), MASKDWORD),
3209 R_P0_TSSI_ALIM3 + (path << 13),
3210 rtw89_phy_read32_mask(rtwdev, R_P0_TSSI_ALIM3 + (path << 13), MASKDWORD),
3211 R_TSSI_PA_K5 + (path << 13),
3212 rtw89_phy_read32_mask(rtwdev, R_TSSI_PA_K5 + (path << 13), MASKDWORD),
3213 R_P0_TSSI_ALIM2 + (path << 13),
3214 rtw89_phy_read32_mask(rtwdev, R_P0_TSSI_ALIM2 + (path << 13), MASKDWORD),
3215 R_P0_TSSI_ALIM4 + (path << 13),
3216 rtw89_phy_read32_mask(rtwdev, R_P0_TSSI_ALIM4 + (path << 13), MASKDWORD),
3217 R_TSSI_PA_K8 + (path << 13),
3218 rtw89_phy_read32_mask(rtwdev, R_TSSI_PA_K8 + (path << 13), MASKDWORD));
3219 }
3220
_tssi_alimentk_done(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy,enum rtw89_rf_path path,const struct rtw89_chan * chan)3221 static void _tssi_alimentk_done(struct rtw89_dev *rtwdev,
3222 enum rtw89_phy_idx phy, enum rtw89_rf_path path,
3223 const struct rtw89_chan *chan)
3224 {
3225 struct rtw89_tssi_info *tssi_info = &rtwdev->tssi;
3226 u8 channel = chan->channel;
3227 u8 band;
3228
3229 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3230 "======>%s phy=%d path=%d\n", __func__, phy, path);
3231
3232 if (channel >= 1 && channel <= 14)
3233 band = TSSI_ALIMK_2G;
3234 else if (channel >= 36 && channel <= 64)
3235 band = TSSI_ALIMK_5GL;
3236 else if (channel >= 100 && channel <= 144)
3237 band = TSSI_ALIMK_5GM;
3238 else if (channel >= 149 && channel <= 177)
3239 band = TSSI_ALIMK_5GH;
3240 else
3241 band = TSSI_ALIMK_2G;
3242
3243 if (tssi_info->alignment_done[path][band]) {
3244 rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_ALIM1 + (path << 13), MASKDWORD,
3245 tssi_info->alignment_value[path][band][0]);
3246 rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_ALIM3 + (path << 13), MASKDWORD,
3247 tssi_info->alignment_value[path][band][1]);
3248 rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_ALIM2 + (path << 13), MASKDWORD,
3249 tssi_info->alignment_value[path][band][2]);
3250 rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_ALIM4 + (path << 13), MASKDWORD,
3251 tssi_info->alignment_value[path][band][3]);
3252 }
3253
3254 _tssi_alimentk_dump_result(rtwdev, path);
3255 }
3256
rtw8851b_by_rate_dpd(struct rtw89_dev * rtwdev)3257 static void rtw8851b_by_rate_dpd(struct rtw89_dev *rtwdev)
3258 {
3259 rtw89_write32_mask(rtwdev, R_AX_PWR_SWING_OTHER_CTRL0,
3260 B_AX_CFIR_BY_RATE_OFF_MASK, 0x21861);
3261 }
3262
rtw8851b_dpk_init(struct rtw89_dev * rtwdev)3263 void rtw8851b_dpk_init(struct rtw89_dev *rtwdev)
3264 {
3265 rtw8851b_by_rate_dpd(rtwdev);
3266 }
3267
rtw8851b_aack(struct rtw89_dev * rtwdev)3268 void rtw8851b_aack(struct rtw89_dev *rtwdev)
3269 {
3270 u32 tmp05, tmpd3, ib[4];
3271 u32 tmp;
3272 int ret;
3273 int rek;
3274 int i;
3275
3276 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[LCK]DO AACK\n");
3277
3278 tmp05 = rtw89_read_rf(rtwdev, RF_PATH_A, RR_RSV1, RFREG_MASK);
3279 tmpd3 = rtw89_read_rf(rtwdev, RF_PATH_A, RR_LCK_TRG, RFREG_MASK);
3280 rtw89_write_rf(rtwdev, RF_PATH_A, RR_MOD, RR_MOD_MASK, 0x3);
3281 rtw89_write_rf(rtwdev, RF_PATH_A, RR_RSV1, RFREG_MASK, 0x0);
3282 rtw89_write_rf(rtwdev, RF_PATH_A, RR_LCK_TRG, RR_LCK_ST, 0x0);
3283
3284 for (rek = 0; rek < 4; rek++) {
3285 rtw89_write_rf(rtwdev, RF_PATH_A, RR_AACK, RFREG_MASK, 0x8201e);
3286 rtw89_write_rf(rtwdev, RF_PATH_A, RR_AACK, RFREG_MASK, 0x8201f);
3287 fsleep(100);
3288
3289 ret = read_poll_timeout_atomic(rtw89_read_rf, tmp, tmp,
3290 1, 1000, false,
3291 rtwdev, RF_PATH_A, 0xd0, BIT(16));
3292 if (ret)
3293 rtw89_warn(rtwdev, "[LCK]AACK timeout\n");
3294
3295 rtw89_write_rf(rtwdev, RF_PATH_A, RR_VCI, RR_VCI_ON, 0x1);
3296 for (i = 0; i < 4; i++) {
3297 rtw89_write_rf(rtwdev, RF_PATH_A, RR_VCO, RR_VCO_SEL, i);
3298 ib[i] = rtw89_read_rf(rtwdev, RF_PATH_A, RR_IBD, RR_IBD_VAL);
3299 }
3300 rtw89_write_rf(rtwdev, RF_PATH_A, RR_VCI, RR_VCI_ON, 0x0);
3301
3302 if (ib[0] != 0 && ib[1] != 0 && ib[2] != 0 && ib[3] != 0)
3303 break;
3304 }
3305
3306 if (rek != 0)
3307 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[LCK]AACK rek = %d\n", rek);
3308
3309 rtw89_write_rf(rtwdev, RF_PATH_A, RR_RSV1, RFREG_MASK, tmp05);
3310 rtw89_write_rf(rtwdev, RF_PATH_A, RR_LCK_TRG, RFREG_MASK, tmpd3);
3311 }
3312
_lck_keep_thermal(struct rtw89_dev * rtwdev)3313 static void _lck_keep_thermal(struct rtw89_dev *rtwdev)
3314 {
3315 struct rtw89_lck_info *lck = &rtwdev->lck;
3316
3317 lck->thermal[RF_PATH_A] =
3318 ewma_thermal_read(&rtwdev->phystat.avg_thermal[RF_PATH_A]);
3319 rtw89_debug(rtwdev, RTW89_DBG_RFK_TRACK,
3320 "[LCK] path=%d thermal=0x%x", RF_PATH_A, lck->thermal[RF_PATH_A]);
3321 }
3322
rtw8851b_lck(struct rtw89_dev * rtwdev)3323 static void rtw8851b_lck(struct rtw89_dev *rtwdev)
3324 {
3325 u32 tmp05, tmp18, tmpd3;
3326
3327 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[LCK]DO LCK\n");
3328
3329 tmp05 = rtw89_read_rf(rtwdev, RF_PATH_A, RR_RSV1, RFREG_MASK);
3330 tmp18 = rtw89_read_rf(rtwdev, RF_PATH_A, RR_CFGCH, RFREG_MASK);
3331 tmpd3 = rtw89_read_rf(rtwdev, RF_PATH_A, RR_LCK_TRG, RFREG_MASK);
3332
3333 rtw89_write_rf(rtwdev, RF_PATH_A, RR_MOD, RR_MOD_MASK, 0x3);
3334 rtw89_write_rf(rtwdev, RF_PATH_A, RR_RSV1, RFREG_MASK, 0x0);
3335 rtw89_write_rf(rtwdev, RF_PATH_A, RR_LCK_TRG, RR_LCK_TRGSEL, 0x1);
3336
3337 _set_ch(rtwdev, tmp18);
3338 rtw89_write_rf(rtwdev, RF_PATH_A, RR_LCK_TRG, RFREG_MASK, tmpd3);
3339 rtw89_write_rf(rtwdev, RF_PATH_A, RR_RSV1, RFREG_MASK, tmp05);
3340
3341 _lck_keep_thermal(rtwdev);
3342 }
3343
3344 #define RTW8851B_LCK_TH 8
3345
rtw8851b_lck_track(struct rtw89_dev * rtwdev)3346 void rtw8851b_lck_track(struct rtw89_dev *rtwdev)
3347 {
3348 struct rtw89_lck_info *lck = &rtwdev->lck;
3349 u8 cur_thermal;
3350 int delta;
3351
3352 cur_thermal =
3353 ewma_thermal_read(&rtwdev->phystat.avg_thermal[RF_PATH_A]);
3354 delta = abs((int)cur_thermal - lck->thermal[RF_PATH_A]);
3355
3356 rtw89_debug(rtwdev, RTW89_DBG_RFK_TRACK,
3357 "[LCK] path=%d current thermal=0x%x delta=0x%x\n",
3358 RF_PATH_A, cur_thermal, delta);
3359
3360 if (delta >= RTW8851B_LCK_TH) {
3361 rtw8851b_aack(rtwdev);
3362 rtw8851b_lck(rtwdev);
3363 }
3364 }
3365
rtw8851b_lck_init(struct rtw89_dev * rtwdev)3366 void rtw8851b_lck_init(struct rtw89_dev *rtwdev)
3367 {
3368 _lck_keep_thermal(rtwdev);
3369 }
3370
rtw8851b_rck(struct rtw89_dev * rtwdev)3371 void rtw8851b_rck(struct rtw89_dev *rtwdev)
3372 {
3373 _rck(rtwdev, RF_PATH_A);
3374 }
3375
rtw8851b_dack(struct rtw89_dev * rtwdev)3376 void rtw8851b_dack(struct rtw89_dev *rtwdev)
3377 {
3378 _dac_cal(rtwdev, false);
3379 }
3380
rtw8851b_iqk(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx,enum rtw89_chanctx_idx chanctx_idx)3381 void rtw8851b_iqk(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx,
3382 enum rtw89_chanctx_idx chanctx_idx)
3383 {
3384 u8 phy_map = rtw89_btc_phymap(rtwdev, phy_idx, 0, chanctx_idx);
3385 u32 tx_en;
3386
3387 rtw89_btc_ntfy_wl_rfk(rtwdev, phy_map, BTC_WRFKT_IQK, BTC_WRFK_START);
3388 rtw89_chip_stop_sch_tx(rtwdev, phy_idx, &tx_en, RTW89_SCH_TX_SEL_ALL);
3389 _wait_rx_mode(rtwdev, _kpath(rtwdev, phy_idx));
3390
3391 _iqk_init(rtwdev);
3392 _iqk(rtwdev, phy_idx, false, chanctx_idx);
3393
3394 rtw89_chip_resume_sch_tx(rtwdev, phy_idx, tx_en);
3395 rtw89_btc_ntfy_wl_rfk(rtwdev, phy_map, BTC_WRFKT_IQK, BTC_WRFK_STOP);
3396 }
3397
rtw8851b_rx_dck(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx,enum rtw89_chanctx_idx chanctx_idx)3398 void rtw8851b_rx_dck(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx,
3399 enum rtw89_chanctx_idx chanctx_idx)
3400 {
3401 u8 phy_map = rtw89_btc_phymap(rtwdev, phy_idx, 0, chanctx_idx);
3402 u32 tx_en;
3403
3404 rtw89_btc_ntfy_wl_rfk(rtwdev, phy_map, BTC_WRFKT_RXDCK, BTC_WRFK_START);
3405 rtw89_chip_stop_sch_tx(rtwdev, phy_idx, &tx_en, RTW89_SCH_TX_SEL_ALL);
3406 _wait_rx_mode(rtwdev, _kpath(rtwdev, phy_idx));
3407
3408 _rx_dck(rtwdev, phy_idx, false, chanctx_idx);
3409
3410 rtw89_chip_resume_sch_tx(rtwdev, phy_idx, tx_en);
3411 rtw89_btc_ntfy_wl_rfk(rtwdev, phy_map, BTC_WRFKT_RXDCK, BTC_WRFK_STOP);
3412 }
3413
rtw8851b_dpk(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx,enum rtw89_chanctx_idx chanctx_idx)3414 void rtw8851b_dpk(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx,
3415 enum rtw89_chanctx_idx chanctx_idx)
3416 {
3417 u8 phy_map = rtw89_btc_phymap(rtwdev, phy_idx, 0, chanctx_idx);
3418 u32 tx_en;
3419
3420 rtw89_btc_ntfy_wl_rfk(rtwdev, phy_map, BTC_WRFKT_DPK, BTC_WRFK_START);
3421 rtw89_chip_stop_sch_tx(rtwdev, phy_idx, &tx_en, RTW89_SCH_TX_SEL_ALL);
3422 _wait_rx_mode(rtwdev, _kpath(rtwdev, phy_idx));
3423
3424 rtwdev->dpk.is_dpk_enable = true;
3425 rtwdev->dpk.is_dpk_reload_en = false;
3426 _dpk(rtwdev, phy_idx, false, chanctx_idx);
3427
3428 rtw89_chip_resume_sch_tx(rtwdev, phy_idx, tx_en);
3429 rtw89_btc_ntfy_wl_rfk(rtwdev, phy_map, BTC_WRFKT_DPK, BTC_WRFK_STOP);
3430 }
3431
rtw8851b_dpk_track(struct rtw89_dev * rtwdev)3432 void rtw8851b_dpk_track(struct rtw89_dev *rtwdev)
3433 {
3434 _dpk_track(rtwdev);
3435 }
3436
rtw8851b_tssi(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy,bool hwtx_en,enum rtw89_chanctx_idx chanctx_idx)3437 void rtw8851b_tssi(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
3438 bool hwtx_en, enum rtw89_chanctx_idx chanctx_idx)
3439 {
3440 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, chanctx_idx);
3441 u8 phy_map = rtw89_btc_phymap(rtwdev, phy, RF_A, chanctx_idx);
3442 u8 i;
3443
3444 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "[TSSI] %s: phy=%d\n", __func__, phy);
3445 rtw89_btc_ntfy_wl_rfk(rtwdev, phy_map, BTC_WRFKT_IQK, BTC_WRFK_ONESHOT_START);
3446
3447 _tssi_disable(rtwdev, phy);
3448
3449 for (i = RF_PATH_A; i < RF_PATH_NUM_8851B; i++) {
3450 _tssi_set_sys(rtwdev, phy, i, chan);
3451 _tssi_ini_txpwr_ctrl_bb(rtwdev, phy, i);
3452 _tssi_ini_txpwr_ctrl_bb_he_tb(rtwdev, phy, i);
3453 _tssi_set_dck(rtwdev, phy, i);
3454 _tssi_set_tmeter_tbl(rtwdev, phy, i, chan);
3455 _tssi_set_dac_gain_tbl(rtwdev, phy, i);
3456 _tssi_slope_cal_org(rtwdev, phy, i, chan);
3457 _tssi_alignment_default(rtwdev, phy, i, true, chan);
3458 _tssi_set_tssi_slope(rtwdev, phy, i);
3459 }
3460
3461 _tssi_enable(rtwdev, phy);
3462 _tssi_set_efuse_to_de(rtwdev, phy, chan);
3463
3464 rtw89_btc_ntfy_wl_rfk(rtwdev, phy_map, BTC_WRFKT_IQK, BTC_WRFK_ONESHOT_STOP);
3465 }
3466
rtw8851b_tssi_scan(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy,const struct rtw89_chan * chan)3467 void rtw8851b_tssi_scan(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
3468 const struct rtw89_chan *chan)
3469 {
3470 u8 channel = chan->channel;
3471 u32 i;
3472
3473 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3474 "======>%s phy=%d channel=%d\n", __func__, phy, channel);
3475
3476 _tssi_disable(rtwdev, phy);
3477
3478 for (i = RF_PATH_A; i < RF_PATH_NUM_8851B; i++) {
3479 _tssi_set_sys(rtwdev, phy, i, chan);
3480 _tssi_set_tmeter_tbl(rtwdev, phy, i, chan);
3481 _tssi_slope_cal_org(rtwdev, phy, i, chan);
3482 _tssi_alignment_default(rtwdev, phy, i, true, chan);
3483 }
3484
3485 _tssi_enable(rtwdev, phy);
3486 _tssi_set_efuse_to_de(rtwdev, phy, chan);
3487 }
3488
rtw8851b_tssi_default_txagc(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy,bool enable,enum rtw89_chanctx_idx chanctx_idx)3489 static void rtw8851b_tssi_default_txagc(struct rtw89_dev *rtwdev,
3490 enum rtw89_phy_idx phy, bool enable,
3491 enum rtw89_chanctx_idx chanctx_idx)
3492 {
3493 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, chanctx_idx);
3494 u8 channel = chan->channel;
3495
3496 rtw89_debug(rtwdev, RTW89_DBG_RFK, "======> %s ch=%d\n",
3497 __func__, channel);
3498
3499 if (enable)
3500 return;
3501
3502 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3503 "======>%s 1 SCAN_END Set 0x5818[7:0]=0x%x\n",
3504 __func__,
3505 rtw89_phy_read32_mask(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_OFT));
3506
3507 rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_OFT, 0xc0);
3508 rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_OFT_EN, 0x0);
3509 rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_OFT_EN, 0x1);
3510
3511 _tssi_alimentk_done(rtwdev, phy, RF_PATH_A, chan);
3512
3513 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3514 "======>%s 2 SCAN_END Set 0x5818[7:0]=0x%x\n",
3515 __func__,
3516 rtw89_phy_read32_mask(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_OFT));
3517
3518 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3519 "======> %s SCAN_END\n", __func__);
3520 }
3521
rtw8851b_wifi_scan_notify(struct rtw89_dev * rtwdev,bool scan_start,enum rtw89_phy_idx phy_idx,enum rtw89_chanctx_idx chanctx_idx)3522 void rtw8851b_wifi_scan_notify(struct rtw89_dev *rtwdev, bool scan_start,
3523 enum rtw89_phy_idx phy_idx,
3524 enum rtw89_chanctx_idx chanctx_idx)
3525 {
3526 if (scan_start)
3527 rtw8851b_tssi_default_txagc(rtwdev, phy_idx, true, chanctx_idx);
3528 else
3529 rtw8851b_tssi_default_txagc(rtwdev, phy_idx, false, chanctx_idx);
3530 }
3531
_bw_setting(struct rtw89_dev * rtwdev,enum rtw89_rf_path path,enum rtw89_bandwidth bw,bool dav)3532 static void _bw_setting(struct rtw89_dev *rtwdev, enum rtw89_rf_path path,
3533 enum rtw89_bandwidth bw, bool dav)
3534 {
3535 u32 reg18_addr = dav ? RR_CFGCH : RR_CFGCH_V1;
3536 u32 rf_reg18;
3537
3538 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[RFK]===> %s\n", __func__);
3539
3540 rf_reg18 = rtw89_read_rf(rtwdev, path, reg18_addr, RFREG_MASK);
3541 if (rf_reg18 == INV_RF_DATA) {
3542 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3543 "[RFK]Invalid RF_0x18 for Path-%d\n", path);
3544 return;
3545 }
3546 rf_reg18 &= ~RR_CFGCH_BW;
3547
3548 switch (bw) {
3549 case RTW89_CHANNEL_WIDTH_5:
3550 case RTW89_CHANNEL_WIDTH_10:
3551 case RTW89_CHANNEL_WIDTH_20:
3552 rf_reg18 |= FIELD_PREP(RR_CFGCH_BW, CFGCH_BW_20M);
3553 break;
3554 case RTW89_CHANNEL_WIDTH_40:
3555 rf_reg18 |= FIELD_PREP(RR_CFGCH_BW, CFGCH_BW_40M);
3556 break;
3557 case RTW89_CHANNEL_WIDTH_80:
3558 rf_reg18 |= FIELD_PREP(RR_CFGCH_BW, CFGCH_BW_80M);
3559 break;
3560 default:
3561 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[RFK]Fail to set CH\n");
3562 }
3563
3564 rf_reg18 &= ~(RR_CFGCH_POW_LCK | RR_CFGCH_TRX_AH | RR_CFGCH_BCN |
3565 RR_CFGCH_BW2) & RFREG_MASK;
3566 rf_reg18 |= RR_CFGCH_BW2;
3567 rtw89_write_rf(rtwdev, path, reg18_addr, RFREG_MASK, rf_reg18);
3568
3569 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[RFK] set %x at path%d, %x =0x%x\n",
3570 bw, path, reg18_addr,
3571 rtw89_read_rf(rtwdev, path, reg18_addr, RFREG_MASK));
3572 }
3573
_ctrl_bw(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy,enum rtw89_bandwidth bw)3574 static void _ctrl_bw(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
3575 enum rtw89_bandwidth bw)
3576 {
3577 _bw_setting(rtwdev, RF_PATH_A, bw, true);
3578 _bw_setting(rtwdev, RF_PATH_A, bw, false);
3579 }
3580
_set_s0_arfc18(struct rtw89_dev * rtwdev,u32 val)3581 static bool _set_s0_arfc18(struct rtw89_dev *rtwdev, u32 val)
3582 {
3583 u32 bak;
3584 u32 tmp;
3585 int ret;
3586
3587 bak = rtw89_read_rf(rtwdev, RF_PATH_A, RR_LDO, RFREG_MASK);
3588 rtw89_write_rf(rtwdev, RF_PATH_A, RR_LDO, RR_LDO_SEL, 0x1);
3589 rtw89_write_rf(rtwdev, RF_PATH_A, RR_CFGCH, RFREG_MASK, val);
3590
3591 ret = read_poll_timeout_atomic(rtw89_read_rf, tmp, tmp == 0, 1, 1000,
3592 false, rtwdev, RF_PATH_A, RR_LPF, RR_LPF_BUSY);
3593 if (ret)
3594 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[LCK]LCK timeout\n");
3595
3596 rtw89_write_rf(rtwdev, RF_PATH_A, RR_LDO, RFREG_MASK, bak);
3597
3598 return !!ret;
3599 }
3600
_lck_check(struct rtw89_dev * rtwdev)3601 static void _lck_check(struct rtw89_dev *rtwdev)
3602 {
3603 u32 tmp;
3604
3605 if (rtw89_read_rf(rtwdev, RF_PATH_A, RR_SYNFB, RR_SYNFB_LK) == 0) {
3606 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[LCK]SYN MMD reset\n");
3607
3608 rtw89_write_rf(rtwdev, RF_PATH_A, RR_MMD, RR_MMD_RST_EN, 0x1);
3609 rtw89_write_rf(rtwdev, RF_PATH_A, RR_MMD, RR_MMD_RST_SYN, 0x0);
3610 rtw89_write_rf(rtwdev, RF_PATH_A, RR_MMD, RR_MMD_RST_SYN, 0x1);
3611 rtw89_write_rf(rtwdev, RF_PATH_A, RR_MMD, RR_MMD_RST_EN, 0x0);
3612 }
3613
3614 udelay(10);
3615
3616 if (rtw89_read_rf(rtwdev, RF_PATH_A, RR_SYNFB, RR_SYNFB_LK) == 0) {
3617 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[LCK]re-set RF 0x18\n");
3618
3619 rtw89_write_rf(rtwdev, RF_PATH_A, RR_LCK_TRG, RR_LCK_TRGSEL, 0x1);
3620 tmp = rtw89_read_rf(rtwdev, RF_PATH_A, RR_CFGCH, RFREG_MASK);
3621 _set_s0_arfc18(rtwdev, tmp);
3622 rtw89_write_rf(rtwdev, RF_PATH_A, RR_LCK_TRG, RR_LCK_TRGSEL, 0x0);
3623 }
3624
3625 if (rtw89_read_rf(rtwdev, RF_PATH_A, RR_SYNFB, RR_SYNFB_LK) == 0) {
3626 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[LCK]SYN off/on\n");
3627
3628 tmp = rtw89_read_rf(rtwdev, RF_PATH_A, RR_POW, RFREG_MASK);
3629 rtw89_write_rf(rtwdev, RF_PATH_A, RR_POW, RFREG_MASK, tmp);
3630 tmp = rtw89_read_rf(rtwdev, RF_PATH_A, RR_SX, RFREG_MASK);
3631 rtw89_write_rf(rtwdev, RF_PATH_A, RR_SX, RFREG_MASK, tmp);
3632
3633 rtw89_write_rf(rtwdev, RF_PATH_A, RR_SYNLUT, RR_SYNLUT_MOD, 0x1);
3634 rtw89_write_rf(rtwdev, RF_PATH_A, RR_POW, RR_POW_SYN, 0x0);
3635 rtw89_write_rf(rtwdev, RF_PATH_A, RR_POW, RR_POW_SYN, 0x3);
3636 rtw89_write_rf(rtwdev, RF_PATH_A, RR_SYNLUT, RR_SYNLUT_MOD, 0x0);
3637
3638 rtw89_write_rf(rtwdev, RF_PATH_A, RR_LCK_TRG, RR_LCK_TRGSEL, 0x1);
3639 tmp = rtw89_read_rf(rtwdev, RF_PATH_A, RR_CFGCH, RFREG_MASK);
3640 _set_s0_arfc18(rtwdev, tmp);
3641 rtw89_write_rf(rtwdev, RF_PATH_A, RR_LCK_TRG, RR_LCK_TRGSEL, 0x0);
3642
3643 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[LCK]0xb2=%x, 0xc5=%x\n",
3644 rtw89_read_rf(rtwdev, RF_PATH_A, RR_VCO, RFREG_MASK),
3645 rtw89_read_rf(rtwdev, RF_PATH_A, RR_SYNFB, RFREG_MASK));
3646 }
3647 }
3648
_set_ch(struct rtw89_dev * rtwdev,u32 val)3649 static void _set_ch(struct rtw89_dev *rtwdev, u32 val)
3650 {
3651 bool timeout;
3652
3653 timeout = _set_s0_arfc18(rtwdev, val);
3654 if (!timeout)
3655 _lck_check(rtwdev);
3656 }
3657
_ch_setting(struct rtw89_dev * rtwdev,enum rtw89_rf_path path,u8 central_ch,bool dav)3658 static void _ch_setting(struct rtw89_dev *rtwdev, enum rtw89_rf_path path,
3659 u8 central_ch, bool dav)
3660 {
3661 u32 reg18_addr = dav ? RR_CFGCH : RR_CFGCH_V1;
3662 bool is_2g_ch = central_ch <= 14;
3663 u32 rf_reg18;
3664
3665 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[RFK]===> %s\n", __func__);
3666
3667 rf_reg18 = rtw89_read_rf(rtwdev, path, reg18_addr, RFREG_MASK);
3668 rf_reg18 &= ~(RR_CFGCH_BAND1 | RR_CFGCH_POW_LCK | RR_CFGCH_TRX_AH |
3669 RR_CFGCH_BCN | RR_CFGCH_BAND0 | RR_CFGCH_CH);
3670 rf_reg18 |= FIELD_PREP(RR_CFGCH_CH, central_ch);
3671
3672 if (!is_2g_ch)
3673 rf_reg18 |= FIELD_PREP(RR_CFGCH_BAND1, CFGCH_BAND1_5G) |
3674 FIELD_PREP(RR_CFGCH_BAND0, CFGCH_BAND0_5G);
3675
3676 rf_reg18 &= ~(RR_CFGCH_POW_LCK | RR_CFGCH_TRX_AH | RR_CFGCH_BCN |
3677 RR_CFGCH_BW2) & RFREG_MASK;
3678 rf_reg18 |= RR_CFGCH_BW2;
3679
3680 if (path == RF_PATH_A && dav)
3681 _set_ch(rtwdev, rf_reg18);
3682 else
3683 rtw89_write_rf(rtwdev, path, reg18_addr, RFREG_MASK, rf_reg18);
3684
3685 rtw89_write_rf(rtwdev, path, RR_LCKST, RR_LCKST_BIN, 0);
3686 rtw89_write_rf(rtwdev, path, RR_LCKST, RR_LCKST_BIN, 1);
3687
3688 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3689 "[RFK]CH: %d for Path-%d, reg0x%x = 0x%x\n",
3690 central_ch, path, reg18_addr,
3691 rtw89_read_rf(rtwdev, path, reg18_addr, RFREG_MASK));
3692 }
3693
_ctrl_ch(struct rtw89_dev * rtwdev,u8 central_ch)3694 static void _ctrl_ch(struct rtw89_dev *rtwdev, u8 central_ch)
3695 {
3696 _ch_setting(rtwdev, RF_PATH_A, central_ch, true);
3697 _ch_setting(rtwdev, RF_PATH_A, central_ch, false);
3698 }
3699
_set_rxbb_bw(struct rtw89_dev * rtwdev,enum rtw89_bandwidth bw,enum rtw89_rf_path path)3700 static void _set_rxbb_bw(struct rtw89_dev *rtwdev, enum rtw89_bandwidth bw,
3701 enum rtw89_rf_path path)
3702 {
3703 rtw89_write_rf(rtwdev, path, RR_LUTWE2, RR_LUTWE2_RTXBW, 0x1);
3704 rtw89_write_rf(rtwdev, path, RR_LUTWA, RR_LUTWA_M2, 0x12);
3705
3706 if (bw == RTW89_CHANNEL_WIDTH_20)
3707 rtw89_write_rf(rtwdev, path, RR_LUTWD0, RR_LUTWD0_LB, 0x1b);
3708 else if (bw == RTW89_CHANNEL_WIDTH_40)
3709 rtw89_write_rf(rtwdev, path, RR_LUTWD0, RR_LUTWD0_LB, 0x13);
3710 else if (bw == RTW89_CHANNEL_WIDTH_80)
3711 rtw89_write_rf(rtwdev, path, RR_LUTWD0, RR_LUTWD0_LB, 0xb);
3712 else
3713 rtw89_write_rf(rtwdev, path, RR_LUTWD0, RR_LUTWD0_LB, 0x3);
3714
3715 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[RFK] set S%d RXBB BW 0x3F = 0x%x\n", path,
3716 rtw89_read_rf(rtwdev, path, RR_LUTWD0, RR_LUTWD0_LB));
3717
3718 rtw89_write_rf(rtwdev, path, RR_LUTWE2, RR_LUTWE2_RTXBW, 0x0);
3719 }
3720
_rxbb_bw(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy,enum rtw89_bandwidth bw)3721 static void _rxbb_bw(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,
3722 enum rtw89_bandwidth bw)
3723 {
3724 u8 kpath, path;
3725
3726 kpath = _kpath(rtwdev, phy);
3727
3728 for (path = 0; path < RF_PATH_NUM_8851B; path++) {
3729 if (!(kpath & BIT(path)))
3730 continue;
3731
3732 _set_rxbb_bw(rtwdev, bw, path);
3733 }
3734 }
3735
rtw8851b_ctrl_bw_ch(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy,u8 central_ch,enum rtw89_band band,enum rtw89_bandwidth bw)3736 static void rtw8851b_ctrl_bw_ch(struct rtw89_dev *rtwdev,
3737 enum rtw89_phy_idx phy, u8 central_ch,
3738 enum rtw89_band band, enum rtw89_bandwidth bw)
3739 {
3740 _ctrl_ch(rtwdev, central_ch);
3741 _ctrl_bw(rtwdev, phy, bw);
3742 _rxbb_bw(rtwdev, phy, bw);
3743 }
3744
rtw8851b_set_channel_rf(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_phy_idx phy_idx)3745 void rtw8851b_set_channel_rf(struct rtw89_dev *rtwdev,
3746 const struct rtw89_chan *chan,
3747 enum rtw89_phy_idx phy_idx)
3748 {
3749 rtw8851b_ctrl_bw_ch(rtwdev, phy_idx, chan->channel, chan->band_type,
3750 chan->band_width);
3751 }
3752