1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /* Copyright(c) 2019-2020 Realtek Corporation
3 */
4
5 #if defined(__FreeBSD__)
6 #define LINUXKPI_PARAM_PREFIX rtw89_
7 #endif
8
9 #include <linux/ip.h>
10 #include <linux/sort.h>
11 #include <linux/udp.h>
12
13 #include "cam.h"
14 #include "chan.h"
15 #include "coex.h"
16 #include "core.h"
17 #include "efuse.h"
18 #include "fw.h"
19 #include "mac.h"
20 #include "phy.h"
21 #include "ps.h"
22 #include "reg.h"
23 #include "sar.h"
24 #include "ser.h"
25 #include "txrx.h"
26 #include "util.h"
27 #include "wow.h"
28
29 static bool rtw89_disable_ps_mode;
30 module_param_named(disable_ps_mode, rtw89_disable_ps_mode, bool, 0644);
31 MODULE_PARM_DESC(disable_ps_mode, "Set Y to disable low power mode");
32
33 #if defined(__FreeBSD__)
34 static bool rtw_ht_support = false;
35 module_param_named(support_ht, rtw_ht_support, bool, 0644);
36 MODULE_PARM_DESC(support_ht, "Set to Y to enable HT support");
37
38 static bool rtw_vht_support = false;
39 module_param_named(support_vht, rtw_vht_support, bool, 0644);
40 MODULE_PARM_DESC(support_vht, "Set to Y to enable VHT support");
41
42 static bool rtw_eht_support = false;
43 module_param_named(support_eht, rtw_eht_support, bool, 0644);
44 MODULE_PARM_DESC(support_eht, "Set to Y to enable EHT support");
45 #endif
46
47
48 #define RTW89_DEF_CHAN(_freq, _hw_val, _flags, _band) \
49 { .center_freq = _freq, .hw_value = _hw_val, .flags = _flags, .band = _band, }
50 #define RTW89_DEF_CHAN_2G(_freq, _hw_val) \
51 RTW89_DEF_CHAN(_freq, _hw_val, 0, NL80211_BAND_2GHZ)
52 #define RTW89_DEF_CHAN_5G(_freq, _hw_val) \
53 RTW89_DEF_CHAN(_freq, _hw_val, 0, NL80211_BAND_5GHZ)
54 #define RTW89_DEF_CHAN_5G_NO_HT40MINUS(_freq, _hw_val) \
55 RTW89_DEF_CHAN(_freq, _hw_val, IEEE80211_CHAN_NO_HT40MINUS, NL80211_BAND_5GHZ)
56 #define RTW89_DEF_CHAN_6G(_freq, _hw_val) \
57 RTW89_DEF_CHAN(_freq, _hw_val, 0, NL80211_BAND_6GHZ)
58
59 static struct ieee80211_channel rtw89_channels_2ghz[] = {
60 RTW89_DEF_CHAN_2G(2412, 1),
61 RTW89_DEF_CHAN_2G(2417, 2),
62 RTW89_DEF_CHAN_2G(2422, 3),
63 RTW89_DEF_CHAN_2G(2427, 4),
64 RTW89_DEF_CHAN_2G(2432, 5),
65 RTW89_DEF_CHAN_2G(2437, 6),
66 RTW89_DEF_CHAN_2G(2442, 7),
67 RTW89_DEF_CHAN_2G(2447, 8),
68 RTW89_DEF_CHAN_2G(2452, 9),
69 RTW89_DEF_CHAN_2G(2457, 10),
70 RTW89_DEF_CHAN_2G(2462, 11),
71 RTW89_DEF_CHAN_2G(2467, 12),
72 RTW89_DEF_CHAN_2G(2472, 13),
73 RTW89_DEF_CHAN_2G(2484, 14),
74 };
75
76 static struct ieee80211_channel rtw89_channels_5ghz[] = {
77 RTW89_DEF_CHAN_5G(5180, 36),
78 RTW89_DEF_CHAN_5G(5200, 40),
79 RTW89_DEF_CHAN_5G(5220, 44),
80 RTW89_DEF_CHAN_5G(5240, 48),
81 RTW89_DEF_CHAN_5G(5260, 52),
82 RTW89_DEF_CHAN_5G(5280, 56),
83 RTW89_DEF_CHAN_5G(5300, 60),
84 RTW89_DEF_CHAN_5G(5320, 64),
85 RTW89_DEF_CHAN_5G(5500, 100),
86 RTW89_DEF_CHAN_5G(5520, 104),
87 RTW89_DEF_CHAN_5G(5540, 108),
88 RTW89_DEF_CHAN_5G(5560, 112),
89 RTW89_DEF_CHAN_5G(5580, 116),
90 RTW89_DEF_CHAN_5G(5600, 120),
91 RTW89_DEF_CHAN_5G(5620, 124),
92 RTW89_DEF_CHAN_5G(5640, 128),
93 RTW89_DEF_CHAN_5G(5660, 132),
94 RTW89_DEF_CHAN_5G(5680, 136),
95 RTW89_DEF_CHAN_5G(5700, 140),
96 RTW89_DEF_CHAN_5G(5720, 144),
97 RTW89_DEF_CHAN_5G(5745, 149),
98 RTW89_DEF_CHAN_5G(5765, 153),
99 RTW89_DEF_CHAN_5G(5785, 157),
100 RTW89_DEF_CHAN_5G(5805, 161),
101 RTW89_DEF_CHAN_5G_NO_HT40MINUS(5825, 165),
102 RTW89_DEF_CHAN_5G(5845, 169),
103 RTW89_DEF_CHAN_5G(5865, 173),
104 RTW89_DEF_CHAN_5G(5885, 177),
105 };
106
107 static_assert(RTW89_5GHZ_UNII4_START_INDEX + RTW89_5GHZ_UNII4_CHANNEL_NUM ==
108 ARRAY_SIZE(rtw89_channels_5ghz));
109
110 static struct ieee80211_channel rtw89_channels_6ghz[] = {
111 RTW89_DEF_CHAN_6G(5955, 1),
112 RTW89_DEF_CHAN_6G(5975, 5),
113 RTW89_DEF_CHAN_6G(5995, 9),
114 RTW89_DEF_CHAN_6G(6015, 13),
115 RTW89_DEF_CHAN_6G(6035, 17),
116 RTW89_DEF_CHAN_6G(6055, 21),
117 RTW89_DEF_CHAN_6G(6075, 25),
118 RTW89_DEF_CHAN_6G(6095, 29),
119 RTW89_DEF_CHAN_6G(6115, 33),
120 RTW89_DEF_CHAN_6G(6135, 37),
121 RTW89_DEF_CHAN_6G(6155, 41),
122 RTW89_DEF_CHAN_6G(6175, 45),
123 RTW89_DEF_CHAN_6G(6195, 49),
124 RTW89_DEF_CHAN_6G(6215, 53),
125 RTW89_DEF_CHAN_6G(6235, 57),
126 RTW89_DEF_CHAN_6G(6255, 61),
127 RTW89_DEF_CHAN_6G(6275, 65),
128 RTW89_DEF_CHAN_6G(6295, 69),
129 RTW89_DEF_CHAN_6G(6315, 73),
130 RTW89_DEF_CHAN_6G(6335, 77),
131 RTW89_DEF_CHAN_6G(6355, 81),
132 RTW89_DEF_CHAN_6G(6375, 85),
133 RTW89_DEF_CHAN_6G(6395, 89),
134 RTW89_DEF_CHAN_6G(6415, 93),
135 RTW89_DEF_CHAN_6G(6435, 97),
136 RTW89_DEF_CHAN_6G(6455, 101),
137 RTW89_DEF_CHAN_6G(6475, 105),
138 RTW89_DEF_CHAN_6G(6495, 109),
139 RTW89_DEF_CHAN_6G(6515, 113),
140 RTW89_DEF_CHAN_6G(6535, 117),
141 RTW89_DEF_CHAN_6G(6555, 121),
142 RTW89_DEF_CHAN_6G(6575, 125),
143 RTW89_DEF_CHAN_6G(6595, 129),
144 RTW89_DEF_CHAN_6G(6615, 133),
145 RTW89_DEF_CHAN_6G(6635, 137),
146 RTW89_DEF_CHAN_6G(6655, 141),
147 RTW89_DEF_CHAN_6G(6675, 145),
148 RTW89_DEF_CHAN_6G(6695, 149),
149 RTW89_DEF_CHAN_6G(6715, 153),
150 RTW89_DEF_CHAN_6G(6735, 157),
151 RTW89_DEF_CHAN_6G(6755, 161),
152 RTW89_DEF_CHAN_6G(6775, 165),
153 RTW89_DEF_CHAN_6G(6795, 169),
154 RTW89_DEF_CHAN_6G(6815, 173),
155 RTW89_DEF_CHAN_6G(6835, 177),
156 RTW89_DEF_CHAN_6G(6855, 181),
157 RTW89_DEF_CHAN_6G(6875, 185),
158 RTW89_DEF_CHAN_6G(6895, 189),
159 RTW89_DEF_CHAN_6G(6915, 193),
160 RTW89_DEF_CHAN_6G(6935, 197),
161 RTW89_DEF_CHAN_6G(6955, 201),
162 RTW89_DEF_CHAN_6G(6975, 205),
163 RTW89_DEF_CHAN_6G(6995, 209),
164 RTW89_DEF_CHAN_6G(7015, 213),
165 RTW89_DEF_CHAN_6G(7035, 217),
166 RTW89_DEF_CHAN_6G(7055, 221),
167 RTW89_DEF_CHAN_6G(7075, 225),
168 RTW89_DEF_CHAN_6G(7095, 229),
169 RTW89_DEF_CHAN_6G(7115, 233),
170 };
171
172 static struct ieee80211_rate rtw89_bitrates[] = {
173 { .bitrate = 10, .hw_value = 0x00, },
174 { .bitrate = 20, .hw_value = 0x01, },
175 { .bitrate = 55, .hw_value = 0x02, },
176 { .bitrate = 110, .hw_value = 0x03, },
177 { .bitrate = 60, .hw_value = 0x04, },
178 { .bitrate = 90, .hw_value = 0x05, },
179 { .bitrate = 120, .hw_value = 0x06, },
180 { .bitrate = 180, .hw_value = 0x07, },
181 { .bitrate = 240, .hw_value = 0x08, },
182 { .bitrate = 360, .hw_value = 0x09, },
183 { .bitrate = 480, .hw_value = 0x0a, },
184 { .bitrate = 540, .hw_value = 0x0b, },
185 };
186
187 static const struct ieee80211_iface_limit rtw89_iface_limits[] = {
188 {
189 .max = 1,
190 .types = BIT(NL80211_IFTYPE_STATION),
191 },
192 {
193 .max = 1,
194 .types = BIT(NL80211_IFTYPE_P2P_CLIENT) |
195 BIT(NL80211_IFTYPE_P2P_GO) |
196 BIT(NL80211_IFTYPE_AP),
197 },
198 };
199
200 static const struct ieee80211_iface_limit rtw89_iface_limits_mcc[] = {
201 {
202 .max = 1,
203 .types = BIT(NL80211_IFTYPE_STATION),
204 },
205 {
206 .max = 1,
207 .types = BIT(NL80211_IFTYPE_P2P_CLIENT) |
208 BIT(NL80211_IFTYPE_P2P_GO),
209 },
210 };
211
212 static const struct ieee80211_iface_combination rtw89_iface_combs[] = {
213 {
214 .limits = rtw89_iface_limits,
215 .n_limits = ARRAY_SIZE(rtw89_iface_limits),
216 .max_interfaces = RTW89_MAX_INTERFACE_NUM,
217 .num_different_channels = 1,
218 },
219 {
220 .limits = rtw89_iface_limits_mcc,
221 .n_limits = ARRAY_SIZE(rtw89_iface_limits_mcc),
222 .max_interfaces = RTW89_MAX_INTERFACE_NUM,
223 .num_different_channels = 2,
224 },
225 };
226
227 static const u8 rtw89_ext_capa_sta[] = {
228 [0] = WLAN_EXT_CAPA1_EXT_CHANNEL_SWITCHING,
229 [2] = WLAN_EXT_CAPA3_MULTI_BSSID_SUPPORT,
230 [7] = WLAN_EXT_CAPA8_OPMODE_NOTIF,
231 };
232
233 static const struct wiphy_iftype_ext_capab rtw89_iftypes_ext_capa[] = {
234 {
235 .iftype = NL80211_IFTYPE_STATION,
236 .extended_capabilities = rtw89_ext_capa_sta,
237 .extended_capabilities_mask = rtw89_ext_capa_sta,
238 .extended_capabilities_len = sizeof(rtw89_ext_capa_sta),
239 /* relevant only if EHT is supported */
240 .eml_capabilities = 0,
241 .mld_capa_and_ops = 0,
242 },
243 };
244
245 #define RTW89_6GHZ_SPAN_HEAD 6145
246 #define RTW89_6GHZ_SPAN_IDX(center_freq) \
247 ((((int)(center_freq) - RTW89_6GHZ_SPAN_HEAD) / 5) / 2)
248
249 #define RTW89_DECL_6GHZ_SPAN(center_freq, subband_l, subband_h) \
250 [RTW89_6GHZ_SPAN_IDX(center_freq)] = { \
251 .sar_subband_low = RTW89_SAR_6GHZ_ ## subband_l, \
252 .sar_subband_high = RTW89_SAR_6GHZ_ ## subband_h, \
253 .acpi_sar_subband_low = RTW89_ACPI_SAR_6GHZ_ ## subband_l, \
254 .acpi_sar_subband_high = RTW89_ACPI_SAR_6GHZ_ ## subband_h, \
255 .ant_gain_subband_low = RTW89_ANT_GAIN_6GHZ_ ## subband_l, \
256 .ant_gain_subband_high = RTW89_ANT_GAIN_6GHZ_ ## subband_h, \
257 }
258
259 /* Since 6GHz subbands are not edge aligned, some cases span two subbands.
260 * In the following, we describe each of them with rtw89_6ghz_span.
261 */
262 static const struct rtw89_6ghz_span rtw89_overlapping_6ghz[] = {
263 RTW89_DECL_6GHZ_SPAN(6145, SUBBAND_5_L, SUBBAND_5_H),
264 RTW89_DECL_6GHZ_SPAN(6165, SUBBAND_5_L, SUBBAND_5_H),
265 RTW89_DECL_6GHZ_SPAN(6185, SUBBAND_5_L, SUBBAND_5_H),
266 RTW89_DECL_6GHZ_SPAN(6505, SUBBAND_6, SUBBAND_7_L),
267 RTW89_DECL_6GHZ_SPAN(6525, SUBBAND_6, SUBBAND_7_L),
268 RTW89_DECL_6GHZ_SPAN(6545, SUBBAND_6, SUBBAND_7_L),
269 RTW89_DECL_6GHZ_SPAN(6665, SUBBAND_7_L, SUBBAND_7_H),
270 RTW89_DECL_6GHZ_SPAN(6705, SUBBAND_7_L, SUBBAND_7_H),
271 RTW89_DECL_6GHZ_SPAN(6825, SUBBAND_7_H, SUBBAND_8),
272 RTW89_DECL_6GHZ_SPAN(6865, SUBBAND_7_H, SUBBAND_8),
273 RTW89_DECL_6GHZ_SPAN(6875, SUBBAND_7_H, SUBBAND_8),
274 RTW89_DECL_6GHZ_SPAN(6885, SUBBAND_7_H, SUBBAND_8),
275 };
276
277 const struct rtw89_6ghz_span *
rtw89_get_6ghz_span(struct rtw89_dev * rtwdev,u32 center_freq)278 rtw89_get_6ghz_span(struct rtw89_dev *rtwdev, u32 center_freq)
279 {
280 int idx;
281
282 if (center_freq >= RTW89_6GHZ_SPAN_HEAD) {
283 idx = RTW89_6GHZ_SPAN_IDX(center_freq);
284 /* To decrease size of rtw89_overlapping_6ghz[],
285 * RTW89_6GHZ_SPAN_IDX() truncates the leading NULLs
286 * to make first span as index 0 of the table. So, if center
287 * frequency is less than the first one, it will get netative.
288 */
289 if (idx >= 0 && idx < ARRAY_SIZE(rtw89_overlapping_6ghz))
290 return &rtw89_overlapping_6ghz[idx];
291 }
292
293 return NULL;
294 }
295
rtw89_legacy_rate_to_bitrate(struct rtw89_dev * rtwdev,u8 legacy_rate,u16 * bitrate)296 bool rtw89_legacy_rate_to_bitrate(struct rtw89_dev *rtwdev, u8 legacy_rate, u16 *bitrate)
297 {
298 const struct ieee80211_rate *rate;
299
300 if (unlikely(legacy_rate >= ARRAY_SIZE(rtw89_bitrates))) {
301 rtw89_debug(rtwdev, RTW89_DBG_UNEXP,
302 "invalid legacy rate %d\n", legacy_rate);
303 return false;
304 }
305
306 rate = &rtw89_bitrates[legacy_rate];
307 *bitrate = rate->bitrate;
308
309 return true;
310 }
311
312 static const struct ieee80211_supported_band rtw89_sband_2ghz = {
313 .band = NL80211_BAND_2GHZ,
314 .channels = rtw89_channels_2ghz,
315 .n_channels = ARRAY_SIZE(rtw89_channels_2ghz),
316 .bitrates = rtw89_bitrates,
317 .n_bitrates = ARRAY_SIZE(rtw89_bitrates),
318 .ht_cap = {0},
319 .vht_cap = {0},
320 };
321
322 static const struct ieee80211_supported_band rtw89_sband_5ghz = {
323 .band = NL80211_BAND_5GHZ,
324 .channels = rtw89_channels_5ghz,
325 .n_channels = ARRAY_SIZE(rtw89_channels_5ghz),
326
327 /* 5G has no CCK rates, 1M/2M/5.5M/11M */
328 .bitrates = rtw89_bitrates + 4,
329 .n_bitrates = ARRAY_SIZE(rtw89_bitrates) - 4,
330 .ht_cap = {0},
331 .vht_cap = {0},
332 };
333
334 static const struct ieee80211_supported_band rtw89_sband_6ghz = {
335 .band = NL80211_BAND_6GHZ,
336 .channels = rtw89_channels_6ghz,
337 .n_channels = ARRAY_SIZE(rtw89_channels_6ghz),
338
339 /* 6G has no CCK rates, 1M/2M/5.5M/11M */
340 .bitrates = rtw89_bitrates + 4,
341 .n_bitrates = ARRAY_SIZE(rtw89_bitrates) - 4,
342 };
343
344 static const struct rtw89_hw_rate_def {
345 enum rtw89_hw_rate ht;
346 enum rtw89_hw_rate vht[RTW89_NSS_NUM];
347 } rtw89_hw_rate[RTW89_CHIP_GEN_NUM] = {
348 [RTW89_CHIP_AX] = {
349 .ht = RTW89_HW_RATE_MCS0,
350 .vht = {RTW89_HW_RATE_VHT_NSS1_MCS0,
351 RTW89_HW_RATE_VHT_NSS2_MCS0,
352 RTW89_HW_RATE_VHT_NSS3_MCS0,
353 RTW89_HW_RATE_VHT_NSS4_MCS0},
354 },
355 [RTW89_CHIP_BE] = {
356 .ht = RTW89_HW_RATE_V1_MCS0,
357 .vht = {RTW89_HW_RATE_V1_VHT_NSS1_MCS0,
358 RTW89_HW_RATE_V1_VHT_NSS2_MCS0,
359 RTW89_HW_RATE_V1_VHT_NSS3_MCS0,
360 RTW89_HW_RATE_V1_VHT_NSS4_MCS0},
361 },
362 };
363
__rtw89_traffic_stats_accu(struct rtw89_traffic_stats * stats,struct sk_buff * skb,bool tx)364 static void __rtw89_traffic_stats_accu(struct rtw89_traffic_stats *stats,
365 struct sk_buff *skb, bool tx)
366 {
367 if (tx) {
368 stats->tx_cnt++;
369 stats->tx_unicast += skb->len;
370 } else {
371 stats->rx_cnt++;
372 stats->rx_unicast += skb->len;
373 }
374 }
375
rtw89_traffic_stats_accu(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif,struct sk_buff * skb,bool accu_dev,bool tx)376 static void rtw89_traffic_stats_accu(struct rtw89_dev *rtwdev,
377 struct rtw89_vif *rtwvif,
378 struct sk_buff *skb,
379 bool accu_dev, bool tx)
380 {
381 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
382
383 if (!ieee80211_is_data(hdr->frame_control))
384 return;
385
386 if (is_broadcast_ether_addr(hdr->addr1) ||
387 is_multicast_ether_addr(hdr->addr1))
388 return;
389
390 if (accu_dev)
391 __rtw89_traffic_stats_accu(&rtwdev->stats, skb, tx);
392
393 if (rtwvif) {
394 __rtw89_traffic_stats_accu(&rtwvif->stats, skb, tx);
395 __rtw89_traffic_stats_accu(&rtwvif->stats_ps, skb, tx);
396 }
397 }
398
rtw89_get_default_chandef(struct cfg80211_chan_def * chandef)399 void rtw89_get_default_chandef(struct cfg80211_chan_def *chandef)
400 {
401 cfg80211_chandef_create(chandef, &rtw89_channels_2ghz[0],
402 NL80211_CHAN_NO_HT);
403 }
404
rtw89_get_channel_params(const struct cfg80211_chan_def * chandef,struct rtw89_chan * chan)405 void rtw89_get_channel_params(const struct cfg80211_chan_def *chandef,
406 struct rtw89_chan *chan)
407 {
408 struct ieee80211_channel *channel = chandef->chan;
409 enum nl80211_chan_width width = chandef->width;
410 u32 primary_freq, center_freq;
411 u8 center_chan;
412 u8 bandwidth = RTW89_CHANNEL_WIDTH_20;
413 u32 offset;
414 u8 band;
415
416 center_chan = channel->hw_value;
417 primary_freq = channel->center_freq;
418 center_freq = chandef->center_freq1;
419
420 switch (width) {
421 case NL80211_CHAN_WIDTH_20_NOHT:
422 case NL80211_CHAN_WIDTH_20:
423 bandwidth = RTW89_CHANNEL_WIDTH_20;
424 break;
425 case NL80211_CHAN_WIDTH_40:
426 bandwidth = RTW89_CHANNEL_WIDTH_40;
427 if (primary_freq > center_freq) {
428 center_chan -= 2;
429 } else {
430 center_chan += 2;
431 }
432 break;
433 case NL80211_CHAN_WIDTH_80:
434 case NL80211_CHAN_WIDTH_160:
435 bandwidth = nl_to_rtw89_bandwidth(width);
436 if (primary_freq > center_freq) {
437 offset = (primary_freq - center_freq - 10) / 20;
438 center_chan -= 2 + offset * 4;
439 } else {
440 offset = (center_freq - primary_freq - 10) / 20;
441 center_chan += 2 + offset * 4;
442 }
443 break;
444 default:
445 center_chan = 0;
446 break;
447 }
448
449 switch (channel->band) {
450 default:
451 case NL80211_BAND_2GHZ:
452 band = RTW89_BAND_2G;
453 break;
454 case NL80211_BAND_5GHZ:
455 band = RTW89_BAND_5G;
456 break;
457 case NL80211_BAND_6GHZ:
458 band = RTW89_BAND_6G;
459 break;
460 }
461
462 rtw89_chan_create(chan, center_chan, channel->hw_value, band, bandwidth);
463 }
464
__rtw89_core_set_chip_txpwr(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_phy_idx phy_idx)465 static void __rtw89_core_set_chip_txpwr(struct rtw89_dev *rtwdev,
466 const struct rtw89_chan *chan,
467 enum rtw89_phy_idx phy_idx)
468 {
469 const struct rtw89_chip_info *chip = rtwdev->chip;
470 bool entity_active;
471
472 entity_active = rtw89_get_entity_state(rtwdev, phy_idx);
473 if (!entity_active)
474 return;
475
476 chip->ops->set_txpwr(rtwdev, chan, phy_idx);
477 }
478
rtw89_core_set_chip_txpwr(struct rtw89_dev * rtwdev)479 void rtw89_core_set_chip_txpwr(struct rtw89_dev *rtwdev)
480 {
481 const struct rtw89_chan *chan;
482
483 chan = rtw89_mgnt_chan_get(rtwdev, 0);
484 __rtw89_core_set_chip_txpwr(rtwdev, chan, RTW89_PHY_0);
485
486 if (!rtwdev->support_mlo)
487 return;
488
489 chan = rtw89_mgnt_chan_get(rtwdev, 1);
490 __rtw89_core_set_chip_txpwr(rtwdev, chan, RTW89_PHY_1);
491 }
492
rtw89_chip_rfk_channel(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link)493 void rtw89_chip_rfk_channel(struct rtw89_dev *rtwdev,
494 struct rtw89_vif_link *rtwvif_link)
495 {
496 const struct rtw89_chip_info *chip = rtwdev->chip;
497 bool mon = !!rtwdev->pure_monitor_mode_vif;
498 bool prehdl_link = false;
499
500 if (chip->chip_gen != RTW89_CHIP_AX &&
501 !RTW89_CHK_FW_FEATURE_GROUP(WITH_RFK_PRE_NOTIFY, &rtwdev->fw) &&
502 !mon && !rtw89_entity_check_hw(rtwdev, rtwvif_link->phy_idx))
503 prehdl_link = true;
504
505 if (prehdl_link) {
506 rtw89_entity_force_hw(rtwdev, rtwvif_link->phy_idx);
507 rtw89_set_channel(rtwdev);
508 }
509
510 if (chip->ops->rfk_channel)
511 chip->ops->rfk_channel(rtwdev, rtwvif_link);
512
513 if (prehdl_link) {
514 rtw89_entity_force_hw(rtwdev, RTW89_PHY_NUM);
515 rtw89_set_channel(rtwdev);
516 }
517 }
518
rtw89_chip_rfk_channel_for_pure_mon_vif(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx)519 static void rtw89_chip_rfk_channel_for_pure_mon_vif(struct rtw89_dev *rtwdev,
520 enum rtw89_phy_idx phy_idx)
521 {
522 struct rtw89_vif *rtwvif = rtwdev->pure_monitor_mode_vif;
523 struct rtw89_vif_link *rtwvif_link;
524
525 if (!rtwvif)
526 return;
527
528 rtwvif_link = rtw89_vif_get_link_inst(rtwvif, phy_idx);
529 if (!rtwvif_link)
530 return;
531
532 rtw89_chip_rfk_channel(rtwdev, rtwvif_link);
533 }
534
__rtw89_set_channel(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_mac_idx mac_idx,enum rtw89_phy_idx phy_idx)535 static void __rtw89_set_channel(struct rtw89_dev *rtwdev,
536 const struct rtw89_chan *chan,
537 enum rtw89_mac_idx mac_idx,
538 enum rtw89_phy_idx phy_idx)
539 {
540 const struct rtw89_chip_info *chip = rtwdev->chip;
541 const struct rtw89_chan_rcd *chan_rcd;
542 struct rtw89_channel_help_params bak;
543 bool entity_active;
544
545 entity_active = rtw89_get_entity_state(rtwdev, phy_idx);
546
547 chan_rcd = rtw89_chan_rcd_get_by_chan(chan);
548
549 rtw89_chip_set_channel_prepare(rtwdev, &bak, chan, mac_idx, phy_idx);
550
551 chip->ops->set_channel(rtwdev, chan, mac_idx, phy_idx);
552
553 chip->ops->set_txpwr(rtwdev, chan, phy_idx);
554
555 rtw89_chip_set_channel_done(rtwdev, &bak, chan, mac_idx, phy_idx);
556
557 if (!entity_active || chan_rcd->band_changed) {
558 rtw89_btc_ntfy_switch_band(rtwdev, phy_idx, chan->band_type);
559 rtw89_chip_rfk_band_changed(rtwdev, phy_idx, chan);
560 }
561
562 rtw89_set_entity_state(rtwdev, phy_idx, true);
563
564 rtw89_chip_rfk_channel_for_pure_mon_vif(rtwdev, phy_idx);
565 }
566
rtw89_set_channel(struct rtw89_dev * rtwdev)567 int rtw89_set_channel(struct rtw89_dev *rtwdev)
568 {
569 const struct rtw89_chan *chan;
570 enum rtw89_entity_mode mode;
571
572 mode = rtw89_entity_recalc(rtwdev);
573 if (mode < 0 || mode >= NUM_OF_RTW89_ENTITY_MODE) {
574 WARN(1, "Invalid ent mode: %d\n", mode);
575 return -EINVAL;
576 }
577
578 chan = rtw89_mgnt_chan_get(rtwdev, 0);
579 __rtw89_set_channel(rtwdev, chan, RTW89_MAC_0, RTW89_PHY_0);
580
581 if (!rtwdev->support_mlo)
582 return 0;
583
584 chan = rtw89_mgnt_chan_get(rtwdev, 1);
585 __rtw89_set_channel(rtwdev, chan, RTW89_MAC_1, RTW89_PHY_1);
586
587 return 0;
588 }
589
590 static enum rtw89_core_tx_type
rtw89_core_get_tx_type(struct rtw89_dev * rtwdev,struct sk_buff * skb)591 rtw89_core_get_tx_type(struct rtw89_dev *rtwdev,
592 struct sk_buff *skb)
593 {
594 struct ieee80211_hdr *hdr = (void *)skb->data;
595 __le16 fc = hdr->frame_control;
596
597 if (ieee80211_is_mgmt(fc) || ieee80211_is_any_nullfunc(fc))
598 return RTW89_CORE_TX_TYPE_MGMT;
599
600 return RTW89_CORE_TX_TYPE_DATA;
601 }
602
603 static void
rtw89_core_tx_update_ampdu_info(struct rtw89_dev * rtwdev,struct rtw89_core_tx_request * tx_req,enum btc_pkt_type pkt_type)604 rtw89_core_tx_update_ampdu_info(struct rtw89_dev *rtwdev,
605 struct rtw89_core_tx_request *tx_req,
606 enum btc_pkt_type pkt_type)
607 {
608 struct rtw89_sta_link *rtwsta_link = tx_req->rtwsta_link;
609 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info;
610 struct ieee80211_link_sta *link_sta;
611 struct sk_buff *skb = tx_req->skb;
612 struct rtw89_sta *rtwsta;
613 u8 ampdu_num;
614 u8 tid;
615
616 if (pkt_type == PACKET_EAPOL) {
617 desc_info->bk = true;
618 return;
619 }
620
621 if (!(IEEE80211_SKB_CB(skb)->flags & IEEE80211_TX_CTL_AMPDU))
622 return;
623
624 if (!rtwsta_link) {
625 rtw89_warn(rtwdev, "cannot set ampdu info without sta\n");
626 return;
627 }
628
629 tid = skb->priority & IEEE80211_QOS_CTL_TAG1D_MASK;
630 rtwsta = rtwsta_link->rtwsta;
631
632 rcu_read_lock();
633
634 link_sta = rtw89_sta_rcu_dereference_link(rtwsta_link, false);
635 ampdu_num = (u8)((rtwsta->ampdu_params[tid].agg_num ?
636 rtwsta->ampdu_params[tid].agg_num :
637 4 << link_sta->ht_cap.ampdu_factor) - 1);
638
639 desc_info->agg_en = true;
640 desc_info->ampdu_density = link_sta->ht_cap.ampdu_density;
641 desc_info->ampdu_num = ampdu_num;
642
643 rcu_read_unlock();
644 }
645
646 static void
rtw89_core_tx_update_sec_key(struct rtw89_dev * rtwdev,struct rtw89_core_tx_request * tx_req)647 rtw89_core_tx_update_sec_key(struct rtw89_dev *rtwdev,
648 struct rtw89_core_tx_request *tx_req)
649 {
650 struct rtw89_cam_info *cam_info = &rtwdev->cam_info;
651 const struct rtw89_chip_info *chip = rtwdev->chip;
652 const struct rtw89_sec_cam_entry *sec_cam;
653 struct ieee80211_tx_info *info;
654 struct ieee80211_key_conf *key;
655 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info;
656 struct sk_buff *skb = tx_req->skb;
657 u8 sec_type = RTW89_SEC_KEY_TYPE_NONE;
658 u8 sec_cam_idx;
659 u64 pn64;
660
661 info = IEEE80211_SKB_CB(skb);
662 key = info->control.hw_key;
663 sec_cam_idx = key->hw_key_idx;
664 sec_cam = cam_info->sec_entries[sec_cam_idx];
665 if (!sec_cam) {
666 rtw89_warn(rtwdev, "sec cam entry is empty\n");
667 return;
668 }
669
670 switch (key->cipher) {
671 case WLAN_CIPHER_SUITE_WEP40:
672 sec_type = RTW89_SEC_KEY_TYPE_WEP40;
673 break;
674 case WLAN_CIPHER_SUITE_WEP104:
675 sec_type = RTW89_SEC_KEY_TYPE_WEP104;
676 break;
677 case WLAN_CIPHER_SUITE_TKIP:
678 sec_type = RTW89_SEC_KEY_TYPE_TKIP;
679 break;
680 case WLAN_CIPHER_SUITE_CCMP:
681 sec_type = RTW89_SEC_KEY_TYPE_CCMP128;
682 break;
683 case WLAN_CIPHER_SUITE_CCMP_256:
684 sec_type = RTW89_SEC_KEY_TYPE_CCMP256;
685 break;
686 case WLAN_CIPHER_SUITE_GCMP:
687 sec_type = RTW89_SEC_KEY_TYPE_GCMP128;
688 break;
689 case WLAN_CIPHER_SUITE_GCMP_256:
690 sec_type = RTW89_SEC_KEY_TYPE_GCMP256;
691 break;
692 default:
693 rtw89_warn(rtwdev, "key cipher not supported %d\n", key->cipher);
694 return;
695 }
696
697 desc_info->sec_en = true;
698 desc_info->sec_keyid = key->keyidx;
699 desc_info->sec_type = sec_type;
700 desc_info->sec_cam_idx = sec_cam->sec_cam_idx;
701
702 if (!chip->hw_sec_hdr)
703 return;
704
705 pn64 = atomic64_inc_return(&key->tx_pn);
706 desc_info->sec_seq[0] = pn64;
707 desc_info->sec_seq[1] = pn64 >> 8;
708 desc_info->sec_seq[2] = pn64 >> 16;
709 desc_info->sec_seq[3] = pn64 >> 24;
710 desc_info->sec_seq[4] = pn64 >> 32;
711 desc_info->sec_seq[5] = pn64 >> 40;
712 desc_info->wp_offset = 1; /* in unit of 8 bytes for security header */
713 }
714
rtw89_core_get_mgmt_rate(struct rtw89_dev * rtwdev,struct rtw89_core_tx_request * tx_req,const struct rtw89_chan * chan)715 static u16 rtw89_core_get_mgmt_rate(struct rtw89_dev *rtwdev,
716 struct rtw89_core_tx_request *tx_req,
717 const struct rtw89_chan *chan)
718 {
719 struct sk_buff *skb = tx_req->skb;
720 struct rtw89_vif_link *rtwvif_link = tx_req->rtwvif_link;
721 struct rtw89_sta_link *rtwsta_link = tx_req->rtwsta_link;
722 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
723 struct ieee80211_vif *vif = tx_info->control.vif;
724 struct ieee80211_bss_conf *bss_conf;
725 u16 lowest_rate;
726 u16 rate;
727
728 if (tx_info->flags & IEEE80211_TX_CTL_NO_CCK_RATE ||
729 (vif && vif->p2p))
730 lowest_rate = RTW89_HW_RATE_OFDM6;
731 else if (chan->band_type == RTW89_BAND_2G)
732 lowest_rate = RTW89_HW_RATE_CCK1;
733 else
734 lowest_rate = RTW89_HW_RATE_OFDM6;
735
736 if (!rtwvif_link)
737 return lowest_rate;
738
739 rcu_read_lock();
740
741 bss_conf = rtw89_vif_rcu_dereference_link(rtwvif_link, false);
742 if (!bss_conf->basic_rates || !rtwsta_link) {
743 rate = lowest_rate;
744 goto out;
745 }
746
747 rate = __ffs(bss_conf->basic_rates) + lowest_rate;
748
749 out:
750 rcu_read_unlock();
751
752 return rate;
753 }
754
rtw89_core_tx_get_mac_id(struct rtw89_dev * rtwdev,struct rtw89_core_tx_request * tx_req)755 static u8 rtw89_core_tx_get_mac_id(struct rtw89_dev *rtwdev,
756 struct rtw89_core_tx_request *tx_req)
757 {
758 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info;
759 struct rtw89_vif_link *rtwvif_link = tx_req->rtwvif_link;
760 struct rtw89_sta_link *rtwsta_link = tx_req->rtwsta_link;
761
762 if (desc_info->mlo && !desc_info->sw_mld) {
763 if (rtwsta_link)
764 return rtw89_sta_get_main_macid(rtwsta_link->rtwsta);
765 else
766 return rtw89_vif_get_main_macid(rtwvif_link->rtwvif);
767 }
768
769 if (!rtwsta_link)
770 return rtwvif_link->mac_id;
771
772 return rtwsta_link->mac_id;
773 }
774
rtw89_core_tx_update_llc_hdr(struct rtw89_dev * rtwdev,struct rtw89_tx_desc_info * desc_info,struct sk_buff * skb)775 static void rtw89_core_tx_update_llc_hdr(struct rtw89_dev *rtwdev,
776 struct rtw89_tx_desc_info *desc_info,
777 struct sk_buff *skb)
778 {
779 struct ieee80211_hdr *hdr = (void *)skb->data;
780 __le16 fc = hdr->frame_control;
781
782 desc_info->hdr_llc_len = ieee80211_hdrlen(fc);
783 desc_info->hdr_llc_len >>= 1; /* in unit of 2 bytes */
784 }
785
rtw89_core_get_ch_dma(struct rtw89_dev * rtwdev,u8 qsel)786 u8 rtw89_core_get_ch_dma(struct rtw89_dev *rtwdev, u8 qsel)
787 {
788 switch (qsel) {
789 default:
790 rtw89_warn(rtwdev, "Cannot map qsel to dma: %d\n", qsel);
791 fallthrough;
792 case RTW89_TX_QSEL_BE_0:
793 case RTW89_TX_QSEL_BE_1:
794 case RTW89_TX_QSEL_BE_2:
795 case RTW89_TX_QSEL_BE_3:
796 return RTW89_TXCH_ACH0;
797 case RTW89_TX_QSEL_BK_0:
798 case RTW89_TX_QSEL_BK_1:
799 case RTW89_TX_QSEL_BK_2:
800 case RTW89_TX_QSEL_BK_3:
801 return RTW89_TXCH_ACH1;
802 case RTW89_TX_QSEL_VI_0:
803 case RTW89_TX_QSEL_VI_1:
804 case RTW89_TX_QSEL_VI_2:
805 case RTW89_TX_QSEL_VI_3:
806 return RTW89_TXCH_ACH2;
807 case RTW89_TX_QSEL_VO_0:
808 case RTW89_TX_QSEL_VO_1:
809 case RTW89_TX_QSEL_VO_2:
810 case RTW89_TX_QSEL_VO_3:
811 return RTW89_TXCH_ACH3;
812 case RTW89_TX_QSEL_B0_MGMT:
813 return RTW89_TXCH_CH8;
814 case RTW89_TX_QSEL_B0_HI:
815 return RTW89_TXCH_CH9;
816 case RTW89_TX_QSEL_B1_MGMT:
817 return RTW89_TXCH_CH10;
818 case RTW89_TX_QSEL_B1_HI:
819 return RTW89_TXCH_CH11;
820 }
821 }
822 EXPORT_SYMBOL(rtw89_core_get_ch_dma);
823
rtw89_core_get_ch_dma_v1(struct rtw89_dev * rtwdev,u8 qsel)824 u8 rtw89_core_get_ch_dma_v1(struct rtw89_dev *rtwdev, u8 qsel)
825 {
826 switch (qsel) {
827 default:
828 rtw89_warn(rtwdev, "Cannot map qsel to dma v1: %d\n", qsel);
829 fallthrough;
830 case RTW89_TX_QSEL_BE_0:
831 case RTW89_TX_QSEL_BK_0:
832 return RTW89_TXCH_ACH0;
833 case RTW89_TX_QSEL_VI_0:
834 case RTW89_TX_QSEL_VO_0:
835 return RTW89_TXCH_ACH2;
836 case RTW89_TX_QSEL_B0_MGMT:
837 case RTW89_TX_QSEL_B0_HI:
838 return RTW89_TXCH_CH8;
839 case RTW89_TX_QSEL_B1_MGMT:
840 case RTW89_TX_QSEL_B1_HI:
841 return RTW89_TXCH_CH10;
842 }
843 }
844 EXPORT_SYMBOL(rtw89_core_get_ch_dma_v1);
845
rtw89_core_get_ch_dma_v2(struct rtw89_dev * rtwdev,u8 qsel)846 u8 rtw89_core_get_ch_dma_v2(struct rtw89_dev *rtwdev, u8 qsel)
847 {
848 switch (qsel) {
849 default:
850 rtw89_warn(rtwdev, "Cannot map qsel to dma v2: %d\n", qsel);
851 fallthrough;
852 case RTW89_TX_QSEL_BE_0:
853 case RTW89_TX_QSEL_VO_0:
854 return RTW89_TXCH_ACH0;
855 case RTW89_TX_QSEL_BK_0:
856 case RTW89_TX_QSEL_VI_0:
857 return RTW89_TXCH_ACH2;
858 case RTW89_TX_QSEL_B0_MGMT:
859 case RTW89_TX_QSEL_B0_HI:
860 return RTW89_TXCH_CH8;
861 }
862 }
863 EXPORT_SYMBOL(rtw89_core_get_ch_dma_v2);
864
865 static void
rtw89_core_tx_update_mgmt_info(struct rtw89_dev * rtwdev,struct rtw89_core_tx_request * tx_req)866 rtw89_core_tx_update_mgmt_info(struct rtw89_dev *rtwdev,
867 struct rtw89_core_tx_request *tx_req)
868 {
869 const struct rtw89_chip_info *chip = rtwdev->chip;
870 struct rtw89_vif_link *rtwvif_link = tx_req->rtwvif_link;
871 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info;
872 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev,
873 rtwvif_link->chanctx_idx);
874 struct sk_buff *skb = tx_req->skb;
875 u8 qsel, ch_dma;
876
877 qsel = rtw89_core_get_qsel_mgmt(rtwdev, tx_req);
878 ch_dma = rtw89_chip_get_ch_dma(rtwdev, qsel);
879
880 desc_info->qsel = qsel;
881 desc_info->ch_dma = ch_dma;
882 desc_info->sw_mld = true;
883 desc_info->port = desc_info->hiq ? rtwvif_link->port : 0;
884 desc_info->mac_id = rtw89_core_tx_get_mac_id(rtwdev, tx_req);
885 desc_info->hw_ssn_sel = RTW89_MGMT_HW_SSN_SEL;
886 desc_info->hw_seq_mode = RTW89_MGMT_HW_SEQ_MODE;
887
888 /* fixed data rate for mgmt frames */
889 desc_info->en_wd_info = true;
890 desc_info->use_rate = true;
891 desc_info->dis_data_fb = true;
892 desc_info->data_rate = rtw89_core_get_mgmt_rate(rtwdev, tx_req, chan);
893
894 if (chip->hw_mgmt_tx_encrypt && IEEE80211_SKB_CB(skb)->control.hw_key) {
895 rtw89_core_tx_update_sec_key(rtwdev, tx_req);
896 rtw89_core_tx_update_llc_hdr(rtwdev, desc_info, skb);
897 }
898
899 rtw89_debug(rtwdev, RTW89_DBG_TXRX,
900 "tx mgmt frame with rate 0x%x on channel %d (band %d, bw %d)\n",
901 desc_info->data_rate, chan->channel, chan->band_type,
902 chan->band_width);
903 }
904
905 static void
rtw89_core_tx_update_h2c_info(struct rtw89_dev * rtwdev,struct rtw89_core_tx_request * tx_req)906 rtw89_core_tx_update_h2c_info(struct rtw89_dev *rtwdev,
907 struct rtw89_core_tx_request *tx_req)
908 {
909 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info;
910
911 desc_info->is_bmc = false;
912 desc_info->wd_page = false;
913 desc_info->ch_dma = RTW89_DMA_H2C;
914 }
915
rtw89_core_get_no_ul_ofdma_htc(struct rtw89_dev * rtwdev,__le32 * htc,const struct rtw89_chan * chan)916 static void rtw89_core_get_no_ul_ofdma_htc(struct rtw89_dev *rtwdev, __le32 *htc,
917 const struct rtw89_chan *chan)
918 {
919 static const u8 rtw89_bandwidth_to_om[] = {
920 [RTW89_CHANNEL_WIDTH_20] = HTC_OM_CHANNEL_WIDTH_20,
921 [RTW89_CHANNEL_WIDTH_40] = HTC_OM_CHANNEL_WIDTH_40,
922 [RTW89_CHANNEL_WIDTH_80] = HTC_OM_CHANNEL_WIDTH_80,
923 [RTW89_CHANNEL_WIDTH_160] = HTC_OM_CHANNEL_WIDTH_160_OR_80_80,
924 [RTW89_CHANNEL_WIDTH_80_80] = HTC_OM_CHANNEL_WIDTH_160_OR_80_80,
925 };
926 const struct rtw89_chip_info *chip = rtwdev->chip;
927 struct rtw89_hal *hal = &rtwdev->hal;
928 u8 om_bandwidth;
929
930 if (!chip->dis_2g_40m_ul_ofdma ||
931 chan->band_type != RTW89_BAND_2G ||
932 chan->band_width != RTW89_CHANNEL_WIDTH_40)
933 return;
934
935 om_bandwidth = chan->band_width < ARRAY_SIZE(rtw89_bandwidth_to_om) ?
936 rtw89_bandwidth_to_om[chan->band_width] : 0;
937 *htc = le32_encode_bits(RTW89_HTC_VARIANT_HE, RTW89_HTC_MASK_VARIANT) |
938 le32_encode_bits(RTW89_HTC_VARIANT_HE_CID_OM, RTW89_HTC_MASK_CTL_ID) |
939 le32_encode_bits(hal->rx_nss - 1, RTW89_HTC_MASK_HTC_OM_RX_NSS) |
940 le32_encode_bits(om_bandwidth, RTW89_HTC_MASK_HTC_OM_CH_WIDTH) |
941 le32_encode_bits(1, RTW89_HTC_MASK_HTC_OM_UL_MU_DIS) |
942 le32_encode_bits(hal->tx_nss - 1, RTW89_HTC_MASK_HTC_OM_TX_NSTS) |
943 le32_encode_bits(0, RTW89_HTC_MASK_HTC_OM_ER_SU_DIS) |
944 le32_encode_bits(0, RTW89_HTC_MASK_HTC_OM_DL_MU_MIMO_RR) |
945 le32_encode_bits(0, RTW89_HTC_MASK_HTC_OM_UL_MU_DATA_DIS);
946 }
947
948 static bool
__rtw89_core_tx_check_he_qos_htc(struct rtw89_dev * rtwdev,struct rtw89_core_tx_request * tx_req,enum btc_pkt_type pkt_type)949 __rtw89_core_tx_check_he_qos_htc(struct rtw89_dev *rtwdev,
950 struct rtw89_core_tx_request *tx_req,
951 enum btc_pkt_type pkt_type)
952 {
953 struct rtw89_sta_link *rtwsta_link = tx_req->rtwsta_link;
954 struct sk_buff *skb = tx_req->skb;
955 struct ieee80211_hdr *hdr = (void *)skb->data;
956 struct ieee80211_link_sta *link_sta;
957 __le16 fc = hdr->frame_control;
958
959 /* AP IOT issue with EAPoL, ARP and DHCP */
960 if (pkt_type < PACKET_MAX)
961 return false;
962
963 if (!rtwsta_link)
964 return false;
965
966 rcu_read_lock();
967
968 link_sta = rtw89_sta_rcu_dereference_link(rtwsta_link, false);
969 if (!link_sta->he_cap.has_he) {
970 rcu_read_unlock();
971 return false;
972 }
973
974 rcu_read_unlock();
975
976 if (!ieee80211_is_data_qos(fc))
977 return false;
978
979 if (skb_headroom(skb) < IEEE80211_HT_CTL_LEN)
980 return false;
981
982 if (rtwsta_link && rtwsta_link->ra_report.might_fallback_legacy)
983 return false;
984
985 return true;
986 }
987
988 static void
__rtw89_core_tx_adjust_he_qos_htc(struct rtw89_dev * rtwdev,struct rtw89_core_tx_request * tx_req)989 __rtw89_core_tx_adjust_he_qos_htc(struct rtw89_dev *rtwdev,
990 struct rtw89_core_tx_request *tx_req)
991 {
992 struct rtw89_sta_link *rtwsta_link = tx_req->rtwsta_link;
993 struct sk_buff *skb = tx_req->skb;
994 struct ieee80211_hdr *hdr = (void *)skb->data;
995 __le16 fc = hdr->frame_control;
996 void *data;
997 __le32 *htc;
998 u8 *qc;
999 int hdr_len;
1000
1001 hdr_len = ieee80211_has_a4(fc) ? 32 : 26;
1002 data = skb_push(skb, IEEE80211_HT_CTL_LEN);
1003 #if defined(__linux__)
1004 memmove(data, data + IEEE80211_HT_CTL_LEN, hdr_len);
1005 #elif defined(__FreeBSD__)
1006 memmove(data, (u8 *)data + IEEE80211_HT_CTL_LEN, hdr_len);
1007 #endif
1008
1009 hdr = data;
1010 #if defined(__linux__)
1011 htc = data + hdr_len;
1012 #elif defined(__FreeBSD__)
1013 htc = (__le32 *)((u8 *)data + hdr_len);
1014 #endif
1015 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_ORDER);
1016 *htc = rtwsta_link->htc_template ? rtwsta_link->htc_template :
1017 le32_encode_bits(RTW89_HTC_VARIANT_HE, RTW89_HTC_MASK_VARIANT) |
1018 le32_encode_bits(RTW89_HTC_VARIANT_HE_CID_CAS, RTW89_HTC_MASK_CTL_ID);
1019
1020 #if defined(__linux__)
1021 qc = data + hdr_len - IEEE80211_QOS_CTL_LEN;
1022 #elif defined(__FreeBSD__)
1023 qc = (u8 *)data + hdr_len - IEEE80211_QOS_CTL_LEN;
1024 #endif
1025 qc[0] |= IEEE80211_QOS_CTL_EOSP;
1026 }
1027
1028 static void
rtw89_core_tx_update_he_qos_htc(struct rtw89_dev * rtwdev,struct rtw89_core_tx_request * tx_req,enum btc_pkt_type pkt_type)1029 rtw89_core_tx_update_he_qos_htc(struct rtw89_dev *rtwdev,
1030 struct rtw89_core_tx_request *tx_req,
1031 enum btc_pkt_type pkt_type)
1032 {
1033 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info;
1034 struct rtw89_vif_link *rtwvif_link = tx_req->rtwvif_link;
1035
1036 if (!__rtw89_core_tx_check_he_qos_htc(rtwdev, tx_req, pkt_type))
1037 goto desc_bk;
1038
1039 __rtw89_core_tx_adjust_he_qos_htc(rtwdev, tx_req);
1040
1041 desc_info->pkt_size += IEEE80211_HT_CTL_LEN;
1042 desc_info->a_ctrl_bsr = true;
1043
1044 desc_bk:
1045 if (!rtwvif_link || rtwvif_link->last_a_ctrl == desc_info->a_ctrl_bsr)
1046 return;
1047
1048 rtwvif_link->last_a_ctrl = desc_info->a_ctrl_bsr;
1049 desc_info->bk = true;
1050 }
1051
rtw89_core_get_data_rate(struct rtw89_dev * rtwdev,struct rtw89_core_tx_request * tx_req)1052 static u16 rtw89_core_get_data_rate(struct rtw89_dev *rtwdev,
1053 struct rtw89_core_tx_request *tx_req)
1054 {
1055 struct rtw89_vif_link *rtwvif_link = tx_req->rtwvif_link;
1056 struct rtw89_sta_link *rtwsta_link = tx_req->rtwsta_link;
1057 struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link);
1058 struct rtw89_phy_rate_pattern *rate_pattern = &rtwvif_link->rate_pattern;
1059 enum rtw89_chanctx_idx idx = rtwvif_link->chanctx_idx;
1060 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, idx);
1061 struct ieee80211_link_sta *link_sta;
1062 u16 lowest_rate;
1063 u16 rate;
1064
1065 if (rate_pattern->enable)
1066 return rate_pattern->rate;
1067
1068 if (vif->p2p)
1069 lowest_rate = RTW89_HW_RATE_OFDM6;
1070 else if (chan->band_type == RTW89_BAND_2G)
1071 lowest_rate = RTW89_HW_RATE_CCK1;
1072 else
1073 lowest_rate = RTW89_HW_RATE_OFDM6;
1074
1075 if (!rtwsta_link)
1076 return lowest_rate;
1077
1078 rcu_read_lock();
1079
1080 link_sta = rtw89_sta_rcu_dereference_link(rtwsta_link, false);
1081 if (!link_sta->supp_rates[chan->band_type]) {
1082 rate = lowest_rate;
1083 goto out;
1084 }
1085
1086 rate = __ffs(link_sta->supp_rates[chan->band_type]) + lowest_rate;
1087
1088 out:
1089 rcu_read_unlock();
1090
1091 return rate;
1092 }
1093
1094 static void
rtw89_core_tx_update_data_info(struct rtw89_dev * rtwdev,struct rtw89_core_tx_request * tx_req)1095 rtw89_core_tx_update_data_info(struct rtw89_dev *rtwdev,
1096 struct rtw89_core_tx_request *tx_req)
1097 {
1098 struct rtw89_vif_link *rtwvif_link = tx_req->rtwvif_link;
1099 struct rtw89_sta_link *rtwsta_link = tx_req->rtwsta_link;
1100 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info;
1101 struct sk_buff *skb = tx_req->skb;
1102 u8 tid, tid_indicate;
1103 u8 qsel, ch_dma;
1104
1105 tid = skb->priority & IEEE80211_QOS_CTL_TAG1D_MASK;
1106 tid_indicate = rtw89_core_get_tid_indicate(rtwdev, tid);
1107 qsel = desc_info->hiq ? RTW89_TX_QSEL_B0_HI : rtw89_core_get_qsel(rtwdev, tid);
1108 ch_dma = rtw89_chip_get_ch_dma(rtwdev, qsel);
1109
1110 desc_info->ch_dma = ch_dma;
1111 desc_info->tid_indicate = tid_indicate;
1112 desc_info->qsel = qsel;
1113 desc_info->sw_mld = false;
1114 desc_info->mac_id = rtw89_core_tx_get_mac_id(rtwdev, tx_req);
1115 desc_info->port = desc_info->hiq ? rtwvif_link->port : 0;
1116 desc_info->er_cap = rtwsta_link ? rtwsta_link->er_cap : false;
1117 desc_info->stbc = rtwsta_link ? rtwsta_link->ra.stbc_cap : false;
1118 desc_info->ldpc = rtwsta_link ? rtwsta_link->ra.ldpc_cap : false;
1119
1120 /* enable wd_info for AMPDU */
1121 desc_info->en_wd_info = true;
1122
1123 if (IEEE80211_SKB_CB(skb)->control.hw_key)
1124 rtw89_core_tx_update_sec_key(rtwdev, tx_req);
1125
1126 desc_info->data_retry_lowest_rate = rtw89_core_get_data_rate(rtwdev, tx_req);
1127 }
1128
1129 static enum btc_pkt_type
rtw89_core_tx_btc_spec_pkt_notify(struct rtw89_dev * rtwdev,struct rtw89_core_tx_request * tx_req)1130 rtw89_core_tx_btc_spec_pkt_notify(struct rtw89_dev *rtwdev,
1131 struct rtw89_core_tx_request *tx_req)
1132 {
1133 struct wiphy *wiphy = rtwdev->hw->wiphy;
1134 struct sk_buff *skb = tx_req->skb;
1135 struct udphdr *udphdr;
1136
1137 if (IEEE80211_SKB_CB(skb)->control.flags & IEEE80211_TX_CTRL_PORT_CTRL_PROTO) {
1138 wiphy_work_queue(wiphy, &rtwdev->btc.eapol_notify_work);
1139 return PACKET_EAPOL;
1140 }
1141
1142 if (skb->protocol == htons(ETH_P_ARP)) {
1143 wiphy_work_queue(wiphy, &rtwdev->btc.arp_notify_work);
1144 return PACKET_ARP;
1145 }
1146
1147 if (skb->protocol == htons(ETH_P_IP) &&
1148 ip_hdr(skb)->protocol == IPPROTO_UDP) {
1149 udphdr = udp_hdr(skb);
1150 if (((udphdr->source == htons(67) && udphdr->dest == htons(68)) ||
1151 (udphdr->source == htons(68) && udphdr->dest == htons(67))) &&
1152 skb->len > 282) {
1153 wiphy_work_queue(wiphy, &rtwdev->btc.dhcp_notify_work);
1154 return PACKET_DHCP;
1155 }
1156 }
1157
1158 if (skb->protocol == htons(ETH_P_IP) &&
1159 ip_hdr(skb)->protocol == IPPROTO_ICMP) {
1160 wiphy_work_queue(wiphy, &rtwdev->btc.icmp_notify_work);
1161 return PACKET_ICMP;
1162 }
1163
1164 return PACKET_MAX;
1165 }
1166
1167 static void
rtw89_core_tx_wake(struct rtw89_dev * rtwdev,struct rtw89_core_tx_request * tx_req)1168 rtw89_core_tx_wake(struct rtw89_dev *rtwdev,
1169 struct rtw89_core_tx_request *tx_req)
1170 {
1171 const struct rtw89_chip_info *chip = rtwdev->chip;
1172
1173 if (!RTW89_CHK_FW_FEATURE(TX_WAKE, &rtwdev->fw))
1174 return;
1175
1176 switch (chip->chip_id) {
1177 case RTL8852BT:
1178 if (test_bit(RTW89_FLAG_LEISURE_PS, rtwdev->flags))
1179 goto notify;
1180 break;
1181 case RTL8852C:
1182 if (test_bit(RTW89_FLAG_LOW_POWER_MODE, rtwdev->flags))
1183 goto notify;
1184 break;
1185 default:
1186 if (test_bit(RTW89_FLAG_LOW_POWER_MODE, rtwdev->flags) &&
1187 tx_req->tx_type == RTW89_CORE_TX_TYPE_MGMT)
1188 goto notify;
1189 break;
1190 }
1191
1192 return;
1193
1194 notify:
1195 rtw89_mac_notify_wake(rtwdev);
1196 }
1197
rtw89_core_tx_update_injection(struct rtw89_dev * rtwdev,struct rtw89_core_tx_request * tx_req,struct ieee80211_tx_info * info)1198 static void rtw89_core_tx_update_injection(struct rtw89_dev *rtwdev,
1199 struct rtw89_core_tx_request *tx_req,
1200 struct ieee80211_tx_info *info)
1201 {
1202 const struct rtw89_hw_rate_def *hw_rate = &rtw89_hw_rate[rtwdev->chip->chip_gen];
1203 enum mac80211_rate_control_flags flags = info->control.rates[0].flags;
1204 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info;
1205 const struct rtw89_chan *chan;
1206 u8 idx = info->control.rates[0].idx;
1207 u8 nss, mcs;
1208
1209 desc_info->use_rate = true;
1210 desc_info->dis_data_fb = true;
1211
1212 if (flags & IEEE80211_TX_RC_160_MHZ_WIDTH)
1213 desc_info->data_bw = 3;
1214 else if (flags & IEEE80211_TX_RC_80_MHZ_WIDTH)
1215 desc_info->data_bw = 2;
1216 else if (flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
1217 desc_info->data_bw = 1;
1218
1219 if (flags & IEEE80211_TX_RC_SHORT_GI)
1220 desc_info->gi_ltf = 1;
1221
1222 if (flags & IEEE80211_TX_RC_VHT_MCS) {
1223 nss = umin(idx >> 4, ARRAY_SIZE(hw_rate->vht) - 1);
1224 mcs = idx & 0xf;
1225 desc_info->data_rate = hw_rate->vht[nss] + mcs;
1226 } else if (flags & IEEE80211_TX_RC_MCS) {
1227 desc_info->data_rate = hw_rate->ht + idx;
1228 } else {
1229 chan = rtw89_chan_get(rtwdev, tx_req->rtwvif_link->chanctx_idx);
1230
1231 desc_info->data_rate = idx + (chan->band_type == RTW89_BAND_2G ?
1232 RTW89_HW_RATE_CCK1 : RTW89_HW_RATE_OFDM6);
1233 }
1234 }
1235
1236 static void
rtw89_core_tx_update_desc_info(struct rtw89_dev * rtwdev,struct rtw89_core_tx_request * tx_req)1237 rtw89_core_tx_update_desc_info(struct rtw89_dev *rtwdev,
1238 struct rtw89_core_tx_request *tx_req)
1239 {
1240 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info;
1241 struct sk_buff *skb = tx_req->skb;
1242 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1243 struct ieee80211_hdr *hdr = (void *)skb->data;
1244 struct rtw89_addr_cam_entry *addr_cam;
1245 enum btc_pkt_type pkt_type;
1246 bool upd_wlan_hdr = false;
1247 bool is_bmc;
1248 u16 seq;
1249
1250 desc_info->pkt_size = skb->len;
1251
1252 if (unlikely(tx_req->tx_type == RTW89_CORE_TX_TYPE_FWCMD)) {
1253 rtw89_core_tx_update_h2c_info(rtwdev, tx_req);
1254 return;
1255 }
1256
1257 tx_req->tx_type = rtw89_core_get_tx_type(rtwdev, skb);
1258
1259 if (tx_req->sta)
1260 desc_info->mlo = tx_req->sta->mlo;
1261 else if (tx_req->vif)
1262 desc_info->mlo = ieee80211_vif_is_mld(tx_req->vif);
1263
1264 seq = (le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_SEQ) >> 4;
1265 addr_cam = rtw89_get_addr_cam_of(tx_req->rtwvif_link,
1266 tx_req->rtwsta_link);
1267 if (addr_cam->valid && desc_info->mlo)
1268 upd_wlan_hdr = true;
1269
1270 if (info->flags & IEEE80211_TX_CTL_REQ_TX_STATUS || tx_req->with_wait)
1271 rtw89_tx_rpt_init(rtwdev, tx_req);
1272
1273 is_bmc = (is_broadcast_ether_addr(hdr->addr1) ||
1274 is_multicast_ether_addr(hdr->addr1));
1275
1276 desc_info->seq = seq;
1277 desc_info->is_bmc = is_bmc;
1278 desc_info->wd_page = true;
1279 desc_info->hiq = info->flags & IEEE80211_TX_CTL_SEND_AFTER_DTIM;
1280 desc_info->upd_wlan_hdr = upd_wlan_hdr;
1281
1282 switch (tx_req->tx_type) {
1283 case RTW89_CORE_TX_TYPE_MGMT:
1284 rtw89_core_tx_update_mgmt_info(rtwdev, tx_req);
1285 break;
1286 case RTW89_CORE_TX_TYPE_DATA:
1287 rtw89_core_tx_update_data_info(rtwdev, tx_req);
1288 pkt_type = rtw89_core_tx_btc_spec_pkt_notify(rtwdev, tx_req);
1289 rtw89_core_tx_update_he_qos_htc(rtwdev, tx_req, pkt_type);
1290 rtw89_core_tx_update_ampdu_info(rtwdev, tx_req, pkt_type);
1291 rtw89_core_tx_update_llc_hdr(rtwdev, desc_info, skb);
1292 break;
1293 default:
1294 break;
1295 }
1296
1297 if (unlikely(info->flags & IEEE80211_TX_CTL_INJECTED))
1298 rtw89_core_tx_update_injection(rtwdev, tx_req, info);
1299 }
1300
rtw89_tx_wait_work(struct wiphy * wiphy,struct wiphy_work * work)1301 static void rtw89_tx_wait_work(struct wiphy *wiphy, struct wiphy_work *work)
1302 {
1303 struct rtw89_dev *rtwdev = container_of(work, struct rtw89_dev,
1304 tx_wait_work.work);
1305
1306 rtw89_tx_wait_list_clear(rtwdev);
1307 }
1308
rtw89_core_tx_kick_off(struct rtw89_dev * rtwdev,u8 qsel)1309 void rtw89_core_tx_kick_off(struct rtw89_dev *rtwdev, u8 qsel)
1310 {
1311 u8 ch_dma;
1312
1313 ch_dma = rtw89_chip_get_ch_dma(rtwdev, qsel);
1314
1315 rtw89_hci_tx_kick_off(rtwdev, ch_dma);
1316 }
1317
rtw89_core_tx_kick_off_and_wait(struct rtw89_dev * rtwdev,struct sk_buff * skb,struct rtw89_tx_wait_info * wait,int qsel,unsigned int timeout)1318 int rtw89_core_tx_kick_off_and_wait(struct rtw89_dev *rtwdev, struct sk_buff *skb,
1319 struct rtw89_tx_wait_info *wait, int qsel,
1320 unsigned int timeout)
1321 {
1322 unsigned long time_left;
1323 int ret = 0;
1324
1325 lockdep_assert_wiphy(rtwdev->hw->wiphy);
1326
1327 rtw89_core_tx_kick_off(rtwdev, qsel);
1328 time_left = wait_for_completion_timeout(&wait->completion,
1329 msecs_to_jiffies(timeout));
1330
1331 if (time_left == 0) {
1332 ret = -ETIMEDOUT;
1333 list_add_tail(&wait->list, &rtwdev->tx_waits);
1334 wiphy_delayed_work_queue(rtwdev->hw->wiphy, &rtwdev->tx_wait_work,
1335 RTW89_TX_WAIT_WORK_TIMEOUT);
1336 } else {
1337 if (!wait->tx_done)
1338 ret = -EAGAIN;
1339 rtw89_tx_wait_release(wait);
1340 }
1341
1342 return ret;
1343 }
1344
rtw89_h2c_tx(struct rtw89_dev * rtwdev,struct sk_buff * skb,bool fwdl)1345 int rtw89_h2c_tx(struct rtw89_dev *rtwdev,
1346 struct sk_buff *skb, bool fwdl)
1347 {
1348 struct rtw89_core_tx_request tx_req = {0};
1349 u32 cnt;
1350 int ret;
1351
1352 if (!test_bit(RTW89_FLAG_POWERON, rtwdev->flags)) {
1353 rtw89_debug(rtwdev, RTW89_DBG_FW,
1354 "ignore h2c due to power is off with firmware state=%d\n",
1355 test_bit(RTW89_FLAG_FW_RDY, rtwdev->flags));
1356 dev_kfree_skb(skb);
1357 return 0;
1358 }
1359
1360 tx_req.skb = skb;
1361 tx_req.tx_type = RTW89_CORE_TX_TYPE_FWCMD;
1362 if (fwdl)
1363 tx_req.desc_info.fw_dl = true;
1364
1365 rtw89_core_tx_update_desc_info(rtwdev, &tx_req);
1366
1367 if (!fwdl)
1368 rtw89_hex_dump(rtwdev, RTW89_DBG_FW, "H2C: ", skb->data, skb->len);
1369
1370 cnt = rtw89_hci_check_and_reclaim_tx_resource(rtwdev, RTW89_TXCH_CH12);
1371 if (cnt == 0) {
1372 rtw89_err(rtwdev, "no tx fwcmd resource\n");
1373 return -ENOSPC;
1374 }
1375
1376 ret = rtw89_hci_tx_write(rtwdev, &tx_req);
1377 if (ret) {
1378 rtw89_err(rtwdev, "failed to transmit skb to HCI\n");
1379 return ret;
1380 }
1381 rtw89_hci_tx_kick_off(rtwdev, RTW89_TXCH_CH12);
1382
1383 return 0;
1384 }
1385
rtw89_core_tx_write_link(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link,struct rtw89_sta_link * rtwsta_link,struct sk_buff * skb,int * qsel,struct rtw89_tx_wait_info * wait)1386 static int rtw89_core_tx_write_link(struct rtw89_dev *rtwdev,
1387 struct rtw89_vif_link *rtwvif_link,
1388 struct rtw89_sta_link *rtwsta_link,
1389 struct sk_buff *skb, int *qsel,
1390 struct rtw89_tx_wait_info *wait)
1391 {
1392 struct ieee80211_sta *sta = rtwsta_link_to_sta_safe(rtwsta_link);
1393 struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link);
1394 struct rtw89_tx_skb_data *skb_data = RTW89_TX_SKB_CB(skb);
1395 struct rtw89_vif *rtwvif = rtwvif_link->rtwvif;
1396 struct rtw89_core_tx_request tx_req = {};
1397 int ret;
1398
1399 tx_req.skb = skb;
1400 tx_req.vif = vif;
1401 tx_req.sta = sta;
1402 tx_req.rtwvif_link = rtwvif_link;
1403 tx_req.rtwsta_link = rtwsta_link;
1404 tx_req.with_wait = !!wait;
1405
1406 rtw89_traffic_stats_accu(rtwdev, rtwvif, skb, true, true);
1407 rtw89_wow_parse_akm(rtwdev, skb);
1408 rtw89_core_tx_update_desc_info(rtwdev, &tx_req);
1409 rtw89_core_tx_wake(rtwdev, &tx_req);
1410
1411 rcu_assign_pointer(skb_data->wait, wait);
1412
1413 ret = rtw89_hci_tx_write(rtwdev, &tx_req);
1414 if (ret) {
1415 rtw89_err(rtwdev, "failed to transmit skb to HCI\n");
1416 return ret;
1417 }
1418
1419 if (qsel)
1420 *qsel = tx_req.desc_info.qsel;
1421
1422 return 0;
1423 }
1424
rtw89_core_tx_write(struct rtw89_dev * rtwdev,struct ieee80211_vif * vif,struct ieee80211_sta * sta,struct sk_buff * skb,int * qsel)1425 int rtw89_core_tx_write(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif,
1426 struct ieee80211_sta *sta, struct sk_buff *skb, int *qsel)
1427 {
1428 struct rtw89_sta *rtwsta = sta_to_rtwsta_safe(sta);
1429 struct rtw89_vif *rtwvif = vif_to_rtwvif(vif);
1430 struct rtw89_sta_link *rtwsta_link = NULL;
1431 struct rtw89_vif_link *rtwvif_link;
1432
1433 if (rtwsta) {
1434 rtwsta_link = rtw89_get_designated_link(rtwsta);
1435 if (unlikely(!rtwsta_link)) {
1436 rtw89_err(rtwdev, "tx: find no sta designated link\n");
1437 return -ENOLINK;
1438 }
1439
1440 rtwvif_link = rtwsta_link->rtwvif_link;
1441 } else {
1442 rtwvif_link = rtw89_get_designated_link(rtwvif);
1443 if (unlikely(!rtwvif_link)) {
1444 rtw89_err(rtwdev, "tx: find no vif designated link\n");
1445 return -ENOLINK;
1446 }
1447 }
1448
1449 return rtw89_core_tx_write_link(rtwdev, rtwvif_link, rtwsta_link, skb, qsel, NULL);
1450 }
1451
rtw89_build_txwd_body0(struct rtw89_tx_desc_info * desc_info)1452 static __le32 rtw89_build_txwd_body0(struct rtw89_tx_desc_info *desc_info)
1453 {
1454 u32 dword = FIELD_PREP(RTW89_TXWD_BODY0_WP_OFFSET, desc_info->wp_offset) |
1455 FIELD_PREP(RTW89_TXWD_BODY0_WD_INFO_EN, desc_info->en_wd_info) |
1456 FIELD_PREP(RTW89_TXWD_BODY0_CHANNEL_DMA, desc_info->ch_dma) |
1457 FIELD_PREP(RTW89_TXWD_BODY0_HDR_LLC_LEN, desc_info->hdr_llc_len) |
1458 FIELD_PREP(RTW89_TXWD_BODY0_WD_PAGE, desc_info->wd_page) |
1459 FIELD_PREP(RTW89_TXWD_BODY0_FW_DL, desc_info->fw_dl) |
1460 FIELD_PREP(RTW89_TXWD_BODY0_HW_SSN_SEL, desc_info->hw_ssn_sel) |
1461 FIELD_PREP(RTW89_TXWD_BODY0_HW_SSN_MODE, desc_info->hw_seq_mode);
1462
1463 return cpu_to_le32(dword);
1464 }
1465
rtw89_build_txwd_body0_v1(struct rtw89_tx_desc_info * desc_info)1466 static __le32 rtw89_build_txwd_body0_v1(struct rtw89_tx_desc_info *desc_info)
1467 {
1468 u32 dword = FIELD_PREP(RTW89_TXWD_BODY0_WP_OFFSET_V1, desc_info->wp_offset) |
1469 FIELD_PREP(RTW89_TXWD_BODY0_WD_INFO_EN, desc_info->en_wd_info) |
1470 FIELD_PREP(RTW89_TXWD_BODY0_CHANNEL_DMA, desc_info->ch_dma) |
1471 FIELD_PREP(RTW89_TXWD_BODY0_HDR_LLC_LEN, desc_info->hdr_llc_len) |
1472 FIELD_PREP(RTW89_TXWD_BODY0_WD_PAGE, desc_info->wd_page) |
1473 FIELD_PREP(RTW89_TXWD_BODY0_FW_DL, desc_info->fw_dl);
1474
1475 return cpu_to_le32(dword);
1476 }
1477
rtw89_build_txwd_body1_v1(struct rtw89_tx_desc_info * desc_info)1478 static __le32 rtw89_build_txwd_body1_v1(struct rtw89_tx_desc_info *desc_info)
1479 {
1480 u32 dword = FIELD_PREP(RTW89_TXWD_BODY1_ADDR_INFO_NUM, desc_info->addr_info_nr) |
1481 FIELD_PREP(RTW89_TXWD_BODY1_SEC_KEYID, desc_info->sec_keyid) |
1482 FIELD_PREP(RTW89_TXWD_BODY1_SEC_TYPE, desc_info->sec_type);
1483
1484 return cpu_to_le32(dword);
1485 }
1486
rtw89_build_txwd_body2(struct rtw89_tx_desc_info * desc_info)1487 static __le32 rtw89_build_txwd_body2(struct rtw89_tx_desc_info *desc_info)
1488 {
1489 u32 dword = FIELD_PREP(RTW89_TXWD_BODY2_TID_INDICATE, desc_info->tid_indicate) |
1490 FIELD_PREP(RTW89_TXWD_BODY2_QSEL, desc_info->qsel) |
1491 FIELD_PREP(RTW89_TXWD_BODY2_TXPKT_SIZE, desc_info->pkt_size) |
1492 FIELD_PREP(RTW89_TXWD_BODY2_MACID, desc_info->mac_id);
1493
1494 return cpu_to_le32(dword);
1495 }
1496
rtw89_build_txwd_body3(struct rtw89_tx_desc_info * desc_info)1497 static __le32 rtw89_build_txwd_body3(struct rtw89_tx_desc_info *desc_info)
1498 {
1499 u32 dword = FIELD_PREP(RTW89_TXWD_BODY3_SW_SEQ, desc_info->seq) |
1500 FIELD_PREP(RTW89_TXWD_BODY3_AGG_EN, desc_info->agg_en) |
1501 FIELD_PREP(RTW89_TXWD_BODY3_BK, desc_info->bk);
1502
1503 return cpu_to_le32(dword);
1504 }
1505
rtw89_build_txwd_body4(struct rtw89_tx_desc_info * desc_info)1506 static __le32 rtw89_build_txwd_body4(struct rtw89_tx_desc_info *desc_info)
1507 {
1508 u32 dword = FIELD_PREP(RTW89_TXWD_BODY4_SEC_IV_L0, desc_info->sec_seq[0]) |
1509 FIELD_PREP(RTW89_TXWD_BODY4_SEC_IV_L1, desc_info->sec_seq[1]);
1510
1511 return cpu_to_le32(dword);
1512 }
1513
rtw89_build_txwd_body5(struct rtw89_tx_desc_info * desc_info)1514 static __le32 rtw89_build_txwd_body5(struct rtw89_tx_desc_info *desc_info)
1515 {
1516 u32 dword = FIELD_PREP(RTW89_TXWD_BODY5_SEC_IV_H2, desc_info->sec_seq[2]) |
1517 FIELD_PREP(RTW89_TXWD_BODY5_SEC_IV_H3, desc_info->sec_seq[3]) |
1518 FIELD_PREP(RTW89_TXWD_BODY5_SEC_IV_H4, desc_info->sec_seq[4]) |
1519 FIELD_PREP(RTW89_TXWD_BODY5_SEC_IV_H5, desc_info->sec_seq[5]);
1520
1521 return cpu_to_le32(dword);
1522 }
1523
rtw89_build_txwd_body7_v1(struct rtw89_tx_desc_info * desc_info)1524 static __le32 rtw89_build_txwd_body7_v1(struct rtw89_tx_desc_info *desc_info)
1525 {
1526 u32 dword = FIELD_PREP(RTW89_TXWD_BODY7_USE_RATE_V1, desc_info->use_rate) |
1527 FIELD_PREP(RTW89_TXWD_BODY7_DATA_BW, desc_info->data_bw) |
1528 FIELD_PREP(RTW89_TXWD_BODY7_GI_LTF, desc_info->gi_ltf) |
1529 FIELD_PREP(RTW89_TXWD_BODY7_DATA_RATE, desc_info->data_rate);
1530
1531 return cpu_to_le32(dword);
1532 }
1533
rtw89_build_txwd_info0(struct rtw89_tx_desc_info * desc_info)1534 static __le32 rtw89_build_txwd_info0(struct rtw89_tx_desc_info *desc_info)
1535 {
1536 u32 dword = FIELD_PREP(RTW89_TXWD_INFO0_USE_RATE, desc_info->use_rate) |
1537 FIELD_PREP(RTW89_TXWD_INFO0_DATA_BW, desc_info->data_bw) |
1538 FIELD_PREP(RTW89_TXWD_INFO0_GI_LTF, desc_info->gi_ltf) |
1539 FIELD_PREP(RTW89_TXWD_INFO0_DATA_RATE, desc_info->data_rate) |
1540 FIELD_PREP(RTW89_TXWD_INFO0_DATA_STBC, desc_info->stbc) |
1541 FIELD_PREP(RTW89_TXWD_INFO0_DATA_LDPC, desc_info->ldpc) |
1542 FIELD_PREP(RTW89_TXWD_INFO0_DISDATAFB, desc_info->dis_data_fb) |
1543 FIELD_PREP(RTW89_TXWD_INFO0_MULTIPORT_ID, desc_info->port);
1544
1545 return cpu_to_le32(dword);
1546 }
1547
rtw89_build_txwd_info0_v1(struct rtw89_tx_desc_info * desc_info)1548 static __le32 rtw89_build_txwd_info0_v1(struct rtw89_tx_desc_info *desc_info)
1549 {
1550 u32 dword = FIELD_PREP(RTW89_TXWD_INFO0_DATA_STBC, desc_info->stbc) |
1551 FIELD_PREP(RTW89_TXWD_INFO0_DATA_LDPC, desc_info->ldpc) |
1552 FIELD_PREP(RTW89_TXWD_INFO0_DISDATAFB, desc_info->dis_data_fb) |
1553 FIELD_PREP(RTW89_TXWD_INFO0_MULTIPORT_ID, desc_info->port) |
1554 FIELD_PREP(RTW89_TXWD_INFO0_DATA_ER, desc_info->er_cap) |
1555 FIELD_PREP(RTW89_TXWD_INFO0_DATA_BW_ER, 0);
1556
1557 return cpu_to_le32(dword);
1558 }
1559
rtw89_build_txwd_info1(struct rtw89_tx_desc_info * desc_info)1560 static __le32 rtw89_build_txwd_info1(struct rtw89_tx_desc_info *desc_info)
1561 {
1562 u32 dword = FIELD_PREP(RTW89_TXWD_INFO1_MAX_AGGNUM, desc_info->ampdu_num) |
1563 FIELD_PREP(RTW89_TXWD_INFO1_A_CTRL_BSR, desc_info->a_ctrl_bsr) |
1564 FIELD_PREP(RTW89_TXWD_INFO1_DATA_RTY_LOWEST_RATE,
1565 desc_info->data_retry_lowest_rate) |
1566 FIELD_PREP(RTW89_TXWD_INFO1_DATA_TXCNT_LMT_SEL,
1567 desc_info->tx_cnt_lmt_en) |
1568 FIELD_PREP(RTW89_TXWD_INFO1_DATA_TXCNT_LMT, desc_info->tx_cnt_lmt);
1569
1570 return cpu_to_le32(dword);
1571 }
1572
rtw89_build_txwd_info2(struct rtw89_tx_desc_info * desc_info)1573 static __le32 rtw89_build_txwd_info2(struct rtw89_tx_desc_info *desc_info)
1574 {
1575 u32 dword = FIELD_PREP(RTW89_TXWD_INFO2_AMPDU_DENSITY, desc_info->ampdu_density) |
1576 FIELD_PREP(RTW89_TXWD_INFO2_SEC_TYPE, desc_info->sec_type) |
1577 FIELD_PREP(RTW89_TXWD_INFO2_SEC_HW_ENC, desc_info->sec_en) |
1578 FIELD_PREP(RTW89_TXWD_INFO2_SEC_CAM_IDX, desc_info->sec_cam_idx);
1579
1580 return cpu_to_le32(dword);
1581 }
1582
rtw89_build_txwd_info2_v1(struct rtw89_tx_desc_info * desc_info)1583 static __le32 rtw89_build_txwd_info2_v1(struct rtw89_tx_desc_info *desc_info)
1584 {
1585 u32 dword = FIELD_PREP(RTW89_TXWD_INFO2_AMPDU_DENSITY, desc_info->ampdu_density) |
1586 FIELD_PREP(RTW89_TXWD_INFO2_FORCE_KEY_EN, desc_info->sec_en) |
1587 FIELD_PREP(RTW89_TXWD_INFO2_SEC_CAM_IDX, desc_info->sec_cam_idx);
1588
1589 return cpu_to_le32(dword);
1590 }
1591
rtw89_build_txwd_info3(struct rtw89_tx_desc_info * desc_info)1592 static __le32 rtw89_build_txwd_info3(struct rtw89_tx_desc_info *desc_info)
1593 {
1594 u32 dword = FIELD_PREP(RTW89_TXWD_INFO3_SPE_RPT, desc_info->report);
1595
1596 return cpu_to_le32(dword);
1597 }
1598
rtw89_build_txwd_info4(struct rtw89_tx_desc_info * desc_info)1599 static __le32 rtw89_build_txwd_info4(struct rtw89_tx_desc_info *desc_info)
1600 {
1601 bool rts_en = !desc_info->is_bmc;
1602 u32 dword = FIELD_PREP(RTW89_TXWD_INFO4_RTS_EN, rts_en) |
1603 FIELD_PREP(RTW89_TXWD_INFO4_HW_RTS_EN, 1) |
1604 FIELD_PREP(RTW89_TXWD_INFO4_SW_DEFINE, desc_info->sn);
1605
1606 return cpu_to_le32(dword);
1607 }
1608
rtw89_core_fill_txdesc(struct rtw89_dev * rtwdev,struct rtw89_tx_desc_info * desc_info,void * txdesc)1609 void rtw89_core_fill_txdesc(struct rtw89_dev *rtwdev,
1610 struct rtw89_tx_desc_info *desc_info,
1611 void *txdesc)
1612 {
1613 struct rtw89_txwd_body *txwd_body = (struct rtw89_txwd_body *)txdesc;
1614 struct rtw89_txwd_info *txwd_info;
1615
1616 txwd_body->dword0 = rtw89_build_txwd_body0(desc_info);
1617 txwd_body->dword2 = rtw89_build_txwd_body2(desc_info);
1618 txwd_body->dword3 = rtw89_build_txwd_body3(desc_info);
1619
1620 if (!desc_info->en_wd_info)
1621 return;
1622
1623 txwd_info = (struct rtw89_txwd_info *)(txwd_body + 1);
1624 txwd_info->dword0 = rtw89_build_txwd_info0(desc_info);
1625 txwd_info->dword1 = rtw89_build_txwd_info1(desc_info);
1626 txwd_info->dword2 = rtw89_build_txwd_info2(desc_info);
1627 txwd_info->dword3 = rtw89_build_txwd_info3(desc_info);
1628 txwd_info->dword4 = rtw89_build_txwd_info4(desc_info);
1629
1630 }
1631 EXPORT_SYMBOL(rtw89_core_fill_txdesc);
1632
rtw89_core_fill_txdesc_v1(struct rtw89_dev * rtwdev,struct rtw89_tx_desc_info * desc_info,void * txdesc)1633 void rtw89_core_fill_txdesc_v1(struct rtw89_dev *rtwdev,
1634 struct rtw89_tx_desc_info *desc_info,
1635 void *txdesc)
1636 {
1637 struct rtw89_txwd_body_v1 *txwd_body = (struct rtw89_txwd_body_v1 *)txdesc;
1638 struct rtw89_txwd_info *txwd_info;
1639
1640 txwd_body->dword0 = rtw89_build_txwd_body0_v1(desc_info);
1641 txwd_body->dword1 = rtw89_build_txwd_body1_v1(desc_info);
1642 txwd_body->dword2 = rtw89_build_txwd_body2(desc_info);
1643 txwd_body->dword3 = rtw89_build_txwd_body3(desc_info);
1644 if (desc_info->sec_en) {
1645 txwd_body->dword4 = rtw89_build_txwd_body4(desc_info);
1646 txwd_body->dword5 = rtw89_build_txwd_body5(desc_info);
1647 }
1648 txwd_body->dword7 = rtw89_build_txwd_body7_v1(desc_info);
1649
1650 if (!desc_info->en_wd_info)
1651 return;
1652
1653 txwd_info = (struct rtw89_txwd_info *)(txwd_body + 1);
1654 txwd_info->dword0 = rtw89_build_txwd_info0_v1(desc_info);
1655 txwd_info->dword1 = rtw89_build_txwd_info1(desc_info);
1656 txwd_info->dword2 = rtw89_build_txwd_info2_v1(desc_info);
1657 txwd_info->dword3 = rtw89_build_txwd_info3(desc_info);
1658 txwd_info->dword4 = rtw89_build_txwd_info4(desc_info);
1659 }
1660 EXPORT_SYMBOL(rtw89_core_fill_txdesc_v1);
1661
rtw89_build_txwd_body0_v2(struct rtw89_tx_desc_info * desc_info)1662 static __le32 rtw89_build_txwd_body0_v2(struct rtw89_tx_desc_info *desc_info)
1663 {
1664 u32 dword = FIELD_PREP(BE_TXD_BODY0_WP_OFFSET_V1, desc_info->wp_offset) |
1665 FIELD_PREP(BE_TXD_BODY0_WDINFO_EN, desc_info->en_wd_info) |
1666 FIELD_PREP(BE_TXD_BODY0_CH_DMA, desc_info->ch_dma) |
1667 FIELD_PREP(BE_TXD_BODY0_HDR_LLC_LEN, desc_info->hdr_llc_len) |
1668 FIELD_PREP(BE_TXD_BODY0_WD_PAGE, desc_info->wd_page);
1669
1670 return cpu_to_le32(dword);
1671 }
1672
rtw89_build_txwd_body1_v2(struct rtw89_tx_desc_info * desc_info)1673 static __le32 rtw89_build_txwd_body1_v2(struct rtw89_tx_desc_info *desc_info)
1674 {
1675 u32 dword = FIELD_PREP(BE_TXD_BODY1_ADDR_INFO_NUM, desc_info->addr_info_nr) |
1676 FIELD_PREP(BE_TXD_BODY1_SEC_KEYID, desc_info->sec_keyid) |
1677 FIELD_PREP(BE_TXD_BODY1_SEC_TYPE, desc_info->sec_type);
1678
1679 return cpu_to_le32(dword);
1680 }
1681
rtw89_build_txwd_body2_v2(struct rtw89_tx_desc_info * desc_info)1682 static __le32 rtw89_build_txwd_body2_v2(struct rtw89_tx_desc_info *desc_info)
1683 {
1684 u32 dword = FIELD_PREP(BE_TXD_BODY2_TID_IND, desc_info->tid_indicate) |
1685 FIELD_PREP(BE_TXD_BODY2_QSEL, desc_info->qsel) |
1686 FIELD_PREP(BE_TXD_BODY2_TXPKTSIZE, desc_info->pkt_size) |
1687 FIELD_PREP(BE_TXD_BODY2_AGG_EN, desc_info->agg_en) |
1688 FIELD_PREP(BE_TXD_BODY2_BK, desc_info->bk) |
1689 FIELD_PREP(BE_TXD_BODY2_MACID, desc_info->mac_id);
1690
1691 return cpu_to_le32(dword);
1692 }
1693
rtw89_build_txwd_body2_v3(struct rtw89_tx_desc_info * desc_info)1694 static __le32 rtw89_build_txwd_body2_v3(struct rtw89_tx_desc_info *desc_info)
1695 {
1696 u32 dword = FIELD_PREP(BE_TXD_BODY2_TID_IND_V1, desc_info->tid_indicate) |
1697 FIELD_PREP(BE_TXD_BODY2_QSEL_V1, desc_info->qsel) |
1698 FIELD_PREP(BE_TXD_BODY2_TXPKTSIZE, desc_info->pkt_size) |
1699 FIELD_PREP(BE_TXD_BODY2_AGG_EN, desc_info->agg_en) |
1700 FIELD_PREP(BE_TXD_BODY2_MACID_V1, desc_info->mac_id);
1701
1702 return cpu_to_le32(dword);
1703 }
1704
rtw89_build_txwd_body3_v2(struct rtw89_tx_desc_info * desc_info)1705 static __le32 rtw89_build_txwd_body3_v2(struct rtw89_tx_desc_info *desc_info)
1706 {
1707 u32 dword = FIELD_PREP(BE_TXD_BODY3_WIFI_SEQ, desc_info->seq) |
1708 FIELD_PREP(BE_TXD_BODY3_MLO_FLAG, desc_info->mlo) |
1709 FIELD_PREP(BE_TXD_BODY3_IS_MLD_SW_EN, desc_info->sw_mld);
1710
1711 return cpu_to_le32(dword);
1712 }
1713
rtw89_build_txwd_body3_v3(struct rtw89_tx_desc_info * desc_info)1714 static __le32 rtw89_build_txwd_body3_v3(struct rtw89_tx_desc_info *desc_info)
1715 {
1716 u32 dword = FIELD_PREP(BE_TXD_BODY3_WIFI_SEQ, desc_info->seq) |
1717 FIELD_PREP(BE_TXD_BODY3_MLO_FLAG, desc_info->mlo) |
1718 FIELD_PREP(BE_TXD_BODY3_IS_MLD_SW_EN, desc_info->sw_mld) |
1719 FIELD_PREP(BE_TXD_BODY3_BK_V1, desc_info->bk);
1720
1721 return cpu_to_le32(dword);
1722 }
1723
rtw89_build_txwd_body4_v2(struct rtw89_tx_desc_info * desc_info)1724 static __le32 rtw89_build_txwd_body4_v2(struct rtw89_tx_desc_info *desc_info)
1725 {
1726 u32 dword = FIELD_PREP(BE_TXD_BODY4_SEC_IV_L0, desc_info->sec_seq[0]) |
1727 FIELD_PREP(BE_TXD_BODY4_SEC_IV_L1, desc_info->sec_seq[1]);
1728
1729 return cpu_to_le32(dword);
1730 }
1731
rtw89_build_txwd_body5_v2(struct rtw89_tx_desc_info * desc_info)1732 static __le32 rtw89_build_txwd_body5_v2(struct rtw89_tx_desc_info *desc_info)
1733 {
1734 u32 dword = FIELD_PREP(BE_TXD_BODY5_SEC_IV_H2, desc_info->sec_seq[2]) |
1735 FIELD_PREP(BE_TXD_BODY5_SEC_IV_H3, desc_info->sec_seq[3]) |
1736 FIELD_PREP(BE_TXD_BODY5_SEC_IV_H4, desc_info->sec_seq[4]) |
1737 FIELD_PREP(BE_TXD_BODY5_SEC_IV_H5, desc_info->sec_seq[5]);
1738
1739 return cpu_to_le32(dword);
1740 }
1741
rtw89_build_txwd_body6_v2(struct rtw89_tx_desc_info * desc_info)1742 static __le32 rtw89_build_txwd_body6_v2(struct rtw89_tx_desc_info *desc_info)
1743 {
1744 u32 dword = FIELD_PREP(BE_TXD_BODY6_UPD_WLAN_HDR, desc_info->upd_wlan_hdr);
1745
1746 return cpu_to_le32(dword);
1747 }
1748
rtw89_build_txwd_body7_v2(struct rtw89_tx_desc_info * desc_info)1749 static __le32 rtw89_build_txwd_body7_v2(struct rtw89_tx_desc_info *desc_info)
1750 {
1751 u32 dword = FIELD_PREP(BE_TXD_BODY7_USERATE_SEL, desc_info->use_rate) |
1752 FIELD_PREP(BE_TXD_BODY7_DATA_BW, desc_info->data_bw) |
1753 FIELD_PREP(BE_TXD_BODY7_GI_LTF, desc_info->gi_ltf) |
1754 FIELD_PREP(BE_TXD_BODY7_DATA_ER, desc_info->er_cap) |
1755 FIELD_PREP(BE_TXD_BODY7_DATA_BW_ER, 0) |
1756 FIELD_PREP(BE_TXD_BODY7_DATARATE, desc_info->data_rate);
1757
1758 return cpu_to_le32(dword);
1759 }
1760
rtw89_build_txwd_info0_v2(struct rtw89_tx_desc_info * desc_info)1761 static __le32 rtw89_build_txwd_info0_v2(struct rtw89_tx_desc_info *desc_info)
1762 {
1763 u32 dword = FIELD_PREP(BE_TXD_INFO0_DATA_STBC, desc_info->stbc) |
1764 FIELD_PREP(BE_TXD_INFO0_DATA_LDPC, desc_info->ldpc) |
1765 FIELD_PREP(BE_TXD_INFO0_DISDATAFB, desc_info->dis_data_fb) |
1766 FIELD_PREP(BE_TXD_INFO0_MULTIPORT_ID, desc_info->port) |
1767 FIELD_PREP(BE_TXD_INFO0_DATA_TXCNT_LMT_SEL,
1768 desc_info->tx_cnt_lmt_en) |
1769 FIELD_PREP(BE_TXD_INFO0_DATA_TXCNT_LMT, desc_info->tx_cnt_lmt);
1770
1771 return cpu_to_le32(dword);
1772 }
1773
rtw89_build_txwd_info1_v2(struct rtw89_tx_desc_info * desc_info)1774 static __le32 rtw89_build_txwd_info1_v2(struct rtw89_tx_desc_info *desc_info)
1775 {
1776 u32 dword = FIELD_PREP(BE_TXD_INFO1_MAX_AGG_NUM, desc_info->ampdu_num) |
1777 FIELD_PREP(BE_TXD_INFO1_A_CTRL_BSR, desc_info->a_ctrl_bsr) |
1778 FIELD_PREP(BE_TXD_INFO1_DATA_RTY_LOWEST_RATE,
1779 desc_info->data_retry_lowest_rate) |
1780 FIELD_PREP(BE_TXD_INFO1_SW_DEFINE, desc_info->sn);
1781
1782 return cpu_to_le32(dword);
1783 }
1784
rtw89_build_txwd_info2_v2(struct rtw89_tx_desc_info * desc_info)1785 static __le32 rtw89_build_txwd_info2_v2(struct rtw89_tx_desc_info *desc_info)
1786 {
1787 u32 dword = FIELD_PREP(BE_TXD_INFO2_AMPDU_DENSITY, desc_info->ampdu_density) |
1788 FIELD_PREP(BE_TXD_INFO2_FORCE_KEY_EN, desc_info->sec_en) |
1789 FIELD_PREP(BE_TXD_INFO2_SEC_CAM_IDX, desc_info->sec_cam_idx) |
1790 FIELD_PREP(BE_TXD_INFO2_SPE_RPT_V1, desc_info->report);
1791
1792 return cpu_to_le32(dword);
1793 }
1794
rtw89_build_txwd_info2_v3(struct rtw89_tx_desc_info * desc_info)1795 static __le32 rtw89_build_txwd_info2_v3(struct rtw89_tx_desc_info *desc_info)
1796 {
1797 u32 dword = FIELD_PREP(BE_TXD_INFO2_AMPDU_DENSITY, desc_info->ampdu_density) |
1798 FIELD_PREP(BE_TXD_INFO2_FORCE_KEY_EN_V1, desc_info->sec_en) |
1799 FIELD_PREP(BE_TXD_INFO2_SEC_CAM_IDX_V1, desc_info->sec_cam_idx);
1800
1801 return cpu_to_le32(dword);
1802 }
1803
rtw89_build_txwd_info4_v2(struct rtw89_tx_desc_info * desc_info)1804 static __le32 rtw89_build_txwd_info4_v2(struct rtw89_tx_desc_info *desc_info)
1805 {
1806 bool rts_en = !desc_info->is_bmc;
1807 u32 dword = FIELD_PREP(BE_TXD_INFO4_RTS_EN, rts_en) |
1808 FIELD_PREP(BE_TXD_INFO4_HW_RTS_EN, 1);
1809
1810 return cpu_to_le32(dword);
1811 }
1812
rtw89_core_fill_txdesc_v2(struct rtw89_dev * rtwdev,struct rtw89_tx_desc_info * desc_info,void * txdesc)1813 void rtw89_core_fill_txdesc_v2(struct rtw89_dev *rtwdev,
1814 struct rtw89_tx_desc_info *desc_info,
1815 void *txdesc)
1816 {
1817 struct rtw89_txwd_body_v2 *txwd_body = txdesc;
1818 struct rtw89_txwd_info_v2 *txwd_info;
1819
1820 txwd_body->dword0 = rtw89_build_txwd_body0_v2(desc_info);
1821 txwd_body->dword1 = rtw89_build_txwd_body1_v2(desc_info);
1822 txwd_body->dword2 = rtw89_build_txwd_body2_v2(desc_info);
1823 txwd_body->dword3 = rtw89_build_txwd_body3_v2(desc_info);
1824 if (desc_info->sec_en) {
1825 txwd_body->dword4 = rtw89_build_txwd_body4_v2(desc_info);
1826 txwd_body->dword5 = rtw89_build_txwd_body5_v2(desc_info);
1827 }
1828 txwd_body->dword6 = rtw89_build_txwd_body6_v2(desc_info);
1829 txwd_body->dword7 = rtw89_build_txwd_body7_v2(desc_info);
1830
1831 if (!desc_info->en_wd_info)
1832 return;
1833
1834 txwd_info = (struct rtw89_txwd_info_v2 *)(txwd_body + 1);
1835 txwd_info->dword0 = rtw89_build_txwd_info0_v2(desc_info);
1836 txwd_info->dword1 = rtw89_build_txwd_info1_v2(desc_info);
1837 txwd_info->dword2 = rtw89_build_txwd_info2_v2(desc_info);
1838 txwd_info->dword4 = rtw89_build_txwd_info4_v2(desc_info);
1839 }
1840 EXPORT_SYMBOL(rtw89_core_fill_txdesc_v2);
1841
rtw89_core_fill_txdesc_v3(struct rtw89_dev * rtwdev,struct rtw89_tx_desc_info * desc_info,void * txdesc)1842 void rtw89_core_fill_txdesc_v3(struct rtw89_dev *rtwdev,
1843 struct rtw89_tx_desc_info *desc_info,
1844 void *txdesc)
1845 {
1846 struct rtw89_txwd_body_v2 *txwd_body = txdesc;
1847 struct rtw89_txwd_info_v2 *txwd_info;
1848
1849 txwd_body->dword0 = rtw89_build_txwd_body0_v2(desc_info);
1850 txwd_body->dword1 = rtw89_build_txwd_body1_v2(desc_info);
1851 txwd_body->dword2 = rtw89_build_txwd_body2_v3(desc_info);
1852 txwd_body->dword3 = rtw89_build_txwd_body3_v3(desc_info);
1853 if (desc_info->sec_en) {
1854 txwd_body->dword4 = rtw89_build_txwd_body4_v2(desc_info);
1855 txwd_body->dword5 = rtw89_build_txwd_body5_v2(desc_info);
1856 }
1857 txwd_body->dword6 = rtw89_build_txwd_body6_v2(desc_info);
1858 txwd_body->dword7 = rtw89_build_txwd_body7_v2(desc_info);
1859
1860 if (!desc_info->en_wd_info)
1861 return;
1862
1863 txwd_info = (struct rtw89_txwd_info_v2 *)(txwd_body + 1);
1864 txwd_info->dword0 = rtw89_build_txwd_info0_v2(desc_info);
1865 txwd_info->dword1 = rtw89_build_txwd_info1_v2(desc_info);
1866 txwd_info->dword2 = rtw89_build_txwd_info2_v3(desc_info);
1867 txwd_info->dword4 = rtw89_build_txwd_info4_v2(desc_info);
1868 }
1869 EXPORT_SYMBOL(rtw89_core_fill_txdesc_v3);
1870
rtw89_build_txwd_fwcmd0_v1(struct rtw89_tx_desc_info * desc_info)1871 static __le32 rtw89_build_txwd_fwcmd0_v1(struct rtw89_tx_desc_info *desc_info)
1872 {
1873 u32 dword = FIELD_PREP(AX_RXD_RPKT_LEN_MASK, desc_info->pkt_size) |
1874 FIELD_PREP(AX_RXD_RPKT_TYPE_MASK, desc_info->fw_dl ?
1875 RTW89_CORE_RX_TYPE_FWDL :
1876 RTW89_CORE_RX_TYPE_H2C);
1877
1878 return cpu_to_le32(dword);
1879 }
1880
rtw89_core_fill_txdesc_fwcmd_v1(struct rtw89_dev * rtwdev,struct rtw89_tx_desc_info * desc_info,void * txdesc)1881 void rtw89_core_fill_txdesc_fwcmd_v1(struct rtw89_dev *rtwdev,
1882 struct rtw89_tx_desc_info *desc_info,
1883 void *txdesc)
1884 {
1885 struct rtw89_rxdesc_short *txwd_v1 = (struct rtw89_rxdesc_short *)txdesc;
1886
1887 txwd_v1->dword0 = rtw89_build_txwd_fwcmd0_v1(desc_info);
1888 }
1889 EXPORT_SYMBOL(rtw89_core_fill_txdesc_fwcmd_v1);
1890
rtw89_build_txwd_fwcmd0_v2(struct rtw89_tx_desc_info * desc_info)1891 static __le32 rtw89_build_txwd_fwcmd0_v2(struct rtw89_tx_desc_info *desc_info)
1892 {
1893 u32 dword = FIELD_PREP(BE_RXD_RPKT_LEN_MASK, desc_info->pkt_size) |
1894 FIELD_PREP(BE_RXD_RPKT_TYPE_MASK, desc_info->fw_dl ?
1895 RTW89_CORE_RX_TYPE_FWDL :
1896 RTW89_CORE_RX_TYPE_H2C);
1897
1898 return cpu_to_le32(dword);
1899 }
1900
rtw89_core_fill_txdesc_fwcmd_v2(struct rtw89_dev * rtwdev,struct rtw89_tx_desc_info * desc_info,void * txdesc)1901 void rtw89_core_fill_txdesc_fwcmd_v2(struct rtw89_dev *rtwdev,
1902 struct rtw89_tx_desc_info *desc_info,
1903 void *txdesc)
1904 {
1905 struct rtw89_rxdesc_short_v2 *txwd_v2 = (struct rtw89_rxdesc_short_v2 *)txdesc;
1906
1907 txwd_v2->dword0 = rtw89_build_txwd_fwcmd0_v2(desc_info);
1908 }
1909 EXPORT_SYMBOL(rtw89_core_fill_txdesc_fwcmd_v2);
1910
rtw89_core_rx_process_mac_ppdu(struct rtw89_dev * rtwdev,struct sk_buff * skb,struct rtw89_rx_phy_ppdu * phy_ppdu)1911 static int rtw89_core_rx_process_mac_ppdu(struct rtw89_dev *rtwdev,
1912 struct sk_buff *skb,
1913 struct rtw89_rx_phy_ppdu *phy_ppdu)
1914 {
1915 const struct rtw89_chip_info *chip = rtwdev->chip;
1916 const struct rtw89_rxinfo *rxinfo = (const struct rtw89_rxinfo *)skb->data;
1917 const struct rtw89_rxinfo_user *user;
1918 enum rtw89_chip_gen chip_gen = rtwdev->chip->chip_gen;
1919 int rx_cnt_size = RTW89_PPDU_MAC_RX_CNT_SIZE;
1920 bool rx_cnt_valid = false;
1921 bool invalid = false;
1922 u8 plcp_size = 0;
1923 u8 *phy_sts;
1924 u8 usr_num;
1925 int i;
1926
1927 if (chip_gen == RTW89_CHIP_BE) {
1928 invalid = le32_get_bits(rxinfo->w0, RTW89_RXINFO_W0_INVALID_V1);
1929 rx_cnt_size = RTW89_PPDU_MAC_RX_CNT_SIZE_V1;
1930 }
1931
1932 if (invalid)
1933 return -EINVAL;
1934
1935 rx_cnt_valid = le32_get_bits(rxinfo->w0, RTW89_RXINFO_W0_RX_CNT_VLD);
1936 if (chip_gen == RTW89_CHIP_BE) {
1937 plcp_size = le32_get_bits(rxinfo->w0, RTW89_RXINFO_W0_PLCP_LEN_V1) << 3;
1938 usr_num = le32_get_bits(rxinfo->w0, RTW89_RXINFO_W0_USR_NUM_V1);
1939 } else {
1940 plcp_size = le32_get_bits(rxinfo->w1, RTW89_RXINFO_W1_PLCP_LEN) << 3;
1941 usr_num = le32_get_bits(rxinfo->w0, RTW89_RXINFO_W0_USR_NUM);
1942 }
1943 if (usr_num > chip->ppdu_max_usr) {
1944 rtw89_warn(rtwdev, "Invalid user number (%d) in mac info\n",
1945 usr_num);
1946 return -EINVAL;
1947 }
1948
1949 for (i = 0; i < usr_num; i++) {
1950 user = &rxinfo->user[i];
1951 if (!le32_get_bits(user->w0, RTW89_RXINFO_USER_MAC_ID_VALID))
1952 continue;
1953 /* For WiFi 7 chips, RXWD.mac_id of PPDU status is not set
1954 * by hardware, so update mac_id by rxinfo_user[].mac_id.
1955 */
1956 if (chip->chip_id == RTL8922A)
1957 phy_ppdu->mac_id =
1958 le32_get_bits(user->w0, RTW89_RXINFO_USER_MACID);
1959 else if (chip->chip_id == RTL8922D)
1960 phy_ppdu->mac_id =
1961 le32_get_bits(user->w0, RTW89_RXINFO_USER_MACID_V1);
1962
1963 phy_ppdu->has_data =
1964 le32_get_bits(user->w0, RTW89_RXINFO_USER_DATA);
1965 phy_ppdu->has_bcn =
1966 le32_get_bits(user->w0, RTW89_RXINFO_USER_BCN);
1967 break;
1968 }
1969
1970 phy_sts = skb->data + RTW89_PPDU_MAC_INFO_SIZE;
1971 phy_sts += usr_num * RTW89_PPDU_MAC_INFO_USR_SIZE;
1972 /* 8-byte alignment */
1973 if (usr_num & BIT(0))
1974 phy_sts += RTW89_PPDU_MAC_INFO_USR_SIZE;
1975 if (rx_cnt_valid)
1976 phy_sts += rx_cnt_size;
1977 phy_sts += plcp_size;
1978
1979 if (phy_sts > skb->data + skb->len)
1980 return -EINVAL;
1981
1982 phy_ppdu->buf = phy_sts;
1983 phy_ppdu->len = skb->data + skb->len - phy_sts;
1984
1985 return 0;
1986 }
1987
rtw89_get_data_rate_nss(struct rtw89_dev * rtwdev,u16 data_rate)1988 static u8 rtw89_get_data_rate_nss(struct rtw89_dev *rtwdev, u16 data_rate)
1989 {
1990 u8 data_rate_mode;
1991
1992 data_rate_mode = rtw89_get_data_rate_mode(rtwdev, data_rate);
1993 switch (data_rate_mode) {
1994 case DATA_RATE_MODE_NON_HT:
1995 return 1;
1996 case DATA_RATE_MODE_HT:
1997 return rtw89_get_data_ht_nss(rtwdev, data_rate) + 1;
1998 case DATA_RATE_MODE_VHT:
1999 case DATA_RATE_MODE_HE:
2000 case DATA_RATE_MODE_EHT:
2001 return rtw89_get_data_nss(rtwdev, data_rate) + 1;
2002 default:
2003 rtw89_warn(rtwdev, "invalid RX rate mode %d\n", data_rate_mode);
2004 return 0;
2005 }
2006 }
2007
rtw89_core_rx_process_phy_ppdu_iter(void * data,struct ieee80211_sta * sta)2008 static void rtw89_core_rx_process_phy_ppdu_iter(void *data,
2009 struct ieee80211_sta *sta)
2010 {
2011 struct rtw89_rx_phy_ppdu *phy_ppdu = (struct rtw89_rx_phy_ppdu *)data;
2012 struct rtw89_sta *rtwsta = sta_to_rtwsta(sta);
2013 struct rtw89_dev *rtwdev = rtwsta->rtwdev;
2014 struct rtw89_hal *hal = &rtwdev->hal;
2015 struct rtw89_sta_link *rtwsta_link;
2016 u8 ant_num = hal->ant_diversity ? 2 : rtwdev->chip->rf_path_num;
2017 u8 ant_pos = U8_MAX;
2018 u8 evm_pos = 0;
2019 int i;
2020
2021 rtwsta_link = rtw89_sta_get_link_inst(rtwsta, phy_ppdu->phy_idx);
2022 if (unlikely(!rtwsta_link))
2023 return;
2024
2025 if (rtwsta_link->mac_id != phy_ppdu->mac_id || !phy_ppdu->to_self)
2026 return;
2027
2028 if (hal->ant_diversity && hal->antenna_rx) {
2029 ant_pos = __ffs(hal->antenna_rx);
2030 evm_pos = ant_pos;
2031 }
2032
2033 ewma_rssi_add(&rtwsta_link->avg_rssi, phy_ppdu->rssi_avg);
2034
2035 if (ant_pos < ant_num) {
2036 ewma_rssi_add(&rtwsta_link->rssi[ant_pos], phy_ppdu->rssi[0]);
2037 } else {
2038 for (i = 0; i < rtwdev->chip->rf_path_num; i++)
2039 ewma_rssi_add(&rtwsta_link->rssi[i], phy_ppdu->rssi[i]);
2040 }
2041
2042 if (phy_ppdu->ofdm.has && (phy_ppdu->has_data || phy_ppdu->has_bcn)) {
2043 ewma_snr_add(&rtwsta_link->avg_snr, phy_ppdu->ofdm.avg_snr);
2044 if (rtw89_get_data_rate_nss(rtwdev, phy_ppdu->rate) == 1) {
2045 ewma_evm_add(&rtwsta_link->evm_1ss, phy_ppdu->ofdm.evm_min);
2046 } else {
2047 ewma_evm_add(&rtwsta_link->evm_min[evm_pos],
2048 phy_ppdu->ofdm.evm_min);
2049 ewma_evm_add(&rtwsta_link->evm_max[evm_pos],
2050 phy_ppdu->ofdm.evm_max);
2051 }
2052 }
2053 }
2054
2055 #define VAR_LEN 0xff
2056 #define VAR_LEN_UNIT 8
rtw89_core_get_phy_status_ie_len(struct rtw89_dev * rtwdev,const struct rtw89_phy_sts_iehdr * iehdr)2057 static u16 rtw89_core_get_phy_status_ie_len(struct rtw89_dev *rtwdev,
2058 const struct rtw89_phy_sts_iehdr *iehdr)
2059 {
2060 static const u8 physts_ie_len_tabs[RTW89_CHIP_GEN_NUM][32] = {
2061 [RTW89_CHIP_AX] = {
2062 16, 32, 24, 24, 8, 8, 8, 8, VAR_LEN, 8, VAR_LEN, 176, VAR_LEN,
2063 VAR_LEN, VAR_LEN, VAR_LEN, VAR_LEN, VAR_LEN, 16, 24, VAR_LEN,
2064 VAR_LEN, VAR_LEN, 0, 24, 24, 24, 24, 32, 32, 32, 32
2065 },
2066 [RTW89_CHIP_BE] = {
2067 32, 40, 24, 24, 8, 8, 8, 8, VAR_LEN, 8, VAR_LEN, 176, VAR_LEN,
2068 VAR_LEN, VAR_LEN, VAR_LEN, VAR_LEN, VAR_LEN, 88, 56, VAR_LEN,
2069 VAR_LEN, VAR_LEN, 0, 24, 24, 24, 24, 32, 32, 32, 32
2070 },
2071 };
2072 const u8 *physts_ie_len_tab;
2073 u16 ie_len;
2074 u8 ie;
2075
2076 physts_ie_len_tab = physts_ie_len_tabs[rtwdev->chip->chip_gen];
2077
2078 ie = le32_get_bits(iehdr->w0, RTW89_PHY_STS_IEHDR_TYPE);
2079 if (physts_ie_len_tab[ie] != VAR_LEN)
2080 ie_len = physts_ie_len_tab[ie];
2081 else
2082 ie_len = le32_get_bits(iehdr->w0, RTW89_PHY_STS_IEHDR_LEN) * VAR_LEN_UNIT;
2083
2084 return ie_len;
2085 }
2086
rtw89_core_parse_phy_status_ie01_v2(struct rtw89_dev * rtwdev,const struct rtw89_phy_sts_iehdr * iehdr,struct rtw89_rx_phy_ppdu * phy_ppdu)2087 static void rtw89_core_parse_phy_status_ie01_v2(struct rtw89_dev *rtwdev,
2088 const struct rtw89_phy_sts_iehdr *iehdr,
2089 struct rtw89_rx_phy_ppdu *phy_ppdu)
2090 {
2091 const struct rtw89_phy_sts_ie01_v2 *ie;
2092 u8 *rpl_fd = phy_ppdu->rpl_fd;
2093
2094 ie = (const struct rtw89_phy_sts_ie01_v2 *)iehdr;
2095 rpl_fd[RF_PATH_A] = le32_get_bits(ie->w8, RTW89_PHY_STS_IE01_V2_W8_RPL_FD_A);
2096 rpl_fd[RF_PATH_B] = le32_get_bits(ie->w8, RTW89_PHY_STS_IE01_V2_W8_RPL_FD_B);
2097 rpl_fd[RF_PATH_C] = le32_get_bits(ie->w9, RTW89_PHY_STS_IE01_V2_W9_RPL_FD_C);
2098 rpl_fd[RF_PATH_D] = le32_get_bits(ie->w9, RTW89_PHY_STS_IE01_V2_W9_RPL_FD_D);
2099
2100 phy_ppdu->bw_idx = le32_get_bits(ie->w5, RTW89_PHY_STS_IE01_V2_W5_BW_IDX);
2101 }
2102
rtw89_core_parse_phy_status_ie01(struct rtw89_dev * rtwdev,const struct rtw89_phy_sts_iehdr * iehdr,struct rtw89_rx_phy_ppdu * phy_ppdu)2103 static void rtw89_core_parse_phy_status_ie01(struct rtw89_dev *rtwdev,
2104 const struct rtw89_phy_sts_iehdr *iehdr,
2105 struct rtw89_rx_phy_ppdu *phy_ppdu)
2106 {
2107 const struct rtw89_phy_sts_ie01 *ie = (const struct rtw89_phy_sts_ie01 *)iehdr;
2108 s16 cfo;
2109 u32 t;
2110
2111 phy_ppdu->chan_idx = le32_get_bits(ie->w0, RTW89_PHY_STS_IE01_W0_CH_IDX);
2112
2113 if (rtwdev->hw->conf.flags & IEEE80211_CONF_MONITOR) {
2114 phy_ppdu->ldpc = le32_get_bits(ie->w2, RTW89_PHY_STS_IE01_W2_LDPC);
2115 phy_ppdu->stbc = le32_get_bits(ie->w2, RTW89_PHY_STS_IE01_W2_STBC);
2116 }
2117
2118 if (!phy_ppdu->hdr_2_en)
2119 phy_ppdu->rx_path_en =
2120 le32_get_bits(ie->w0, RTW89_PHY_STS_IE01_W0_RX_PATH_EN);
2121
2122 if (phy_ppdu->rate < RTW89_HW_RATE_OFDM6)
2123 return;
2124
2125 if (!phy_ppdu->to_self)
2126 return;
2127
2128 phy_ppdu->rpl_avg = le32_get_bits(ie->w0, RTW89_PHY_STS_IE01_W0_RSSI_AVG_FD);
2129 phy_ppdu->ofdm.avg_snr = le32_get_bits(ie->w2, RTW89_PHY_STS_IE01_W2_AVG_SNR);
2130 phy_ppdu->ofdm.evm_max = le32_get_bits(ie->w2, RTW89_PHY_STS_IE01_W2_EVM_MAX);
2131 phy_ppdu->ofdm.evm_min = le32_get_bits(ie->w2, RTW89_PHY_STS_IE01_W2_EVM_MIN);
2132 phy_ppdu->ofdm.has = true;
2133
2134 /* sign conversion for S(12,2) */
2135 if (rtwdev->chip->cfo_src_fd) {
2136 t = le32_get_bits(ie->w1, RTW89_PHY_STS_IE01_W1_FD_CFO);
2137 cfo = sign_extend32(t, 11);
2138 } else {
2139 t = le32_get_bits(ie->w1, RTW89_PHY_STS_IE01_W1_PREMB_CFO);
2140 cfo = sign_extend32(t, 11);
2141 }
2142
2143 rtw89_phy_cfo_parse(rtwdev, cfo, phy_ppdu);
2144
2145 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE)
2146 rtw89_core_parse_phy_status_ie01_v2(rtwdev, iehdr, phy_ppdu);
2147 }
2148
rtw89_core_parse_phy_status_ie00(struct rtw89_dev * rtwdev,const struct rtw89_phy_sts_iehdr * iehdr,struct rtw89_rx_phy_ppdu * phy_ppdu)2149 static void rtw89_core_parse_phy_status_ie00(struct rtw89_dev *rtwdev,
2150 const struct rtw89_phy_sts_iehdr *iehdr,
2151 struct rtw89_rx_phy_ppdu *phy_ppdu)
2152 {
2153 const struct rtw89_phy_sts_ie00 *ie = (const struct rtw89_phy_sts_ie00 *)iehdr;
2154 u16 tmp_rpl;
2155
2156 tmp_rpl = le32_get_bits(ie->w0, RTW89_PHY_STS_IE00_W0_RPL);
2157 phy_ppdu->rpl_avg = tmp_rpl >> 1;
2158
2159 if (!phy_ppdu->hdr_2_en)
2160 phy_ppdu->rx_path_en =
2161 le32_get_bits(ie->w3, RTW89_PHY_STS_IE00_W3_RX_PATH_EN);
2162 }
2163
rtw89_core_parse_phy_status_ie00_v2(struct rtw89_dev * rtwdev,const struct rtw89_phy_sts_iehdr * iehdr,struct rtw89_rx_phy_ppdu * phy_ppdu)2164 static void rtw89_core_parse_phy_status_ie00_v2(struct rtw89_dev *rtwdev,
2165 const struct rtw89_phy_sts_iehdr *iehdr,
2166 struct rtw89_rx_phy_ppdu *phy_ppdu)
2167 {
2168 const struct rtw89_phy_sts_ie00_v2 *ie;
2169 u8 *rpl_path = phy_ppdu->rpl_path;
2170 u16 tmp_rpl[RF_PATH_MAX];
2171 u8 i;
2172
2173 ie = (const struct rtw89_phy_sts_ie00_v2 *)iehdr;
2174 tmp_rpl[RF_PATH_A] = le32_get_bits(ie->w4, RTW89_PHY_STS_IE00_V2_W4_RPL_TD_A);
2175 tmp_rpl[RF_PATH_B] = le32_get_bits(ie->w4, RTW89_PHY_STS_IE00_V2_W4_RPL_TD_B);
2176 tmp_rpl[RF_PATH_C] = le32_get_bits(ie->w4, RTW89_PHY_STS_IE00_V2_W4_RPL_TD_C);
2177 tmp_rpl[RF_PATH_D] = le32_get_bits(ie->w5, RTW89_PHY_STS_IE00_V2_W5_RPL_TD_D);
2178
2179 for (i = 0; i < RF_PATH_MAX; i++)
2180 rpl_path[i] = tmp_rpl[i] >> 1;
2181 }
2182
rtw89_core_process_phy_status_ie(struct rtw89_dev * rtwdev,const struct rtw89_phy_sts_iehdr * iehdr,struct rtw89_rx_phy_ppdu * phy_ppdu)2183 static int rtw89_core_process_phy_status_ie(struct rtw89_dev *rtwdev,
2184 const struct rtw89_phy_sts_iehdr *iehdr,
2185 struct rtw89_rx_phy_ppdu *phy_ppdu)
2186 {
2187 u8 ie;
2188
2189 ie = le32_get_bits(iehdr->w0, RTW89_PHY_STS_IEHDR_TYPE);
2190
2191 switch (ie) {
2192 case RTW89_PHYSTS_IE00_CMN_CCK:
2193 rtw89_core_parse_phy_status_ie00(rtwdev, iehdr, phy_ppdu);
2194 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE)
2195 rtw89_core_parse_phy_status_ie00_v2(rtwdev, iehdr, phy_ppdu);
2196 break;
2197 case RTW89_PHYSTS_IE01_CMN_OFDM:
2198 rtw89_core_parse_phy_status_ie01(rtwdev, iehdr, phy_ppdu);
2199 break;
2200 default:
2201 break;
2202 }
2203
2204 return 0;
2205 }
2206
rtw89_core_update_phy_ppdu_hdr_v2(struct rtw89_rx_phy_ppdu * phy_ppdu)2207 static void rtw89_core_update_phy_ppdu_hdr_v2(struct rtw89_rx_phy_ppdu *phy_ppdu)
2208 {
2209 #if defined(__linux__)
2210 const struct rtw89_phy_sts_hdr_v2 *hdr = phy_ppdu->buf + PHY_STS_HDR_LEN;
2211 #elif defined(__FreeBSD__)
2212 const struct rtw89_phy_sts_hdr_v2 *hdr = (void *)((u8 *)phy_ppdu->buf + PHY_STS_HDR_LEN);
2213 #endif
2214
2215 phy_ppdu->rx_path_en = le32_get_bits(hdr->w0, RTW89_PHY_STS_HDR_V2_W0_PATH_EN);
2216 }
2217
rtw89_core_update_phy_ppdu(struct rtw89_rx_phy_ppdu * phy_ppdu)2218 static void rtw89_core_update_phy_ppdu(struct rtw89_rx_phy_ppdu *phy_ppdu)
2219 {
2220 const struct rtw89_phy_sts_hdr *hdr = phy_ppdu->buf;
2221 u8 *rssi = phy_ppdu->rssi;
2222
2223 phy_ppdu->ie = le32_get_bits(hdr->w0, RTW89_PHY_STS_HDR_W0_IE_MAP);
2224 phy_ppdu->rssi_avg = le32_get_bits(hdr->w0, RTW89_PHY_STS_HDR_W0_RSSI_AVG);
2225 rssi[RF_PATH_A] = le32_get_bits(hdr->w1, RTW89_PHY_STS_HDR_W1_RSSI_A);
2226 rssi[RF_PATH_B] = le32_get_bits(hdr->w1, RTW89_PHY_STS_HDR_W1_RSSI_B);
2227 rssi[RF_PATH_C] = le32_get_bits(hdr->w1, RTW89_PHY_STS_HDR_W1_RSSI_C);
2228 rssi[RF_PATH_D] = le32_get_bits(hdr->w1, RTW89_PHY_STS_HDR_W1_RSSI_D);
2229
2230 phy_ppdu->hdr_2_en = le32_get_bits(hdr->w0, RTW89_PHY_STS_HDR_W0_HDR_2_EN);
2231 if (phy_ppdu->hdr_2_en)
2232 rtw89_core_update_phy_ppdu_hdr_v2(phy_ppdu);
2233 }
2234
rtw89_core_rx_process_phy_ppdu(struct rtw89_dev * rtwdev,struct rtw89_rx_phy_ppdu * phy_ppdu)2235 static int rtw89_core_rx_process_phy_ppdu(struct rtw89_dev *rtwdev,
2236 struct rtw89_rx_phy_ppdu *phy_ppdu)
2237 {
2238 const struct rtw89_phy_sts_hdr *hdr = phy_ppdu->buf;
2239 u32 len_from_header;
2240 bool physts_valid;
2241
2242 physts_valid = le32_get_bits(hdr->w0, RTW89_PHY_STS_HDR_W0_VALID);
2243 if (!physts_valid)
2244 return -EINVAL;
2245
2246 len_from_header = le32_get_bits(hdr->w0, RTW89_PHY_STS_HDR_W0_LEN) << 3;
2247
2248 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE)
2249 len_from_header += PHY_STS_HDR_LEN;
2250
2251 if (len_from_header != phy_ppdu->len) {
2252 rtw89_debug(rtwdev, RTW89_DBG_UNEXP, "phy ppdu len mismatch\n");
2253 return -EINVAL;
2254 }
2255 rtw89_core_update_phy_ppdu(phy_ppdu);
2256
2257 return 0;
2258 }
2259
rtw89_core_rx_parse_phy_sts(struct rtw89_dev * rtwdev,struct rtw89_rx_phy_ppdu * phy_ppdu)2260 static int rtw89_core_rx_parse_phy_sts(struct rtw89_dev *rtwdev,
2261 struct rtw89_rx_phy_ppdu *phy_ppdu)
2262 {
2263 u16 ie_len;
2264 #if defined(__linux__)
2265 void *pos, *end;
2266 #elif defined(__FreeBSD__)
2267 u8 *pos, *end;
2268 #endif
2269
2270 /* mark invalid reports and bypass them */
2271 if (phy_ppdu->ie < RTW89_CCK_PKT)
2272 return -EINVAL;
2273
2274 #if defined(__linux__)
2275 pos = phy_ppdu->buf + PHY_STS_HDR_LEN;
2276 if (phy_ppdu->hdr_2_en)
2277 pos += PHY_STS_HDR_LEN;
2278 end = phy_ppdu->buf + phy_ppdu->len;
2279 #elif defined(__FreeBSD__)
2280 pos = (u8 *)phy_ppdu->buf + PHY_STS_HDR_LEN;
2281 if (phy_ppdu->hdr_2_en)
2282 pos += PHY_STS_HDR_LEN;
2283 end = (u8 *)phy_ppdu->buf + phy_ppdu->len;
2284 #endif
2285 while (pos < end) {
2286 #if defined(__linux__)
2287 const struct rtw89_phy_sts_iehdr *iehdr = pos;
2288 #elif defined(__FreeBSD__)
2289 const struct rtw89_phy_sts_iehdr *iehdr = (void *)pos;
2290 #endif
2291
2292 ie_len = rtw89_core_get_phy_status_ie_len(rtwdev, iehdr);
2293 rtw89_core_process_phy_status_ie(rtwdev, iehdr, phy_ppdu);
2294 pos += ie_len;
2295 if (pos > end || ie_len == 0) {
2296 rtw89_debug(rtwdev, RTW89_DBG_TXRX,
2297 "phy status parse failed\n");
2298 return -EINVAL;
2299 }
2300 }
2301
2302 rtw89_chip_convert_rpl_to_rssi(rtwdev, phy_ppdu);
2303 rtw89_phy_antdiv_parse(rtwdev, phy_ppdu);
2304
2305 return 0;
2306 }
2307
rtw89_core_rx_process_phy_sts(struct rtw89_dev * rtwdev,struct rtw89_rx_phy_ppdu * phy_ppdu)2308 static void rtw89_core_rx_process_phy_sts(struct rtw89_dev *rtwdev,
2309 struct rtw89_rx_phy_ppdu *phy_ppdu)
2310 {
2311 int ret;
2312
2313 ret = rtw89_core_rx_parse_phy_sts(rtwdev, phy_ppdu);
2314 if (ret)
2315 rtw89_debug(rtwdev, RTW89_DBG_TXRX, "parse phy sts failed\n");
2316 else
2317 phy_ppdu->valid = true;
2318
2319 ieee80211_iterate_stations_atomic(rtwdev->hw,
2320 rtw89_core_rx_process_phy_ppdu_iter,
2321 phy_ppdu);
2322 }
2323
rtw89_rxdesc_to_nl_he_gi(struct rtw89_dev * rtwdev,u8 desc_info_gi,bool rx_status)2324 static u8 rtw89_rxdesc_to_nl_he_gi(struct rtw89_dev *rtwdev,
2325 u8 desc_info_gi,
2326 bool rx_status)
2327 {
2328 switch (desc_info_gi) {
2329 case RTW89_GILTF_SGI_4XHE08:
2330 case RTW89_GILTF_2XHE08:
2331 case RTW89_GILTF_1XHE08:
2332 return NL80211_RATE_INFO_HE_GI_0_8;
2333 case RTW89_GILTF_2XHE16:
2334 case RTW89_GILTF_1XHE16:
2335 return NL80211_RATE_INFO_HE_GI_1_6;
2336 case RTW89_GILTF_LGI_4XHE32:
2337 return NL80211_RATE_INFO_HE_GI_3_2;
2338 default:
2339 rtw89_warn(rtwdev, "invalid gi_ltf=%d", desc_info_gi);
2340 if (rx_status)
2341 return NL80211_RATE_INFO_HE_GI_3_2;
2342 return U8_MAX;
2343 }
2344 }
2345
rtw89_rxdesc_to_nl_eht_gi(struct rtw89_dev * rtwdev,u8 desc_info_gi,bool rx_status)2346 static u8 rtw89_rxdesc_to_nl_eht_gi(struct rtw89_dev *rtwdev,
2347 u8 desc_info_gi,
2348 bool rx_status)
2349 {
2350 switch (desc_info_gi) {
2351 case RTW89_GILTF_SGI_4XHE08:
2352 case RTW89_GILTF_2XHE08:
2353 case RTW89_GILTF_1XHE08:
2354 return NL80211_RATE_INFO_EHT_GI_0_8;
2355 case RTW89_GILTF_2XHE16:
2356 case RTW89_GILTF_1XHE16:
2357 return NL80211_RATE_INFO_EHT_GI_1_6;
2358 case RTW89_GILTF_LGI_4XHE32:
2359 return NL80211_RATE_INFO_EHT_GI_3_2;
2360 default:
2361 rtw89_warn(rtwdev, "invalid gi_ltf=%d", desc_info_gi);
2362 if (rx_status)
2363 return NL80211_RATE_INFO_EHT_GI_3_2;
2364 return U8_MAX;
2365 }
2366 }
2367
rtw89_rxdesc_to_nl_he_eht_gi(struct rtw89_dev * rtwdev,u8 desc_info_gi,bool rx_status,bool eht)2368 static u8 rtw89_rxdesc_to_nl_he_eht_gi(struct rtw89_dev *rtwdev,
2369 u8 desc_info_gi,
2370 bool rx_status, bool eht)
2371 {
2372 return eht ? rtw89_rxdesc_to_nl_eht_gi(rtwdev, desc_info_gi, rx_status) :
2373 rtw89_rxdesc_to_nl_he_gi(rtwdev, desc_info_gi, rx_status);
2374 }
2375
2376 static
rtw89_check_rx_statu_gi_match(struct ieee80211_rx_status * status,u8 gi_ltf,bool eht)2377 bool rtw89_check_rx_statu_gi_match(struct ieee80211_rx_status *status, u8 gi_ltf,
2378 bool eht)
2379 {
2380 if (eht)
2381 return status->eht.gi == gi_ltf;
2382
2383 return status->he_gi == gi_ltf;
2384 }
2385
rtw89_core_rx_ppdu_match(struct rtw89_dev * rtwdev,struct rtw89_rx_desc_info * desc_info,struct ieee80211_rx_status * status)2386 static bool rtw89_core_rx_ppdu_match(struct rtw89_dev *rtwdev,
2387 struct rtw89_rx_desc_info *desc_info,
2388 struct ieee80211_rx_status *status)
2389 {
2390 u8 band = desc_info->bb_sel ? RTW89_PHY_1 : RTW89_PHY_0;
2391 u8 data_rate_mode, bw, rate_idx = MASKBYTE0, gi_ltf;
2392 bool eht = false;
2393 u16 data_rate;
2394 bool ret;
2395
2396 data_rate = desc_info->data_rate;
2397 data_rate_mode = rtw89_get_data_rate_mode(rtwdev, data_rate);
2398 if (data_rate_mode == DATA_RATE_MODE_NON_HT) {
2399 rate_idx = rtw89_get_data_not_ht_idx(rtwdev, data_rate);
2400 /* rate_idx is still hardware value here */
2401 } else if (data_rate_mode == DATA_RATE_MODE_HT) {
2402 rate_idx = rtw89_get_data_ht_mcs(rtwdev, data_rate);
2403 } else if (data_rate_mode == DATA_RATE_MODE_VHT ||
2404 data_rate_mode == DATA_RATE_MODE_HE ||
2405 data_rate_mode == DATA_RATE_MODE_EHT) {
2406 rate_idx = rtw89_get_data_mcs(rtwdev, data_rate);
2407 } else {
2408 rtw89_warn(rtwdev, "invalid RX rate mode %d\n", data_rate_mode);
2409 }
2410
2411 eht = data_rate_mode == DATA_RATE_MODE_EHT;
2412 bw = rtw89_hw_to_rate_info_bw(desc_info->bw);
2413 gi_ltf = rtw89_rxdesc_to_nl_he_eht_gi(rtwdev, desc_info->gi_ltf, false, eht);
2414 ret = rtwdev->ppdu_sts.curr_rx_ppdu_cnt[band] == desc_info->ppdu_cnt &&
2415 status->rate_idx == rate_idx &&
2416 rtw89_check_rx_statu_gi_match(status, gi_ltf, eht) &&
2417 status->bw == bw;
2418
2419 return ret;
2420 }
2421
2422 struct rtw89_vif_rx_stats_iter_data {
2423 struct rtw89_dev *rtwdev;
2424 struct rtw89_rx_phy_ppdu *phy_ppdu;
2425 struct rtw89_rx_desc_info *desc_info;
2426 struct sk_buff *skb;
2427 const u8 *bssid;
2428 };
2429
rtw89_stats_trigger_frame(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link,struct ieee80211_bss_conf * bss_conf,struct sk_buff * skb)2430 static void rtw89_stats_trigger_frame(struct rtw89_dev *rtwdev,
2431 struct rtw89_vif_link *rtwvif_link,
2432 struct ieee80211_bss_conf *bss_conf,
2433 struct sk_buff *skb)
2434 {
2435 struct ieee80211_trigger *tf = (struct ieee80211_trigger *)skb->data;
2436 struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link);
2437 struct rtw89_vif *rtwvif = rtwvif_link->rtwvif;
2438 u8 *pos, *end, type, tf_bw;
2439 u16 aid, tf_rua;
2440
2441 if (!ether_addr_equal(bss_conf->bssid, tf->ta) ||
2442 rtwvif_link->wifi_role != RTW89_WIFI_ROLE_STATION ||
2443 rtwvif_link->net_type == RTW89_NET_TYPE_NO_LINK)
2444 return;
2445
2446 type = le64_get_bits(tf->common_info, IEEE80211_TRIGGER_TYPE_MASK);
2447 if (type != IEEE80211_TRIGGER_TYPE_BASIC && type != IEEE80211_TRIGGER_TYPE_MU_BAR)
2448 return;
2449
2450 end = (u8 *)tf + skb->len;
2451 pos = tf->variable;
2452
2453 while (end - pos >= RTW89_TF_BASIC_USER_INFO_SZ) {
2454 aid = RTW89_GET_TF_USER_INFO_AID12(pos);
2455 tf_rua = RTW89_GET_TF_USER_INFO_RUA(pos);
2456 tf_bw = le64_get_bits(tf->common_info, IEEE80211_TRIGGER_ULBW_MASK);
2457 rtw89_debug(rtwdev, RTW89_DBG_TXRX,
2458 "[TF] aid: %d, ul_mcs: %d, rua: %d, bw: %d\n",
2459 aid, RTW89_GET_TF_USER_INFO_UL_MCS(pos),
2460 tf_rua, tf_bw);
2461
2462 if (aid == RTW89_TF_PAD)
2463 break;
2464
2465 if (aid == vif->cfg.aid) {
2466 enum nl80211_he_ru_alloc rua;
2467
2468 rtwvif->stats.rx_tf_acc++;
2469 rtwdev->stats.rx_tf_acc++;
2470
2471 /* The following only required for HE trigger frame, but we
2472 * cannot use UL HE-SIG-A2 reserved subfield to identify it
2473 * since some 11ax APs will fill it with all 0s, which will
2474 * be misunderstood as EHT trigger frame.
2475 */
2476 if (bss_conf->eht_support)
2477 break;
2478
2479 rua = rtw89_he_rua_to_ru_alloc(tf_rua >> 1);
2480
2481 if (tf_bw == IEEE80211_TRIGGER_ULBW_160_80P80MHZ &&
2482 rua <= NL80211_RATE_INFO_HE_RU_ALLOC_106)
2483 rtwvif_link->pwr_diff_en = true;
2484 break;
2485 }
2486
2487 pos += RTW89_TF_BASIC_USER_INFO_SZ;
2488 }
2489 }
2490
rtw89_cancel_6ghz_probe_work(struct wiphy * wiphy,struct wiphy_work * work)2491 static void rtw89_cancel_6ghz_probe_work(struct wiphy *wiphy, struct wiphy_work *work)
2492 {
2493 struct rtw89_dev *rtwdev = container_of(work, struct rtw89_dev,
2494 cancel_6ghz_probe_work);
2495 struct list_head *pkt_list = rtwdev->scan_info.pkt_list;
2496 struct rtw89_pktofld_info *info;
2497
2498 lockdep_assert_wiphy(wiphy);
2499
2500 if (!rtwdev->scanning)
2501 return;
2502
2503 list_for_each_entry(info, &pkt_list[NL80211_BAND_6GHZ], list) {
2504 if (!info->cancel || !test_bit(info->id, rtwdev->pkt_offload))
2505 continue;
2506
2507 rtw89_fw_h2c_del_pkt_offload(rtwdev, info->id);
2508
2509 /* Don't delete/free info from pkt_list at this moment. Let it
2510 * be deleted/freed in rtw89_release_pkt_list() after scanning,
2511 * since if during scanning, pkt_list is accessed in bottom half.
2512 */
2513 }
2514 }
2515
rtw89_core_cancel_6ghz_probe_tx(struct rtw89_dev * rtwdev,struct sk_buff * skb)2516 static void rtw89_core_cancel_6ghz_probe_tx(struct rtw89_dev *rtwdev,
2517 struct sk_buff *skb)
2518 {
2519 struct ieee80211_rx_status *rx_status = IEEE80211_SKB_RXCB(skb);
2520 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
2521 struct list_head *pkt_list = rtwdev->scan_info.pkt_list;
2522 struct rtw89_pktofld_info *info;
2523 const u8 *ies = mgmt->u.beacon.variable, *ssid_ie;
2524 bool queue_work = false;
2525
2526 if (rx_status->band != NL80211_BAND_6GHZ)
2527 return;
2528
2529 if (unlikely(!(rtwdev->chip->support_bands & BIT(NL80211_BAND_6GHZ)))) {
2530 rtw89_debug(rtwdev, RTW89_DBG_UNEXP, "invalid rx on unsupported 6 GHz\n");
2531 return;
2532 }
2533
2534 ssid_ie = cfg80211_find_ie(WLAN_EID_SSID, ies, skb->len);
2535
2536 list_for_each_entry(info, &pkt_list[NL80211_BAND_6GHZ], list) {
2537 if (ether_addr_equal(info->bssid, mgmt->bssid)) {
2538 info->cancel = true;
2539 queue_work = true;
2540 continue;
2541 }
2542
2543 if (!ssid_ie || ssid_ie[1] != info->ssid_len || info->ssid_len == 0)
2544 continue;
2545
2546 if (memcmp(&ssid_ie[2], info->ssid, info->ssid_len) == 0) {
2547 info->cancel = true;
2548 queue_work = true;
2549 }
2550 }
2551
2552 if (queue_work)
2553 wiphy_work_queue(rtwdev->hw->wiphy, &rtwdev->cancel_6ghz_probe_work);
2554 }
2555
rtw89_vif_sync_bcn_tsf(struct rtw89_vif_link * rtwvif_link,struct ieee80211_hdr * hdr,size_t len)2556 static void rtw89_vif_sync_bcn_tsf(struct rtw89_vif_link *rtwvif_link,
2557 struct ieee80211_hdr *hdr, size_t len)
2558 {
2559 struct ieee80211_mgmt *mgmt = (typeof(mgmt))hdr;
2560
2561 if (len < offsetof(typeof(*mgmt), u.beacon.variable))
2562 return;
2563
2564 WRITE_ONCE(rtwvif_link->sync_bcn_tsf, le64_to_cpu(mgmt->u.beacon.timestamp));
2565 }
2566
rtw89_bcn_calc_min_tbtt(struct rtw89_dev * rtwdev,u32 tbtt1,u32 tbtt2)2567 static u32 rtw89_bcn_calc_min_tbtt(struct rtw89_dev *rtwdev, u32 tbtt1, u32 tbtt2)
2568 {
2569 struct rtw89_beacon_track_info *bcn_track = &rtwdev->bcn_track;
2570 u32 close_bcn_intvl_th = bcn_track->close_bcn_intvl_th;
2571 u32 tbtt_diff_th = bcn_track->tbtt_diff_th;
2572
2573 if (tbtt2 > tbtt1)
2574 swap(tbtt1, tbtt2);
2575
2576 if (tbtt1 - tbtt2 > tbtt_diff_th)
2577 return tbtt1;
2578 else if (tbtt2 > close_bcn_intvl_th)
2579 return tbtt2;
2580 else if (tbtt1 > close_bcn_intvl_th)
2581 return tbtt1;
2582 else
2583 return tbtt2;
2584 }
2585
rtw89_bcn_cfg_tbtt_offset(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link)2586 static void rtw89_bcn_cfg_tbtt_offset(struct rtw89_dev *rtwdev,
2587 struct rtw89_vif_link *rtwvif_link)
2588 {
2589 struct rtw89_beacon_track_info *bcn_track = &rtwdev->bcn_track;
2590 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;
2591 u32 offset = bcn_track->tbtt_offset;
2592
2593 if (chip_id == RTL8852A || rtw89_is_rtl885xb(rtwdev)) {
2594 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
2595 const struct rtw89_port_reg *p = mac->port_base;
2596 u32 bcnspc, val;
2597
2598 bcnspc = rtw89_read32_port_mask(rtwdev, rtwvif_link,
2599 p->bcn_space, B_AX_BCN_SPACE_MASK);
2600 val = bcnspc - (offset / 1024);
2601 val = u32_encode_bits(val, B_AX_TBTT_SHIFT_OFST_MAG) |
2602 B_AX_TBTT_SHIFT_OFST_SIGN;
2603
2604 rtw89_write16_port_mask(rtwdev, rtwvif_link, p->tbtt_shift,
2605 B_AX_TBTT_SHIFT_OFST_MASK, val);
2606
2607 return;
2608 }
2609
2610 rtw89_fw_h2c_tbtt_tuning(rtwdev, rtwvif_link, offset);
2611 }
2612
rtw89_bcn_update_tbtt_offset(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link)2613 static void rtw89_bcn_update_tbtt_offset(struct rtw89_dev *rtwdev,
2614 struct rtw89_vif_link *rtwvif_link)
2615 {
2616 struct rtw89_beacon_stat *bcn_stat = &rtwdev->phystat.bcn_stat;
2617 struct rtw89_beacon_track_info *bcn_track = &rtwdev->bcn_track;
2618 u32 *tbtt_us = bcn_stat->tbtt_us;
2619 u32 offset = tbtt_us[0];
2620 u8 i;
2621
2622 for (i = 1; i < RTW89_BCN_TRACK_STAT_NR; i++)
2623 offset = rtw89_bcn_calc_min_tbtt(rtwdev, tbtt_us[i], offset);
2624
2625 if (bcn_track->tbtt_offset == offset)
2626 return;
2627
2628 bcn_track->tbtt_offset = offset;
2629 rtw89_bcn_cfg_tbtt_offset(rtwdev, rtwvif_link);
2630 }
2631
cmp_u16(const void * a,const void * b)2632 static int cmp_u16(const void *a, const void *b)
2633 {
2634 return *(const u16 *)a - *(const u16 *)b;
2635 }
2636
_rtw89_bcn_calc_drift(u16 tbtt,u16 offset,u16 beacon_int)2637 static u16 _rtw89_bcn_calc_drift(u16 tbtt, u16 offset, u16 beacon_int)
2638 {
2639 if (tbtt < offset)
2640 return beacon_int - offset + tbtt;
2641
2642 return tbtt - offset;
2643 }
2644
rtw89_bcn_calc_drift(struct rtw89_dev * rtwdev)2645 static void rtw89_bcn_calc_drift(struct rtw89_dev *rtwdev)
2646 {
2647 struct rtw89_beacon_stat *bcn_stat = &rtwdev->phystat.bcn_stat;
2648 struct rtw89_beacon_track_info *bcn_track = &rtwdev->bcn_track;
2649 u16 offset_tu = bcn_track->tbtt_offset / 1024;
2650 u16 *tbtt_tu = bcn_stat->tbtt_tu;
2651 u16 *drift = bcn_stat->drift;
2652 u8 i;
2653
2654 bcn_stat->tbtt_tu_min = U16_MAX;
2655 bcn_stat->tbtt_tu_max = 0;
2656 for (i = 0; i < RTW89_BCN_TRACK_STAT_NR; i++) {
2657 drift[i] = _rtw89_bcn_calc_drift(tbtt_tu[i], offset_tu,
2658 bcn_track->beacon_int);
2659
2660 bcn_stat->tbtt_tu_min = min(bcn_stat->tbtt_tu_min, tbtt_tu[i]);
2661 bcn_stat->tbtt_tu_max = max(bcn_stat->tbtt_tu_max, tbtt_tu[i]);
2662 }
2663
2664 sort(drift, RTW89_BCN_TRACK_STAT_NR, sizeof(*drift), cmp_u16, NULL);
2665 }
2666
rtw89_bcn_calc_distribution(struct rtw89_dev * rtwdev)2667 static void rtw89_bcn_calc_distribution(struct rtw89_dev *rtwdev)
2668 {
2669 struct rtw89_beacon_stat *bcn_stat = &rtwdev->phystat.bcn_stat;
2670 struct rtw89_beacon_dist *bcn_dist = &bcn_stat->bcn_dist;
2671 u16 lower_bound, upper_bound, outlier_count = 0;
2672 u16 *drift = bcn_stat->drift;
2673 u16 *bins = bcn_dist->bins;
2674 u16 q1, q3, iqr, tmp;
2675 u8 i;
2676
2677 BUILD_BUG_ON(RTW89_BCN_TRACK_STAT_NR % 4 != 0);
2678
2679 memset(bcn_dist, 0, sizeof(*bcn_dist));
2680
2681 bcn_dist->min = drift[0];
2682 bcn_dist->max = drift[RTW89_BCN_TRACK_STAT_NR - 1];
2683
2684 tmp = RTW89_BCN_TRACK_STAT_NR / 4;
2685 q1 = ((drift[tmp] + drift[tmp - 1]) * RTW89_BCN_TRACK_SCALE_FACTOR) / 2;
2686
2687 tmp = (RTW89_BCN_TRACK_STAT_NR * 3) / 4;
2688 q3 = ((drift[tmp] + drift[tmp - 1]) * RTW89_BCN_TRACK_SCALE_FACTOR) / 2;
2689
2690 iqr = q3 - q1;
2691 tmp = (3 * iqr) / 2;
2692
2693 if (bcn_dist->min <= 5)
2694 lower_bound = bcn_dist->min;
2695 else if (q1 > tmp)
2696 lower_bound = (q1 - tmp) / RTW89_BCN_TRACK_SCALE_FACTOR;
2697 else
2698 lower_bound = 0;
2699
2700 upper_bound = (q3 + tmp) / RTW89_BCN_TRACK_SCALE_FACTOR;
2701
2702 for (i = 0; i < RTW89_BCN_TRACK_STAT_NR; i++) {
2703 u16 tbtt = bcn_stat->tbtt_tu[i];
2704 u16 min = bcn_stat->tbtt_tu_min;
2705 u8 bin_idx;
2706
2707 /* histogram */
2708 bin_idx = min((tbtt - min) / RTW89_BCN_TRACK_BIN_WIDTH,
2709 RTW89_BCN_TRACK_MAX_BIN_NUM - 1);
2710 bins[bin_idx]++;
2711
2712 /* boxplot outlier */
2713 if (drift[i] < lower_bound || drift[i] > upper_bound)
2714 outlier_count++;
2715 }
2716
2717 bcn_dist->outlier_count = outlier_count;
2718 bcn_dist->lower_bound = lower_bound;
2719 bcn_dist->upper_bound = upper_bound;
2720 }
2721
rtw89_bcn_get_coverage(struct rtw89_dev * rtwdev,u16 threshold)2722 static u8 rtw89_bcn_get_coverage(struct rtw89_dev *rtwdev, u16 threshold)
2723 {
2724 struct rtw89_beacon_stat *bcn_stat = &rtwdev->phystat.bcn_stat;
2725 int l = 0, r = RTW89_BCN_TRACK_STAT_NR - 1, m;
2726 u16 *drift = bcn_stat->drift;
2727 int index = -1;
2728 u8 count = 0;
2729
2730 while (l <= r) {
2731 m = l + (r - l) / 2;
2732
2733 if (drift[m] <= threshold) {
2734 index = m;
2735 l = m + 1;
2736 } else {
2737 r = m - 1;
2738 }
2739 }
2740
2741 count = (index == -1) ? 0 : (index + 1);
2742
2743 return (count * PERCENT) / RTW89_BCN_TRACK_STAT_NR;
2744 }
2745
rtw89_bcn_get_histogram_bound(struct rtw89_dev * rtwdev,u8 target)2746 static u16 rtw89_bcn_get_histogram_bound(struct rtw89_dev *rtwdev, u8 target)
2747 {
2748 struct rtw89_beacon_stat *bcn_stat = &rtwdev->phystat.bcn_stat;
2749 struct rtw89_beacon_dist *bcn_dist = &bcn_stat->bcn_dist;
2750 u16 tbtt_tu_max = bcn_stat->tbtt_tu_max;
2751 u16 upper, lower = bcn_stat->tbtt_tu_min;
2752 u8 i, count = 0;
2753
2754 for (i = 0; i < RTW89_BCN_TRACK_MAX_BIN_NUM; i++) {
2755 upper = lower + RTW89_BCN_TRACK_BIN_WIDTH - 1;
2756 if (i == RTW89_BCN_TRACK_MAX_BIN_NUM - 1)
2757 upper = max(upper, tbtt_tu_max);
2758
2759 count += bcn_dist->bins[i];
2760 if (count > target)
2761 break;
2762
2763 lower = upper + 1;
2764 }
2765
2766 return upper;
2767 }
2768
rtw89_bcn_get_rx_time(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan)2769 static u16 rtw89_bcn_get_rx_time(struct rtw89_dev *rtwdev,
2770 const struct rtw89_chan *chan)
2771 {
2772 #define RTW89_SYMBOL_TIME_2GHZ 192
2773 #define RTW89_SYMBOL_TIME_5GHZ 20
2774 #define RTW89_SYMBOL_TIME_6GHZ 20
2775 struct rtw89_pkt_stat *pkt_stat = &rtwdev->phystat.cur_pkt_stat;
2776 u16 bitrate, val;
2777
2778 if (!rtw89_legacy_rate_to_bitrate(rtwdev, pkt_stat->beacon_rate, &bitrate))
2779 return 0;
2780
2781 val = (pkt_stat->beacon_len * 8 * RTW89_BCN_TRACK_SCALE_FACTOR) / bitrate;
2782
2783 switch (chan->band_type) {
2784 default:
2785 case RTW89_BAND_2G:
2786 val += RTW89_SYMBOL_TIME_2GHZ;
2787 break;
2788 case RTW89_BAND_5G:
2789 val += RTW89_SYMBOL_TIME_5GHZ;
2790 break;
2791 case RTW89_BAND_6G:
2792 val += RTW89_SYMBOL_TIME_6GHZ;
2793 break;
2794 }
2795
2796 /* convert to millisecond */
2797 return DIV_ROUND_UP(val, 1000);
2798 }
2799
rtw89_bcn_calc_timeout(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link)2800 static void rtw89_bcn_calc_timeout(struct rtw89_dev *rtwdev,
2801 struct rtw89_vif_link *rtwvif_link)
2802 {
2803 #define RTW89_BCN_TRACK_EXTEND_TIMEOUT 5
2804 #define RTW89_BCN_TRACK_COVERAGE_TH 0 /* unit: TU */
2805 #define RTW89_BCN_TRACK_STRONG_RSSI 80
2806 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, rtwvif_link->chanctx_idx);
2807 struct rtw89_pkt_stat *pkt_stat = &rtwdev->phystat.cur_pkt_stat;
2808 struct rtw89_beacon_stat *bcn_stat = &rtwdev->phystat.bcn_stat;
2809 struct rtw89_beacon_track_info *bcn_track = &rtwdev->bcn_track;
2810 struct rtw89_beacon_dist *bcn_dist = &bcn_stat->bcn_dist;
2811 u16 outlier_high_bcn_th = bcn_track->outlier_high_bcn_th;
2812 u16 outlier_low_bcn_th = bcn_track->outlier_low_bcn_th;
2813 u8 rssi = ewma_rssi_read(&rtwdev->phystat.bcn_rssi);
2814 u16 target_bcn_th = bcn_track->target_bcn_th;
2815 u16 low_bcn_th = bcn_track->low_bcn_th;
2816 u16 med_bcn_th = bcn_track->med_bcn_th;
2817 u16 beacon_int = bcn_track->beacon_int;
2818 u16 bcn_timeout;
2819
2820 if (pkt_stat->beacon_nr < low_bcn_th) {
2821 bcn_timeout = (RTW89_BCN_TRACK_TARGET_BCN * beacon_int) / PERCENT;
2822 goto out;
2823 }
2824
2825 if (bcn_dist->outlier_count >= outlier_high_bcn_th) {
2826 bcn_timeout = bcn_dist->max;
2827 goto out;
2828 }
2829
2830 if (pkt_stat->beacon_nr < med_bcn_th) {
2831 if (bcn_dist->outlier_count > outlier_low_bcn_th)
2832 bcn_timeout = (bcn_dist->max + bcn_dist->upper_bound) / 2;
2833 else
2834 bcn_timeout = bcn_dist->upper_bound +
2835 RTW89_BCN_TRACK_EXTEND_TIMEOUT;
2836
2837 goto out;
2838 }
2839
2840 if (rssi >= RTW89_BCN_TRACK_STRONG_RSSI) {
2841 if (rtw89_bcn_get_coverage(rtwdev, RTW89_BCN_TRACK_COVERAGE_TH) >= 90) {
2842 /* ideal case */
2843 bcn_timeout = 0;
2844 } else {
2845 u16 offset_tu = bcn_track->tbtt_offset / 1024;
2846 u16 upper_bound;
2847
2848 upper_bound =
2849 rtw89_bcn_get_histogram_bound(rtwdev, target_bcn_th);
2850 bcn_timeout =
2851 _rtw89_bcn_calc_drift(upper_bound, offset_tu, beacon_int);
2852 }
2853
2854 goto out;
2855 }
2856
2857 bcn_timeout = bcn_stat->drift[target_bcn_th];
2858
2859 out:
2860 bcn_track->bcn_timeout = bcn_timeout + rtw89_bcn_get_rx_time(rtwdev, chan);
2861 }
2862
rtw89_bcn_update_timeout(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link)2863 static void rtw89_bcn_update_timeout(struct rtw89_dev *rtwdev,
2864 struct rtw89_vif_link *rtwvif_link)
2865 {
2866 rtw89_bcn_calc_drift(rtwdev);
2867 rtw89_bcn_calc_distribution(rtwdev);
2868 rtw89_bcn_calc_timeout(rtwdev, rtwvif_link);
2869 }
2870
rtw89_core_bcn_track(struct rtw89_dev * rtwdev)2871 static void rtw89_core_bcn_track(struct rtw89_dev *rtwdev)
2872 {
2873 struct rtw89_beacon_track_info *bcn_track = &rtwdev->bcn_track;
2874 struct rtw89_vif_link *rtwvif_link;
2875 struct rtw89_vif *rtwvif;
2876 unsigned int link_id;
2877
2878 if (!RTW89_CHK_FW_FEATURE(BEACON_TRACKING, &rtwdev->fw))
2879 return;
2880
2881 if (!rtwdev->lps_enabled)
2882 return;
2883
2884 if (!bcn_track->is_data_ready)
2885 return;
2886
2887 rtw89_for_each_rtwvif(rtwdev, rtwvif) {
2888 rtw89_vif_for_each_link(rtwvif, rtwvif_link, link_id) {
2889 if (!(rtwvif_link->wifi_role == RTW89_WIFI_ROLE_STATION ||
2890 rtwvif_link->wifi_role == RTW89_WIFI_ROLE_P2P_CLIENT))
2891 continue;
2892
2893 rtw89_bcn_update_tbtt_offset(rtwdev, rtwvif_link);
2894 rtw89_bcn_update_timeout(rtwdev, rtwvif_link);
2895 }
2896 }
2897 }
2898
rtw89_core_bcn_track_can_lps(struct rtw89_dev * rtwdev)2899 static bool rtw89_core_bcn_track_can_lps(struct rtw89_dev *rtwdev)
2900 {
2901 struct rtw89_beacon_track_info *bcn_track = &rtwdev->bcn_track;
2902
2903 if (!RTW89_CHK_FW_FEATURE(BEACON_TRACKING, &rtwdev->fw))
2904 return true;
2905
2906 return bcn_track->is_data_ready;
2907 }
2908
rtw89_core_bcn_track_assoc(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link)2909 static void rtw89_core_bcn_track_assoc(struct rtw89_dev *rtwdev,
2910 struct rtw89_vif_link *rtwvif_link)
2911 {
2912 #define RTW89_BCN_TRACK_MED_BCN 70
2913 #define RTW89_BCN_TRACK_LOW_BCN 30
2914 #define RTW89_BCN_TRACK_OUTLIER_HIGH_BCN 30
2915 #define RTW89_BCN_TRACK_OUTLIER_LOW_BCN 20
2916 struct rtw89_beacon_track_info *bcn_track = &rtwdev->bcn_track;
2917 u32 period = jiffies_to_msecs(RTW89_TRACK_WORK_PERIOD);
2918 struct ieee80211_bss_conf *bss_conf;
2919 u32 beacons_in_period;
2920 u32 bcn_intvl_us;
2921 u16 beacon_int;
2922 u8 dtim;
2923
2924 rcu_read_lock();
2925 bss_conf = rtw89_vif_rcu_dereference_link(rtwvif_link, true);
2926 beacon_int = bss_conf->beacon_int ?: 100;
2927 dtim = bss_conf->dtim_period;
2928 rcu_read_unlock();
2929
2930 #if defined(__FreeBSD__)
2931 WARN(beacon_int == 0 || dtim == 0, "period %u / beacon_int %u / dtim %u\n",
2932 period, beacon_int, dtim);
2933 #endif
2934 beacons_in_period = period / beacon_int / dtim;
2935 bcn_intvl_us = ieee80211_tu_to_usec(beacon_int);
2936
2937 bcn_track->low_bcn_th =
2938 (beacons_in_period * RTW89_BCN_TRACK_LOW_BCN) / PERCENT;
2939 bcn_track->med_bcn_th =
2940 (beacons_in_period * RTW89_BCN_TRACK_MED_BCN) / PERCENT;
2941 bcn_track->outlier_low_bcn_th =
2942 (RTW89_BCN_TRACK_STAT_NR * RTW89_BCN_TRACK_OUTLIER_LOW_BCN) / PERCENT;
2943 bcn_track->outlier_high_bcn_th =
2944 (RTW89_BCN_TRACK_STAT_NR * RTW89_BCN_TRACK_OUTLIER_HIGH_BCN) / PERCENT;
2945 bcn_track->target_bcn_th =
2946 (RTW89_BCN_TRACK_STAT_NR * RTW89_BCN_TRACK_TARGET_BCN) / PERCENT;
2947
2948 bcn_track->close_bcn_intvl_th = ieee80211_tu_to_usec(beacon_int - 3);
2949 bcn_track->tbtt_diff_th = (bcn_intvl_us * 85) / PERCENT;
2950 bcn_track->beacon_int = beacon_int;
2951 bcn_track->dtim = dtim;
2952 }
2953
rtw89_core_bcn_track_reset(struct rtw89_dev * rtwdev)2954 static void rtw89_core_bcn_track_reset(struct rtw89_dev *rtwdev)
2955 {
2956 memset(&rtwdev->phystat.bcn_stat, 0, sizeof(rtwdev->phystat.bcn_stat));
2957 memset(&rtwdev->bcn_track, 0, sizeof(rtwdev->bcn_track));
2958 }
2959
rtw89_vif_rx_bcn_stat(struct rtw89_dev * rtwdev,struct sk_buff * skb)2960 static void rtw89_vif_rx_bcn_stat(struct rtw89_dev *rtwdev, struct sk_buff *skb)
2961 {
2962 #define RTW89_APPEND_TSF_2GHZ 384
2963 #define RTW89_APPEND_TSF_5GHZ 52
2964 #define RTW89_APPEND_TSF_6GHZ 52
2965 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
2966 struct ieee80211_rx_status *rx_status = IEEE80211_SKB_RXCB(skb);
2967 struct rtw89_beacon_stat *bcn_stat = &rtwdev->phystat.bcn_stat;
2968 struct rtw89_beacon_track_info *bcn_track = &rtwdev->bcn_track;
2969 u32 bcn_intvl_us = ieee80211_tu_to_usec(bcn_track->beacon_int);
2970 u64 tsf = le64_to_cpu(mgmt->u.beacon.timestamp);
2971 u8 wp, num = bcn_stat->num;
2972 u16 append;
2973
2974 if (!RTW89_CHK_FW_FEATURE(BEACON_TRACKING, &rtwdev->fw))
2975 return;
2976
2977 /* Skip if not yet associated */
2978 if (!bcn_intvl_us)
2979 return;
2980
2981 switch (rx_status->band) {
2982 default:
2983 case NL80211_BAND_2GHZ:
2984 append = RTW89_APPEND_TSF_2GHZ;
2985 break;
2986 case NL80211_BAND_5GHZ:
2987 append = RTW89_APPEND_TSF_5GHZ;
2988 break;
2989 case NL80211_BAND_6GHZ:
2990 append = RTW89_APPEND_TSF_6GHZ;
2991 break;
2992 }
2993
2994 wp = bcn_stat->wp;
2995 div_u64_rem(tsf - append, bcn_intvl_us, &bcn_stat->tbtt_us[wp]);
2996 bcn_stat->tbtt_tu[wp] = bcn_stat->tbtt_us[wp] / 1024;
2997 bcn_stat->wp = (wp + 1) % RTW89_BCN_TRACK_STAT_NR;
2998 bcn_stat->num = umin(num + 1, RTW89_BCN_TRACK_STAT_NR);
2999 bcn_track->is_data_ready = bcn_stat->num == RTW89_BCN_TRACK_STAT_NR;
3000 }
3001
rtw89_vif_rx_stats_iter(void * data,u8 * mac,struct ieee80211_vif * vif)3002 static void rtw89_vif_rx_stats_iter(void *data, u8 *mac,
3003 struct ieee80211_vif *vif)
3004 {
3005 struct rtw89_vif_rx_stats_iter_data *iter_data = data;
3006 struct rtw89_dev *rtwdev = iter_data->rtwdev;
3007 struct rtw89_vif *rtwvif = vif_to_rtwvif(vif);
3008 struct rtw89_pkt_stat *pkt_stat = &rtwdev->phystat.cur_pkt_stat;
3009 struct rtw89_rx_desc_info *desc_info = iter_data->desc_info;
3010 struct sk_buff *skb = iter_data->skb;
3011 struct ieee80211_rx_status *rx_status = IEEE80211_SKB_RXCB(skb);
3012 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
3013 struct rtw89_rx_phy_ppdu *phy_ppdu = iter_data->phy_ppdu;
3014 bool is_mld = ieee80211_vif_is_mld(vif);
3015 struct ieee80211_bss_conf *bss_conf;
3016 struct rtw89_vif_link *rtwvif_link;
3017 const u8 *bssid = iter_data->bssid;
3018 const u8 *target_bssid;
3019
3020 if (rtwdev->scanning &&
3021 (ieee80211_is_beacon(hdr->frame_control) ||
3022 ieee80211_is_probe_resp(hdr->frame_control)))
3023 rtw89_core_cancel_6ghz_probe_tx(rtwdev, skb);
3024
3025 rcu_read_lock();
3026
3027 rtwvif_link = rtw89_vif_get_link_inst(rtwvif, desc_info->bb_sel);
3028 if (unlikely(!rtwvif_link))
3029 goto out;
3030
3031 bss_conf = rtw89_vif_rcu_dereference_link(rtwvif_link, false);
3032 if (!bss_conf->bssid)
3033 goto out;
3034
3035 if (ieee80211_is_trigger(hdr->frame_control)) {
3036 rtw89_stats_trigger_frame(rtwdev, rtwvif_link, bss_conf, skb);
3037 goto out;
3038 }
3039
3040 target_bssid = ieee80211_is_beacon(hdr->frame_control) &&
3041 bss_conf->nontransmitted ?
3042 bss_conf->transmitter_bssid : bss_conf->bssid;
3043 if (!ether_addr_equal(target_bssid, bssid))
3044 goto out;
3045
3046 if (is_mld) {
3047 rx_status->link_valid = true;
3048 rx_status->link_id = rtwvif_link->link_id;
3049 }
3050
3051 if (ieee80211_is_beacon(hdr->frame_control)) {
3052 if (vif->type == NL80211_IFTYPE_STATION &&
3053 !test_bit(RTW89_FLAG_WOWLAN, rtwdev->flags)) {
3054 rtw89_vif_sync_bcn_tsf(rtwvif_link, hdr, skb->len);
3055 rtw89_fw_h2c_rssi_offload(rtwdev, phy_ppdu);
3056 }
3057
3058 if (phy_ppdu) {
3059 ewma_rssi_add(&rtwdev->phystat.bcn_rssi, phy_ppdu->rssi_avg);
3060 if (!test_bit(RTW89_FLAG_LOW_POWER_MODE, rtwdev->flags))
3061 rtwvif_link->bcn_bw_idx = phy_ppdu->bw_idx;
3062 }
3063
3064 pkt_stat->beacon_nr++;
3065 pkt_stat->beacon_rate = desc_info->data_rate;
3066 pkt_stat->beacon_len = skb->len;
3067
3068 rtw89_vif_rx_bcn_stat(rtwdev, skb);
3069 }
3070
3071 if (!ether_addr_equal(bss_conf->addr, hdr->addr1))
3072 goto out;
3073
3074 if (desc_info->data_rate < RTW89_HW_RATE_NR)
3075 pkt_stat->rx_rate_cnt[desc_info->data_rate]++;
3076
3077 rtw89_traffic_stats_accu(rtwdev, rtwvif, skb, false, false);
3078
3079 out:
3080 rcu_read_unlock();
3081 }
3082
rtw89_core_rx_stats(struct rtw89_dev * rtwdev,struct rtw89_rx_phy_ppdu * phy_ppdu,struct rtw89_rx_desc_info * desc_info,struct sk_buff * skb)3083 static void rtw89_core_rx_stats(struct rtw89_dev *rtwdev,
3084 struct rtw89_rx_phy_ppdu *phy_ppdu,
3085 struct rtw89_rx_desc_info *desc_info,
3086 struct sk_buff *skb)
3087 {
3088 struct rtw89_vif_rx_stats_iter_data iter_data;
3089
3090 rtw89_traffic_stats_accu(rtwdev, NULL, skb, true, false);
3091
3092 iter_data.rtwdev = rtwdev;
3093 iter_data.phy_ppdu = phy_ppdu;
3094 iter_data.desc_info = desc_info;
3095 iter_data.skb = skb;
3096 iter_data.bssid = get_hdr_bssid((struct ieee80211_hdr *)skb->data);
3097 rtw89_iterate_vifs_bh(rtwdev, rtw89_vif_rx_stats_iter, &iter_data);
3098 }
3099
rtw89_correct_cck_chan(struct rtw89_dev * rtwdev,struct ieee80211_rx_status * status)3100 static void rtw89_correct_cck_chan(struct rtw89_dev *rtwdev,
3101 struct ieee80211_rx_status *status)
3102 {
3103 const struct rtw89_chan_rcd *rcd =
3104 rtw89_chan_rcd_get(rtwdev, RTW89_CHANCTX_0);
3105 u16 chan = rcd->prev_primary_channel;
3106 u8 band = rtw89_hw_to_nl80211_band(rcd->prev_band_type);
3107
3108 if (status->band != NL80211_BAND_2GHZ &&
3109 status->encoding == RX_ENC_LEGACY &&
3110 status->rate_idx < RTW89_HW_RATE_OFDM6) {
3111 status->freq = ieee80211_channel_to_frequency(chan, band);
3112 status->band = band;
3113 }
3114 }
3115
rtw89_core_hw_to_sband_rate(struct ieee80211_rx_status * rx_status)3116 static void rtw89_core_hw_to_sband_rate(struct ieee80211_rx_status *rx_status)
3117 {
3118 if (rx_status->band == NL80211_BAND_2GHZ ||
3119 rx_status->encoding != RX_ENC_LEGACY)
3120 return;
3121
3122 /* Some control frames' freq(ACKs in this case) are reported wrong due
3123 * to FW notify timing, set to lowest rate to prevent overflow.
3124 */
3125 if (rx_status->rate_idx < RTW89_HW_RATE_OFDM6) {
3126 rx_status->rate_idx = 0;
3127 return;
3128 }
3129
3130 /* No 4 CCK rates for non-2G */
3131 rx_status->rate_idx -= 4;
3132 }
3133
3134 static
rtw89_core_update_rx_status_by_ppdu(struct rtw89_dev * rtwdev,struct ieee80211_rx_status * rx_status,struct rtw89_rx_phy_ppdu * phy_ppdu)3135 void rtw89_core_update_rx_status_by_ppdu(struct rtw89_dev *rtwdev,
3136 struct ieee80211_rx_status *rx_status,
3137 struct rtw89_rx_phy_ppdu *phy_ppdu)
3138 {
3139 if (!(rtwdev->hw->conf.flags & IEEE80211_CONF_MONITOR))
3140 return;
3141
3142 if (!phy_ppdu)
3143 return;
3144
3145 if (phy_ppdu->ldpc)
3146 rx_status->enc_flags |= RX_ENC_FLAG_LDPC;
3147 if (phy_ppdu->stbc)
3148 rx_status->enc_flags |= u8_encode_bits(1, RX_ENC_FLAG_STBC_MASK);
3149 }
3150
3151 static const u8 rx_status_bw_to_radiotap_eht_usig[] = {
3152 [RATE_INFO_BW_20] = IEEE80211_RADIOTAP_EHT_USIG_COMMON_BW_20MHZ,
3153 [RATE_INFO_BW_5] = U8_MAX,
3154 [RATE_INFO_BW_10] = U8_MAX,
3155 [RATE_INFO_BW_40] = IEEE80211_RADIOTAP_EHT_USIG_COMMON_BW_40MHZ,
3156 [RATE_INFO_BW_80] = IEEE80211_RADIOTAP_EHT_USIG_COMMON_BW_80MHZ,
3157 [RATE_INFO_BW_160] = IEEE80211_RADIOTAP_EHT_USIG_COMMON_BW_160MHZ,
3158 [RATE_INFO_BW_HE_RU] = U8_MAX,
3159 [RATE_INFO_BW_320] = IEEE80211_RADIOTAP_EHT_USIG_COMMON_BW_320MHZ_1,
3160 [RATE_INFO_BW_EHT_RU] = U8_MAX,
3161 };
3162
rtw89_core_update_radiotap_eht(struct rtw89_dev * rtwdev,struct sk_buff * skb,struct ieee80211_rx_status * rx_status)3163 static void rtw89_core_update_radiotap_eht(struct rtw89_dev *rtwdev,
3164 struct sk_buff *skb,
3165 struct ieee80211_rx_status *rx_status)
3166 {
3167 struct ieee80211_radiotap_eht_usig *usig;
3168 struct ieee80211_radiotap_eht *eht;
3169 struct ieee80211_radiotap_tlv *tlv;
3170 int eht_len = struct_size(eht, user_info, 1);
3171 int usig_len = sizeof(*usig);
3172 int len;
3173 u8 bw;
3174
3175 len = sizeof(*tlv) + ALIGN(eht_len, 4) +
3176 sizeof(*tlv) + ALIGN(usig_len, 4);
3177
3178 rx_status->flag |= RX_FLAG_RADIOTAP_TLV_AT_END;
3179 skb_reset_mac_header(skb);
3180
3181 /* EHT */
3182 tlv = skb_push(skb, len);
3183 memset(tlv, 0, len);
3184 tlv->type = cpu_to_le16(IEEE80211_RADIOTAP_EHT);
3185 tlv->len = cpu_to_le16(eht_len);
3186
3187 eht = (struct ieee80211_radiotap_eht *)tlv->data;
3188 eht->known = cpu_to_le32(IEEE80211_RADIOTAP_EHT_KNOWN_GI);
3189 eht->data[0] =
3190 le32_encode_bits(rx_status->eht.gi, IEEE80211_RADIOTAP_EHT_DATA0_GI);
3191
3192 eht->user_info[0] =
3193 cpu_to_le32(IEEE80211_RADIOTAP_EHT_USER_INFO_MCS_KNOWN |
3194 IEEE80211_RADIOTAP_EHT_USER_INFO_NSS_KNOWN_O |
3195 IEEE80211_RADIOTAP_EHT_USER_INFO_CODING_KNOWN);
3196 eht->user_info[0] |=
3197 le32_encode_bits(rx_status->rate_idx, IEEE80211_RADIOTAP_EHT_USER_INFO_MCS) |
3198 le32_encode_bits(rx_status->nss, IEEE80211_RADIOTAP_EHT_USER_INFO_NSS_O);
3199 if (rx_status->enc_flags & RX_ENC_FLAG_LDPC)
3200 eht->user_info[0] |=
3201 cpu_to_le32(IEEE80211_RADIOTAP_EHT_USER_INFO_CODING);
3202
3203 /* U-SIG */
3204 #if defined(__linux__)
3205 tlv = (void *)tlv + sizeof(*tlv) + ALIGN(eht_len, 4);
3206 #elif defined(__FreeBSD__)
3207 tlv = (void *)((u8 *)tlv + sizeof(*tlv) + ALIGN(eht_len, 4));
3208 #endif
3209 tlv->type = cpu_to_le16(IEEE80211_RADIOTAP_EHT_USIG);
3210 tlv->len = cpu_to_le16(usig_len);
3211
3212 if (rx_status->bw >= ARRAY_SIZE(rx_status_bw_to_radiotap_eht_usig))
3213 return;
3214
3215 bw = rx_status_bw_to_radiotap_eht_usig[rx_status->bw];
3216 if (bw == U8_MAX)
3217 return;
3218
3219 usig = (struct ieee80211_radiotap_eht_usig *)tlv->data;
3220 usig->common =
3221 le32_encode_bits(1, IEEE80211_RADIOTAP_EHT_USIG_COMMON_BW_KNOWN) |
3222 le32_encode_bits(bw, IEEE80211_RADIOTAP_EHT_USIG_COMMON_BW);
3223 }
3224
rtw89_core_update_radiotap(struct rtw89_dev * rtwdev,struct sk_buff * skb,struct ieee80211_rx_status * rx_status)3225 static void rtw89_core_update_radiotap(struct rtw89_dev *rtwdev,
3226 struct sk_buff *skb,
3227 struct ieee80211_rx_status *rx_status)
3228 {
3229 static const struct ieee80211_radiotap_he known_he = {
3230 .data1 = cpu_to_le16(IEEE80211_RADIOTAP_HE_DATA1_DATA_MCS_KNOWN |
3231 IEEE80211_RADIOTAP_HE_DATA1_CODING_KNOWN |
3232 IEEE80211_RADIOTAP_HE_DATA1_STBC_KNOWN |
3233 IEEE80211_RADIOTAP_HE_DATA1_BW_RU_ALLOC_KNOWN),
3234 .data2 = cpu_to_le16(IEEE80211_RADIOTAP_HE_DATA2_GI_KNOWN),
3235 };
3236 struct ieee80211_radiotap_he *he;
3237
3238 if (!(rtwdev->hw->conf.flags & IEEE80211_CONF_MONITOR))
3239 return;
3240
3241 if (rx_status->encoding == RX_ENC_HE) {
3242 rx_status->flag |= RX_FLAG_RADIOTAP_HE;
3243 he = skb_push(skb, sizeof(*he));
3244 *he = known_he;
3245 } else if (rx_status->encoding == RX_ENC_EHT) {
3246 rtw89_core_update_radiotap_eht(rtwdev, skb, rx_status);
3247 }
3248 }
3249
rtw89_core_validate_rx_signal(struct ieee80211_rx_status * rx_status)3250 static void rtw89_core_validate_rx_signal(struct ieee80211_rx_status *rx_status)
3251 {
3252 if (!rx_status->signal)
3253 rx_status->flag |= RX_FLAG_NO_SIGNAL_VAL;
3254 }
3255
rtw89_core_update_rx_freq_from_ie(struct rtw89_dev * rtwdev,struct sk_buff * skb,struct ieee80211_rx_status * rx_status)3256 static void rtw89_core_update_rx_freq_from_ie(struct rtw89_dev *rtwdev,
3257 struct sk_buff *skb,
3258 struct ieee80211_rx_status *rx_status)
3259 {
3260 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
3261 size_t hdr_len, ielen;
3262 u8 *variable;
3263 int chan;
3264
3265 if (!rtwdev->chip->rx_freq_frome_ie)
3266 return;
3267
3268 if (!rtwdev->scanning)
3269 return;
3270
3271 if (ieee80211_is_beacon(mgmt->frame_control)) {
3272 variable = mgmt->u.beacon.variable;
3273 hdr_len = offsetof(struct ieee80211_mgmt,
3274 u.beacon.variable);
3275 } else if (ieee80211_is_probe_resp(mgmt->frame_control)) {
3276 variable = mgmt->u.probe_resp.variable;
3277 hdr_len = offsetof(struct ieee80211_mgmt,
3278 u.probe_resp.variable);
3279 } else {
3280 return;
3281 }
3282
3283 if (skb->len > hdr_len)
3284 ielen = skb->len - hdr_len;
3285 else
3286 return;
3287
3288 /* The parsing code for both 2GHz and 5GHz bands is the same in this
3289 * function.
3290 */
3291 chan = cfg80211_get_ies_channel_number(variable, ielen, NL80211_BAND_2GHZ);
3292 if (chan == -1)
3293 return;
3294
3295 rx_status->band = chan > 14 ? RTW89_BAND_5G : RTW89_BAND_2G;
3296 rx_status->freq = ieee80211_channel_to_frequency(chan, rx_status->band);
3297 }
3298
rtw89_core_correct_mcc_chan(struct rtw89_dev * rtwdev,struct rtw89_rx_desc_info * desc_info,struct ieee80211_rx_status * rx_status,struct rtw89_rx_phy_ppdu * phy_ppdu)3299 static void rtw89_core_correct_mcc_chan(struct rtw89_dev *rtwdev,
3300 struct rtw89_rx_desc_info *desc_info,
3301 struct ieee80211_rx_status *rx_status,
3302 struct rtw89_rx_phy_ppdu *phy_ppdu)
3303 {
3304 enum rtw89_chip_gen chip_gen = rtwdev->chip->chip_gen;
3305 struct rtw89_vif_link *rtwvif_link;
3306 struct rtw89_sta_link *rtwsta_link;
3307 const struct rtw89_chan *chan;
3308 u8 mac_id = desc_info->mac_id;
3309 enum rtw89_entity_mode mode;
3310 enum nl80211_band band;
3311
3312 mode = rtw89_get_entity_mode(rtwdev);
3313 if (likely(mode != RTW89_ENTITY_MODE_MCC))
3314 return;
3315
3316 if (chip_gen == RTW89_CHIP_BE && phy_ppdu)
3317 mac_id = phy_ppdu->mac_id;
3318
3319 rcu_read_lock();
3320
3321 rtwsta_link = rtw89_assoc_link_rcu_dereference(rtwdev, mac_id);
3322 if (!rtwsta_link)
3323 goto out;
3324
3325 rtwvif_link = rtwsta_link->rtwvif_link;
3326 chan = rtw89_chan_get(rtwdev, rtwvif_link->chanctx_idx);
3327 band = rtw89_hw_to_nl80211_band(chan->band_type);
3328 rx_status->freq = ieee80211_channel_to_frequency(chan->primary_channel, band);
3329
3330 out:
3331 rcu_read_unlock();
3332 }
3333
rtw89_core_rx_to_mac80211(struct rtw89_dev * rtwdev,struct rtw89_rx_phy_ppdu * phy_ppdu,struct rtw89_rx_desc_info * desc_info,struct sk_buff * skb_ppdu,struct ieee80211_rx_status * rx_status)3334 static void rtw89_core_rx_to_mac80211(struct rtw89_dev *rtwdev,
3335 struct rtw89_rx_phy_ppdu *phy_ppdu,
3336 struct rtw89_rx_desc_info *desc_info,
3337 struct sk_buff *skb_ppdu,
3338 struct ieee80211_rx_status *rx_status)
3339 {
3340 struct napi_struct *napi = &rtwdev->napi;
3341
3342 /* In low power mode, napi isn't scheduled. Receive it to netif. */
3343 if (unlikely(!napi_is_scheduled(napi)))
3344 napi = NULL;
3345
3346 rtw89_core_hw_to_sband_rate(rx_status);
3347 rtw89_core_rx_stats(rtwdev, phy_ppdu, desc_info, skb_ppdu);
3348 rtw89_core_update_rx_status_by_ppdu(rtwdev, rx_status, phy_ppdu);
3349 rtw89_core_update_radiotap(rtwdev, skb_ppdu, rx_status);
3350 rtw89_core_validate_rx_signal(rx_status);
3351 rtw89_core_update_rx_freq_from_ie(rtwdev, skb_ppdu, rx_status);
3352 rtw89_core_correct_mcc_chan(rtwdev, desc_info, rx_status, phy_ppdu);
3353
3354 /* In low power mode, it does RX in thread context. */
3355 local_bh_disable();
3356 ieee80211_rx_napi(rtwdev->hw, NULL, skb_ppdu, napi);
3357 local_bh_enable();
3358 rtwdev->napi_budget_countdown--;
3359 }
3360
rtw89_core_rx_pending_skb(struct rtw89_dev * rtwdev,struct rtw89_rx_phy_ppdu * phy_ppdu,struct rtw89_rx_desc_info * desc_info,struct sk_buff * skb)3361 static void rtw89_core_rx_pending_skb(struct rtw89_dev *rtwdev,
3362 struct rtw89_rx_phy_ppdu *phy_ppdu,
3363 struct rtw89_rx_desc_info *desc_info,
3364 struct sk_buff *skb)
3365 {
3366 u8 band = desc_info->bb_sel ? RTW89_PHY_1 : RTW89_PHY_0;
3367 int curr = rtwdev->ppdu_sts.curr_rx_ppdu_cnt[band];
3368 struct sk_buff *skb_ppdu = NULL, *tmp;
3369 struct ieee80211_rx_status *rx_status;
3370
3371 if (curr > RTW89_MAX_PPDU_CNT)
3372 return;
3373
3374 skb_queue_walk_safe(&rtwdev->ppdu_sts.rx_queue[band], skb_ppdu, tmp) {
3375 skb_unlink(skb_ppdu, &rtwdev->ppdu_sts.rx_queue[band]);
3376 rx_status = IEEE80211_SKB_RXCB(skb_ppdu);
3377 if (rtw89_core_rx_ppdu_match(rtwdev, desc_info, rx_status))
3378 rtw89_chip_query_ppdu(rtwdev, phy_ppdu, rx_status);
3379 rtw89_correct_cck_chan(rtwdev, rx_status);
3380 rtw89_core_rx_to_mac80211(rtwdev, phy_ppdu, desc_info, skb_ppdu, rx_status);
3381 }
3382 }
3383
rtw89_core_rx_process_ppdu_sts(struct rtw89_dev * rtwdev,struct rtw89_rx_desc_info * desc_info,struct sk_buff * skb)3384 static void rtw89_core_rx_process_ppdu_sts(struct rtw89_dev *rtwdev,
3385 struct rtw89_rx_desc_info *desc_info,
3386 struct sk_buff *skb)
3387 {
3388 struct rtw89_rx_phy_ppdu phy_ppdu = {.buf = skb->data, .valid = false,
3389 .len = skb->len,
3390 .to_self = desc_info->addr1_match,
3391 .rate = desc_info->data_rate,
3392 .mac_id = desc_info->mac_id,
3393 .phy_idx = desc_info->bb_sel};
3394 int ret;
3395
3396 if (desc_info->mac_info_valid) {
3397 ret = rtw89_core_rx_process_mac_ppdu(rtwdev, skb, &phy_ppdu);
3398 if (ret)
3399 goto out;
3400 }
3401
3402 ret = rtw89_core_rx_process_phy_ppdu(rtwdev, &phy_ppdu);
3403 if (ret)
3404 goto out;
3405
3406 rtw89_core_rx_process_phy_sts(rtwdev, &phy_ppdu);
3407
3408 out:
3409 rtw89_core_rx_pending_skb(rtwdev, &phy_ppdu, desc_info, skb);
3410 dev_kfree_skb_any(skb);
3411 }
3412
rtw89_core_rx_process_report(struct rtw89_dev * rtwdev,struct rtw89_rx_desc_info * desc_info,struct sk_buff * skb)3413 static void rtw89_core_rx_process_report(struct rtw89_dev *rtwdev,
3414 struct rtw89_rx_desc_info *desc_info,
3415 struct sk_buff *skb)
3416 {
3417 switch (desc_info->pkt_type) {
3418 case RTW89_CORE_RX_TYPE_C2H:
3419 rtw89_fw_c2h_irqsafe(rtwdev, skb);
3420 break;
3421 case RTW89_CORE_RX_TYPE_PPDU_STAT:
3422 rtw89_core_rx_process_ppdu_sts(rtwdev, desc_info, skb);
3423 break;
3424 default:
3425 rtw89_debug(rtwdev, RTW89_DBG_TXRX, "unhandled pkt_type=%d\n",
3426 desc_info->pkt_type);
3427 dev_kfree_skb_any(skb);
3428 break;
3429 }
3430 }
3431
rtw89_core_query_rxdesc(struct rtw89_dev * rtwdev,struct rtw89_rx_desc_info * desc_info,u8 * data,u32 data_offset)3432 void rtw89_core_query_rxdesc(struct rtw89_dev *rtwdev,
3433 struct rtw89_rx_desc_info *desc_info,
3434 u8 *data, u32 data_offset)
3435 {
3436 const struct rtw89_chip_info *chip = rtwdev->chip;
3437 struct rtw89_rxdesc_short *rxd_s;
3438 struct rtw89_rxdesc_long *rxd_l;
3439 u8 shift_len, drv_info_len;
3440
3441 rxd_s = (struct rtw89_rxdesc_short *)(data + data_offset);
3442 desc_info->pkt_size = le32_get_bits(rxd_s->dword0, AX_RXD_RPKT_LEN_MASK);
3443 desc_info->drv_info_size = le32_get_bits(rxd_s->dword0, AX_RXD_DRV_INFO_SIZE_MASK);
3444 desc_info->long_rxdesc = le32_get_bits(rxd_s->dword0, AX_RXD_LONG_RXD);
3445 desc_info->pkt_type = le32_get_bits(rxd_s->dword0, AX_RXD_RPKT_TYPE_MASK);
3446 desc_info->mac_info_valid = le32_get_bits(rxd_s->dword0, AX_RXD_MAC_INFO_VLD);
3447 if (chip->chip_id == RTL8852C)
3448 desc_info->bw = le32_get_bits(rxd_s->dword1, AX_RXD_BW_v1_MASK);
3449 else
3450 desc_info->bw = le32_get_bits(rxd_s->dword1, AX_RXD_BW_MASK);
3451 desc_info->data_rate = le32_get_bits(rxd_s->dword1, AX_RXD_RX_DATARATE_MASK);
3452 desc_info->gi_ltf = le32_get_bits(rxd_s->dword1, AX_RXD_RX_GI_LTF_MASK);
3453 desc_info->user_id = le32_get_bits(rxd_s->dword1, AX_RXD_USER_ID_MASK);
3454 desc_info->sr_en = le32_get_bits(rxd_s->dword1, AX_RXD_SR_EN);
3455 desc_info->ppdu_cnt = le32_get_bits(rxd_s->dword1, AX_RXD_PPDU_CNT_MASK);
3456 desc_info->ppdu_type = le32_get_bits(rxd_s->dword1, AX_RXD_PPDU_TYPE_MASK);
3457 desc_info->free_run_cnt = le32_get_bits(rxd_s->dword2, AX_RXD_FREERUN_CNT_MASK);
3458 desc_info->icv_err = le32_get_bits(rxd_s->dword3, AX_RXD_ICV_ERR);
3459 desc_info->crc32_err = le32_get_bits(rxd_s->dword3, AX_RXD_CRC32_ERR);
3460 desc_info->hw_dec = le32_get_bits(rxd_s->dword3, AX_RXD_HW_DEC);
3461 desc_info->sw_dec = le32_get_bits(rxd_s->dword3, AX_RXD_SW_DEC);
3462 desc_info->addr1_match = le32_get_bits(rxd_s->dword3, AX_RXD_A1_MATCH);
3463
3464 shift_len = desc_info->shift << 1; /* 2-byte unit */
3465 drv_info_len = desc_info->drv_info_size << 3; /* 8-byte unit */
3466 desc_info->offset = data_offset + shift_len + drv_info_len;
3467 if (desc_info->long_rxdesc)
3468 desc_info->rxd_len = sizeof(struct rtw89_rxdesc_long);
3469 else
3470 desc_info->rxd_len = sizeof(struct rtw89_rxdesc_short);
3471 desc_info->ready = true;
3472
3473 if (!desc_info->long_rxdesc)
3474 return;
3475
3476 rxd_l = (struct rtw89_rxdesc_long *)(data + data_offset);
3477 desc_info->frame_type = le32_get_bits(rxd_l->dword4, AX_RXD_TYPE_MASK);
3478 desc_info->addr_cam_valid = le32_get_bits(rxd_l->dword5, AX_RXD_ADDR_CAM_VLD);
3479 desc_info->addr_cam_id = le32_get_bits(rxd_l->dword5, AX_RXD_ADDR_CAM_MASK);
3480 desc_info->sec_cam_id = le32_get_bits(rxd_l->dword5, AX_RXD_SEC_CAM_IDX_MASK);
3481 desc_info->mac_id = le32_get_bits(rxd_l->dword5, AX_RXD_MAC_ID_MASK);
3482 desc_info->rx_pl_id = le32_get_bits(rxd_l->dword5, AX_RXD_RX_PL_ID_MASK);
3483 }
3484 EXPORT_SYMBOL(rtw89_core_query_rxdesc);
3485
rtw89_core_query_rxdesc_v2(struct rtw89_dev * rtwdev,struct rtw89_rx_desc_info * desc_info,u8 * data,u32 data_offset)3486 void rtw89_core_query_rxdesc_v2(struct rtw89_dev *rtwdev,
3487 struct rtw89_rx_desc_info *desc_info,
3488 u8 *data, u32 data_offset)
3489 {
3490 struct rtw89_rxdesc_phy_rpt_v2 *rxd_rpt;
3491 struct rtw89_rxdesc_short_v2 *rxd_s;
3492 struct rtw89_rxdesc_long_v2 *rxd_l;
3493 u16 shift_len, drv_info_len, phy_rtp_len, hdr_cnv_len;
3494
3495 rxd_s = (struct rtw89_rxdesc_short_v2 *)(data + data_offset);
3496
3497 desc_info->pkt_size = le32_get_bits(rxd_s->dword0, BE_RXD_RPKT_LEN_MASK);
3498 desc_info->drv_info_size = le32_get_bits(rxd_s->dword0, BE_RXD_DRV_INFO_SZ_MASK);
3499 desc_info->phy_rpt_size = le32_get_bits(rxd_s->dword0, BE_RXD_PHY_RPT_SZ_MASK);
3500 desc_info->hdr_cnv_size = le32_get_bits(rxd_s->dword0, BE_RXD_HDR_CNV_SZ_MASK);
3501 desc_info->shift = le32_get_bits(rxd_s->dword0, BE_RXD_SHIFT_MASK);
3502 desc_info->long_rxdesc = le32_get_bits(rxd_s->dword0, BE_RXD_LONG_RXD);
3503 desc_info->pkt_type = le32_get_bits(rxd_s->dword0, BE_RXD_RPKT_TYPE_MASK);
3504 desc_info->bb_sel = le32_get_bits(rxd_s->dword0, BE_RXD_BB_SEL);
3505 if (desc_info->pkt_type == RTW89_CORE_RX_TYPE_PPDU_STAT)
3506 desc_info->mac_info_valid = true;
3507
3508 desc_info->frame_type = le32_get_bits(rxd_s->dword2, BE_RXD_TYPE_MASK);
3509 desc_info->mac_id = le32_get_bits(rxd_s->dword2, BE_RXD_MAC_ID_MASK);
3510 desc_info->addr_cam_valid = le32_get_bits(rxd_s->dword2, BE_RXD_ADDR_CAM_VLD);
3511
3512 desc_info->icv_err = le32_get_bits(rxd_s->dword3, BE_RXD_ICV_ERR);
3513 desc_info->crc32_err = le32_get_bits(rxd_s->dword3, BE_RXD_CRC32_ERR);
3514 desc_info->hw_dec = le32_get_bits(rxd_s->dword3, BE_RXD_HW_DEC);
3515 desc_info->sw_dec = le32_get_bits(rxd_s->dword3, BE_RXD_SW_DEC);
3516 desc_info->addr1_match = le32_get_bits(rxd_s->dword3, BE_RXD_A1_MATCH);
3517
3518 desc_info->bw = le32_get_bits(rxd_s->dword4, BE_RXD_BW_MASK);
3519 desc_info->data_rate = le32_get_bits(rxd_s->dword4, BE_RXD_RX_DATARATE_MASK);
3520 desc_info->gi_ltf = le32_get_bits(rxd_s->dword4, BE_RXD_RX_GI_LTF_MASK);
3521 desc_info->ppdu_cnt = le32_get_bits(rxd_s->dword4, BE_RXD_PPDU_CNT_MASK);
3522 desc_info->ppdu_type = le32_get_bits(rxd_s->dword4, BE_RXD_PPDU_TYPE_MASK);
3523
3524 desc_info->free_run_cnt = le32_to_cpu(rxd_s->dword5);
3525
3526 shift_len = desc_info->shift << 1; /* 2-byte unit */
3527 drv_info_len = desc_info->drv_info_size << 3; /* 8-byte unit */
3528 phy_rtp_len = desc_info->phy_rpt_size << 3; /* 8-byte unit */
3529 hdr_cnv_len = desc_info->hdr_cnv_size << 4; /* 16-byte unit */
3530 desc_info->offset = data_offset + shift_len + drv_info_len +
3531 phy_rtp_len + hdr_cnv_len;
3532
3533 if (desc_info->long_rxdesc)
3534 desc_info->rxd_len = sizeof(struct rtw89_rxdesc_long_v2);
3535 else
3536 desc_info->rxd_len = sizeof(struct rtw89_rxdesc_short_v2);
3537 desc_info->ready = true;
3538
3539 if (phy_rtp_len == sizeof(*rxd_rpt)) {
3540 rxd_rpt = (struct rtw89_rxdesc_phy_rpt_v2 *)(data + data_offset +
3541 desc_info->rxd_len);
3542 desc_info->rssi = le32_get_bits(rxd_rpt->dword0, BE_RXD_PHY_RSSI);
3543 }
3544
3545 if (!desc_info->long_rxdesc)
3546 return;
3547
3548 rxd_l = (struct rtw89_rxdesc_long_v2 *)(data + data_offset);
3549
3550 desc_info->sr_en = le32_get_bits(rxd_l->dword6, BE_RXD_SR_EN);
3551 desc_info->user_id = le32_get_bits(rxd_l->dword6, BE_RXD_USER_ID_MASK);
3552 desc_info->addr_cam_id = le32_get_bits(rxd_l->dword6, BE_RXD_ADDR_CAM_MASK);
3553 desc_info->sec_cam_id = le32_get_bits(rxd_l->dword6, BE_RXD_SEC_CAM_IDX_MASK);
3554
3555 desc_info->rx_pl_id = le32_get_bits(rxd_l->dword7, BE_RXD_RX_PL_ID_MASK);
3556 }
3557 EXPORT_SYMBOL(rtw89_core_query_rxdesc_v2);
3558
rtw89_core_query_rxdesc_v3(struct rtw89_dev * rtwdev,struct rtw89_rx_desc_info * desc_info,u8 * data,u32 data_offset)3559 void rtw89_core_query_rxdesc_v3(struct rtw89_dev *rtwdev,
3560 struct rtw89_rx_desc_info *desc_info,
3561 u8 *data, u32 data_offset)
3562 {
3563 struct rtw89_rxdesc_phy_rpt_v2 *rxd_rpt;
3564 struct rtw89_rxdesc_short_v3 *rxd_s;
3565 struct rtw89_rxdesc_long_v3 *rxd_l;
3566 u16 shift_len, drv_info_len, phy_rtp_len, hdr_cnv_len;
3567
3568 rxd_s = (struct rtw89_rxdesc_short_v3 *)(data + data_offset);
3569
3570 desc_info->pkt_size = le32_get_bits(rxd_s->dword0, BE_RXD_RPKT_LEN_MASK);
3571 desc_info->drv_info_size = le32_get_bits(rxd_s->dword0, BE_RXD_DRV_INFO_SZ_MASK);
3572 desc_info->phy_rpt_size = le32_get_bits(rxd_s->dword0, BE_RXD_PHY_RPT_SZ_MASK);
3573 desc_info->hdr_cnv_size = le32_get_bits(rxd_s->dword0, BE_RXD_HDR_CNV_SZ_MASK);
3574 desc_info->shift = le32_get_bits(rxd_s->dword0, BE_RXD_SHIFT_MASK);
3575 desc_info->long_rxdesc = le32_get_bits(rxd_s->dword0, BE_RXD_LONG_RXD);
3576 desc_info->pkt_type = le32_get_bits(rxd_s->dword0, BE_RXD_RPKT_TYPE_MASK);
3577 desc_info->bb_sel = le32_get_bits(rxd_s->dword0, BE_RXD_BB_SEL);
3578 if (desc_info->pkt_type == RTW89_CORE_RX_TYPE_PPDU_STAT)
3579 desc_info->mac_info_valid = true;
3580
3581 desc_info->frame_type = le32_get_bits(rxd_s->dword2, BE_RXD_TYPE_MASK);
3582 desc_info->mac_id = le32_get_bits(rxd_s->dword2, BE_RXD_MAC_ID_V1);
3583 desc_info->addr_cam_valid = le32_get_bits(rxd_s->dword2, BE_RXD_ADDR_CAM_VLD);
3584
3585 desc_info->icv_err = le32_get_bits(rxd_s->dword3, BE_RXD_ICV_ERR);
3586 desc_info->crc32_err = le32_get_bits(rxd_s->dword3, BE_RXD_CRC32_ERR);
3587 desc_info->hw_dec = le32_get_bits(rxd_s->dword3, BE_RXD_HW_DEC);
3588 desc_info->sw_dec = le32_get_bits(rxd_s->dword3, BE_RXD_SW_DEC);
3589 desc_info->addr1_match = le32_get_bits(rxd_s->dword3, BE_RXD_A1_MATCH);
3590
3591 desc_info->bw = le32_get_bits(rxd_s->dword4, BE_RXD_BW_MASK);
3592 desc_info->data_rate = le32_get_bits(rxd_s->dword4, BE_RXD_RX_DATARATE_MASK);
3593 desc_info->gi_ltf = le32_get_bits(rxd_s->dword4, BE_RXD_RX_GI_LTF_MASK);
3594 desc_info->ppdu_cnt = le32_get_bits(rxd_s->dword4, BE_RXD_PPDU_CNT_MASK);
3595 desc_info->ppdu_type = le32_get_bits(rxd_s->dword4, BE_RXD_PPDU_TYPE_MASK);
3596
3597 desc_info->free_run_cnt = le32_to_cpu(rxd_s->dword5);
3598
3599 shift_len = desc_info->shift << 1; /* 2-byte unit */
3600 drv_info_len = desc_info->drv_info_size << 3; /* 8-byte unit */
3601 phy_rtp_len = desc_info->phy_rpt_size << 3; /* 8-byte unit */
3602 hdr_cnv_len = desc_info->hdr_cnv_size << 4; /* 16-byte unit */
3603 desc_info->offset = data_offset + shift_len + drv_info_len +
3604 phy_rtp_len + hdr_cnv_len;
3605
3606 if (desc_info->long_rxdesc)
3607 desc_info->rxd_len = sizeof(struct rtw89_rxdesc_long_v3);
3608 else
3609 desc_info->rxd_len = sizeof(struct rtw89_rxdesc_short_v3);
3610 desc_info->ready = true;
3611
3612 if (phy_rtp_len == sizeof(*rxd_rpt)) {
3613 rxd_rpt = (struct rtw89_rxdesc_phy_rpt_v2 *)(data + data_offset +
3614 desc_info->rxd_len);
3615 desc_info->rssi = le32_get_bits(rxd_rpt->dword0, BE_RXD_PHY_RSSI);
3616 }
3617
3618 if (!desc_info->long_rxdesc)
3619 return;
3620
3621 rxd_l = (struct rtw89_rxdesc_long_v3 *)(data + data_offset);
3622
3623 desc_info->sr_en = le32_get_bits(rxd_l->dword6, BE_RXD_SR_EN);
3624 desc_info->user_id = le32_get_bits(rxd_l->dword6, BE_RXD_USER_ID_MASK);
3625 desc_info->addr_cam_id = le32_get_bits(rxd_l->dword6, BE_RXD_ADDR_CAM_V1);
3626 desc_info->sec_cam_id = le32_get_bits(rxd_l->dword6, BE_RXD_SEC_CAM_IDX_V1);
3627
3628 desc_info->rx_pl_id = le32_get_bits(rxd_l->dword7, BE_RXD_RX_PL_ID_MASK);
3629 }
3630 EXPORT_SYMBOL(rtw89_core_query_rxdesc_v3);
3631
3632 struct rtw89_core_iter_rx_status {
3633 struct rtw89_dev *rtwdev;
3634 struct ieee80211_rx_status *rx_status;
3635 struct rtw89_rx_desc_info *desc_info;
3636 u8 mac_id;
3637 };
3638
3639 static
rtw89_core_stats_sta_rx_status_iter(void * data,struct ieee80211_sta * sta)3640 void rtw89_core_stats_sta_rx_status_iter(void *data, struct ieee80211_sta *sta)
3641 {
3642 struct rtw89_core_iter_rx_status *iter_data =
3643 (struct rtw89_core_iter_rx_status *)data;
3644 struct ieee80211_rx_status *rx_status = iter_data->rx_status;
3645 struct rtw89_rx_desc_info *desc_info = iter_data->desc_info;
3646 struct rtw89_sta *rtwsta = sta_to_rtwsta(sta);
3647 struct rtw89_sta_link *rtwsta_link;
3648 u8 mac_id = iter_data->mac_id;
3649
3650 rtwsta_link = rtw89_sta_get_link_inst(rtwsta, desc_info->bb_sel);
3651 if (unlikely(!rtwsta_link))
3652 return;
3653
3654 if (mac_id != rtwsta_link->mac_id)
3655 return;
3656
3657 rtwsta_link->rx_status = *rx_status;
3658 rtwsta_link->rx_hw_rate = desc_info->data_rate;
3659 }
3660
rtw89_core_stats_sta_rx_status(struct rtw89_dev * rtwdev,struct rtw89_rx_desc_info * desc_info,struct ieee80211_rx_status * rx_status)3661 static void rtw89_core_stats_sta_rx_status(struct rtw89_dev *rtwdev,
3662 struct rtw89_rx_desc_info *desc_info,
3663 struct ieee80211_rx_status *rx_status)
3664 {
3665 struct rtw89_core_iter_rx_status iter_data;
3666
3667 if (!desc_info->addr1_match || !desc_info->long_rxdesc)
3668 return;
3669
3670 if (desc_info->frame_type != RTW89_RX_TYPE_DATA)
3671 return;
3672
3673 iter_data.rtwdev = rtwdev;
3674 iter_data.rx_status = rx_status;
3675 iter_data.desc_info = desc_info;
3676 iter_data.mac_id = desc_info->mac_id;
3677 ieee80211_iterate_stations_atomic(rtwdev->hw,
3678 rtw89_core_stats_sta_rx_status_iter,
3679 &iter_data);
3680 }
3681
rtw89_core_update_rx_status(struct rtw89_dev * rtwdev,struct sk_buff * skb,struct rtw89_rx_desc_info * desc_info,struct ieee80211_rx_status * rx_status)3682 static void rtw89_core_update_rx_status(struct rtw89_dev *rtwdev,
3683 struct sk_buff *skb,
3684 struct rtw89_rx_desc_info *desc_info,
3685 struct ieee80211_rx_status *rx_status)
3686 {
3687 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
3688 const struct cfg80211_chan_def *chandef =
3689 rtw89_chandef_get(rtwdev, RTW89_CHANCTX_0);
3690 u16 data_rate;
3691 u8 data_rate_mode;
3692 bool eht = false;
3693 u8 gi;
3694
3695 /* currently using single PHY */
3696 rx_status->freq = chandef->chan->center_freq;
3697 rx_status->band = chandef->chan->band;
3698
3699 if (ieee80211_is_beacon(hdr->frame_control) ||
3700 ieee80211_is_probe_resp(hdr->frame_control))
3701 rx_status->boottime_ns = ktime_get_boottime_ns();
3702
3703 if (rtwdev->scanning &&
3704 RTW89_CHK_FW_FEATURE(SCAN_OFFLOAD, &rtwdev->fw)) {
3705 const struct rtw89_chan *cur = rtw89_scan_chan_get(rtwdev);
3706 u8 chan = cur->primary_channel;
3707 u8 band = cur->band_type;
3708 enum nl80211_band nl_band;
3709
3710 nl_band = rtw89_hw_to_nl80211_band(band);
3711 rx_status->freq = ieee80211_channel_to_frequency(chan, nl_band);
3712 rx_status->band = nl_band;
3713 }
3714
3715 if (desc_info->icv_err || desc_info->crc32_err)
3716 rx_status->flag |= RX_FLAG_FAILED_FCS_CRC;
3717
3718 if (desc_info->hw_dec &&
3719 !(desc_info->sw_dec || desc_info->icv_err))
3720 rx_status->flag |= RX_FLAG_DECRYPTED;
3721
3722 rx_status->bw = rtw89_hw_to_rate_info_bw(desc_info->bw);
3723
3724 data_rate = desc_info->data_rate;
3725 data_rate_mode = rtw89_get_data_rate_mode(rtwdev, data_rate);
3726 if (data_rate_mode == DATA_RATE_MODE_NON_HT) {
3727 rx_status->encoding = RX_ENC_LEGACY;
3728 rx_status->rate_idx = rtw89_get_data_not_ht_idx(rtwdev, data_rate);
3729 /* convert rate_idx after we get the correct band */
3730 } else if (data_rate_mode == DATA_RATE_MODE_HT) {
3731 rx_status->encoding = RX_ENC_HT;
3732 rx_status->rate_idx = rtw89_get_data_ht_mcs(rtwdev, data_rate);
3733 if (desc_info->gi_ltf)
3734 rx_status->enc_flags |= RX_ENC_FLAG_SHORT_GI;
3735 } else if (data_rate_mode == DATA_RATE_MODE_VHT) {
3736 rx_status->encoding = RX_ENC_VHT;
3737 rx_status->rate_idx = rtw89_get_data_mcs(rtwdev, data_rate);
3738 rx_status->nss = rtw89_get_data_nss(rtwdev, data_rate) + 1;
3739 if (desc_info->gi_ltf)
3740 rx_status->enc_flags |= RX_ENC_FLAG_SHORT_GI;
3741 } else if (data_rate_mode == DATA_RATE_MODE_HE) {
3742 rx_status->encoding = RX_ENC_HE;
3743 rx_status->rate_idx = rtw89_get_data_mcs(rtwdev, data_rate);
3744 rx_status->nss = rtw89_get_data_nss(rtwdev, data_rate) + 1;
3745 } else if (data_rate_mode == DATA_RATE_MODE_EHT) {
3746 rx_status->encoding = RX_ENC_EHT;
3747 rx_status->rate_idx = rtw89_get_data_mcs(rtwdev, data_rate);
3748 rx_status->nss = rtw89_get_data_nss(rtwdev, data_rate) + 1;
3749 eht = true;
3750 } else {
3751 rtw89_warn(rtwdev, "invalid RX rate mode %d\n", data_rate_mode);
3752 }
3753
3754 /* he_gi is used to match ppdu, so we always fill it. */
3755 gi = rtw89_rxdesc_to_nl_he_eht_gi(rtwdev, desc_info->gi_ltf, true, eht);
3756 if (eht)
3757 rx_status->eht.gi = gi;
3758 else
3759 rx_status->he_gi = gi;
3760 rx_status->flag |= RX_FLAG_MACTIME_START;
3761 rx_status->mactime = desc_info->free_run_cnt;
3762
3763 rtw89_chip_phy_rpt_to_rssi(rtwdev, desc_info, rx_status);
3764 rtw89_core_stats_sta_rx_status(rtwdev, desc_info, rx_status);
3765 }
3766
rtw89_update_ps_mode(struct rtw89_dev * rtwdev)3767 static enum rtw89_ps_mode rtw89_update_ps_mode(struct rtw89_dev *rtwdev)
3768 {
3769 const struct rtw89_chip_info *chip = rtwdev->chip;
3770
3771 if (rtwdev->hci.type != RTW89_HCI_TYPE_PCIE)
3772 return RTW89_PS_MODE_NONE;
3773
3774 if (rtw89_disable_ps_mode || !chip->ps_mode_supported ||
3775 RTW89_CHK_FW_FEATURE(NO_DEEP_PS, &rtwdev->fw))
3776 return RTW89_PS_MODE_NONE;
3777
3778 if ((chip->ps_mode_supported & BIT(RTW89_PS_MODE_PWR_GATED)) &&
3779 !RTW89_CHK_FW_FEATURE(NO_LPS_PG, &rtwdev->fw))
3780 return RTW89_PS_MODE_PWR_GATED;
3781
3782 if (chip->ps_mode_supported & BIT(RTW89_PS_MODE_CLK_GATED))
3783 return RTW89_PS_MODE_CLK_GATED;
3784
3785 if (chip->ps_mode_supported & BIT(RTW89_PS_MODE_RFOFF))
3786 return RTW89_PS_MODE_RFOFF;
3787
3788 return RTW89_PS_MODE_NONE;
3789 }
3790
rtw89_core_flush_ppdu_rx_queue(struct rtw89_dev * rtwdev,struct rtw89_rx_desc_info * desc_info)3791 static void rtw89_core_flush_ppdu_rx_queue(struct rtw89_dev *rtwdev,
3792 struct rtw89_rx_desc_info *desc_info)
3793 {
3794 struct rtw89_ppdu_sts_info *ppdu_sts = &rtwdev->ppdu_sts;
3795 u8 band = desc_info->bb_sel ? RTW89_PHY_1 : RTW89_PHY_0;
3796 struct ieee80211_rx_status *rx_status;
3797 struct sk_buff *skb_ppdu, *tmp;
3798
3799 skb_queue_walk_safe(&ppdu_sts->rx_queue[band], skb_ppdu, tmp) {
3800 skb_unlink(skb_ppdu, &ppdu_sts->rx_queue[band]);
3801 rx_status = IEEE80211_SKB_RXCB(skb_ppdu);
3802 rtw89_core_rx_to_mac80211(rtwdev, NULL, desc_info, skb_ppdu, rx_status);
3803 }
3804 }
3805
3806 static
rtw89_core_rx_pkt_hdl(struct rtw89_dev * rtwdev,const struct sk_buff * skb,const struct rtw89_rx_desc_info * desc)3807 void rtw89_core_rx_pkt_hdl(struct rtw89_dev *rtwdev, const struct sk_buff *skb,
3808 const struct rtw89_rx_desc_info *desc)
3809 {
3810 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
3811 struct rtw89_sta_link *rtwsta_link;
3812 struct ieee80211_sta *sta;
3813 struct rtw89_sta *rtwsta;
3814 u8 macid = desc->mac_id;
3815
3816 if (!refcount_read(&rtwdev->refcount_ap_info))
3817 return;
3818
3819 rcu_read_lock();
3820
3821 rtwsta_link = rtw89_assoc_link_rcu_dereference(rtwdev, macid);
3822 if (!rtwsta_link)
3823 goto out;
3824
3825 rtwsta = rtwsta_link->rtwsta;
3826 if (!test_bit(RTW89_REMOTE_STA_IN_PS, rtwsta->flags))
3827 goto out;
3828
3829 sta = rtwsta_to_sta(rtwsta);
3830 if (ieee80211_is_pspoll(hdr->frame_control))
3831 ieee80211_sta_pspoll(sta);
3832 else if (ieee80211_has_pm(hdr->frame_control) &&
3833 (ieee80211_is_data_qos(hdr->frame_control) ||
3834 ieee80211_is_qos_nullfunc(hdr->frame_control)))
3835 ieee80211_sta_uapsd_trigger(sta, ieee80211_get_tid(hdr));
3836
3837 out:
3838 rcu_read_unlock();
3839 }
3840
rtw89_core_rx(struct rtw89_dev * rtwdev,struct rtw89_rx_desc_info * desc_info,struct sk_buff * skb)3841 void rtw89_core_rx(struct rtw89_dev *rtwdev,
3842 struct rtw89_rx_desc_info *desc_info,
3843 struct sk_buff *skb)
3844 {
3845 struct ieee80211_rx_status *rx_status;
3846 struct rtw89_ppdu_sts_info *ppdu_sts = &rtwdev->ppdu_sts;
3847 u8 ppdu_cnt = desc_info->ppdu_cnt;
3848 u8 band = desc_info->bb_sel ? RTW89_PHY_1 : RTW89_PHY_0;
3849
3850 if (desc_info->pkt_type != RTW89_CORE_RX_TYPE_WIFI) {
3851 rtw89_core_rx_process_report(rtwdev, desc_info, skb);
3852 return;
3853 }
3854
3855 if (ppdu_sts->curr_rx_ppdu_cnt[band] != ppdu_cnt) {
3856 rtw89_core_flush_ppdu_rx_queue(rtwdev, desc_info);
3857 ppdu_sts->curr_rx_ppdu_cnt[band] = ppdu_cnt;
3858 }
3859
3860 rx_status = IEEE80211_SKB_RXCB(skb);
3861 memset(rx_status, 0, sizeof(*rx_status));
3862 rtw89_core_update_rx_status(rtwdev, skb, desc_info, rx_status);
3863 rtw89_core_rx_pkt_hdl(rtwdev, skb, desc_info);
3864 if (desc_info->long_rxdesc &&
3865 BIT(desc_info->frame_type) & PPDU_FILTER_BITMAP)
3866 skb_queue_tail(&ppdu_sts->rx_queue[band], skb);
3867 else
3868 rtw89_core_rx_to_mac80211(rtwdev, NULL, desc_info, skb, rx_status);
3869 }
3870 EXPORT_SYMBOL(rtw89_core_rx);
3871
rtw89_core_napi_start(struct rtw89_dev * rtwdev)3872 void rtw89_core_napi_start(struct rtw89_dev *rtwdev)
3873 {
3874 if (test_and_set_bit(RTW89_FLAG_NAPI_RUNNING, rtwdev->flags))
3875 return;
3876
3877 napi_enable(&rtwdev->napi);
3878 }
3879 EXPORT_SYMBOL(rtw89_core_napi_start);
3880
rtw89_core_napi_stop(struct rtw89_dev * rtwdev)3881 void rtw89_core_napi_stop(struct rtw89_dev *rtwdev)
3882 {
3883 if (!test_and_clear_bit(RTW89_FLAG_NAPI_RUNNING, rtwdev->flags))
3884 return;
3885
3886 napi_synchronize(&rtwdev->napi);
3887 napi_disable(&rtwdev->napi);
3888 }
3889 EXPORT_SYMBOL(rtw89_core_napi_stop);
3890
rtw89_core_napi_init(struct rtw89_dev * rtwdev)3891 int rtw89_core_napi_init(struct rtw89_dev *rtwdev)
3892 {
3893 rtwdev->netdev = alloc_netdev_dummy(0);
3894 if (!rtwdev->netdev)
3895 return -ENOMEM;
3896
3897 netif_napi_add(rtwdev->netdev, &rtwdev->napi,
3898 rtwdev->hci.ops->napi_poll);
3899 return 0;
3900 }
3901 EXPORT_SYMBOL(rtw89_core_napi_init);
3902
rtw89_core_napi_deinit(struct rtw89_dev * rtwdev)3903 void rtw89_core_napi_deinit(struct rtw89_dev *rtwdev)
3904 {
3905 rtw89_core_napi_stop(rtwdev);
3906 netif_napi_del(&rtwdev->napi);
3907 free_netdev(rtwdev->netdev);
3908 }
3909 EXPORT_SYMBOL(rtw89_core_napi_deinit);
3910
rtw89_core_ba_work(struct work_struct * work)3911 static void rtw89_core_ba_work(struct work_struct *work)
3912 {
3913 struct rtw89_dev *rtwdev =
3914 container_of(work, struct rtw89_dev, ba_work);
3915 struct rtw89_txq *rtwtxq, *tmp;
3916 int ret;
3917
3918 spin_lock_bh(&rtwdev->ba_lock);
3919 list_for_each_entry_safe(rtwtxq, tmp, &rtwdev->ba_list, list) {
3920 struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq);
3921 struct ieee80211_sta *sta = txq->sta;
3922 struct rtw89_sta *rtwsta = sta_to_rtwsta_safe(sta);
3923 u8 tid = txq->tid;
3924
3925 if (!sta) {
3926 rtw89_warn(rtwdev, "cannot start BA without sta\n");
3927 goto skip_ba_work;
3928 }
3929
3930 if (rtwsta->disassoc) {
3931 rtw89_debug(rtwdev, RTW89_DBG_TXRX,
3932 "cannot start BA with disassoc sta\n");
3933 goto skip_ba_work;
3934 }
3935
3936 ret = ieee80211_start_tx_ba_session(sta, tid, 0);
3937 if (ret) {
3938 rtw89_debug(rtwdev, RTW89_DBG_TXRX,
3939 "failed to setup BA session for %pM:%2d: %d\n",
3940 sta->addr, tid, ret);
3941 if (ret == -EINVAL)
3942 set_bit(RTW89_TXQ_F_BLOCK_BA, &rtwtxq->flags);
3943 }
3944 skip_ba_work:
3945 list_del_init(&rtwtxq->list);
3946 }
3947 spin_unlock_bh(&rtwdev->ba_lock);
3948 }
3949
rtw89_core_free_sta_pending_ba(struct rtw89_dev * rtwdev,struct ieee80211_sta * sta)3950 void rtw89_core_free_sta_pending_ba(struct rtw89_dev *rtwdev,
3951 struct ieee80211_sta *sta)
3952 {
3953 struct rtw89_txq *rtwtxq, *tmp;
3954
3955 spin_lock_bh(&rtwdev->ba_lock);
3956 list_for_each_entry_safe(rtwtxq, tmp, &rtwdev->ba_list, list) {
3957 struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq);
3958
3959 if (sta == txq->sta)
3960 list_del_init(&rtwtxq->list);
3961 }
3962 spin_unlock_bh(&rtwdev->ba_lock);
3963 }
3964
rtw89_core_free_sta_pending_forbid_ba(struct rtw89_dev * rtwdev,struct ieee80211_sta * sta)3965 void rtw89_core_free_sta_pending_forbid_ba(struct rtw89_dev *rtwdev,
3966 struct ieee80211_sta *sta)
3967 {
3968 struct rtw89_txq *rtwtxq, *tmp;
3969
3970 spin_lock_bh(&rtwdev->ba_lock);
3971 list_for_each_entry_safe(rtwtxq, tmp, &rtwdev->forbid_ba_list, list) {
3972 struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq);
3973
3974 if (sta == txq->sta) {
3975 clear_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags);
3976 list_del_init(&rtwtxq->list);
3977 }
3978 }
3979 spin_unlock_bh(&rtwdev->ba_lock);
3980 }
3981
rtw89_core_free_sta_pending_roc_tx(struct rtw89_dev * rtwdev,struct ieee80211_sta * sta)3982 void rtw89_core_free_sta_pending_roc_tx(struct rtw89_dev *rtwdev,
3983 struct ieee80211_sta *sta)
3984 {
3985 struct rtw89_sta *rtwsta = sta_to_rtwsta(sta);
3986 struct sk_buff *skb;
3987
3988 while ((skb = skb_dequeue(&rtwsta->roc_queue)))
3989 dev_kfree_skb_any(skb);
3990 }
3991
rtw89_core_stop_tx_ba_session(struct rtw89_dev * rtwdev,struct rtw89_txq * rtwtxq)3992 static void rtw89_core_stop_tx_ba_session(struct rtw89_dev *rtwdev,
3993 struct rtw89_txq *rtwtxq)
3994 {
3995 struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq);
3996 struct ieee80211_sta *sta = txq->sta;
3997 struct rtw89_sta *rtwsta = sta_to_rtwsta_safe(sta);
3998
3999 if (unlikely(!rtwsta) || unlikely(rtwsta->disassoc))
4000 return;
4001
4002 if (!test_bit(RTW89_TXQ_F_AMPDU, &rtwtxq->flags) ||
4003 test_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags))
4004 return;
4005
4006 spin_lock_bh(&rtwdev->ba_lock);
4007 if (!test_and_set_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags))
4008 list_add_tail(&rtwtxq->list, &rtwdev->forbid_ba_list);
4009 spin_unlock_bh(&rtwdev->ba_lock);
4010
4011 ieee80211_stop_tx_ba_session(sta, txq->tid);
4012 cancel_delayed_work(&rtwdev->forbid_ba_work);
4013 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->forbid_ba_work,
4014 RTW89_FORBID_BA_TIMER);
4015 }
4016
rtw89_core_txq_check_agg(struct rtw89_dev * rtwdev,struct rtw89_txq * rtwtxq,struct sk_buff * skb)4017 static void rtw89_core_txq_check_agg(struct rtw89_dev *rtwdev,
4018 struct rtw89_txq *rtwtxq,
4019 struct sk_buff *skb)
4020 {
4021 struct ieee80211_hw *hw = rtwdev->hw;
4022 struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq);
4023 struct ieee80211_sta *sta = txq->sta;
4024 struct rtw89_sta *rtwsta = sta_to_rtwsta_safe(sta);
4025
4026 if (test_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags))
4027 return;
4028
4029 if (unlikely(skb->protocol == cpu_to_be16(ETH_P_PAE))) {
4030 rtw89_core_stop_tx_ba_session(rtwdev, rtwtxq);
4031 return;
4032 }
4033
4034 if (unlikely(!sta))
4035 return;
4036
4037 if (unlikely(test_bit(RTW89_TXQ_F_BLOCK_BA, &rtwtxq->flags)))
4038 return;
4039
4040 if (test_bit(RTW89_TXQ_F_AMPDU, &rtwtxq->flags)) {
4041 IEEE80211_SKB_CB(skb)->flags |= IEEE80211_TX_CTL_AMPDU;
4042 return;
4043 }
4044
4045 spin_lock_bh(&rtwdev->ba_lock);
4046 if (!rtwsta->disassoc && list_empty(&rtwtxq->list)) {
4047 list_add_tail(&rtwtxq->list, &rtwdev->ba_list);
4048 ieee80211_queue_work(hw, &rtwdev->ba_work);
4049 }
4050 spin_unlock_bh(&rtwdev->ba_lock);
4051 }
4052
rtw89_core_txq_push(struct rtw89_dev * rtwdev,struct rtw89_txq * rtwtxq,unsigned long frame_cnt,unsigned long byte_cnt)4053 static void rtw89_core_txq_push(struct rtw89_dev *rtwdev,
4054 struct rtw89_txq *rtwtxq,
4055 unsigned long frame_cnt,
4056 unsigned long byte_cnt)
4057 {
4058 struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq);
4059 struct ieee80211_vif *vif = txq->vif;
4060 struct ieee80211_sta *sta = txq->sta;
4061 struct sk_buff *skb;
4062 unsigned long i;
4063 int ret;
4064
4065 rcu_read_lock();
4066 for (i = 0; i < frame_cnt; i++) {
4067 skb = ieee80211_tx_dequeue_ni(rtwdev->hw, txq);
4068 if (!skb) {
4069 rtw89_debug(rtwdev, RTW89_DBG_TXRX, "dequeue a NULL skb\n");
4070 goto out;
4071 }
4072 rtw89_core_txq_check_agg(rtwdev, rtwtxq, skb);
4073 ret = rtw89_core_tx_write(rtwdev, vif, sta, skb, NULL);
4074 if (ret) {
4075 rtw89_err(rtwdev, "failed to push txq: %d\n", ret);
4076 ieee80211_free_txskb(rtwdev->hw, skb);
4077 break;
4078 }
4079 }
4080 out:
4081 rcu_read_unlock();
4082 }
4083
rtw89_check_and_reclaim_tx_resource(struct rtw89_dev * rtwdev,u8 tid)4084 static u32 rtw89_check_and_reclaim_tx_resource(struct rtw89_dev *rtwdev, u8 tid)
4085 {
4086 u8 qsel, ch_dma;
4087
4088 qsel = rtw89_core_get_qsel(rtwdev, tid);
4089 ch_dma = rtw89_chip_get_ch_dma(rtwdev, qsel);
4090
4091 return rtw89_hci_check_and_reclaim_tx_resource(rtwdev, ch_dma);
4092 }
4093
rtw89_core_txq_agg_wait(struct rtw89_dev * rtwdev,struct ieee80211_txq * txq,unsigned long * frame_cnt,bool * sched_txq,bool * reinvoke)4094 static bool rtw89_core_txq_agg_wait(struct rtw89_dev *rtwdev,
4095 struct ieee80211_txq *txq,
4096 unsigned long *frame_cnt,
4097 bool *sched_txq, bool *reinvoke)
4098 {
4099 struct rtw89_txq *rtwtxq = (struct rtw89_txq *)txq->drv_priv;
4100 struct rtw89_sta *rtwsta = sta_to_rtwsta_safe(txq->sta);
4101 struct rtw89_sta_link *rtwsta_link;
4102
4103 if (!rtwsta)
4104 return false;
4105
4106 rtwsta_link = rtw89_get_designated_link(rtwsta);
4107 if (unlikely(!rtwsta_link)) {
4108 rtw89_err(rtwdev, "agg wait: find no designated link\n");
4109 return false;
4110 }
4111
4112 if (rtwsta_link->max_agg_wait <= 0)
4113 return false;
4114
4115 if (rtwdev->stats.tx_tfc_lv <= RTW89_TFC_MID)
4116 return false;
4117
4118 if (*frame_cnt > 1) {
4119 *frame_cnt -= 1;
4120 *sched_txq = true;
4121 *reinvoke = true;
4122 rtwtxq->wait_cnt = 1;
4123 return false;
4124 }
4125
4126 if (*frame_cnt == 1 && rtwtxq->wait_cnt < rtwsta_link->max_agg_wait) {
4127 *reinvoke = true;
4128 rtwtxq->wait_cnt++;
4129 return true;
4130 }
4131
4132 rtwtxq->wait_cnt = 0;
4133 return false;
4134 }
4135
rtw89_core_txq_schedule(struct rtw89_dev * rtwdev,u8 ac,bool * reinvoke)4136 static void rtw89_core_txq_schedule(struct rtw89_dev *rtwdev, u8 ac, bool *reinvoke)
4137 {
4138 struct ieee80211_hw *hw = rtwdev->hw;
4139 struct ieee80211_txq *txq;
4140 struct rtw89_vif *rtwvif;
4141 struct rtw89_txq *rtwtxq;
4142 unsigned long frame_cnt;
4143 unsigned long byte_cnt;
4144 u32 tx_resource;
4145 bool sched_txq;
4146
4147 ieee80211_txq_schedule_start(hw, ac);
4148 while ((txq = ieee80211_next_txq(hw, ac))) {
4149 rtwtxq = (struct rtw89_txq *)txq->drv_priv;
4150 rtwvif = vif_to_rtwvif(txq->vif);
4151
4152 if (rtwvif->offchan) {
4153 ieee80211_return_txq(hw, txq, true);
4154 continue;
4155 }
4156 tx_resource = rtw89_check_and_reclaim_tx_resource(rtwdev, txq->tid);
4157 sched_txq = false;
4158
4159 ieee80211_txq_get_depth(txq, &frame_cnt, &byte_cnt);
4160 if (rtw89_core_txq_agg_wait(rtwdev, txq, &frame_cnt, &sched_txq, reinvoke)) {
4161 ieee80211_return_txq(hw, txq, true);
4162 continue;
4163 }
4164 frame_cnt = min_t(unsigned long, frame_cnt, tx_resource);
4165 rtw89_core_txq_push(rtwdev, rtwtxq, frame_cnt, byte_cnt);
4166 ieee80211_return_txq(hw, txq, sched_txq);
4167 if (frame_cnt != 0)
4168 rtw89_core_tx_kick_off(rtwdev, rtw89_core_get_qsel(rtwdev, txq->tid));
4169
4170 /* bound of tx_resource could get stuck due to burst traffic */
4171 if (frame_cnt == tx_resource)
4172 *reinvoke = true;
4173 }
4174 ieee80211_txq_schedule_end(hw, ac);
4175 }
4176
rtw89_ips_work(struct wiphy * wiphy,struct wiphy_work * work)4177 static void rtw89_ips_work(struct wiphy *wiphy, struct wiphy_work *work)
4178 {
4179 struct rtw89_dev *rtwdev = container_of(work, struct rtw89_dev,
4180 ips_work);
4181
4182 lockdep_assert_wiphy(wiphy);
4183
4184 rtw89_enter_ips_by_hwflags(rtwdev);
4185 }
4186
rtw89_core_txq_work(struct work_struct * w)4187 static void rtw89_core_txq_work(struct work_struct *w)
4188 {
4189 struct rtw89_dev *rtwdev = container_of(w, struct rtw89_dev, txq_work);
4190 bool reinvoke = false;
4191 u8 ac;
4192
4193 for (ac = 0; ac < IEEE80211_NUM_ACS; ac++)
4194 rtw89_core_txq_schedule(rtwdev, ac, &reinvoke);
4195
4196 if (reinvoke) {
4197 /* reinvoke to process the last frame */
4198 mod_delayed_work(rtwdev->txq_wq, &rtwdev->txq_reinvoke_work, 1);
4199 }
4200 }
4201
rtw89_core_txq_reinvoke_work(struct work_struct * w)4202 static void rtw89_core_txq_reinvoke_work(struct work_struct *w)
4203 {
4204 struct rtw89_dev *rtwdev = container_of(w, struct rtw89_dev,
4205 txq_reinvoke_work.work);
4206
4207 queue_work(rtwdev->txq_wq, &rtwdev->txq_work);
4208 }
4209
rtw89_forbid_ba_work(struct work_struct * w)4210 static void rtw89_forbid_ba_work(struct work_struct *w)
4211 {
4212 struct rtw89_dev *rtwdev = container_of(w, struct rtw89_dev,
4213 forbid_ba_work.work);
4214 struct rtw89_txq *rtwtxq, *tmp;
4215
4216 spin_lock_bh(&rtwdev->ba_lock);
4217 list_for_each_entry_safe(rtwtxq, tmp, &rtwdev->forbid_ba_list, list) {
4218 clear_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags);
4219 list_del_init(&rtwtxq->list);
4220 }
4221 spin_unlock_bh(&rtwdev->ba_lock);
4222 }
4223
rtw89_core_sta_pending_tx_iter(void * data,struct ieee80211_sta * sta)4224 static void rtw89_core_sta_pending_tx_iter(void *data,
4225 struct ieee80211_sta *sta)
4226 {
4227 struct rtw89_sta *rtwsta = sta_to_rtwsta(sta);
4228 struct rtw89_dev *rtwdev = rtwsta->rtwdev;
4229 struct rtw89_vif *rtwvif = rtwsta->rtwvif;
4230 struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif);
4231 struct rtw89_vif_link *target = data;
4232 struct rtw89_vif_link *rtwvif_link;
4233 unsigned int link_id;
4234 struct sk_buff *skb;
4235 int qsel, ret;
4236
4237 rtw89_vif_for_each_link(rtwvif, rtwvif_link, link_id)
4238 if (rtwvif_link->chanctx_idx == target->chanctx_idx)
4239 goto bottom;
4240
4241 return;
4242
4243 bottom:
4244 if (skb_queue_len(&rtwsta->roc_queue) == 0)
4245 return;
4246
4247 while ((skb = skb_dequeue(&rtwsta->roc_queue))) {
4248 ret = rtw89_core_tx_write(rtwdev, vif, sta, skb, &qsel);
4249 if (ret) {
4250 rtw89_warn(rtwdev, "pending tx failed with %d\n", ret);
4251 dev_kfree_skb_any(skb);
4252 } else {
4253 rtw89_core_tx_kick_off(rtwdev, qsel);
4254 }
4255 }
4256 }
4257
rtw89_core_handle_sta_pending_tx(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link)4258 static void rtw89_core_handle_sta_pending_tx(struct rtw89_dev *rtwdev,
4259 struct rtw89_vif_link *rtwvif_link)
4260 {
4261 ieee80211_iterate_stations_atomic(rtwdev->hw,
4262 rtw89_core_sta_pending_tx_iter,
4263 rtwvif_link);
4264 }
4265
rtw89_core_send_nullfunc(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link,bool qos,bool ps,int timeout)4266 int rtw89_core_send_nullfunc(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link,
4267 bool qos, bool ps, int timeout)
4268 {
4269 struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link);
4270 int link_id = ieee80211_vif_is_mld(vif) ? rtwvif_link->link_id : -1;
4271 struct rtw89_sta_link *rtwsta_link;
4272 struct rtw89_tx_wait_info *wait;
4273 struct ieee80211_sta *sta;
4274 struct ieee80211_hdr *hdr;
4275 struct rtw89_sta *rtwsta;
4276 struct sk_buff *skb;
4277 int ret, qsel;
4278
4279 if (vif->type != NL80211_IFTYPE_STATION || !vif->cfg.assoc)
4280 return 0;
4281
4282 wait = kzalloc_obj(*wait);
4283 if (!wait)
4284 return -ENOMEM;
4285
4286 init_completion(&wait->completion);
4287
4288 rcu_read_lock();
4289 sta = ieee80211_find_sta(vif, vif->cfg.ap_addr);
4290 if (!sta) {
4291 ret = -EINVAL;
4292 goto out;
4293 }
4294 rtwsta = sta_to_rtwsta(sta);
4295
4296 skb = ieee80211_nullfunc_get(rtwdev->hw, vif, link_id, qos);
4297 if (!skb) {
4298 ret = -ENOMEM;
4299 goto out;
4300 }
4301
4302 wait->skb = skb;
4303
4304 hdr = (struct ieee80211_hdr *)skb->data;
4305 if (ps)
4306 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
4307
4308 rtwsta_link = rtwsta->links[rtwvif_link->link_id];
4309 if (unlikely(!rtwsta_link)) {
4310 ret = -ENOLINK;
4311 dev_kfree_skb_any(skb);
4312 goto out;
4313 }
4314
4315 ret = rtw89_core_tx_write_link(rtwdev, rtwvif_link, rtwsta_link, skb, &qsel, wait);
4316 if (ret) {
4317 rtw89_warn(rtwdev, "nullfunc transmit failed: %d\n", ret);
4318 dev_kfree_skb_any(skb);
4319 goto out;
4320 }
4321
4322 rcu_read_unlock();
4323
4324 return rtw89_core_tx_kick_off_and_wait(rtwdev, skb, wait, qsel,
4325 timeout);
4326 out:
4327 rcu_read_unlock();
4328 kfree(wait);
4329
4330 return ret;
4331 }
4332
rtw89_roc_start(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif)4333 void rtw89_roc_start(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif)
4334 {
4335 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
4336 struct rtw89_chanctx_pause_parm pause_parm = {
4337 .rsn = RTW89_CHANCTX_PAUSE_REASON_ROC,
4338 };
4339 struct ieee80211_hw *hw = rtwdev->hw;
4340 struct rtw89_roc *roc = &rtwvif->roc;
4341 struct rtw89_vif_link *rtwvif_link;
4342 struct cfg80211_chan_def roc_chan;
4343 struct rtw89_vif *tmp_vif;
4344 u32 reg;
4345 int ret;
4346
4347 lockdep_assert_wiphy(hw->wiphy);
4348
4349 rtw89_leave_ips_by_hwflags(rtwdev);
4350 rtw89_leave_lps(rtwdev);
4351
4352 rtwvif_link = rtw89_get_designated_link(rtwvif);
4353 if (unlikely(!rtwvif_link)) {
4354 rtw89_err(rtwdev, "roc start: find no designated link\n");
4355 return;
4356 }
4357
4358 roc->link_id = rtwvif_link->link_id;
4359
4360 pause_parm.trigger = rtwvif_link;
4361 rtw89_chanctx_pause(rtwdev, &pause_parm);
4362
4363 ret = rtw89_core_send_nullfunc(rtwdev, rtwvif_link, true, true,
4364 RTW89_ROC_TX_TIMEOUT);
4365 if (ret)
4366 rtw89_debug(rtwdev, RTW89_DBG_TXRX,
4367 "roc send null-1 failed: %d\n", ret);
4368
4369 rtw89_for_each_rtwvif(rtwdev, tmp_vif) {
4370 struct rtw89_vif_link *tmp_link;
4371 unsigned int link_id;
4372
4373 rtw89_vif_for_each_link(tmp_vif, tmp_link, link_id) {
4374 if (tmp_link->chanctx_idx == rtwvif_link->chanctx_idx) {
4375 tmp_vif->offchan = true;
4376 break;
4377 }
4378 }
4379 }
4380
4381 cfg80211_chandef_create(&roc_chan, &roc->chan, NL80211_CHAN_NO_HT);
4382 rtw89_config_roc_chandef(rtwdev, rtwvif_link, &roc_chan);
4383 rtw89_set_channel(rtwdev);
4384
4385 reg = rtw89_mac_reg_by_idx(rtwdev, mac->rx_fltr, rtwvif_link->mac_idx);
4386 rtw89_write32_clr(rtwdev, reg, B_AX_A_UC_CAM_MATCH | B_AX_A_BC_CAM_MATCH);
4387
4388 ieee80211_ready_on_channel(hw);
4389 wiphy_delayed_work_cancel(hw->wiphy, &rtwvif->roc.roc_work);
4390 wiphy_delayed_work_queue(hw->wiphy, &rtwvif->roc.roc_work,
4391 msecs_to_jiffies(rtwvif->roc.duration));
4392 }
4393
rtw89_roc_end(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif)4394 void rtw89_roc_end(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif)
4395 {
4396 struct ieee80211_hw *hw = rtwdev->hw;
4397 struct rtw89_roc *roc = &rtwvif->roc;
4398 struct rtw89_vif_link *rtwvif_link;
4399 struct rtw89_vif *tmp_vif;
4400 int ret;
4401
4402 lockdep_assert_wiphy(hw->wiphy);
4403
4404 ieee80211_remain_on_channel_expired(hw);
4405
4406 rtw89_leave_ips_by_hwflags(rtwdev);
4407 rtw89_leave_lps(rtwdev);
4408
4409 rtwvif_link = rtwvif->links[roc->link_id];
4410 if (unlikely(!rtwvif_link)) {
4411 rtw89_err(rtwdev, "roc end: find no link (link id %u)\n",
4412 roc->link_id);
4413 return;
4414 }
4415
4416 rtw89_mac_set_rx_fltr(rtwdev, rtwvif_link->mac_idx, rtwdev->hal.rx_fltr);
4417
4418 roc->state = RTW89_ROC_IDLE;
4419 rtw89_config_roc_chandef(rtwdev, rtwvif_link, NULL);
4420 rtw89_chanctx_proceed(rtwdev, NULL);
4421 ret = rtw89_core_send_nullfunc(rtwdev, rtwvif_link, true, false,
4422 RTW89_ROC_TX_TIMEOUT);
4423 if (ret)
4424 rtw89_debug(rtwdev, RTW89_DBG_TXRX,
4425 "roc send null-0 failed: %d\n", ret);
4426
4427 rtw89_for_each_rtwvif(rtwdev, tmp_vif)
4428 tmp_vif->offchan = false;
4429
4430 rtw89_core_handle_sta_pending_tx(rtwdev, rtwvif_link);
4431 queue_work(rtwdev->txq_wq, &rtwdev->txq_work);
4432
4433 if (hw->conf.flags & IEEE80211_CONF_IDLE)
4434 wiphy_delayed_work_queue(hw->wiphy, &roc->roc_work,
4435 msecs_to_jiffies(RTW89_ROC_IDLE_TIMEOUT));
4436 }
4437
rtw89_roc_work(struct wiphy * wiphy,struct wiphy_work * work)4438 void rtw89_roc_work(struct wiphy *wiphy, struct wiphy_work *work)
4439 {
4440 struct rtw89_vif *rtwvif = container_of(work, struct rtw89_vif,
4441 roc.roc_work.work);
4442 struct rtw89_dev *rtwdev = rtwvif->rtwdev;
4443 struct rtw89_roc *roc = &rtwvif->roc;
4444
4445 lockdep_assert_wiphy(wiphy);
4446
4447 switch (roc->state) {
4448 case RTW89_ROC_IDLE:
4449 rtw89_enter_ips_by_hwflags(rtwdev);
4450 break;
4451 case RTW89_ROC_MGMT:
4452 case RTW89_ROC_NORMAL:
4453 rtw89_roc_end(rtwdev, rtwvif);
4454 break;
4455 default:
4456 break;
4457 }
4458 }
4459
rtw89_get_traffic_level(struct rtw89_dev * rtwdev,u32 throughput,u64 cnt,enum rtw89_tfc_interval interval)4460 static enum rtw89_tfc_lv rtw89_get_traffic_level(struct rtw89_dev *rtwdev,
4461 u32 throughput, u64 cnt,
4462 enum rtw89_tfc_interval interval)
4463 {
4464 u64 cnt_level;
4465
4466 switch (interval) {
4467 default:
4468 case RTW89_TFC_INTERVAL_100MS:
4469 cnt_level = 5;
4470 break;
4471 case RTW89_TFC_INTERVAL_2SEC:
4472 cnt_level = 100;
4473 break;
4474 }
4475
4476 if (cnt < cnt_level)
4477 return RTW89_TFC_IDLE;
4478 if (throughput > 50)
4479 return RTW89_TFC_HIGH;
4480 if (throughput > 10)
4481 return RTW89_TFC_MID;
4482 if (throughput > 2)
4483 return RTW89_TFC_LOW;
4484 return RTW89_TFC_ULTRA_LOW;
4485 }
4486
rtw89_traffic_stats_calc(struct rtw89_dev * rtwdev,struct rtw89_traffic_stats * stats,enum rtw89_tfc_interval interval)4487 static bool rtw89_traffic_stats_calc(struct rtw89_dev *rtwdev,
4488 struct rtw89_traffic_stats *stats,
4489 enum rtw89_tfc_interval interval)
4490 {
4491 enum rtw89_tfc_lv tx_tfc_lv = stats->tx_tfc_lv;
4492 enum rtw89_tfc_lv rx_tfc_lv = stats->rx_tfc_lv;
4493
4494 stats->tx_throughput_raw = rtw89_bytes_to_mbps(stats->tx_unicast, interval);
4495 stats->rx_throughput_raw = rtw89_bytes_to_mbps(stats->rx_unicast, interval);
4496
4497 ewma_tp_add(&stats->tx_ewma_tp, stats->tx_throughput_raw);
4498 ewma_tp_add(&stats->rx_ewma_tp, stats->rx_throughput_raw);
4499
4500 stats->tx_throughput = ewma_tp_read(&stats->tx_ewma_tp);
4501 stats->rx_throughput = ewma_tp_read(&stats->rx_ewma_tp);
4502 stats->tx_tfc_lv = rtw89_get_traffic_level(rtwdev, stats->tx_throughput,
4503 stats->tx_cnt, interval);
4504 stats->rx_tfc_lv = rtw89_get_traffic_level(rtwdev, stats->rx_throughput,
4505 stats->rx_cnt, interval);
4506 stats->tx_avg_len = stats->tx_cnt ?
4507 DIV_ROUND_DOWN_ULL(stats->tx_unicast, stats->tx_cnt) : 0;
4508 stats->rx_avg_len = stats->rx_cnt ?
4509 DIV_ROUND_DOWN_ULL(stats->rx_unicast, stats->rx_cnt) : 0;
4510
4511 stats->tx_unicast = 0;
4512 stats->rx_unicast = 0;
4513 stats->tx_cnt = 0;
4514 stats->rx_cnt = 0;
4515 stats->rx_tf_periodic = stats->rx_tf_acc;
4516 stats->rx_tf_acc = 0;
4517
4518 if (tx_tfc_lv != stats->tx_tfc_lv || rx_tfc_lv != stats->rx_tfc_lv)
4519 return true;
4520
4521 return false;
4522 }
4523
rtw89_traffic_stats_track(struct rtw89_dev * rtwdev)4524 static bool rtw89_traffic_stats_track(struct rtw89_dev *rtwdev)
4525 {
4526 struct rtw89_vif_link *rtwvif_link;
4527 struct rtw89_vif *rtwvif;
4528 unsigned int link_id;
4529 bool tfc_changed;
4530
4531 tfc_changed = rtw89_traffic_stats_calc(rtwdev, &rtwdev->stats,
4532 RTW89_TFC_INTERVAL_2SEC);
4533
4534 rtw89_for_each_rtwvif(rtwdev, rtwvif) {
4535 rtw89_traffic_stats_calc(rtwdev, &rtwvif->stats,
4536 RTW89_TFC_INTERVAL_2SEC);
4537
4538 rtw89_vif_for_each_link(rtwvif, rtwvif_link, link_id)
4539 rtw89_fw_h2c_tp_offload(rtwdev, rtwvif_link);
4540 }
4541
4542 return tfc_changed;
4543 }
4544
rtw89_enter_lps_track(struct rtw89_dev * rtwdev)4545 static void rtw89_enter_lps_track(struct rtw89_dev *rtwdev)
4546 {
4547 struct ieee80211_vif *vif;
4548 struct rtw89_vif *rtwvif;
4549
4550 rtw89_for_each_rtwvif(rtwdev, rtwvif) {
4551 if (rtwvif->tdls_peer)
4552 continue;
4553 if (rtwvif->offchan)
4554 continue;
4555
4556 if (rtwvif->stats_ps.tx_tfc_lv >= RTW89_TFC_MID ||
4557 rtwvif->stats_ps.rx_tfc_lv >= RTW89_TFC_MID)
4558 continue;
4559
4560 vif = rtwvif_to_vif(rtwvif);
4561
4562 if (!(vif->type == NL80211_IFTYPE_STATION ||
4563 vif->type == NL80211_IFTYPE_P2P_CLIENT))
4564 continue;
4565
4566 if (!rtw89_core_bcn_track_can_lps(rtwdev))
4567 continue;
4568
4569 rtw89_enter_lps(rtwdev, rtwvif, true);
4570 }
4571 }
4572
rtw89_core_rfk_track(struct rtw89_dev * rtwdev)4573 static void rtw89_core_rfk_track(struct rtw89_dev *rtwdev)
4574 {
4575 enum rtw89_entity_mode mode;
4576
4577 mode = rtw89_get_entity_mode(rtwdev);
4578 if (mode == RTW89_ENTITY_MODE_MCC)
4579 return;
4580
4581 rtw89_chip_rfk_track(rtwdev);
4582 }
4583
rtw89_core_update_p2p_ps(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link,struct ieee80211_bss_conf * bss_conf)4584 void rtw89_core_update_p2p_ps(struct rtw89_dev *rtwdev,
4585 struct rtw89_vif_link *rtwvif_link,
4586 struct ieee80211_bss_conf *bss_conf)
4587 {
4588 enum rtw89_entity_mode mode = rtw89_get_entity_mode(rtwdev);
4589
4590 if (mode == RTW89_ENTITY_MODE_MCC)
4591 rtw89_queue_chanctx_change(rtwdev, RTW89_CHANCTX_P2P_PS_CHANGE);
4592 else
4593 rtw89_process_p2p_ps(rtwdev, rtwvif_link, bss_conf);
4594 }
4595
rtw89_traffic_stats_init(struct rtw89_dev * rtwdev,struct rtw89_traffic_stats * stats)4596 void rtw89_traffic_stats_init(struct rtw89_dev *rtwdev,
4597 struct rtw89_traffic_stats *stats)
4598 {
4599 stats->tx_unicast = 0;
4600 stats->rx_unicast = 0;
4601 stats->tx_cnt = 0;
4602 stats->rx_cnt = 0;
4603 ewma_tp_init(&stats->tx_ewma_tp);
4604 ewma_tp_init(&stats->rx_ewma_tp);
4605 }
4606
4607 #define RTW89_MLSR_GOTO_2GHZ_THRESHOLD -53
4608 #define RTW89_MLSR_EXIT_2GHZ_THRESHOLD -38
rtw89_core_mlsr_link_decision(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif)4609 static void rtw89_core_mlsr_link_decision(struct rtw89_dev *rtwdev,
4610 struct rtw89_vif *rtwvif)
4611 {
4612 unsigned int sel_link_id = IEEE80211_MLD_MAX_NUM_LINKS;
4613 struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif);
4614 struct rtw89_vif_link *rtwvif_link;
4615 const struct rtw89_chan *chan;
4616 unsigned long usable_links;
4617 unsigned int link_id;
4618 u8 decided_bands;
4619 u8 rssi;
4620
4621 rssi = ewma_rssi_read(&rtwdev->phystat.bcn_rssi);
4622 if (unlikely(!rssi))
4623 return;
4624
4625 if (RTW89_RSSI_RAW_TO_DBM(rssi) >= RTW89_MLSR_EXIT_2GHZ_THRESHOLD)
4626 decided_bands = BIT(RTW89_BAND_5G) | BIT(RTW89_BAND_6G);
4627 else if (RTW89_RSSI_RAW_TO_DBM(rssi) <= RTW89_MLSR_GOTO_2GHZ_THRESHOLD)
4628 decided_bands = BIT(RTW89_BAND_2G);
4629 else
4630 return;
4631
4632 usable_links = ieee80211_vif_usable_links(vif);
4633
4634 rtwvif_link = rtw89_get_designated_link(rtwvif);
4635 if (unlikely(!rtwvif_link))
4636 goto select;
4637
4638 chan = rtw89_chan_get(rtwdev, rtwvif_link->chanctx_idx);
4639 if (decided_bands & BIT(chan->band_type))
4640 return;
4641
4642 usable_links &= ~BIT(rtwvif_link->link_id);
4643
4644 select:
4645 rcu_read_lock();
4646
4647 for_each_set_bit(link_id, &usable_links, IEEE80211_MLD_MAX_NUM_LINKS) {
4648 struct ieee80211_bss_conf *link_conf;
4649 struct ieee80211_channel *channel;
4650 enum rtw89_band band;
4651
4652 link_conf = rcu_dereference(vif->link_conf[link_id]);
4653 if (unlikely(!link_conf))
4654 continue;
4655
4656 channel = link_conf->chanreq.oper.chan;
4657 if (unlikely(!channel))
4658 continue;
4659
4660 band = rtw89_nl80211_to_hw_band(channel->band);
4661 if (decided_bands & BIT(band)) {
4662 sel_link_id = link_id;
4663 break;
4664 }
4665 }
4666
4667 rcu_read_unlock();
4668
4669 if (sel_link_id == IEEE80211_MLD_MAX_NUM_LINKS)
4670 return;
4671
4672 rtw89_core_mlsr_switch(rtwdev, rtwvif, sel_link_id);
4673 }
4674
rtw89_core_mlo_track(struct rtw89_dev * rtwdev)4675 static void rtw89_core_mlo_track(struct rtw89_dev *rtwdev)
4676 {
4677 struct rtw89_hal *hal = &rtwdev->hal;
4678 struct ieee80211_vif *vif;
4679 struct rtw89_vif *rtwvif;
4680
4681 if (hal->disabled_dm_bitmap & BIT(RTW89_DM_MLO))
4682 return;
4683
4684 rtw89_for_each_rtwvif(rtwdev, rtwvif) {
4685 vif = rtwvif_to_vif(rtwvif);
4686 if (!vif->cfg.assoc || !ieee80211_vif_is_mld(vif))
4687 continue;
4688
4689 switch (rtwvif->mlo_mode) {
4690 case RTW89_MLO_MODE_MLSR:
4691 rtw89_core_mlsr_link_decision(rtwdev, rtwvif);
4692 break;
4693 default:
4694 break;
4695 }
4696 }
4697 }
4698
rtw89_track_ps_work(struct wiphy * wiphy,struct wiphy_work * work)4699 static void rtw89_track_ps_work(struct wiphy *wiphy, struct wiphy_work *work)
4700 {
4701 struct rtw89_dev *rtwdev = container_of(work, struct rtw89_dev,
4702 track_ps_work.work);
4703 struct rtw89_vif *rtwvif;
4704
4705 lockdep_assert_wiphy(wiphy);
4706
4707 if (test_bit(RTW89_FLAG_FORBIDDEN_TRACK_WORK, rtwdev->flags))
4708 return;
4709
4710 if (!test_bit(RTW89_FLAG_RUNNING, rtwdev->flags))
4711 return;
4712
4713 wiphy_delayed_work_queue(wiphy, &rtwdev->track_ps_work,
4714 RTW89_TRACK_PS_WORK_PERIOD);
4715
4716 rtw89_for_each_rtwvif(rtwdev, rtwvif)
4717 rtw89_traffic_stats_calc(rtwdev, &rtwvif->stats_ps,
4718 RTW89_TFC_INTERVAL_100MS);
4719
4720 if (rtwdev->scanning)
4721 return;
4722
4723 if (rtwdev->lps_enabled && !rtwdev->btc.lps)
4724 rtw89_enter_lps_track(rtwdev);
4725 }
4726
rtw89_track_work(struct wiphy * wiphy,struct wiphy_work * work)4727 static void rtw89_track_work(struct wiphy *wiphy, struct wiphy_work *work)
4728 {
4729 struct rtw89_dev *rtwdev = container_of(work, struct rtw89_dev,
4730 track_work.work);
4731 bool tfc_changed;
4732
4733 lockdep_assert_wiphy(wiphy);
4734
4735 if (test_bit(RTW89_FLAG_FORBIDDEN_TRACK_WORK, rtwdev->flags))
4736 return;
4737
4738 if (!test_bit(RTW89_FLAG_RUNNING, rtwdev->flags))
4739 return;
4740
4741 wiphy_delayed_work_queue(wiphy, &rtwdev->track_work,
4742 RTW89_TRACK_WORK_PERIOD);
4743
4744 tfc_changed = rtw89_traffic_stats_track(rtwdev);
4745 if (rtwdev->scanning)
4746 return;
4747
4748 rtw89_leave_lps(rtwdev);
4749
4750 if (tfc_changed) {
4751 rtw89_hci_recalc_int_mit(rtwdev);
4752 rtw89_btc_ntfy_wl_sta(rtwdev);
4753 }
4754 rtw89_mac_bf_monitor_track(rtwdev);
4755 rtw89_core_bcn_track(rtwdev);
4756 rtw89_phy_stat_track(rtwdev);
4757 rtw89_phy_env_monitor_track(rtwdev);
4758 rtw89_phy_dig(rtwdev);
4759 rtw89_core_rfk_track(rtwdev);
4760 rtw89_phy_ra_update(rtwdev);
4761 rtw89_phy_cfo_track(rtwdev);
4762 rtw89_phy_tx_path_div_track(rtwdev);
4763 rtw89_phy_antdiv_track(rtwdev);
4764 rtw89_phy_ul_tb_ctrl_track(rtwdev);
4765 rtw89_phy_edcca_track(rtwdev);
4766 rtw89_sar_track(rtwdev);
4767 rtw89_chanctx_track(rtwdev);
4768 rtw89_core_rfkill_poll(rtwdev, false);
4769 rtw89_core_mlo_track(rtwdev);
4770
4771 if (rtwdev->lps_enabled && !rtwdev->btc.lps)
4772 rtw89_enter_lps_track(rtwdev);
4773 }
4774
rtw89_core_acquire_bit_map(unsigned long * addr,unsigned long size)4775 u8 rtw89_core_acquire_bit_map(unsigned long *addr, unsigned long size)
4776 {
4777 unsigned long bit;
4778
4779 bit = find_first_zero_bit(addr, size);
4780 if (bit < size)
4781 set_bit(bit, addr);
4782
4783 return bit;
4784 }
4785
rtw89_core_release_bit_map(unsigned long * addr,u8 bit)4786 void rtw89_core_release_bit_map(unsigned long *addr, u8 bit)
4787 {
4788 clear_bit(bit, addr);
4789 }
4790
rtw89_core_release_all_bits_map(unsigned long * addr,unsigned int nbits)4791 void rtw89_core_release_all_bits_map(unsigned long *addr, unsigned int nbits)
4792 {
4793 bitmap_zero(addr, nbits);
4794 }
4795
rtw89_core_acquire_sta_ba_entry(struct rtw89_dev * rtwdev,struct rtw89_sta_link * rtwsta_link,u8 tid,u8 * cam_idx)4796 int rtw89_core_acquire_sta_ba_entry(struct rtw89_dev *rtwdev,
4797 struct rtw89_sta_link *rtwsta_link, u8 tid,
4798 u8 *cam_idx)
4799 {
4800 const struct rtw89_chip_info *chip = rtwdev->chip;
4801 struct rtw89_cam_info *cam_info = &rtwdev->cam_info;
4802 struct rtw89_ba_cam_entry *entry = NULL, *tmp;
4803 u8 idx;
4804 int i;
4805
4806 lockdep_assert_wiphy(rtwdev->hw->wiphy);
4807
4808 idx = rtw89_core_acquire_bit_map(cam_info->ba_cam_map, chip->bacam_num);
4809 if (idx == chip->bacam_num) {
4810 /* allocate a static BA CAM to tid=0/5, so replace the existing
4811 * one if BA CAM is full. Hardware will process the original tid
4812 * automatically.
4813 */
4814 if (tid != 0 && tid != 5)
4815 return -ENOSPC;
4816
4817 for_each_set_bit(i, cam_info->ba_cam_map, chip->bacam_num) {
4818 tmp = &cam_info->ba_cam_entry[i];
4819 if (tmp->tid == 0 || tmp->tid == 5)
4820 continue;
4821
4822 idx = i;
4823 entry = tmp;
4824 list_del(&entry->list);
4825 break;
4826 }
4827
4828 if (!entry)
4829 return -ENOSPC;
4830 } else {
4831 entry = &cam_info->ba_cam_entry[idx];
4832 }
4833
4834 entry->tid = tid;
4835 list_add_tail(&entry->list, &rtwsta_link->ba_cam_list);
4836
4837 *cam_idx = idx;
4838
4839 return 0;
4840 }
4841
rtw89_core_release_sta_ba_entry(struct rtw89_dev * rtwdev,struct rtw89_sta_link * rtwsta_link,u8 tid,u8 * cam_idx)4842 int rtw89_core_release_sta_ba_entry(struct rtw89_dev *rtwdev,
4843 struct rtw89_sta_link *rtwsta_link, u8 tid,
4844 u8 *cam_idx)
4845 {
4846 struct rtw89_cam_info *cam_info = &rtwdev->cam_info;
4847 struct rtw89_ba_cam_entry *entry = NULL, *tmp;
4848 u8 idx;
4849
4850 lockdep_assert_wiphy(rtwdev->hw->wiphy);
4851
4852 list_for_each_entry_safe(entry, tmp, &rtwsta_link->ba_cam_list, list) {
4853 if (entry->tid != tid)
4854 continue;
4855
4856 idx = entry - cam_info->ba_cam_entry;
4857 list_del(&entry->list);
4858
4859 rtw89_core_release_bit_map(cam_info->ba_cam_map, idx);
4860 *cam_idx = idx;
4861 return 0;
4862 }
4863
4864 return -ENOENT;
4865 }
4866
4867 #define RTW89_TYPE_MAPPING(_type) \
4868 case NL80211_IFTYPE_ ## _type: \
4869 rtwvif_link->wifi_role = RTW89_WIFI_ROLE_ ## _type; \
4870 break
rtw89_vif_type_mapping(struct rtw89_vif_link * rtwvif_link,bool assoc)4871 void rtw89_vif_type_mapping(struct rtw89_vif_link *rtwvif_link, bool assoc)
4872 {
4873 const struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link);
4874 const struct ieee80211_bss_conf *bss_conf;
4875
4876 switch (vif->type) {
4877 case NL80211_IFTYPE_STATION:
4878 if (vif->p2p)
4879 rtwvif_link->wifi_role = RTW89_WIFI_ROLE_P2P_CLIENT;
4880 else
4881 rtwvif_link->wifi_role = RTW89_WIFI_ROLE_STATION;
4882 break;
4883 case NL80211_IFTYPE_AP:
4884 if (vif->p2p)
4885 rtwvif_link->wifi_role = RTW89_WIFI_ROLE_P2P_GO;
4886 else
4887 rtwvif_link->wifi_role = RTW89_WIFI_ROLE_AP;
4888 break;
4889 RTW89_TYPE_MAPPING(ADHOC);
4890 RTW89_TYPE_MAPPING(MONITOR);
4891 RTW89_TYPE_MAPPING(MESH_POINT);
4892 default:
4893 WARN_ON(1);
4894 break;
4895 }
4896
4897 switch (vif->type) {
4898 case NL80211_IFTYPE_AP:
4899 case NL80211_IFTYPE_MESH_POINT:
4900 rtwvif_link->net_type = RTW89_NET_TYPE_AP_MODE;
4901 rtwvif_link->self_role = RTW89_SELF_ROLE_AP;
4902 break;
4903 case NL80211_IFTYPE_ADHOC:
4904 rtwvif_link->net_type = RTW89_NET_TYPE_AD_HOC;
4905 rtwvif_link->self_role = RTW89_SELF_ROLE_CLIENT;
4906 break;
4907 case NL80211_IFTYPE_STATION:
4908 if (assoc) {
4909 rtwvif_link->net_type = RTW89_NET_TYPE_INFRA;
4910
4911 rcu_read_lock();
4912 bss_conf = rtw89_vif_rcu_dereference_link(rtwvif_link, false);
4913 rtwvif_link->trigger = bss_conf->he_support;
4914 rcu_read_unlock();
4915 } else {
4916 rtwvif_link->net_type = RTW89_NET_TYPE_NO_LINK;
4917 rtwvif_link->trigger = false;
4918 }
4919 rtwvif_link->self_role = RTW89_SELF_ROLE_CLIENT;
4920 rtwvif_link->addr_cam.sec_ent_mode = RTW89_ADDR_CAM_SEC_NORMAL;
4921 break;
4922 case NL80211_IFTYPE_MONITOR:
4923 break;
4924 default:
4925 WARN_ON(1);
4926 break;
4927 }
4928 }
4929
rtw89_core_sta_link_add(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link,struct rtw89_sta_link * rtwsta_link)4930 int rtw89_core_sta_link_add(struct rtw89_dev *rtwdev,
4931 struct rtw89_vif_link *rtwvif_link,
4932 struct rtw89_sta_link *rtwsta_link)
4933 {
4934 const struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link);
4935 const struct ieee80211_sta *sta = rtwsta_link_to_sta(rtwsta_link);
4936 struct rtw89_hal *hal = &rtwdev->hal;
4937 u8 ant_num = hal->ant_diversity ? 2 : rtwdev->chip->rf_path_num;
4938 int i;
4939 int ret;
4940
4941 rtwsta_link->prev_rssi = 0;
4942 INIT_LIST_HEAD(&rtwsta_link->ba_cam_list);
4943 ewma_rssi_init(&rtwsta_link->avg_rssi);
4944 ewma_snr_init(&rtwsta_link->avg_snr);
4945 ewma_evm_init(&rtwsta_link->evm_1ss);
4946 for (i = 0; i < ant_num; i++) {
4947 ewma_rssi_init(&rtwsta_link->rssi[i]);
4948 ewma_evm_init(&rtwsta_link->evm_min[i]);
4949 ewma_evm_init(&rtwsta_link->evm_max[i]);
4950 }
4951
4952 if (vif->type == NL80211_IFTYPE_STATION && !sta->tdls) {
4953 /* must do rtw89_reg_6ghz_recalc() before rfk channel */
4954 ret = rtw89_reg_6ghz_recalc(rtwdev, rtwvif_link, true);
4955 if (ret)
4956 return ret;
4957
4958 rtw89_btc_ntfy_role_info(rtwdev, rtwvif_link, rtwsta_link,
4959 BTC_ROLE_MSTS_STA_CONN_START);
4960 rtw89_chip_rfk_channel(rtwdev, rtwvif_link);
4961
4962 if (vif->p2p) {
4963 rtw89_mac_get_tx_retry_limit(rtwdev, rtwsta_link,
4964 &rtwsta_link->tx_retry);
4965 rtw89_mac_set_tx_retry_limit(rtwdev, rtwsta_link, false, 60);
4966 }
4967 rtw89_phy_dig_suspend(rtwdev);
4968 } else if (vif->type == NL80211_IFTYPE_AP || sta->tdls) {
4969 ret = rtw89_mac_set_macid_pause(rtwdev, rtwsta_link->mac_id, false);
4970 if (ret) {
4971 rtw89_warn(rtwdev, "failed to send h2c macid pause\n");
4972 return ret;
4973 }
4974
4975 ret = rtw89_fw_h2c_role_maintain(rtwdev, rtwvif_link, rtwsta_link,
4976 RTW89_ROLE_CREATE);
4977 if (ret) {
4978 rtw89_warn(rtwdev, "failed to send h2c role info\n");
4979 return ret;
4980 }
4981
4982 ret = rtw89_chip_h2c_default_cmac_tbl(rtwdev, rtwvif_link, rtwsta_link);
4983 if (ret)
4984 return ret;
4985
4986 ret = rtw89_chip_h2c_default_dmac_tbl(rtwdev, rtwvif_link, rtwsta_link);
4987 if (ret)
4988 return ret;
4989 }
4990
4991 return 0;
4992 }
4993
rtw89_core_sta_link_disassoc(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link,struct rtw89_sta_link * rtwsta_link)4994 int rtw89_core_sta_link_disassoc(struct rtw89_dev *rtwdev,
4995 struct rtw89_vif_link *rtwvif_link,
4996 struct rtw89_sta_link *rtwsta_link)
4997 {
4998 const struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link);
4999
5000 rtw89_assoc_link_clr(rtwsta_link);
5001
5002 if (vif->type == NL80211_IFTYPE_STATION) {
5003 rtw89_fw_h2c_set_bcn_fltr_cfg(rtwdev, rtwvif_link, false);
5004 rtw89_core_bcn_track_reset(rtwdev);
5005 }
5006
5007 if (rtwvif_link->wifi_role == RTW89_WIFI_ROLE_P2P_CLIENT)
5008 rtw89_p2p_noa_once_deinit(rtwvif_link);
5009
5010 return 0;
5011 }
5012
rtw89_core_sta_link_disconnect(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link,struct rtw89_sta_link * rtwsta_link)5013 int rtw89_core_sta_link_disconnect(struct rtw89_dev *rtwdev,
5014 struct rtw89_vif_link *rtwvif_link,
5015 struct rtw89_sta_link *rtwsta_link)
5016 {
5017 const struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link);
5018 const struct ieee80211_sta *sta = rtwsta_link_to_sta(rtwsta_link);
5019 int ret;
5020
5021 rtw89_mac_bf_monitor_calc(rtwdev, rtwsta_link, true);
5022 rtw89_mac_bf_disassoc(rtwdev, rtwvif_link, rtwsta_link);
5023
5024 if (vif->type == NL80211_IFTYPE_AP || sta->tdls)
5025 rtw89_cam_deinit_addr_cam(rtwdev, &rtwsta_link->addr_cam);
5026 if (sta->tdls)
5027 rtw89_cam_deinit_bssid_cam(rtwdev, &rtwsta_link->bssid_cam);
5028
5029 if (vif->type == NL80211_IFTYPE_STATION && !sta->tdls) {
5030 rtw89_vif_type_mapping(rtwvif_link, false);
5031 rtw89_fw_release_general_pkt_list_vif(rtwdev, rtwvif_link, true);
5032 }
5033
5034 ret = rtw89_chip_h2c_assoc_cmac_tbl(rtwdev, rtwvif_link, rtwsta_link);
5035 if (ret) {
5036 rtw89_warn(rtwdev, "failed to send h2c cmac table\n");
5037 return ret;
5038 }
5039
5040 ret = rtw89_fw_h2c_join_info(rtwdev, rtwvif_link, rtwsta_link, true);
5041 if (ret) {
5042 rtw89_warn(rtwdev, "failed to send h2c join info\n");
5043 return ret;
5044 }
5045
5046 /* update cam aid mac_id net_type */
5047 ret = rtw89_fw_h2c_cam(rtwdev, rtwvif_link, rtwsta_link, NULL,
5048 RTW89_ROLE_CON_DISCONN);
5049 if (ret) {
5050 rtw89_warn(rtwdev, "failed to send h2c cam\n");
5051 return ret;
5052 }
5053
5054 return ret;
5055 }
5056
rtw89_sta_link_can_er(struct rtw89_dev * rtwdev,struct ieee80211_bss_conf * bss_conf,struct ieee80211_link_sta * link_sta)5057 static bool rtw89_sta_link_can_er(struct rtw89_dev *rtwdev,
5058 struct ieee80211_bss_conf *bss_conf,
5059 struct ieee80211_link_sta *link_sta)
5060 {
5061 if (!bss_conf->he_support ||
5062 bss_conf->he_oper.params & IEEE80211_HE_OPERATION_ER_SU_DISABLE)
5063 return false;
5064
5065 if (rtwdev->chip->chip_id == RTL8852C &&
5066 rtw89_sta_link_has_su_mu_4xhe08(link_sta) &&
5067 !rtw89_sta_link_has_er_su_4xhe08(link_sta))
5068 return false;
5069
5070 return true;
5071 }
5072
rtw89_core_sta_link_assoc(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link,struct rtw89_sta_link * rtwsta_link)5073 int rtw89_core_sta_link_assoc(struct rtw89_dev *rtwdev,
5074 struct rtw89_vif_link *rtwvif_link,
5075 struct rtw89_sta_link *rtwsta_link)
5076 {
5077 const struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link);
5078 const struct ieee80211_sta *sta = rtwsta_link_to_sta(rtwsta_link);
5079 struct rtw89_bssid_cam_entry *bssid_cam = rtw89_get_bssid_cam_of(rtwvif_link,
5080 rtwsta_link);
5081 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev,
5082 rtwvif_link->chanctx_idx);
5083 struct ieee80211_link_sta *link_sta;
5084 int ret;
5085
5086 if (vif->type == NL80211_IFTYPE_AP || sta->tdls) {
5087 if (sta->tdls) {
5088 rcu_read_lock();
5089
5090 link_sta = rtw89_sta_rcu_dereference_link(rtwsta_link, true);
5091 ret = rtw89_cam_init_bssid_cam(rtwdev, rtwvif_link, bssid_cam,
5092 link_sta->addr);
5093 if (ret) {
5094 rtw89_warn(rtwdev, "failed to send h2c init bssid cam for TDLS\n");
5095 rcu_read_unlock();
5096 return ret;
5097 }
5098
5099 rcu_read_unlock();
5100 }
5101
5102 ret = rtw89_cam_init_addr_cam(rtwdev, &rtwsta_link->addr_cam, bssid_cam);
5103 if (ret) {
5104 rtw89_warn(rtwdev, "failed to send h2c init addr cam\n");
5105 return ret;
5106 }
5107 }
5108
5109 ret = rtw89_chip_h2c_assoc_cmac_tbl(rtwdev, rtwvif_link, rtwsta_link);
5110 if (ret) {
5111 rtw89_warn(rtwdev, "failed to send h2c cmac table\n");
5112 return ret;
5113 }
5114
5115 ret = rtw89_fw_h2c_join_info(rtwdev, rtwvif_link, rtwsta_link, false);
5116 if (ret) {
5117 rtw89_warn(rtwdev, "failed to send h2c join info\n");
5118 return ret;
5119 }
5120
5121 /* update cam aid mac_id net_type */
5122 ret = rtw89_fw_h2c_cam(rtwdev, rtwvif_link, rtwsta_link, NULL,
5123 RTW89_ROLE_CON_DISCONN);
5124 if (ret) {
5125 rtw89_warn(rtwdev, "failed to send h2c cam\n");
5126 return ret;
5127 }
5128
5129 rtw89_phy_ra_assoc(rtwdev, rtwsta_link);
5130 rtw89_mac_bf_assoc(rtwdev, rtwvif_link, rtwsta_link);
5131 rtw89_mac_bf_monitor_calc(rtwdev, rtwsta_link, false);
5132
5133 if (vif->type == NL80211_IFTYPE_STATION && !sta->tdls) {
5134 struct ieee80211_bss_conf *bss_conf;
5135
5136 rcu_read_lock();
5137
5138 bss_conf = rtw89_vif_rcu_dereference_link(rtwvif_link, true);
5139 link_sta = rtw89_sta_rcu_dereference_link(rtwsta_link, true);
5140 rtwsta_link->er_cap = rtw89_sta_link_can_er(rtwdev, bss_conf, link_sta);
5141
5142 rcu_read_unlock();
5143
5144 rtw89_btc_ntfy_role_info(rtwdev, rtwvif_link, rtwsta_link,
5145 BTC_ROLE_MSTS_STA_CONN_END);
5146 rtw89_core_get_no_ul_ofdma_htc(rtwdev, &rtwsta_link->htc_template, chan);
5147 rtw89_phy_ul_tb_assoc(rtwdev, rtwvif_link);
5148 rtw89_core_bcn_track_assoc(rtwdev, rtwvif_link);
5149
5150 ret = rtw89_fw_h2c_general_pkt(rtwdev, rtwvif_link, rtwsta_link->mac_id);
5151 if (ret) {
5152 rtw89_warn(rtwdev, "failed to send h2c general packet\n");
5153 return ret;
5154 }
5155
5156 rtw89_fw_h2c_set_bcn_fltr_cfg(rtwdev, rtwvif_link, true);
5157
5158 if (vif->p2p)
5159 rtw89_mac_set_tx_retry_limit(rtwdev, rtwsta_link, false,
5160 rtwsta_link->tx_retry);
5161 rtw89_phy_dig_resume(rtwdev, false);
5162 }
5163
5164 rtw89_assoc_link_set(rtwsta_link);
5165 return ret;
5166 }
5167
rtw89_core_sta_link_remove(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link,struct rtw89_sta_link * rtwsta_link)5168 int rtw89_core_sta_link_remove(struct rtw89_dev *rtwdev,
5169 struct rtw89_vif_link *rtwvif_link,
5170 struct rtw89_sta_link *rtwsta_link)
5171 {
5172 const struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link);
5173 const struct ieee80211_sta *sta = rtwsta_link_to_sta(rtwsta_link);
5174 int ret;
5175
5176 if (vif->type == NL80211_IFTYPE_STATION && !sta->tdls) {
5177 rtw89_reg_6ghz_recalc(rtwdev, rtwvif_link, false);
5178 rtw89_btc_ntfy_role_info(rtwdev, rtwvif_link, rtwsta_link,
5179 BTC_ROLE_MSTS_STA_DIS_CONN);
5180
5181 if (vif->p2p)
5182 rtw89_mac_set_tx_retry_limit(rtwdev, rtwsta_link, false,
5183 rtwsta_link->tx_retry);
5184 } else if (vif->type == NL80211_IFTYPE_AP || sta->tdls) {
5185 ret = rtw89_fw_h2c_role_maintain(rtwdev, rtwvif_link, rtwsta_link,
5186 RTW89_ROLE_REMOVE);
5187 if (ret) {
5188 rtw89_warn(rtwdev, "failed to send h2c role info\n");
5189 return ret;
5190 }
5191 }
5192
5193 return 0;
5194 }
5195
_rtw89_core_set_tid_config(struct rtw89_dev * rtwdev,struct ieee80211_sta * sta,struct cfg80211_tid_cfg * tid_conf)5196 static void _rtw89_core_set_tid_config(struct rtw89_dev *rtwdev,
5197 struct ieee80211_sta *sta,
5198 struct cfg80211_tid_cfg *tid_conf)
5199 {
5200 struct ieee80211_txq *txq;
5201 struct rtw89_txq *rtwtxq;
5202 u32 mask = tid_conf->mask;
5203 u8 tids = tid_conf->tids;
5204 int tids_nbit = BITS_PER_BYTE;
5205 int i;
5206
5207 for (i = 0; i < tids_nbit; i++, tids >>= 1) {
5208 if (!tids)
5209 break;
5210
5211 if (!(tids & BIT(0)))
5212 continue;
5213
5214 txq = sta->txq[i];
5215 rtwtxq = (struct rtw89_txq *)txq->drv_priv;
5216
5217 if (mask & BIT(NL80211_TID_CONFIG_ATTR_AMPDU_CTRL)) {
5218 if (tid_conf->ampdu == NL80211_TID_CONFIG_ENABLE) {
5219 clear_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags);
5220 } else {
5221 if (test_bit(RTW89_TXQ_F_AMPDU, &rtwtxq->flags))
5222 ieee80211_stop_tx_ba_session(sta, txq->tid);
5223 spin_lock_bh(&rtwdev->ba_lock);
5224 list_del_init(&rtwtxq->list);
5225 set_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags);
5226 spin_unlock_bh(&rtwdev->ba_lock);
5227 }
5228 }
5229
5230 if (mask & BIT(NL80211_TID_CONFIG_ATTR_AMSDU_CTRL) && tids == 0xff) {
5231 if (tid_conf->amsdu == NL80211_TID_CONFIG_ENABLE)
5232 sta->max_amsdu_subframes = 0;
5233 else
5234 sta->max_amsdu_subframes = 1;
5235 }
5236 }
5237 }
5238
rtw89_core_set_tid_config(struct rtw89_dev * rtwdev,struct ieee80211_sta * sta,struct cfg80211_tid_config * tid_config)5239 void rtw89_core_set_tid_config(struct rtw89_dev *rtwdev,
5240 struct ieee80211_sta *sta,
5241 struct cfg80211_tid_config *tid_config)
5242 {
5243 int i;
5244
5245 for (i = 0; i < tid_config->n_tid_conf; i++)
5246 _rtw89_core_set_tid_config(rtwdev, sta,
5247 &tid_config->tid_conf[i]);
5248 }
5249
rtw89_init_ht_cap(struct rtw89_dev * rtwdev,struct ieee80211_sta_ht_cap * ht_cap)5250 static void rtw89_init_ht_cap(struct rtw89_dev *rtwdev,
5251 struct ieee80211_sta_ht_cap *ht_cap)
5252 {
5253 static const __le16 highest[RF_PATH_MAX] = {
5254 cpu_to_le16(150), cpu_to_le16(300), cpu_to_le16(450), cpu_to_le16(600),
5255 };
5256 struct rtw89_hal *hal = &rtwdev->hal;
5257 u8 nss = hal->rx_nss;
5258 int i;
5259
5260 ht_cap->ht_supported = true;
5261 ht_cap->cap = 0;
5262 ht_cap->cap |= IEEE80211_HT_CAP_SGI_20 |
5263 IEEE80211_HT_CAP_MAX_AMSDU |
5264 IEEE80211_HT_CAP_TX_STBC |
5265 (1 << IEEE80211_HT_CAP_RX_STBC_SHIFT);
5266 ht_cap->cap |= IEEE80211_HT_CAP_LDPC_CODING;
5267 ht_cap->cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
5268 IEEE80211_HT_CAP_DSSSCCK40 |
5269 IEEE80211_HT_CAP_SGI_40;
5270 ht_cap->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
5271 ht_cap->ampdu_density = IEEE80211_HT_MPDU_DENSITY_NONE;
5272 ht_cap->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
5273 for (i = 0; i < nss; i++)
5274 ht_cap->mcs.rx_mask[i] = 0xFF;
5275 ht_cap->mcs.rx_mask[4] = 0x01;
5276 ht_cap->mcs.rx_highest = highest[nss - 1];
5277 }
5278
rtw89_init_vht_cap(struct rtw89_dev * rtwdev,struct ieee80211_sta_vht_cap * vht_cap)5279 static void rtw89_init_vht_cap(struct rtw89_dev *rtwdev,
5280 struct ieee80211_sta_vht_cap *vht_cap)
5281 {
5282 static const __le16 highest_bw80[RF_PATH_MAX] = {
5283 cpu_to_le16(433), cpu_to_le16(867), cpu_to_le16(1300), cpu_to_le16(1733),
5284 };
5285 static const __le16 highest_bw160[RF_PATH_MAX] = {
5286 cpu_to_le16(867), cpu_to_le16(1733), cpu_to_le16(2600), cpu_to_le16(3467),
5287 };
5288 const struct rtw89_chip_info *chip = rtwdev->chip;
5289 const __le16 *highest = chip->support_bandwidths & BIT(NL80211_CHAN_WIDTH_160) ?
5290 highest_bw160 : highest_bw80;
5291 struct rtw89_hal *hal = &rtwdev->hal;
5292 u16 tx_mcs_map = 0, rx_mcs_map = 0;
5293 u8 sts_cap = 3;
5294 int i;
5295
5296 for (i = 0; i < 8; i++) {
5297 if (i < hal->tx_nss)
5298 tx_mcs_map |= IEEE80211_VHT_MCS_SUPPORT_0_9 << (i * 2);
5299 else
5300 tx_mcs_map |= IEEE80211_VHT_MCS_NOT_SUPPORTED << (i * 2);
5301 if (i < hal->rx_nss)
5302 rx_mcs_map |= IEEE80211_VHT_MCS_SUPPORT_0_9 << (i * 2);
5303 else
5304 rx_mcs_map |= IEEE80211_VHT_MCS_NOT_SUPPORTED << (i * 2);
5305 }
5306
5307 vht_cap->vht_supported = true;
5308 vht_cap->cap = chip->max_vht_mpdu_cap |
5309 IEEE80211_VHT_CAP_SHORT_GI_80 |
5310 IEEE80211_VHT_CAP_RXSTBC_1 |
5311 IEEE80211_VHT_CAP_HTC_VHT |
5312 IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_MASK |
5313 0;
5314 vht_cap->cap |= IEEE80211_VHT_CAP_TXSTBC;
5315 vht_cap->cap |= IEEE80211_VHT_CAP_RXLDPC;
5316 vht_cap->cap |= IEEE80211_VHT_CAP_MU_BEAMFORMEE_CAPABLE |
5317 IEEE80211_VHT_CAP_SU_BEAMFORMEE_CAPABLE;
5318 vht_cap->cap |= sts_cap << IEEE80211_VHT_CAP_BEAMFORMEE_STS_SHIFT;
5319 if (chip->support_bandwidths & BIT(NL80211_CHAN_WIDTH_160))
5320 vht_cap->cap |= IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_160MHZ |
5321 IEEE80211_VHT_CAP_SHORT_GI_160;
5322 vht_cap->vht_mcs.rx_mcs_map = cpu_to_le16(rx_mcs_map);
5323 vht_cap->vht_mcs.tx_mcs_map = cpu_to_le16(tx_mcs_map);
5324 vht_cap->vht_mcs.rx_highest = highest[hal->rx_nss - 1];
5325 vht_cap->vht_mcs.tx_highest = highest[hal->tx_nss - 1];
5326
5327 if (ieee80211_hw_check(rtwdev->hw, SUPPORTS_VHT_EXT_NSS_BW))
5328 vht_cap->vht_mcs.tx_highest |=
5329 cpu_to_le16(IEEE80211_VHT_EXT_NSS_BW_CAPABLE);
5330 }
5331
rtw89_init_he_cap(struct rtw89_dev * rtwdev,enum nl80211_band band,enum nl80211_iftype iftype,struct ieee80211_sband_iftype_data * iftype_data)5332 static void rtw89_init_he_cap(struct rtw89_dev *rtwdev,
5333 enum nl80211_band band,
5334 enum nl80211_iftype iftype,
5335 struct ieee80211_sband_iftype_data *iftype_data)
5336 {
5337 const struct rtw89_chip_info *chip = rtwdev->chip;
5338 struct rtw89_hal *hal = &rtwdev->hal;
5339 bool no_ng16 = (chip->chip_id == RTL8852A && hal->cv == CHIP_CBV) ||
5340 (chip->chip_id == RTL8852B && hal->cv == CHIP_CAV);
5341 struct ieee80211_sta_he_cap *he_cap;
5342 int nss = hal->rx_nss;
5343 u8 *mac_cap_info;
5344 u8 *phy_cap_info;
5345 u16 mcs_map = 0;
5346 int i;
5347
5348 for (i = 0; i < 8; i++) {
5349 if (i < nss)
5350 mcs_map |= IEEE80211_HE_MCS_SUPPORT_0_11 << (i * 2);
5351 else
5352 mcs_map |= IEEE80211_HE_MCS_NOT_SUPPORTED << (i * 2);
5353 }
5354
5355 he_cap = &iftype_data->he_cap;
5356 mac_cap_info = he_cap->he_cap_elem.mac_cap_info;
5357 phy_cap_info = he_cap->he_cap_elem.phy_cap_info;
5358
5359 he_cap->has_he = true;
5360 mac_cap_info[0] = IEEE80211_HE_MAC_CAP0_HTC_HE;
5361 if (iftype == NL80211_IFTYPE_STATION)
5362 mac_cap_info[1] = IEEE80211_HE_MAC_CAP1_TF_MAC_PAD_DUR_16US;
5363 mac_cap_info[2] = IEEE80211_HE_MAC_CAP2_ALL_ACK |
5364 IEEE80211_HE_MAC_CAP2_BSR;
5365 mac_cap_info[3] = IEEE80211_HE_MAC_CAP3_MAX_AMPDU_LEN_EXP_EXT_2;
5366 if (iftype == NL80211_IFTYPE_AP)
5367 mac_cap_info[3] |= IEEE80211_HE_MAC_CAP3_OMI_CONTROL;
5368 mac_cap_info[4] = IEEE80211_HE_MAC_CAP4_OPS |
5369 IEEE80211_HE_MAC_CAP4_AMSDU_IN_AMPDU;
5370 if (iftype == NL80211_IFTYPE_STATION)
5371 mac_cap_info[5] = IEEE80211_HE_MAC_CAP5_HT_VHT_TRIG_FRAME_RX;
5372 if (band == NL80211_BAND_2GHZ) {
5373 phy_cap_info[0] =
5374 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_IN_2G;
5375 } else {
5376 phy_cap_info[0] =
5377 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_80MHZ_IN_5G;
5378 if (chip->support_bandwidths & BIT(NL80211_CHAN_WIDTH_160))
5379 phy_cap_info[0] |= IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_160MHZ_IN_5G;
5380 }
5381 phy_cap_info[1] = IEEE80211_HE_PHY_CAP1_DEVICE_CLASS_A |
5382 IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD |
5383 IEEE80211_HE_PHY_CAP1_HE_LTF_AND_GI_FOR_HE_PPDUS_0_8US;
5384 phy_cap_info[2] = IEEE80211_HE_PHY_CAP2_NDP_4x_LTF_AND_3_2US |
5385 IEEE80211_HE_PHY_CAP2_STBC_TX_UNDER_80MHZ |
5386 IEEE80211_HE_PHY_CAP2_STBC_RX_UNDER_80MHZ |
5387 IEEE80211_HE_PHY_CAP2_DOPPLER_TX;
5388 phy_cap_info[3] = IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_RX_16_QAM;
5389 if (iftype == NL80211_IFTYPE_STATION)
5390 phy_cap_info[3] |= IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_TX_16_QAM |
5391 IEEE80211_HE_PHY_CAP3_DCM_MAX_TX_NSS_2;
5392 if (iftype == NL80211_IFTYPE_AP)
5393 phy_cap_info[3] |= IEEE80211_HE_PHY_CAP3_RX_PARTIAL_BW_SU_IN_20MHZ_MU;
5394 phy_cap_info[4] = IEEE80211_HE_PHY_CAP4_SU_BEAMFORMEE |
5395 IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_UNDER_80MHZ_4;
5396 if (chip->support_bandwidths & BIT(NL80211_CHAN_WIDTH_160))
5397 phy_cap_info[4] |= IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_ABOVE_80MHZ_4;
5398 phy_cap_info[5] = no_ng16 ? 0 :
5399 IEEE80211_HE_PHY_CAP5_NG16_SU_FEEDBACK |
5400 IEEE80211_HE_PHY_CAP5_NG16_MU_FEEDBACK;
5401 phy_cap_info[6] = IEEE80211_HE_PHY_CAP6_CODEBOOK_SIZE_42_SU |
5402 IEEE80211_HE_PHY_CAP6_CODEBOOK_SIZE_75_MU |
5403 IEEE80211_HE_PHY_CAP6_TRIG_SU_BEAMFORMING_FB |
5404 IEEE80211_HE_PHY_CAP6_PARTIAL_BW_EXT_RANGE;
5405 phy_cap_info[7] = IEEE80211_HE_PHY_CAP7_POWER_BOOST_FACTOR_SUPP |
5406 IEEE80211_HE_PHY_CAP7_HE_SU_MU_PPDU_4XLTF_AND_08_US_GI |
5407 IEEE80211_HE_PHY_CAP7_MAX_NC_1;
5408 phy_cap_info[8] = IEEE80211_HE_PHY_CAP8_HE_ER_SU_PPDU_4XLTF_AND_08_US_GI |
5409 IEEE80211_HE_PHY_CAP8_HE_ER_SU_1XLTF_AND_08_US_GI |
5410 IEEE80211_HE_PHY_CAP8_DCM_MAX_RU_996;
5411 if (chip->support_bandwidths & BIT(NL80211_CHAN_WIDTH_160))
5412 phy_cap_info[8] |= IEEE80211_HE_PHY_CAP8_20MHZ_IN_160MHZ_HE_PPDU |
5413 IEEE80211_HE_PHY_CAP8_80MHZ_IN_160MHZ_HE_PPDU;
5414 phy_cap_info[9] = IEEE80211_HE_PHY_CAP9_LONGER_THAN_16_SIGB_OFDM_SYM |
5415 IEEE80211_HE_PHY_CAP9_RX_1024_QAM_LESS_THAN_242_TONE_RU |
5416 IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_COMP_SIGB |
5417 IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_NON_COMP_SIGB |
5418 u8_encode_bits(IEEE80211_HE_PHY_CAP9_NOMINAL_PKT_PADDING_16US,
5419 IEEE80211_HE_PHY_CAP9_NOMINAL_PKT_PADDING_MASK);
5420 if (iftype == NL80211_IFTYPE_STATION)
5421 phy_cap_info[9] |= IEEE80211_HE_PHY_CAP9_TX_1024_QAM_LESS_THAN_242_TONE_RU;
5422 he_cap->he_mcs_nss_supp.rx_mcs_80 = cpu_to_le16(mcs_map);
5423 he_cap->he_mcs_nss_supp.tx_mcs_80 = cpu_to_le16(mcs_map);
5424 if (chip->support_bandwidths & BIT(NL80211_CHAN_WIDTH_160)) {
5425 he_cap->he_mcs_nss_supp.rx_mcs_160 = cpu_to_le16(mcs_map);
5426 he_cap->he_mcs_nss_supp.tx_mcs_160 = cpu_to_le16(mcs_map);
5427 }
5428
5429 if (band == NL80211_BAND_6GHZ) {
5430 __le16 capa;
5431
5432 capa = le16_encode_bits(IEEE80211_HT_MPDU_DENSITY_NONE,
5433 IEEE80211_HE_6GHZ_CAP_MIN_MPDU_START) |
5434 le16_encode_bits(IEEE80211_VHT_MAX_AMPDU_1024K,
5435 IEEE80211_HE_6GHZ_CAP_MAX_AMPDU_LEN_EXP) |
5436 le16_encode_bits(chip->max_vht_mpdu_cap,
5437 IEEE80211_HE_6GHZ_CAP_MAX_MPDU_LEN);
5438 iftype_data->he_6ghz_capa.capa = capa;
5439 }
5440 }
5441
rtw89_init_eht_cap(struct rtw89_dev * rtwdev,enum nl80211_band band,enum nl80211_iftype iftype,struct ieee80211_sband_iftype_data * iftype_data)5442 static void rtw89_init_eht_cap(struct rtw89_dev *rtwdev,
5443 enum nl80211_band band,
5444 enum nl80211_iftype iftype,
5445 struct ieee80211_sband_iftype_data *iftype_data)
5446 {
5447 const struct rtw89_chip_info *chip = rtwdev->chip;
5448 struct ieee80211_eht_cap_elem_fixed *eht_cap_elem;
5449 struct ieee80211_eht_mcs_nss_supp *eht_nss;
5450 struct ieee80211_sta_eht_cap *eht_cap;
5451 struct rtw89_hal *hal = &rtwdev->hal;
5452 bool support_mcs_12_13 = true;
5453 bool support_320mhz = false;
5454 u8 val, val_mcs13;
5455 int sts = 8;
5456
5457 if (chip->chip_gen == RTW89_CHIP_AX || hal->no_eht)
5458 return;
5459
5460 if (hal->no_mcs_12_13)
5461 support_mcs_12_13 = false;
5462
5463 if (band == NL80211_BAND_6GHZ &&
5464 chip->support_bandwidths & BIT(NL80211_CHAN_WIDTH_320))
5465 support_320mhz = true;
5466
5467 eht_cap = &iftype_data->eht_cap;
5468 eht_cap_elem = &eht_cap->eht_cap_elem;
5469 eht_nss = &eht_cap->eht_mcs_nss_supp;
5470
5471 eht_cap->has_eht = true;
5472
5473 eht_cap_elem->mac_cap_info[0] =
5474 u8_encode_bits(chip->max_eht_mpdu_cap,
5475 IEEE80211_EHT_MAC_CAP0_MAX_MPDU_LEN_MASK);
5476 eht_cap_elem->mac_cap_info[1] = 0;
5477
5478 eht_cap_elem->phy_cap_info[0] =
5479 IEEE80211_EHT_PHY_CAP0_NDP_4_EHT_LFT_32_GI |
5480 IEEE80211_EHT_PHY_CAP0_SU_BEAMFORMEE;
5481 if (support_320mhz)
5482 eht_cap_elem->phy_cap_info[0] |=
5483 IEEE80211_EHT_PHY_CAP0_320MHZ_IN_6GHZ;
5484
5485 eht_cap_elem->phy_cap_info[0] |=
5486 u8_encode_bits(u8_get_bits(sts - 1, BIT(0)),
5487 IEEE80211_EHT_PHY_CAP0_BEAMFORMEE_SS_80MHZ_MASK);
5488 eht_cap_elem->phy_cap_info[1] =
5489 u8_encode_bits(u8_get_bits(sts - 1, GENMASK(2, 1)),
5490 IEEE80211_EHT_PHY_CAP1_BEAMFORMEE_SS_80MHZ_MASK) |
5491 u8_encode_bits(sts - 1,
5492 IEEE80211_EHT_PHY_CAP1_BEAMFORMEE_SS_160MHZ_MASK);
5493 if (support_320mhz)
5494 eht_cap_elem->phy_cap_info[1] |=
5495 u8_encode_bits(sts - 1,
5496 IEEE80211_EHT_PHY_CAP1_BEAMFORMEE_SS_320MHZ_MASK);
5497
5498 eht_cap_elem->phy_cap_info[2] = 0;
5499
5500 eht_cap_elem->phy_cap_info[3] =
5501 IEEE80211_EHT_PHY_CAP3_CODEBOOK_4_2_SU_FDBK |
5502 IEEE80211_EHT_PHY_CAP3_CODEBOOK_7_5_MU_FDBK |
5503 IEEE80211_EHT_PHY_CAP3_TRIG_SU_BF_FDBK |
5504 IEEE80211_EHT_PHY_CAP3_TRIG_MU_BF_PART_BW_FDBK;
5505
5506 eht_cap_elem->phy_cap_info[4] =
5507 IEEE80211_EHT_PHY_CAP4_POWER_BOOST_FACT_SUPP |
5508 u8_encode_bits(1, IEEE80211_EHT_PHY_CAP4_MAX_NC_MASK);
5509
5510 eht_cap_elem->phy_cap_info[5] =
5511 u8_encode_bits(IEEE80211_EHT_PHY_CAP5_COMMON_NOMINAL_PKT_PAD_20US,
5512 IEEE80211_EHT_PHY_CAP5_COMMON_NOMINAL_PKT_PAD_MASK);
5513
5514 eht_cap_elem->phy_cap_info[6] = 0;
5515 eht_cap_elem->phy_cap_info[7] = 0;
5516 eht_cap_elem->phy_cap_info[8] = 0;
5517
5518 val = u8_encode_bits(hal->rx_nss, IEEE80211_EHT_MCS_NSS_RX) |
5519 u8_encode_bits(hal->tx_nss, IEEE80211_EHT_MCS_NSS_TX);
5520 val_mcs13 = support_mcs_12_13 ? val : 0;
5521
5522 eht_nss->bw._80.rx_tx_mcs9_max_nss = val;
5523 eht_nss->bw._80.rx_tx_mcs11_max_nss = val;
5524 eht_nss->bw._80.rx_tx_mcs13_max_nss = val_mcs13;
5525 eht_nss->bw._160.rx_tx_mcs9_max_nss = val;
5526 eht_nss->bw._160.rx_tx_mcs11_max_nss = val;
5527 eht_nss->bw._160.rx_tx_mcs13_max_nss = val_mcs13;
5528 if (support_320mhz) {
5529 eht_nss->bw._320.rx_tx_mcs9_max_nss = val;
5530 eht_nss->bw._320.rx_tx_mcs11_max_nss = val;
5531 eht_nss->bw._320.rx_tx_mcs13_max_nss = val_mcs13;
5532 }
5533 }
5534
5535 #define RTW89_SBAND_IFTYPES_NR 2
5536
rtw89_init_he_eht_cap(struct rtw89_dev * rtwdev,enum nl80211_band band,struct ieee80211_supported_band * sband)5537 static int rtw89_init_he_eht_cap(struct rtw89_dev *rtwdev,
5538 enum nl80211_band band,
5539 struct ieee80211_supported_band *sband)
5540 {
5541 struct ieee80211_sband_iftype_data *iftype_data;
5542 enum nl80211_iftype iftype;
5543 int idx = 0;
5544
5545 iftype_data = devm_kcalloc(rtwdev->dev, RTW89_SBAND_IFTYPES_NR,
5546 sizeof(*iftype_data), GFP_KERNEL);
5547 if (!iftype_data)
5548 return -ENOMEM;
5549
5550 for (iftype = 0; iftype < NUM_NL80211_IFTYPES; iftype++) {
5551 switch (iftype) {
5552 case NL80211_IFTYPE_STATION:
5553 case NL80211_IFTYPE_AP:
5554 break;
5555 default:
5556 continue;
5557 }
5558
5559 if (idx >= RTW89_SBAND_IFTYPES_NR) {
5560 rtw89_warn(rtwdev, "run out of iftype_data\n");
5561 break;
5562 }
5563
5564 iftype_data[idx].types_mask = BIT(iftype);
5565
5566 rtw89_init_he_cap(rtwdev, band, iftype, &iftype_data[idx]);
5567 rtw89_init_eht_cap(rtwdev, band, iftype, &iftype_data[idx]);
5568
5569 idx++;
5570 }
5571
5572 _ieee80211_set_sband_iftype_data(sband, iftype_data, idx);
5573 return 0;
5574 }
5575
5576 static struct ieee80211_supported_band *
rtw89_core_sband_dup(struct rtw89_dev * rtwdev,const struct ieee80211_supported_band * sband)5577 rtw89_core_sband_dup(struct rtw89_dev *rtwdev,
5578 const struct ieee80211_supported_band *sband)
5579 {
5580 struct ieee80211_supported_band *dup;
5581
5582 dup = devm_kmemdup(rtwdev->dev, sband, sizeof(*sband), GFP_KERNEL);
5583 if (!dup)
5584 return NULL;
5585
5586 dup->channels = devm_kmemdup(rtwdev->dev, sband->channels,
5587 sizeof(*sband->channels) * sband->n_channels,
5588 GFP_KERNEL);
5589 if (!dup->channels)
5590 return NULL;
5591
5592 dup->bitrates = devm_kmemdup(rtwdev->dev, sband->bitrates,
5593 sizeof(*sband->bitrates) * sband->n_bitrates,
5594 GFP_KERNEL);
5595 if (!dup->bitrates)
5596 return NULL;
5597
5598 return dup;
5599 }
5600
rtw89_core_set_supported_band(struct rtw89_dev * rtwdev)5601 static int rtw89_core_set_supported_band(struct rtw89_dev *rtwdev)
5602 {
5603 struct ieee80211_hw *hw = rtwdev->hw;
5604 struct ieee80211_supported_band *sband;
5605 u8 support_bands = rtwdev->chip->support_bands;
5606 int ret;
5607
5608 if (support_bands & BIT(NL80211_BAND_2GHZ)) {
5609 sband = rtw89_core_sband_dup(rtwdev, &rtw89_sband_2ghz);
5610 if (!sband)
5611 return -ENOMEM;
5612 #if defined(__FreeBSD__)
5613 if (rtw_ht_support)
5614 #endif
5615 rtw89_init_ht_cap(rtwdev, &sband->ht_cap);
5616 #if defined(__FreeBSD__)
5617 if (rtw_eht_support) {
5618 #endif
5619 ret = rtw89_init_he_eht_cap(rtwdev, NL80211_BAND_2GHZ, sband);
5620 if (ret)
5621 return ret;
5622 #if defined(__FreeBSD__)
5623 }
5624 #endif
5625 hw->wiphy->bands[NL80211_BAND_2GHZ] = sband;
5626 }
5627
5628 if (support_bands & BIT(NL80211_BAND_5GHZ)) {
5629 sband = rtw89_core_sband_dup(rtwdev, &rtw89_sband_5ghz);
5630 if (!sband)
5631 return -ENOMEM;
5632 #if defined(__FreeBSD__)
5633 if (rtw_ht_support)
5634 #endif
5635 rtw89_init_ht_cap(rtwdev, &sband->ht_cap);
5636 #if defined(__FreeBSD__)
5637 if (rtw_vht_support)
5638 #endif
5639 rtw89_init_vht_cap(rtwdev, &sband->vht_cap);
5640 #if defined(__FreeBSD__)
5641 if (rtw_eht_support) {
5642 #endif
5643 ret = rtw89_init_he_eht_cap(rtwdev, NL80211_BAND_5GHZ, sband);
5644 if (ret)
5645 return ret;
5646 #if defined(__FreeBSD__)
5647 }
5648 #endif
5649 hw->wiphy->bands[NL80211_BAND_5GHZ] = sband;
5650 }
5651
5652 #if defined(__FreeBSD__)
5653 if (rtw_eht_support)
5654 #endif
5655 if (support_bands & BIT(NL80211_BAND_6GHZ)) {
5656 sband = rtw89_core_sband_dup(rtwdev, &rtw89_sband_6ghz);
5657 if (!sband)
5658 return -ENOMEM;
5659 ret = rtw89_init_he_eht_cap(rtwdev, NL80211_BAND_6GHZ, sband);
5660 if (ret)
5661 return ret;
5662 hw->wiphy->bands[NL80211_BAND_6GHZ] = sband;
5663 }
5664
5665 return 0;
5666 }
5667
rtw89_core_ppdu_sts_init(struct rtw89_dev * rtwdev)5668 static void rtw89_core_ppdu_sts_init(struct rtw89_dev *rtwdev)
5669 {
5670 int i;
5671
5672 for (i = 0; i < RTW89_PHY_NUM; i++)
5673 skb_queue_head_init(&rtwdev->ppdu_sts.rx_queue[i]);
5674 for (i = 0; i < RTW89_PHY_NUM; i++)
5675 rtwdev->ppdu_sts.curr_rx_ppdu_cnt[i] = U8_MAX;
5676 }
5677
rtw89_core_update_beacon_work(struct wiphy * wiphy,struct wiphy_work * work)5678 void rtw89_core_update_beacon_work(struct wiphy *wiphy, struct wiphy_work *work)
5679 {
5680 struct rtw89_dev *rtwdev;
5681 struct rtw89_vif_link *rtwvif_link = container_of(work, struct rtw89_vif_link,
5682 update_beacon_work);
5683
5684 lockdep_assert_wiphy(wiphy);
5685
5686 if (rtwvif_link->net_type != RTW89_NET_TYPE_AP_MODE)
5687 return;
5688
5689 rtwdev = rtwvif_link->rtwvif->rtwdev;
5690
5691 rtw89_chip_h2c_update_beacon(rtwdev, rtwvif_link);
5692 }
5693
rtw89_core_csa_beacon_work(struct wiphy * wiphy,struct wiphy_work * work)5694 void rtw89_core_csa_beacon_work(struct wiphy *wiphy, struct wiphy_work *work)
5695 {
5696 struct rtw89_vif_link *rtwvif_link =
5697 container_of(work, struct rtw89_vif_link, csa_beacon_work.work);
5698 struct rtw89_vif *rtwvif = rtwvif_link->rtwvif;
5699 struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif);
5700 struct rtw89_dev *rtwdev = rtwvif->rtwdev;
5701 struct ieee80211_bss_conf *bss_conf;
5702 unsigned int delay;
5703
5704 lockdep_assert_wiphy(wiphy);
5705
5706 if (rtwvif_link->net_type != RTW89_NET_TYPE_AP_MODE)
5707 return;
5708
5709 rcu_read_lock();
5710
5711 bss_conf = rtw89_vif_rcu_dereference_link(rtwvif_link, true);
5712 if (!bss_conf->csa_active) {
5713 rcu_read_unlock();
5714 return;
5715 }
5716
5717 delay = ieee80211_tu_to_usec(bss_conf->beacon_int);
5718
5719 rcu_read_unlock();
5720
5721 if (!ieee80211_beacon_cntdwn_is_complete(vif, rtwvif_link->link_id)) {
5722 rtw89_chip_h2c_update_beacon(rtwdev, rtwvif_link);
5723
5724 wiphy_delayed_work_queue(wiphy, &rtwvif_link->csa_beacon_work,
5725 usecs_to_jiffies(delay));
5726 } else {
5727 ieee80211_csa_finish(vif, rtwvif_link->link_id);
5728 }
5729 }
5730
5731 struct rtw89_wait_response *
rtw89_wait_for_cond_prep(struct rtw89_wait_info * wait,unsigned int cond)5732 rtw89_wait_for_cond_prep(struct rtw89_wait_info *wait, unsigned int cond)
5733 {
5734 struct rtw89_wait_response *prep;
5735 unsigned int cur;
5736
5737 /* use -EPERM _iff_ telling eval side not to make any changes */
5738
5739 cur = atomic_cmpxchg(&wait->cond, RTW89_WAIT_COND_IDLE, cond);
5740 if (cur != RTW89_WAIT_COND_IDLE)
5741 return ERR_PTR(-EPERM);
5742
5743 prep = kzalloc_obj(*prep);
5744 if (!prep)
5745 return ERR_PTR(-ENOMEM);
5746
5747 init_completion(&prep->completion);
5748
5749 rcu_assign_pointer(wait->resp, prep);
5750
5751 return prep;
5752 }
5753
rtw89_wait_for_cond_eval(struct rtw89_wait_info * wait,struct rtw89_wait_response * prep,int err)5754 int rtw89_wait_for_cond_eval(struct rtw89_wait_info *wait,
5755 struct rtw89_wait_response *prep, int err)
5756 {
5757 unsigned long time_left;
5758
5759 if (IS_ERR(prep)) {
5760 err = err ?: PTR_ERR(prep);
5761
5762 /* special error case: no permission to reset anything */
5763 if (PTR_ERR(prep) == -EPERM)
5764 return err;
5765
5766 goto reset;
5767 }
5768
5769 if (err)
5770 goto cleanup;
5771
5772 time_left = wait_for_completion_timeout(&prep->completion,
5773 RTW89_WAIT_FOR_COND_TIMEOUT);
5774 if (time_left == 0) {
5775 err = -ETIMEDOUT;
5776 goto cleanup;
5777 }
5778
5779 wait->data = prep->data;
5780
5781 cleanup:
5782 rcu_assign_pointer(wait->resp, NULL);
5783 kfree_rcu(prep, rcu_head);
5784
5785 reset:
5786 atomic_set(&wait->cond, RTW89_WAIT_COND_IDLE);
5787
5788 if (err)
5789 return err;
5790
5791 if (wait->data.err)
5792 return -EFAULT;
5793
5794 return 0;
5795 }
5796
rtw89_complete_cond_resp(struct rtw89_wait_response * resp,const struct rtw89_completion_data * data)5797 static void rtw89_complete_cond_resp(struct rtw89_wait_response *resp,
5798 const struct rtw89_completion_data *data)
5799 {
5800 resp->data = *data;
5801 complete(&resp->completion);
5802 }
5803
rtw89_complete_cond(struct rtw89_wait_info * wait,unsigned int cond,const struct rtw89_completion_data * data)5804 void rtw89_complete_cond(struct rtw89_wait_info *wait, unsigned int cond,
5805 const struct rtw89_completion_data *data)
5806 {
5807 struct rtw89_wait_response *resp;
5808 unsigned int cur;
5809
5810 guard(rcu)();
5811
5812 resp = rcu_dereference(wait->resp);
5813 if (!resp)
5814 return;
5815
5816 cur = atomic_cmpxchg(&wait->cond, cond, RTW89_WAIT_COND_IDLE);
5817 if (cur != cond)
5818 return;
5819
5820 rtw89_complete_cond_resp(resp, data);
5821 }
5822
rtw89_core_ntfy_btc_event(struct rtw89_dev * rtwdev,enum rtw89_btc_hmsg event)5823 void rtw89_core_ntfy_btc_event(struct rtw89_dev *rtwdev, enum rtw89_btc_hmsg event)
5824 {
5825 u16 bt_req_len;
5826
5827 switch (event) {
5828 case RTW89_BTC_HMSG_SET_BT_REQ_SLOT:
5829 bt_req_len = rtw89_coex_query_bt_req_len(rtwdev, RTW89_PHY_0);
5830 rtw89_debug(rtwdev, RTW89_DBG_BTC,
5831 "coex updates BT req len to %d TU\n", bt_req_len);
5832 rtw89_queue_chanctx_change(rtwdev, RTW89_CHANCTX_BT_SLOT_CHANGE);
5833 break;
5834 default:
5835 if (event < NUM_OF_RTW89_BTC_HMSG)
5836 rtw89_debug(rtwdev, RTW89_DBG_BTC,
5837 "unhandled BTC HMSG event: %d\n", event);
5838 else
5839 rtw89_warn(rtwdev,
5840 "unrecognized BTC HMSG event: %d\n", event);
5841 break;
5842 }
5843 }
5844
rtw89_check_quirks(struct rtw89_dev * rtwdev,const struct dmi_system_id * quirks)5845 void rtw89_check_quirks(struct rtw89_dev *rtwdev, const struct dmi_system_id *quirks)
5846 {
5847 const struct dmi_system_id *match;
5848 enum rtw89_quirks quirk;
5849
5850 if (!quirks)
5851 return;
5852
5853 for (match = dmi_first_match(quirks); match; match = dmi_first_match(match + 1)) {
5854 quirk = (uintptr_t)match->driver_data;
5855 if (quirk >= NUM_OF_RTW89_QUIRKS)
5856 continue;
5857
5858 set_bit(quirk, rtwdev->quirks);
5859 }
5860 }
5861 EXPORT_SYMBOL(rtw89_check_quirks);
5862
rtw89_core_start(struct rtw89_dev * rtwdev)5863 int rtw89_core_start(struct rtw89_dev *rtwdev)
5864 {
5865 bool no_bbmcu = !rtwdev->chip->bbmcu_nr;
5866 int ret;
5867
5868 ret = rtw89_mac_preinit(rtwdev);
5869 if (ret) {
5870 rtw89_err(rtwdev, "mac preinit fail, ret: %d\n", ret);
5871 return ret;
5872 }
5873
5874 if (no_bbmcu)
5875 rtw89_chip_bb_preinit(rtwdev);
5876
5877 rtw89_phy_init_bb_afe(rtwdev);
5878
5879 /* above do preinit before downloading firmware */
5880
5881 ret = rtw89_mac_init(rtwdev);
5882 if (ret) {
5883 rtw89_err(rtwdev, "mac init fail, ret:%d\n", ret);
5884 return ret;
5885 }
5886
5887 rtw89_btc_ntfy_poweron(rtwdev);
5888
5889 /* efuse process */
5890
5891 /* pre-config BB/RF, BB reset/RFC reset */
5892 ret = rtw89_chip_reset_bb_rf(rtwdev);
5893 if (ret)
5894 return ret;
5895
5896 rtw89_phy_init_bb_reg(rtwdev);
5897 rtw89_chip_bb_postinit(rtwdev);
5898 rtw89_phy_init_rf_reg(rtwdev, false);
5899
5900 rtw89_btc_ntfy_init(rtwdev, BTC_MODE_NORMAL);
5901
5902 rtw89_phy_dm_init(rtwdev);
5903
5904 rtw89_mac_set_edcca_mode_bands(rtwdev, true);
5905 rtw89_mac_cfg_ppdu_status_bands(rtwdev, true);
5906 rtw89_mac_cfg_phy_rpt_bands(rtwdev, true);
5907 rtw89_mac_update_rts_threshold(rtwdev);
5908
5909 ret = rtw89_hci_start(rtwdev);
5910 if (ret) {
5911 rtw89_err(rtwdev, "failed to start hci\n");
5912 return ret;
5913 }
5914
5915 wiphy_delayed_work_queue(rtwdev->hw->wiphy, &rtwdev->track_work,
5916 RTW89_TRACK_WORK_PERIOD);
5917 wiphy_delayed_work_queue(rtwdev->hw->wiphy, &rtwdev->track_ps_work,
5918 RTW89_TRACK_PS_WORK_PERIOD);
5919
5920 set_bit(RTW89_FLAG_RUNNING, rtwdev->flags);
5921
5922 rtw89_chip_rfk_init_late(rtwdev);
5923 rtw89_btc_ntfy_radio_state(rtwdev, BTC_RFCTRL_WL_ON);
5924 rtw89_fw_h2c_fw_log(rtwdev, rtwdev->fw.log.enable);
5925 rtw89_fw_h2c_init_ba_cam(rtwdev);
5926 rtw89_tas_fw_timer_enable(rtwdev, true);
5927 rtwdev->ps_hang_cnt = 0;
5928
5929 return 0;
5930 }
5931
rtw89_core_stop(struct rtw89_dev * rtwdev)5932 void rtw89_core_stop(struct rtw89_dev *rtwdev)
5933 {
5934 struct wiphy *wiphy = rtwdev->hw->wiphy;
5935 struct rtw89_btc *btc = &rtwdev->btc;
5936
5937 lockdep_assert_wiphy(wiphy);
5938
5939 /* Prvent to stop twice; enter_ips and ops_stop */
5940 if (!test_bit(RTW89_FLAG_RUNNING, rtwdev->flags))
5941 return;
5942
5943 rtw89_tas_fw_timer_enable(rtwdev, false);
5944 rtw89_btc_ntfy_radio_state(rtwdev, BTC_RFCTRL_WL_OFF);
5945
5946 clear_bit(RTW89_FLAG_RUNNING, rtwdev->flags);
5947
5948 wiphy_work_cancel(wiphy, &rtwdev->c2h_work);
5949 wiphy_work_cancel(wiphy, &rtwdev->cancel_6ghz_probe_work);
5950 wiphy_work_cancel(wiphy, &btc->eapol_notify_work);
5951 wiphy_work_cancel(wiphy, &btc->arp_notify_work);
5952 wiphy_work_cancel(wiphy, &btc->dhcp_notify_work);
5953 wiphy_work_cancel(wiphy, &btc->icmp_notify_work);
5954 cancel_delayed_work_sync(&rtwdev->txq_reinvoke_work);
5955 wiphy_delayed_work_cancel(wiphy, &rtwdev->tx_wait_work);
5956 wiphy_delayed_work_cancel(wiphy, &rtwdev->track_work);
5957 wiphy_delayed_work_cancel(wiphy, &rtwdev->track_ps_work);
5958 wiphy_delayed_work_cancel(wiphy, &rtwdev->chanctx_work);
5959 wiphy_delayed_work_cancel(wiphy, &rtwdev->coex_act1_work);
5960 wiphy_delayed_work_cancel(wiphy, &rtwdev->coex_bt_devinfo_work);
5961 wiphy_delayed_work_cancel(wiphy, &rtwdev->coex_rfk_chk_work);
5962 wiphy_delayed_work_cancel(wiphy, &rtwdev->cfo_track_work);
5963 wiphy_delayed_work_cancel(wiphy, &rtwdev->mcc_prepare_done_work);
5964 cancel_delayed_work_sync(&rtwdev->forbid_ba_work);
5965 wiphy_delayed_work_cancel(wiphy, &rtwdev->antdiv_work);
5966
5967 rtw89_btc_ntfy_poweroff(rtwdev);
5968 rtw89_hci_flush_queues(rtwdev, BIT(rtwdev->hw->queues) - 1, true);
5969 rtw89_mac_flush_txq(rtwdev, BIT(rtwdev->hw->queues) - 1, true);
5970 rtw89_hci_stop(rtwdev);
5971 rtw89_hci_deinit(rtwdev);
5972 rtw89_mac_pwr_off(rtwdev);
5973 rtw89_hci_reset(rtwdev);
5974 }
5975
rtw89_acquire_mac_id(struct rtw89_dev * rtwdev)5976 u8 rtw89_acquire_mac_id(struct rtw89_dev *rtwdev)
5977 {
5978 const struct rtw89_chip_info *chip = rtwdev->chip;
5979 u8 mac_id_num;
5980 u8 mac_id;
5981
5982 if (rtwdev->support_mlo)
5983 mac_id_num = chip->support_macid_num / chip->support_link_num;
5984 else
5985 mac_id_num = chip->support_macid_num;
5986
5987 mac_id = find_first_zero_bit(rtwdev->mac_id_map, mac_id_num);
5988 if (mac_id == mac_id_num)
5989 return RTW89_MAX_MAC_ID_NUM;
5990
5991 set_bit(mac_id, rtwdev->mac_id_map);
5992 return mac_id;
5993 }
5994
rtw89_release_mac_id(struct rtw89_dev * rtwdev,u8 mac_id)5995 void rtw89_release_mac_id(struct rtw89_dev *rtwdev, u8 mac_id)
5996 {
5997 clear_bit(mac_id, rtwdev->mac_id_map);
5998 }
5999
rtw89_init_vif(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif,u8 mac_id,u8 port)6000 void rtw89_init_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
6001 u8 mac_id, u8 port)
6002 {
6003 const struct rtw89_chip_info *chip = rtwdev->chip;
6004 u8 support_link_num = chip->support_link_num;
6005 u8 support_mld_num = 0;
6006 unsigned int link_id;
6007 u8 index;
6008
6009 bitmap_zero(rtwvif->links_inst_map, __RTW89_MLD_MAX_LINK_NUM);
6010 for (link_id = 0; link_id < IEEE80211_MLD_MAX_NUM_LINKS; link_id++)
6011 rtwvif->links[link_id] = NULL;
6012
6013 rtwvif->rtwdev = rtwdev;
6014
6015 if (rtwdev->support_mlo) {
6016 rtwvif->links_inst_valid_num = support_link_num;
6017 support_mld_num = chip->support_macid_num / support_link_num;
6018 } else {
6019 rtwvif->links_inst_valid_num = 1;
6020 }
6021
6022 for (index = 0; index < rtwvif->links_inst_valid_num; index++) {
6023 struct rtw89_vif_link *inst = &rtwvif->links_inst[index];
6024
6025 inst->rtwvif = rtwvif;
6026 inst->mac_id = mac_id + index * support_mld_num;
6027 inst->mac_idx = RTW89_MAC_0 + index;
6028 inst->phy_idx = RTW89_PHY_0 + index;
6029
6030 /* multi-link use the same port id on different HW bands */
6031 inst->port = port;
6032 }
6033 }
6034
rtw89_init_sta(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif,struct rtw89_sta * rtwsta,u8 mac_id)6035 void rtw89_init_sta(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
6036 struct rtw89_sta *rtwsta, u8 mac_id)
6037 {
6038 const struct rtw89_chip_info *chip = rtwdev->chip;
6039 u8 support_link_num = chip->support_link_num;
6040 u8 support_mld_num = 0;
6041 unsigned int link_id;
6042 u8 index;
6043
6044 bitmap_zero(rtwsta->links_inst_map, __RTW89_MLD_MAX_LINK_NUM);
6045 for (link_id = 0; link_id < IEEE80211_MLD_MAX_NUM_LINKS; link_id++)
6046 rtwsta->links[link_id] = NULL;
6047
6048 rtwsta->rtwdev = rtwdev;
6049 rtwsta->rtwvif = rtwvif;
6050
6051 if (rtwdev->support_mlo) {
6052 rtwsta->links_inst_valid_num = support_link_num;
6053 support_mld_num = chip->support_macid_num / support_link_num;
6054 } else {
6055 rtwsta->links_inst_valid_num = 1;
6056 }
6057
6058 for (index = 0; index < rtwsta->links_inst_valid_num; index++) {
6059 struct rtw89_sta_link *inst = &rtwsta->links_inst[index];
6060
6061 inst->rtwvif_link = &rtwvif->links_inst[index];
6062
6063 inst->rtwsta = rtwsta;
6064 inst->mac_id = mac_id + index * support_mld_num;
6065 }
6066 }
6067
rtw89_vif_set_link(struct rtw89_vif * rtwvif,unsigned int link_id)6068 struct rtw89_vif_link *rtw89_vif_set_link(struct rtw89_vif *rtwvif,
6069 unsigned int link_id)
6070 {
6071 struct rtw89_vif_link *rtwvif_link = rtwvif->links[link_id];
6072 u8 index;
6073 int ret;
6074
6075 if (rtwvif_link)
6076 return rtwvif_link;
6077
6078 index = find_first_zero_bit(rtwvif->links_inst_map,
6079 rtwvif->links_inst_valid_num);
6080 if (index == rtwvif->links_inst_valid_num) {
6081 ret = -EBUSY;
6082 goto err;
6083 }
6084
6085 rtwvif_link = &rtwvif->links_inst[index];
6086 rtwvif_link->link_id = link_id;
6087
6088 set_bit(index, rtwvif->links_inst_map);
6089 rtwvif->links[link_id] = rtwvif_link;
6090 list_add_tail(&rtwvif_link->dlink_schd, &rtwvif->dlink_pool);
6091 return rtwvif_link;
6092
6093 err:
6094 rtw89_err(rtwvif->rtwdev, "vif (link_id %u) failed to set link: %d\n",
6095 link_id, ret);
6096 return NULL;
6097 }
6098
rtw89_vif_unset_link(struct rtw89_vif * rtwvif,unsigned int link_id)6099 void rtw89_vif_unset_link(struct rtw89_vif *rtwvif, unsigned int link_id)
6100 {
6101 struct rtw89_vif_link **container = &rtwvif->links[link_id];
6102 struct rtw89_vif_link *link = *container;
6103 u8 index;
6104
6105 if (!link)
6106 return;
6107
6108 index = rtw89_vif_link_inst_get_index(link);
6109 clear_bit(index, rtwvif->links_inst_map);
6110 *container = NULL;
6111 list_del(&link->dlink_schd);
6112 }
6113
rtw89_sta_set_link(struct rtw89_sta * rtwsta,unsigned int link_id)6114 struct rtw89_sta_link *rtw89_sta_set_link(struct rtw89_sta *rtwsta,
6115 unsigned int link_id)
6116 {
6117 struct rtw89_vif *rtwvif = rtwsta->rtwvif;
6118 struct rtw89_vif_link *rtwvif_link = rtwvif->links[link_id];
6119 struct rtw89_sta_link *rtwsta_link = rtwsta->links[link_id];
6120 u8 index;
6121 int ret;
6122
6123 if (rtwsta_link)
6124 return rtwsta_link;
6125
6126 if (!rtwvif_link) {
6127 ret = -ENOLINK;
6128 goto err;
6129 }
6130
6131 index = rtw89_vif_link_inst_get_index(rtwvif_link);
6132 if (test_bit(index, rtwsta->links_inst_map)) {
6133 ret = -EBUSY;
6134 goto err;
6135 }
6136
6137 rtwsta_link = &rtwsta->links_inst[index];
6138 rtwsta_link->link_id = link_id;
6139
6140 set_bit(index, rtwsta->links_inst_map);
6141 rtwsta->links[link_id] = rtwsta_link;
6142 list_add_tail(&rtwsta_link->dlink_schd, &rtwsta->dlink_pool);
6143 return rtwsta_link;
6144
6145 err:
6146 rtw89_err(rtwsta->rtwdev, "sta (link_id %u) failed to set link: %d\n",
6147 link_id, ret);
6148 return NULL;
6149 }
6150
rtw89_sta_unset_link(struct rtw89_sta * rtwsta,unsigned int link_id)6151 void rtw89_sta_unset_link(struct rtw89_sta *rtwsta, unsigned int link_id)
6152 {
6153 struct rtw89_sta_link **container = &rtwsta->links[link_id];
6154 struct rtw89_sta_link *link = *container;
6155 u8 index;
6156
6157 if (!link)
6158 return;
6159
6160 index = rtw89_sta_link_inst_get_index(link);
6161 clear_bit(index, rtwsta->links_inst_map);
6162 *container = NULL;
6163 list_del(&link->dlink_schd);
6164 }
6165
rtw89_core_init(struct rtw89_dev * rtwdev)6166 int rtw89_core_init(struct rtw89_dev *rtwdev)
6167 {
6168 struct rtw89_btc *btc = &rtwdev->btc;
6169 u8 band;
6170
6171 bitmap_or(rtwdev->quirks, rtwdev->quirks, &rtwdev->chip->default_quirks,
6172 NUM_OF_RTW89_QUIRKS);
6173
6174 INIT_LIST_HEAD(&rtwdev->ba_list);
6175 INIT_LIST_HEAD(&rtwdev->forbid_ba_list);
6176 INIT_LIST_HEAD(&rtwdev->rtwvifs_list);
6177 INIT_LIST_HEAD(&rtwdev->early_h2c_list);
6178 for (band = NL80211_BAND_2GHZ; band < NUM_NL80211_BANDS; band++) {
6179 if (!(rtwdev->chip->support_bands & BIT(band)))
6180 continue;
6181 INIT_LIST_HEAD(&rtwdev->scan_info.pkt_list[band]);
6182 }
6183 INIT_LIST_HEAD(&rtwdev->scan_info.chan_list);
6184 INIT_LIST_HEAD(&rtwdev->tx_waits);
6185 INIT_WORK(&rtwdev->ba_work, rtw89_core_ba_work);
6186 INIT_WORK(&rtwdev->txq_work, rtw89_core_txq_work);
6187 INIT_DELAYED_WORK(&rtwdev->txq_reinvoke_work, rtw89_core_txq_reinvoke_work);
6188 wiphy_delayed_work_init(&rtwdev->track_work, rtw89_track_work);
6189 wiphy_delayed_work_init(&rtwdev->track_ps_work, rtw89_track_ps_work);
6190 wiphy_delayed_work_init(&rtwdev->chanctx_work, rtw89_chanctx_work);
6191 wiphy_delayed_work_init(&rtwdev->coex_act1_work, rtw89_coex_act1_work);
6192 wiphy_delayed_work_init(&rtwdev->coex_bt_devinfo_work, rtw89_coex_bt_devinfo_work);
6193 wiphy_delayed_work_init(&rtwdev->coex_rfk_chk_work, rtw89_coex_rfk_chk_work);
6194 wiphy_delayed_work_init(&rtwdev->cfo_track_work, rtw89_phy_cfo_track_work);
6195 wiphy_delayed_work_init(&rtwdev->mcc_prepare_done_work, rtw89_mcc_prepare_done_work);
6196 wiphy_delayed_work_init(&rtwdev->tx_wait_work, rtw89_tx_wait_work);
6197 INIT_DELAYED_WORK(&rtwdev->forbid_ba_work, rtw89_forbid_ba_work);
6198 wiphy_delayed_work_init(&rtwdev->antdiv_work, rtw89_phy_antdiv_work);
6199 rtwdev->txq_wq = alloc_workqueue("rtw89_tx_wq", WQ_UNBOUND | WQ_HIGHPRI, 0);
6200 if (!rtwdev->txq_wq)
6201 return -ENOMEM;
6202 spin_lock_init(&rtwdev->ba_lock);
6203 spin_lock_init(&rtwdev->rpwm_lock);
6204 mutex_init(&rtwdev->rf_mutex);
6205 rtwdev->total_sta_assoc = 0;
6206
6207 rtw89_init_wait(&rtwdev->mcc.wait);
6208 rtw89_init_wait(&rtwdev->mlo.wait);
6209 rtw89_init_wait(&rtwdev->mac.fw_ofld_wait);
6210 rtw89_init_wait(&rtwdev->wow.wait);
6211 rtw89_init_wait(&rtwdev->mac.ps_wait);
6212
6213 wiphy_work_init(&rtwdev->c2h_work, rtw89_fw_c2h_work);
6214 wiphy_work_init(&rtwdev->ips_work, rtw89_ips_work);
6215 wiphy_work_init(&rtwdev->cancel_6ghz_probe_work, rtw89_cancel_6ghz_probe_work);
6216 INIT_WORK(&rtwdev->load_firmware_work, rtw89_load_firmware_work);
6217
6218 spin_lock_init(&rtwdev->tx_rpt.skb_lock);
6219 skb_queue_head_init(&rtwdev->c2h_queue);
6220 rtw89_core_ppdu_sts_init(rtwdev);
6221 rtw89_traffic_stats_init(rtwdev, &rtwdev->stats);
6222
6223 rtwdev->hal.rx_fltr = DEFAULT_AX_RX_FLTR;
6224 rtwdev->dbcc_en = false;
6225 rtwdev->mlo_dbcc_mode = MLO_DBCC_NOT_SUPPORT;
6226 rtwdev->mac.qta_mode = RTW89_QTA_SCC;
6227
6228 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE) {
6229 rtwdev->dbcc_en = true;
6230 rtwdev->mac.qta_mode = RTW89_QTA_DBCC;
6231 rtwdev->mlo_dbcc_mode = MLO_1_PLUS_1_1RF;
6232 }
6233
6234 rtwdev->bbs[RTW89_PHY_0].phy_idx = RTW89_PHY_0;
6235 rtwdev->bbs[RTW89_PHY_1].phy_idx = RTW89_PHY_1;
6236
6237 wiphy_work_init(&btc->eapol_notify_work, rtw89_btc_ntfy_eapol_packet_work);
6238 wiphy_work_init(&btc->arp_notify_work, rtw89_btc_ntfy_arp_packet_work);
6239 wiphy_work_init(&btc->dhcp_notify_work, rtw89_btc_ntfy_dhcp_packet_work);
6240 wiphy_work_init(&btc->icmp_notify_work, rtw89_btc_ntfy_icmp_packet_work);
6241
6242 init_completion(&rtwdev->fw.req.completion);
6243 init_completion(&rtwdev->rfk_wait.completion);
6244
6245 schedule_work(&rtwdev->load_firmware_work);
6246
6247 rtw89_ser_init(rtwdev);
6248 rtw89_entity_init(rtwdev);
6249 rtw89_sar_init(rtwdev);
6250 rtw89_phy_ant_gain_init(rtwdev);
6251
6252 return 0;
6253 }
6254 EXPORT_SYMBOL(rtw89_core_init);
6255
rtw89_core_deinit(struct rtw89_dev * rtwdev)6256 void rtw89_core_deinit(struct rtw89_dev *rtwdev)
6257 {
6258 rtw89_ser_deinit(rtwdev);
6259 rtw89_unload_firmware(rtwdev);
6260 __rtw89_fw_free_all_early_h2c(rtwdev);
6261
6262 destroy_workqueue(rtwdev->txq_wq);
6263 mutex_destroy(&rtwdev->rf_mutex);
6264 }
6265 EXPORT_SYMBOL(rtw89_core_deinit);
6266
rtw89_core_scan_start(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link,const u8 * mac_addr,bool hw_scan)6267 void rtw89_core_scan_start(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link,
6268 const u8 *mac_addr, bool hw_scan)
6269 {
6270 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev,
6271 rtwvif_link->chanctx_idx);
6272 struct rtw89_bb_ctx *bb = rtw89_get_bb_ctx(rtwdev, rtwvif_link->phy_idx);
6273
6274 rtwdev->scanning = true;
6275
6276 ether_addr_copy(rtwvif_link->mac_addr, mac_addr);
6277 rtw89_btc_ntfy_scan_start(rtwdev, rtwvif_link->phy_idx, chan->band_type);
6278 rtw89_chip_rfk_scan(rtwdev, rtwvif_link, true);
6279 rtw89_hci_recalc_int_mit(rtwdev);
6280 rtw89_phy_config_edcca(rtwdev, bb, true);
6281 rtw89_tas_scan(rtwdev, true);
6282
6283 rtw89_fw_h2c_cam(rtwdev, rtwvif_link, NULL, mac_addr,
6284 RTW89_ROLE_INFO_CHANGE);
6285 }
6286
rtw89_core_scan_complete(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link,bool hw_scan)6287 void rtw89_core_scan_complete(struct rtw89_dev *rtwdev,
6288 struct rtw89_vif_link *rtwvif_link, bool hw_scan)
6289 {
6290 struct ieee80211_bss_conf *bss_conf;
6291 struct rtw89_bb_ctx *bb;
6292 int ret;
6293
6294 if (!rtwvif_link)
6295 return;
6296
6297 rcu_read_lock();
6298
6299 bss_conf = rtw89_vif_rcu_dereference_link(rtwvif_link, true);
6300 ether_addr_copy(rtwvif_link->mac_addr, bss_conf->addr);
6301
6302 rcu_read_unlock();
6303
6304 rtw89_fw_h2c_cam(rtwdev, rtwvif_link, NULL, NULL,
6305 RTW89_ROLE_INFO_CHANGE);
6306
6307 rtw89_chip_rfk_scan(rtwdev, rtwvif_link, false);
6308 rtw89_btc_ntfy_scan_finish(rtwdev, rtwvif_link->phy_idx);
6309 bb = rtw89_get_bb_ctx(rtwdev, rtwvif_link->phy_idx);
6310 rtw89_phy_config_edcca(rtwdev, bb, false);
6311 rtw89_tas_scan(rtwdev, false);
6312
6313 if (hw_scan) {
6314 ret = rtw89_core_send_nullfunc(rtwdev, rtwvif_link, false, false,
6315 RTW89_SCAN_NULL_TIMEOUT);
6316 if (ret)
6317 rtw89_debug(rtwdev, RTW89_DBG_TXRX,
6318 "scan send null-0 failed: %d\n", ret);
6319 }
6320
6321 rtwdev->scanning = false;
6322 rtw89_for_each_active_bb(rtwdev, bb)
6323 bb->dig.bypass_dig = true;
6324 if (hw_scan && (rtwdev->hw->conf.flags & IEEE80211_CONF_IDLE))
6325 wiphy_work_queue(rtwdev->hw->wiphy, &rtwdev->ips_work);
6326 }
6327
rtw89_read_chip_ver(struct rtw89_dev * rtwdev)6328 static void rtw89_read_chip_ver(struct rtw89_dev *rtwdev)
6329 {
6330 const struct rtw89_chip_info *chip = rtwdev->chip;
6331 struct rtw89_hal *hal = &rtwdev->hal;
6332 int ret;
6333 u8 val2;
6334 u8 val;
6335 u8 cv;
6336
6337 cv = rtw89_read32_mask(rtwdev, R_AX_SYS_CFG1, B_AX_CHIP_VER_MASK);
6338 if (chip->chip_id == RTL8852A && cv <= CHIP_CBV) {
6339 if (rtw89_read32(rtwdev, R_AX_GPIO0_7_FUNC_SEL) == RTW89_R32_DEAD)
6340 cv = CHIP_CAV;
6341 else
6342 cv = CHIP_CBV;
6343 }
6344
6345 hal->cv = cv;
6346
6347 if (rtw89_is_rtl885xb(rtwdev) || chip->chip_gen >= RTW89_CHIP_BE) {
6348 ret = rtw89_mac_read_xtal_si(rtwdev, XTAL_SI_CV, &val);
6349 if (ret)
6350 return;
6351
6352 hal->acv = u8_get_bits(val, XTAL_SI_ACV_MASK);
6353 }
6354
6355 if (chip->chip_gen >= RTW89_CHIP_BE) {
6356 hal->cid =
6357 rtw89_read32_mask(rtwdev, R_BE_SYS_CHIPINFO, B_BE_HW_ID_MASK);
6358
6359 ret = rtw89_mac_read_xtal_si(rtwdev, XTAL_SI_CHIP_ID_L, &val);
6360 if (ret)
6361 return;
6362 ret = rtw89_mac_read_xtal_si(rtwdev, XTAL_SI_CHIP_ID_H, &val2);
6363 if (ret)
6364 return;
6365
6366 hal->aid = val | val2 << 8;
6367 }
6368 }
6369
rtw89_core_setup_phycap(struct rtw89_dev * rtwdev)6370 static void rtw89_core_setup_phycap(struct rtw89_dev *rtwdev)
6371 {
6372 const struct rtw89_chip_info *chip = rtwdev->chip;
6373
6374 rtwdev->hal.support_cckpd =
6375 !(rtwdev->chip->chip_id == RTL8852A && rtwdev->hal.cv <= CHIP_CBV) &&
6376 !(rtwdev->chip->chip_id == RTL8852B && rtwdev->hal.cv <= CHIP_CAV);
6377 rtwdev->hal.support_igi =
6378 rtwdev->chip->chip_id == RTL8852A && rtwdev->hal.cv <= CHIP_CBV;
6379
6380 if (test_bit(RTW89_QUIRK_THERMAL_PROT_120C, rtwdev->quirks))
6381 rtwdev->hal.thermal_prot_th = chip->thermal_th[1];
6382 else if (test_bit(RTW89_QUIRK_THERMAL_PROT_110C, rtwdev->quirks))
6383 rtwdev->hal.thermal_prot_th = chip->thermal_th[0];
6384 else
6385 rtwdev->hal.thermal_prot_th = 0;
6386 }
6387
rtw89_core_setup_rfe_parms(struct rtw89_dev * rtwdev)6388 static void rtw89_core_setup_rfe_parms(struct rtw89_dev *rtwdev)
6389 {
6390 const struct rtw89_chip_info *chip = rtwdev->chip;
6391 const struct rtw89_rfe_parms_conf *conf = chip->rfe_parms_conf;
6392 struct rtw89_efuse *efuse = &rtwdev->efuse;
6393 const struct rtw89_rfe_parms *sel;
6394 u8 rfe_type = efuse->rfe_type;
6395
6396 if (!conf) {
6397 sel = chip->dflt_parms;
6398 goto out;
6399 }
6400
6401 while (conf->rfe_parms) {
6402 if (rfe_type == conf->rfe_type) {
6403 sel = conf->rfe_parms;
6404 goto out;
6405 }
6406 conf++;
6407 }
6408
6409 sel = chip->dflt_parms;
6410
6411 out:
6412 rtwdev->rfe_parms = rtw89_load_rfe_data_from_fw(rtwdev, sel);
6413 rtw89_load_txpwr_table(rtwdev, rtwdev->rfe_parms->byr_tbl);
6414 }
6415
rtw89_core_mlsr_switch(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif,unsigned int link_id)6416 int rtw89_core_mlsr_switch(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
6417 unsigned int link_id)
6418 {
6419 struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif);
6420 u16 usable_links = ieee80211_vif_usable_links(vif);
6421 u16 active_links = vif->active_links;
6422 struct rtw89_vif_link *target;
6423 int ret;
6424
6425 lockdep_assert_wiphy(rtwdev->hw->wiphy);
6426
6427 if (unlikely(!ieee80211_vif_is_mld(vif)))
6428 return -EOPNOTSUPP;
6429
6430 if (unlikely(link_id >= IEEE80211_MLD_MAX_NUM_LINKS ||
6431 !(usable_links & BIT(link_id)))) {
6432 rtw89_warn(rtwdev, "%s: link id %u is not usable\n", __func__,
6433 link_id);
6434 return -ENOLINK;
6435 }
6436
6437 if (active_links == BIT(link_id))
6438 return 0;
6439
6440 rtw89_debug(rtwdev, RTW89_DBG_STATE, "%s: switch to link id %u MLSR\n",
6441 __func__, link_id);
6442
6443 rtw89_leave_lps(rtwdev);
6444
6445 ieee80211_stop_queues(rtwdev->hw);
6446 flush_work(&rtwdev->txq_work);
6447
6448 ret = ieee80211_set_active_links(vif, BIT(link_id));
6449 if (ret) {
6450 rtw89_err(rtwdev, "%s: failed to work on link id %u\n",
6451 __func__, link_id);
6452 goto wake_queue;
6453 }
6454
6455 target = rtwvif->links[link_id];
6456 if (unlikely(!target)) {
6457 rtw89_err(rtwdev, "%s: failed to confirm link id %u\n",
6458 __func__, link_id);
6459
6460 ieee80211_set_active_links(vif, active_links);
6461 ret = -EFAULT;
6462 goto wake_queue;
6463 }
6464
6465 if (RTW89_CHK_FW_FEATURE_GROUP(WITH_RFK_PRE_NOTIFY, &rtwdev->fw))
6466 rtw89_chip_rfk_channel(rtwdev, target);
6467
6468 rtwvif->mlo_mode = RTW89_MLO_MODE_MLSR;
6469
6470 wake_queue:
6471 ieee80211_wake_queues(rtwdev->hw);
6472
6473 return ret;
6474 }
6475
rtw89_chip_efuse_info_setup(struct rtw89_dev * rtwdev)6476 static int rtw89_chip_efuse_info_setup(struct rtw89_dev *rtwdev)
6477 {
6478 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
6479 int ret;
6480
6481 ret = rtw89_mac_partial_init(rtwdev, false);
6482 if (ret)
6483 return ret;
6484
6485 ret = mac->parse_efuse_map(rtwdev);
6486 if (ret)
6487 return ret;
6488
6489 ret = mac->parse_phycap_map(rtwdev);
6490 if (ret)
6491 return ret;
6492
6493 ret = rtw89_mac_setup_phycap(rtwdev);
6494 if (ret)
6495 return ret;
6496
6497 rtw89_core_setup_phycap(rtwdev);
6498
6499 rtw89_hci_mac_pre_deinit(rtwdev);
6500
6501 return 0;
6502 }
6503
rtw89_chip_board_info_setup(struct rtw89_dev * rtwdev)6504 static int rtw89_chip_board_info_setup(struct rtw89_dev *rtwdev)
6505 {
6506 rtw89_chip_fem_setup(rtwdev);
6507
6508 return 0;
6509 }
6510
rtw89_chip_has_rfkill(struct rtw89_dev * rtwdev)6511 static bool rtw89_chip_has_rfkill(struct rtw89_dev *rtwdev)
6512 {
6513 return !!rtwdev->chip->rfkill_init;
6514 }
6515
rtw89_core_rfkill_init(struct rtw89_dev * rtwdev)6516 static void rtw89_core_rfkill_init(struct rtw89_dev *rtwdev)
6517 {
6518 const struct rtw89_rfkill_regs *regs = rtwdev->chip->rfkill_init;
6519
6520 rtw89_write16_mask(rtwdev, regs->pinmux.addr,
6521 regs->pinmux.mask, regs->pinmux.data);
6522 rtw89_write16_mask(rtwdev, regs->mode.addr,
6523 regs->mode.mask, regs->mode.data);
6524 }
6525
rtw89_core_rfkill_get(struct rtw89_dev * rtwdev)6526 static bool rtw89_core_rfkill_get(struct rtw89_dev *rtwdev)
6527 {
6528 const struct rtw89_reg_def *reg = &rtwdev->chip->rfkill_get;
6529
6530 return !rtw89_read8_mask(rtwdev, reg->addr, reg->mask);
6531 }
6532
rtw89_rfkill_polling_init(struct rtw89_dev * rtwdev)6533 static void rtw89_rfkill_polling_init(struct rtw89_dev *rtwdev)
6534 {
6535 if (!rtw89_chip_has_rfkill(rtwdev))
6536 return;
6537
6538 rtw89_core_rfkill_init(rtwdev);
6539 rtw89_core_rfkill_poll(rtwdev, true);
6540 wiphy_rfkill_start_polling(rtwdev->hw->wiphy);
6541 }
6542
rtw89_rfkill_polling_deinit(struct rtw89_dev * rtwdev)6543 static void rtw89_rfkill_polling_deinit(struct rtw89_dev *rtwdev)
6544 {
6545 if (!rtw89_chip_has_rfkill(rtwdev))
6546 return;
6547
6548 wiphy_rfkill_stop_polling(rtwdev->hw->wiphy);
6549 }
6550
rtw89_core_rfkill_poll(struct rtw89_dev * rtwdev,bool force)6551 void rtw89_core_rfkill_poll(struct rtw89_dev *rtwdev, bool force)
6552 {
6553 bool prev, blocked;
6554
6555 if (!rtw89_chip_has_rfkill(rtwdev))
6556 return;
6557
6558 prev = test_bit(RTW89_FLAG_HW_RFKILL_STATE, rtwdev->flags);
6559 blocked = rtw89_core_rfkill_get(rtwdev);
6560
6561 if (!force && prev == blocked)
6562 return;
6563
6564 rtw89_info(rtwdev, "rfkill hardware state changed to %s\n",
6565 blocked ? "disable" : "enable");
6566
6567 if (blocked)
6568 set_bit(RTW89_FLAG_HW_RFKILL_STATE, rtwdev->flags);
6569 else
6570 clear_bit(RTW89_FLAG_HW_RFKILL_STATE, rtwdev->flags);
6571
6572 wiphy_rfkill_set_hw_state(rtwdev->hw->wiphy, blocked);
6573 }
6574
rtw89_chip_info_setup(struct rtw89_dev * rtwdev)6575 int rtw89_chip_info_setup(struct rtw89_dev *rtwdev)
6576 {
6577 struct rtw89_efuse *efuse = &rtwdev->efuse;
6578 struct rtw89_hal *hal = &rtwdev->hal;
6579 int ret;
6580
6581 rtw89_read_chip_ver(rtwdev);
6582
6583 ret = rtw89_mac_pwr_on(rtwdev);
6584 if (ret) {
6585 rtw89_err(rtwdev, "failed to power on\n");
6586 return ret;
6587 }
6588
6589 ret = rtw89_wait_firmware_completion(rtwdev);
6590 if (ret) {
6591 rtw89_err(rtwdev, "failed to wait firmware completion\n");
6592 goto out;
6593 }
6594
6595 ret = rtw89_fw_recognize(rtwdev);
6596 if (ret) {
6597 rtw89_err(rtwdev, "failed to recognize firmware\n");
6598 goto out;
6599 }
6600
6601 ret = rtw89_chip_efuse_info_setup(rtwdev);
6602 if (ret)
6603 goto out;
6604
6605 ret = rtw89_fw_recognize_elements(rtwdev);
6606 if (ret) {
6607 rtw89_err(rtwdev, "failed to recognize firmware elements\n");
6608 goto out;
6609 }
6610
6611 ret = rtw89_chip_board_info_setup(rtwdev);
6612 if (ret)
6613 goto out;
6614
6615 rtw89_core_setup_rfe_parms(rtwdev);
6616 rtwdev->ps_mode = rtw89_update_ps_mode(rtwdev);
6617
6618 rtw89_info(rtwdev, "chip info CID: %x, CV: %x, AID: %x, ACV: %x, RFE: %d\n",
6619 hal->cid, hal->cv, hal->aid, hal->acv, efuse->rfe_type);
6620
6621 out:
6622 rtw89_mac_pwr_off(rtwdev);
6623
6624 return ret;
6625 }
6626 EXPORT_SYMBOL(rtw89_chip_info_setup);
6627
rtw89_chip_cfg_txpwr_ul_tb_offset(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link)6628 void rtw89_chip_cfg_txpwr_ul_tb_offset(struct rtw89_dev *rtwdev,
6629 struct rtw89_vif_link *rtwvif_link)
6630 {
6631 struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link);
6632 const struct rtw89_chip_info *chip = rtwdev->chip;
6633 struct ieee80211_bss_conf *bss_conf;
6634
6635 rcu_read_lock();
6636
6637 bss_conf = rtw89_vif_rcu_dereference_link(rtwvif_link, false);
6638 if (!bss_conf->he_support || !vif->cfg.assoc) {
6639 rcu_read_unlock();
6640 return;
6641 }
6642
6643 rcu_read_unlock();
6644
6645 if (chip->ops->set_txpwr_ul_tb_offset)
6646 chip->ops->set_txpwr_ul_tb_offset(rtwdev, 0, rtwvif_link->mac_idx);
6647 }
6648
rtw89_core_register_hw(struct rtw89_dev * rtwdev)6649 static int rtw89_core_register_hw(struct rtw89_dev *rtwdev)
6650 {
6651 const struct rtw89_chip_info *chip = rtwdev->chip;
6652 u8 n = rtwdev->support_mlo ? chip->support_link_num : 1;
6653 struct ieee80211_hw *hw = rtwdev->hw;
6654 struct rtw89_efuse *efuse = &rtwdev->efuse;
6655 struct rtw89_hal *hal = &rtwdev->hal;
6656 int ret;
6657 int tx_headroom = IEEE80211_HT_CTL_LEN;
6658
6659 if (rtwdev->hci.type == RTW89_HCI_TYPE_USB)
6660 tx_headroom += chip->txwd_body_size + chip->txwd_info_size;
6661
6662 hw->vif_data_size = struct_size_t(struct rtw89_vif, links_inst, n);
6663 hw->sta_data_size = struct_size_t(struct rtw89_sta, links_inst, n);
6664 hw->txq_data_size = sizeof(struct rtw89_txq);
6665 hw->chanctx_data_size = sizeof(struct rtw89_chanctx_cfg);
6666
6667 SET_IEEE80211_PERM_ADDR(hw, efuse->addr);
6668
6669 hw->extra_tx_headroom = tx_headroom;
6670 hw->queues = IEEE80211_NUM_ACS;
6671 hw->max_rx_aggregation_subframes = chip->max_rx_agg_num;
6672 hw->max_tx_aggregation_subframes = chip->max_tx_agg_num;
6673 hw->uapsd_max_sp_len = IEEE80211_WMM_IE_STA_QOSINFO_SP_ALL;
6674
6675 hw->radiotap_mcs_details |= IEEE80211_RADIOTAP_MCS_HAVE_FEC |
6676 IEEE80211_RADIOTAP_MCS_HAVE_STBC;
6677 hw->radiotap_vht_details |= IEEE80211_RADIOTAP_VHT_KNOWN_STBC;
6678
6679 ieee80211_hw_set(hw, SIGNAL_DBM);
6680 ieee80211_hw_set(hw, HAS_RATE_CONTROL);
6681 ieee80211_hw_set(hw, MFP_CAPABLE);
6682 ieee80211_hw_set(hw, REPORTS_TX_ACK_STATUS);
6683 ieee80211_hw_set(hw, AMPDU_AGGREGATION);
6684 ieee80211_hw_set(hw, RX_INCLUDES_FCS);
6685 ieee80211_hw_set(hw, TX_AMSDU);
6686 ieee80211_hw_set(hw, SUPPORT_FAST_XMIT);
6687 ieee80211_hw_set(hw, SUPPORTS_AMSDU_IN_AMPDU);
6688 ieee80211_hw_set(hw, SUPPORTS_PS);
6689 ieee80211_hw_set(hw, SUPPORTS_DYNAMIC_PS);
6690 ieee80211_hw_set(hw, SINGLE_SCAN_ON_ALL_BANDS);
6691 ieee80211_hw_set(hw, SUPPORTS_MULTI_BSSID);
6692 ieee80211_hw_set(hw, WANT_MONITOR_VIF);
6693 ieee80211_hw_set(hw, CHANCTX_STA_CSA);
6694
6695 if (chip->support_bandwidths & BIT(NL80211_CHAN_WIDTH_160))
6696 ieee80211_hw_set(hw, SUPPORTS_VHT_EXT_NSS_BW);
6697
6698 if (RTW89_CHK_FW_FEATURE(BEACON_FILTER, &rtwdev->fw))
6699 ieee80211_hw_set(hw, CONNECTION_MONITOR);
6700
6701 if (RTW89_CHK_FW_FEATURE(NOTIFY_AP_INFO, &rtwdev->fw))
6702 ieee80211_hw_set(hw, AP_LINK_PS);
6703
6704 hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION) |
6705 BIT(NL80211_IFTYPE_AP) |
6706 BIT(NL80211_IFTYPE_P2P_CLIENT) |
6707 BIT(NL80211_IFTYPE_P2P_GO);
6708
6709 if (hal->ant_diversity) {
6710 hw->wiphy->available_antennas_tx = 0x3;
6711 hw->wiphy->available_antennas_rx = 0x3;
6712 } else {
6713 hw->wiphy->available_antennas_tx = BIT(rtwdev->chip->rf_path_num) - 1;
6714 hw->wiphy->available_antennas_rx = BIT(rtwdev->chip->rf_path_num) - 1;
6715 }
6716
6717 hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_TDLS |
6718 WIPHY_FLAG_TDLS_EXTERNAL_SETUP |
6719 WIPHY_FLAG_AP_UAPSD |
6720 WIPHY_FLAG_HAS_CHANNEL_SWITCH |
6721 WIPHY_FLAG_SUPPORTS_EXT_KEK_KCK;
6722
6723 if (!chip->support_rnr)
6724 hw->wiphy->flags |= WIPHY_FLAG_SPLIT_SCAN_6GHZ;
6725
6726 if (chip->chip_gen == RTW89_CHIP_BE)
6727 hw->wiphy->flags |= WIPHY_FLAG_DISABLE_WEXT;
6728
6729 if (rtwdev->support_mlo) {
6730 hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_MLO;
6731 hw->wiphy->iftype_ext_capab = rtw89_iftypes_ext_capa;
6732 hw->wiphy->num_iftype_ext_capab = ARRAY_SIZE(rtw89_iftypes_ext_capa);
6733 }
6734
6735 hw->wiphy->features |= NL80211_FEATURE_SCAN_RANDOM_MAC_ADDR;
6736
6737 hw->wiphy->max_scan_ssids = RTW89_SCANOFLD_MAX_SSID;
6738 hw->wiphy->max_scan_ie_len = RTW89_SCANOFLD_MAX_IE_LEN;
6739
6740 #ifdef CONFIG_PM
6741 hw->wiphy->wowlan = rtwdev->chip->wowlan_stub;
6742 hw->wiphy->max_sched_scan_ssids = RTW89_SCANOFLD_MAX_SSID;
6743 #endif
6744
6745 hw->wiphy->tid_config_support.vif |= BIT(NL80211_TID_CONFIG_ATTR_AMPDU_CTRL);
6746 hw->wiphy->tid_config_support.peer |= BIT(NL80211_TID_CONFIG_ATTR_AMPDU_CTRL);
6747 hw->wiphy->tid_config_support.vif |= BIT(NL80211_TID_CONFIG_ATTR_AMSDU_CTRL);
6748 hw->wiphy->tid_config_support.peer |= BIT(NL80211_TID_CONFIG_ATTR_AMSDU_CTRL);
6749 hw->wiphy->max_remain_on_channel_duration = 1000;
6750
6751 wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_CAN_REPLACE_PTK0);
6752 wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_SCAN_RANDOM_SN);
6753 wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_SET_SCAN_DWELL);
6754
6755 ret = rtw89_core_set_supported_band(rtwdev);
6756 if (ret) {
6757 rtw89_err(rtwdev, "failed to set supported band\n");
6758 return ret;
6759 }
6760
6761 ret = rtw89_regd_setup(rtwdev);
6762 if (ret) {
6763 rtw89_err(rtwdev, "failed to set up regd\n");
6764 return ret;
6765 }
6766
6767 hw->wiphy->sar_capa = &rtw89_sar_capa;
6768
6769 ret = ieee80211_register_hw(hw);
6770 if (ret) {
6771 rtw89_err(rtwdev, "failed to register hw\n");
6772 return ret;
6773 }
6774
6775 ret = rtw89_regd_init_hint(rtwdev);
6776 if (ret) {
6777 rtw89_err(rtwdev, "failed to init regd\n");
6778 goto err_unregister_hw;
6779 }
6780
6781 rtw89_rfkill_polling_init(rtwdev);
6782
6783 return 0;
6784
6785 err_unregister_hw:
6786 ieee80211_unregister_hw(hw);
6787
6788 return ret;
6789 }
6790
rtw89_core_unregister_hw(struct rtw89_dev * rtwdev)6791 static void rtw89_core_unregister_hw(struct rtw89_dev *rtwdev)
6792 {
6793 struct ieee80211_hw *hw = rtwdev->hw;
6794
6795 rtw89_rfkill_polling_deinit(rtwdev);
6796 ieee80211_unregister_hw(hw);
6797 }
6798
rtw89_core_register(struct rtw89_dev * rtwdev)6799 int rtw89_core_register(struct rtw89_dev *rtwdev)
6800 {
6801 int ret;
6802
6803 ret = rtw89_core_register_hw(rtwdev);
6804 if (ret) {
6805 rtw89_err(rtwdev, "failed to register core hw\n");
6806 return ret;
6807 }
6808
6809 rtw89_phy_dm_init_data(rtwdev);
6810 rtw89_debugfs_init(rtwdev);
6811
6812 return 0;
6813 }
6814 EXPORT_SYMBOL(rtw89_core_register);
6815
rtw89_core_unregister(struct rtw89_dev * rtwdev)6816 void rtw89_core_unregister(struct rtw89_dev *rtwdev)
6817 {
6818 rtw89_core_unregister_hw(rtwdev);
6819
6820 rtw89_debugfs_deinit(rtwdev);
6821 }
6822 EXPORT_SYMBOL(rtw89_core_unregister);
6823
rtw89_alloc_ieee80211_hw(struct device * device,u32 bus_data_size,const struct rtw89_chip_info * chip,const struct rtw89_chip_variant * variant)6824 struct rtw89_dev *rtw89_alloc_ieee80211_hw(struct device *device,
6825 u32 bus_data_size,
6826 const struct rtw89_chip_info *chip,
6827 const struct rtw89_chip_variant *variant)
6828 {
6829 struct rtw89_fw_info early_fw = {};
6830 const struct firmware *firmware;
6831 struct ieee80211_hw *hw;
6832 struct rtw89_dev *rtwdev;
6833 struct ieee80211_ops *ops;
6834 u32 driver_data_size;
6835 int fw_format = -1;
6836 bool support_mlo;
6837 bool no_chanctx;
6838
6839 firmware = rtw89_early_fw_feature_recognize(device, chip, &early_fw, &fw_format);
6840
6841 ops = kmemdup(&rtw89_ops, sizeof(rtw89_ops), GFP_KERNEL);
6842 if (!ops)
6843 goto err;
6844
6845 no_chanctx = chip->support_chanctx_num == 0 ||
6846 !RTW89_CHK_FW_FEATURE(SCAN_OFFLOAD, &early_fw) ||
6847 !RTW89_CHK_FW_FEATURE(BEACON_FILTER, &early_fw);
6848
6849 if (no_chanctx) {
6850 ops->add_chanctx = ieee80211_emulate_add_chanctx;
6851 ops->remove_chanctx = ieee80211_emulate_remove_chanctx;
6852 ops->change_chanctx = ieee80211_emulate_change_chanctx;
6853 ops->switch_vif_chanctx = ieee80211_emulate_switch_vif_chanctx;
6854 ops->assign_vif_chanctx = NULL;
6855 ops->unassign_vif_chanctx = NULL;
6856 ops->remain_on_channel = NULL;
6857 ops->cancel_remain_on_channel = NULL;
6858 }
6859
6860 if (!chip->support_noise)
6861 ops->get_survey = NULL;
6862
6863 driver_data_size = sizeof(struct rtw89_dev) + bus_data_size;
6864 hw = ieee80211_alloc_hw(driver_data_size, ops);
6865 if (!hw)
6866 goto err;
6867
6868 /* Currently, our AP_LINK_PS handling only works for non-MLD softap
6869 * or MLD-single-link softap. If RTW89_MLD_NON_STA_LINK_NUM enlarges,
6870 * please tweak entire AP_LINKS_PS handling before supporting MLO.
6871 */
6872 support_mlo = !no_chanctx && chip->support_link_num &&
6873 RTW89_CHK_FW_FEATURE(NOTIFY_AP_INFO, &early_fw) &&
6874 RTW89_MLD_NON_STA_LINK_NUM == 1;
6875
6876 hw->wiphy->iface_combinations = rtw89_iface_combs;
6877
6878 if (no_chanctx || chip->support_chanctx_num == 1)
6879 hw->wiphy->n_iface_combinations = 1;
6880 else
6881 hw->wiphy->n_iface_combinations = ARRAY_SIZE(rtw89_iface_combs);
6882
6883 rtwdev = hw->priv;
6884 rtwdev->hw = hw;
6885 rtwdev->dev = device;
6886 rtwdev->ops = ops;
6887 rtwdev->chip = chip;
6888 rtwdev->variant = variant;
6889 rtwdev->fw.req.firmware = firmware;
6890 rtwdev->fw.fw_format = fw_format;
6891 rtwdev->support_mlo = support_mlo;
6892
6893 rtw89_debug(rtwdev, RTW89_DBG_CHAN, "probe driver %s chanctx\n",
6894 no_chanctx ? "without" : "with");
6895 rtw89_debug(rtwdev, RTW89_DBG_CHAN, "probe driver %s MLO cap\n",
6896 support_mlo ? "with" : "without");
6897
6898 return rtwdev;
6899
6900 err:
6901 kfree(ops);
6902 release_firmware(firmware);
6903 return NULL;
6904 }
6905 EXPORT_SYMBOL(rtw89_alloc_ieee80211_hw);
6906
rtw89_free_ieee80211_hw(struct rtw89_dev * rtwdev)6907 void rtw89_free_ieee80211_hw(struct rtw89_dev *rtwdev)
6908 {
6909 kfree(rtwdev->ops);
6910 kfree(rtwdev->rfe_data);
6911 release_firmware(rtwdev->fw.req.firmware);
6912 ieee80211_free_hw(rtwdev->hw);
6913 }
6914 EXPORT_SYMBOL(rtw89_free_ieee80211_hw);
6915
6916 MODULE_AUTHOR("Realtek Corporation");
6917 MODULE_DESCRIPTION("Realtek 802.11ax wireless core module");
6918 MODULE_LICENSE("Dual BSD/GPL");
6919 #if defined(__FreeBSD__)
6920 MODULE_VERSION(rtw89, 1);
6921 MODULE_DEPEND(rtw89, linuxkpi, 1, 1, 1);
6922 MODULE_DEPEND(rtw89, linuxkpi_wlan, 1, 1, 1);
6923 #endif
6924