1 /*-
2 * Copyright (c) 2015-2021 Mellanox Technologies. All rights reserved.
3 * Copyright (c) 2022 NVIDIA corporation & affiliates.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 */
26
27 #include "opt_ipsec.h"
28 #include "opt_kern_tls.h"
29 #include "opt_rss.h"
30 #include "opt_ratelimit.h"
31
32 #include <dev/mlx5/mlx5_en/en.h>
33 #include <dev/mlx5/mlx5_accel/ipsec.h>
34
35 #include <sys/eventhandler.h>
36 #include <sys/sockio.h>
37 #include <machine/atomic.h>
38
39 #include <net/debugnet.h>
40 #include <netinet/tcp_ratelimit.h>
41 #include <netipsec/keydb.h>
42 #include <netipsec/ipsec_offload.h>
43
44 static int mlx5e_get_wqe_sz(struct mlx5e_priv *priv, u32 *wqe_sz, u32 *nsegs);
45 static if_snd_tag_query_t mlx5e_ul_snd_tag_query;
46 static if_snd_tag_free_t mlx5e_ul_snd_tag_free;
47
48 struct mlx5e_channel_param {
49 struct mlx5e_rq_param rq;
50 struct mlx5e_sq_param sq;
51 struct mlx5e_cq_param rx_cq;
52 struct mlx5e_cq_param tx_cq;
53 };
54
55 struct media {
56 u32 subtype;
57 u64 baudrate;
58 };
59
60 static const struct media mlx5e_mode_table[MLX5E_LINK_SPEEDS_NUMBER] =
61 {
62 [MLX5E_1000BASE_CX_SGMII] = {
63 .subtype = IFM_1000_CX_SGMII,
64 .baudrate = IF_Mbps(1000ULL),
65 },
66 [MLX5E_1000BASE_KX] = {
67 .subtype = IFM_1000_KX,
68 .baudrate = IF_Mbps(1000ULL),
69 },
70 [MLX5E_10GBASE_CX4] = {
71 .subtype = IFM_10G_CX4,
72 .baudrate = IF_Gbps(10ULL),
73 },
74 [MLX5E_10GBASE_KX4] = {
75 .subtype = IFM_10G_KX4,
76 .baudrate = IF_Gbps(10ULL),
77 },
78 [MLX5E_10GBASE_KR] = {
79 .subtype = IFM_10G_KR,
80 .baudrate = IF_Gbps(10ULL),
81 },
82 [MLX5E_20GBASE_KR2] = {
83 .subtype = IFM_20G_KR2,
84 .baudrate = IF_Gbps(20ULL),
85 },
86 [MLX5E_40GBASE_CR4] = {
87 .subtype = IFM_40G_CR4,
88 .baudrate = IF_Gbps(40ULL),
89 },
90 [MLX5E_40GBASE_KR4] = {
91 .subtype = IFM_40G_KR4,
92 .baudrate = IF_Gbps(40ULL),
93 },
94 [MLX5E_56GBASE_R4] = {
95 .subtype = IFM_56G_R4,
96 .baudrate = IF_Gbps(56ULL),
97 },
98 [MLX5E_10GBASE_CR] = {
99 .subtype = IFM_10G_CR1,
100 .baudrate = IF_Gbps(10ULL),
101 },
102 [MLX5E_10GBASE_SR] = {
103 .subtype = IFM_10G_SR,
104 .baudrate = IF_Gbps(10ULL),
105 },
106 [MLX5E_10GBASE_ER_LR] = {
107 .subtype = IFM_10G_ER,
108 .baudrate = IF_Gbps(10ULL),
109 },
110 [MLX5E_40GBASE_SR4] = {
111 .subtype = IFM_40G_SR4,
112 .baudrate = IF_Gbps(40ULL),
113 },
114 [MLX5E_40GBASE_LR4_ER4] = {
115 .subtype = IFM_40G_LR4,
116 .baudrate = IF_Gbps(40ULL),
117 },
118 [MLX5E_100GBASE_CR4] = {
119 .subtype = IFM_100G_CR4,
120 .baudrate = IF_Gbps(100ULL),
121 },
122 [MLX5E_100GBASE_SR4] = {
123 .subtype = IFM_100G_SR4,
124 .baudrate = IF_Gbps(100ULL),
125 },
126 [MLX5E_100GBASE_KR4] = {
127 .subtype = IFM_100G_KR4,
128 .baudrate = IF_Gbps(100ULL),
129 },
130 [MLX5E_100GBASE_LR4] = {
131 .subtype = IFM_100G_LR4,
132 .baudrate = IF_Gbps(100ULL),
133 },
134 [MLX5E_100BASE_TX] = {
135 .subtype = IFM_100_TX,
136 .baudrate = IF_Mbps(100ULL),
137 },
138 [MLX5E_1000BASE_T] = {
139 .subtype = IFM_1000_T,
140 .baudrate = IF_Mbps(1000ULL),
141 },
142 [MLX5E_10GBASE_T] = {
143 .subtype = IFM_10G_T,
144 .baudrate = IF_Gbps(10ULL),
145 },
146 [MLX5E_25GBASE_CR] = {
147 .subtype = IFM_25G_CR,
148 .baudrate = IF_Gbps(25ULL),
149 },
150 [MLX5E_25GBASE_KR] = {
151 .subtype = IFM_25G_KR,
152 .baudrate = IF_Gbps(25ULL),
153 },
154 [MLX5E_25GBASE_SR] = {
155 .subtype = IFM_25G_SR,
156 .baudrate = IF_Gbps(25ULL),
157 },
158 [MLX5E_50GBASE_CR2] = {
159 .subtype = IFM_50G_CR2,
160 .baudrate = IF_Gbps(50ULL),
161 },
162 [MLX5E_50GBASE_KR2] = {
163 .subtype = IFM_50G_KR2,
164 .baudrate = IF_Gbps(50ULL),
165 },
166 [MLX5E_50GBASE_KR4] = {
167 .subtype = IFM_50G_KR4,
168 .baudrate = IF_Gbps(50ULL),
169 },
170 };
171
172 static const struct media mlx5e_ext_mode_table[MLX5E_EXT_LINK_SPEEDS_NUMBER][MLX5E_CONNECTOR_TYPE_NUMBER] =
173 {
174 /**/
175 [MLX5E_SGMII_100M][MLX5E_PORT_UNKNOWN] = {
176 .subtype = IFM_100_SGMII,
177 .baudrate = IF_Mbps(100),
178 },
179
180 /**/
181 [MLX5E_1000BASE_X_SGMII][MLX5E_PORT_UNKNOWN] = {
182 .subtype = IFM_1000_CX,
183 .baudrate = IF_Mbps(1000),
184 },
185 [MLX5E_1000BASE_X_SGMII][MLX5E_PORT_FIBRE] = {
186 .subtype = IFM_1000_SX,
187 .baudrate = IF_Mbps(1000),
188 },
189
190 /**/
191 [MLX5E_5GBASE_R][MLX5E_PORT_UNKNOWN] = {
192 .subtype = IFM_5000_KR,
193 .baudrate = IF_Mbps(5000),
194 },
195 [MLX5E_5GBASE_R][MLX5E_PORT_TP] = {
196 .subtype = IFM_5000_T,
197 .baudrate = IF_Mbps(5000),
198 },
199
200 /**/
201 [MLX5E_10GBASE_XFI_XAUI_1][MLX5E_PORT_UNKNOWN] = {
202 .subtype = IFM_10G_KR,
203 .baudrate = IF_Gbps(10ULL),
204 },
205 [MLX5E_10GBASE_XFI_XAUI_1][MLX5E_PORT_DA] = {
206 .subtype = IFM_10G_CR1,
207 .baudrate = IF_Gbps(10ULL),
208 },
209 [MLX5E_10GBASE_XFI_XAUI_1][MLX5E_PORT_FIBRE] = {
210 .subtype = IFM_10G_SR,
211 .baudrate = IF_Gbps(10ULL),
212 },
213
214 /**/
215 [MLX5E_40GBASE_XLAUI_4_XLPPI_4][MLX5E_PORT_UNKNOWN] = {
216 .subtype = IFM_40G_KR4,
217 .baudrate = IF_Gbps(40ULL),
218 },
219 [MLX5E_40GBASE_XLAUI_4_XLPPI_4][MLX5E_PORT_DA] = {
220 .subtype = IFM_40G_CR4,
221 .baudrate = IF_Gbps(40ULL),
222 },
223 [MLX5E_40GBASE_XLAUI_4_XLPPI_4][MLX5E_PORT_FIBRE] = {
224 .subtype = IFM_40G_SR4,
225 .baudrate = IF_Gbps(40ULL),
226 },
227
228 /**/
229 [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_PORT_UNKNOWN] = {
230 .subtype = IFM_25G_KR,
231 .baudrate = IF_Gbps(25ULL),
232 },
233 [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_PORT_DA] = {
234 .subtype = IFM_25G_CR,
235 .baudrate = IF_Gbps(25ULL),
236 },
237 [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_PORT_FIBRE] = {
238 .subtype = IFM_25G_SR,
239 .baudrate = IF_Gbps(25ULL),
240 },
241 [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_PORT_TP] = {
242 .subtype = IFM_25G_T,
243 .baudrate = IF_Gbps(25ULL),
244 },
245
246 /**/
247 [MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2][MLX5E_PORT_UNKNOWN] = {
248 .subtype = IFM_50G_KR2,
249 .baudrate = IF_Gbps(50ULL),
250 },
251 [MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2][MLX5E_PORT_DA] = {
252 .subtype = IFM_50G_CR2,
253 .baudrate = IF_Gbps(50ULL),
254 },
255 [MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2][MLX5E_PORT_FIBRE] = {
256 .subtype = IFM_50G_SR2,
257 .baudrate = IF_Gbps(50ULL),
258 },
259
260 /**/
261 [MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR][MLX5E_PORT_UNKNOWN] = {
262 .subtype = IFM_50G_KR_PAM4,
263 .baudrate = IF_Gbps(50ULL),
264 },
265 [MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR][MLX5E_PORT_DA] = {
266 .subtype = IFM_50G_CP,
267 .baudrate = IF_Gbps(50ULL),
268 },
269 [MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR][MLX5E_PORT_FIBRE] = {
270 .subtype = IFM_50G_SR,
271 .baudrate = IF_Gbps(50ULL),
272 },
273
274 /**/
275 [MLX5E_CAUI_4_100GBASE_CR4_KR4][MLX5E_PORT_UNKNOWN] = {
276 .subtype = IFM_100G_KR4,
277 .baudrate = IF_Gbps(100ULL),
278 },
279 [MLX5E_CAUI_4_100GBASE_CR4_KR4][MLX5E_PORT_DA] = {
280 .subtype = IFM_100G_CR4,
281 .baudrate = IF_Gbps(100ULL),
282 },
283 [MLX5E_CAUI_4_100GBASE_CR4_KR4][MLX5E_PORT_FIBRE] = {
284 .subtype = IFM_100G_SR4,
285 .baudrate = IF_Gbps(100ULL),
286 },
287
288 /**/
289 [MLX5E_100GAUI_1_100GBASE_CR_KR][MLX5E_PORT_UNKNOWN] = {
290 .subtype = IFM_100G_KR_PAM4,
291 .baudrate = IF_Gbps(100ULL),
292 },
293 [MLX5E_100GAUI_1_100GBASE_CR_KR][MLX5E_PORT_DA] = {
294 .subtype = IFM_100G_CR_PAM4,
295 .baudrate = IF_Gbps(100ULL),
296 },
297 [MLX5E_100GAUI_1_100GBASE_CR_KR][MLX5E_PORT_FIBRE] = {
298 .subtype = IFM_100G_SR2, /* XXX */
299 .baudrate = IF_Gbps(100ULL),
300 },
301
302 /**/
303 [MLX5E_100GAUI_2_100GBASE_CR2_KR2][MLX5E_PORT_UNKNOWN] = {
304 .subtype = IFM_100G_KR4,
305 .baudrate = IF_Gbps(100ULL),
306 },
307 [MLX5E_100GAUI_2_100GBASE_CR2_KR2][MLX5E_PORT_DA] = {
308 .subtype = IFM_100G_CP2,
309 .baudrate = IF_Gbps(100ULL),
310 },
311 [MLX5E_100GAUI_2_100GBASE_CR2_KR2][MLX5E_PORT_FIBRE] = {
312 .subtype = IFM_100G_SR2,
313 .baudrate = IF_Gbps(100ULL),
314 },
315
316 /**/
317 [MLX5E_200GAUI_2_200GBASE_CR2_KR2][MLX5E_PORT_UNKNOWN] = {
318 .subtype = IFM_200G_KR4_PAM4, /* XXX */
319 .baudrate = IF_Gbps(200ULL),
320 },
321 [MLX5E_200GAUI_2_200GBASE_CR2_KR2][MLX5E_PORT_DA] = {
322 .subtype = IFM_200G_CR4_PAM4, /* XXX */
323 .baudrate = IF_Gbps(200ULL),
324 },
325 [MLX5E_200GAUI_2_200GBASE_CR2_KR2][MLX5E_PORT_FIBRE] = {
326 .subtype = IFM_200G_SR4, /* XXX */
327 .baudrate = IF_Gbps(200ULL),
328 },
329
330 /**/
331 [MLX5E_200GAUI_4_200GBASE_CR4_KR4][MLX5E_PORT_UNKNOWN] = {
332 .subtype = IFM_200G_KR4_PAM4,
333 .baudrate = IF_Gbps(200ULL),
334 },
335 [MLX5E_200GAUI_4_200GBASE_CR4_KR4][MLX5E_PORT_DA] = {
336 .subtype = IFM_200G_CR4_PAM4,
337 .baudrate = IF_Gbps(200ULL),
338 },
339 [MLX5E_200GAUI_4_200GBASE_CR4_KR4][MLX5E_PORT_FIBRE] = {
340 .subtype = IFM_200G_SR4,
341 .baudrate = IF_Gbps(200ULL),
342 },
343
344 /**/
345 [MLX5E_400GAUI_8][MLX5E_PORT_UNKNOWN] = {
346 .subtype = IFM_400G_LR8, /* XXX */
347 .baudrate = IF_Gbps(400ULL),
348 },
349
350 /**/
351 [MLX5E_400GAUI_4_400GBASE_CR4_KR4][MLX5E_PORT_UNKNOWN] = {
352 .subtype = IFM_400G_LR8, /* XXX */
353 .baudrate = IF_Gbps(400ULL),
354 },
355
356 /**/
357 [MLX5E_400GAUI_2_400GBASE_CR2_KR2][MLX5E_PORT_UNKNOWN] = {
358 .subtype = IFM_400G_KR2_PAM4,
359 .baudrate = IF_Gbps(400ULL),
360 },
361 [MLX5E_400GAUI_2_400GBASE_CR2_KR2][MLX5E_PORT_DA] = {
362 .subtype = IFM_400G_CR2,
363 .baudrate = IF_Gbps(400ULL),
364 },
365 [MLX5E_400GAUI_2_400GBASE_CR2_KR2][MLX5E_PORT_FIBRE] = {
366 .subtype = IFM_400G_SR2,
367 .baudrate = IF_Gbps(400ULL),
368 },
369
370 /**/
371 [MLX5E_800GAUI_8_800GBASE_CR8_KR8][MLX5E_PORT_UNKNOWN] = {
372 .subtype = IFM_800G_KR8, /* 800GAUI-8 / KR8a */
373 .baudrate = IF_Gbps(800ULL),
374 },
375 [MLX5E_800GAUI_8_800GBASE_CR8_KR8][MLX5E_PORT_DA] = {
376 .subtype = IFM_800G_CR8, /* 800GBASE-CR8 */
377 .baudrate = IF_Gbps(800ULL),
378 },
379 [MLX5E_800GAUI_8_800GBASE_CR8_KR8][MLX5E_PORT_FIBRE] = {
380 .subtype = IFM_800G_SR8,
381 .baudrate = IF_Gbps(800ULL),
382 },
383
384 /**/
385 [MLX5E_800GAUI_4_800GBASE_CR4_KR4][MLX5E_PORT_UNKNOWN] = {
386 .subtype = IFM_800G_KR4_PAM4, /* 800GAUI-4 / KR4 */
387 .baudrate = IF_Gbps(800ULL),
388 },
389 [MLX5E_800GAUI_4_800GBASE_CR4_KR4][MLX5E_PORT_DA] = {
390 .subtype = IFM_800G_CR4, /* 800GBASE-CR4 */
391 .baudrate = IF_Gbps(800ULL),
392 },
393 [MLX5E_800GAUI_4_800GBASE_CR4_KR4][MLX5E_PORT_FIBRE] = {
394 .subtype = IFM_800G_SR4,
395 .baudrate = IF_Gbps(800ULL),
396 },
397 };
398
399 static const struct if_snd_tag_sw mlx5e_ul_snd_tag_sw = {
400 .snd_tag_query = mlx5e_ul_snd_tag_query,
401 .snd_tag_free = mlx5e_ul_snd_tag_free,
402 .type = IF_SND_TAG_TYPE_UNLIMITED
403 };
404
405 DEBUGNET_DEFINE(mlx5_en);
406
407 MALLOC_DEFINE(M_MLX5EN, "MLX5EN", "MLX5 Ethernet");
408
409 static void
mlx5e_update_carrier(struct mlx5e_priv * priv)410 mlx5e_update_carrier(struct mlx5e_priv *priv)
411 {
412 struct mlx5_core_dev *mdev = priv->mdev;
413 u32 out[MLX5_ST_SZ_DW(ptys_reg)];
414 u32 eth_proto_oper;
415 int error;
416 u8 i;
417 u8 connector_type;
418 u8 port_state;
419 u8 is_er_type;
420 bool ext;
421 struct media media_entry = {};
422
423 port_state = mlx5_query_vport_state(mdev,
424 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT, 0);
425
426 if (port_state == VPORT_STATE_UP) {
427 priv->media_status_last |= IFM_ACTIVE;
428 } else {
429 priv->media_status_last &= ~IFM_ACTIVE;
430 priv->media_active_last = IFM_ETHER;
431 if_link_state_change(priv->ifp, LINK_STATE_DOWN);
432 return;
433 }
434
435 error = mlx5_query_port_ptys(mdev, out, sizeof(out),
436 MLX5_PTYS_EN, 1);
437 if (error) {
438 priv->media_active_last = IFM_ETHER;
439 if_setbaudrate(priv->ifp, 1);
440 mlx5_en_err(priv->ifp, "query port ptys failed: 0x%x\n",
441 error);
442 return;
443 }
444
445 ext = MLX5_CAP_PCAM_FEATURE(mdev, ptys_extended_ethernet);
446 eth_proto_oper = MLX5_GET_ETH_PROTO(ptys_reg, out, ext,
447 eth_proto_oper);
448 if (eth_proto_oper == 0) {
449 priv->media_active_last = IFM_ETHER;
450 if_setbaudrate(priv->ifp, 1);
451 mlx5_en_err(priv->ifp, "eth_proto_oper is 0\n");
452 return;
453 }
454 connector_type = MLX5_GET(ptys_reg, out, connector_type);
455 if (connector_type >= MLX5E_CONNECTOR_TYPE_NUMBER)
456 connector_type = MLX5E_PORT_UNKNOWN;
457
458 i = ilog2(eth_proto_oper);
459
460 if (ext) {
461 media_entry = mlx5e_ext_mode_table[i][connector_type];
462 /* check if we should use fallback entry */
463 if (media_entry.subtype == 0)
464 media_entry = mlx5e_ext_mode_table[i][MLX5E_PORT_UNKNOWN];
465 } else {
466 media_entry = mlx5e_mode_table[i];
467 }
468
469 if (media_entry.subtype == 0) {
470 mlx5_en_err(priv->ifp,
471 "Could not find operational media subtype\n");
472 return;
473 }
474
475 switch (media_entry.subtype) {
476 case IFM_10G_ER:
477 error = mlx5_query_pddr_range_info(mdev, 1, &is_er_type);
478 if (error != 0) {
479 mlx5_en_err(priv->ifp,
480 "query port pddr failed: %d\n", error);
481 }
482 if (error != 0 || is_er_type == 0)
483 media_entry.subtype = IFM_10G_LR;
484 break;
485 case IFM_40G_LR4:
486 error = mlx5_query_pddr_range_info(mdev, 1, &is_er_type);
487 if (error != 0) {
488 mlx5_en_err(priv->ifp,
489 "query port pddr failed: %d\n", error);
490 }
491 if (error == 0 && is_er_type != 0)
492 media_entry.subtype = IFM_40G_ER4;
493 break;
494 }
495 priv->media_active_last = media_entry.subtype | IFM_ETHER | IFM_FDX;
496 if_setbaudrate(priv->ifp, media_entry.baudrate);
497
498 if_link_state_change(priv->ifp, LINK_STATE_UP);
499 }
500
501 static void
mlx5e_media_status(if_t dev,struct ifmediareq * ifmr)502 mlx5e_media_status(if_t dev, struct ifmediareq *ifmr)
503 {
504 struct mlx5e_priv *priv = if_getsoftc(dev);
505
506 ifmr->ifm_status = priv->media_status_last;
507 ifmr->ifm_current = ifmr->ifm_active = priv->media_active_last |
508 (priv->params.rx_pauseframe_control ? IFM_ETH_RXPAUSE : 0) |
509 (priv->params.tx_pauseframe_control ? IFM_ETH_TXPAUSE : 0);
510
511 }
512
513 static u32
mlx5e_find_link_mode(u32 subtype,bool ext)514 mlx5e_find_link_mode(u32 subtype, bool ext)
515 {
516 u32 link_mode = 0;
517
518 switch (subtype) {
519 case 0:
520 goto done;
521 case IFM_10G_LR:
522 subtype = IFM_10G_ER;
523 break;
524 case IFM_40G_ER4:
525 subtype = IFM_40G_LR4;
526 break;
527 default:
528 break;
529 }
530
531 if (ext) {
532 for (unsigned i = 0; i != MLX5E_EXT_LINK_SPEEDS_NUMBER; i++) {
533 for (unsigned j = 0; j != MLX5E_CABLE_TYPE_NUMBER; j++) {
534 if (mlx5e_ext_mode_table[i][j].subtype == subtype)
535 link_mode |= MLX5E_PROT_MASK(i);
536 }
537 }
538 } else {
539 for (unsigned i = 0; i != MLX5E_LINK_SPEEDS_NUMBER; i++) {
540 if (mlx5e_mode_table[i].subtype == subtype)
541 link_mode |= MLX5E_PROT_MASK(i);
542 }
543 }
544 done:
545 return (link_mode);
546 }
547
548 static int
mlx5e_set_port_pause_and_pfc(struct mlx5e_priv * priv)549 mlx5e_set_port_pause_and_pfc(struct mlx5e_priv *priv)
550 {
551 return (mlx5_set_port_pause_and_pfc(priv->mdev, 1,
552 priv->params.rx_pauseframe_control,
553 priv->params.tx_pauseframe_control,
554 priv->params.rx_priority_flow_control,
555 priv->params.tx_priority_flow_control));
556 }
557
558 static int
mlx5e_set_port_pfc(struct mlx5e_priv * priv)559 mlx5e_set_port_pfc(struct mlx5e_priv *priv)
560 {
561 int error;
562
563 if (priv->gone != 0) {
564 error = -ENXIO;
565 } else if (priv->params.rx_pauseframe_control ||
566 priv->params.tx_pauseframe_control) {
567 mlx5_en_err(priv->ifp,
568 "Global pauseframes must be disabled before enabling PFC.\n");
569 error = -EINVAL;
570 } else {
571 error = mlx5e_set_port_pause_and_pfc(priv);
572 }
573 return (error);
574 }
575
576 static int
mlx5e_media_change(if_t dev)577 mlx5e_media_change(if_t dev)
578 {
579 struct mlx5e_priv *priv = if_getsoftc(dev);
580 struct mlx5_core_dev *mdev = priv->mdev;
581 u32 eth_proto_cap;
582 u32 link_mode;
583 u32 out[MLX5_ST_SZ_DW(ptys_reg)];
584 int was_opened;
585 int locked;
586 int error;
587 bool ext;
588
589 locked = PRIV_LOCKED(priv);
590 if (!locked)
591 PRIV_LOCK(priv);
592
593 if (IFM_TYPE(priv->media.ifm_media) != IFM_ETHER) {
594 error = EINVAL;
595 goto done;
596 }
597
598 error = mlx5_query_port_ptys(mdev, out, sizeof(out),
599 MLX5_PTYS_EN, 1);
600 if (error != 0) {
601 mlx5_en_err(dev, "Query port media capability failed\n");
602 goto done;
603 }
604
605 ext = MLX5_CAP_PCAM_FEATURE(mdev, ptys_extended_ethernet);
606 link_mode = mlx5e_find_link_mode(IFM_SUBTYPE(priv->media.ifm_media), ext);
607
608 /* query supported capabilities */
609 eth_proto_cap = MLX5_GET_ETH_PROTO(ptys_reg, out, ext,
610 eth_proto_capability);
611
612 /* check for autoselect */
613 if (IFM_SUBTYPE(priv->media.ifm_media) == IFM_AUTO) {
614 link_mode = eth_proto_cap;
615 if (link_mode == 0) {
616 mlx5_en_err(dev, "Port media capability is zero\n");
617 error = EINVAL;
618 goto done;
619 }
620 } else {
621 link_mode = link_mode & eth_proto_cap;
622 if (link_mode == 0) {
623 mlx5_en_err(dev, "Not supported link mode requested\n");
624 error = EINVAL;
625 goto done;
626 }
627 }
628 if (priv->media.ifm_media & (IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE)) {
629 /* check if PFC is enabled */
630 if (priv->params.rx_priority_flow_control ||
631 priv->params.tx_priority_flow_control) {
632 mlx5_en_err(dev, "PFC must be disabled before enabling global pauseframes.\n");
633 error = EINVAL;
634 goto done;
635 }
636 }
637 /* update pauseframe control bits */
638 priv->params.rx_pauseframe_control =
639 (priv->media.ifm_media & IFM_ETH_RXPAUSE) ? 1 : 0;
640 priv->params.tx_pauseframe_control =
641 (priv->media.ifm_media & IFM_ETH_TXPAUSE) ? 1 : 0;
642
643 /* check if device is opened */
644 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
645
646 /* reconfigure the hardware */
647 mlx5_set_port_status(mdev, MLX5_PORT_DOWN);
648 mlx5_set_port_proto(mdev, link_mode, MLX5_PTYS_EN, ext);
649 error = -mlx5e_set_port_pause_and_pfc(priv);
650 if (was_opened)
651 mlx5_set_port_status(mdev, MLX5_PORT_UP);
652
653 done:
654 if (!locked)
655 PRIV_UNLOCK(priv);
656 return (error);
657 }
658
659 static void
mlx5e_update_carrier_work(struct work_struct * work)660 mlx5e_update_carrier_work(struct work_struct *work)
661 {
662 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
663 update_carrier_work);
664
665 PRIV_LOCK(priv);
666 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
667 mlx5e_update_carrier(priv);
668 PRIV_UNLOCK(priv);
669 }
670
671 #define MLX5E_PCIE_PERF_GET_64(a,b,c,d,e,f) \
672 s_debug->c = MLX5_GET64(mpcnt_reg, out, counter_set.f.c);
673
674 #define MLX5E_PCIE_PERF_GET_32(a,b,c,d,e,f) \
675 s_debug->c = MLX5_GET(mpcnt_reg, out, counter_set.f.c);
676
677 static void
mlx5e_update_pcie_counters(struct mlx5e_priv * priv)678 mlx5e_update_pcie_counters(struct mlx5e_priv *priv)
679 {
680 struct mlx5_core_dev *mdev = priv->mdev;
681 struct mlx5e_port_stats_debug *s_debug = &priv->stats.port_stats_debug;
682 const unsigned sz = MLX5_ST_SZ_BYTES(mpcnt_reg);
683 void *out;
684 void *in;
685 int err;
686
687 /* allocate firmware request structures */
688 in = mlx5_vzalloc(sz);
689 out = mlx5_vzalloc(sz);
690 if (in == NULL || out == NULL)
691 goto free_out;
692
693 MLX5_SET(mpcnt_reg, in, grp, MLX5_PCIE_PERFORMANCE_COUNTERS_GROUP);
694 err = mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_MPCNT, 0, 0);
695 if (err != 0)
696 goto free_out;
697
698 MLX5E_PCIE_PERFORMANCE_COUNTERS_64(MLX5E_PCIE_PERF_GET_64)
699 MLX5E_PCIE_PERFORMANCE_COUNTERS_32(MLX5E_PCIE_PERF_GET_32)
700
701 MLX5_SET(mpcnt_reg, in, grp, MLX5_PCIE_TIMERS_AND_STATES_COUNTERS_GROUP);
702 err = mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_MPCNT, 0, 0);
703 if (err != 0)
704 goto free_out;
705
706 MLX5E_PCIE_TIMERS_AND_STATES_COUNTERS_32(MLX5E_PCIE_PERF_GET_32)
707
708 MLX5_SET(mpcnt_reg, in, grp, MLX5_PCIE_LANE_COUNTERS_GROUP);
709 err = mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_MPCNT, 0, 0);
710 if (err != 0)
711 goto free_out;
712
713 MLX5E_PCIE_LANE_COUNTERS_32(MLX5E_PCIE_PERF_GET_32)
714
715 free_out:
716 /* free firmware request structures */
717 kvfree(in);
718 kvfree(out);
719 }
720
721 /*
722 * This function reads the physical port counters from the firmware
723 * using a pre-defined layout defined by various MLX5E_PPORT_XXX()
724 * macros. The output is converted from big-endian 64-bit values into
725 * host endian ones and stored in the "priv->stats.pport" structure.
726 */
727 static void
mlx5e_update_pport_counters(struct mlx5e_priv * priv)728 mlx5e_update_pport_counters(struct mlx5e_priv *priv)
729 {
730 struct mlx5_core_dev *mdev = priv->mdev;
731 struct mlx5e_pport_stats *s = &priv->stats.pport;
732 struct mlx5e_port_stats_debug *s_debug = &priv->stats.port_stats_debug;
733 u32 *in;
734 u32 *out;
735 const u64 *ptr;
736 unsigned sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
737 unsigned x;
738 unsigned y;
739 unsigned z;
740
741 /* allocate firmware request structures */
742 in = mlx5_vzalloc(sz);
743 out = mlx5_vzalloc(sz);
744 if (in == NULL || out == NULL)
745 goto free_out;
746
747 /*
748 * Get pointer to the 64-bit counter set which is located at a
749 * fixed offset in the output firmware request structure:
750 */
751 ptr = (const uint64_t *)MLX5_ADDR_OF(ppcnt_reg, out, counter_set);
752
753 MLX5_SET(ppcnt_reg, in, local_port, 1);
754
755 /* read IEEE802_3 counter group using predefined counter layout */
756 MLX5_SET(ppcnt_reg, in, grp, MLX5_IEEE_802_3_COUNTERS_GROUP);
757 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
758 for (x = 0, y = MLX5E_PPORT_PER_PRIO_STATS_NUM;
759 x != MLX5E_PPORT_IEEE802_3_STATS_NUM; x++, y++)
760 s->arg[y] = be64toh(ptr[x]);
761
762 /* read RFC2819 counter group using predefined counter layout */
763 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2819_COUNTERS_GROUP);
764 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
765 for (x = 0; x != MLX5E_PPORT_RFC2819_STATS_NUM; x++, y++)
766 s->arg[y] = be64toh(ptr[x]);
767
768 for (y = 0; x != MLX5E_PPORT_RFC2819_STATS_NUM +
769 MLX5E_PPORT_RFC2819_STATS_DEBUG_NUM; x++, y++)
770 s_debug->arg[y] = be64toh(ptr[x]);
771
772 /* read RFC2863 counter group using predefined counter layout */
773 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2863_COUNTERS_GROUP);
774 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
775 for (x = 0; x != MLX5E_PPORT_RFC2863_STATS_DEBUG_NUM; x++, y++)
776 s_debug->arg[y] = be64toh(ptr[x]);
777
778 /* read physical layer stats counter group using predefined counter layout */
779 MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_COUNTERS_GROUP);
780 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
781 for (x = 0; x != MLX5E_PPORT_PHYSICAL_LAYER_STATS_DEBUG_NUM; x++, y++)
782 s_debug->arg[y] = be64toh(ptr[x]);
783
784 /* read Extended Ethernet counter group using predefined counter layout */
785 MLX5_SET(ppcnt_reg, in, grp, MLX5_ETHERNET_EXTENDED_COUNTERS_GROUP);
786 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
787 for (x = 0; x != MLX5E_PPORT_ETHERNET_EXTENDED_STATS_DEBUG_NUM; x++, y++)
788 s_debug->arg[y] = be64toh(ptr[x]);
789
790 /* read Extended Statistical Group */
791 if (MLX5_CAP_GEN(mdev, pcam_reg) &&
792 MLX5_CAP_PCAM_FEATURE(mdev, ppcnt_statistical_group) &&
793 MLX5_CAP_PCAM_FEATURE(mdev, per_lane_error_counters)) {
794 /* read Extended Statistical counter group using predefined counter layout */
795 MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_STATISTICAL_GROUP);
796 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
797
798 for (x = 0; x != MLX5E_PPORT_STATISTICAL_DEBUG_NUM; x++, y++)
799 s_debug->arg[y] = be64toh(ptr[x]);
800 }
801
802 /* read PCIE counters */
803 mlx5e_update_pcie_counters(priv);
804
805 /* read per-priority counters */
806 MLX5_SET(ppcnt_reg, in, grp, MLX5_PER_PRIORITY_COUNTERS_GROUP);
807
808 /* iterate all the priorities */
809 for (y = z = 0; z != MLX5E_PPORT_PER_PRIO_STATS_NUM_PRIO; z++) {
810 MLX5_SET(ppcnt_reg, in, prio_tc, z);
811 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
812
813 /* read per priority stats counter group using predefined counter layout */
814 for (x = 0; x != (MLX5E_PPORT_PER_PRIO_STATS_NUM /
815 MLX5E_PPORT_PER_PRIO_STATS_NUM_PRIO); x++, y++)
816 s->arg[y] = be64toh(ptr[x]);
817 }
818
819 free_out:
820 /* free firmware request structures */
821 kvfree(in);
822 kvfree(out);
823 }
824
825 static void
mlx5e_grp_vnic_env_update_stats(struct mlx5e_priv * priv)826 mlx5e_grp_vnic_env_update_stats(struct mlx5e_priv *priv)
827 {
828 u32 out[MLX5_ST_SZ_DW(query_vnic_env_out)] = {};
829 u32 in[MLX5_ST_SZ_DW(query_vnic_env_in)] = {};
830
831 if (!MLX5_CAP_GEN(priv->mdev, nic_receive_steering_discard))
832 return;
833
834 MLX5_SET(query_vnic_env_in, in, opcode,
835 MLX5_CMD_OP_QUERY_VNIC_ENV);
836 MLX5_SET(query_vnic_env_in, in, op_mod, 0);
837 MLX5_SET(query_vnic_env_in, in, other_vport, 0);
838
839 if (mlx5_cmd_exec(priv->mdev, in, sizeof(in), out, sizeof(out)) != 0)
840 return;
841
842 priv->stats.vport.rx_steer_missed_packets =
843 MLX5_GET64(query_vnic_env_out, out,
844 vport_env.nic_receive_steering_discard);
845 }
846
847 /*
848 * This function is called regularly to collect all statistics
849 * counters from the firmware. The values can be viewed through the
850 * sysctl interface. Execution is serialized using the priv's global
851 * configuration lock.
852 */
853 static void
mlx5e_update_stats_locked(struct mlx5e_priv * priv)854 mlx5e_update_stats_locked(struct mlx5e_priv *priv)
855 {
856 struct mlx5_core_dev *mdev = priv->mdev;
857 struct mlx5e_vport_stats *s = &priv->stats.vport;
858 struct mlx5e_sq_stats *sq_stats;
859 u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)];
860 u32 *out;
861 int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out);
862 u64 tso_packets = 0;
863 u64 tso_bytes = 0;
864 u64 tx_queue_dropped = 0;
865 u64 tx_defragged = 0;
866 u64 tx_offload_none = 0;
867 u64 lro_packets = 0;
868 u64 lro_bytes = 0;
869 u64 sw_lro_queued = 0;
870 u64 sw_lro_flushed = 0;
871 u64 rx_csum_none = 0;
872 u64 rx_wqe_err = 0;
873 u64 rx_packets = 0;
874 u64 rx_bytes = 0;
875 u64 rx_decrypted_error = 0;
876 u64 rx_decrypted_ok = 0;
877 u32 rx_out_of_buffer = 0;
878 int error;
879 int i;
880 int j;
881
882 out = mlx5_vzalloc(outlen);
883 if (out == NULL)
884 goto free_out;
885
886 /* Collect firts the SW counters and then HW for consistency */
887 for (i = 0; i < priv->params.num_channels; i++) {
888 struct mlx5e_channel *pch = priv->channel + i;
889 struct mlx5e_rq *rq = &pch->rq;
890 struct mlx5e_rq_stats *rq_stats = &pch->rq.stats;
891
892 /* collect stats from LRO */
893 rq_stats->sw_lro_queued = rq->lro.lro_queued;
894 rq_stats->sw_lro_flushed = rq->lro.lro_flushed;
895 sw_lro_queued += rq_stats->sw_lro_queued;
896 sw_lro_flushed += rq_stats->sw_lro_flushed;
897 lro_packets += rq_stats->lro_packets;
898 lro_bytes += rq_stats->lro_bytes;
899 rx_csum_none += rq_stats->csum_none;
900 rx_wqe_err += rq_stats->wqe_err;
901 rx_packets += rq_stats->packets;
902 rx_bytes += rq_stats->bytes;
903 rx_decrypted_error += rq_stats->decrypted_error_packets;
904 rx_decrypted_ok += rq_stats->decrypted_ok_packets;
905
906 for (j = 0; j < priv->num_tc; j++) {
907 sq_stats = &pch->sq[j].stats;
908
909 tso_packets += sq_stats->tso_packets;
910 tso_bytes += sq_stats->tso_bytes;
911 tx_queue_dropped += sq_stats->dropped;
912 tx_queue_dropped += sq_stats->enobuf;
913 tx_defragged += sq_stats->defragged;
914 tx_offload_none += sq_stats->csum_offload_none;
915 }
916 }
917
918 #ifdef RATELIMIT
919 /* Collect statistics from all rate-limit queues */
920 for (j = 0; j < priv->rl.param.tx_worker_threads_def; j++) {
921 struct mlx5e_rl_worker *rlw = priv->rl.workers + j;
922
923 for (i = 0; i < priv->rl.param.tx_channels_per_worker_def; i++) {
924 struct mlx5e_rl_channel *channel = rlw->channels + i;
925 struct mlx5e_sq *sq = channel->sq;
926
927 if (sq == NULL)
928 continue;
929
930 sq_stats = &sq->stats;
931
932 tso_packets += sq_stats->tso_packets;
933 tso_bytes += sq_stats->tso_bytes;
934 tx_queue_dropped += sq_stats->dropped;
935 tx_queue_dropped += sq_stats->enobuf;
936 tx_defragged += sq_stats->defragged;
937 tx_offload_none += sq_stats->csum_offload_none;
938 }
939 }
940 #endif
941
942 /* update counters */
943 s->tso_packets = tso_packets;
944 s->tso_bytes = tso_bytes;
945 s->tx_queue_dropped = tx_queue_dropped;
946 s->tx_defragged = tx_defragged;
947 s->lro_packets = lro_packets;
948 s->lro_bytes = lro_bytes;
949 s->sw_lro_queued = sw_lro_queued;
950 s->sw_lro_flushed = sw_lro_flushed;
951 s->rx_csum_none = rx_csum_none;
952 s->rx_wqe_err = rx_wqe_err;
953 s->rx_packets = rx_packets;
954 s->rx_bytes = rx_bytes;
955 s->rx_decrypted_error_packets = rx_decrypted_error;
956 s->rx_decrypted_ok_packets = rx_decrypted_ok;
957
958 mlx5e_grp_vnic_env_update_stats(priv);
959
960 /* HW counters */
961 memset(in, 0, sizeof(in));
962
963 MLX5_SET(query_vport_counter_in, in, opcode,
964 MLX5_CMD_OP_QUERY_VPORT_COUNTER);
965 MLX5_SET(query_vport_counter_in, in, op_mod, 0);
966 MLX5_SET(query_vport_counter_in, in, other_vport, 0);
967
968 memset(out, 0, outlen);
969
970 /* get number of out-of-buffer drops first */
971 if (test_bit(MLX5E_STATE_OPENED, &priv->state) != 0 &&
972 mlx5_vport_query_out_of_rx_buffer(mdev, priv->counter_set_id,
973 &rx_out_of_buffer) == 0) {
974 s->rx_out_of_buffer = rx_out_of_buffer;
975 }
976
977 /* get port statistics */
978 if (mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen) == 0) {
979 #define MLX5_GET_CTR(out, x) \
980 MLX5_GET64(query_vport_counter_out, out, x)
981
982 s->rx_error_packets =
983 MLX5_GET_CTR(out, received_errors.packets);
984 s->rx_error_bytes =
985 MLX5_GET_CTR(out, received_errors.octets);
986 s->tx_error_packets =
987 MLX5_GET_CTR(out, transmit_errors.packets);
988 s->tx_error_bytes =
989 MLX5_GET_CTR(out, transmit_errors.octets);
990
991 s->rx_unicast_packets =
992 MLX5_GET_CTR(out, received_eth_unicast.packets);
993 s->rx_unicast_bytes =
994 MLX5_GET_CTR(out, received_eth_unicast.octets);
995 s->tx_unicast_packets =
996 MLX5_GET_CTR(out, transmitted_eth_unicast.packets);
997 s->tx_unicast_bytes =
998 MLX5_GET_CTR(out, transmitted_eth_unicast.octets);
999
1000 s->rx_multicast_packets =
1001 MLX5_GET_CTR(out, received_eth_multicast.packets);
1002 s->rx_multicast_bytes =
1003 MLX5_GET_CTR(out, received_eth_multicast.octets);
1004 s->tx_multicast_packets =
1005 MLX5_GET_CTR(out, transmitted_eth_multicast.packets);
1006 s->tx_multicast_bytes =
1007 MLX5_GET_CTR(out, transmitted_eth_multicast.octets);
1008
1009 s->rx_broadcast_packets =
1010 MLX5_GET_CTR(out, received_eth_broadcast.packets);
1011 s->rx_broadcast_bytes =
1012 MLX5_GET_CTR(out, received_eth_broadcast.octets);
1013 s->tx_broadcast_packets =
1014 MLX5_GET_CTR(out, transmitted_eth_broadcast.packets);
1015 s->tx_broadcast_bytes =
1016 MLX5_GET_CTR(out, transmitted_eth_broadcast.octets);
1017
1018 s->tx_packets = s->tx_unicast_packets +
1019 s->tx_multicast_packets + s->tx_broadcast_packets;
1020 s->tx_bytes = s->tx_unicast_bytes + s->tx_multicast_bytes +
1021 s->tx_broadcast_bytes;
1022
1023 /* Update calculated offload counters */
1024 s->tx_csum_offload = s->tx_packets - tx_offload_none;
1025 s->rx_csum_good = s->rx_packets - s->rx_csum_none;
1026 }
1027
1028 /* Get physical port counters */
1029 mlx5e_update_pport_counters(priv);
1030
1031 s->tx_jumbo_packets =
1032 priv->stats.port_stats_debug.tx_stat_p1519to2047octets +
1033 priv->stats.port_stats_debug.tx_stat_p2048to4095octets +
1034 priv->stats.port_stats_debug.tx_stat_p4096to8191octets +
1035 priv->stats.port_stats_debug.tx_stat_p8192to10239octets;
1036
1037 free_out:
1038 kvfree(out);
1039
1040 /* Update diagnostics, if any */
1041 if (priv->params_ethtool.diag_pci_enable ||
1042 priv->params_ethtool.diag_general_enable) {
1043 error = mlx5_core_get_diagnostics_full(mdev,
1044 priv->params_ethtool.diag_pci_enable ? &priv->params_pci : NULL,
1045 priv->params_ethtool.diag_general_enable ? &priv->params_general : NULL);
1046 if (error != 0)
1047 mlx5_en_err(priv->ifp,
1048 "Failed reading diagnostics: %d\n", error);
1049 }
1050
1051 /* Update FEC, if any */
1052 error = mlx5e_fec_update(priv);
1053 if (error != 0 && error != EOPNOTSUPP) {
1054 mlx5_en_err(priv->ifp,
1055 "Updating FEC failed: %d\n", error);
1056 }
1057
1058 /* Update temperature, if any */
1059 if (priv->params_ethtool.hw_num_temp != 0) {
1060 error = mlx5e_hw_temperature_update(priv);
1061 if (error != 0 && error != EOPNOTSUPP) {
1062 mlx5_en_err(priv->ifp,
1063 "Updating temperature failed: %d\n", error);
1064 }
1065 }
1066 }
1067
1068 static void
mlx5e_update_stats_work(struct work_struct * work)1069 mlx5e_update_stats_work(struct work_struct *work)
1070 {
1071 struct mlx5e_priv *priv;
1072
1073 priv = container_of(work, struct mlx5e_priv, update_stats_work);
1074 PRIV_LOCK(priv);
1075 if (test_bit(MLX5E_STATE_OPENED, &priv->state) != 0 &&
1076 !test_bit(MLX5_INTERFACE_STATE_TEARDOWN, &priv->mdev->intf_state))
1077 mlx5e_update_stats_locked(priv);
1078 PRIV_UNLOCK(priv);
1079 }
1080
1081 static void
mlx5e_update_stats(void * arg)1082 mlx5e_update_stats(void *arg)
1083 {
1084 struct mlx5e_priv *priv = arg;
1085
1086 queue_work(priv->wq, &priv->update_stats_work);
1087
1088 callout_reset(&priv->watchdog, hz / 4, &mlx5e_update_stats, priv);
1089 }
1090
1091 static void
mlx5e_async_event_sub(struct mlx5e_priv * priv,enum mlx5_dev_event event)1092 mlx5e_async_event_sub(struct mlx5e_priv *priv,
1093 enum mlx5_dev_event event)
1094 {
1095 switch (event) {
1096 case MLX5_DEV_EVENT_PORT_UP:
1097 case MLX5_DEV_EVENT_PORT_DOWN:
1098 queue_work(priv->wq, &priv->update_carrier_work);
1099 break;
1100
1101 default:
1102 break;
1103 }
1104 }
1105
1106 static void
mlx5e_async_event(struct mlx5_core_dev * mdev,void * vpriv,enum mlx5_dev_event event,unsigned long param)1107 mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv,
1108 enum mlx5_dev_event event, unsigned long param)
1109 {
1110 struct mlx5e_priv *priv = vpriv;
1111
1112 mtx_lock(&priv->async_events_mtx);
1113 if (test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state))
1114 mlx5e_async_event_sub(priv, event);
1115 mtx_unlock(&priv->async_events_mtx);
1116 }
1117
1118 static void
mlx5e_enable_async_events(struct mlx5e_priv * priv)1119 mlx5e_enable_async_events(struct mlx5e_priv *priv)
1120 {
1121 set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state);
1122 }
1123
1124 static void
mlx5e_disable_async_events(struct mlx5e_priv * priv)1125 mlx5e_disable_async_events(struct mlx5e_priv *priv)
1126 {
1127 mtx_lock(&priv->async_events_mtx);
1128 clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state);
1129 mtx_unlock(&priv->async_events_mtx);
1130 }
1131
1132 static void mlx5e_calibration_callout(void *arg);
1133 static int mlx5e_calibration_duration = 20;
1134 static int mlx5e_fast_calibration = 1;
1135 static int mlx5e_normal_calibration = 30;
1136
1137 static SYSCTL_NODE(_hw_mlx5, OID_AUTO, calibr, CTLFLAG_RW | CTLFLAG_MPSAFE, 0,
1138 "MLX5 timestamp calibration parameters");
1139
1140 SYSCTL_INT(_hw_mlx5_calibr, OID_AUTO, duration, CTLFLAG_RWTUN,
1141 &mlx5e_calibration_duration, 0,
1142 "Duration of initial calibration");
1143 SYSCTL_INT(_hw_mlx5_calibr, OID_AUTO, fast, CTLFLAG_RWTUN,
1144 &mlx5e_fast_calibration, 0,
1145 "Recalibration interval during initial calibration");
1146 SYSCTL_INT(_hw_mlx5_calibr, OID_AUTO, normal, CTLFLAG_RWTUN,
1147 &mlx5e_normal_calibration, 0,
1148 "Recalibration interval during normal operations");
1149
1150 /*
1151 * Ignites the calibration process.
1152 */
1153 static void
mlx5e_reset_calibration_callout(struct mlx5e_priv * priv)1154 mlx5e_reset_calibration_callout(struct mlx5e_priv *priv)
1155 {
1156
1157 if (priv->clbr_done == 0)
1158 mlx5e_calibration_callout(priv);
1159 else
1160 callout_reset_sbt_curcpu(&priv->tstmp_clbr, (priv->clbr_done <
1161 mlx5e_calibration_duration ? mlx5e_fast_calibration :
1162 mlx5e_normal_calibration) * SBT_1S, 0,
1163 mlx5e_calibration_callout, priv, C_DIRECT_EXEC);
1164 }
1165
1166 static uint64_t
mlx5e_timespec2usec(const struct timespec * ts)1167 mlx5e_timespec2usec(const struct timespec *ts)
1168 {
1169
1170 return ((uint64_t)ts->tv_sec * 1000000000 + ts->tv_nsec);
1171 }
1172
1173 static uint64_t
mlx5e_hw_clock(struct mlx5e_priv * priv)1174 mlx5e_hw_clock(struct mlx5e_priv *priv)
1175 {
1176 struct mlx5_init_seg *iseg;
1177 uint32_t hw_h, hw_h1, hw_l;
1178
1179 iseg = priv->mdev->iseg;
1180 do {
1181 hw_h = ioread32be(&iseg->internal_timer_h);
1182 hw_l = ioread32be(&iseg->internal_timer_l);
1183 hw_h1 = ioread32be(&iseg->internal_timer_h);
1184 } while (hw_h1 != hw_h);
1185 return (((uint64_t)hw_h << 32) | hw_l);
1186 }
1187
1188 /*
1189 * The calibration callout, it runs either in the context of the
1190 * thread which enables calibration, or in callout. It takes the
1191 * snapshot of system and adapter clocks, then advances the pointers to
1192 * the calibration point to allow rx path to read the consistent data
1193 * lockless.
1194 */
1195 static void
mlx5e_calibration_callout(void * arg)1196 mlx5e_calibration_callout(void *arg)
1197 {
1198 struct mlx5e_priv *priv;
1199 struct mlx5e_clbr_point *next, *curr;
1200 struct timespec ts;
1201 int clbr_curr_next;
1202
1203 priv = arg;
1204 curr = &priv->clbr_points[priv->clbr_curr];
1205 clbr_curr_next = priv->clbr_curr + 1;
1206 if (clbr_curr_next >= nitems(priv->clbr_points))
1207 clbr_curr_next = 0;
1208 next = &priv->clbr_points[clbr_curr_next];
1209
1210 next->base_prev = curr->base_curr;
1211 next->clbr_hw_prev = curr->clbr_hw_curr;
1212
1213 next->clbr_hw_curr = mlx5e_hw_clock(priv);
1214 if (((next->clbr_hw_curr - curr->clbr_hw_curr) >> MLX5E_TSTMP_PREC) ==
1215 0) {
1216 if (priv->clbr_done != 0) {
1217 mlx5_en_err(priv->ifp,
1218 "HW failed tstmp frozen %#jx %#jx, disabling\n",
1219 next->clbr_hw_curr, curr->clbr_hw_prev);
1220 priv->clbr_done = 0;
1221 }
1222 atomic_store_rel_int(&curr->clbr_gen, 0);
1223 return;
1224 }
1225
1226 nanouptime(&ts);
1227 next->base_curr = mlx5e_timespec2usec(&ts);
1228
1229 curr->clbr_gen = 0;
1230 atomic_thread_fence_rel();
1231 priv->clbr_curr = clbr_curr_next;
1232 atomic_store_rel_int(&next->clbr_gen, ++(priv->clbr_gen));
1233
1234 if (priv->clbr_done < mlx5e_calibration_duration)
1235 priv->clbr_done++;
1236 mlx5e_reset_calibration_callout(priv);
1237 }
1238
1239 static const char *mlx5e_rq_stats_desc[] = {
1240 MLX5E_RQ_STATS(MLX5E_STATS_DESC)
1241 };
1242
1243 static int
mlx5e_create_rq(struct mlx5e_channel * c,struct mlx5e_rq_param * param,struct mlx5e_rq * rq)1244 mlx5e_create_rq(struct mlx5e_channel *c,
1245 struct mlx5e_rq_param *param,
1246 struct mlx5e_rq *rq)
1247 {
1248 struct mlx5e_priv *priv = c->priv;
1249 struct mlx5_core_dev *mdev = priv->mdev;
1250 char buffer[16];
1251 void *rqc = param->rqc;
1252 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
1253 int wq_sz;
1254 int err;
1255 int i;
1256 u32 nsegs, wqe_sz;
1257
1258 err = mlx5e_get_wqe_sz(priv, &wqe_sz, &nsegs);
1259 if (err != 0)
1260 goto done;
1261
1262 /* Create DMA descriptor TAG */
1263 if ((err = -bus_dma_tag_create(
1264 bus_get_dma_tag(mdev->pdev->dev.bsddev),
1265 1, /* any alignment */
1266 0, /* no boundary */
1267 BUS_SPACE_MAXADDR, /* lowaddr */
1268 BUS_SPACE_MAXADDR, /* highaddr */
1269 NULL, NULL, /* filter, filterarg */
1270 nsegs * wqe_sz, /* maxsize */
1271 nsegs, /* nsegments */
1272 nsegs * wqe_sz, /* maxsegsize */
1273 0, /* flags */
1274 NULL, NULL, /* lockfunc, lockfuncarg */
1275 &rq->dma_tag)))
1276 goto done;
1277
1278 err = mlx5_wq_ll_create(mdev, ¶m->wq, rqc_wq, &rq->wq,
1279 &rq->wq_ctrl);
1280 if (err)
1281 goto err_free_dma_tag;
1282
1283 rq->wq.db = &rq->wq.db[MLX5_RCV_DBR];
1284
1285 err = mlx5e_get_wqe_sz(priv, &rq->wqe_sz, &rq->nsegs);
1286 if (err != 0)
1287 goto err_rq_wq_destroy;
1288
1289 wq_sz = mlx5_wq_ll_get_size(&rq->wq);
1290
1291 err = -tcp_lro_init_args(&rq->lro, priv->ifp, TCP_LRO_ENTRIES, wq_sz);
1292 if (err)
1293 goto err_rq_wq_destroy;
1294
1295 rq->mbuf = malloc_domainset(wq_sz * sizeof(rq->mbuf[0]), M_MLX5EN,
1296 mlx5_dev_domainset(mdev), M_WAITOK | M_ZERO);
1297 for (i = 0; i != wq_sz; i++) {
1298 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, i);
1299 int j;
1300
1301 err = -bus_dmamap_create(rq->dma_tag, 0, &rq->mbuf[i].dma_map);
1302 if (err != 0) {
1303 while (i--)
1304 bus_dmamap_destroy(rq->dma_tag, rq->mbuf[i].dma_map);
1305 goto err_rq_mbuf_free;
1306 }
1307
1308 /* set value for constant fields */
1309 for (j = 0; j < rq->nsegs; j++)
1310 wqe->data[j].lkey = cpu_to_be32(priv->mr.key);
1311 }
1312
1313 INIT_WORK(&rq->dim.work, mlx5e_dim_work);
1314 if (priv->params.rx_cq_moderation_mode < 2) {
1315 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_DISABLED;
1316 } else {
1317 void *cqc = container_of(param,
1318 struct mlx5e_channel_param, rq)->rx_cq.cqc;
1319
1320 switch (MLX5_GET(cqc, cqc, cq_period_mode)) {
1321 case MLX5_CQ_PERIOD_MODE_START_FROM_EQE:
1322 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE;
1323 break;
1324 case MLX5_CQ_PERIOD_MODE_START_FROM_CQE:
1325 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_CQE;
1326 break;
1327 default:
1328 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_DISABLED;
1329 break;
1330 }
1331 }
1332
1333 rq->ifp = priv->ifp;
1334 rq->channel = c;
1335 rq->ix = c->ix;
1336
1337 snprintf(buffer, sizeof(buffer), "rxstat%d", c->ix);
1338 mlx5e_create_stats(&rq->stats.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
1339 buffer, mlx5e_rq_stats_desc, MLX5E_RQ_STATS_NUM,
1340 rq->stats.arg);
1341 return (0);
1342
1343 err_rq_mbuf_free:
1344 free(rq->mbuf, M_MLX5EN);
1345 tcp_lro_free(&rq->lro);
1346 err_rq_wq_destroy:
1347 mlx5_wq_destroy(&rq->wq_ctrl);
1348 err_free_dma_tag:
1349 bus_dma_tag_destroy(rq->dma_tag);
1350 done:
1351 return (err);
1352 }
1353
1354 static void
mlx5e_destroy_rq(struct mlx5e_rq * rq)1355 mlx5e_destroy_rq(struct mlx5e_rq *rq)
1356 {
1357 int wq_sz;
1358 int i;
1359
1360 /* destroy all sysctl nodes */
1361 sysctl_ctx_free(&rq->stats.ctx);
1362
1363 /* free leftover LRO packets, if any */
1364 tcp_lro_free(&rq->lro);
1365
1366 wq_sz = mlx5_wq_ll_get_size(&rq->wq);
1367 for (i = 0; i != wq_sz; i++) {
1368 if (rq->mbuf[i].mbuf != NULL) {
1369 if (rq->mbuf[i].ipsec_mtag != NULL)
1370 m_tag_free(&rq->mbuf[i].ipsec_mtag->tag);
1371 bus_dmamap_unload(rq->dma_tag, rq->mbuf[i].dma_map);
1372 m_freem(rq->mbuf[i].mbuf);
1373 }
1374 bus_dmamap_destroy(rq->dma_tag, rq->mbuf[i].dma_map);
1375 }
1376 free(rq->mbuf, M_MLX5EN);
1377 mlx5_wq_destroy(&rq->wq_ctrl);
1378 bus_dma_tag_destroy(rq->dma_tag);
1379 }
1380
1381 static int
mlx5e_enable_rq(struct mlx5e_rq * rq,struct mlx5e_rq_param * param)1382 mlx5e_enable_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param)
1383 {
1384 struct mlx5e_channel *c = rq->channel;
1385 struct mlx5e_priv *priv = c->priv;
1386 struct mlx5_core_dev *mdev = priv->mdev;
1387 void *in;
1388 void *rqc;
1389 void *wq;
1390 int inlen;
1391 int err;
1392 u8 ts_format;
1393
1394 inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
1395 sizeof(u64) * rq->wq_ctrl.buf.npages;
1396 in = mlx5_vzalloc(inlen);
1397 if (in == NULL)
1398 return (-ENOMEM);
1399
1400 ts_format = mlx5_get_rq_default_ts(mdev);
1401 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
1402 wq = MLX5_ADDR_OF(rqc, rqc, wq);
1403
1404 memcpy(rqc, param->rqc, sizeof(param->rqc));
1405
1406 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
1407 MLX5_SET(rqc, rqc, ts_format, ts_format);
1408 MLX5_SET(rqc, rqc, flush_in_error_en, 1);
1409 if (priv->counter_set_id >= 0)
1410 MLX5_SET(rqc, rqc, counter_set_id, priv->counter_set_id);
1411 MLX5_SET(wq, wq, log_wq_pg_sz, rq->wq_ctrl.buf.page_shift -
1412 MLX5_ADAPTER_PAGE_SHIFT);
1413 MLX5_SET64(wq, wq, dbr_addr, rq->wq_ctrl.db.dma);
1414
1415 mlx5_fill_page_array(&rq->wq_ctrl.buf,
1416 (__be64 *) MLX5_ADDR_OF(wq, wq, pas));
1417
1418 err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
1419
1420 kvfree(in);
1421
1422 return (err);
1423 }
1424
1425 static int
mlx5e_modify_rq(struct mlx5e_rq * rq,int curr_state,int next_state)1426 mlx5e_modify_rq(struct mlx5e_rq *rq, int curr_state, int next_state)
1427 {
1428 struct mlx5e_channel *c = rq->channel;
1429 struct mlx5e_priv *priv = c->priv;
1430 struct mlx5_core_dev *mdev = priv->mdev;
1431
1432 void *in;
1433 void *rqc;
1434 int inlen;
1435 int err;
1436
1437 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
1438 in = mlx5_vzalloc(inlen);
1439 if (in == NULL)
1440 return (-ENOMEM);
1441
1442 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
1443
1444 MLX5_SET(modify_rq_in, in, rqn, rq->rqn);
1445 MLX5_SET(modify_rq_in, in, rq_state, curr_state);
1446 MLX5_SET(rqc, rqc, state, next_state);
1447
1448 err = mlx5_core_modify_rq(mdev, in, inlen);
1449
1450 kvfree(in);
1451
1452 return (err);
1453 }
1454
1455 static void
mlx5e_disable_rq(struct mlx5e_rq * rq)1456 mlx5e_disable_rq(struct mlx5e_rq *rq)
1457 {
1458 struct mlx5e_channel *c = rq->channel;
1459 struct mlx5e_priv *priv = c->priv;
1460 struct mlx5_core_dev *mdev = priv->mdev;
1461
1462 mlx5_core_destroy_rq(mdev, rq->rqn);
1463 }
1464
1465 static int
mlx5e_open_rq(struct mlx5e_channel * c,struct mlx5e_rq_param * param,struct mlx5e_rq * rq)1466 mlx5e_open_rq(struct mlx5e_channel *c,
1467 struct mlx5e_rq_param *param,
1468 struct mlx5e_rq *rq)
1469 {
1470 int err;
1471
1472 err = mlx5e_create_rq(c, param, rq);
1473 if (err)
1474 return (err);
1475
1476 /* set CQN in RQ parameters */
1477 MLX5_SET(rqc, param->rqc, cqn, c->rq.cq.mcq.cqn);
1478
1479 err = mlx5e_enable_rq(rq, param);
1480 if (err)
1481 goto err_destroy_rq;
1482
1483 err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
1484 if (err)
1485 goto err_disable_rq;
1486
1487 c->rq.enabled = 1;
1488
1489 return (0);
1490
1491 err_disable_rq:
1492 mlx5e_disable_rq(rq);
1493 err_destroy_rq:
1494 mlx5e_destroy_rq(rq);
1495
1496 return (err);
1497 }
1498
1499 static void
mlx5e_close_rq(struct mlx5e_rq * rq)1500 mlx5e_close_rq(struct mlx5e_rq *rq)
1501 {
1502 mtx_lock(&rq->mtx);
1503 rq->enabled = 0;
1504 callout_stop(&rq->watchdog);
1505 mtx_unlock(&rq->mtx);
1506
1507 mlx5e_modify_rq(rq, MLX5_RQC_STATE_RDY, MLX5_RQC_STATE_ERR);
1508 }
1509
1510 static void
mlx5e_close_rq_wait(struct mlx5e_rq * rq)1511 mlx5e_close_rq_wait(struct mlx5e_rq *rq)
1512 {
1513
1514 mtx_lock(&rq->mtx);
1515 MPASS(rq->enabled == 0);
1516 while (rq->processing > 0) {
1517 /*
1518 * No wakeup, relying on timeout.
1519 * Use msleep_sbt() since msleep() conflicts with linuxkpi.
1520 */
1521 msleep_sbt(&rq->processing, &rq->mtx, 0, "mlx5ecrq",
1522 tick_sbt * hz, 0, C_HARDCLOCK);
1523 }
1524 mtx_unlock(&rq->mtx);
1525 mlx5e_disable_rq(rq);
1526 mlx5e_close_cq(&rq->cq);
1527 cancel_work_sync(&rq->dim.work);
1528 mlx5e_destroy_rq(rq);
1529 }
1530
1531 /*
1532 * What is a drop RQ and why is it needed?
1533 *
1534 * The RSS indirection table, also called the RQT, selects the
1535 * destination RQ based on the receive queue number, RQN. The RQT is
1536 * frequently referred to by flow steering rules to distribute traffic
1537 * among multiple RQs. The problem is that the RQs cannot be destroyed
1538 * before the RQT referring them is destroyed too. Further, TLS RX
1539 * rules may still be referring to the RQT even if the link went
1540 * down. Because there is no magic RQN for dropping packets, we create
1541 * a dummy RQ, also called drop RQ, which sole purpose is to drop all
1542 * received packets. When the link goes down this RQN is filled in all
1543 * RQT entries, of the main RQT, so the real RQs which are about to be
1544 * destroyed can be released and the TLS RX rules can be sustained.
1545 */
1546 static void
mlx5e_open_drop_rq_comp(struct mlx5_core_cq * mcq __unused,struct mlx5_eqe * eqe __unused)1547 mlx5e_open_drop_rq_comp(struct mlx5_core_cq *mcq __unused, struct mlx5_eqe *eqe __unused)
1548 {
1549 }
1550
1551 static int
mlx5e_open_drop_rq(struct mlx5e_priv * priv,struct mlx5e_rq * drop_rq)1552 mlx5e_open_drop_rq(struct mlx5e_priv *priv,
1553 struct mlx5e_rq *drop_rq)
1554 {
1555 struct mlx5e_cq_param param_cq = {};
1556 struct mlx5e_rq_param param_rq = {};
1557 void *rqc_wq = MLX5_ADDR_OF(rqc, param_rq.rqc, wq);
1558 int err;
1559
1560 /* set channel pointer */
1561 drop_rq->channel = priv->channel;
1562
1563 /* set basic CQ parameters needed */
1564 MLX5_SET(cqc, param_cq.cqc, log_cq_size, 0);
1565 MLX5_SET(cqc, param_cq.cqc, uar_page, priv->mdev->priv.uar->index);
1566
1567 /* open receive completion queue */
1568 err = mlx5e_open_cq(priv, ¶m_cq, &drop_rq->cq,
1569 &mlx5e_open_drop_rq_comp, 0);
1570 if (err)
1571 goto err_done;
1572
1573 /* set basic WQ parameters needed */
1574 MLX5_SET(wq, rqc_wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1575 MLX5_SET(wq, rqc_wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
1576 MLX5_SET(wq, rqc_wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe) + sizeof(struct mlx5_wqe_data_seg)));
1577 MLX5_SET(wq, rqc_wq, log_wq_sz, 0);
1578 MLX5_SET(wq, rqc_wq, pd, priv->pdn);
1579
1580 param_rq.wq.linear = 1;
1581
1582 err = mlx5_wq_ll_create(priv->mdev, ¶m_rq.wq, rqc_wq, &drop_rq->wq,
1583 &drop_rq->wq_ctrl);
1584 if (err)
1585 goto err_close_cq;
1586
1587 /* set CQN in RQ parameters */
1588 MLX5_SET(rqc, param_rq.rqc, cqn, drop_rq->cq.mcq.cqn);
1589
1590 err = mlx5e_enable_rq(drop_rq, ¶m_rq);
1591 if (err)
1592 goto err_wq_destroy;
1593
1594 err = mlx5e_modify_rq(drop_rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
1595 if (err)
1596 goto err_disable_rq;
1597
1598 return (err);
1599
1600 err_disable_rq:
1601 mlx5e_disable_rq(drop_rq);
1602 err_wq_destroy:
1603 mlx5_wq_destroy(&drop_rq->wq_ctrl);
1604 err_close_cq:
1605 mlx5e_close_cq(&drop_rq->cq);
1606 err_done:
1607 return (err);
1608 }
1609
1610 static void
mlx5e_close_drop_rq(struct mlx5e_rq * drop_rq)1611 mlx5e_close_drop_rq(struct mlx5e_rq *drop_rq)
1612 {
1613 mlx5e_modify_rq(drop_rq, MLX5_RQC_STATE_RDY, MLX5_RQC_STATE_ERR);
1614 mlx5e_disable_rq(drop_rq);
1615 mlx5_wq_destroy(&drop_rq->wq_ctrl);
1616 mlx5e_close_cq(&drop_rq->cq);
1617 }
1618
1619 void
mlx5e_free_sq_db(struct mlx5e_sq * sq)1620 mlx5e_free_sq_db(struct mlx5e_sq *sq)
1621 {
1622 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1623 int x;
1624
1625 for (x = 0; x != wq_sz; x++) {
1626 if (sq->mbuf[x].mbuf != NULL) {
1627 bus_dmamap_unload(sq->dma_tag, sq->mbuf[x].dma_map);
1628 m_freem(sq->mbuf[x].mbuf);
1629 }
1630 if (sq->mbuf[x].mst != NULL) {
1631 m_snd_tag_rele(sq->mbuf[x].mst);
1632 sq->mbuf[x].mst = NULL;
1633 }
1634 bus_dmamap_destroy(sq->dma_tag, sq->mbuf[x].dma_map);
1635 }
1636 free(sq->mbuf, M_MLX5EN);
1637 }
1638
1639 int
mlx5e_alloc_sq_db(struct mlx5e_sq * sq)1640 mlx5e_alloc_sq_db(struct mlx5e_sq *sq)
1641 {
1642 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1643 int err;
1644 int x;
1645
1646 sq->mbuf = malloc_domainset(wq_sz * sizeof(sq->mbuf[0]), M_MLX5EN,
1647 mlx5_dev_domainset(sq->priv->mdev), M_WAITOK | M_ZERO);
1648
1649 /* Create DMA descriptor MAPs */
1650 for (x = 0; x != wq_sz; x++) {
1651 err = -bus_dmamap_create(sq->dma_tag, 0, &sq->mbuf[x].dma_map);
1652 if (err != 0) {
1653 while (x--)
1654 bus_dmamap_destroy(sq->dma_tag, sq->mbuf[x].dma_map);
1655 free(sq->mbuf, M_MLX5EN);
1656 return (err);
1657 }
1658 }
1659 return (0);
1660 }
1661
1662 static const char *mlx5e_sq_stats_desc[] = {
1663 MLX5E_SQ_STATS(MLX5E_STATS_DESC)
1664 };
1665
1666 void
mlx5e_update_sq_inline(struct mlx5e_sq * sq)1667 mlx5e_update_sq_inline(struct mlx5e_sq *sq)
1668 {
1669 sq->max_inline = sq->priv->params.tx_max_inline;
1670 sq->min_inline_mode = sq->priv->params.tx_min_inline_mode;
1671
1672 /*
1673 * Check if trust state is DSCP or if inline mode is NONE which
1674 * indicates CX-5 or newer hardware.
1675 */
1676 if (sq->priv->params_ethtool.trust_state != MLX5_QPTS_TRUST_PCP ||
1677 sq->min_inline_mode == MLX5_INLINE_MODE_NONE) {
1678 if (MLX5_CAP_ETH(sq->priv->mdev, wqe_vlan_insert))
1679 sq->min_insert_caps = MLX5E_INSERT_VLAN | MLX5E_INSERT_NON_VLAN;
1680 else
1681 sq->min_insert_caps = MLX5E_INSERT_NON_VLAN;
1682 } else {
1683 sq->min_insert_caps = 0;
1684 }
1685 }
1686
1687 static void
mlx5e_refresh_sq_inline_sub(struct mlx5e_priv * priv,struct mlx5e_channel * c)1688 mlx5e_refresh_sq_inline_sub(struct mlx5e_priv *priv, struct mlx5e_channel *c)
1689 {
1690 int i;
1691
1692 for (i = 0; i != priv->num_tc; i++) {
1693 mtx_lock(&c->sq[i].lock);
1694 mlx5e_update_sq_inline(&c->sq[i]);
1695 mtx_unlock(&c->sq[i].lock);
1696 }
1697 }
1698
1699 void
mlx5e_refresh_sq_inline(struct mlx5e_priv * priv)1700 mlx5e_refresh_sq_inline(struct mlx5e_priv *priv)
1701 {
1702 int i;
1703
1704 /* check if channels are closed */
1705 if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
1706 return;
1707
1708 for (i = 0; i < priv->params.num_channels; i++)
1709 mlx5e_refresh_sq_inline_sub(priv, &priv->channel[i]);
1710 }
1711
1712 static int
mlx5e_create_sq(struct mlx5e_channel * c,int tc,struct mlx5e_sq_param * param,struct mlx5e_sq * sq)1713 mlx5e_create_sq(struct mlx5e_channel *c,
1714 int tc,
1715 struct mlx5e_sq_param *param,
1716 struct mlx5e_sq *sq)
1717 {
1718 struct mlx5e_priv *priv = c->priv;
1719 struct mlx5_core_dev *mdev = priv->mdev;
1720 char buffer[16];
1721 void *sqc = param->sqc;
1722 void *sqc_wq = MLX5_ADDR_OF(sqc, sqc, wq);
1723 int err;
1724
1725 /* Create DMA descriptor TAG */
1726 if ((err = -bus_dma_tag_create(
1727 bus_get_dma_tag(mdev->pdev->dev.bsddev),
1728 1, /* any alignment */
1729 0, /* no boundary */
1730 BUS_SPACE_MAXADDR, /* lowaddr */
1731 BUS_SPACE_MAXADDR, /* highaddr */
1732 NULL, NULL, /* filter, filterarg */
1733 MLX5E_MAX_TX_PAYLOAD_SIZE, /* maxsize */
1734 MLX5E_MAX_TX_MBUF_FRAGS, /* nsegments */
1735 MLX5E_MAX_TX_MBUF_SIZE, /* maxsegsize */
1736 0, /* flags */
1737 NULL, NULL, /* lockfunc, lockfuncarg */
1738 &sq->dma_tag)))
1739 goto done;
1740
1741 sq->mkey_be = cpu_to_be32(priv->mr.key);
1742 sq->ifp = priv->ifp;
1743 sq->priv = priv;
1744 sq->tc = tc;
1745
1746 err = mlx5_wq_cyc_create(mdev, ¶m->wq, sqc_wq, &sq->wq,
1747 &sq->wq_ctrl);
1748 if (err)
1749 goto err_free_dma_tag;
1750
1751 sq->wq.db = &sq->wq.db[MLX5_SND_DBR];
1752
1753 err = mlx5e_alloc_sq_db(sq);
1754 if (err)
1755 goto err_sq_wq_destroy;
1756
1757 mlx5e_update_sq_inline(sq);
1758
1759 snprintf(buffer, sizeof(buffer), "txstat%dtc%d", c->ix, tc);
1760 mlx5e_create_stats(&sq->stats.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
1761 buffer, mlx5e_sq_stats_desc, MLX5E_SQ_STATS_NUM,
1762 sq->stats.arg);
1763
1764 return (0);
1765
1766 err_sq_wq_destroy:
1767 mlx5_wq_destroy(&sq->wq_ctrl);
1768
1769 err_free_dma_tag:
1770 bus_dma_tag_destroy(sq->dma_tag);
1771 done:
1772 return (err);
1773 }
1774
1775 static void
mlx5e_destroy_sq(struct mlx5e_sq * sq)1776 mlx5e_destroy_sq(struct mlx5e_sq *sq)
1777 {
1778 /* destroy all sysctl nodes */
1779 sysctl_ctx_free(&sq->stats.ctx);
1780
1781 mlx5e_free_sq_db(sq);
1782 mlx5_wq_destroy(&sq->wq_ctrl);
1783 bus_dma_tag_destroy(sq->dma_tag);
1784 }
1785
1786 int
mlx5e_enable_sq(struct mlx5e_sq * sq,struct mlx5e_sq_param * param,const struct mlx5_sq_bfreg * bfreg,int tis_num)1787 mlx5e_enable_sq(struct mlx5e_sq *sq, struct mlx5e_sq_param *param,
1788 const struct mlx5_sq_bfreg *bfreg, int tis_num)
1789 {
1790 void *in;
1791 void *sqc;
1792 void *wq;
1793 int inlen;
1794 int err;
1795 u8 ts_format;
1796
1797 inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
1798 sizeof(u64) * sq->wq_ctrl.buf.npages;
1799 in = mlx5_vzalloc(inlen);
1800 if (in == NULL)
1801 return (-ENOMEM);
1802
1803 sq->uar_map = bfreg->map;
1804
1805 ts_format = mlx5_get_sq_default_ts(sq->priv->mdev);
1806 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1807 wq = MLX5_ADDR_OF(sqc, sqc, wq);
1808
1809 memcpy(sqc, param->sqc, sizeof(param->sqc));
1810
1811 MLX5_SET(sqc, sqc, tis_num_0, tis_num);
1812 MLX5_SET(sqc, sqc, cqn, sq->cq.mcq.cqn);
1813 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
1814 MLX5_SET(sqc, sqc, ts_format, ts_format);
1815 MLX5_SET(sqc, sqc, tis_lst_sz, 1);
1816 MLX5_SET(sqc, sqc, flush_in_error_en, 1);
1817 MLX5_SET(sqc, sqc, allow_swp, 1);
1818
1819 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1820 MLX5_SET(wq, wq, uar_page, bfreg->index);
1821 MLX5_SET(wq, wq, log_wq_pg_sz, sq->wq_ctrl.buf.page_shift -
1822 MLX5_ADAPTER_PAGE_SHIFT);
1823 MLX5_SET64(wq, wq, dbr_addr, sq->wq_ctrl.db.dma);
1824
1825 mlx5_fill_page_array(&sq->wq_ctrl.buf,
1826 (__be64 *) MLX5_ADDR_OF(wq, wq, pas));
1827
1828 err = mlx5_core_create_sq(sq->priv->mdev, in, inlen, &sq->sqn);
1829
1830 kvfree(in);
1831
1832 return (err);
1833 }
1834
1835 int
mlx5e_modify_sq(struct mlx5e_sq * sq,int curr_state,int next_state)1836 mlx5e_modify_sq(struct mlx5e_sq *sq, int curr_state, int next_state)
1837 {
1838 void *in;
1839 void *sqc;
1840 int inlen;
1841 int err;
1842
1843 inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
1844 in = mlx5_vzalloc(inlen);
1845 if (in == NULL)
1846 return (-ENOMEM);
1847
1848 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
1849
1850 MLX5_SET(modify_sq_in, in, sqn, sq->sqn);
1851 MLX5_SET(modify_sq_in, in, sq_state, curr_state);
1852 MLX5_SET(sqc, sqc, state, next_state);
1853
1854 err = mlx5_core_modify_sq(sq->priv->mdev, in, inlen);
1855
1856 kvfree(in);
1857
1858 return (err);
1859 }
1860
1861 void
mlx5e_disable_sq(struct mlx5e_sq * sq)1862 mlx5e_disable_sq(struct mlx5e_sq *sq)
1863 {
1864
1865 mlx5_core_destroy_sq(sq->priv->mdev, sq->sqn);
1866 }
1867
1868 static int
mlx5e_open_sq(struct mlx5e_channel * c,int tc,struct mlx5e_sq_param * param,struct mlx5e_sq * sq)1869 mlx5e_open_sq(struct mlx5e_channel *c,
1870 int tc,
1871 struct mlx5e_sq_param *param,
1872 struct mlx5e_sq *sq)
1873 {
1874 int err;
1875
1876 sq->cev_factor = c->priv->params_ethtool.tx_completion_fact;
1877
1878 /* ensure the TX completion event factor is not zero */
1879 if (sq->cev_factor == 0)
1880 sq->cev_factor = 1;
1881
1882 err = mlx5e_create_sq(c, tc, param, sq);
1883 if (err)
1884 return (err);
1885
1886 err = mlx5e_enable_sq(sq, param, &c->bfreg, c->priv->tisn[tc]);
1887 if (err)
1888 goto err_destroy_sq;
1889
1890 err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST, MLX5_SQC_STATE_RDY);
1891 if (err)
1892 goto err_disable_sq;
1893
1894 WRITE_ONCE(sq->running, 1);
1895
1896 return (0);
1897
1898 err_disable_sq:
1899 mlx5e_disable_sq(sq);
1900 err_destroy_sq:
1901 mlx5e_destroy_sq(sq);
1902
1903 return (err);
1904 }
1905
1906 static void
mlx5e_sq_send_nops_locked(struct mlx5e_sq * sq,int can_sleep)1907 mlx5e_sq_send_nops_locked(struct mlx5e_sq *sq, int can_sleep)
1908 {
1909 /* fill up remainder with NOPs */
1910 while (sq->cev_counter != 0) {
1911 while (!mlx5e_sq_has_room_for(sq, 1)) {
1912 if (can_sleep != 0) {
1913 mtx_unlock(&sq->lock);
1914 msleep(4);
1915 mtx_lock(&sq->lock);
1916 } else {
1917 goto done;
1918 }
1919 }
1920 /* send a single NOP */
1921 mlx5e_send_nop(sq, 1);
1922 atomic_thread_fence_rel();
1923 }
1924 done:
1925 mlx5e_tx_notify_hw(sq, false);
1926 }
1927
1928 void
mlx5e_sq_cev_timeout(void * arg)1929 mlx5e_sq_cev_timeout(void *arg)
1930 {
1931 struct mlx5e_sq *sq = arg;
1932
1933 mtx_assert(&sq->lock, MA_OWNED);
1934
1935 /* check next state */
1936 switch (sq->cev_next_state) {
1937 case MLX5E_CEV_STATE_SEND_NOPS:
1938 /* fill TX ring with NOPs, if any */
1939 mlx5e_sq_send_nops_locked(sq, 0);
1940
1941 /* check if completed */
1942 if (sq->cev_counter == 0) {
1943 sq->cev_next_state = MLX5E_CEV_STATE_INITIAL;
1944 return;
1945 }
1946 break;
1947 default:
1948 /* send NOPs on next timeout */
1949 sq->cev_next_state = MLX5E_CEV_STATE_SEND_NOPS;
1950 break;
1951 }
1952
1953 /* restart timer */
1954 callout_reset_curcpu(&sq->cev_callout, hz, mlx5e_sq_cev_timeout, sq);
1955 }
1956
1957 void
mlx5e_drain_sq(struct mlx5e_sq * sq)1958 mlx5e_drain_sq(struct mlx5e_sq *sq)
1959 {
1960 int error;
1961 struct mlx5_core_dev *mdev= sq->priv->mdev;
1962
1963 /*
1964 * Check if already stopped.
1965 *
1966 * NOTE: Serialization of this function is managed by the
1967 * caller ensuring the priv's state lock is locked or in case
1968 * of rate limit support, a single thread manages drain and
1969 * resume of SQs. The "running" variable can therefore safely
1970 * be read without any locks.
1971 */
1972 if (READ_ONCE(sq->running) == 0)
1973 return;
1974
1975 /* don't put more packets into the SQ */
1976 WRITE_ONCE(sq->running, 0);
1977
1978 /* serialize access to DMA rings */
1979 mtx_lock(&sq->lock);
1980
1981 /* teardown event factor timer, if any */
1982 sq->cev_next_state = MLX5E_CEV_STATE_HOLD_NOPS;
1983 callout_stop(&sq->cev_callout);
1984
1985 /* send dummy NOPs in order to flush the transmit ring */
1986 mlx5e_sq_send_nops_locked(sq, 1);
1987 mtx_unlock(&sq->lock);
1988
1989 /* wait till SQ is empty or link is down */
1990 mtx_lock(&sq->lock);
1991 while (sq->cc != sq->pc &&
1992 (sq->priv->media_status_last & IFM_ACTIVE) != 0 &&
1993 mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR &&
1994 pci_channel_offline(mdev->pdev) == 0) {
1995 mtx_unlock(&sq->lock);
1996 msleep(1);
1997 sq->cq.mcq.comp(&sq->cq.mcq, NULL);
1998 mtx_lock(&sq->lock);
1999 }
2000 mtx_unlock(&sq->lock);
2001
2002 /* error out remaining requests */
2003 error = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RDY, MLX5_SQC_STATE_ERR);
2004 if (error != 0) {
2005 mlx5_en_err(sq->ifp,
2006 "mlx5e_modify_sq() from RDY to ERR failed: %d\n", error);
2007 }
2008
2009 /* wait till SQ is empty */
2010 mtx_lock(&sq->lock);
2011 while (sq->cc != sq->pc &&
2012 mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR &&
2013 pci_channel_offline(mdev->pdev) == 0) {
2014 mtx_unlock(&sq->lock);
2015 msleep(1);
2016 sq->cq.mcq.comp(&sq->cq.mcq, NULL);
2017 mtx_lock(&sq->lock);
2018 }
2019 mtx_unlock(&sq->lock);
2020 }
2021
2022 static void
mlx5e_close_sq_wait(struct mlx5e_sq * sq)2023 mlx5e_close_sq_wait(struct mlx5e_sq *sq)
2024 {
2025
2026 mlx5e_drain_sq(sq);
2027 mlx5e_disable_sq(sq);
2028 mlx5e_destroy_sq(sq);
2029 }
2030
2031 static int
mlx5e_create_cq(struct mlx5e_priv * priv,struct mlx5e_cq_param * param,struct mlx5e_cq * cq,mlx5e_cq_comp_t * comp,int eq_ix)2032 mlx5e_create_cq(struct mlx5e_priv *priv,
2033 struct mlx5e_cq_param *param,
2034 struct mlx5e_cq *cq,
2035 mlx5e_cq_comp_t *comp,
2036 int eq_ix)
2037 {
2038 struct mlx5_core_dev *mdev = priv->mdev;
2039 struct mlx5_core_cq *mcq = &cq->mcq;
2040 int eqn_not_used;
2041 int irqn;
2042 int err;
2043 u32 i;
2044
2045 err = mlx5_vector2eqn(mdev, eq_ix, &eqn_not_used, &irqn);
2046 if (err)
2047 return (err);
2048
2049 err = mlx5_cqwq_create(mdev, ¶m->wq, param->cqc, &cq->wq,
2050 &cq->wq_ctrl);
2051 if (err)
2052 return (err);
2053
2054 mcq->cqe_sz = 64;
2055 mcq->set_ci_db = cq->wq_ctrl.db.db;
2056 mcq->arm_db = cq->wq_ctrl.db.db + 1;
2057 *mcq->set_ci_db = 0;
2058 *mcq->arm_db = 0;
2059 mcq->vector = eq_ix;
2060 mcq->comp = comp;
2061 mcq->event = mlx5e_cq_error_event;
2062 mcq->irqn = irqn;
2063
2064 for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
2065 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
2066
2067 cqe->op_own = 0xf1;
2068 }
2069
2070 cq->priv = priv;
2071
2072 return (0);
2073 }
2074
2075 static void
mlx5e_destroy_cq(struct mlx5e_cq * cq)2076 mlx5e_destroy_cq(struct mlx5e_cq *cq)
2077 {
2078 mlx5_wq_destroy(&cq->wq_ctrl);
2079 }
2080
2081 static int
mlx5e_enable_cq(struct mlx5e_cq * cq,struct mlx5e_cq_param * param,int eq_ix)2082 mlx5e_enable_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param, int eq_ix)
2083 {
2084 struct mlx5_core_cq *mcq = &cq->mcq;
2085 u32 out[MLX5_ST_SZ_DW(create_cq_out)];
2086 void *in;
2087 void *cqc;
2088 int inlen;
2089 int irqn_not_used;
2090 int eqn;
2091 int err;
2092
2093 inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
2094 sizeof(u64) * cq->wq_ctrl.buf.npages;
2095 in = mlx5_vzalloc(inlen);
2096 if (in == NULL)
2097 return (-ENOMEM);
2098
2099 cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
2100
2101 memcpy(cqc, param->cqc, sizeof(param->cqc));
2102
2103 mlx5_fill_page_array(&cq->wq_ctrl.buf,
2104 (__be64 *) MLX5_ADDR_OF(create_cq_in, in, pas));
2105
2106 mlx5_vector2eqn(cq->priv->mdev, eq_ix, &eqn, &irqn_not_used);
2107
2108 MLX5_SET(cqc, cqc, c_eqn, eqn);
2109 MLX5_SET(cqc, cqc, log_page_size, cq->wq_ctrl.buf.page_shift -
2110 MLX5_ADAPTER_PAGE_SHIFT);
2111 MLX5_SET64(cqc, cqc, dbr_addr, cq->wq_ctrl.db.dma);
2112
2113 err = mlx5_core_create_cq(cq->priv->mdev, mcq, in, inlen, out, sizeof(out));
2114
2115 kvfree(in);
2116
2117 if (err)
2118 return (err);
2119
2120 mlx5e_cq_arm(cq, MLX5_GET_DOORBELL_LOCK(&cq->priv->doorbell_lock));
2121
2122 return (0);
2123 }
2124
2125 static void
mlx5e_disable_cq(struct mlx5e_cq * cq)2126 mlx5e_disable_cq(struct mlx5e_cq *cq)
2127 {
2128
2129 mlx5_core_destroy_cq(cq->priv->mdev, &cq->mcq);
2130 }
2131
2132 int
mlx5e_open_cq(struct mlx5e_priv * priv,struct mlx5e_cq_param * param,struct mlx5e_cq * cq,mlx5e_cq_comp_t * comp,int eq_ix)2133 mlx5e_open_cq(struct mlx5e_priv *priv,
2134 struct mlx5e_cq_param *param,
2135 struct mlx5e_cq *cq,
2136 mlx5e_cq_comp_t *comp,
2137 int eq_ix)
2138 {
2139 int err;
2140
2141 err = mlx5e_create_cq(priv, param, cq, comp, eq_ix);
2142 if (err)
2143 return (err);
2144
2145 err = mlx5e_enable_cq(cq, param, eq_ix);
2146 if (err)
2147 goto err_destroy_cq;
2148
2149 return (0);
2150
2151 err_destroy_cq:
2152 mlx5e_destroy_cq(cq);
2153
2154 return (err);
2155 }
2156
2157 void
mlx5e_close_cq(struct mlx5e_cq * cq)2158 mlx5e_close_cq(struct mlx5e_cq *cq)
2159 {
2160 mlx5e_disable_cq(cq);
2161 mlx5e_destroy_cq(cq);
2162 }
2163
2164 static int
mlx5e_open_tx_cqs(struct mlx5e_channel * c,struct mlx5e_channel_param * cparam)2165 mlx5e_open_tx_cqs(struct mlx5e_channel *c,
2166 struct mlx5e_channel_param *cparam)
2167 {
2168 int err;
2169 int tc;
2170
2171 for (tc = 0; tc < c->priv->num_tc; tc++) {
2172 /* open completion queue */
2173 err = mlx5e_open_cq(c->priv, &cparam->tx_cq, &c->sq[tc].cq,
2174 &mlx5e_tx_cq_comp, c->ix);
2175 if (err)
2176 goto err_close_tx_cqs;
2177 }
2178 return (0);
2179
2180 err_close_tx_cqs:
2181 for (tc--; tc >= 0; tc--)
2182 mlx5e_close_cq(&c->sq[tc].cq);
2183
2184 return (err);
2185 }
2186
2187 static void
mlx5e_close_tx_cqs(struct mlx5e_channel * c)2188 mlx5e_close_tx_cqs(struct mlx5e_channel *c)
2189 {
2190 int tc;
2191
2192 for (tc = 0; tc < c->priv->num_tc; tc++)
2193 mlx5e_close_cq(&c->sq[tc].cq);
2194 }
2195
2196 static int
mlx5e_open_sqs(struct mlx5e_channel * c,struct mlx5e_channel_param * cparam)2197 mlx5e_open_sqs(struct mlx5e_channel *c,
2198 struct mlx5e_channel_param *cparam)
2199 {
2200 int err;
2201 int tc;
2202
2203 for (tc = 0; tc < c->priv->num_tc; tc++) {
2204 err = mlx5e_open_sq(c, tc, &cparam->sq, &c->sq[tc]);
2205 if (err)
2206 goto err_close_sqs;
2207 }
2208
2209 return (0);
2210
2211 err_close_sqs:
2212 for (tc--; tc >= 0; tc--)
2213 mlx5e_close_sq_wait(&c->sq[tc]);
2214
2215 return (err);
2216 }
2217
2218 static void
mlx5e_close_sqs_wait(struct mlx5e_channel * c)2219 mlx5e_close_sqs_wait(struct mlx5e_channel *c)
2220 {
2221 int tc;
2222
2223 for (tc = 0; tc < c->priv->num_tc; tc++)
2224 mlx5e_close_sq_wait(&c->sq[tc]);
2225 }
2226
2227 static void
mlx5e_chan_static_init(struct mlx5e_priv * priv,struct mlx5e_channel * c,int ix)2228 mlx5e_chan_static_init(struct mlx5e_priv *priv, struct mlx5e_channel *c, int ix)
2229 {
2230 int tc;
2231
2232 /* setup priv and channel number */
2233 c->priv = priv;
2234 c->ix = ix;
2235
2236 /* setup send tag */
2237 m_snd_tag_init(&c->tag, c->priv->ifp, &mlx5e_ul_snd_tag_sw);
2238
2239 init_completion(&c->completion);
2240
2241 mtx_init(&c->rq.mtx, "mlx5rx", MTX_NETWORK_LOCK, MTX_DEF);
2242
2243 callout_init_mtx(&c->rq.watchdog, &c->rq.mtx, 0);
2244
2245 for (tc = 0; tc != MLX5E_MAX_TX_NUM_TC; tc++) {
2246 struct mlx5e_sq *sq = c->sq + tc;
2247
2248 mtx_init(&sq->lock, "mlx5tx",
2249 MTX_NETWORK_LOCK " TX", MTX_DEF);
2250 mtx_init(&sq->comp_lock, "mlx5comp",
2251 MTX_NETWORK_LOCK " TX", MTX_DEF);
2252
2253 callout_init_mtx(&sq->cev_callout, &sq->lock, 0);
2254 }
2255
2256 mlx5e_iq_static_init(&c->iq);
2257 }
2258
2259 static void
mlx5e_chan_wait_for_completion(struct mlx5e_channel * c)2260 mlx5e_chan_wait_for_completion(struct mlx5e_channel *c)
2261 {
2262
2263 m_snd_tag_rele(&c->tag);
2264 wait_for_completion(&c->completion);
2265 }
2266
2267 static void
mlx5e_priv_wait_for_completion(struct mlx5e_priv * priv,const uint32_t channels)2268 mlx5e_priv_wait_for_completion(struct mlx5e_priv *priv, const uint32_t channels)
2269 {
2270 uint32_t x;
2271
2272 for (x = 0; x != channels; x++)
2273 mlx5e_chan_wait_for_completion(&priv->channel[x]);
2274 }
2275
2276 static void
mlx5e_chan_static_destroy(struct mlx5e_channel * c)2277 mlx5e_chan_static_destroy(struct mlx5e_channel *c)
2278 {
2279 int tc;
2280
2281 callout_drain(&c->rq.watchdog);
2282
2283 mtx_destroy(&c->rq.mtx);
2284
2285 for (tc = 0; tc != MLX5E_MAX_TX_NUM_TC; tc++) {
2286 callout_drain(&c->sq[tc].cev_callout);
2287 mtx_destroy(&c->sq[tc].lock);
2288 mtx_destroy(&c->sq[tc].comp_lock);
2289 }
2290
2291 mlx5e_iq_static_destroy(&c->iq);
2292 }
2293
2294 static int
mlx5e_open_channel(struct mlx5e_priv * priv,struct mlx5e_channel_param * cparam,struct mlx5e_channel * c)2295 mlx5e_open_channel(struct mlx5e_priv *priv,
2296 struct mlx5e_channel_param *cparam,
2297 struct mlx5e_channel *c)
2298 {
2299 struct epoch_tracker et;
2300 int i, err;
2301
2302 /* zero non-persistent data */
2303 MLX5E_ZERO(&c->rq, mlx5e_rq_zero_start);
2304 for (i = 0; i != priv->num_tc; i++)
2305 MLX5E_ZERO(&c->sq[i], mlx5e_sq_zero_start);
2306 MLX5E_ZERO(&c->iq, mlx5e_iq_zero_start);
2307
2308 /* open transmit completion queue */
2309 err = mlx5e_open_tx_cqs(c, cparam);
2310 if (err)
2311 goto err_free;
2312
2313 /* open receive completion queue */
2314 err = mlx5e_open_cq(c->priv, &cparam->rx_cq, &c->rq.cq,
2315 &mlx5e_rx_cq_comp, c->ix);
2316 if (err)
2317 goto err_close_tx_cqs;
2318
2319 err = mlx5e_open_sqs(c, cparam);
2320 if (err)
2321 goto err_close_rx_cq;
2322
2323 err = mlx5e_iq_open(c, &cparam->sq, &cparam->tx_cq, &c->iq);
2324 if (err)
2325 goto err_close_sqs;
2326
2327 err = mlx5e_open_rq(c, &cparam->rq, &c->rq);
2328 if (err)
2329 goto err_close_iq;
2330
2331 /* poll receive queue initially */
2332 NET_EPOCH_ENTER(et);
2333 c->rq.cq.mcq.comp(&c->rq.cq.mcq, NULL);
2334 NET_EPOCH_EXIT(et);
2335
2336 return (0);
2337
2338 err_close_iq:
2339 mlx5e_iq_close(&c->iq);
2340
2341 err_close_sqs:
2342 mlx5e_close_sqs_wait(c);
2343
2344 err_close_rx_cq:
2345 mlx5e_close_cq(&c->rq.cq);
2346
2347 err_close_tx_cqs:
2348 mlx5e_close_tx_cqs(c);
2349
2350 err_free:
2351 return (err);
2352 }
2353
2354 static void
mlx5e_close_channel(struct mlx5e_channel * c)2355 mlx5e_close_channel(struct mlx5e_channel *c)
2356 {
2357 mlx5e_close_rq(&c->rq);
2358 }
2359
2360 static void
mlx5e_close_channel_wait(struct mlx5e_channel * c)2361 mlx5e_close_channel_wait(struct mlx5e_channel *c)
2362 {
2363 mlx5e_close_rq_wait(&c->rq);
2364 mlx5e_iq_close(&c->iq);
2365 mlx5e_close_sqs_wait(c);
2366 mlx5e_close_tx_cqs(c);
2367 }
2368
2369 static int
mlx5e_get_wqe_sz(struct mlx5e_priv * priv,u32 * wqe_sz,u32 * nsegs)2370 mlx5e_get_wqe_sz(struct mlx5e_priv *priv, u32 *wqe_sz, u32 *nsegs)
2371 {
2372 u32 r, n, maxs;
2373
2374 maxs = priv->params.hw_lro_en ? priv->params.lro_wqe_sz :
2375 MLX5E_SW2MB_MTU(if_getmtu(priv->ifp));
2376 r = maxs > MCLBYTES ? MJUMPAGESIZE : MCLBYTES;
2377
2378 /*
2379 * n + 1 must be a power of two, because stride size must be.
2380 * Stride size is 16 * (n + 1), as the first segment is
2381 * control.
2382 */
2383 n = roundup_pow_of_two(1 + howmany(maxs, r)) - 1;
2384 if (n > MLX5E_MAX_BUSDMA_RX_SEGS)
2385 return (-ENOMEM);
2386
2387 *wqe_sz = r;
2388 *nsegs = n;
2389 return (0);
2390 }
2391
2392 static void
mlx5e_build_rq_param(struct mlx5e_priv * priv,struct mlx5e_rq_param * param)2393 mlx5e_build_rq_param(struct mlx5e_priv *priv,
2394 struct mlx5e_rq_param *param)
2395 {
2396 void *rqc = param->rqc;
2397 void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
2398 u32 wqe_sz, nsegs;
2399
2400 mlx5e_get_wqe_sz(priv, &wqe_sz, &nsegs);
2401 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
2402 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
2403 MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe) +
2404 nsegs * sizeof(struct mlx5_wqe_data_seg)));
2405 MLX5_SET(wq, wq, log_wq_sz, priv->params.log_rq_size);
2406 MLX5_SET(wq, wq, pd, priv->pdn);
2407
2408 param->wq.linear = 1;
2409 }
2410
2411 static void
mlx5e_build_sq_param(struct mlx5e_priv * priv,struct mlx5e_sq_param * param)2412 mlx5e_build_sq_param(struct mlx5e_priv *priv,
2413 struct mlx5e_sq_param *param)
2414 {
2415 void *sqc = param->sqc;
2416 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2417
2418 MLX5_SET(wq, wq, log_wq_sz, priv->params.log_sq_size);
2419 MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
2420 MLX5_SET(wq, wq, pd, priv->pdn);
2421
2422 param->wq.linear = 1;
2423 }
2424
2425 static void
mlx5e_build_common_cq_param(struct mlx5e_priv * priv,struct mlx5e_cq_param * param)2426 mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
2427 struct mlx5e_cq_param *param)
2428 {
2429 void *cqc = param->cqc;
2430
2431 MLX5_SET(cqc, cqc, uar_page, priv->mdev->priv.uar->index);
2432 }
2433
2434 static void
mlx5e_get_default_profile(struct mlx5e_priv * priv,int mode,struct net_dim_cq_moder * ptr)2435 mlx5e_get_default_profile(struct mlx5e_priv *priv, int mode, struct net_dim_cq_moder *ptr)
2436 {
2437
2438 *ptr = net_dim_get_profile(mode, MLX5E_DIM_DEFAULT_PROFILE);
2439
2440 /* apply LRO restrictions */
2441 if (priv->params.hw_lro_en &&
2442 ptr->pkts > MLX5E_DIM_MAX_RX_CQ_MODERATION_PKTS_WITH_LRO) {
2443 ptr->pkts = MLX5E_DIM_MAX_RX_CQ_MODERATION_PKTS_WITH_LRO;
2444 }
2445 }
2446
2447 static void
mlx5e_build_rx_cq_param(struct mlx5e_priv * priv,struct mlx5e_cq_param * param)2448 mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
2449 struct mlx5e_cq_param *param)
2450 {
2451 struct net_dim_cq_moder curr;
2452 void *cqc = param->cqc;
2453
2454 /*
2455 * We use MLX5_CQE_FORMAT_HASH because the RX hash mini CQE
2456 * format is more beneficial for FreeBSD use case.
2457 *
2458 * Adding support for MLX5_CQE_FORMAT_CSUM will require changes
2459 * in mlx5e_decompress_cqe.
2460 */
2461 if (priv->params.cqe_zipping_en) {
2462 MLX5_SET(cqc, cqc, mini_cqe_res_format, MLX5_CQE_FORMAT_HASH);
2463 MLX5_SET(cqc, cqc, cqe_compression_en, 1);
2464 }
2465
2466 MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_rq_size);
2467
2468 switch (priv->params.rx_cq_moderation_mode) {
2469 case 0:
2470 MLX5_SET(cqc, cqc, cq_period, priv->params.rx_cq_moderation_usec);
2471 MLX5_SET(cqc, cqc, cq_max_count, priv->params.rx_cq_moderation_pkts);
2472 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
2473 break;
2474 case 1:
2475 MLX5_SET(cqc, cqc, cq_period, priv->params.rx_cq_moderation_usec);
2476 MLX5_SET(cqc, cqc, cq_max_count, priv->params.rx_cq_moderation_pkts);
2477 if (MLX5_CAP_GEN(priv->mdev, cq_period_start_from_cqe))
2478 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
2479 else
2480 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
2481 break;
2482 case 2:
2483 mlx5e_get_default_profile(priv, NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE, &curr);
2484 MLX5_SET(cqc, cqc, cq_period, curr.usec);
2485 MLX5_SET(cqc, cqc, cq_max_count, curr.pkts);
2486 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
2487 break;
2488 case 3:
2489 mlx5e_get_default_profile(priv, NET_DIM_CQ_PERIOD_MODE_START_FROM_CQE, &curr);
2490 MLX5_SET(cqc, cqc, cq_period, curr.usec);
2491 MLX5_SET(cqc, cqc, cq_max_count, curr.pkts);
2492 if (MLX5_CAP_GEN(priv->mdev, cq_period_start_from_cqe))
2493 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
2494 else
2495 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
2496 break;
2497 default:
2498 break;
2499 }
2500
2501 mlx5e_dim_build_cq_param(priv, param);
2502
2503 mlx5e_build_common_cq_param(priv, param);
2504 }
2505
2506 static void
mlx5e_build_tx_cq_param(struct mlx5e_priv * priv,struct mlx5e_cq_param * param)2507 mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
2508 struct mlx5e_cq_param *param)
2509 {
2510 void *cqc = param->cqc;
2511
2512 MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_sq_size);
2513 MLX5_SET(cqc, cqc, cq_period, priv->params.tx_cq_moderation_usec);
2514 MLX5_SET(cqc, cqc, cq_max_count, priv->params.tx_cq_moderation_pkts);
2515
2516 switch (priv->params.tx_cq_moderation_mode) {
2517 case 0:
2518 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
2519 break;
2520 default:
2521 if (MLX5_CAP_GEN(priv->mdev, cq_period_start_from_cqe))
2522 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
2523 else
2524 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
2525 break;
2526 }
2527
2528 mlx5e_build_common_cq_param(priv, param);
2529 }
2530
2531 static void
mlx5e_build_channel_param(struct mlx5e_priv * priv,struct mlx5e_channel_param * cparam)2532 mlx5e_build_channel_param(struct mlx5e_priv *priv,
2533 struct mlx5e_channel_param *cparam)
2534 {
2535 memset(cparam, 0, sizeof(*cparam));
2536
2537 mlx5e_build_rq_param(priv, &cparam->rq);
2538 mlx5e_build_sq_param(priv, &cparam->sq);
2539 mlx5e_build_rx_cq_param(priv, &cparam->rx_cq);
2540 mlx5e_build_tx_cq_param(priv, &cparam->tx_cq);
2541 }
2542
2543 static int
mlx5e_open_channels(struct mlx5e_priv * priv)2544 mlx5e_open_channels(struct mlx5e_priv *priv)
2545 {
2546 struct mlx5e_channel_param *cparam;
2547 int err;
2548 int i;
2549
2550 cparam = malloc(sizeof(*cparam), M_MLX5EN, M_WAITOK);
2551
2552 mlx5e_build_channel_param(priv, cparam);
2553 for (i = 0; i < priv->params.num_channels; i++) {
2554 err = mlx5e_open_channel(priv, cparam, &priv->channel[i]);
2555 if (err)
2556 goto err_close_channels;
2557
2558 /* Bind interrupt vectors, if any. */
2559 if (priv->params_ethtool.irq_cpu_base > -1) {
2560 cpuset_t cpuset;
2561 int cpu;
2562 int irq;
2563 int eqn;
2564 int nirq;
2565
2566 err = mlx5_vector2eqn(priv->mdev, i,
2567 &eqn, &nirq);
2568
2569 /* error here is non-fatal */
2570 if (err != 0)
2571 continue;
2572
2573 irq = priv->mdev->priv.msix_arr[nirq].vector;
2574 cpu = (unsigned)(priv->params_ethtool.irq_cpu_base +
2575 i * priv->params_ethtool.irq_cpu_stride) % (unsigned)mp_ncpus;
2576
2577 CPU_ZERO(&cpuset);
2578 CPU_SET(cpu, &cpuset);
2579 intr_setaffinity(irq, CPU_WHICH_INTRHANDLER, &cpuset);
2580 }
2581 }
2582 free(cparam, M_MLX5EN);
2583 return (0);
2584
2585 err_close_channels:
2586 while (i--) {
2587 mlx5e_close_channel(&priv->channel[i]);
2588 mlx5e_close_channel_wait(&priv->channel[i]);
2589 }
2590 free(cparam, M_MLX5EN);
2591 return (err);
2592 }
2593
2594 static void
mlx5e_close_channels(struct mlx5e_priv * priv)2595 mlx5e_close_channels(struct mlx5e_priv *priv)
2596 {
2597 int i;
2598
2599 for (i = 0; i < priv->params.num_channels; i++)
2600 mlx5e_close_channel(&priv->channel[i]);
2601 for (i = 0; i < priv->params.num_channels; i++)
2602 mlx5e_close_channel_wait(&priv->channel[i]);
2603 }
2604
2605 static int
mlx5e_refresh_sq_params(struct mlx5e_priv * priv,struct mlx5e_sq * sq)2606 mlx5e_refresh_sq_params(struct mlx5e_priv *priv, struct mlx5e_sq *sq)
2607 {
2608
2609 if (MLX5_CAP_GEN(priv->mdev, cq_period_mode_modify)) {
2610 uint8_t cq_mode;
2611
2612 switch (priv->params.tx_cq_moderation_mode) {
2613 case 0:
2614 case 2:
2615 cq_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
2616 break;
2617 default:
2618 cq_mode = MLX5_CQ_PERIOD_MODE_START_FROM_CQE;
2619 break;
2620 }
2621
2622 return (mlx5_core_modify_cq_moderation_mode(priv->mdev, &sq->cq.mcq,
2623 priv->params.tx_cq_moderation_usec,
2624 priv->params.tx_cq_moderation_pkts,
2625 cq_mode));
2626 }
2627
2628 return (mlx5_core_modify_cq_moderation(priv->mdev, &sq->cq.mcq,
2629 priv->params.tx_cq_moderation_usec,
2630 priv->params.tx_cq_moderation_pkts));
2631 }
2632
2633 static int
mlx5e_refresh_rq_params(struct mlx5e_priv * priv,struct mlx5e_rq * rq)2634 mlx5e_refresh_rq_params(struct mlx5e_priv *priv, struct mlx5e_rq *rq)
2635 {
2636
2637 if (MLX5_CAP_GEN(priv->mdev, cq_period_mode_modify)) {
2638 uint8_t cq_mode;
2639 uint8_t dim_mode;
2640 int retval;
2641
2642 switch (priv->params.rx_cq_moderation_mode) {
2643 case 0:
2644 case 2:
2645 cq_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
2646 dim_mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE;
2647 break;
2648 default:
2649 cq_mode = MLX5_CQ_PERIOD_MODE_START_FROM_CQE;
2650 dim_mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_CQE;
2651 break;
2652 }
2653
2654 /* tear down dynamic interrupt moderation */
2655 mtx_lock(&rq->mtx);
2656 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_DISABLED;
2657 mtx_unlock(&rq->mtx);
2658
2659 /* wait for dynamic interrupt moderation work task, if any */
2660 cancel_work_sync(&rq->dim.work);
2661
2662 if (priv->params.rx_cq_moderation_mode >= 2) {
2663 struct net_dim_cq_moder curr;
2664
2665 mlx5e_get_default_profile(priv, dim_mode, &curr);
2666
2667 retval = mlx5_core_modify_cq_moderation_mode(priv->mdev, &rq->cq.mcq,
2668 curr.usec, curr.pkts, cq_mode);
2669
2670 /* set dynamic interrupt moderation mode and zero defaults */
2671 mtx_lock(&rq->mtx);
2672 rq->dim.mode = dim_mode;
2673 rq->dim.state = 0;
2674 rq->dim.profile_ix = MLX5E_DIM_DEFAULT_PROFILE;
2675 mtx_unlock(&rq->mtx);
2676 } else {
2677 retval = mlx5_core_modify_cq_moderation_mode(priv->mdev, &rq->cq.mcq,
2678 priv->params.rx_cq_moderation_usec,
2679 priv->params.rx_cq_moderation_pkts,
2680 cq_mode);
2681 }
2682 return (retval);
2683 }
2684
2685 return (mlx5_core_modify_cq_moderation(priv->mdev, &rq->cq.mcq,
2686 priv->params.rx_cq_moderation_usec,
2687 priv->params.rx_cq_moderation_pkts));
2688 }
2689
2690 static int
mlx5e_refresh_channel_params_sub(struct mlx5e_priv * priv,struct mlx5e_channel * c)2691 mlx5e_refresh_channel_params_sub(struct mlx5e_priv *priv, struct mlx5e_channel *c)
2692 {
2693 int err;
2694 int i;
2695
2696 err = mlx5e_refresh_rq_params(priv, &c->rq);
2697 if (err)
2698 goto done;
2699
2700 for (i = 0; i != priv->num_tc; i++) {
2701 err = mlx5e_refresh_sq_params(priv, &c->sq[i]);
2702 if (err)
2703 goto done;
2704 }
2705 done:
2706 return (err);
2707 }
2708
2709 int
mlx5e_refresh_channel_params(struct mlx5e_priv * priv)2710 mlx5e_refresh_channel_params(struct mlx5e_priv *priv)
2711 {
2712 int i;
2713
2714 /* check if channels are closed */
2715 if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
2716 return (EINVAL);
2717
2718 for (i = 0; i < priv->params.num_channels; i++) {
2719 int err;
2720
2721 err = mlx5e_refresh_channel_params_sub(priv, &priv->channel[i]);
2722 if (err)
2723 return (err);
2724 }
2725 return (0);
2726 }
2727
2728 static int
mlx5e_open_tis(struct mlx5e_priv * priv,int tc)2729 mlx5e_open_tis(struct mlx5e_priv *priv, int tc)
2730 {
2731 struct mlx5_core_dev *mdev = priv->mdev;
2732 u32 in[MLX5_ST_SZ_DW(create_tis_in)];
2733 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
2734
2735 memset(in, 0, sizeof(in));
2736
2737 MLX5_SET(tisc, tisc, prio, tc);
2738 MLX5_SET(tisc, tisc, transport_domain, priv->tdn);
2739
2740 return (mlx5_core_create_tis(mdev, in, sizeof(in), &priv->tisn[tc]));
2741 }
2742
2743 static void
mlx5e_close_tis(struct mlx5e_priv * priv,int tc)2744 mlx5e_close_tis(struct mlx5e_priv *priv, int tc)
2745 {
2746 mlx5_core_destroy_tis(priv->mdev, priv->tisn[tc], 0);
2747 }
2748
2749 static int
mlx5e_open_tises(struct mlx5e_priv * priv)2750 mlx5e_open_tises(struct mlx5e_priv *priv)
2751 {
2752 int num_tc = priv->num_tc;
2753 int err;
2754 int tc;
2755
2756 for (tc = 0; tc < num_tc; tc++) {
2757 err = mlx5e_open_tis(priv, tc);
2758 if (err)
2759 goto err_close_tises;
2760 }
2761
2762 return (0);
2763
2764 err_close_tises:
2765 for (tc--; tc >= 0; tc--)
2766 mlx5e_close_tis(priv, tc);
2767
2768 return (err);
2769 }
2770
2771 static void
mlx5e_close_tises(struct mlx5e_priv * priv)2772 mlx5e_close_tises(struct mlx5e_priv *priv)
2773 {
2774 int num_tc = priv->num_tc;
2775 int tc;
2776
2777 for (tc = 0; tc < num_tc; tc++)
2778 mlx5e_close_tis(priv, tc);
2779 }
2780
2781 static int
mlx5e_open_default_rqt(struct mlx5e_priv * priv,u32 * prqtn,int sz)2782 mlx5e_open_default_rqt(struct mlx5e_priv *priv, u32 *prqtn, int sz)
2783 {
2784 u32 *in;
2785 void *rqtc;
2786 int inlen;
2787 int err;
2788 int i;
2789
2790 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
2791 in = mlx5_vzalloc(inlen);
2792 if (in == NULL)
2793 return (-ENOMEM);
2794 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
2795
2796 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
2797 MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
2798
2799 for (i = 0; i != sz; i++)
2800 MLX5_SET(rqtc, rqtc, rq_num[i], priv->drop_rq.rqn);
2801
2802 err = mlx5_core_create_rqt(priv->mdev, in, inlen, prqtn);
2803 kvfree(in);
2804
2805 return (err);
2806 }
2807
2808 static int
mlx5e_open_rqts(struct mlx5e_priv * priv)2809 mlx5e_open_rqts(struct mlx5e_priv *priv)
2810 {
2811 int err;
2812 int i;
2813
2814 err = mlx5e_open_default_rqt(priv, &priv->rqtn,
2815 1 << priv->params.rx_hash_log_tbl_sz);
2816 if (err)
2817 goto err_default;
2818
2819 for (i = 0; i != priv->mdev->priv.eq_table.num_comp_vectors; i++) {
2820 err = mlx5e_open_default_rqt(priv, &priv->channel[i].rqtn, 1);
2821 if (err)
2822 goto err_channel;
2823 }
2824 return (0);
2825
2826 err_channel:
2827 while (i--)
2828 mlx5_core_destroy_rqt(priv->mdev, priv->channel[i].rqtn, 0);
2829
2830 mlx5_core_destroy_rqt(priv->mdev, priv->rqtn, 0);
2831
2832 err_default:
2833 return (err);
2834 }
2835
2836 static void
mlx5e_close_rqts(struct mlx5e_priv * priv)2837 mlx5e_close_rqts(struct mlx5e_priv *priv)
2838 {
2839 int i;
2840
2841 for (i = 0; i != priv->mdev->priv.eq_table.num_comp_vectors; i++)
2842 mlx5_core_destroy_rqt(priv->mdev, priv->channel[i].rqtn, 0);
2843
2844 mlx5_core_destroy_rqt(priv->mdev, priv->rqtn, 0);
2845 }
2846
2847 static int
mlx5e_activate_rqt(struct mlx5e_priv * priv)2848 mlx5e_activate_rqt(struct mlx5e_priv *priv)
2849 {
2850 u32 *in;
2851 void *rqtc;
2852 int inlen;
2853 int err;
2854 int sz;
2855 int i;
2856
2857 sz = 1 << priv->params.rx_hash_log_tbl_sz;
2858
2859 inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32) * sz;
2860 in = mlx5_vzalloc(inlen);
2861 if (in == NULL)
2862 return (-ENOMEM);
2863
2864 rqtc = MLX5_ADDR_OF(modify_rqt_in, in, ctx);
2865
2866 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
2867 MLX5_SET(modify_rqt_in, in, bitmask.rqn_list, 1);
2868
2869 for (i = 0; i != sz; i++) {
2870 int ix;
2871 #ifdef RSS
2872 ix = rss_get_indirection_to_bucket(i);
2873 #else
2874 ix = i;
2875 #endif
2876 /* ensure we don't overflow */
2877 ix %= priv->params.num_channels;
2878
2879 /* apply receive side scaling stride, if any */
2880 ix -= ix % (int)priv->params.channels_rsss;
2881
2882 MLX5_SET(rqtc, rqtc, rq_num[i], priv->channel[ix].rq.rqn);
2883 }
2884
2885 err = mlx5_core_modify_rqt(priv->mdev, priv->rqtn, in, inlen);
2886 if (err)
2887 goto err_modify;
2888
2889 inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32);
2890
2891 MLX5_SET(rqtc, rqtc, rqt_actual_size, 1);
2892
2893 for (i = 0; i != priv->mdev->priv.eq_table.num_comp_vectors; i++) {
2894 int ix;
2895 #ifdef RSS
2896 ix = rss_get_indirection_to_bucket(i);
2897 #else
2898 ix = i;
2899 #endif
2900 /* ensure we don't overflow */
2901 ix %= priv->params.num_channels;
2902
2903 /* apply receive side scaling stride, if any */
2904 ix -= ix % (int)priv->params.channels_rsss;
2905
2906 MLX5_SET(rqtc, rqtc, rq_num[0], priv->channel[ix].rq.rqn);
2907
2908 err = mlx5_core_modify_rqt(priv->mdev, priv->channel[i].rqtn, in, inlen);
2909 if (err)
2910 goto err_modify;
2911 }
2912
2913 err_modify:
2914 kvfree(in);
2915 return (err);
2916 }
2917
2918 static int
mlx5e_deactivate_rqt(struct mlx5e_priv * priv)2919 mlx5e_deactivate_rqt(struct mlx5e_priv *priv)
2920 {
2921 u32 *in;
2922 void *rqtc;
2923 int inlen;
2924 int err;
2925 int sz;
2926 int i;
2927
2928 sz = 1 << priv->params.rx_hash_log_tbl_sz;
2929
2930 inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32) * sz;
2931 in = mlx5_vzalloc(inlen);
2932 if (in == NULL)
2933 return (-ENOMEM);
2934
2935 rqtc = MLX5_ADDR_OF(modify_rqt_in, in, ctx);
2936
2937 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
2938 MLX5_SET(modify_rqt_in, in, bitmask.rqn_list, 1);
2939
2940 for (i = 0; i != sz; i++)
2941 MLX5_SET(rqtc, rqtc, rq_num[i], priv->drop_rq.rqn);
2942
2943 err = mlx5_core_modify_rqt(priv->mdev, priv->rqtn, in, inlen);
2944 if (err)
2945 goto err_modify;
2946
2947 inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32);
2948
2949 MLX5_SET(rqtc, rqtc, rqt_actual_size, 1);
2950
2951 for (i = 0; i != priv->mdev->priv.eq_table.num_comp_vectors; i++) {
2952 MLX5_SET(rqtc, rqtc, rq_num[0], priv->drop_rq.rqn);
2953
2954 err = mlx5_core_modify_rqt(priv->mdev, priv->channel[i].rqtn, in, inlen);
2955 if (err)
2956 goto err_modify;
2957 }
2958
2959 err_modify:
2960 kvfree(in);
2961 return (err);
2962 }
2963
2964 #define MLX5E_RSS_KEY_SIZE (10 * 4) /* bytes */
2965
2966 static void
mlx5e_get_rss_key(void * key_ptr)2967 mlx5e_get_rss_key(void *key_ptr)
2968 {
2969 rss_getkey(key_ptr);
2970 }
2971
2972 static void
mlx5e_hw_lro_set_tir_ctx_lro_max_msg_sz(struct mlx5e_priv * priv,u32 * tirc)2973 mlx5e_hw_lro_set_tir_ctx_lro_max_msg_sz(struct mlx5e_priv *priv, u32 *tirc)
2974 {
2975 MLX5_SET(tirc, tirc, lro_max_msg_sz, (priv->params.lro_wqe_sz >> 8) -
2976 (MLX5_CAP_ETH(priv->mdev, lro_max_msg_sz_mode) == 0 ? 1 : 0));
2977 }
2978
2979 static void
mlx5e_hw_lro_set_tir_ctx(struct mlx5e_priv * priv,u32 * tirc)2980 mlx5e_hw_lro_set_tir_ctx(struct mlx5e_priv *priv, u32 *tirc)
2981 {
2982 MLX5_SET(tirc, tirc, lro_enable_mask,
2983 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
2984 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
2985 /* TODO: add the option to choose timer value dynamically */
2986 MLX5_SET(tirc, tirc, lro_timeout_period_usecs,
2987 MLX5_CAP_ETH(priv->mdev, lro_timer_supported_periods[2]));
2988 mlx5e_hw_lro_set_tir_ctx_lro_max_msg_sz(priv, tirc);
2989 }
2990
2991 static int
mlx5e_hw_lro_update_tir(struct mlx5e_priv * priv,int tt,bool inner_vxlan)2992 mlx5e_hw_lro_update_tir(struct mlx5e_priv *priv, int tt, bool inner_vxlan)
2993 {
2994 struct mlx5_core_dev *mdev = priv->mdev;
2995 u32 *in;
2996 void *tirc;
2997 int inlen;
2998 int err;
2999
3000 inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
3001 in = mlx5_vzalloc(inlen);
3002 if (in == NULL)
3003 return (-ENOMEM);
3004 tirc = MLX5_ADDR_OF(modify_tir_in, in, tir_context);
3005
3006 /* fill the command part */
3007 MLX5_SET(modify_tir_in, in, tirn, inner_vxlan ?
3008 priv->tirn_inner_vxlan[tt] : priv->tirn[tt]);
3009 MLX5_SET64(modify_tir_in, in, modify_bitmask,
3010 (1 << MLX5_MODIFY_TIR_BITMASK_LRO));
3011
3012 /* fill the context */
3013 if (priv->params.hw_lro_en)
3014 mlx5e_hw_lro_set_tir_ctx(priv, tirc);
3015
3016 err = mlx5_core_modify_tir(mdev, in, inlen);
3017
3018 kvfree(in);
3019 return (err);
3020 }
3021
3022 int
mlx5e_hw_lro_update_tirs(struct mlx5e_priv * priv)3023 mlx5e_hw_lro_update_tirs(struct mlx5e_priv *priv)
3024 {
3025 int err, err1, i;
3026
3027 err = 0;
3028 for (i = 0; i != 2 * MLX5E_NUM_TT; i++) {
3029 err1 = mlx5e_hw_lro_update_tir(priv, i / 2, (i % 2) ? true :
3030 false);
3031 if (err1 != 0 && err == 0)
3032 err = err1;
3033 }
3034 return (-err);
3035 }
3036
3037 static void
mlx5e_build_tir_ctx(struct mlx5e_priv * priv,u32 * tirc,int tt,bool inner_vxlan)3038 mlx5e_build_tir_ctx(struct mlx5e_priv *priv, u32 * tirc, int tt, bool inner_vxlan)
3039 {
3040 void *hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
3041 void *hfsi = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_inner);
3042 void *hfs = inner_vxlan ? hfsi : hfso;
3043 __be32 *hkey;
3044
3045 MLX5_SET(tirc, tirc, transport_domain, priv->tdn);
3046
3047 #define MLX5_HASH_IP (MLX5_HASH_FIELD_SEL_SRC_IP |\
3048 MLX5_HASH_FIELD_SEL_DST_IP)
3049
3050 #define MLX5_HASH_ALL (MLX5_HASH_FIELD_SEL_SRC_IP |\
3051 MLX5_HASH_FIELD_SEL_DST_IP |\
3052 MLX5_HASH_FIELD_SEL_L4_SPORT |\
3053 MLX5_HASH_FIELD_SEL_L4_DPORT)
3054
3055 #define MLX5_HASH_IP_IPSEC_SPI (MLX5_HASH_FIELD_SEL_SRC_IP |\
3056 MLX5_HASH_FIELD_SEL_DST_IP |\
3057 MLX5_HASH_FIELD_SEL_IPSEC_SPI)
3058
3059 if (priv->params.hw_lro_en)
3060 mlx5e_hw_lro_set_tir_ctx(priv, tirc);
3061
3062 if (inner_vxlan)
3063 MLX5_SET(tirc, tirc, tunneled_offload_en, 1);
3064
3065 /*
3066 * All packets must go through the indirection table, RQT,
3067 * because it is not possible to modify the RQN of the TIR
3068 * for direct dispatchment after it is created, typically
3069 * when the link goes up and down.
3070 */
3071 MLX5_SET(tirc, tirc, disp_type,
3072 MLX5_TIRC_DISP_TYPE_INDIRECT);
3073 MLX5_SET(tirc, tirc, indirect_table,
3074 priv->rqtn);
3075 MLX5_SET(tirc, tirc, rx_hash_fn,
3076 MLX5_TIRC_RX_HASH_FN_HASH_TOEPLITZ);
3077 hkey = (__be32 *) MLX5_ADDR_OF(tirc, tirc, rx_hash_toeplitz_key);
3078
3079 CTASSERT(MLX5_FLD_SZ_BYTES(tirc, rx_hash_toeplitz_key) >=
3080 MLX5E_RSS_KEY_SIZE);
3081
3082 /*
3083 * The FreeBSD RSS implementation does currently not
3084 * support symmetric Toeplitz hashes:
3085 */
3086 MLX5_SET(tirc, tirc, rx_hash_symmetric, 0);
3087 mlx5e_get_rss_key(hkey);
3088
3089 switch (tt) {
3090 case MLX5E_TT_IPV4_TCP:
3091 MLX5_SET(rx_hash_field_select, hfs, l3_prot_type,
3092 MLX5_L3_PROT_TYPE_IPV4);
3093 MLX5_SET(rx_hash_field_select, hfs, l4_prot_type,
3094 MLX5_L4_PROT_TYPE_TCP);
3095 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_TCP_IPV4)) {
3096 MLX5_SET(rx_hash_field_select, hfs, selected_fields,
3097 MLX5_HASH_IP);
3098 } else
3099 MLX5_SET(rx_hash_field_select, hfs, selected_fields,
3100 MLX5_HASH_ALL);
3101 break;
3102
3103 case MLX5E_TT_IPV6_TCP:
3104 MLX5_SET(rx_hash_field_select, hfs, l3_prot_type,
3105 MLX5_L3_PROT_TYPE_IPV6);
3106 MLX5_SET(rx_hash_field_select, hfs, l4_prot_type,
3107 MLX5_L4_PROT_TYPE_TCP);
3108 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_TCP_IPV6)) {
3109 MLX5_SET(rx_hash_field_select, hfs, selected_fields,
3110 MLX5_HASH_IP);
3111 } else
3112 MLX5_SET(rx_hash_field_select, hfs, selected_fields,
3113 MLX5_HASH_ALL);
3114 break;
3115
3116 case MLX5E_TT_IPV4_UDP:
3117 MLX5_SET(rx_hash_field_select, hfs, l3_prot_type,
3118 MLX5_L3_PROT_TYPE_IPV4);
3119 MLX5_SET(rx_hash_field_select, hfs, l4_prot_type,
3120 MLX5_L4_PROT_TYPE_UDP);
3121 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_UDP_IPV4)) {
3122 MLX5_SET(rx_hash_field_select, hfs, selected_fields,
3123 MLX5_HASH_IP);
3124 } else
3125 MLX5_SET(rx_hash_field_select, hfs, selected_fields,
3126 MLX5_HASH_ALL);
3127 break;
3128
3129 case MLX5E_TT_IPV6_UDP:
3130 MLX5_SET(rx_hash_field_select, hfs, l3_prot_type,
3131 MLX5_L3_PROT_TYPE_IPV6);
3132 MLX5_SET(rx_hash_field_select, hfs, l4_prot_type,
3133 MLX5_L4_PROT_TYPE_UDP);
3134 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_UDP_IPV6)) {
3135 MLX5_SET(rx_hash_field_select, hfs, selected_fields,
3136 MLX5_HASH_IP);
3137 } else
3138 MLX5_SET(rx_hash_field_select, hfs, selected_fields,
3139 MLX5_HASH_ALL);
3140 break;
3141
3142 case MLX5E_TT_IPV4_IPSEC_AH:
3143 MLX5_SET(rx_hash_field_select, hfs, l3_prot_type,
3144 MLX5_L3_PROT_TYPE_IPV4);
3145 MLX5_SET(rx_hash_field_select, hfs, selected_fields,
3146 MLX5_HASH_IP_IPSEC_SPI);
3147 break;
3148
3149 case MLX5E_TT_IPV6_IPSEC_AH:
3150 MLX5_SET(rx_hash_field_select, hfs, l3_prot_type,
3151 MLX5_L3_PROT_TYPE_IPV6);
3152 MLX5_SET(rx_hash_field_select, hfs, selected_fields,
3153 MLX5_HASH_IP_IPSEC_SPI);
3154 break;
3155
3156 case MLX5E_TT_IPV4_IPSEC_ESP:
3157 MLX5_SET(rx_hash_field_select, hfs, l3_prot_type,
3158 MLX5_L3_PROT_TYPE_IPV4);
3159 MLX5_SET(rx_hash_field_select, hfs, selected_fields,
3160 MLX5_HASH_IP_IPSEC_SPI);
3161 break;
3162
3163 case MLX5E_TT_IPV6_IPSEC_ESP:
3164 MLX5_SET(rx_hash_field_select, hfs, l3_prot_type,
3165 MLX5_L3_PROT_TYPE_IPV6);
3166 MLX5_SET(rx_hash_field_select, hfs, selected_fields,
3167 MLX5_HASH_IP_IPSEC_SPI);
3168 break;
3169
3170 case MLX5E_TT_IPV4:
3171 MLX5_SET(rx_hash_field_select, hfs, l3_prot_type,
3172 MLX5_L3_PROT_TYPE_IPV4);
3173 MLX5_SET(rx_hash_field_select, hfs, selected_fields,
3174 MLX5_HASH_IP);
3175 break;
3176
3177 case MLX5E_TT_IPV6:
3178 MLX5_SET(rx_hash_field_select, hfs, l3_prot_type,
3179 MLX5_L3_PROT_TYPE_IPV6);
3180 MLX5_SET(rx_hash_field_select, hfs, selected_fields,
3181 MLX5_HASH_IP);
3182 break;
3183
3184 default:
3185 break;
3186 }
3187 }
3188
3189 static int
mlx5e_open_tir(struct mlx5e_priv * priv,int tt,bool inner_vxlan)3190 mlx5e_open_tir(struct mlx5e_priv *priv, int tt, bool inner_vxlan)
3191 {
3192 struct mlx5_core_dev *mdev = priv->mdev;
3193 u32 *in;
3194 void *tirc;
3195 int inlen;
3196 int err;
3197
3198 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
3199 in = mlx5_vzalloc(inlen);
3200 if (in == NULL)
3201 return (-ENOMEM);
3202 tirc = MLX5_ADDR_OF(create_tir_in, in, tir_context);
3203
3204 mlx5e_build_tir_ctx(priv, tirc, tt, inner_vxlan);
3205
3206 err = mlx5_core_create_tir(mdev, in, inlen, inner_vxlan ?
3207 &priv->tirn_inner_vxlan[tt] : &priv->tirn[tt]);
3208
3209 kvfree(in);
3210
3211 return (err);
3212 }
3213
3214 static void
mlx5e_close_tir(struct mlx5e_priv * priv,int tt,bool inner_vxlan)3215 mlx5e_close_tir(struct mlx5e_priv *priv, int tt, bool inner_vxlan)
3216 {
3217 mlx5_core_destroy_tir(priv->mdev, inner_vxlan ?
3218 priv->tirn_inner_vxlan[tt] : priv->tirn[tt], 0);
3219 }
3220
3221 static int
mlx5e_open_tirs(struct mlx5e_priv * priv)3222 mlx5e_open_tirs(struct mlx5e_priv *priv)
3223 {
3224 int err;
3225 int i;
3226
3227 for (i = 0; i != 2 * MLX5E_NUM_TT; i++) {
3228 err = mlx5e_open_tir(priv, i / 2, (i % 2) ? true : false);
3229 if (err)
3230 goto err_close_tirs;
3231 }
3232
3233 return (0);
3234
3235 err_close_tirs:
3236 for (i--; i >= 0; i--)
3237 mlx5e_close_tir(priv, i / 2, (i % 2) ? true : false);
3238
3239 return (err);
3240 }
3241
3242 static void
mlx5e_close_tirs(struct mlx5e_priv * priv)3243 mlx5e_close_tirs(struct mlx5e_priv *priv)
3244 {
3245 int i;
3246
3247 for (i = 0; i != 2 * MLX5E_NUM_TT; i++)
3248 mlx5e_close_tir(priv, i / 2, (i % 2) ? true : false);
3249 }
3250
3251 /*
3252 * SW MTU does not include headers,
3253 * HW MTU includes all headers and checksums.
3254 */
3255 static int
mlx5e_set_dev_port_mtu(if_t ifp,int sw_mtu)3256 mlx5e_set_dev_port_mtu(if_t ifp, int sw_mtu)
3257 {
3258 struct mlx5e_priv *priv = if_getsoftc(ifp);
3259 struct mlx5_core_dev *mdev = priv->mdev;
3260 int hw_mtu;
3261 int err;
3262
3263 hw_mtu = MLX5E_SW2HW_MTU(sw_mtu);
3264
3265 err = mlx5_set_port_mtu(mdev, hw_mtu);
3266 if (err) {
3267 mlx5_en_err(ifp, "mlx5_set_port_mtu failed setting %d, err=%d\n",
3268 sw_mtu, err);
3269 return (err);
3270 }
3271
3272 /* Update vport context MTU */
3273 err = mlx5_set_vport_mtu(mdev, hw_mtu);
3274 if (err) {
3275 mlx5_en_err(ifp,
3276 "Failed updating vport context with MTU size, err=%d\n",
3277 err);
3278 }
3279
3280 if_setmtu(ifp, sw_mtu);
3281
3282 err = mlx5_query_vport_mtu(mdev, &hw_mtu);
3283 if (err || !hw_mtu) {
3284 /* fallback to port oper mtu */
3285 err = mlx5_query_port_oper_mtu(mdev, &hw_mtu);
3286 }
3287 if (err) {
3288 mlx5_en_err(ifp,
3289 "Query port MTU, after setting new MTU value, failed\n");
3290 return (err);
3291 } else if (MLX5E_HW2SW_MTU(hw_mtu) < sw_mtu) {
3292 err = -E2BIG,
3293 mlx5_en_err(ifp,
3294 "Port MTU %d is smaller than ifp mtu %d\n",
3295 hw_mtu, sw_mtu);
3296 } else if (MLX5E_HW2SW_MTU(hw_mtu) > sw_mtu) {
3297 err = -EINVAL;
3298 mlx5_en_err(ifp,
3299 "Port MTU %d is bigger than ifp mtu %d\n",
3300 hw_mtu, sw_mtu);
3301 }
3302 priv->params_ethtool.hw_mtu = hw_mtu;
3303
3304 /* compute MSB */
3305 while (hw_mtu & (hw_mtu - 1))
3306 hw_mtu &= (hw_mtu - 1);
3307 priv->params_ethtool.hw_mtu_msb = hw_mtu;
3308
3309 return (err);
3310 }
3311
3312 int
mlx5e_open_locked(if_t ifp)3313 mlx5e_open_locked(if_t ifp)
3314 {
3315 struct mlx5e_priv *priv = if_getsoftc(ifp);
3316 int err;
3317 u16 set_id;
3318
3319 /* check if already opened */
3320 if (test_bit(MLX5E_STATE_OPENED, &priv->state) != 0)
3321 return (0);
3322
3323 #ifdef RSS
3324 if (rss_getnumbuckets() > priv->params.num_channels) {
3325 mlx5_en_info(ifp,
3326 "NOTE: There are more RSS buckets(%u) than channels(%u) available\n",
3327 rss_getnumbuckets(), priv->params.num_channels);
3328 }
3329 #endif
3330 err = mlx5e_open_tises(priv);
3331 if (err) {
3332 mlx5_en_err(ifp, "mlx5e_open_tises failed, %d\n", err);
3333 return (err);
3334 }
3335 err = mlx5_vport_alloc_q_counter(priv->mdev,
3336 MLX5_INTERFACE_PROTOCOL_ETH, &set_id);
3337 if (err) {
3338 mlx5_en_err(priv->ifp,
3339 "mlx5_vport_alloc_q_counter failed: %d\n", err);
3340 goto err_close_tises;
3341 }
3342 /* store counter set ID */
3343 priv->counter_set_id = set_id;
3344
3345 err = mlx5e_open_channels(priv);
3346 if (err) {
3347 mlx5_en_err(ifp,
3348 "mlx5e_open_channels failed, %d\n", err);
3349 goto err_dalloc_q_counter;
3350 }
3351 err = mlx5e_activate_rqt(priv);
3352 if (err) {
3353 mlx5_en_err(ifp, "mlx5e_activate_rqt failed, %d\n", err);
3354 goto err_close_channels;
3355 }
3356
3357 set_bit(MLX5E_STATE_OPENED, &priv->state);
3358
3359 mlx5e_update_carrier(priv);
3360
3361 #ifdef KERN_TLS
3362 if ((if_getcapenable(ifp) & (IFCAP_TXTLS4 | IFCAP_TXTLS6)) != 0)
3363 mlx5e_tls_prealloc_tags(priv);
3364 #endif
3365
3366 return (0);
3367
3368 err_close_channels:
3369 mlx5e_close_channels(priv);
3370
3371 err_dalloc_q_counter:
3372 mlx5_vport_dealloc_q_counter(priv->mdev,
3373 MLX5_INTERFACE_PROTOCOL_ETH, priv->counter_set_id);
3374
3375 err_close_tises:
3376 mlx5e_close_tises(priv);
3377
3378 return (err);
3379 }
3380
3381 static void
mlx5e_open(void * arg)3382 mlx5e_open(void *arg)
3383 {
3384 struct mlx5e_priv *priv = arg;
3385
3386 PRIV_LOCK(priv);
3387 if (mlx5_set_port_status(priv->mdev, MLX5_PORT_UP))
3388 mlx5_en_err(priv->ifp,
3389 "Setting port status to up failed\n");
3390
3391 mlx5e_open_locked(priv->ifp);
3392 if_setdrvflagbits(priv->ifp, IFF_DRV_RUNNING, 0);
3393 PRIV_UNLOCK(priv);
3394 }
3395
3396 int
mlx5e_close_locked(if_t ifp)3397 mlx5e_close_locked(if_t ifp)
3398 {
3399 struct mlx5e_priv *priv = if_getsoftc(ifp);
3400
3401 /* check if already closed */
3402 if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
3403 return (0);
3404
3405 clear_bit(MLX5E_STATE_OPENED, &priv->state);
3406
3407 if_link_state_change(priv->ifp, LINK_STATE_DOWN);
3408
3409 mlx5e_deactivate_rqt(priv);
3410 mlx5e_close_channels(priv);
3411 mlx5_vport_dealloc_q_counter(priv->mdev,
3412 MLX5_INTERFACE_PROTOCOL_ETH, priv->counter_set_id);
3413 mlx5e_close_tises(priv);
3414
3415 return (0);
3416 }
3417
3418 static uint64_t
mlx5e_get_counter(if_t ifp,ift_counter cnt)3419 mlx5e_get_counter(if_t ifp, ift_counter cnt)
3420 {
3421 struct mlx5e_priv *priv = if_getsoftc(ifp);
3422 u64 retval;
3423
3424 /* PRIV_LOCK(priv); XXX not allowed */
3425 switch (cnt) {
3426 case IFCOUNTER_IPACKETS:
3427 retval = priv->stats.vport.rx_packets;
3428 break;
3429 case IFCOUNTER_IERRORS:
3430 retval = priv->stats.pport.in_range_len_errors +
3431 priv->stats.pport.out_of_range_len +
3432 priv->stats.pport.too_long_errors +
3433 priv->stats.pport.check_seq_err +
3434 priv->stats.pport.alignment_err;
3435 break;
3436 case IFCOUNTER_IQDROPS:
3437 retval = priv->stats.vport.rx_out_of_buffer;
3438 break;
3439 case IFCOUNTER_OPACKETS:
3440 retval = priv->stats.vport.tx_packets;
3441 break;
3442 case IFCOUNTER_OERRORS:
3443 retval = priv->stats.port_stats_debug.out_discards;
3444 break;
3445 case IFCOUNTER_IBYTES:
3446 retval = priv->stats.vport.rx_bytes;
3447 break;
3448 case IFCOUNTER_OBYTES:
3449 retval = priv->stats.vport.tx_bytes;
3450 break;
3451 case IFCOUNTER_IMCASTS:
3452 retval = priv->stats.vport.rx_multicast_packets;
3453 break;
3454 case IFCOUNTER_OMCASTS:
3455 retval = priv->stats.vport.tx_multicast_packets;
3456 break;
3457 case IFCOUNTER_OQDROPS:
3458 retval = priv->stats.vport.tx_queue_dropped;
3459 break;
3460 case IFCOUNTER_COLLISIONS:
3461 retval = priv->stats.pport.collisions;
3462 break;
3463 default:
3464 retval = if_get_counter_default(ifp, cnt);
3465 break;
3466 }
3467 /* PRIV_UNLOCK(priv); XXX not allowed */
3468 return (retval);
3469 }
3470
3471 static void
mlx5e_set_rx_mode(if_t ifp)3472 mlx5e_set_rx_mode(if_t ifp)
3473 {
3474 struct mlx5e_priv *priv = if_getsoftc(ifp);
3475
3476 queue_work(priv->wq, &priv->set_rx_mode_work);
3477 }
3478
3479 static bool
mlx5e_is_ipsec_capable(struct mlx5_core_dev * mdev)3480 mlx5e_is_ipsec_capable(struct mlx5_core_dev *mdev)
3481 {
3482 #ifdef IPSEC_OFFLOAD
3483 if ((mlx5_ipsec_device_caps(mdev) & MLX5_IPSEC_CAP_PACKET_OFFLOAD) != 0)
3484 return (true);
3485 #endif
3486 return (false);
3487 }
3488
3489 static bool
mlx5e_is_ratelimit_capable(struct mlx5_core_dev * mdev)3490 mlx5e_is_ratelimit_capable(struct mlx5_core_dev *mdev)
3491 {
3492 #ifdef RATELIMIT
3493 if (MLX5_CAP_GEN(mdev, qos) &&
3494 MLX5_CAP_QOS(mdev, packet_pacing))
3495 return (true);
3496 #endif
3497 return (false);
3498 }
3499
3500 static bool
mlx5e_is_tlstx_capable(struct mlx5_core_dev * mdev)3501 mlx5e_is_tlstx_capable(struct mlx5_core_dev *mdev)
3502 {
3503 #ifdef KERN_TLS
3504 if (MLX5_CAP_GEN(mdev, tls_tx) != 0 &&
3505 MLX5_CAP_GEN(mdev, log_max_dek) != 0)
3506 return (true);
3507 #endif
3508 return (false);
3509 }
3510
3511 static bool
mlx5e_is_tlsrx_capable(struct mlx5_core_dev * mdev)3512 mlx5e_is_tlsrx_capable(struct mlx5_core_dev *mdev)
3513 {
3514 #ifdef KERN_TLS
3515 if (MLX5_CAP_GEN(mdev, tls_rx) != 0 &&
3516 MLX5_CAP_GEN(mdev, log_max_dek) != 0 &&
3517 MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
3518 ft_field_support.outer_ip_version) != 0)
3519 return (true);
3520 #endif
3521 return (false);
3522 }
3523
3524 static int
mlx5e_ioctl(if_t ifp,u_long command,caddr_t data)3525 mlx5e_ioctl(if_t ifp, u_long command, caddr_t data)
3526 {
3527 struct mlx5e_priv *priv;
3528 struct ifreq *ifr;
3529 struct ifdownreason *ifdr;
3530 struct ifi2creq i2c;
3531 struct ifrsskey *ifrk;
3532 struct ifrsshash *ifrh;
3533 struct siocsifcapnv_driver_data *drv_ioctl_data, drv_ioctl_data_d;
3534 int error = 0;
3535 int mask;
3536 int size_read = 0;
3537 int module_status;
3538 int module_num;
3539 int max_mtu;
3540 uint8_t read_addr;
3541
3542 priv = if_getsoftc(ifp);
3543
3544 /* check if detaching */
3545 if (priv == NULL || priv->gone != 0)
3546 return (ENXIO);
3547
3548 switch (command) {
3549 case SIOCSIFMTU:
3550 ifr = (struct ifreq *)data;
3551
3552 PRIV_LOCK(priv);
3553 mlx5_query_port_max_mtu(priv->mdev, &max_mtu);
3554
3555 if (ifr->ifr_mtu >= MLX5E_MTU_MIN &&
3556 ifr->ifr_mtu <= MIN(MLX5E_MTU_MAX, max_mtu)) {
3557 int was_opened;
3558
3559 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
3560 if (was_opened)
3561 mlx5e_close_locked(ifp);
3562
3563 /* set new MTU */
3564 mlx5e_set_dev_port_mtu(ifp, ifr->ifr_mtu);
3565
3566 if (was_opened)
3567 mlx5e_open_locked(ifp);
3568 } else {
3569 error = EINVAL;
3570 mlx5_en_err(ifp,
3571 "Invalid MTU value. Min val: %d, Max val: %d\n",
3572 MLX5E_MTU_MIN, MIN(MLX5E_MTU_MAX, max_mtu));
3573 }
3574 PRIV_UNLOCK(priv);
3575 break;
3576 case SIOCSIFFLAGS:
3577 if ((if_getflags(ifp) & IFF_UP) &&
3578 (if_getdrvflags(ifp) & IFF_DRV_RUNNING)) {
3579 mlx5e_set_rx_mode(ifp);
3580 break;
3581 }
3582 PRIV_LOCK(priv);
3583 if (if_getflags(ifp) & IFF_UP) {
3584 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) {
3585 if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
3586 mlx5e_open_locked(ifp);
3587 if_setdrvflagbits(ifp, IFF_DRV_RUNNING, 0);
3588 mlx5_set_port_status(priv->mdev, MLX5_PORT_UP);
3589 }
3590 } else {
3591 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
3592 mlx5_set_port_status(priv->mdev,
3593 MLX5_PORT_DOWN);
3594 if (test_bit(MLX5E_STATE_OPENED, &priv->state) != 0)
3595 mlx5e_close_locked(ifp);
3596 mlx5e_update_carrier(priv);
3597 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
3598 }
3599 }
3600 PRIV_UNLOCK(priv);
3601 break;
3602 case SIOCADDMULTI:
3603 case SIOCDELMULTI:
3604 mlx5e_set_rx_mode(ifp);
3605 break;
3606 case SIOCSIFMEDIA:
3607 case SIOCGIFMEDIA:
3608 case SIOCGIFXMEDIA:
3609 ifr = (struct ifreq *)data;
3610 error = ifmedia_ioctl(ifp, ifr, &priv->media, command);
3611 break;
3612 case SIOCGIFCAPNV:
3613 error = 0;
3614 break;
3615 case SIOCSIFCAP:
3616 ifr = (struct ifreq *)data;
3617 drv_ioctl_data = &drv_ioctl_data_d;
3618 drv_ioctl_data->reqcap = ifr->ifr_reqcap;
3619 PRIV_LOCK(priv);
3620 drv_ioctl_data->reqcap2 = if_getcapenable2(ifp);
3621 drv_ioctl_data->nvcap = NULL;
3622 goto siocsifcap_driver;
3623 case SIOCSIFCAPNV:
3624 drv_ioctl_data = (struct siocsifcapnv_driver_data *)data;
3625 PRIV_LOCK(priv);
3626 siocsifcap_driver:
3627 if (!mlx5e_is_tlstx_capable(priv->mdev)) {
3628 drv_ioctl_data->reqcap &= ~(IFCAP_TXTLS4 |
3629 IFCAP_TXTLS6);
3630 }
3631 if (!mlx5e_is_tlsrx_capable(priv->mdev)) {
3632 drv_ioctl_data->reqcap2 &= ~(
3633 IFCAP2_BIT(IFCAP2_RXTLS4) |
3634 IFCAP2_BIT(IFCAP2_RXTLS6));
3635 }
3636 if (!mlx5e_is_ipsec_capable(priv->mdev)) {
3637 drv_ioctl_data->reqcap2 &=
3638 ~IFCAP2_BIT(IFCAP2_IPSEC_OFFLOAD);
3639 }
3640 if (!mlx5e_is_ratelimit_capable(priv->mdev)) {
3641 drv_ioctl_data->reqcap &= ~(IFCAP_TXTLS_RTLMT |
3642 IFCAP_TXRTLMT);
3643 }
3644
3645 mask = drv_ioctl_data->reqcap ^ if_getcapenable(ifp);
3646
3647 if (mask & IFCAP_TXCSUM) {
3648 if_togglecapenable(ifp, IFCAP_TXCSUM);
3649 if_togglehwassist(ifp, (CSUM_TCP | CSUM_UDP | CSUM_IP));
3650
3651 if (IFCAP_TSO4 & if_getcapenable(ifp) &&
3652 !(IFCAP_TXCSUM & if_getcapenable(ifp))) {
3653 mask &= ~IFCAP_TSO4;
3654 if_setcapenablebit(ifp, 0, IFCAP_TSO4);
3655 if_sethwassistbits(ifp, 0, CSUM_IP_TSO);
3656 mlx5_en_err(ifp,
3657 "tso4 disabled due to -txcsum.\n");
3658 }
3659 }
3660 if (mask & IFCAP_TXCSUM_IPV6) {
3661 if_togglecapenable(ifp, IFCAP_TXCSUM_IPV6);
3662 if_togglehwassist(ifp, (CSUM_UDP_IPV6 | CSUM_TCP_IPV6));
3663
3664 if (IFCAP_TSO6 & if_getcapenable(ifp) &&
3665 !(IFCAP_TXCSUM_IPV6 & if_getcapenable(ifp))) {
3666 mask &= ~IFCAP_TSO6;
3667 if_setcapenablebit(ifp, 0, IFCAP_TSO6);
3668 if_sethwassistbits(ifp, 0, CSUM_IP6_TSO);
3669 mlx5_en_err(ifp,
3670 "tso6 disabled due to -txcsum6.\n");
3671 }
3672 }
3673 if (mask & IFCAP_MEXTPG)
3674 if_togglecapenable(ifp, IFCAP_MEXTPG);
3675 if (mask & IFCAP_TXTLS4)
3676 if_togglecapenable(ifp, IFCAP_TXTLS4);
3677 if (mask & IFCAP_TXTLS6)
3678 if_togglecapenable(ifp, IFCAP_TXTLS6);
3679 #ifdef RATELIMIT
3680 if (mask & IFCAP_TXTLS_RTLMT)
3681 if_togglecapenable(ifp, IFCAP_TXTLS_RTLMT);
3682 #endif
3683 if (mask & IFCAP_RXCSUM)
3684 if_togglecapenable(ifp, IFCAP_RXCSUM);
3685 if (mask & IFCAP_RXCSUM_IPV6)
3686 if_togglecapenable(ifp, IFCAP_RXCSUM_IPV6);
3687 if (mask & IFCAP_TSO4) {
3688 if (!(IFCAP_TSO4 & if_getcapenable(ifp)) &&
3689 !(IFCAP_TXCSUM & if_getcapenable(ifp))) {
3690 mlx5_en_err(ifp, "enable txcsum first.\n");
3691 error = EAGAIN;
3692 goto out;
3693 }
3694 if_togglecapenable(ifp, IFCAP_TSO4);
3695 if_togglehwassist(ifp, CSUM_IP_TSO);
3696 }
3697 if (mask & IFCAP_TSO6) {
3698 if (!(IFCAP_TSO6 & if_getcapenable(ifp)) &&
3699 !(IFCAP_TXCSUM_IPV6 & if_getcapenable(ifp))) {
3700 mlx5_en_err(ifp, "enable txcsum6 first.\n");
3701 error = EAGAIN;
3702 goto out;
3703 }
3704 if_togglecapenable(ifp, IFCAP_TSO6);
3705 if_togglehwassist(ifp, CSUM_IP6_TSO);
3706 }
3707 if (mask & IFCAP_VLAN_HWTSO)
3708 if_togglecapenable(ifp, IFCAP_VLAN_HWTSO);
3709 if (mask & IFCAP_VLAN_HWFILTER) {
3710 if (if_getcapenable(ifp) & IFCAP_VLAN_HWFILTER)
3711 mlx5e_disable_vlan_filter(priv);
3712 else
3713 mlx5e_enable_vlan_filter(priv);
3714
3715 if_togglecapenable(ifp, IFCAP_VLAN_HWFILTER);
3716 }
3717 if (mask & IFCAP_VLAN_HWTAGGING)
3718 if_togglecapenable(ifp, IFCAP_VLAN_HWTAGGING);
3719 if (mask & IFCAP_WOL_MAGIC)
3720 if_togglecapenable(ifp, IFCAP_WOL_MAGIC);
3721 if (mask & IFCAP_VXLAN_HWCSUM) {
3722 const bool was_enabled =
3723 (if_getcapenable(ifp) & IFCAP_VXLAN_HWCSUM) != 0;
3724 if (was_enabled)
3725 mlx5e_del_all_vxlan_rules(priv);
3726 if_togglecapenable(ifp, IFCAP_VXLAN_HWCSUM);
3727 if_togglehwassist(ifp, CSUM_INNER_IP | CSUM_INNER_IP_UDP |
3728 CSUM_INNER_IP_TCP | CSUM_INNER_IP6_UDP |
3729 CSUM_INNER_IP6_TCP);
3730 if (!was_enabled) {
3731 int err = mlx5e_add_all_vxlan_rules(priv);
3732 if (err != 0) {
3733 mlx5_en_err(ifp,
3734 "mlx5e_add_all_vxlan_rules() failed, %d (ignored)\n", err);
3735 }
3736 }
3737 }
3738 if (mask & IFCAP_VXLAN_HWTSO) {
3739 if_togglecapenable(ifp, IFCAP_VXLAN_HWTSO);
3740 if_togglehwassist(ifp, CSUM_INNER_IP_TSO |
3741 CSUM_INNER_IP6_TSO);
3742 }
3743
3744 VLAN_CAPABILITIES(ifp);
3745
3746 /* hw_lro and IFCAP_LRO are divorsed, only toggle sw LRO. */
3747 if (mask & IFCAP_LRO)
3748 if_togglecapenable(ifp, IFCAP_LRO);
3749
3750 if (mask & IFCAP_HWRXTSTMP) {
3751 if_togglecapenable(ifp, IFCAP_HWRXTSTMP);
3752 if (if_getcapenable(ifp) & IFCAP_HWRXTSTMP) {
3753 if (priv->clbr_done == 0)
3754 mlx5e_reset_calibration_callout(priv);
3755 } else {
3756 callout_drain(&priv->tstmp_clbr);
3757 priv->clbr_done = 0;
3758 }
3759 }
3760 mask = drv_ioctl_data->reqcap2 ^ if_getcapenable2(ifp);
3761 if ((mask & IFCAP2_BIT(IFCAP2_RXTLS4)) != 0)
3762 if_togglecapenable2(ifp, IFCAP2_BIT(IFCAP2_RXTLS4));
3763 if ((mask & IFCAP2_BIT(IFCAP2_RXTLS6)) != 0)
3764 if_togglecapenable2(ifp, IFCAP2_BIT(IFCAP2_RXTLS6));
3765 #ifdef IPSEC_OFFLOAD
3766 if ((mask & IFCAP2_BIT(IFCAP2_IPSEC_OFFLOAD)) != 0) {
3767 bool was_enabled = (if_getcapenable2(ifp) &
3768 IFCAP2_BIT(IFCAP2_IPSEC_OFFLOAD)) != 0;
3769 mlx5e_close_locked(ifp);
3770 if (was_enabled)
3771 ipsec_accel_on_ifdown(priv->ifp);
3772 if_togglecapenable2(ifp,
3773 IFCAP2_BIT(IFCAP2_IPSEC_OFFLOAD));
3774 mlx5e_open_locked(ifp);
3775 }
3776 #endif
3777 out:
3778 PRIV_UNLOCK(priv);
3779 break;
3780
3781 case SIOCGI2C:
3782 /* fallthru */
3783 case SIOCGI2CPB:
3784 ifr = (struct ifreq *)data;
3785
3786 /*
3787 * Copy from the user-space address ifr_data to the
3788 * kernel-space address i2c
3789 */
3790 error = copyin(ifr_data_get_ptr(ifr), &i2c, sizeof(i2c));
3791 if (error)
3792 break;
3793 /* ensure page and bank are 0 for legacy SIOCGI2C ioctls */
3794 if (command == SIOCGI2C)
3795 i2c.page = i2c.bank = 0;
3796
3797 if (i2c.len > sizeof(i2c.data)) {
3798 error = EINVAL;
3799 break;
3800 }
3801
3802 PRIV_LOCK(priv);
3803 /* Get module_num which is required for the query_eeprom */
3804 error = mlx5_query_module_num(priv->mdev, &module_num);
3805 if (error) {
3806 mlx5_en_err(ifp,
3807 "Query module num failed, eeprom reading is not supported\n");
3808 error = EINVAL;
3809 goto err_i2c;
3810 }
3811 /* Check if module is present before doing an access */
3812 module_status = mlx5_query_module_status(priv->mdev, module_num);
3813 if (module_status != MLX5_MODULE_STATUS_PLUGGED_ENABLED) {
3814 if (bootverbose)
3815 mlx5_en_err(ifp,
3816 "Query module %d status: not plugged (%d), "
3817 "eeprom reading is not supported\n",
3818 module_num, module_status);
3819 error = EINVAL;
3820 goto err_i2c;
3821 }
3822 /*
3823 * Currently 0XA0 and 0xA2 are the only addresses permitted.
3824 * The internal conversion is as follows:
3825 */
3826 if (i2c.dev_addr == 0xA0)
3827 read_addr = MLX5_I2C_ADDR_LOW;
3828 else if (i2c.dev_addr == 0xA2)
3829 read_addr = MLX5_I2C_ADDR_HIGH;
3830 else {
3831 mlx5_en_err(ifp,
3832 "Query eeprom failed, Invalid Address: %X\n",
3833 i2c.dev_addr);
3834 error = EINVAL;
3835 goto err_i2c;
3836 }
3837
3838 if (i2c.bank != 0) {
3839 mlx5_en_err(ifp,
3840 "Query eeprom failed, Invalid Bank: %X\n",
3841 i2c.bank);
3842 error = EINVAL;
3843 goto err_i2c;
3844 }
3845
3846 error = mlx5_query_eeprom(priv->mdev,
3847 read_addr, i2c.page,
3848 (uint32_t)i2c.offset, (uint32_t)i2c.len, module_num,
3849 (uint32_t *)i2c.data, &size_read);
3850 if (error) {
3851 mlx5_en_err(ifp,
3852 "Query eeprom failed, eeprom reading is not supported\n");
3853 error = EINVAL;
3854 goto err_i2c;
3855 }
3856
3857 if (i2c.len > MLX5_EEPROM_MAX_BYTES) {
3858 error = mlx5_query_eeprom(priv->mdev,
3859 read_addr, i2c.page,
3860 (uint32_t)(i2c.offset + size_read),
3861 (uint32_t)(i2c.len - size_read), module_num,
3862 (uint32_t *)(i2c.data + size_read), &size_read);
3863 }
3864 if (error) {
3865 mlx5_en_err(ifp,
3866 "Query eeprom failed, eeprom reading is not supported\n");
3867 error = EINVAL;
3868 goto err_i2c;
3869 }
3870
3871 error = copyout(&i2c, ifr_data_get_ptr(ifr), sizeof(i2c));
3872 err_i2c:
3873 PRIV_UNLOCK(priv);
3874 break;
3875 case SIOCGIFDOWNREASON:
3876 ifdr = (struct ifdownreason *)data;
3877 bzero(ifdr->ifdr_msg, sizeof(ifdr->ifdr_msg));
3878 PRIV_LOCK(priv);
3879 error = -mlx5_query_pddr_troubleshooting_info(priv->mdev, NULL,
3880 ifdr->ifdr_msg, sizeof(ifdr->ifdr_msg));
3881 PRIV_UNLOCK(priv);
3882 if (error == 0)
3883 ifdr->ifdr_reason = IFDR_REASON_MSG;
3884 break;
3885
3886 case SIOCGIFRSSKEY:
3887 ifrk = (struct ifrsskey *)data;
3888 ifrk->ifrk_func = RSS_FUNC_TOEPLITZ;
3889 ifrk->ifrk_keylen = MLX5E_RSS_KEY_SIZE;
3890 CTASSERT(sizeof(ifrk->ifrk_key) >= MLX5E_RSS_KEY_SIZE);
3891 mlx5e_get_rss_key(ifrk->ifrk_key);
3892 break;
3893
3894 case SIOCGIFRSSHASH:
3895 ifrh = (struct ifrsshash *)data;
3896 ifrh->ifrh_func = RSS_FUNC_TOEPLITZ;
3897 ifrh->ifrh_types =
3898 RSS_TYPE_IPV4 |
3899 RSS_TYPE_TCP_IPV4 |
3900 RSS_TYPE_UDP_IPV4 |
3901 RSS_TYPE_IPV6 |
3902 RSS_TYPE_TCP_IPV6 |
3903 RSS_TYPE_UDP_IPV6;
3904 break;
3905
3906 default:
3907 error = ether_ioctl(ifp, command, data);
3908 break;
3909 }
3910 return (error);
3911 }
3912
3913 static int
mlx5e_check_required_hca_cap(struct mlx5_core_dev * mdev)3914 mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
3915 {
3916 /*
3917 * TODO: uncoment once FW really sets all these bits if
3918 * (!mdev->caps.eth.rss_ind_tbl_cap || !mdev->caps.eth.csum_cap ||
3919 * !mdev->caps.eth.max_lso_cap || !mdev->caps.eth.vlan_cap ||
3920 * !(mdev->caps.gen.flags & MLX5_DEV_CAP_FLAG_SCQE_BRK_MOD)) return
3921 * -ENOTSUPP;
3922 */
3923
3924 /* TODO: add more must-to-have features */
3925
3926 if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
3927 return (-ENODEV);
3928
3929 return (0);
3930 }
3931
3932 static u16
mlx5e_get_max_inline_cap(struct mlx5_core_dev * mdev)3933 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev)
3934 {
3935 const int min_size = ETHER_VLAN_ENCAP_LEN + ETHER_HDR_LEN;
3936 const int max_size = MLX5E_MAX_TX_INLINE;
3937 const int bf_buf_size =
3938 ((1U << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2U) -
3939 (sizeof(struct mlx5e_tx_wqe) - 2);
3940
3941 /* verify against driver limits */
3942 if (bf_buf_size > max_size)
3943 return (max_size);
3944 else if (bf_buf_size < min_size)
3945 return (min_size);
3946 else
3947 return (bf_buf_size);
3948 }
3949
3950 static int
mlx5e_build_ifp_priv(struct mlx5_core_dev * mdev,struct mlx5e_priv * priv,int num_comp_vectors)3951 mlx5e_build_ifp_priv(struct mlx5_core_dev *mdev,
3952 struct mlx5e_priv *priv,
3953 int num_comp_vectors)
3954 {
3955 int err;
3956
3957 /*
3958 * TODO: Consider link speed for setting "log_sq_size",
3959 * "log_rq_size" and "cq_moderation_xxx":
3960 */
3961 priv->params.log_sq_size =
3962 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
3963 priv->params.log_rq_size =
3964 MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
3965 priv->params.rx_cq_moderation_usec =
3966 MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ?
3967 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE :
3968 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
3969 priv->params.rx_cq_moderation_mode =
3970 MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ? 1 : 0;
3971 priv->params.rx_cq_moderation_pkts =
3972 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
3973 priv->params.tx_cq_moderation_usec =
3974 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
3975 priv->params.tx_cq_moderation_pkts =
3976 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
3977 priv->params.rx_hash_log_tbl_sz =
3978 (order_base_2(num_comp_vectors) >
3979 MLX5E_PARAMS_DEFAULT_RX_HASH_LOG_TBL_SZ) ?
3980 order_base_2(num_comp_vectors) :
3981 MLX5E_PARAMS_DEFAULT_RX_HASH_LOG_TBL_SZ;
3982 priv->params.num_tc = 1;
3983 priv->params.default_vlan_prio = 0;
3984 priv->counter_set_id = -1;
3985 priv->params.tx_max_inline = mlx5e_get_max_inline_cap(mdev);
3986
3987 err = mlx5_query_min_inline(mdev, &priv->params.tx_min_inline_mode);
3988 if (err)
3989 return (err);
3990
3991 /*
3992 * hw lro is currently defaulted to off. when it won't anymore we
3993 * will consider the HW capability: "!!MLX5_CAP_ETH(mdev, lro_cap)"
3994 */
3995 priv->params.hw_lro_en = false;
3996 priv->params.lro_wqe_sz = MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ;
3997
3998 /*
3999 * CQE zipping is off, because the per-packet 32-bit Toeplitz hash
4000 * is then not supported. The 32-bit Toeplitz hash is needed to
4001 * correctly demultiplex incoming traffic into the expected
4002 * network queues.
4003 */
4004 priv->params.cqe_zipping_en = false;
4005
4006 priv->mdev = mdev;
4007 priv->params.num_channels = num_comp_vectors;
4008 priv->params.channels_rsss = 1;
4009 priv->order_base_2_num_channels = order_base_2(num_comp_vectors);
4010 priv->queue_mapping_channel_mask =
4011 roundup_pow_of_two(num_comp_vectors) - 1;
4012 priv->num_tc = priv->params.num_tc;
4013 priv->default_vlan_prio = priv->params.default_vlan_prio;
4014
4015 INIT_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
4016 INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
4017 INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
4018
4019 return (0);
4020 }
4021
4022 static void
mlx5e_mkey_set_relaxed_ordering(struct mlx5_core_dev * mdev,void * mkc)4023 mlx5e_mkey_set_relaxed_ordering(struct mlx5_core_dev *mdev, void *mkc)
4024 {
4025 bool ro_pci_enable =
4026 pci_get_relaxed_ordering_enabled(mdev->pdev->dev.bsddev);
4027 bool ro_write = MLX5_CAP_GEN(mdev, relaxed_ordering_write);
4028 bool ro_read = MLX5_CAP_GEN(mdev, relaxed_ordering_read);
4029
4030 MLX5_SET(mkc, mkc, relaxed_ordering_read, ro_pci_enable && ro_read);
4031 MLX5_SET(mkc, mkc, relaxed_ordering_write, ro_pci_enable && ro_write);
4032 }
4033
4034 static int
mlx5e_create_mkey(struct mlx5e_priv * priv,u32 pdn,struct mlx5_core_mkey * mkey)4035 mlx5e_create_mkey(struct mlx5e_priv *priv, u32 pdn,
4036 struct mlx5_core_mkey *mkey)
4037 {
4038 if_t ifp = priv->ifp;
4039 struct mlx5_core_dev *mdev = priv->mdev;
4040 int inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
4041 void *mkc;
4042 u32 *in;
4043 int err;
4044
4045 in = mlx5_vzalloc(inlen);
4046 if (in == NULL) {
4047 mlx5_en_err(ifp, "failed to allocate inbox\n");
4048 return (-ENOMEM);
4049 }
4050
4051 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
4052 MLX5_SET(mkc, mkc, access_mode, MLX5_ACCESS_MODE_PA);
4053 MLX5_SET(mkc, mkc, umr_en, 1); /* used by HW TLS */
4054 MLX5_SET(mkc, mkc, lw, 1);
4055 MLX5_SET(mkc, mkc, lr, 1);
4056 mlx5e_mkey_set_relaxed_ordering(mdev, mkc);
4057 MLX5_SET(mkc, mkc, pd, pdn);
4058 MLX5_SET(mkc, mkc, length64, 1);
4059 MLX5_SET(mkc, mkc, qpn, 0xffffff);
4060
4061 err = mlx5_core_create_mkey(mdev, mkey, in, inlen);
4062 if (err)
4063 mlx5_en_err(ifp, "mlx5_core_create_mkey failed, %d\n",
4064 err);
4065
4066 kvfree(in);
4067 return (err);
4068 }
4069
4070 static const char *mlx5e_vport_stats_desc[] = {
4071 MLX5E_VPORT_STATS(MLX5E_STATS_DESC)
4072 };
4073
4074 static const char *mlx5e_pport_stats_desc[] = {
4075 MLX5E_PPORT_STATS(MLX5E_STATS_DESC)
4076 };
4077
4078 static int
mlx5e_priv_static_init(struct mlx5e_priv * priv,struct mlx5_core_dev * mdev,const uint32_t channels)4079 mlx5e_priv_static_init(struct mlx5e_priv *priv, struct mlx5_core_dev *mdev,
4080 const uint32_t channels)
4081 {
4082 uint32_t x;
4083 int err;
4084
4085 mtx_init(&priv->async_events_mtx, "mlx5async", MTX_NETWORK_LOCK, MTX_DEF);
4086 sx_init(&priv->state_lock, "mlx5state");
4087 callout_init_mtx(&priv->watchdog, &priv->async_events_mtx, 0);
4088 MLX5_INIT_DOORBELL_LOCK(&priv->doorbell_lock);
4089 for (x = 0; x != channels; x++)
4090 mlx5e_chan_static_init(priv, &priv->channel[x], x);
4091
4092 for (x = 0; x != channels; x++) {
4093 err = mlx5_alloc_bfreg(mdev, &priv->channel[x].bfreg, false, false);
4094 if (err)
4095 goto err_alloc_bfreg;
4096 }
4097 return (0);
4098
4099 err_alloc_bfreg:
4100 while (x--)
4101 mlx5_free_bfreg(mdev, &priv->channel[x].bfreg);
4102
4103 for (x = 0; x != channels; x++)
4104 mlx5e_chan_static_destroy(&priv->channel[x]);
4105 callout_drain(&priv->watchdog);
4106 mtx_destroy(&priv->async_events_mtx);
4107 sx_destroy(&priv->state_lock);
4108 return (err);
4109 }
4110
4111 static void
mlx5e_priv_static_destroy(struct mlx5e_priv * priv,struct mlx5_core_dev * mdev,const uint32_t channels)4112 mlx5e_priv_static_destroy(struct mlx5e_priv *priv, struct mlx5_core_dev *mdev,
4113 const uint32_t channels)
4114 {
4115 uint32_t x;
4116
4117 for (x = 0; x != channels; x++)
4118 mlx5_free_bfreg(mdev, &priv->channel[x].bfreg);
4119 for (x = 0; x != channels; x++)
4120 mlx5e_chan_static_destroy(&priv->channel[x]);
4121 callout_drain(&priv->watchdog);
4122 mtx_destroy(&priv->async_events_mtx);
4123 sx_destroy(&priv->state_lock);
4124 }
4125
4126 static int
sysctl_firmware(SYSCTL_HANDLER_ARGS)4127 sysctl_firmware(SYSCTL_HANDLER_ARGS)
4128 {
4129 /*
4130 * %d.%d%.d the string format.
4131 * fw_rev_{maj,min,sub} return u16, 2^16 = 65536.
4132 * We need at most 5 chars to store that.
4133 * It also has: two "." and NULL at the end, which means we need 18
4134 * (5*3 + 3) chars at most.
4135 */
4136 char fw[18];
4137 struct mlx5e_priv *priv = arg1;
4138 int error;
4139
4140 snprintf(fw, sizeof(fw), "%d.%d.%d", fw_rev_maj(priv->mdev), fw_rev_min(priv->mdev),
4141 fw_rev_sub(priv->mdev));
4142 error = sysctl_handle_string(oidp, fw, sizeof(fw), req);
4143 return (error);
4144 }
4145
4146 static void
mlx5e_disable_tx_dma(struct mlx5e_channel * ch)4147 mlx5e_disable_tx_dma(struct mlx5e_channel *ch)
4148 {
4149 int i;
4150
4151 for (i = 0; i < ch->priv->num_tc; i++)
4152 mlx5e_drain_sq(&ch->sq[i]);
4153 }
4154
4155 static void
mlx5e_reset_sq_doorbell_record(struct mlx5e_sq * sq)4156 mlx5e_reset_sq_doorbell_record(struct mlx5e_sq *sq)
4157 {
4158
4159 sq->doorbell.d32[0] = cpu_to_be32(MLX5_OPCODE_NOP);
4160 sq->doorbell.d32[1] = cpu_to_be32(sq->sqn << 8);
4161 mlx5e_tx_notify_hw(sq, true);
4162 }
4163
4164 void
mlx5e_resume_sq(struct mlx5e_sq * sq)4165 mlx5e_resume_sq(struct mlx5e_sq *sq)
4166 {
4167 int err;
4168
4169 /* check if already enabled */
4170 if (READ_ONCE(sq->running) != 0)
4171 return;
4172
4173 err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_ERR,
4174 MLX5_SQC_STATE_RST);
4175 if (err != 0) {
4176 mlx5_en_err(sq->ifp,
4177 "mlx5e_modify_sq() from ERR to RST failed: %d\n", err);
4178 }
4179
4180 sq->cc = 0;
4181 sq->pc = 0;
4182
4183 /* reset doorbell prior to moving from RST to RDY */
4184 mlx5e_reset_sq_doorbell_record(sq);
4185
4186 err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST,
4187 MLX5_SQC_STATE_RDY);
4188 if (err != 0) {
4189 mlx5_en_err(sq->ifp,
4190 "mlx5e_modify_sq() from RST to RDY failed: %d\n", err);
4191 }
4192
4193 sq->cev_next_state = MLX5E_CEV_STATE_INITIAL;
4194 WRITE_ONCE(sq->running, 1);
4195 }
4196
4197 static void
mlx5e_enable_tx_dma(struct mlx5e_channel * ch)4198 mlx5e_enable_tx_dma(struct mlx5e_channel *ch)
4199 {
4200 int i;
4201
4202 for (i = 0; i < ch->priv->num_tc; i++)
4203 mlx5e_resume_sq(&ch->sq[i]);
4204 }
4205
4206 static void
mlx5e_disable_rx_dma(struct mlx5e_channel * ch)4207 mlx5e_disable_rx_dma(struct mlx5e_channel *ch)
4208 {
4209 struct mlx5e_rq *rq = &ch->rq;
4210 struct epoch_tracker et;
4211 int err;
4212
4213 mtx_lock(&rq->mtx);
4214 rq->enabled = 0;
4215 callout_stop(&rq->watchdog);
4216 mtx_unlock(&rq->mtx);
4217
4218 err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_RDY, MLX5_RQC_STATE_ERR);
4219 if (err != 0) {
4220 mlx5_en_err(rq->ifp,
4221 "mlx5e_modify_rq() from RDY to RST failed: %d\n", err);
4222 }
4223
4224 while (!mlx5_wq_ll_is_empty(&rq->wq)) {
4225 msleep(1);
4226 NET_EPOCH_ENTER(et);
4227 rq->cq.mcq.comp(&rq->cq.mcq, NULL);
4228 NET_EPOCH_EXIT(et);
4229 }
4230
4231 /*
4232 * Transitioning into RST state will allow the FW to track less ERR state queues,
4233 * thus reducing the recv queue flushing time
4234 */
4235 err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_ERR, MLX5_RQC_STATE_RST);
4236 if (err != 0) {
4237 mlx5_en_err(rq->ifp,
4238 "mlx5e_modify_rq() from ERR to RST failed: %d\n", err);
4239 }
4240 }
4241
4242 static void
mlx5e_enable_rx_dma(struct mlx5e_channel * ch)4243 mlx5e_enable_rx_dma(struct mlx5e_channel *ch)
4244 {
4245 struct mlx5e_rq *rq = &ch->rq;
4246 struct epoch_tracker et;
4247 int err;
4248
4249 rq->wq.wqe_ctr = 0;
4250 mlx5_wq_ll_update_db_record(&rq->wq);
4251 err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
4252 if (err != 0) {
4253 mlx5_en_err(rq->ifp,
4254 "mlx5e_modify_rq() from RST to RDY failed: %d\n", err);
4255 }
4256
4257 rq->enabled = 1;
4258
4259 NET_EPOCH_ENTER(et);
4260 rq->cq.mcq.comp(&rq->cq.mcq, NULL);
4261 NET_EPOCH_EXIT(et);
4262 }
4263
4264 void
mlx5e_modify_tx_dma(struct mlx5e_priv * priv,uint8_t value)4265 mlx5e_modify_tx_dma(struct mlx5e_priv *priv, uint8_t value)
4266 {
4267 int i;
4268
4269 if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
4270 return;
4271
4272 for (i = 0; i < priv->params.num_channels; i++) {
4273 if (value)
4274 mlx5e_disable_tx_dma(&priv->channel[i]);
4275 else
4276 mlx5e_enable_tx_dma(&priv->channel[i]);
4277 }
4278 }
4279
4280 void
mlx5e_modify_rx_dma(struct mlx5e_priv * priv,uint8_t value)4281 mlx5e_modify_rx_dma(struct mlx5e_priv *priv, uint8_t value)
4282 {
4283 int i;
4284
4285 if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
4286 return;
4287
4288 for (i = 0; i < priv->params.num_channels; i++) {
4289 if (value)
4290 mlx5e_disable_rx_dma(&priv->channel[i]);
4291 else
4292 mlx5e_enable_rx_dma(&priv->channel[i]);
4293 }
4294 }
4295
4296 static void
mlx5e_add_hw_stats(struct mlx5e_priv * priv)4297 mlx5e_add_hw_stats(struct mlx5e_priv *priv)
4298 {
4299 SYSCTL_ADD_PROC(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_hw),
4300 OID_AUTO, "fw_version", CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE,
4301 priv, 0, sysctl_firmware, "A", "HCA firmware version");
4302
4303 SYSCTL_ADD_STRING(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_hw),
4304 OID_AUTO, "board_id", CTLFLAG_RD, priv->mdev->board_id, 0,
4305 "Board ID");
4306 }
4307
4308 static int
mlx5e_sysctl_tx_priority_flow_control(SYSCTL_HANDLER_ARGS)4309 mlx5e_sysctl_tx_priority_flow_control(SYSCTL_HANDLER_ARGS)
4310 {
4311 struct mlx5e_priv *priv = arg1;
4312 uint8_t temp[MLX5E_MAX_PRIORITY];
4313 uint32_t tx_pfc;
4314 int err;
4315 int i;
4316
4317 PRIV_LOCK(priv);
4318
4319 tx_pfc = priv->params.tx_priority_flow_control;
4320
4321 for (i = 0; i != MLX5E_MAX_PRIORITY; i++)
4322 temp[i] = (tx_pfc >> i) & 1;
4323
4324 err = SYSCTL_OUT(req, temp, MLX5E_MAX_PRIORITY);
4325 if (err || !req->newptr)
4326 goto done;
4327 err = SYSCTL_IN(req, temp, MLX5E_MAX_PRIORITY);
4328 if (err)
4329 goto done;
4330
4331 priv->params.tx_priority_flow_control = 0;
4332
4333 /* range check input value */
4334 for (i = 0; i != MLX5E_MAX_PRIORITY; i++) {
4335 if (temp[i] > 1) {
4336 err = ERANGE;
4337 goto done;
4338 }
4339 priv->params.tx_priority_flow_control |= (temp[i] << i);
4340 }
4341
4342 /* check if update is required */
4343 if (tx_pfc != priv->params.tx_priority_flow_control)
4344 err = -mlx5e_set_port_pfc(priv);
4345 done:
4346 if (err != 0)
4347 priv->params.tx_priority_flow_control= tx_pfc;
4348 PRIV_UNLOCK(priv);
4349
4350 return (err);
4351 }
4352
4353 static int
mlx5e_sysctl_rx_priority_flow_control(SYSCTL_HANDLER_ARGS)4354 mlx5e_sysctl_rx_priority_flow_control(SYSCTL_HANDLER_ARGS)
4355 {
4356 struct mlx5e_priv *priv = arg1;
4357 uint8_t temp[MLX5E_MAX_PRIORITY];
4358 uint32_t rx_pfc;
4359 int err;
4360 int i;
4361
4362 PRIV_LOCK(priv);
4363
4364 rx_pfc = priv->params.rx_priority_flow_control;
4365
4366 for (i = 0; i != MLX5E_MAX_PRIORITY; i++)
4367 temp[i] = (rx_pfc >> i) & 1;
4368
4369 err = SYSCTL_OUT(req, temp, MLX5E_MAX_PRIORITY);
4370 if (err || !req->newptr)
4371 goto done;
4372 err = SYSCTL_IN(req, temp, MLX5E_MAX_PRIORITY);
4373 if (err)
4374 goto done;
4375
4376 priv->params.rx_priority_flow_control = 0;
4377
4378 /* range check input value */
4379 for (i = 0; i != MLX5E_MAX_PRIORITY; i++) {
4380 if (temp[i] > 1) {
4381 err = ERANGE;
4382 goto done;
4383 }
4384 priv->params.rx_priority_flow_control |= (temp[i] << i);
4385 }
4386
4387 /* check if update is required */
4388 if (rx_pfc != priv->params.rx_priority_flow_control) {
4389 err = -mlx5e_set_port_pfc(priv);
4390 if (err == 0 && priv->sw_is_port_buf_owner)
4391 err = mlx5e_update_buf_lossy(priv);
4392 }
4393 done:
4394 if (err != 0)
4395 priv->params.rx_priority_flow_control= rx_pfc;
4396 PRIV_UNLOCK(priv);
4397
4398 return (err);
4399 }
4400
4401 static void
mlx5e_setup_pauseframes(struct mlx5e_priv * priv)4402 mlx5e_setup_pauseframes(struct mlx5e_priv *priv)
4403 {
4404 int error;
4405
4406 /* enable pauseframes by default */
4407 priv->params.tx_pauseframe_control = 1;
4408 priv->params.rx_pauseframe_control = 1;
4409
4410 /* disable ports flow control, PFC, by default */
4411 priv->params.tx_priority_flow_control = 0;
4412 priv->params.rx_priority_flow_control = 0;
4413
4414 /* register pauseframe SYSCTLs */
4415 SYSCTL_ADD_INT(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
4416 OID_AUTO, "tx_pauseframe_control", CTLFLAG_RDTUN,
4417 &priv->params.tx_pauseframe_control, 0,
4418 "Set to enable TX pause frames. Clear to disable.");
4419
4420 SYSCTL_ADD_INT(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
4421 OID_AUTO, "rx_pauseframe_control", CTLFLAG_RDTUN,
4422 &priv->params.rx_pauseframe_control, 0,
4423 "Set to enable RX pause frames. Clear to disable.");
4424
4425 /* register priority flow control, PFC, SYSCTLs */
4426 SYSCTL_ADD_PROC(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
4427 OID_AUTO, "tx_priority_flow_control", CTLTYPE_U8 | CTLFLAG_RWTUN |
4428 CTLFLAG_MPSAFE, priv, 0, &mlx5e_sysctl_tx_priority_flow_control, "CU",
4429 "Set to enable TX ports flow control frames for priorities 0..7. Clear to disable.");
4430
4431 SYSCTL_ADD_PROC(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
4432 OID_AUTO, "rx_priority_flow_control", CTLTYPE_U8 | CTLFLAG_RWTUN |
4433 CTLFLAG_MPSAFE, priv, 0, &mlx5e_sysctl_rx_priority_flow_control, "CU",
4434 "Set to enable RX ports flow control frames for priorities 0..7. Clear to disable.");
4435
4436 PRIV_LOCK(priv);
4437
4438 /* range check */
4439 priv->params.tx_pauseframe_control =
4440 priv->params.tx_pauseframe_control ? 1 : 0;
4441 priv->params.rx_pauseframe_control =
4442 priv->params.rx_pauseframe_control ? 1 : 0;
4443
4444 /* update firmware */
4445 error = mlx5e_set_port_pause_and_pfc(priv);
4446 if (error == -EINVAL) {
4447 mlx5_en_err(priv->ifp,
4448 "Global pauseframes must be disabled before enabling PFC.\n");
4449 priv->params.rx_priority_flow_control = 0;
4450 priv->params.tx_priority_flow_control = 0;
4451
4452 /* update firmware */
4453 (void) mlx5e_set_port_pause_and_pfc(priv);
4454 }
4455 PRIV_UNLOCK(priv);
4456 }
4457
4458 static int
mlx5e_ul_snd_tag_alloc(if_t ifp,union if_snd_tag_alloc_params * params,struct m_snd_tag ** ppmt)4459 mlx5e_ul_snd_tag_alloc(if_t ifp,
4460 union if_snd_tag_alloc_params *params,
4461 struct m_snd_tag **ppmt)
4462 {
4463 struct mlx5e_priv *priv;
4464 struct mlx5e_channel *pch;
4465
4466 priv = if_getsoftc(ifp);
4467
4468 if (unlikely(priv->gone || params->hdr.flowtype == M_HASHTYPE_NONE)) {
4469 return (EOPNOTSUPP);
4470 } else {
4471 /* keep this code synced with mlx5e_select_queue() */
4472 u32 ch = priv->params.num_channels;
4473 #ifdef RSS
4474 u32 temp;
4475
4476 if (rss_hash2bucket(params->hdr.flowid,
4477 params->hdr.flowtype, &temp) == 0)
4478 ch = temp % ch;
4479 else
4480 #endif
4481 ch = (params->hdr.flowid % 128) % ch;
4482
4483 /*
4484 * NOTE: The channels array is only freed at detach
4485 * and it safe to return a pointer to the send tag
4486 * inside the channels structure as long as we
4487 * reference the priv.
4488 */
4489 pch = priv->channel + ch;
4490
4491 /* check if send queue is not running */
4492 if (unlikely(pch->sq[0].running == 0))
4493 return (ENXIO);
4494 m_snd_tag_ref(&pch->tag);
4495 *ppmt = &pch->tag;
4496 return (0);
4497 }
4498 }
4499
4500 static int
mlx5e_ul_snd_tag_query(struct m_snd_tag * pmt,union if_snd_tag_query_params * params)4501 mlx5e_ul_snd_tag_query(struct m_snd_tag *pmt, union if_snd_tag_query_params *params)
4502 {
4503 struct mlx5e_channel *pch =
4504 container_of(pmt, struct mlx5e_channel, tag);
4505
4506 params->unlimited.max_rate = -1ULL;
4507 params->unlimited.queue_level = mlx5e_sq_queue_level(&pch->sq[0]);
4508 return (0);
4509 }
4510
4511 static void
mlx5e_ul_snd_tag_free(struct m_snd_tag * pmt)4512 mlx5e_ul_snd_tag_free(struct m_snd_tag *pmt)
4513 {
4514 struct mlx5e_channel *pch =
4515 container_of(pmt, struct mlx5e_channel, tag);
4516
4517 complete(&pch->completion);
4518 }
4519
4520 static int
mlx5e_snd_tag_alloc(if_t ifp,union if_snd_tag_alloc_params * params,struct m_snd_tag ** ppmt)4521 mlx5e_snd_tag_alloc(if_t ifp,
4522 union if_snd_tag_alloc_params *params,
4523 struct m_snd_tag **ppmt)
4524 {
4525
4526 switch (params->hdr.type) {
4527 #ifdef RATELIMIT
4528 case IF_SND_TAG_TYPE_RATE_LIMIT:
4529 return (mlx5e_rl_snd_tag_alloc(ifp, params, ppmt));
4530 #ifdef KERN_TLS
4531 case IF_SND_TAG_TYPE_TLS_RATE_LIMIT:
4532 return (mlx5e_tls_snd_tag_alloc(ifp, params, ppmt));
4533 #endif
4534 #endif
4535 case IF_SND_TAG_TYPE_UNLIMITED:
4536 return (mlx5e_ul_snd_tag_alloc(ifp, params, ppmt));
4537 #ifdef KERN_TLS
4538 case IF_SND_TAG_TYPE_TLS:
4539 return (mlx5e_tls_snd_tag_alloc(ifp, params, ppmt));
4540 case IF_SND_TAG_TYPE_TLS_RX:
4541 return (mlx5e_tls_rx_snd_tag_alloc(ifp, params, ppmt));
4542 #endif
4543 default:
4544 return (EOPNOTSUPP);
4545 }
4546 }
4547
4548 #ifdef RATELIMIT
4549 #define NUM_HDWR_RATES_MLX 13
4550 static const uint64_t adapter_rates_mlx[NUM_HDWR_RATES_MLX] = {
4551 135375, /* 1,083,000 */
4552 180500, /* 1,444,000 */
4553 270750, /* 2,166,000 */
4554 361000, /* 2,888,000 */
4555 541500, /* 4,332,000 */
4556 721875, /* 5,775,000 */
4557 1082875, /* 8,663,000 */
4558 1443875, /* 11,551,000 */
4559 2165750, /* 17,326,000 */
4560 2887750, /* 23,102,000 */
4561 4331625, /* 34,653,000 */
4562 5775500, /* 46,204,000 */
4563 8663125 /* 69,305,000 */
4564 };
4565
4566 static void
mlx5e_ratelimit_query(if_t ifp __unused,struct if_ratelimit_query_results * q)4567 mlx5e_ratelimit_query(if_t ifp __unused, struct if_ratelimit_query_results *q)
4568 {
4569 /*
4570 * This function needs updating by the driver maintainer!
4571 * For the MLX card there are currently (ConectX-4?) 13
4572 * pre-set rates and others i.e. ConnectX-5, 6, 7??
4573 *
4574 * This will change based on later adapters
4575 * and this code should be updated to look at ifp
4576 * and figure out the specific adapter type
4577 * settings i.e. how many rates as well
4578 * as if they are fixed (as is shown here) or
4579 * if they are dynamic (example chelsio t4). Also if there
4580 * is a maximum number of flows that the adapter
4581 * can handle that too needs to be updated in
4582 * the max_flows field.
4583 */
4584 q->rate_table = adapter_rates_mlx;
4585 q->flags = RT_IS_FIXED_TABLE;
4586 q->max_flows = 0; /* mlx has no limit */
4587 q->number_of_rates = NUM_HDWR_RATES_MLX;
4588 q->min_segment_burst = 1;
4589 }
4590 #endif
4591
4592 static void
mlx5e_ifm_add(struct mlx5e_priv * priv,int type)4593 mlx5e_ifm_add(struct mlx5e_priv *priv, int type)
4594 {
4595 ifmedia_add(&priv->media, type | IFM_ETHER, 0, NULL);
4596 ifmedia_add(&priv->media, type | IFM_ETHER |
4597 IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE, 0, NULL);
4598 ifmedia_add(&priv->media, type | IFM_ETHER | IFM_ETH_RXPAUSE, 0, NULL);
4599 ifmedia_add(&priv->media, type | IFM_ETHER | IFM_ETH_TXPAUSE, 0, NULL);
4600 ifmedia_add(&priv->media, type | IFM_ETHER | IFM_FDX, 0, NULL);
4601 ifmedia_add(&priv->media, type | IFM_ETHER | IFM_FDX |
4602 IFM_ETH_RXPAUSE, 0, NULL);
4603 ifmedia_add(&priv->media, type | IFM_ETHER | IFM_FDX |
4604 IFM_ETH_TXPAUSE, 0, NULL);
4605 ifmedia_add(&priv->media, type | IFM_ETHER | IFM_FDX |
4606 IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE, 0, NULL);
4607 }
4608
4609 static void *
mlx5e_create_ifp(struct mlx5_core_dev * mdev)4610 mlx5e_create_ifp(struct mlx5_core_dev *mdev)
4611 {
4612 if_t ifp;
4613 struct mlx5e_priv *priv;
4614 u8 dev_addr[ETHER_ADDR_LEN] __aligned(4);
4615 struct sysctl_oid_list *child;
4616 int ncv = mdev->priv.eq_table.num_comp_vectors;
4617 char unit[16];
4618 struct pfil_head_args pa;
4619 int err;
4620 u32 eth_proto_cap;
4621 u32 out[MLX5_ST_SZ_DW(ptys_reg)];
4622 bool ext;
4623 struct media media_entry = {};
4624
4625 if (mlx5e_check_required_hca_cap(mdev)) {
4626 mlx5_core_dbg(mdev, "mlx5e_check_required_hca_cap() failed\n");
4627 return (NULL);
4628 }
4629
4630 /*
4631 * Try to allocate the priv and make room for worst-case
4632 * number of channel structures:
4633 */
4634 priv = malloc_domainset(sizeof(*priv) +
4635 (sizeof(priv->channel[0]) * mdev->priv.eq_table.num_comp_vectors),
4636 M_MLX5EN, mlx5_dev_domainset(mdev), M_WAITOK | M_ZERO);
4637
4638 ifp = priv->ifp = if_alloc_dev(IFT_ETHER, mdev->pdev->dev.bsddev);
4639 /* setup all static fields */
4640 if (mlx5e_priv_static_init(priv, mdev, mdev->priv.eq_table.num_comp_vectors)) {
4641 mlx5_core_err(mdev, "mlx5e_priv_static_init() failed\n");
4642 goto err_free_ifp;
4643 }
4644
4645 if_setsoftc(ifp, priv);
4646 if_initname(ifp, "mce", device_get_unit(mdev->pdev->dev.bsddev));
4647 if_setmtu(ifp, ETHERMTU);
4648 if_setinitfn(ifp, mlx5e_open);
4649 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST);
4650 if_setioctlfn(ifp, mlx5e_ioctl);
4651 if_settransmitfn(ifp, mlx5e_xmit);
4652 if_setqflushfn(ifp, if_qflush);
4653 if_setgetcounterfn(ifp, mlx5e_get_counter);
4654 if_setsendqlen(ifp, ifqmaxlen);
4655 /*
4656 * Set driver features
4657 */
4658 if_setcapabilities(ifp, IFCAP_NV);
4659 if_setcapabilitiesbit(ifp, IFCAP_HWCSUM | IFCAP_HWCSUM_IPV6, 0);
4660 if_setcapabilitiesbit(ifp, IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING, 0);
4661 if_setcapabilitiesbit(ifp, IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWFILTER, 0);
4662 if_setcapabilitiesbit(ifp, IFCAP_LINKSTATE | IFCAP_JUMBO_MTU, 0);
4663 if_setcapabilitiesbit(ifp, IFCAP_LRO, 0);
4664 if_setcapabilitiesbit(ifp, IFCAP_TSO | IFCAP_VLAN_HWTSO, 0);
4665 if_setcapabilitiesbit(ifp, IFCAP_HWSTATS | IFCAP_HWRXTSTMP, 0);
4666 if_setcapabilitiesbit(ifp, IFCAP_MEXTPG, 0);
4667 if (mlx5e_is_tlstx_capable(mdev))
4668 if_setcapabilitiesbit(ifp, IFCAP_TXTLS4 | IFCAP_TXTLS6, 0);
4669 if (mlx5e_is_tlsrx_capable(mdev))
4670 if_setcapabilities2bit(ifp, IFCAP2_BIT(IFCAP2_RXTLS4) |
4671 IFCAP2_BIT(IFCAP2_RXTLS6), 0);
4672 if (mlx5e_is_ratelimit_capable(mdev)) {
4673 if_setcapabilitiesbit(ifp, IFCAP_TXRTLMT, 0);
4674 if (mlx5e_is_tlstx_capable(mdev))
4675 if_setcapabilitiesbit(ifp, IFCAP_TXTLS_RTLMT, 0);
4676 }
4677 if_setcapabilitiesbit(ifp, IFCAP_VXLAN_HWCSUM | IFCAP_VXLAN_HWTSO, 0);
4678 if (mlx5e_is_ipsec_capable(mdev))
4679 if_setcapabilities2bit(ifp, IFCAP2_BIT(IFCAP2_IPSEC_OFFLOAD),
4680 0);
4681
4682 if_setsndtagallocfn(ifp, mlx5e_snd_tag_alloc);
4683 #ifdef RATELIMIT
4684 if_setratelimitqueryfn(ifp, mlx5e_ratelimit_query);
4685 #endif
4686 /* set TSO limits so that we don't have to drop TX packets */
4687 if_sethwtsomax(ifp, MLX5E_MAX_TX_PAYLOAD_SIZE - (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN));
4688 if_sethwtsomaxsegcount(ifp, MLX5E_MAX_TX_MBUF_FRAGS - 1 /* hdr */);
4689 if_sethwtsomaxsegsize(ifp, MLX5E_MAX_TX_MBUF_SIZE);
4690
4691 if_setcapenable(ifp, if_getcapabilities(ifp));
4692 if_setcapenable2(ifp, if_getcapabilities2(ifp));
4693 if_sethwassist(ifp, 0);
4694 if (if_getcapenable(ifp) & IFCAP_TSO)
4695 if_sethwassistbits(ifp, CSUM_TSO, 0);
4696 if (if_getcapenable(ifp) & IFCAP_TXCSUM)
4697 if_sethwassistbits(ifp, (CSUM_TCP | CSUM_UDP | CSUM_IP), 0);
4698 if (if_getcapenable(ifp) & IFCAP_TXCSUM_IPV6)
4699 if_sethwassistbits(ifp, (CSUM_UDP_IPV6 | CSUM_TCP_IPV6), 0);
4700 if (if_getcapabilities(ifp) & IFCAP_VXLAN_HWCSUM)
4701 if_sethwassistbits(ifp, CSUM_INNER_IP6_UDP | CSUM_INNER_IP6_TCP |
4702 CSUM_INNER_IP | CSUM_INNER_IP_UDP | CSUM_INNER_IP_TCP |
4703 CSUM_ENCAP_VXLAN, 0);
4704 if (if_getcapabilities(ifp) & IFCAP_VXLAN_HWTSO)
4705 if_sethwassistbits(ifp, CSUM_INNER_IP6_TSO | CSUM_INNER_IP_TSO, 0);
4706
4707 /* ifnet sysctl tree */
4708 sysctl_ctx_init(&priv->sysctl_ctx);
4709 priv->sysctl_ifnet = SYSCTL_ADD_NODE(&priv->sysctl_ctx, SYSCTL_STATIC_CHILDREN(_dev),
4710 OID_AUTO, if_getdname(ifp), CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
4711 "MLX5 ethernet - interface name");
4712 if (priv->sysctl_ifnet == NULL) {
4713 mlx5_core_err(mdev, "SYSCTL_ADD_NODE() failed\n");
4714 goto err_free_sysctl;
4715 }
4716 snprintf(unit, sizeof(unit), "%d", if_getdunit(ifp));
4717 priv->sysctl_ifnet = SYSCTL_ADD_NODE(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
4718 OID_AUTO, unit, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
4719 "MLX5 ethernet - interface unit");
4720 if (priv->sysctl_ifnet == NULL) {
4721 mlx5_core_err(mdev, "SYSCTL_ADD_NODE() failed\n");
4722 goto err_free_sysctl;
4723 }
4724
4725 /* HW sysctl tree */
4726 child = SYSCTL_CHILDREN(device_get_sysctl_tree(mdev->pdev->dev.bsddev));
4727 priv->sysctl_hw = SYSCTL_ADD_NODE(&priv->sysctl_ctx, child,
4728 OID_AUTO, "hw", CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
4729 "MLX5 ethernet dev hw");
4730 if (priv->sysctl_hw == NULL) {
4731 mlx5_core_err(mdev, "SYSCTL_ADD_NODE() failed\n");
4732 goto err_free_sysctl;
4733 }
4734
4735 err = mlx5e_build_ifp_priv(mdev, priv, ncv);
4736 if (err) {
4737 mlx5_core_err(mdev, "mlx5e_build_ifp_priv() failed (%d)\n", err);
4738 goto err_free_sysctl;
4739 }
4740
4741 /* reuse mlx5core's watchdog workqueue */
4742 priv->wq = mdev->priv.health.wq_watchdog;
4743
4744 err = mlx5_core_alloc_pd(mdev, &priv->pdn, 0);
4745 if (err) {
4746 mlx5_en_err(ifp, "mlx5_core_alloc_pd failed, %d\n", err);
4747 goto err_free_wq;
4748 }
4749 err = mlx5_alloc_transport_domain(mdev, &priv->tdn, 0);
4750 if (err) {
4751 mlx5_en_err(ifp,
4752 "mlx5_alloc_transport_domain failed, %d\n", err);
4753 goto err_dealloc_pd;
4754 }
4755 err = mlx5e_create_mkey(priv, priv->pdn, &priv->mr);
4756 if (err) {
4757 mlx5_en_err(ifp, "mlx5e_create_mkey failed, %d\n", err);
4758 goto err_dealloc_transport_domain;
4759 }
4760 mlx5_query_nic_vport_mac_address(priv->mdev, 0, dev_addr);
4761
4762 /* check if we should generate a random MAC address */
4763 if (MLX5_CAP_GEN(priv->mdev, vport_group_manager) == 0 &&
4764 is_zero_ether_addr(dev_addr)) {
4765 random_ether_addr(dev_addr);
4766 mlx5_en_err(ifp, "Assigned random MAC address\n");
4767 }
4768
4769 err = mlx5e_rl_init(priv);
4770 if (err) {
4771 mlx5_en_err(ifp, "mlx5e_rl_init failed, %d\n", err);
4772 goto err_create_mkey;
4773 }
4774
4775 err = mlx5e_tls_init(priv);
4776 if (err) {
4777 if_printf(ifp, "%s: mlx5e_tls_init failed\n", __func__);
4778 goto err_rl_init;
4779 }
4780
4781 #ifdef IPSEC_OFFLOAD
4782 mlx5e_ipsec_report(priv);
4783 #endif
4784 if ((if_getcapenable2(ifp) & IFCAP2_BIT(IFCAP2_IPSEC_OFFLOAD)) != 0) {
4785 err = mlx5e_ipsec_init(priv);
4786 if (err) {
4787 if_printf(ifp, "%s: mlx5e_tls_init failed\n", __func__);
4788 goto err_tls_init;
4789 }
4790 }
4791
4792 err = mlx5e_open_drop_rq(priv, &priv->drop_rq);
4793 if (err) {
4794 if_printf(ifp, "%s: mlx5e_open_drop_rq failed (%d)\n", __func__, err);
4795 goto err_ipsec_init;
4796 }
4797
4798 err = mlx5e_open_rqts(priv);
4799 if (err) {
4800 if_printf(ifp, "%s: mlx5e_open_rqts failed (%d)\n", __func__, err);
4801 goto err_open_drop_rq;
4802 }
4803
4804 err = mlx5e_open_tirs(priv);
4805 if (err) {
4806 mlx5_en_err(ifp, "mlx5e_open_tirs() failed, %d\n", err);
4807 goto err_open_rqts;
4808 }
4809
4810 err = mlx5e_open_flow_tables(priv);
4811 if (err) {
4812 if_printf(ifp, "%s: mlx5e_open_flow_tables failed (%d)\n", __func__, err);
4813 goto err_open_tirs;
4814 }
4815
4816 err = mlx5e_tls_rx_init(priv);
4817 if (err) {
4818 if_printf(ifp, "%s: mlx5e_tls_rx_init() failed, %d\n", __func__, err);
4819 goto err_open_flow_tables;
4820 }
4821
4822 /* set default MTU */
4823 mlx5e_set_dev_port_mtu(ifp, if_getmtu(ifp));
4824
4825 /* Set default media status */
4826 priv->media_status_last = IFM_AVALID;
4827 priv->media_active_last = IFM_ETHER | IFM_AUTO | IFM_FDX;
4828
4829 /* setup default pauseframes configuration */
4830 mlx5e_setup_pauseframes(priv);
4831
4832 /* Setup supported medias */
4833 if (!mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN, 1)) {
4834 ext = MLX5_CAP_PCAM_FEATURE(mdev,
4835 ptys_extended_ethernet);
4836 eth_proto_cap = MLX5_GET_ETH_PROTO(ptys_reg, out, ext,
4837 eth_proto_capability);
4838 } else {
4839 ext = false;
4840 eth_proto_cap = 0;
4841 mlx5_en_err(ifp, "Query port media capability failed, %d\n", err);
4842 }
4843
4844 ifmedia_init(&priv->media, IFM_IMASK,
4845 mlx5e_media_change, mlx5e_media_status);
4846
4847 if (ext) {
4848 for (unsigned i = 0; i != MLX5E_EXT_LINK_SPEEDS_NUMBER; i++) {
4849 /* check if hardware has the right capability */
4850 if (MLX5E_PROT_MASK(i) & ~eth_proto_cap)
4851 continue;
4852 for (unsigned j = 0; j != MLX5E_CABLE_TYPE_NUMBER; j++) {
4853 media_entry = mlx5e_ext_mode_table[i][j];
4854 if (media_entry.subtype == 0)
4855 continue;
4856 /* check if this subtype was already added */
4857 for (unsigned k = 0; k != i; k++) {
4858 /* check if hardware has the right capability */
4859 if (MLX5E_PROT_MASK(k) & ~eth_proto_cap)
4860 continue;
4861 for (unsigned m = 0; m != MLX5E_CABLE_TYPE_NUMBER; m++) {
4862 if (media_entry.subtype == mlx5e_ext_mode_table[k][m].subtype)
4863 goto skip_ext_media;
4864 }
4865 }
4866 mlx5e_ifm_add(priv, media_entry.subtype);
4867 skip_ext_media:;
4868 }
4869 }
4870 } else {
4871 for (unsigned i = 0; i != MLX5E_LINK_SPEEDS_NUMBER; i++) {
4872 media_entry = mlx5e_mode_table[i];
4873 if (media_entry.subtype == 0)
4874 continue;
4875 if (MLX5E_PROT_MASK(i) & ~eth_proto_cap)
4876 continue;
4877 /* check if this subtype was already added */
4878 for (unsigned k = 0; k != i; k++) {
4879 if (media_entry.subtype == mlx5e_mode_table[k].subtype)
4880 goto skip_media;
4881 }
4882 mlx5e_ifm_add(priv, media_entry.subtype);
4883
4884 /* NOTE: 10G ER and LR shares the same entry */
4885 if (media_entry.subtype == IFM_10G_ER)
4886 mlx5e_ifm_add(priv, IFM_10G_LR);
4887 skip_media:;
4888 }
4889 }
4890
4891 mlx5e_ifm_add(priv, IFM_AUTO);
4892
4893 /* Set autoselect by default */
4894 ifmedia_set(&priv->media, IFM_ETHER | IFM_AUTO | IFM_FDX |
4895 IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE);
4896
4897 DEBUGNET_SET(ifp, mlx5_en);
4898
4899 ether_ifattach(ifp, dev_addr);
4900
4901 /* Register for VLAN events */
4902 priv->vlan_attach = EVENTHANDLER_REGISTER(vlan_config,
4903 mlx5e_vlan_rx_add_vid, priv, EVENTHANDLER_PRI_FIRST);
4904 priv->vlan_detach = EVENTHANDLER_REGISTER(vlan_unconfig,
4905 mlx5e_vlan_rx_kill_vid, priv, EVENTHANDLER_PRI_FIRST);
4906
4907 /* Register for VxLAN events */
4908 priv->vxlan_start = EVENTHANDLER_REGISTER(vxlan_start,
4909 mlx5e_vxlan_start, priv, EVENTHANDLER_PRI_ANY);
4910 priv->vxlan_stop = EVENTHANDLER_REGISTER(vxlan_stop,
4911 mlx5e_vxlan_stop, priv, EVENTHANDLER_PRI_ANY);
4912
4913 /* Link is down by default */
4914 if_link_state_change(ifp, LINK_STATE_DOWN);
4915
4916 mlx5e_enable_async_events(priv);
4917
4918 mlx5e_add_hw_stats(priv);
4919
4920 mlx5e_create_stats(&priv->stats.vport.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
4921 "vstats", mlx5e_vport_stats_desc, MLX5E_VPORT_STATS_NUM,
4922 priv->stats.vport.arg);
4923
4924 mlx5e_create_stats(&priv->stats.pport.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
4925 "pstats", mlx5e_pport_stats_desc, MLX5E_PPORT_STATS_NUM,
4926 priv->stats.pport.arg);
4927
4928 mlx5e_create_ethtool(priv);
4929
4930 mtx_lock(&priv->async_events_mtx);
4931 mlx5e_update_stats(priv);
4932 mtx_unlock(&priv->async_events_mtx);
4933
4934 SYSCTL_ADD_INT(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
4935 OID_AUTO, "rx_clbr_done", CTLFLAG_RD,
4936 &priv->clbr_done, 0,
4937 "RX timestamps calibration state");
4938 callout_init(&priv->tstmp_clbr, 1);
4939 /* Pull out the frequency of the clock in hz */
4940 priv->cclk = (uint64_t)MLX5_CAP_GEN(mdev, device_frequency_khz) * 1000ULL;
4941 mlx5e_reset_calibration_callout(priv);
4942
4943 pa.pa_version = PFIL_VERSION;
4944 pa.pa_flags = PFIL_IN;
4945 pa.pa_type = PFIL_TYPE_ETHERNET;
4946 pa.pa_headname = if_name(ifp);
4947 priv->pfil = pfil_head_register(&pa);
4948
4949 PRIV_LOCK(priv);
4950 err = mlx5e_open_flow_rules(priv);
4951 if (err) {
4952 mlx5_en_err(ifp,
4953 "mlx5e_open_flow_rules() failed, %d (ignored)\n", err);
4954 }
4955 PRIV_UNLOCK(priv);
4956
4957 return (priv);
4958
4959 err_open_flow_tables:
4960 mlx5e_close_flow_tables(priv);
4961
4962 err_open_tirs:
4963 mlx5e_close_tirs(priv);
4964
4965 err_open_rqts:
4966 mlx5e_close_rqts(priv);
4967
4968 err_open_drop_rq:
4969 mlx5e_close_drop_rq(&priv->drop_rq);
4970
4971 err_ipsec_init:
4972 mlx5e_ipsec_cleanup(priv);
4973
4974 err_tls_init:
4975 mlx5e_tls_cleanup(priv);
4976
4977 err_rl_init:
4978 mlx5e_rl_cleanup(priv);
4979
4980 err_create_mkey:
4981 mlx5_core_destroy_mkey(priv->mdev, &priv->mr);
4982
4983 err_dealloc_transport_domain:
4984 mlx5_dealloc_transport_domain(mdev, priv->tdn, 0);
4985
4986 err_dealloc_pd:
4987 mlx5_core_dealloc_pd(mdev, priv->pdn, 0);
4988
4989 err_free_wq:
4990 flush_workqueue(priv->wq);
4991
4992 err_free_sysctl:
4993 sysctl_ctx_free(&priv->sysctl_ctx);
4994 if (priv->sysctl_debug)
4995 sysctl_ctx_free(&priv->stats.port_stats_debug.ctx);
4996 mlx5e_priv_static_destroy(priv, mdev, mdev->priv.eq_table.num_comp_vectors);
4997
4998 err_free_ifp:
4999 if_free(ifp);
5000 free(priv, M_MLX5EN);
5001 return (NULL);
5002 }
5003
5004 static void
mlx5e_destroy_ifp(struct mlx5_core_dev * mdev,void * vpriv)5005 mlx5e_destroy_ifp(struct mlx5_core_dev *mdev, void *vpriv)
5006 {
5007 struct mlx5e_priv *priv = vpriv;
5008 if_t ifp = priv->ifp;
5009
5010 /* don't allow more IOCTLs */
5011 priv->gone = 1;
5012
5013 /* XXX wait a bit to allow IOCTL handlers to complete */
5014 pause("W", hz);
5015
5016 #ifdef RATELIMIT
5017 /*
5018 * Tell the TCP ratelimit code to release the rate-sets attached
5019 * to our ifnet.
5020 */
5021 tcp_rl_release_ifnet(ifp);
5022 /*
5023 * The kernel can still have reference(s) via the m_snd_tag's into
5024 * the ratelimit channels, and these must go away before
5025 * detaching:
5026 */
5027 while (READ_ONCE(priv->rl.stats.tx_active_connections) != 0) {
5028 mlx5_en_err(priv->ifp,
5029 "Waiting for all ratelimit connections to terminate\n");
5030 pause("W", hz);
5031 }
5032 #endif
5033
5034 #ifdef KERN_TLS
5035 /* wait for all TLS tags to get freed */
5036 while (priv->tls.init != 0 &&
5037 uma_zone_get_cur(priv->tls.zone) != 0) {
5038 mlx5_en_err(priv->ifp,
5039 "Waiting for all TLS connections to terminate\n");
5040 pause("W", hz);
5041 }
5042
5043 /* wait for all TLS RX tags to get freed */
5044 while (priv->tls_rx.init != 0 &&
5045 uma_zone_get_cur(priv->tls_rx.zone) != 0) {
5046 mlx5_en_err(priv->ifp,
5047 "Waiting for all TLS RX connections to terminate\n");
5048 pause("W", hz);
5049 }
5050 #endif
5051 /* wait for all unlimited send tags to complete */
5052 mlx5e_priv_wait_for_completion(priv, mdev->priv.eq_table.num_comp_vectors);
5053
5054 /* stop watchdog timer */
5055 callout_drain(&priv->watchdog);
5056
5057 callout_drain(&priv->tstmp_clbr);
5058
5059 if (priv->vlan_attach != NULL)
5060 EVENTHANDLER_DEREGISTER(vlan_config, priv->vlan_attach);
5061 if (priv->vlan_detach != NULL)
5062 EVENTHANDLER_DEREGISTER(vlan_unconfig, priv->vlan_detach);
5063 if (priv->vxlan_start != NULL)
5064 EVENTHANDLER_DEREGISTER(vxlan_start, priv->vxlan_start);
5065 if (priv->vxlan_stop != NULL)
5066 EVENTHANDLER_DEREGISTER(vxlan_stop, priv->vxlan_stop);
5067
5068 /* make sure device gets closed */
5069 PRIV_LOCK(priv);
5070 mlx5e_close_locked(ifp);
5071 mlx5e_close_flow_rules(priv);
5072 PRIV_UNLOCK(priv);
5073
5074 /* deregister pfil */
5075 if (priv->pfil != NULL) {
5076 pfil_head_unregister(priv->pfil);
5077 priv->pfil = NULL;
5078 }
5079
5080 /* unregister device */
5081 ifmedia_removeall(&priv->media);
5082 ether_ifdetach(ifp);
5083
5084 mlx5e_tls_rx_cleanup(priv);
5085 #ifdef IPSEC_OFFLOAD
5086 ipsec_accel_on_ifdown(priv->ifp);
5087 #endif
5088 mlx5e_close_flow_tables(priv);
5089 mlx5e_close_tirs(priv);
5090 mlx5e_close_rqts(priv);
5091 mlx5e_close_drop_rq(&priv->drop_rq);
5092 mlx5e_ipsec_cleanup(priv);
5093 mlx5e_tls_cleanup(priv);
5094 mlx5e_rl_cleanup(priv);
5095
5096 /* destroy all remaining sysctl nodes */
5097 sysctl_ctx_free(&priv->stats.vport.ctx);
5098 sysctl_ctx_free(&priv->stats.pport.ctx);
5099 if (priv->sysctl_debug)
5100 sysctl_ctx_free(&priv->stats.port_stats_debug.ctx);
5101 sysctl_ctx_free(&priv->sysctl_ctx);
5102
5103 mlx5_core_destroy_mkey(priv->mdev, &priv->mr);
5104 mlx5_dealloc_transport_domain(priv->mdev, priv->tdn, 0);
5105 mlx5_core_dealloc_pd(priv->mdev, priv->pdn, 0);
5106 mlx5e_disable_async_events(priv);
5107 flush_workqueue(priv->wq);
5108 mlx5e_priv_static_destroy(priv, mdev, mdev->priv.eq_table.num_comp_vectors);
5109 if_free(ifp);
5110 free(priv, M_MLX5EN);
5111 }
5112
5113 #ifdef DEBUGNET
5114 static void
mlx5_en_debugnet_init(if_t dev,int * nrxr,int * ncl,int * clsize)5115 mlx5_en_debugnet_init(if_t dev, int *nrxr, int *ncl, int *clsize)
5116 {
5117 struct mlx5e_priv *priv = if_getsoftc(dev);
5118
5119 PRIV_LOCK(priv);
5120 *nrxr = priv->params.num_channels;
5121 *ncl = DEBUGNET_MAX_IN_FLIGHT;
5122 *clsize = MLX5E_MAX_RX_BYTES;
5123 PRIV_UNLOCK(priv);
5124 }
5125
5126 static void
mlx5_en_debugnet_event(if_t dev,enum debugnet_ev event)5127 mlx5_en_debugnet_event(if_t dev, enum debugnet_ev event)
5128 {
5129 }
5130
5131 static int
mlx5_en_debugnet_transmit(if_t dev,struct mbuf * m)5132 mlx5_en_debugnet_transmit(if_t dev, struct mbuf *m)
5133 {
5134 struct mlx5e_priv *priv = if_getsoftc(dev);
5135 struct mlx5e_sq *sq;
5136 int err;
5137
5138 if ((if_getdrvflags(dev) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
5139 IFF_DRV_RUNNING || (priv->media_status_last & IFM_ACTIVE) == 0)
5140 return (ENOENT);
5141
5142 sq = &priv->channel[0].sq[0];
5143
5144 if (sq->running == 0) {
5145 m_freem(m);
5146 return (ENOENT);
5147 }
5148
5149 if (mlx5e_sq_xmit(sq, &m) != 0) {
5150 m_freem(m);
5151 err = ENOBUFS;
5152 } else {
5153 err = 0;
5154 }
5155
5156 mlx5e_tx_notify_hw(sq, true);
5157
5158 return (err);
5159 }
5160
5161 static int
mlx5_en_debugnet_poll(if_t dev,int count)5162 mlx5_en_debugnet_poll(if_t dev, int count)
5163 {
5164 struct mlx5e_priv *priv = if_getsoftc(dev);
5165
5166 if ((if_getdrvflags(dev) & IFF_DRV_RUNNING) == 0 ||
5167 (priv->media_status_last & IFM_ACTIVE) == 0)
5168 return (ENOENT);
5169
5170 mlx5_poll_interrupts(priv->mdev);
5171
5172 return (0);
5173 }
5174 #endif /* DEBUGNET */
5175
5176 static void *
mlx5e_get_ifp(void * vpriv)5177 mlx5e_get_ifp(void *vpriv)
5178 {
5179 struct mlx5e_priv *priv = vpriv;
5180
5181 return (priv->ifp);
5182 }
5183
5184 static struct mlx5_interface mlx5e_interface = {
5185 .add = mlx5e_create_ifp,
5186 .remove = mlx5e_destroy_ifp,
5187 .event = mlx5e_async_event,
5188 .protocol = MLX5_INTERFACE_PROTOCOL_ETH,
5189 .get_dev = mlx5e_get_ifp,
5190 };
5191
5192 void
mlx5e_init(void)5193 mlx5e_init(void)
5194 {
5195 mlx5_register_interface(&mlx5e_interface);
5196 }
5197
5198 void
mlx5e_cleanup(void)5199 mlx5e_cleanup(void)
5200 {
5201 mlx5_unregister_interface(&mlx5e_interface);
5202 }
5203
5204 module_init_order(mlx5e_init, SI_ORDER_SIXTH);
5205 module_exit_order(mlx5e_cleanup, SI_ORDER_SIXTH);
5206
5207 MODULE_DEPEND(mlx5en, ipsec, 1, 1, 1);
5208 MODULE_DEPEND(mlx5en, linuxkpi, 1, 1, 1);
5209 MODULE_DEPEND(mlx5en, mlx5, 1, 1, 1);
5210 MODULE_VERSION(mlx5en, 1);
5211