1 /* SPDX-License-Identifier: BSD-3-Clause */
2 /* Copyright(c) 2007-2025 Intel Corporation */
3 /**
4 *****************************************************************************
5 * @file icp_qat_hw_2x_comp.h
6 * @defgroup ICP QAT HW accessors for using the for 2.x Compression Slice
7 * definitions
8 * @ingroup icp_qat_hw_2x_comp
9 * @description
10 * This file documents definitions for the QAT HW COMP SLICE
11 *
12 *****************************************************************************/
13
14 #ifndef _ICP_QAT_HW_20_COMP_H_
15 #define _ICP_QAT_HW_20_COMP_H_
16
17 #include "icp_qat_hw_20_comp_defs.h" /* For HW definitions */
18 #include "icp_qat_fw.h" /* For Set Field Macros. */
19
20 #define BYTE_SWAP_32 __builtin_bswap32
21
22 /**
23 *****************************************************************************
24 * @ingroup icp_qat_fw_comn
25 *
26 * @description
27 * Definition of the hw config csr. This representation has to be further
28 * processed by the corresponding config build function.
29 *
30 *****************************************************************************/
31 typedef struct icp_qat_hw_comp_20_config_csr_lower_s {
32 /* Fields programmable directly by the SW. */
33 icp_qat_hw_comp_20_extended_delay_match_mode_t edmm;
34 icp_qat_hw_comp_20_hw_comp_format_t algo;
35 icp_qat_hw_comp_20_search_depth_t sd;
36 icp_qat_hw_comp_20_hbs_control_t hbs;
37 /* Fields programmable directly by the FW. */
38 /* Block Drop enable. (Set by FW) */
39 icp_qat_hw_comp_20_abd_t abd;
40 icp_qat_hw_comp_20_lllbd_ctrl_t lllbd;
41 /* Advanced HW control (Set to default vals) */
42 icp_qat_hw_comp_20_min_match_control_t mmctrl;
43 icp_qat_hw_comp_20_skip_hash_collision_t hash_col;
44 icp_qat_hw_comp_20_skip_hash_update_t hash_update;
45 icp_qat_hw_comp_20_byte_skip_t skip_ctrl;
46
47 } icp_qat_hw_comp_20_config_csr_lower_t;
48
49 /**
50 *****************************************************************************
51 * @ingroup icp_qat_fw_comn
52 *
53 * @description
54 * Build the longword as expected by the HW
55 *
56 *****************************************************************************/
57 static inline uint32_t
ICP_QAT_FW_COMP_20_BUILD_CONFIG_LOWER(icp_qat_hw_comp_20_config_csr_lower_t csr)58 ICP_QAT_FW_COMP_20_BUILD_CONFIG_LOWER(icp_qat_hw_comp_20_config_csr_lower_t csr)
59 {
60 uint32_t val32 = 0;
61 /* Programmable values */
62 QAT_FIELD_SET(val32,
63 csr.algo,
64 ICP_QAT_HW_COMP_20_CONFIG_CSR_HW_COMP_FORMAT_BITPOS,
65 ICP_QAT_HW_COMP_20_CONFIG_CSR_HW_COMP_FORMAT_MASK);
66
67 QAT_FIELD_SET(val32,
68 csr.sd,
69 ICP_QAT_HW_COMP_20_CONFIG_CSR_SEARCH_DEPTH_BITPOS,
70 ICP_QAT_HW_COMP_20_CONFIG_CSR_SEARCH_DEPTH_MASK);
71
72 QAT_FIELD_SET(
73 val32,
74 csr.edmm,
75 ICP_QAT_HW_COMP_20_CONFIG_CSR_EXTENDED_DELAY_MATCH_MODE_BITPOS,
76 ICP_QAT_HW_COMP_20_CONFIG_CSR_EXTENDED_DELAY_MATCH_MODE_MASK);
77
78 QAT_FIELD_SET(val32,
79 csr.hbs,
80 ICP_QAT_HW_COMP_20_CONFIG_CSR_HBS_CONTROL_BITPOS,
81 ICP_QAT_HW_COMP_20_CONFIG_CSR_HBS_CONTROL_MASK);
82
83 QAT_FIELD_SET(val32,
84 csr.mmctrl,
85 ICP_QAT_HW_COMP_20_CONFIG_CSR_MIN_MATCH_CONTROL_BITPOS,
86 ICP_QAT_HW_COMP_20_CONFIG_CSR_MIN_MATCH_CONTROL_MASK);
87
88 QAT_FIELD_SET(val32,
89 csr.hash_col,
90 ICP_QAT_HW_COMP_20_CONFIG_CSR_SKIP_HASH_COLLISION_BITPOS,
91 ICP_QAT_HW_COMP_20_CONFIG_CSR_SKIP_HASH_COLLISION_MASK);
92
93 QAT_FIELD_SET(val32,
94 csr.hash_update,
95 ICP_QAT_HW_COMP_20_CONFIG_CSR_SKIP_HASH_UPDATE_BITPOS,
96 ICP_QAT_HW_COMP_20_CONFIG_CSR_SKIP_HASH_UPDATE_MASK);
97
98 QAT_FIELD_SET(val32,
99 csr.skip_ctrl,
100 ICP_QAT_HW_COMP_20_CONFIG_CSR_BYTE_SKIP_BITPOS,
101 ICP_QAT_HW_COMP_20_CONFIG_CSR_BYTE_SKIP_MASK);
102 /* Default values. */
103
104 QAT_FIELD_SET(val32,
105 csr.abd,
106 ICP_QAT_HW_COMP_20_CONFIG_CSR_ABD_BITPOS,
107 ICP_QAT_HW_COMP_20_CONFIG_CSR_ABD_MASK);
108
109 QAT_FIELD_SET(val32,
110 csr.lllbd,
111 ICP_QAT_HW_COMP_20_CONFIG_CSR_LLLBD_CTRL_BITPOS,
112 ICP_QAT_HW_COMP_20_CONFIG_CSR_LLLBD_CTRL_MASK);
113
114 return BYTE_SWAP_32(val32);
115 }
116
117 /**
118 *****************************************************************************
119 * @ingroup icp_qat_fw_comn
120 *
121 * @description
122 * Definition of the hw config csr. This representation has to be further
123 * processed by the corresponding config build function.
124 *
125 *****************************************************************************/
126 typedef struct icp_qat_hw_comp_20_config_csr_upper_s {
127 icp_qat_hw_comp_20_scb_control_t scb_ctrl;
128 icp_qat_hw_comp_20_rmb_control_t rmb_ctrl;
129 icp_qat_hw_comp_20_som_control_t som_ctrl;
130 icp_qat_hw_comp_20_skip_hash_rd_control_t skip_hash_ctrl;
131 icp_qat_hw_comp_20_scb_unload_control_t scb_unload_ctrl;
132 icp_qat_hw_comp_20_disable_token_fusion_control_t
133 disable_token_fusion_ctrl;
134 icp_qat_hw_comp_20_lbms_t lbms;
135 icp_qat_hw_comp_20_scb_mode_reset_mask_t scb_mode_reset;
136 uint16_t lazy;
137 uint16_t nice;
138 } icp_qat_hw_comp_20_config_csr_upper_t;
139
140 /**
141 *****************************************************************************
142 * @ingroup icp_qat_fw_comn
143 *
144 * @description
145 * Build the longword as expected by the HW
146 *
147 *****************************************************************************/
148 static inline uint32_t
ICP_QAT_FW_COMP_20_BUILD_CONFIG_UPPER(icp_qat_hw_comp_20_config_csr_upper_t csr)149 ICP_QAT_FW_COMP_20_BUILD_CONFIG_UPPER(icp_qat_hw_comp_20_config_csr_upper_t csr)
150 {
151 uint32_t val32 = 0;
152
153 QAT_FIELD_SET(val32,
154 csr.scb_ctrl,
155 ICP_QAT_HW_COMP_20_CONFIG_CSR_SCB_CONTROL_BITPOS,
156 ICP_QAT_HW_COMP_20_CONFIG_CSR_SCB_CONTROL_MASK);
157
158 QAT_FIELD_SET(val32,
159 csr.rmb_ctrl,
160 ICP_QAT_HW_COMP_20_CONFIG_CSR_RMB_CONTROL_BITPOS,
161 ICP_QAT_HW_COMP_20_CONFIG_CSR_RMB_CONTROL_MASK);
162
163 QAT_FIELD_SET(val32,
164 csr.som_ctrl,
165 ICP_QAT_HW_COMP_20_CONFIG_CSR_SOM_CONTROL_BITPOS,
166 ICP_QAT_HW_COMP_20_CONFIG_CSR_SOM_CONTROL_MASK);
167
168 QAT_FIELD_SET(val32,
169 csr.skip_hash_ctrl,
170 ICP_QAT_HW_COMP_20_CONFIG_CSR_SKIP_HASH_RD_CONTROL_BITPOS,
171 ICP_QAT_HW_COMP_20_CONFIG_CSR_SKIP_HASH_RD_CONTROL_MASK);
172
173 QAT_FIELD_SET(val32,
174 csr.scb_unload_ctrl,
175 ICP_QAT_HW_COMP_20_CONFIG_CSR_SCB_UNLOAD_CONTROL_BITPOS,
176 ICP_QAT_HW_COMP_20_CONFIG_CSR_SCB_UNLOAD_CONTROL_MASK);
177
178 QAT_FIELD_SET(
179 val32,
180 csr.disable_token_fusion_ctrl,
181 ICP_QAT_HW_COMP_20_CONFIG_CSR_DISABLE_TOKEN_FUSION_CONTROL_BITPOS,
182 ICP_QAT_HW_COMP_20_CONFIG_CSR_DISABLE_TOKEN_FUSION_CONTROL_MASK);
183
184 QAT_FIELD_SET(val32,
185 csr.lbms,
186 ICP_QAT_HW_COMP_20_CONFIG_CSR_LBMS_BITPOS,
187 ICP_QAT_HW_COMP_20_CONFIG_CSR_LBMS_MASK);
188
189 QAT_FIELD_SET(val32,
190 csr.scb_mode_reset,
191 ICP_QAT_HW_COMP_20_CONFIG_CSR_SCB_MODE_RESET_MASK_BITPOS,
192 ICP_QAT_HW_COMP_20_CONFIG_CSR_SCB_MODE_RESET_MASK_MASK);
193
194 QAT_FIELD_SET(val32,
195 csr.lazy,
196 ICP_QAT_HW_COMP_20_CONFIG_CSR_LAZY_PARAM_BITPOS,
197 ICP_QAT_HW_COMP_20_CONFIG_CSR_LAZY_PARAM_MASK);
198
199 QAT_FIELD_SET(val32,
200 csr.nice,
201 ICP_QAT_HW_COMP_20_CONFIG_CSR_NICE_PARAM_BITPOS,
202 ICP_QAT_HW_COMP_20_CONFIG_CSR_NICE_PARAM_MASK);
203
204 return BYTE_SWAP_32(val32);
205 }
206
207 /**
208 *****************************************************************************
209 * @ingroup icp_qat_fw_comn
210 *
211 * @description
212 * Definition of the hw config csr. This representation has to be further
213 * processed by the corresponding config build function.
214 *
215 *****************************************************************************/
216 typedef struct icp_qat_hw_decomp_20_config_csr_lower_s {
217 /* Fields programmable directly by the SW. */
218 icp_qat_hw_decomp_20_hbs_control_t hbs;
219 icp_qat_hw_decomp_20_lbms_t lbms;
220 /* Advanced HW control (Set to default vals) */
221 icp_qat_hw_decomp_20_hw_comp_format_t algo;
222 icp_qat_hw_decomp_20_min_match_control_t mmctrl;
223 icp_qat_hw_decomp_20_lz4_block_checksum_present_t lbc;
224 } icp_qat_hw_decomp_20_config_csr_lower_t;
225
226 /**
227 *****************************************************************************
228 * @ingroup icp_qat_fw_comn
229 *
230 * @description
231 * Build the longword as expected by the HW
232 *
233 *****************************************************************************/
234 static inline uint32_t
ICP_QAT_FW_DECOMP_20_BUILD_CONFIG_LOWER(icp_qat_hw_decomp_20_config_csr_lower_t csr)235 ICP_QAT_FW_DECOMP_20_BUILD_CONFIG_LOWER(
236 icp_qat_hw_decomp_20_config_csr_lower_t csr)
237 {
238 uint32_t val32 = 0;
239
240 QAT_FIELD_SET(val32,
241 csr.hbs,
242 ICP_QAT_HW_DECOMP_20_CONFIG_CSR_HBS_CONTROL_BITPOS,
243 ICP_QAT_HW_DECOMP_20_CONFIG_CSR_HBS_CONTROL_MASK);
244
245 QAT_FIELD_SET(val32,
246 csr.lbms,
247 ICP_QAT_HW_DECOMP_20_CONFIG_CSR_LBMS_BITPOS,
248 ICP_QAT_HW_DECOMP_20_CONFIG_CSR_LBMS_MASK);
249
250 QAT_FIELD_SET(val32,
251 csr.algo,
252 ICP_QAT_HW_DECOMP_20_CONFIG_CSR_HW_DECOMP_FORMAT_BITPOS,
253 ICP_QAT_HW_DECOMP_20_CONFIG_CSR_HW_DECOMP_FORMAT_MASK);
254
255 QAT_FIELD_SET(val32,
256 csr.mmctrl,
257 ICP_QAT_HW_DECOMP_20_CONFIG_CSR_MIN_MATCH_CONTROL_BITPOS,
258 ICP_QAT_HW_DECOMP_20_CONFIG_CSR_MIN_MATCH_CONTROL_MASK);
259
260 QAT_FIELD_SET(
261 val32,
262 csr.lbc,
263 ICP_QAT_HW_DECOMP_20_CONFIG_CSR_LZ4_BLOCK_CHECKSUM_PRESENT_BITPOS,
264 ICP_QAT_HW_DECOMP_20_CONFIG_CSR_LZ4_BLOCK_CHECKSUM_PRESENT_MASK);
265
266 return BYTE_SWAP_32(val32);
267 }
268
269 /**
270 *****************************************************************************
271 * @ingroup icp_qat_fw_comn
272 *
273 * @description
274 * Definition of the hw config csr. This representation has to be further
275 * processed by the corresponding config build function.
276 *
277 *****************************************************************************/
278 typedef struct icp_qat_hw_decomp_20_config_csr_upper_s {
279 /* Advanced HW control (Set to default vals) */
280 icp_qat_hw_decomp_20_speculative_decoder_control_t sdc;
281 icp_qat_hw_decomp_20_reserved4_control_t res4;
282 } icp_qat_hw_decomp_20_config_csr_upper_t;
283
284 /**
285 *****************************************************************************
286 * @ingroup icp_qat_fw_comn
287 *
288 * @description
289 * Build the longword as expected by the HW
290 *
291 *****************************************************************************/
292 static inline uint32_t
ICP_QAT_FW_DECOMP_20_BUILD_CONFIG_UPPER(icp_qat_hw_decomp_20_config_csr_upper_t csr)293 ICP_QAT_FW_DECOMP_20_BUILD_CONFIG_UPPER(
294 icp_qat_hw_decomp_20_config_csr_upper_t csr)
295 {
296 uint32_t val32 = 0;
297
298 QAT_FIELD_SET(
299 val32,
300 csr.sdc,
301 ICP_QAT_HW_DECOMP_20_CONFIG_CSR_SPECULATIVE_DECODER_CONTROL_BITPOS,
302 ICP_QAT_HW_DECOMP_20_CONFIG_CSR_SPECULATIVE_DECODER_CONTROL_MASK);
303
304 QAT_FIELD_SET(val32,
305 csr.res4,
306 ICP_QAT_HW_DECOMP_20_CONFIG_CSR_RESERVED4_CONTROL_BITPOS,
307 ICP_QAT_HW_DECOMP_20_CONFIG_CSR_RESERVED4_CONTROL_MASK);
308
309 return BYTE_SWAP_32(val32);
310 }
311 #endif /* ICP_QAT_HW__2X_COMP_H_ */
312