1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2021 Adrian Chadd <adrian@FreeBSD.org>. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice unmodified, this list of conditions, and the following 11 * disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #ifndef __QCOM_ESS_EDMA_VAR_H__ 30 #define __QCOM_ESS_EDMA_VAR_H__ 31 32 #define EDMA_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) 33 #define EDMA_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) 34 #define EDMA_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_mtx, MA_OWNED) 35 36 #define EDMA_RING_LOCK(_ring) mtx_lock(&(_ring)->mtx) 37 #define EDMA_RING_UNLOCK(_ring) mtx_unlock(&(_ring)->mtx) 38 #define EDMA_RING_LOCK_ASSERT(_ring) mtx_assert(&(_ring)->mtx, MA_OWNED) 39 40 /* 41 * register space access macros 42 */ 43 #define EDMA_REG_WRITE(sc, reg, val) do { \ 44 bus_write_4(sc->sc_mem_res, (reg), (val)); \ 45 } while (0) 46 47 #define EDMA_REG_READ(sc, reg) bus_read_4(sc->sc_mem_res, (reg)) 48 49 #define EDMA_REG_SET_BITS(sc, reg, bits) \ 50 EDMA_REG_WRITE(sc, reg, EDMA_REG_READ(sc, (reg)) | (bits)) 51 52 #define EDMA_REG_CLEAR_BITS(sc, reg, bits) \ 53 EDMA_REG_WRITE(sc, reg, EDMA_REG_READ(sc, (reg)) & ~(bits)) 54 55 #define EDMA_REG_BARRIER_WRITE(sc) bus_barrier((sc)->sc_mem_res, \ 56 0, (sc)->sc_mem_res_size, BUS_SPACE_BARRIER_WRITE) 57 #define EDMA_REG_BARRIER_READ(sc) bus_barrier((sc)->sc_mem_res, \ 58 0, (sc)->sc_mem_res_size, BUS_SPACE_BARRIER_READ) 59 #define EDMA_REG_BARRIER_RW(sc) bus_barrier((sc)->sc_mem_res, \ 60 0, (sc)->sc_mem_res_size, \ 61 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE) 62 63 64 /* 65 * Fixed number of interrupts - 16 TX, 8 RX. 66 * 67 * The Linux driver supports 4 or 8 RX queues. 68 */ 69 70 #define QCOM_ESS_EDMA_NUM_TX_IRQS 16 71 #define QCOM_ESS_EDMA_NUM_RX_IRQS 8 72 73 #define QCOM_ESS_EDMA_NUM_TX_RINGS 16 74 #define QCOM_ESS_EDMA_NUM_RX_RINGS 8 75 76 #define EDMA_TX_RING_SIZE 128 77 #define EDMA_RX_RING_SIZE 128 78 79 #define EDMA_TX_BUFRING_SIZE 512 80 81 /* Maximum number of GMAC instances */ 82 #define QCOM_ESS_EDMA_MAX_NUM_GMACS 5 83 84 /* Maximum number of ports to support mapping to GMACs */ 85 #define QCOM_ESS_EDMA_MAX_NUM_PORTS 8 86 87 #define QCOM_ESS_EDMA_MAX_TXFRAGS 8 88 89 struct qcom_ess_edma_softc; 90 91 /* 92 * An instance of an interrupt queue. 93 */ 94 struct qcom_ess_edma_intr { 95 struct qcom_ess_edma_softc *sc; 96 struct resource *irq_res; 97 int irq_rid; 98 void *irq_intr; 99 100 struct { 101 uint64_t num_intr; 102 } stats; 103 }; 104 105 /* 106 * A TX/RX descriptor ring. 107 */ 108 struct qcom_ess_edma_desc_ring { 109 bus_dma_tag_t hw_ring_dma_tag; /* tag for hw ring */ 110 bus_dma_tag_t buffer_dma_tag; /* tag for mbufs */ 111 char *label; 112 113 struct mtx mtx; 114 115 bus_dmamap_t hw_desc_map; 116 bus_addr_t hw_desc_paddr; 117 void *hw_desc; 118 119 void *sw_desc; 120 int hw_entry_size; /* hw desc entry size */ 121 int sw_entry_size; /* sw desc entry size */ 122 int ring_count; /* Number of entries */ 123 int buffer_align; 124 int ring_align; 125 126 uint16_t next_to_fill; 127 uint16_t next_to_clean; 128 uint16_t pending_fill; 129 130 struct { 131 uint64_t num_added; 132 uint64_t num_cleaned; 133 uint64_t num_dropped; 134 uint64_t num_enqueue_full; 135 uint64_t num_rx_no_gmac; 136 uint64_t num_rx_ok; 137 uint64_t num_tx_ok; 138 uint64_t num_tx_maxfrags; 139 uint64_t num_tx_mapfail; 140 uint64_t num_rx_csum_ok; 141 uint64_t num_rx_csum_fail; 142 uint64_t num_tx_complete; 143 uint64_t num_tx_xmit_defer; 144 uint64_t num_tx_xmit_task; 145 } stats; 146 }; 147 148 /* 149 * Structs for transmit and receive software 150 * ring entries. 151 */ 152 struct qcom_ess_edma_sw_desc_tx { 153 struct mbuf *m; 154 bus_dmamap_t m_dmamap; 155 uint32_t is_first:1; 156 uint32_t is_last:1; 157 }; 158 159 struct qcom_ess_edma_sw_desc_rx { 160 struct mbuf *m; 161 bus_dmamap_t m_dmamap; 162 bus_addr_t m_physaddr; 163 }; 164 165 #define QCOM_ESS_EDMA_LABEL_SZ 16 166 167 /* 168 * Per transmit ring TX state for TX queue / buf_ring stuff. 169 */ 170 struct qcom_ess_edma_tx_state { 171 struct task completion_task; 172 struct task xmit_task; 173 struct buf_ring *br; 174 struct taskqueue *completion_tq; 175 struct qcom_ess_edma_softc *sc; 176 char label[QCOM_ESS_EDMA_LABEL_SZ]; 177 int enqueue_is_running; 178 int queue_id; 179 }; 180 181 /* 182 * Per receive ring RX state for taskqueue stuff. 183 */ 184 struct qcom_ess_edma_rx_state { 185 struct task completion_task; 186 struct taskqueue *completion_tq; 187 struct qcom_ess_edma_softc *sc; 188 char label[QCOM_ESS_EDMA_LABEL_SZ]; 189 int queue_id; 190 }; 191 192 struct qcom_ess_edma_gmac { 193 struct qcom_ess_edma_softc *sc; 194 int id; 195 bool enabled; 196 /* Native VLAN ID */ 197 int vlan_id; 198 /* Switch portmask for this instance */ 199 int port_mask; 200 /* MAC address for this ifnet (from device tree) */ 201 struct ether_addr eaddr; 202 /* ifnet interface! */ 203 if_t ifp; 204 /* media interface */ 205 struct ifmedia ifm; 206 }; 207 208 struct qcom_ess_edma_softc { 209 device_t sc_dev; 210 struct mtx sc_mtx; 211 struct resource *sc_mem_res; 212 size_t sc_mem_res_size; 213 int sc_mem_rid; 214 uint32_t sc_debug; 215 bus_dma_tag_t sc_dma_tag; 216 217 struct qcom_ess_edma_intr sc_tx_irq[QCOM_ESS_EDMA_NUM_TX_IRQS]; 218 struct qcom_ess_edma_intr sc_rx_irq[QCOM_ESS_EDMA_NUM_RX_IRQS]; 219 220 struct qcom_ess_edma_desc_ring sc_tx_ring[QCOM_ESS_EDMA_NUM_TX_RINGS]; 221 struct qcom_ess_edma_desc_ring sc_rx_ring[QCOM_ESS_EDMA_NUM_RX_RINGS]; 222 struct qcom_ess_edma_tx_state sc_tx_state[QCOM_ESS_EDMA_NUM_TX_RINGS]; 223 struct qcom_ess_edma_rx_state sc_rx_state[QCOM_ESS_EDMA_NUM_RX_RINGS]; 224 struct qcom_ess_edma_gmac sc_gmac[QCOM_ESS_EDMA_MAX_NUM_GMACS]; 225 226 int sc_gmac_port_map[QCOM_ESS_EDMA_MAX_NUM_PORTS]; 227 228 struct { 229 uint32_t num_gmac; 230 uint32_t mdio_supported; 231 uint32_t poll_required; 232 uint32_t rss_type; 233 234 uint32_t rx_buf_size; 235 bool rx_buf_ether_align; 236 237 uint32_t tx_intr_mask; 238 uint32_t rx_intr_mask; 239 240 /* number of tx/rx descriptor entries in each ring */ 241 uint32_t rx_ring_count; 242 uint32_t tx_ring_count; 243 244 /* how many queues for each CPU */ 245 uint32_t num_tx_queue_per_cpu; 246 } sc_config; 247 248 struct { 249 uint32_t misc_intr_mask; 250 uint32_t wol_intr_mask; 251 uint32_t intr_sw_idx_w; 252 } sc_state; 253 }; 254 255 #endif /* __QCOM_ESS_EDMA_VAR_H__ */ 256