1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2019, 2020, 2023-2025 Kevin Lo <kevlo@openbsd.org>
5 * Copyright (c) 2025 Adrian Chadd <adrian@FreeBSD.org>
6 *
7 * Hardware programming portions from Realtek Semiconductor.
8 *
9 * Permission to use, copy, modify, and distribute this software for any
10 * purpose with or without fee is hereby granted, provided that the above
11 * copyright notice and this permission notice appear in all copies.
12 *
13 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
14 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
15 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
16 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
17 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
18 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
19 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 */
21
22 /* $OpenBSD: if_rge.c,v 1.38 2025/09/19 00:41:14 kevlo Exp $ */
23
24 #include <sys/param.h>
25 #include <sys/systm.h>
26 #include <sys/sockio.h>
27 #include <sys/mbuf.h>
28 #include <sys/malloc.h>
29 #include <sys/endian.h>
30 #include <sys/socket.h>
31 #include <net/if.h>
32 #include <net/if_media.h>
33 #include <sys/queue.h>
34 #include <sys/taskqueue.h>
35 #include <sys/bus.h>
36 #include <sys/module.h>
37 #include <sys/rman.h>
38
39 #include <netinet/in.h>
40 #include <netinet/if_ether.h>
41
42 #include <net/bpf.h>
43 #include <net/ethernet.h>
44 #include <net/if.h>
45 #include <net/if_var.h>
46 #include <net/if_arp.h>
47 #include <net/if_dl.h>
48 #include <net/if_media.h>
49 #include <net/if_types.h>
50 #include <net/if_vlan_var.h>
51
52 #include <machine/bus.h>
53 #include <machine/resource.h>
54
55 #include <dev/mii/mii.h>
56
57 #include <dev/pci/pcivar.h>
58 #include <dev/pci/pcireg.h>
59
60 #include "if_rge_vendor.h"
61 #include "if_rgereg.h"
62 #include "if_rgevar.h"
63 #include "if_rge_microcode.h"
64 #include "if_rge_debug.h"
65
66 #include "if_rge_hw.h"
67
68 static int rge_reset(struct rge_softc *sc);
69 static void rge_set_phy_power(struct rge_softc *sc, int on);
70 static void rge_mac_config_ext_mcu(struct rge_softc *, enum rge_mac_type);
71 static uint64_t rge_mcu_get_bin_version(const uint16_t *, uint16_t);
72 static void rge_mcu_set_version(struct rge_softc *sc, uint64_t mcodever);
73 static void rge_ephy_config_mac_r25(struct rge_softc *sc);
74 static void rge_ephy_config_mac_r25b(struct rge_softc *sc);
75 static void rge_ephy_config_mac_r27(struct rge_softc *sc);
76 static void rge_phy_config_mac_r27(struct rge_softc *sc);
77 static void rge_phy_config_mac_r26_1(struct rge_softc *sc);
78 static void rge_phy_config_mac_r26_2(struct rge_softc *sc);
79 static void rge_phy_config_mac_r25(struct rge_softc *sc);
80 static void rge_phy_config_mac_r25b(struct rge_softc *sc);
81 static void rge_phy_config_mac_r25d_1(struct rge_softc *);
82 static void rge_phy_config_mac_r25d_2(struct rge_softc *);
83 static void rge_phy_config_mcu(struct rge_softc *sc, uint16_t rcodever);
84 static void rge_hw_init(struct rge_softc *sc);
85 static void rge_disable_phy_ocp_pwrsave(struct rge_softc *sc);
86 static void rge_patch_phy_mcu(struct rge_softc *sc, int set);
87 static void rge_disable_hw_im(struct rge_softc *sc);
88 static void rge_disable_sim_im(struct rge_softc *sc);
89 static void rge_setup_sim_im(struct rge_softc *sc);
90 static void rge_switch_mcu_ram_page(struct rge_softc *sc, int page);
91 static int rge_exit_oob(struct rge_softc *sc);
92 static void rge_write_ephy(struct rge_softc *sc, uint16_t reg, uint16_t val);
93 static uint16_t rge_read_ephy(struct rge_softc *sc, uint16_t reg);
94 static uint16_t rge_check_ephy_ext_add(struct rge_softc *sc, uint16_t reg);
95 static void rge_r27_write_ephy(struct rge_softc *sc, uint16_t reg, uint16_t val);
96
97 static int
rge_reset(struct rge_softc * sc)98 rge_reset(struct rge_softc *sc)
99 {
100 int i;
101
102 RGE_CLRBIT_4(sc, RGE_RXCFG, RGE_RXCFG_ALLPHYS | RGE_RXCFG_INDIV |
103 RGE_RXCFG_MULTI | RGE_RXCFG_BROAD | RGE_RXCFG_RUNT |
104 RGE_RXCFG_ERRPKT);
105
106 /* Enable RXDV gate. */
107 RGE_SETBIT_1(sc, RGE_PPSW, 0x08);
108
109 RGE_SETBIT_1(sc, RGE_CMD, RGE_CMD_STOPREQ);
110 DELAY(200);
111
112 for (i = 0; i < 3000; i++) {
113 DELAY(50);
114 if ((RGE_READ_1(sc, RGE_MCUCMD) & (RGE_MCUCMD_RXFIFO_EMPTY |
115 RGE_MCUCMD_TXFIFO_EMPTY)) == (RGE_MCUCMD_RXFIFO_EMPTY |
116 RGE_MCUCMD_TXFIFO_EMPTY))
117 break;
118 }
119 if (sc->rge_type != MAC_R25) {
120 for (i = 0; i < 3000; i++) {
121 DELAY(50);
122 if ((RGE_READ_2(sc, RGE_IM) & 0x0103) == 0x0103)
123 break;
124 }
125 }
126
127 RGE_WRITE_1(sc, RGE_CMD,
128 RGE_READ_1(sc, RGE_CMD) & (RGE_CMD_TXENB | RGE_CMD_RXENB));
129
130 /* Soft reset. */
131 RGE_WRITE_1(sc, RGE_CMD, RGE_CMD_RESET);
132
133 for (i = 0; i < RGE_TIMEOUT; i++) {
134 DELAY(100);
135 if (!(RGE_READ_1(sc, RGE_CMD) & RGE_CMD_RESET))
136 break;
137 }
138 if (i == RGE_TIMEOUT) {
139 RGE_PRINT_ERROR(sc, "reset never completed!\n");
140 return ETIMEDOUT;
141 }
142
143 return 0;
144 }
145
146 /**
147 * @brief Do initial chip power-on and setup.
148 *
149 * Must be called with the driver lock held.
150 */
151 int
rge_chipinit(struct rge_softc * sc)152 rge_chipinit(struct rge_softc *sc)
153 {
154 int error;
155
156 RGE_ASSERT_LOCKED(sc);
157
158 if ((error = rge_exit_oob(sc)) != 0)
159 return error;
160 rge_set_phy_power(sc, 1);
161 rge_hw_init(sc);
162 rge_hw_reset(sc);
163
164 return 0;
165 }
166
167 static void
rge_set_phy_power(struct rge_softc * sc,int on)168 rge_set_phy_power(struct rge_softc *sc, int on)
169 {
170 int i;
171
172 if (on) {
173 RGE_SETBIT_1(sc, RGE_PMCH, 0xc0);
174
175 rge_write_phy(sc, 0, MII_BMCR, BMCR_AUTOEN);
176
177 for (i = 0; i < RGE_TIMEOUT; i++) {
178 if ((rge_read_phy_ocp(sc, 0xa420) & 0x0007) == 3)
179 break;
180 DELAY(1000);
181 }
182 } else {
183 rge_write_phy(sc, 0, MII_BMCR, BMCR_AUTOEN | BMCR_PDOWN);
184 RGE_CLRBIT_1(sc, RGE_PMCH, 0x80);
185 RGE_CLRBIT_1(sc, RGE_PPSW, 0x40);
186 }
187 }
188
189 void
rge_mac_config_mcu(struct rge_softc * sc,enum rge_mac_type type)190 rge_mac_config_mcu(struct rge_softc *sc, enum rge_mac_type type)
191 {
192 uint16_t reg;
193 int i, npages;
194
195 if (type == MAC_R25) {
196 for (npages = 0; npages < 3; npages++) {
197 rge_switch_mcu_ram_page(sc, npages);
198 for (i = 0; i < nitems(rtl8125_mac_bps); i++) {
199 if (npages == 0)
200 rge_write_mac_ocp(sc,
201 rtl8125_mac_bps[i].reg,
202 rtl8125_mac_bps[i].val);
203 else if (npages == 1)
204 rge_write_mac_ocp(sc,
205 rtl8125_mac_bps[i].reg, 0);
206 else {
207 if (rtl8125_mac_bps[i].reg < 0xf9f8)
208 rge_write_mac_ocp(sc,
209 rtl8125_mac_bps[i].reg, 0);
210 }
211 }
212 if (npages == 2) {
213 rge_write_mac_ocp(sc, 0xf9f8, 0x6486);
214 rge_write_mac_ocp(sc, 0xf9fa, 0x0b15);
215 rge_write_mac_ocp(sc, 0xf9fc, 0x090e);
216 rge_write_mac_ocp(sc, 0xf9fe, 0x1139);
217 }
218 }
219 rge_write_mac_ocp(sc, 0xfc26, 0x8000);
220 rge_write_mac_ocp(sc, 0xfc2a, 0x0540);
221 rge_write_mac_ocp(sc, 0xfc2e, 0x0a06);
222 rge_write_mac_ocp(sc, 0xfc30, 0x0eb8);
223 rge_write_mac_ocp(sc, 0xfc32, 0x3a5c);
224 rge_write_mac_ocp(sc, 0xfc34, 0x10a8);
225 rge_write_mac_ocp(sc, 0xfc40, 0x0d54);
226 rge_write_mac_ocp(sc, 0xfc42, 0x0e24);
227 rge_write_mac_ocp(sc, 0xfc48, 0x307a);
228 } else if (type == MAC_R25B) {
229 rge_switch_mcu_ram_page(sc, 0);
230 for (i = 0; i < nitems(rtl8125b_mac_bps); i++) {
231 rge_write_mac_ocp(sc, rtl8125b_mac_bps[i].reg,
232 rtl8125b_mac_bps[i].val);
233 }
234 } else if (type == MAC_R25D_1) {
235 for (npages = 0; npages < 3; npages++) {
236 rge_switch_mcu_ram_page(sc, npages);
237
238 rge_write_mac_ocp(sc, 0xf800,
239 (npages == 0) ? 0xe002 : 0);
240 rge_write_mac_ocp(sc, 0xf802,
241 (npages == 0) ? 0xe006 : 0);
242 rge_write_mac_ocp(sc, 0xf804,
243 (npages == 0) ? 0x4166 : 0);
244 rge_write_mac_ocp(sc, 0xf806,
245 (npages == 0) ? 0x9cf6 : 0);
246 rge_write_mac_ocp(sc, 0xf808,
247 (npages == 0) ? 0xc002 : 0);
248 rge_write_mac_ocp(sc, 0xf80a,
249 (npages == 0) ? 0xb800 : 0);
250 rge_write_mac_ocp(sc, 0xf80c,
251 (npages == 0) ? 0x14a4 : 0);
252 rge_write_mac_ocp(sc, 0xf80e,
253 (npages == 0) ? 0xc102 : 0);
254 rge_write_mac_ocp(sc, 0xf810,
255 (npages == 0) ? 0xb900 : 0);
256
257 for (reg = 0xf812; reg <= 0xf9f6; reg += 2)
258 rge_write_mac_ocp(sc, reg, 0);
259
260 rge_write_mac_ocp(sc, 0xf9f8,
261 (npages == 2) ? 0x6938 : 0);
262 rge_write_mac_ocp(sc, 0xf9fa,
263 (npages == 2) ? 0x0a18 : 0);
264 rge_write_mac_ocp(sc, 0xf9fc,
265 (npages == 2) ? 0x0217 : 0);
266 rge_write_mac_ocp(sc, 0xf9fe,
267 (npages == 2) ? 0x0d2a : 0);
268 }
269 rge_write_mac_ocp(sc, 0xfc26, 0x8000);
270 rge_write_mac_ocp(sc, 0xfc28, 0x14a2);
271 rge_write_mac_ocp(sc, 0xfc48, 0x0001);
272 } else if (type == MAC_R25D_2) {
273 for (npages = 0; npages < 3; npages++) {
274 rge_switch_mcu_ram_page(sc, npages);
275
276 for (i = 0; i < nitems(rtl8125d_2_mac_bps); i++) {
277 if (npages == 0)
278 rge_write_mac_ocp(sc,
279 rtl8125d_2_mac_bps[i].reg,
280 rtl8125d_2_mac_bps[i].val);
281 else
282 rge_write_mac_ocp(sc,
283 rtl8125d_2_mac_bps[i].reg, 0);
284 }
285
286 for (reg = 0xf884; reg <= 0xf9f6; reg += 2)
287 rge_write_mac_ocp(sc, reg, 0);
288
289 rge_write_mac_ocp(sc, 0xf9f8,
290 (npages == 2) ? 0x6938 : 0);
291 rge_write_mac_ocp(sc, 0xf9fa,
292 (npages == 2) ? 0x0a19: 0);
293 rge_write_mac_ocp(sc, 0xf9fc,
294 (npages == 2) ? 0x030e: 0);
295 rge_write_mac_ocp(sc, 0xf9fe,
296 (npages == 2) ? 0x0b2f: 0);
297 }
298 rge_write_mac_ocp(sc, 0xfc26, 0x8000);
299 rge_write_mac_ocp(sc, 0xfc28, 0x2382);
300 rge_write_mac_ocp(sc, 0xfc48, 0x0001);
301 }
302 }
303
304 void
rge_mac_config_ext_mcu(struct rge_softc * sc,enum rge_mac_type type)305 rge_mac_config_ext_mcu(struct rge_softc *sc, enum rge_mac_type type)
306 {
307 const struct rge_mac_bps *bps;
308 uint64_t mcodever = 0;
309 int i;
310
311 /* Read microcode version. */
312 rge_switch_mcu_ram_page(sc, 2);
313 sc->rge_mcodever = 0;
314 for (i = 0; i < 8; i += 2) {
315 sc->rge_mcodever <<= 16;
316 sc->rge_mcodever |= rge_read_mac_ocp(sc, 0xf9f8 + i);
317 }
318 rge_switch_mcu_ram_page(sc, 0);
319
320 if (type == MAC_R26_1) {
321 bps = &rtl8126_1_mac_bps;
322 mcodever =
323 rge_mcu_get_bin_version(rtl8126_1_mac_bps_vals, bps->count);
324 if (sc->rge_mcodever != mcodever) {
325 /* Switch to page 0. */
326 rge_switch_mcu_ram_page(sc, 0);
327 for (i = 0; i < bps->count; i++)
328 rge_write_mac_ocp(sc, bps->regs[i],
329 bps->vals[i]);
330 }
331 rge_write_mac_ocp(sc, 0xfc26, 0x8000);
332 rge_write_mac_ocp(sc, 0xfc2c, 0x2360);
333 rge_write_mac_ocp(sc, 0xfc2e, 0x14a4);
334 rge_write_mac_ocp(sc, 0xfc30, 0x415e);
335 rge_write_mac_ocp(sc, 0xfc32, 0x41e4);
336 rge_write_mac_ocp(sc, 0xfc34, 0x4280);
337 rge_write_mac_ocp(sc, 0xfc36, 0x234a);
338 rge_write_mac_ocp(sc, 0xfc48, 0x00fc);
339 } else if (type == MAC_R26_2) {
340 bps = &rtl8126_2_mac_bps;
341 mcodever =
342 rge_mcu_get_bin_version(rtl8126_2_mac_bps_vals, bps->count);
343 if (sc->rge_mcodever != mcodever) {
344 /* Switch to page 0. */
345 rge_switch_mcu_ram_page(sc, 0);
346 for (i = 0; i < 256; i++)
347 rge_write_mac_ocp(sc, bps->regs[i],
348 bps->vals[i]);
349 /* Switch to page 1. */
350 rge_switch_mcu_ram_page(sc, 1);
351 for (; i < bps->count; i++)
352 rge_write_mac_ocp(sc, bps->regs[i],
353 bps->vals[i]);
354 }
355 rge_write_mac_ocp(sc, 0xfc26, 0x8000);
356 rge_write_mac_ocp(sc, 0xfc2c, 0x14a4);
357 rge_write_mac_ocp(sc, 0xfc2e, 0x4176);
358 rge_write_mac_ocp(sc, 0xfc30, 0x41fc);
359 rge_write_mac_ocp(sc, 0xfc32, 0x4298);
360 rge_write_mac_ocp(sc, 0xfc3a, 0x234a);
361 rge_write_mac_ocp(sc, 0xfc48, 0x023c);
362 } else if (type == MAC_R27) {
363 bps = &rtl8127_mac_bps;
364 mcodever =
365 rge_mcu_get_bin_version(rtl8127_mac_bps_vals, bps->count);
366 if (sc->rge_mcodever != mcodever) {
367 /* Switch to page 0. */
368 rge_switch_mcu_ram_page(sc, 0);
369 for (i = 0; i < 256; i++)
370 rge_write_mac_ocp(sc, bps->regs[i],
371 bps->vals[i]);
372 /* Switch to page 1. */
373 rge_switch_mcu_ram_page(sc, 1);
374 for (; i < bps->count; i++)
375 rge_write_mac_ocp(sc, bps->regs[i],
376 bps->vals[i]);
377 }
378 rge_write_mac_ocp(sc, 0xfc26, 0x8000);
379 rge_write_mac_ocp(sc, 0xfc28, 0x1520);
380 rge_write_mac_ocp(sc, 0xfc2a, 0x41e0);
381 rge_write_mac_ocp(sc, 0xfc2c, 0x508c);
382 rge_write_mac_ocp(sc, 0xfc2e, 0x50f6);
383 rge_write_mac_ocp(sc, 0xfc30, 0x34fa);
384 rge_write_mac_ocp(sc, 0xfc32, 0x0166);
385 rge_write_mac_ocp(sc, 0xfc34, 0x1a6a);
386 rge_write_mac_ocp(sc, 0xfc36, 0x1a2c);
387 rge_write_mac_ocp(sc, 0xfc48, 0x00ff);
388 }
389
390 /* Write microcode version. */
391 rge_mcu_set_version(sc, mcodever);
392 };
393
394 static uint64_t
rge_mcu_get_bin_version(const uint16_t * mac_bps,uint16_t entries)395 rge_mcu_get_bin_version(const uint16_t *mac_bps, uint16_t entries)
396 {
397 uint64_t binver = 0;
398 int i;
399
400 for (i = 0; i < 4; i++) {
401 binver <<= 16;
402 binver |= mac_bps[entries - 4 + i];
403 }
404
405 return binver;
406 }
407
408 static void
rge_mcu_set_version(struct rge_softc * sc,uint64_t mcodever)409 rge_mcu_set_version(struct rge_softc *sc, uint64_t mcodever)
410 {
411 int i;
412
413 /* Switch to page 2. */
414 rge_switch_mcu_ram_page(sc, 2);
415
416 for (i = 0; i < 8; i += 2) {
417 rge_write_mac_ocp(sc, 0xf9f8 + 6 - i, (uint16_t)mcodever);
418 mcodever >>= 16;
419 }
420
421 /* Switch back to page 0. */
422 rge_switch_mcu_ram_page(sc, 0);
423 }
424
425 void
rge_ephy_config(struct rge_softc * sc)426 rge_ephy_config(struct rge_softc *sc)
427 {
428 switch (sc->rge_type) {
429 case MAC_R25:
430 rge_ephy_config_mac_r25(sc);
431 break;
432 case MAC_R25B:
433 rge_ephy_config_mac_r25b(sc);
434 break;
435 case MAC_R27:
436 rge_ephy_config_mac_r27(sc);
437 break;
438 default:
439 break; /* Nothing to do. */
440 }
441 }
442
443 static void
rge_ephy_config_mac_r25(struct rge_softc * sc)444 rge_ephy_config_mac_r25(struct rge_softc *sc)
445 {
446 uint16_t val;
447 int i;
448
449 for (i = 0; i < nitems(mac_r25_ephy); i++)
450 rge_write_ephy(sc, mac_r25_ephy[i].reg, mac_r25_ephy[i].val);
451
452 val = rge_read_ephy(sc, 0x002a) & ~0x7000;
453 rge_write_ephy(sc, 0x002a, val | 0x3000);
454 RGE_EPHY_CLRBIT(sc, 0x0019, 0x0040);
455 RGE_EPHY_SETBIT(sc, 0x001b, 0x0e00);
456 RGE_EPHY_CLRBIT(sc, 0x001b, 0x7000);
457 rge_write_ephy(sc, 0x0002, 0x6042);
458 rge_write_ephy(sc, 0x0006, 0x0014);
459 val = rge_read_ephy(sc, 0x006a) & ~0x7000;
460 rge_write_ephy(sc, 0x006a, val | 0x3000);
461 RGE_EPHY_CLRBIT(sc, 0x0059, 0x0040);
462 RGE_EPHY_SETBIT(sc, 0x005b, 0x0e00);
463 RGE_EPHY_CLRBIT(sc, 0x005b, 0x7000);
464 rge_write_ephy(sc, 0x0042, 0x6042);
465 rge_write_ephy(sc, 0x0046, 0x0014);
466 }
467
468 static void
rge_ephy_config_mac_r25b(struct rge_softc * sc)469 rge_ephy_config_mac_r25b(struct rge_softc *sc)
470 {
471 int i;
472
473 for (i = 0; i < nitems(mac_r25b_ephy); i++)
474 rge_write_ephy(sc, mac_r25b_ephy[i].reg, mac_r25b_ephy[i].val);
475 }
476
477 static void
rge_ephy_config_mac_r27(struct rge_softc * sc)478 rge_ephy_config_mac_r27(struct rge_softc *sc)
479 {
480 int i;
481
482 for (i = 0; i < nitems(mac_r27_ephy); i++)
483 rge_r27_write_ephy(sc, mac_r27_ephy[i].reg,
484 mac_r27_ephy[i].val);
485
486 /* Clear extended address. */
487 rge_write_ephy(sc, RGE_EPHYAR_EXT_ADDR, 0);
488 }
489
490 int
rge_phy_config(struct rge_softc * sc)491 rge_phy_config(struct rge_softc *sc)
492 {
493 uint16_t val = 0;
494 int i;
495
496 rge_ephy_config(sc);
497
498 /* PHY reset. */
499 rge_write_phy(sc, 0, MII_ANAR,
500 rge_read_phy(sc, 0, MII_ANAR) &
501 ~(ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10));
502 rge_write_phy(sc, 0, MII_100T2CR,
503 rge_read_phy(sc, 0, MII_100T2CR) &
504 ~(GTCR_ADV_1000TFDX | GTCR_ADV_1000THDX));
505 switch (sc->rge_type) {
506 case MAC_R27:
507 val |= RGE_ADV_10000TFDX;
508 /* fallthrough */
509 case MAC_R26_1:
510 case MAC_R26_2:
511 val |= RGE_ADV_5000TFDX;
512 /* fallthrough */
513 default:
514 val |= RGE_ADV_2500TFDX;
515 break;
516 }
517 RGE_PHY_CLRBIT(sc, 0xa5d4, val);
518 rge_write_phy(sc, 0, MII_BMCR, BMCR_RESET | BMCR_AUTOEN |
519 BMCR_STARTNEG);
520 for (i = 0; i < 2500; i++) {
521 if (!(rge_read_phy(sc, 0, MII_BMCR) & BMCR_RESET))
522 break;
523 DELAY(1000);
524 }
525 if (i == 2500) {
526 RGE_PRINT_ERROR(sc, "PHY reset failed\n");
527 return (ETIMEDOUT);
528 }
529
530 /* Read ram code version. */
531 rge_write_phy_ocp(sc, 0xa436, 0x801e);
532 sc->rge_rcodever = rge_read_phy_ocp(sc, 0xa438);
533
534 switch (sc->rge_type) {
535 case MAC_R25:
536 rge_phy_config_mac_r25(sc);
537 break;
538 case MAC_R25B:
539 rge_phy_config_mac_r25b(sc);
540 break;
541 case MAC_R25D_1:
542 rge_phy_config_mac_r25d_1(sc);
543 break;
544 case MAC_R25D_2:
545 rge_phy_config_mac_r25d_2(sc);
546 break;
547 case MAC_R26_1:
548 rge_phy_config_mac_r26_1(sc);
549 break;
550 case MAC_R26_2:
551 rge_phy_config_mac_r26_2(sc);
552 break;
553 case MAC_R27:
554 rge_phy_config_mac_r27(sc);
555 break;
556 default:
557 break; /* Can't happen. */
558 }
559
560 RGE_PHY_CLRBIT(sc, 0xa5b4, 0x8000);
561
562 /* Disable EEE. */
563 RGE_MAC_CLRBIT(sc, 0xe040, 0x0003);
564 if (sc->rge_type == MAC_R25) {
565 RGE_MAC_CLRBIT(sc, 0xeb62, 0x0006);
566 RGE_PHY_CLRBIT(sc, 0xa432, 0x0010);
567 } else if (sc->rge_type == MAC_R25B || RGE_TYPE_R25D(sc))
568 RGE_PHY_SETBIT(sc, 0xa432, 0x0010);
569
570 RGE_PHY_CLRBIT(sc, 0xa5d0, (sc->rge_type == MAC_R27) ? 0x000e : 0x0006);
571 RGE_PHY_CLRBIT(sc, 0xa6d4, 0x0001);
572 if (RGE_TYPE_R26(sc) || sc->rge_type == MAC_R27)
573 RGE_PHY_CLRBIT(sc, 0xa6d4, 0x0002);
574 RGE_PHY_CLRBIT(sc, 0xa6d8, 0x0010);
575 RGE_PHY_CLRBIT(sc, 0xa428, 0x0080);
576 RGE_PHY_CLRBIT(sc, 0xa4a2, 0x0200);
577
578 /* Disable advanced EEE. */
579 RGE_MAC_CLRBIT(sc, 0xe052, 0x0001);
580 RGE_PHY_CLRBIT(sc, 0xa442, 0x3000);
581 RGE_PHY_CLRBIT(sc, 0xa430, 0x8000);
582
583 return (0);
584 }
585
586 static void
rge_phy_config_mac_r27(struct rge_softc * sc)587 rge_phy_config_mac_r27(struct rge_softc *sc)
588 {
589 uint16_t val;
590 int i;
591 static const uint16_t mac_cfg_value[] =
592 { 0x815a, 0x0150, 0x81f4, 0x0150, 0x828e, 0x0150, 0x81b1, 0x0000,
593 0x824b, 0x0000, 0x82e5, 0x0000 };
594
595 static const uint16_t mac_cfg2_value[] =
596 { 0x88d7, 0x01a0, 0x88d9, 0x01a0, 0x8ffa, 0x002a, 0x8fee, 0xffdf,
597 0x8ff0, 0xffff, 0x8ff2, 0x0a4a, 0x8ff4, 0xaa5a, 0x8ff6, 0x0a4a,
598 0x8ff8, 0xaa5a };
599
600 static const uint16_t mac_cfg_a438_value[] =
601 { 0x003b, 0x0086, 0x00b7, 0x00db, 0x00fe, 0x00fe, 0x00fe, 0x00fe,
602 0x00c3, 0x0078, 0x0047, 0x0023 };
603
604 rge_phy_config_mcu(sc, RGE_MAC_R27_RCODE_VER);
605
606 rge_write_phy_ocp(sc, 0xa4d2, 0x0000);
607 rge_read_phy_ocp(sc, 0xa4d4);
608
609 RGE_PHY_CLRBIT(sc, 0xa442, 0x0800);
610 rge_write_phy_ocp(sc, 0xa436, 0x8415);
611 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00;
612 rge_write_phy_ocp(sc, 0xa438, val | 0x9300);
613 rge_write_phy_ocp(sc, 0xa436, 0x81a3);
614 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00;
615 rge_write_phy_ocp(sc, 0xa438, val | 0x0f00);
616 rge_write_phy_ocp(sc, 0xa436, 0x81ae);
617 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00;
618 rge_write_phy_ocp(sc, 0xa438, val | 0x0f00);
619 rge_write_phy_ocp(sc, 0xa436, 0x81b9);
620 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00;
621 rge_write_phy_ocp(sc, 0xa438, val | 0xb900);
622 rge_write_phy_ocp(sc, 0xb87c, 0x83b0);
623 RGE_PHY_CLRBIT(sc,0xb87e, 0x0e00);
624 rge_write_phy_ocp(sc, 0xb87c, 0x83c5);
625 RGE_PHY_CLRBIT(sc, 0xb87e, 0x0e00);
626 rge_write_phy_ocp(sc, 0xb87c, 0x83da);
627 RGE_PHY_CLRBIT(sc, 0xb87e, 0x0e00);
628 rge_write_phy_ocp(sc, 0xb87c, 0x83ef);
629 RGE_PHY_CLRBIT(sc, 0xb87e, 0x0e00);
630 val = rge_read_phy_ocp(sc, 0xbf38) & ~0x01f0;
631 rge_write_phy_ocp(sc, 0xbf38, val | 0x0160);
632 val = rge_read_phy_ocp(sc, 0xbf3a) & ~0x001f;
633 rge_write_phy_ocp(sc, 0xbf3a, val | 0x0014);
634 RGE_PHY_CLRBIT(sc, 0xbf28, 0x6000);
635 RGE_PHY_CLRBIT(sc, 0xbf2c, 0xc000);
636 val = rge_read_phy_ocp(sc, 0xbf28) & ~0x1fff;
637 rge_write_phy_ocp(sc, 0xbf28, val | 0x0187);
638 val = rge_read_phy_ocp(sc, 0xbf2a) & ~0x003f;
639 rge_write_phy_ocp(sc, 0xbf2a, val | 0x0003);
640 rge_write_phy_ocp(sc, 0xa436, 0x8173);
641 rge_write_phy_ocp(sc, 0xa438, 0x8620);
642 rge_write_phy_ocp(sc, 0xa436, 0x8175);
643 rge_write_phy_ocp(sc, 0xa438, 0x8671);
644 rge_write_phy_ocp(sc, 0xa436, 0x817c);
645 RGE_PHY_SETBIT(sc, 0xa438, 0x2000);
646 rge_write_phy_ocp(sc, 0xa436, 0x8187);
647 RGE_PHY_SETBIT(sc, 0xa438, 0x2000);
648 rge_write_phy_ocp(sc, 0xA436, 0x8192);
649 RGE_PHY_SETBIT(sc, 0xA438, 0x2000);
650 rge_write_phy_ocp(sc, 0xA436, 0x819D);
651 RGE_PHY_SETBIT(sc, 0xA438, 0x2000);
652 rge_write_phy_ocp(sc, 0xA436, 0x81A8);
653 RGE_PHY_CLRBIT(sc, 0xA438, 0x2000);
654 rge_write_phy_ocp(sc, 0xA436, 0x81B3);
655 RGE_PHY_CLRBIT(sc, 0xA438, 0x2000);
656 rge_write_phy_ocp(sc, 0xA436, 0x81BE);
657 RGE_PHY_SETBIT(sc, 0xA438, 0x2000);
658 rge_write_phy_ocp(sc, 0xa436, 0x817d);
659 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00;
660 rge_write_phy_ocp(sc, 0xa438, val | 0xa600);
661 rge_write_phy_ocp(sc, 0xa436, 0x8188);
662 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00;
663 rge_write_phy_ocp(sc, 0xa438, val | 0xa600);
664 rge_write_phy_ocp(sc, 0xa436, 0x8193);
665 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00;
666 rge_write_phy_ocp(sc, 0xa438, val | 0xa600);
667 rge_write_phy_ocp(sc, 0xa436, 0x819e);
668 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00;
669 rge_write_phy_ocp(sc, 0xa438, val | 0xa600);
670 rge_write_phy_ocp(sc, 0xa436, 0x81a9);
671 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00;
672 rge_write_phy_ocp(sc, 0xa438, val | 0x1400);
673 rge_write_phy_ocp(sc, 0xa436, 0x81b4);
674 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00;
675 rge_write_phy_ocp(sc, 0xa438, val | 0x1400);
676 rge_write_phy_ocp(sc, 0xa436, 0x81bf);
677 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00;
678 rge_write_phy_ocp(sc, 0xa438, val | 0xa600);
679 RGE_PHY_CLRBIT(sc, 0xaeaa, 0x0028);
680 rge_write_phy_ocp(sc, 0xb87c, 0x84f0);
681 rge_write_phy_ocp(sc, 0xb87e, 0x201c);
682 rge_write_phy_ocp(sc, 0xb87c, 0x84f2);
683 rge_write_phy_ocp(sc, 0xb87e, 0x3117);
684 rge_write_phy_ocp(sc, 0xaec6, 0x0000);
685 rge_write_phy_ocp(sc, 0xae20, 0xffff);
686 rge_write_phy_ocp(sc, 0xaece, 0xffff);
687 rge_write_phy_ocp(sc, 0xaed2, 0xffff);
688 rge_write_phy_ocp(sc, 0xaec8, 0x0000);
689 RGE_PHY_CLRBIT(sc, 0xaed0, 0x0001);
690 rge_write_phy_ocp(sc, 0xadb8, 0x0150);
691 rge_write_phy_ocp(sc, 0xb87c, 0x8197);
692 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
693 rge_write_phy_ocp(sc, 0xb87e, val | 0x5000);
694 rge_write_phy_ocp(sc, 0xb87c, 0x8231);
695 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
696 rge_write_phy_ocp(sc, 0xb87e, val | 0x5000);
697 rge_write_phy_ocp(sc, 0xb87c, 0x82cb);
698 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
699 rge_write_phy_ocp(sc, 0xb87e, val | 0x5000);
700 rge_write_phy_ocp(sc, 0xb87c, 0x82cd);
701 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
702 rge_write_phy_ocp(sc, 0xb87e, val | 0x5700);
703 rge_write_phy_ocp(sc, 0xb87c, 0x8233);
704 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
705 rge_write_phy_ocp(sc, 0xb87e, val | 0x5700);
706 rge_write_phy_ocp(sc, 0xb87c, 0x8199);
707 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
708 rge_write_phy_ocp(sc, 0xb87e, val | 0x5700);
709 for (i = 0; i < nitems(mac_cfg_value); i+=2) {
710 rge_write_phy_ocp(sc, 0xb87c, mac_cfg_value[i]);
711 rge_write_phy_ocp(sc, 0xb87e, mac_cfg_value[i + 1]);
712 }
713 rge_write_phy_ocp(sc, 0xb87c, 0x84f7);
714 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
715 rge_write_phy_ocp(sc, 0xb87e, val | 0x2800);
716 RGE_PHY_SETBIT(sc, 0xaec2, 0x1000);
717 rge_write_phy_ocp(sc, 0xb87c, 0x81b3);
718 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
719 rge_write_phy_ocp(sc, 0xb87e, val | 0xad00);
720 rge_write_phy_ocp(sc, 0xb87c, 0x824d);
721 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
722 rge_write_phy_ocp(sc, 0xb87e, val | 0xad00);
723 rge_write_phy_ocp(sc, 0xb87c, 0x82e7);
724 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
725 rge_write_phy_ocp(sc, 0xb87e, val | 0xad00);
726 val = rge_read_phy_ocp(sc, 0xae4e) & ~0x000f;
727 rge_write_phy_ocp(sc, 0xae4e, val | 0x0001);
728 rge_write_phy_ocp(sc, 0xb87c, 0x82ce);
729 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xf000;
730 rge_write_phy_ocp(sc, 0xb87e, val | 0x4000);
731 rge_write_phy_ocp(sc, 0xb87c, 0x84ac);
732 rge_write_phy_ocp(sc, 0xb87e, 0x0000);
733 rge_write_phy_ocp(sc, 0xb87c, 0x84ae);
734 rge_write_phy_ocp(sc, 0xb87e, 0x0000);
735 rge_write_phy_ocp(sc, 0xb87c, 0x84b0);
736 rge_write_phy_ocp(sc, 0xb87e, 0xf818);
737 rge_write_phy_ocp(sc, 0xb87c, 0x84b2);
738 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
739 rge_write_phy_ocp(sc, 0xb87e, val | 0x6000);
740 rge_write_phy_ocp(sc, 0xb87c, 0x8ffc);
741 rge_write_phy_ocp(sc, 0xb87e, 0x6008);
742 rge_write_phy_ocp(sc, 0xb87c, 0x8ffe);
743 rge_write_phy_ocp(sc, 0xb87e, 0xf450);
744 rge_write_phy_ocp(sc, 0xb87c, 0x8015);
745 RGE_PHY_SETBIT(sc, 0xb87e, 0x0200);
746 rge_write_phy_ocp(sc, 0xb87c, 0x8016);
747 RGE_PHY_CLRBIT(sc, 0xb87e, 0x0800);
748 rge_write_phy_ocp(sc, 0xb87c, 0x8fe6);
749 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
750 rge_write_phy_ocp(sc, 0xb87e, val | 0x0800);
751 rge_write_phy_ocp(sc, 0xb87c, 0x8fe4);
752 rge_write_phy_ocp(sc, 0xb87e, 0x2114);
753 rge_write_phy_ocp(sc, 0xb87c, 0x8647);
754 rge_write_phy_ocp(sc, 0xb87e, 0xa7B1);
755 rge_write_phy_ocp(sc, 0xb87c, 0x8649);
756 rge_write_phy_ocp(sc, 0xb87e, 0xbbca);
757 rge_write_phy_ocp(sc, 0xb87c, 0x864b);
758 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
759 rge_write_phy_ocp(sc, 0xb87e, val | 0xdc00);
760 rge_write_phy_ocp(sc, 0xb87c, 0x8154);
761 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xc000;
762 rge_write_phy_ocp(sc, 0xb87e, val | 0x4000);
763 rge_write_phy_ocp(sc, 0xb87c, 0x8158);
764 RGE_PHY_CLRBIT(sc, 0xb87e, 0xc000);
765 rge_write_phy_ocp(sc, 0xb87c, 0x826c);
766 rge_write_phy_ocp(sc, 0xb87e, 0xffff);
767 rge_write_phy_ocp(sc, 0xb87c, 0x826e);
768 rge_write_phy_ocp(sc, 0xb87e, 0xffff);
769 rge_write_phy_ocp(sc, 0xb87c, 0x8872);
770 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
771 rge_write_phy_ocp(sc, 0xb87e, val | 0x0e00);
772 rge_write_phy_ocp(sc, 0xa436, 0x8012);
773 RGE_PHY_SETBIT(sc, 0xa438, 0x0800);
774 rge_write_phy_ocp(sc, 0xa436, 0x8012);
775 RGE_PHY_SETBIT(sc, 0xa438, 0x4000);
776 RGE_PHY_SETBIT(sc, 0xb576, 0x0001);
777 rge_write_phy_ocp(sc, 0xa436, 0x834a);
778 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00;
779 rge_write_phy_ocp(sc, 0xa438, val | 0x0700);
780 rge_write_phy_ocp(sc, 0xb87c, 0x8217);
781 val = rge_read_phy_ocp(sc, 0xb87e) & ~0x3f00;
782 rge_write_phy_ocp(sc, 0xb87e, val | 0x2a00);
783 rge_write_phy_ocp(sc, 0xa436, 0x81b1);
784 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00;
785 rge_write_phy_ocp(sc, 0xa438, val | 0x0b00);
786 rge_write_phy_ocp(sc, 0xb87c, 0x8fed);
787 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
788 rge_write_phy_ocp(sc, 0xb87e, val | 0x4e00);
789 rge_write_phy_ocp(sc, 0xb87c, 0x88ac);
790 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
791 rge_write_phy_ocp(sc, 0xb87e, val | 0x2300);
792 RGE_PHY_SETBIT(sc, 0xbf0c, 0x3800);
793 rge_write_phy_ocp(sc, 0xb87c, 0x88de);
794 RGE_PHY_CLRBIT(sc, 0xb87e, 0xFF00);
795 rge_write_phy_ocp(sc, 0xb87c, 0x80B4);
796 rge_write_phy_ocp(sc, 0xb87e, 0x5195);
797 rge_write_phy_ocp(sc, 0xa436, 0x8370);
798 rge_write_phy_ocp(sc, 0xa438, 0x8671);
799 rge_write_phy_ocp(sc, 0xa436, 0x8372);
800 rge_write_phy_ocp(sc, 0xa438, 0x86c8);
801 rge_write_phy_ocp(sc, 0xa436, 0x8401);
802 rge_write_phy_ocp(sc, 0xa438, 0x86c8);
803 rge_write_phy_ocp(sc, 0xa436, 0x8403);
804 rge_write_phy_ocp(sc, 0xa438, 0x86da);
805 rge_write_phy_ocp(sc, 0xa436, 0x8406);
806 val = rge_read_phy_ocp(sc, 0xa438) & ~0x1800;
807 rge_write_phy_ocp(sc, 0xa438, val | 0x1000);
808 rge_write_phy_ocp(sc, 0xa436, 0x8408);
809 val = rge_read_phy_ocp(sc, 0xa438) & ~0x1800;
810 rge_write_phy_ocp(sc, 0xa438, val | 0x1000);
811 rge_write_phy_ocp(sc, 0xa436, 0x840a);
812 val = rge_read_phy_ocp(sc, 0xa438) & ~0x1800;
813 rge_write_phy_ocp(sc, 0xa438, val | 0x1000);
814 rge_write_phy_ocp(sc, 0xa436, 0x840c);
815 val = rge_read_phy_ocp(sc, 0xa438) & ~0x1800;
816 rge_write_phy_ocp(sc, 0xa438, val | 0x1000);
817 rge_write_phy_ocp(sc, 0xa436, 0x840e);
818 val = rge_read_phy_ocp(sc, 0xa438) & ~0x1800;
819 rge_write_phy_ocp(sc, 0xa438, val | 0x1000);
820 rge_write_phy_ocp(sc, 0xa436, 0x8410);
821 val = rge_read_phy_ocp(sc, 0xa438) & ~0x1800;
822 rge_write_phy_ocp(sc, 0xa438, val | 0x1000);
823 rge_write_phy_ocp(sc, 0xa436, 0x8412);
824 val = rge_read_phy_ocp(sc, 0xa438) & ~0x1800;
825 rge_write_phy_ocp(sc, 0xa438, val | 0x1000);
826 rge_write_phy_ocp(sc, 0xa436, 0x8414);
827 val = rge_read_phy_ocp(sc, 0xa438) & ~0x1800;
828 rge_write_phy_ocp(sc, 0xa438, val | 0x1000);
829 rge_write_phy_ocp(sc, 0xa436, 0x8416);
830 val = rge_read_phy_ocp(sc, 0xa438) & ~0x1800;
831 rge_write_phy_ocp(sc, 0xa438, val | 0x1000);
832 rge_write_phy_ocp(sc, 0xa436, 0x82bd);
833 rge_write_phy_ocp(sc, 0xa438, 0x1f40);
834 val = rge_read_phy_ocp(sc, 0xbfb4) & ~0x07ff;
835 rge_write_phy_ocp(sc, 0xbfb4, val | 0x0328);
836 rge_write_phy_ocp(sc, 0xbfb6, 0x3e14);
837 rge_write_phy_ocp(sc, 0xa436, 0x81c4);
838 for (i = 0; i < nitems(mac_cfg_a438_value); i++)
839 rge_write_phy_ocp(sc, 0xa438, mac_cfg_a438_value[i]);
840 for (i = 0; i < nitems(mac_cfg2_value); i+=2) {
841 rge_write_phy_ocp(sc, 0xb87c, mac_cfg2_value[i]);
842 rge_write_phy_ocp(sc, 0xb87e, mac_cfg2_value[i + 1]);
843 }
844 rge_write_phy_ocp(sc, 0xb87c, 0x88d5);
845 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
846 rge_write_phy_ocp(sc, 0xb87e, val | 0x0200);
847 rge_write_phy_ocp(sc, 0xa436, 0x84bb);
848 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00;
849 rge_write_phy_ocp(sc, 0xa438, val | 0x0a00);
850 rge_write_phy_ocp(sc, 0xa436, 0x84c0);
851 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00;
852 rge_write_phy_ocp(sc, 0xa438, val | 0x1600);
853 RGE_PHY_SETBIT(sc, 0xa430, 0x0003);
854 }
855
856 static void
rge_phy_config_mac_r26_1(struct rge_softc * sc)857 rge_phy_config_mac_r26_1(struct rge_softc *sc)
858 {
859 uint16_t val;
860 int i;
861 static const uint16_t mac_cfg2_a438_value[] =
862 { 0x0044, 0x00a8, 0x00d6, 0x00ec, 0x00f6, 0x00fc, 0x00fe,
863 0x00fe, 0x00bc, 0x0058, 0x002a, 0x003f, 0x3f02, 0x023c,
864 0x3b0a, 0x1c00, 0x0000, 0x0000, 0x0000, 0x0000 };
865
866 static const uint16_t mac_cfg2_b87e_value[] =
867 { 0x03ed, 0x03ff, 0x0009, 0x03fe, 0x000b, 0x0021, 0x03f7,
868 0x03b8, 0x03e0, 0x0049, 0x0049, 0x03e0, 0x03b8, 0x03f7,
869 0x0021, 0x000b, 0x03fe, 0x0009, 0x03ff, 0x03ed, 0x000e,
870 0x03fe, 0x03ed, 0x0006, 0x001a, 0x03f1, 0x03d8, 0x0023,
871 0x0054, 0x0322, 0x00dd, 0x03ab, 0x03dc, 0x0027, 0x000e,
872 0x03e5, 0x03f9, 0x0012, 0x0001, 0x03f1 };
873
874 rge_phy_config_mcu(sc, RGE_MAC_R26_1_RCODE_VER);
875
876 RGE_PHY_SETBIT(sc, 0xa442, 0x0800);
877 rge_write_phy_ocp(sc, 0xa436, 0x80bf);
878 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00;
879 rge_write_phy_ocp(sc, 0xa438, val | 0xed00);
880 rge_write_phy_ocp(sc, 0xa436, 0x80cd);
881 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00;
882 rge_write_phy_ocp(sc, 0xa438, val | 0x1000);
883 rge_write_phy_ocp(sc, 0xa436, 0x80d1);
884 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00;
885 rge_write_phy_ocp(sc, 0xa438, val | 0xc800);
886 rge_write_phy_ocp(sc, 0xa436, 0x80d4);
887 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00;
888 rge_write_phy_ocp(sc, 0xa438, val | 0xc800);
889 rge_write_phy_ocp(sc, 0xa436, 0x80e1);
890 rge_write_phy_ocp(sc, 0xa438, 0x10cc);
891 rge_write_phy_ocp(sc, 0xa436, 0x80e5);
892 rge_write_phy_ocp(sc, 0xa438, 0x4f0c);
893 rge_write_phy_ocp(sc, 0xa436, 0x8387);
894 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00;
895 rge_write_phy_ocp(sc, 0xa438, val | 0x4700);
896 val = rge_read_phy_ocp(sc, 0xa80c) & ~0x00c0;
897 rge_write_phy_ocp(sc, 0xa80c, val | 0x0080);
898 RGE_PHY_CLRBIT(sc, 0xac90, 0x0010);
899 RGE_PHY_CLRBIT(sc, 0xad2c, 0x8000);
900 rge_write_phy_ocp(sc, 0xb87c, 0x8321);
901 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
902 rge_write_phy_ocp(sc, 0xb87e, val | 0x1100);
903 RGE_PHY_SETBIT(sc, 0xacf8, 0x000c);
904 rge_write_phy_ocp(sc, 0xa436, 0x8183);
905 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00;
906 rge_write_phy_ocp(sc, 0xa438, val | 0x5900);
907 RGE_PHY_SETBIT(sc, 0xad94, 0x0020);
908 RGE_PHY_CLRBIT(sc, 0xa654, 0x0800);
909 RGE_PHY_SETBIT(sc, 0xb648, 0x4000);
910 rge_write_phy_ocp(sc, 0xb87c, 0x839e);
911 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
912 rge_write_phy_ocp(sc, 0xb87e, val | 0x2f00);
913 rge_write_phy_ocp(sc, 0xb87c, 0x83f2);
914 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
915 rge_write_phy_ocp(sc, 0xb87e, val | 0x0800);
916 RGE_PHY_SETBIT(sc, 0xada0, 0x0002);
917 rge_write_phy_ocp(sc, 0xb87c, 0x80f3);
918 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
919 rge_write_phy_ocp(sc, 0xb87e, val | 0x9900);
920 rge_write_phy_ocp(sc, 0xb87c, 0x8126);
921 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
922 rge_write_phy_ocp(sc, 0xb87e, val | 0xc100);
923 rge_write_phy_ocp(sc, 0xb87c, 0x893a);
924 rge_write_phy_ocp(sc, 0xb87e, 0x8080);
925 rge_write_phy_ocp(sc, 0xb87c, 0x8647);
926 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
927 rge_write_phy_ocp(sc, 0xb87e, val | 0xe600);
928 rge_write_phy_ocp(sc, 0xb87c, 0x862c);
929 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
930 rge_write_phy_ocp(sc, 0xb87e, val | 0x1200);
931 rge_write_phy_ocp(sc, 0xb87c, 0x864a);
932 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
933 rge_write_phy_ocp(sc, 0xb87e, val | 0xe600);
934 rge_write_phy_ocp(sc, 0xb87c, 0x80a0);
935 rge_write_phy_ocp(sc, 0xb87e, 0xbcbc);
936 rge_write_phy_ocp(sc, 0xb87c, 0x805e);
937 rge_write_phy_ocp(sc, 0xb87e, 0xbcbc);
938 rge_write_phy_ocp(sc, 0xb87c, 0x8056);
939 rge_write_phy_ocp(sc, 0xb87e, 0x3077);
940 rge_write_phy_ocp(sc, 0xb87c, 0x8058);
941 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
942 rge_write_phy_ocp(sc, 0xb87e, val | 0x5a00);
943 rge_write_phy_ocp(sc, 0xb87c, 0x8098);
944 rge_write_phy_ocp(sc, 0xb87e, 0x3077);
945 rge_write_phy_ocp(sc, 0xb87c, 0x809a);
946 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
947 rge_write_phy_ocp(sc, 0xb87e, val | 0x5a00);
948 rge_write_phy_ocp(sc, 0xb87c, 0x8052);
949 rge_write_phy_ocp(sc, 0xb87e, 0x3733);
950 rge_write_phy_ocp(sc, 0xb87c, 0x8094);
951 rge_write_phy_ocp(sc, 0xb87e, 0x3733);
952 rge_write_phy_ocp(sc, 0xb87c, 0x807f);
953 rge_write_phy_ocp(sc, 0xb87e, 0x7c75);
954 rge_write_phy_ocp(sc, 0xb87c, 0x803d);
955 rge_write_phy_ocp(sc, 0xb87e, 0x7c75);
956 rge_write_phy_ocp(sc, 0xb87c, 0x8036);
957 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
958 rge_write_phy_ocp(sc, 0xb87e, val | 0x3000);
959 rge_write_phy_ocp(sc, 0xb87c, 0x8078);
960 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
961 rge_write_phy_ocp(sc, 0xb87e, val | 0x3000);
962 rge_write_phy_ocp(sc, 0xb87c, 0x8031);
963 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
964 rge_write_phy_ocp(sc, 0xb87e, val | 0x3300);
965 rge_write_phy_ocp(sc, 0xb87c, 0x8073);
966 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
967 rge_write_phy_ocp(sc, 0xb87e, val | 0x3300);
968 val = rge_read_phy_ocp(sc, 0xae06) & ~0xfc00;
969 rge_write_phy_ocp(sc, 0xae06, val | 0x7c00);
970 rge_write_phy_ocp(sc, 0xb87c, 0x89D1);
971 rge_write_phy_ocp(sc, 0xb87e, 0x0004);
972 rge_write_phy_ocp(sc, 0xa436, 0x8fbd);
973 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00;
974 rge_write_phy_ocp(sc, 0xa438, val | 0x0a00);
975 rge_write_phy_ocp(sc, 0xa436, 0x8fbe);
976 rge_write_phy_ocp(sc, 0xa438, 0x0d09);
977 rge_write_phy_ocp(sc, 0xb87c, 0x89cd);
978 rge_write_phy_ocp(sc, 0xb87e, 0x0f0f);
979 rge_write_phy_ocp(sc, 0xb87c, 0x89cf);
980 rge_write_phy_ocp(sc, 0xb87e, 0x0f0f);
981 rge_write_phy_ocp(sc, 0xb87c, 0x83a4);
982 rge_write_phy_ocp(sc, 0xb87e, 0x6600);
983 rge_write_phy_ocp(sc, 0xb87c, 0x83a6);
984 rge_write_phy_ocp(sc, 0xb87e, 0x6601);
985 rge_write_phy_ocp(sc, 0xb87c, 0x83c0);
986 rge_write_phy_ocp(sc, 0xb87e, 0x6600);
987 rge_write_phy_ocp(sc, 0xb87c, 0x83c2);
988 rge_write_phy_ocp(sc, 0xb87e, 0x6601);
989 rge_write_phy_ocp(sc, 0xb87c, 0x8414);
990 rge_write_phy_ocp(sc, 0xb87e, 0x6600);
991 rge_write_phy_ocp(sc, 0xb87c, 0x8416);
992 rge_write_phy_ocp(sc, 0xb87e, 0x6601);
993 rge_write_phy_ocp(sc, 0xb87c, 0x83f8);
994 rge_write_phy_ocp(sc, 0xb87e, 0x6600);
995 rge_write_phy_ocp(sc, 0xb87c, 0x83fa);
996 rge_write_phy_ocp(sc, 0xb87e, 0x6601);
997
998 rge_patch_phy_mcu(sc, 1);
999 val = rge_read_phy_ocp(sc, 0xbd96) & ~0x1f00;
1000 rge_write_phy_ocp(sc, 0xbd96, val | 0x1000);
1001 val = rge_read_phy_ocp(sc, 0xbf1c) & ~0x0007;
1002 rge_write_phy_ocp(sc, 0xbf1c, val | 0x0007);
1003 RGE_PHY_CLRBIT(sc, 0xbfbe, 0x8000);
1004 val = rge_read_phy_ocp(sc, 0xbf40) & ~0x0380;
1005 rge_write_phy_ocp(sc, 0xbf40, val | 0x0280);
1006 val = rge_read_phy_ocp(sc, 0xbf90) & ~0x0080;
1007 rge_write_phy_ocp(sc, 0xbf90, val | 0x0060);
1008 val = rge_read_phy_ocp(sc, 0xbf90) & ~0x0010;
1009 rge_write_phy_ocp(sc, 0xbf90, val | 0x000c);
1010 rge_patch_phy_mcu(sc, 0);
1011
1012 rge_write_phy_ocp(sc, 0xa436, 0x843b);
1013 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00;
1014 rge_write_phy_ocp(sc, 0xa438, val | 0x2000);
1015 rge_write_phy_ocp(sc, 0xa436, 0x843d);
1016 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00;
1017 rge_write_phy_ocp(sc, 0xa438, val | 0x2000);
1018 RGE_PHY_CLRBIT(sc, 0xb516, 0x007f);
1019 RGE_PHY_CLRBIT(sc, 0xbf80, 0x0030);
1020
1021 rge_write_phy_ocp(sc, 0xa436, 0x8188);
1022 for (i = 0; i < 11; i++)
1023 rge_write_phy_ocp(sc, 0xa438, mac_cfg2_a438_value[i]);
1024
1025 rge_write_phy_ocp(sc, 0xb87c, 0x8015);
1026 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
1027 rge_write_phy_ocp(sc, 0xb87e, val | 0x0800);
1028 rge_write_phy_ocp(sc, 0xb87c, 0x8ffd);
1029 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
1030 rge_write_phy_ocp(sc, 0xb87e, val | 0);
1031 rge_write_phy_ocp(sc, 0xb87c, 0x8fff);
1032 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
1033 rge_write_phy_ocp(sc, 0xb87e, val | 0x7f00);
1034 rge_write_phy_ocp(sc, 0xb87c, 0x8ffb);
1035 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
1036 rge_write_phy_ocp(sc, 0xb87e, val | 0x0100);
1037 rge_write_phy_ocp(sc, 0xb87c, 0x8fe9);
1038 rge_write_phy_ocp(sc, 0xb87e, 0x0002);
1039 rge_write_phy_ocp(sc, 0xb87c, 0x8fef);
1040 rge_write_phy_ocp(sc, 0xb87e, 0x00a5);
1041 rge_write_phy_ocp(sc, 0xb87c, 0x8ff1);
1042 rge_write_phy_ocp(sc, 0xb87e, 0x0106);
1043 rge_write_phy_ocp(sc, 0xb87c, 0x8fe1);
1044 rge_write_phy_ocp(sc, 0xb87e, 0x0102);
1045 rge_write_phy_ocp(sc, 0xb87c, 0x8fe3);
1046 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
1047 rge_write_phy_ocp(sc, 0xb87e, val | 0x0400);
1048 RGE_PHY_SETBIT(sc, 0xa654, 0x0800);
1049 RGE_PHY_CLRBIT(sc, 0xa654, 0x0003);
1050 rge_write_phy_ocp(sc, 0xac3a, 0x5851);
1051 val = rge_read_phy_ocp(sc, 0xac3c) & ~0xd000;
1052 rge_write_phy_ocp(sc, 0xac3c, val | 0x2000);
1053 val = rge_read_phy_ocp(sc, 0xac42) & ~0x0200;
1054 rge_write_phy_ocp(sc, 0xac42, val | 0x01c0);
1055 RGE_PHY_CLRBIT(sc, 0xac3e, 0xe000);
1056 RGE_PHY_CLRBIT(sc, 0xac42, 0x0038);
1057 val = rge_read_phy_ocp(sc, 0xac42) & ~0x0002;
1058 rge_write_phy_ocp(sc, 0xac42, val | 0x0005);
1059 rge_write_phy_ocp(sc, 0xac1a, 0x00db);
1060 rge_write_phy_ocp(sc, 0xade4, 0x01b5);
1061 RGE_PHY_CLRBIT(sc, 0xad9c, 0x0c00);
1062 rge_write_phy_ocp(sc, 0xb87c, 0x814b);
1063 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
1064 rge_write_phy_ocp(sc, 0xb87e, val | 0x1100);
1065 rge_write_phy_ocp(sc, 0xb87c, 0x814d);
1066 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
1067 rge_write_phy_ocp(sc, 0xb87e, val | 0x1100);
1068 rge_write_phy_ocp(sc, 0xb87c, 0x814f);
1069 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
1070 rge_write_phy_ocp(sc, 0xb87e, val | 0x0b00);
1071 rge_write_phy_ocp(sc, 0xb87c, 0x8142);
1072 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
1073 rge_write_phy_ocp(sc, 0xb87e, val | 0x0100);
1074 rge_write_phy_ocp(sc, 0xb87c, 0x8144);
1075 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
1076 rge_write_phy_ocp(sc, 0xb87e, val | 0x0100);
1077 rge_write_phy_ocp(sc, 0xb87c, 0x8150);
1078 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
1079 rge_write_phy_ocp(sc, 0xb87e, val | 0x0100);
1080 rge_write_phy_ocp(sc, 0xb87c, 0x8118);
1081 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
1082 rge_write_phy_ocp(sc, 0xb87e, val | 0x0700);
1083 rge_write_phy_ocp(sc, 0xb87c, 0x811a);
1084 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
1085 rge_write_phy_ocp(sc, 0xb87e, val | 0x0700);
1086 rge_write_phy_ocp(sc, 0xb87c, 0x811c);
1087 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
1088 rge_write_phy_ocp(sc, 0xb87e, val | 0x0500);
1089 rge_write_phy_ocp(sc, 0xb87c, 0x810f);
1090 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
1091 rge_write_phy_ocp(sc, 0xb87e, val | 0x0100);
1092 rge_write_phy_ocp(sc, 0xb87c, 0x8111);
1093 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
1094 rge_write_phy_ocp(sc, 0xb87e, val | 0x0100);
1095 rge_write_phy_ocp(sc, 0xb87c, 0x811d);
1096 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
1097 rge_write_phy_ocp(sc, 0xb87e, val | 0x0100);
1098 RGE_PHY_SETBIT(sc, 0xac36, 0x1000);
1099 RGE_PHY_CLRBIT(sc, 0xad1c, 0x0100);
1100 val = rge_read_phy_ocp(sc, 0xade8) & ~0xffc0;
1101 rge_write_phy_ocp(sc, 0xade8, val | 0x1400);
1102 rge_write_phy_ocp(sc, 0xb87c, 0x864b);
1103 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
1104 rge_write_phy_ocp(sc, 0xb87e, val | 0x9d00);
1105
1106 rge_write_phy_ocp(sc, 0xa436, 0x8f97);
1107 for (; i < nitems(mac_cfg2_a438_value); i++)
1108 rge_write_phy_ocp(sc, 0xa438, mac_cfg2_a438_value[i]);
1109
1110 RGE_PHY_SETBIT(sc, 0xad9c, 0x0020);
1111 rge_write_phy_ocp(sc, 0xb87c, 0x8122);
1112 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
1113 rge_write_phy_ocp(sc, 0xb87e, val | 0x0c00);
1114
1115 rge_write_phy_ocp(sc, 0xb87c, 0x82c8);
1116 for (i = 0; i < 20; i++)
1117 rge_write_phy_ocp(sc, 0xb87e, mac_cfg2_b87e_value[i]);
1118
1119 rge_write_phy_ocp(sc, 0xb87c, 0x80ef);
1120 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
1121 rge_write_phy_ocp(sc, 0xb87e, val | 0x0c00);
1122
1123 rge_write_phy_ocp(sc, 0xb87c, 0x82a0);
1124 for (; i < nitems(mac_cfg2_b87e_value); i++)
1125 rge_write_phy_ocp(sc, 0xb87e, mac_cfg2_b87e_value[i]);
1126
1127 rge_write_phy_ocp(sc, 0xa436, 0x8018);
1128 RGE_PHY_SETBIT(sc, 0xa438, 0x2000);
1129 rge_write_phy_ocp(sc, 0xb87c, 0x8fe4);
1130 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
1131 rge_write_phy_ocp(sc, 0xb87e, val | 0);
1132 val = rge_read_phy_ocp(sc, 0xb54c) & ~0xffc0;
1133 rge_write_phy_ocp(sc, 0xb54c, val | 0x3700);
1134 }
1135
1136 static void
rge_phy_config_mac_r26_2(struct rge_softc * sc)1137 rge_phy_config_mac_r26_2(struct rge_softc *sc)
1138 {
1139 uint16_t val;
1140 int i;
1141 static const uint16_t mac_cfg3_b87e_value[] =
1142 { 0x03ed, 0x03ff, 0x0009, 0x03fe, 0x000b, 0x0021, 0x03f7,
1143 0x03b8, 0x03e0, 0x0049, 0x0049, 0x03e0, 0x03b8, 0x03f7,
1144 0x0021, 0x000b, 0x03fe, 0x0009, 0x03ff, 0x03ed, 0x82a0,
1145 0x000e, 0x03fe, 0x03ed, 0x0006, 0x001a, 0x03f1, 0x03d8,
1146 0x0023, 0x0054, 0x0322, 0x00dd, 0x03ab, 0x03dc, 0x0027,
1147 0x000e, 0x03e5, 0x03f9, 0x0012, 0x0001, 0x03f1 };
1148
1149 rge_phy_config_mcu(sc, RGE_MAC_R26_2_RCODE_VER);
1150
1151 RGE_PHY_SETBIT(sc, 0xa442, 0x0800);
1152 rge_write_phy_ocp(sc, 0xa436, 0x8183);
1153 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00;
1154 rge_write_phy_ocp(sc, 0xa438, val | 0x5900);
1155 RGE_PHY_SETBIT(sc, 0xa654, 0x0800);
1156 RGE_PHY_SETBIT(sc, 0xb648, 0x4000);
1157 RGE_PHY_SETBIT(sc, 0xad2c, 0x8000);
1158 RGE_PHY_SETBIT(sc, 0xad94, 0x0020);
1159 RGE_PHY_SETBIT(sc, 0xada0, 0x0002);
1160 val = rge_read_phy_ocp(sc, 0xae06) & ~0xfc00;
1161 rge_write_phy_ocp(sc, 0xae06, val | 0x7c00);
1162 rge_write_phy_ocp(sc, 0xb87c, 0x8647);
1163 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
1164 rge_write_phy_ocp(sc, 0xb87e, val | 0xe600);
1165 rge_write_phy_ocp(sc, 0xb87c, 0x8036);
1166 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
1167 rge_write_phy_ocp(sc, 0xb87e, val | 0x3000);
1168 rge_write_phy_ocp(sc, 0xb87c, 0x8078);
1169 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
1170 rge_write_phy_ocp(sc, 0xb87e, val | 0x3000);
1171 rge_write_phy_ocp(sc, 0xb87c, 0x89e9);
1172 RGE_PHY_SETBIT(sc, 0xb87e, 0xff00);
1173 rge_write_phy_ocp(sc, 0xb87c, 0x8ffd);
1174 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
1175 rge_write_phy_ocp(sc, 0xb87e, val | 0x0100);
1176 rge_write_phy_ocp(sc, 0xb87c, 0x8ffe);
1177 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
1178 rge_write_phy_ocp(sc, 0xb87e, val | 0x0200);
1179 rge_write_phy_ocp(sc, 0xb87c, 0x8fff);
1180 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
1181 rge_write_phy_ocp(sc, 0xb87e, val | 0x0400);
1182 rge_write_phy_ocp(sc, 0xa436, 0x8018);
1183 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00;
1184 rge_write_phy_ocp(sc, 0xa438, val | 0x7700);
1185 rge_write_phy_ocp(sc, 0xa436, 0x8f9c);
1186 rge_write_phy_ocp(sc, 0xa438, 0x0005);
1187 rge_write_phy_ocp(sc, 0xa438, 0x0000);
1188 rge_write_phy_ocp(sc, 0xa438, 0x00ed);
1189 rge_write_phy_ocp(sc, 0xa438, 0x0502);
1190 rge_write_phy_ocp(sc, 0xa438, 0x0b00);
1191 rge_write_phy_ocp(sc, 0xa438, 0xd401);
1192 rge_write_phy_ocp(sc, 0xa436, 0x8fa8);
1193 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00;
1194 rge_write_phy_ocp(sc, 0xa438, val | 0x2900);
1195 rge_write_phy_ocp(sc, 0xb87c, 0x814b);
1196 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
1197 rge_write_phy_ocp(sc, 0xb87e, val | 0x1100);
1198 rge_write_phy_ocp(sc, 0xb87c, 0x814d);
1199 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
1200 rge_write_phy_ocp(sc, 0xb87e, val | 0x1100);
1201 rge_write_phy_ocp(sc, 0xb87c, 0x814f);
1202 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
1203 rge_write_phy_ocp(sc, 0xb87e, val | 0x0b00);
1204 rge_write_phy_ocp(sc, 0xb87c, 0x8142);
1205 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
1206 rge_write_phy_ocp(sc, 0xb87e, val | 0x0100);
1207 rge_write_phy_ocp(sc, 0xb87c, 0x8144);
1208 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
1209 rge_write_phy_ocp(sc, 0xb87e, val | 0x0100);
1210 rge_write_phy_ocp(sc, 0xb87c, 0x8150);
1211 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
1212 rge_write_phy_ocp(sc, 0xb87e, val | 0x0100);
1213 rge_write_phy_ocp(sc, 0xb87c, 0x8118);
1214 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
1215 rge_write_phy_ocp(sc, 0xb87e, val | 0x0700);
1216 rge_write_phy_ocp(sc, 0xb87c, 0x811a);
1217 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
1218 rge_write_phy_ocp(sc, 0xb87e, val | 0x0700);
1219 rge_write_phy_ocp(sc, 0xb87c, 0x811c);
1220 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
1221 rge_write_phy_ocp(sc, 0xb87e, val | 0x0500);
1222 rge_write_phy_ocp(sc, 0xb87c, 0x810f);
1223 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
1224 rge_write_phy_ocp(sc, 0xb87e, val | 0x0100);
1225 rge_write_phy_ocp(sc, 0xb87c, 0x8111);
1226 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
1227 rge_write_phy_ocp(sc, 0xb87e, val | 0x0100);
1228 rge_write_phy_ocp(sc, 0xb87c, 0x811d);
1229 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
1230 rge_write_phy_ocp(sc, 0xb87e, val | 0x0100);
1231 RGE_PHY_SETBIT(sc, 0xad1c, 0x0100);
1232 val = rge_read_phy_ocp(sc, 0xade8) & ~0xffc0;
1233 rge_write_phy_ocp(sc, 0xade8, val | 0x1400);
1234 rge_write_phy_ocp(sc, 0xb87c, 0x864b);
1235 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
1236 rge_write_phy_ocp(sc, 0xb87e, val | 0x9d00);
1237 rge_write_phy_ocp(sc, 0xb87c, 0x862c);
1238 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
1239 rge_write_phy_ocp(sc, 0xb87e, val | 0x1200);
1240 rge_write_phy_ocp(sc, 0xa436, 0x8566);
1241 rge_write_phy_ocp(sc, 0xa438, 0x003f);
1242 rge_write_phy_ocp(sc, 0xa438, 0x3f02);
1243 rge_write_phy_ocp(sc, 0xa438, 0x023c);
1244 rge_write_phy_ocp(sc, 0xa438, 0x3b0a);
1245 rge_write_phy_ocp(sc, 0xa438, 0x1c00);
1246 rge_write_phy_ocp(sc, 0xa438, 0x0000);
1247 rge_write_phy_ocp(sc, 0xa438, 0x0000);
1248 rge_write_phy_ocp(sc, 0xa438, 0x0000);
1249 rge_write_phy_ocp(sc, 0xa438, 0x0000);
1250 RGE_PHY_SETBIT(sc, 0xad9c, 0x0020);
1251 rge_write_phy_ocp(sc, 0xb87c, 0x8122);
1252 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
1253 rge_write_phy_ocp(sc, 0xb87e, val | 0x0c00);
1254 rge_write_phy_ocp(sc, 0xb87c, 0x82c8);
1255 for (i = 0; i < 20; i++)
1256 rge_write_phy_ocp(sc, 0xb87e, mac_cfg3_b87e_value[i]);
1257 rge_write_phy_ocp(sc, 0xb87c, 0x80ef);
1258 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
1259 rge_write_phy_ocp(sc, 0xb87e, val | 0x0c00);
1260 for (; i < nitems(mac_cfg3_b87e_value); i++)
1261 rge_write_phy_ocp(sc, 0xb87e, mac_cfg3_b87e_value[i]);
1262 RGE_PHY_SETBIT(sc, 0xa430, 0x0003);
1263 val = rge_read_phy_ocp(sc, 0xb54c) & ~0xffc0;
1264 rge_write_phy_ocp(sc, 0xb54c, val | 0x3700);
1265 RGE_PHY_SETBIT(sc, 0xb648, 0x0040);
1266 rge_write_phy_ocp(sc, 0xb87c, 0x8082);
1267 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
1268 rge_write_phy_ocp(sc, 0xb87e, val | 0x5d00);
1269 rge_write_phy_ocp(sc, 0xb87c, 0x807c);
1270 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
1271 rge_write_phy_ocp(sc, 0xb87e, val | 0x5000);
1272 rge_write_phy_ocp(sc, 0xb87c, 0x809d);
1273 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
1274 rge_write_phy_ocp(sc, 0xb87e, val | 0x5000);
1275 }
1276
1277 static void
rge_phy_config_mac_r25(struct rge_softc * sc)1278 rge_phy_config_mac_r25(struct rge_softc *sc)
1279 {
1280 uint16_t val;
1281 int i;
1282 static const uint16_t mac_cfg3_a438_value[] =
1283 { 0x0043, 0x00a7, 0x00d6, 0x00ec, 0x00f6, 0x00fb, 0x00fd, 0x00ff,
1284 0x00bb, 0x0058, 0x0029, 0x0013, 0x0009, 0x0004, 0x0002 };
1285
1286 static const uint16_t mac_cfg3_b88e_value[] =
1287 { 0xc091, 0x6e12, 0xc092, 0x1214, 0xc094, 0x1516, 0xc096, 0x171b,
1288 0xc098, 0x1b1c, 0xc09a, 0x1f1f, 0xc09c, 0x2021, 0xc09e, 0x2224,
1289 0xc0a0, 0x2424, 0xc0a2, 0x2424, 0xc0a4, 0x2424, 0xc018, 0x0af2,
1290 0xc01a, 0x0d4a, 0xc01c, 0x0f26, 0xc01e, 0x118d, 0xc020, 0x14f3,
1291 0xc022, 0x175a, 0xc024, 0x19c0, 0xc026, 0x1c26, 0xc089, 0x6050,
1292 0xc08a, 0x5f6e, 0xc08c, 0x6e6e, 0xc08e, 0x6e6e, 0xc090, 0x6e12 };
1293
1294 rge_phy_config_mcu(sc, RGE_MAC_R25_RCODE_VER);
1295
1296 RGE_PHY_SETBIT(sc, 0xad4e, 0x0010);
1297 val = rge_read_phy_ocp(sc, 0xad16) & ~0x03ff;
1298 rge_write_phy_ocp(sc, 0xad16, val | 0x03ff);
1299 val = rge_read_phy_ocp(sc, 0xad32) & ~0x003f;
1300 rge_write_phy_ocp(sc, 0xad32, val | 0x0006);
1301 RGE_PHY_CLRBIT(sc, 0xac08, 0x1000);
1302 RGE_PHY_CLRBIT(sc, 0xac08, 0x0100);
1303 val = rge_read_phy_ocp(sc, 0xacc0) & ~0x0003;
1304 rge_write_phy_ocp(sc, 0xacc0, val | 0x0002);
1305 val = rge_read_phy_ocp(sc, 0xad40) & ~0x00e0;
1306 rge_write_phy_ocp(sc, 0xad40, val | 0x0040);
1307 val = rge_read_phy_ocp(sc, 0xad40) & ~0x0007;
1308 rge_write_phy_ocp(sc, 0xad40, val | 0x0004);
1309 RGE_PHY_CLRBIT(sc, 0xac14, 0x0080);
1310 RGE_PHY_CLRBIT(sc, 0xac80, 0x0300);
1311 val = rge_read_phy_ocp(sc, 0xac5e) & ~0x0007;
1312 rge_write_phy_ocp(sc, 0xac5e, val | 0x0002);
1313 rge_write_phy_ocp(sc, 0xad4c, 0x00a8);
1314 rge_write_phy_ocp(sc, 0xac5c, 0x01ff);
1315 val = rge_read_phy_ocp(sc, 0xac8a) & ~0x00f0;
1316 rge_write_phy_ocp(sc, 0xac8a, val | 0x0030);
1317 rge_write_phy_ocp(sc, 0xb87c, 0x8157);
1318 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
1319 rge_write_phy_ocp(sc, 0xb87e, val | 0x0500);
1320 rge_write_phy_ocp(sc, 0xb87c, 0x8159);
1321 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
1322 rge_write_phy_ocp(sc, 0xb87e, val | 0x0700);
1323 rge_write_phy_ocp(sc, 0xb87c, 0x80a2);
1324 rge_write_phy_ocp(sc, 0xb87e, 0x0153);
1325 rge_write_phy_ocp(sc, 0xb87c, 0x809c);
1326 rge_write_phy_ocp(sc, 0xb87e, 0x0153);
1327
1328 rge_write_phy_ocp(sc, 0xa436, 0x81b3);
1329 for (i = 0; i < nitems(mac_cfg3_a438_value); i++)
1330 rge_write_phy_ocp(sc, 0xa438, mac_cfg3_a438_value[i]);
1331 for (i = 0; i < 26; i++)
1332 rge_write_phy_ocp(sc, 0xa438, 0);
1333 rge_write_phy_ocp(sc, 0xa436, 0x8257);
1334 rge_write_phy_ocp(sc, 0xa438, 0x020f);
1335 rge_write_phy_ocp(sc, 0xa436, 0x80ea);
1336 rge_write_phy_ocp(sc, 0xa438, 0x7843);
1337
1338 rge_patch_phy_mcu(sc, 1);
1339 RGE_PHY_CLRBIT(sc, 0xb896, 0x0001);
1340 RGE_PHY_CLRBIT(sc, 0xb892, 0xff00);
1341 for (i = 0; i < nitems(mac_cfg3_b88e_value); i += 2) {
1342 rge_write_phy_ocp(sc, 0xb88e, mac_cfg3_b88e_value[i]);
1343 rge_write_phy_ocp(sc, 0xb890, mac_cfg3_b88e_value[i + 1]);
1344 }
1345 RGE_PHY_SETBIT(sc, 0xb896, 0x0001);
1346 rge_patch_phy_mcu(sc, 0);
1347
1348 RGE_PHY_SETBIT(sc, 0xd068, 0x2000);
1349 rge_write_phy_ocp(sc, 0xa436, 0x81a2);
1350 RGE_PHY_SETBIT(sc, 0xa438, 0x0100);
1351 val = rge_read_phy_ocp(sc, 0xb54c) & ~0xff00;
1352 rge_write_phy_ocp(sc, 0xb54c, val | 0xdb00);
1353 RGE_PHY_CLRBIT(sc, 0xa454, 0x0001);
1354 RGE_PHY_SETBIT(sc, 0xa5d4, 0x0020);
1355 RGE_PHY_CLRBIT(sc, 0xad4e, 0x0010);
1356 RGE_PHY_CLRBIT(sc, 0xa86a, 0x0001);
1357 RGE_PHY_SETBIT(sc, 0xa442, 0x0800);
1358 RGE_PHY_SETBIT(sc, 0xa424, 0x0008);
1359 }
1360
1361 static void
rge_phy_config_mac_r25b(struct rge_softc * sc)1362 rge_phy_config_mac_r25b(struct rge_softc *sc)
1363 {
1364 uint16_t val;
1365 int i;
1366
1367 rge_phy_config_mcu(sc, RGE_MAC_R25B_RCODE_VER);
1368
1369 RGE_PHY_SETBIT(sc, 0xa442, 0x0800);
1370 val = rge_read_phy_ocp(sc, 0xac46) & ~0x00f0;
1371 rge_write_phy_ocp(sc, 0xac46, val | 0x0090);
1372 val = rge_read_phy_ocp(sc, 0xad30) & ~0x0003;
1373 rge_write_phy_ocp(sc, 0xad30, val | 0x0001);
1374 rge_write_phy_ocp(sc, 0xb87c, 0x80f5);
1375 rge_write_phy_ocp(sc, 0xb87e, 0x760e);
1376 rge_write_phy_ocp(sc, 0xb87c, 0x8107);
1377 rge_write_phy_ocp(sc, 0xb87e, 0x360e);
1378 rge_write_phy_ocp(sc, 0xb87c, 0x8551);
1379 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
1380 rge_write_phy_ocp(sc, 0xb87e, val | 0x0800);
1381 val = rge_read_phy_ocp(sc, 0xbf00) & ~0xe000;
1382 rge_write_phy_ocp(sc, 0xbf00, val | 0xa000);
1383 val = rge_read_phy_ocp(sc, 0xbf46) & ~0x0f00;
1384 rge_write_phy_ocp(sc, 0xbf46, val | 0x0300);
1385 for (i = 0; i < 10; i++) {
1386 rge_write_phy_ocp(sc, 0xa436, 0x8044 + i * 6);
1387 rge_write_phy_ocp(sc, 0xa438, 0x2417);
1388 }
1389 RGE_PHY_SETBIT(sc, 0xa4ca, 0x0040);
1390 val = rge_read_phy_ocp(sc, 0xbf84) & ~0xe000;
1391 rge_write_phy_ocp(sc, 0xbf84, val | 0xa000);
1392 rge_write_phy_ocp(sc, 0xa436, 0x8170);
1393 val = rge_read_phy_ocp(sc, 0xa438) & ~0x2700;
1394 rge_write_phy_ocp(sc, 0xa438, val | 0xd800);
1395 RGE_PHY_SETBIT(sc, 0xa424, 0x0008);
1396 }
1397
1398 static void
rge_phy_config_mac_r25d_1(struct rge_softc * sc)1399 rge_phy_config_mac_r25d_1(struct rge_softc *sc)
1400 {
1401 uint16_t val;
1402 int i;
1403
1404 rge_phy_config_mcu(sc, RGE_MAC_R25D_1_RCODE_VER);
1405
1406 RGE_PHY_SETBIT(sc, 0xa442, 0x0800);
1407
1408 rge_patch_phy_mcu(sc, 1);
1409 RGE_PHY_SETBIT(sc, 0xbf96, 0x8000);
1410 val = rge_read_phy_ocp(sc, 0xbf94) & ~0x0007;
1411 rge_write_phy_ocp(sc, 0xbf94, val | 0x0005);
1412 val = rge_read_phy_ocp(sc, 0xbf8e) & ~0x3c00;
1413 rge_write_phy_ocp(sc, 0xbf8e, val | 0x2800);
1414 val = rge_read_phy_ocp(sc, 0xbcd8) & ~0xc000;
1415 rge_write_phy_ocp(sc, 0xbcd8, val | 0x4000);
1416 RGE_PHY_SETBIT(sc, 0xbcd8, 0xc000);
1417 val = rge_read_phy_ocp(sc, 0xbcd8) & ~0xc000;
1418 rge_write_phy_ocp(sc, 0xbcd8, val | 0x4000);
1419 val = rge_read_phy_ocp(sc, 0xbc80) & ~0x001f;
1420 rge_write_phy_ocp(sc, 0xbc80, val | 0x0004);
1421 RGE_PHY_SETBIT(sc, 0xbc82, 0xe000);
1422 RGE_PHY_SETBIT(sc, 0xbc82, 0x1c00);
1423 val = rge_read_phy_ocp(sc, 0xbc80) & ~0x001f;
1424 rge_write_phy_ocp(sc, 0xbc80, val | 0x0005);
1425 val = rge_read_phy_ocp(sc, 0xbc82) & ~0x00e0;
1426 rge_write_phy_ocp(sc, 0xbc82, val | 0x0040);
1427 RGE_PHY_SETBIT(sc, 0xbc82, 0x001c);
1428 RGE_PHY_CLRBIT(sc, 0xbcd8, 0xc000);
1429 val = rge_read_phy_ocp(sc, 0xbcd8) & ~0xc000;
1430 rge_write_phy_ocp(sc, 0xbcd8, val | 0x8000);
1431 RGE_PHY_CLRBIT(sc, 0xbcd8, 0xc000);
1432 RGE_PHY_CLRBIT(sc, 0xbd70, 0x0100);
1433 RGE_PHY_SETBIT(sc, 0xa466, 0x0002);
1434 rge_write_phy_ocp(sc, 0xa436, 0x836a);
1435 RGE_PHY_CLRBIT(sc, 0xa438, 0xff00);
1436 rge_patch_phy_mcu(sc, 0);
1437
1438 rge_write_phy_ocp(sc, 0xb87c, 0x832c);
1439 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
1440 rge_write_phy_ocp(sc, 0xb87e, val | 0x0500);
1441 val = rge_read_phy_ocp(sc, 0xb106) & ~0x0700;
1442 rge_write_phy_ocp(sc, 0xb106, val | 0x0100);
1443 val = rge_read_phy_ocp(sc, 0xb206) & ~0x0700;
1444 rge_write_phy_ocp(sc, 0xb206, val | 0x0200);
1445 val = rge_read_phy_ocp(sc, 0xb306) & ~0x0700;
1446 rge_write_phy_ocp(sc, 0xb306, val | 0x0300);
1447 rge_write_phy_ocp(sc, 0xb87c, 0x80cb);
1448 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
1449 rge_write_phy_ocp(sc, 0xb87e, val | 0x0300);
1450 rge_write_phy_ocp(sc, 0xbcf4, 0x0000);
1451 rge_write_phy_ocp(sc, 0xbcf6, 0x0000);
1452 rge_write_phy_ocp(sc, 0xbc12, 0x0000);
1453 rge_write_phy_ocp(sc, 0xb87c, 0x844d);
1454 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
1455 rge_write_phy_ocp(sc, 0xb87e, val | 0x0200);
1456
1457 rge_write_phy_ocp(sc, 0xb87c, 0x8feb);
1458 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
1459 rge_write_phy_ocp(sc, 0xb87e, val | 0x0100);
1460 rge_write_phy_ocp(sc, 0xb87c, 0x8fe9);
1461 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
1462 rge_write_phy_ocp(sc, 0xb87e, val | 0x0600);
1463
1464 val = rge_read_phy_ocp(sc, 0xac7e) & ~0x01fc;
1465 rge_write_phy_ocp(sc, 0xac7e, val | 0x00B4);
1466 rge_write_phy_ocp(sc, 0xb87c, 0x8105);
1467 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
1468 rge_write_phy_ocp(sc, 0xb87e, val | 0x7a00);
1469 rge_write_phy_ocp(sc, 0xb87c, 0x8117);
1470 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
1471 rge_write_phy_ocp(sc, 0xb87e, val | 0x3a00);
1472 rge_write_phy_ocp(sc, 0xb87c, 0x8103);
1473 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
1474 rge_write_phy_ocp(sc, 0xb87e, val | 0x7400);
1475 rge_write_phy_ocp(sc, 0xb87c, 0x8115);
1476 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
1477 rge_write_phy_ocp(sc, 0xb87e, val | 0x3400);
1478 RGE_PHY_CLRBIT(sc, 0xad40, 0x0030);
1479 val = rge_read_phy_ocp(sc, 0xad66) & ~0x000f;
1480 rge_write_phy_ocp(sc, 0xad66, val | 0x0007);
1481 val = rge_read_phy_ocp(sc, 0xad68) & ~0xf000;
1482 rge_write_phy_ocp(sc, 0xad68, val | 0x8000);
1483 val = rge_read_phy_ocp(sc, 0xad68) & ~0x0f00;
1484 rge_write_phy_ocp(sc, 0xad68, val | 0x0500);
1485 val = rge_read_phy_ocp(sc, 0xad68) & ~0x000f;
1486 rge_write_phy_ocp(sc, 0xad68, val | 0x0002);
1487 val = rge_read_phy_ocp(sc, 0xad6a) & ~0xf000;
1488 rge_write_phy_ocp(sc, 0xad6a, val | 0x7000);
1489 rge_write_phy_ocp(sc, 0xac50, 0x01e8);
1490 rge_write_phy_ocp(sc, 0xa436, 0x81fa);
1491 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00;
1492 rge_write_phy_ocp(sc, 0xa438, val | 0x5400);
1493 val = rge_read_phy_ocp(sc, 0xa864) & ~0x00f0;
1494 rge_write_phy_ocp(sc, 0xa864, val | 0x00c0);
1495 val = rge_read_phy_ocp(sc, 0xa42c) & ~0x00ff;
1496 rge_write_phy_ocp(sc, 0xa42c, val | 0x0002);
1497 rge_write_phy_ocp(sc, 0xa436, 0x80e1);
1498 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00;
1499 rge_write_phy_ocp(sc, 0xa438, val | 0x0f00);
1500 rge_write_phy_ocp(sc, 0xa436, 0x80de);
1501 val = rge_read_phy_ocp(sc, 0xa438) & ~0xf000;
1502 rge_write_phy_ocp(sc, 0xa438, val | 0x0700);
1503 RGE_PHY_SETBIT(sc, 0xa846, 0x0080);
1504 rge_write_phy_ocp(sc, 0xa436, 0x80ba);
1505 rge_write_phy_ocp(sc, 0xa438, 0x8a04);
1506 rge_write_phy_ocp(sc, 0xa436, 0x80bd);
1507 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00;
1508 rge_write_phy_ocp(sc, 0xa438, val | 0xca00);
1509 rge_write_phy_ocp(sc, 0xa436, 0x80b7);
1510 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00;
1511 rge_write_phy_ocp(sc, 0xa438, val | 0xb300);
1512 rge_write_phy_ocp(sc, 0xa436, 0x80ce);
1513 rge_write_phy_ocp(sc, 0xa438, 0x8a04);
1514 rge_write_phy_ocp(sc, 0xa436, 0x80d1);
1515 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00;
1516 rge_write_phy_ocp(sc, 0xa438, val | 0xca00);
1517 rge_write_phy_ocp(sc, 0xa436, 0x80cb);
1518 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00;
1519 rge_write_phy_ocp(sc, 0xa438, val | 0xbb00);
1520 rge_write_phy_ocp(sc, 0xa436, 0x80a6);
1521 rge_write_phy_ocp(sc, 0xa438, 0x4909);
1522 rge_write_phy_ocp(sc, 0xa436, 0x80a8);
1523 rge_write_phy_ocp(sc, 0xa438, 0x05b8);
1524 rge_write_phy_ocp(sc, 0xa436, 0x8200);
1525 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00;
1526 rge_write_phy_ocp(sc, 0xa438, val | 0x5800);
1527 rge_write_phy_ocp(sc, 0xa436, 0x8ff1);
1528 rge_write_phy_ocp(sc, 0xa438, 0x7078);
1529 rge_write_phy_ocp(sc, 0xa436, 0x8ff3);
1530 rge_write_phy_ocp(sc, 0xa438, 0x5d78);
1531 rge_write_phy_ocp(sc, 0xa436, 0x8ff5);
1532 rge_write_phy_ocp(sc, 0xa438, 0x7862);
1533 rge_write_phy_ocp(sc, 0xa436, 0x8ff7);
1534 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00;
1535 rge_write_phy_ocp(sc, 0xa438, val | 0x1400);
1536
1537 rge_write_phy_ocp(sc, 0xa436, 0x814c);
1538 rge_write_phy_ocp(sc, 0xa438, 0x8455);
1539 rge_write_phy_ocp(sc, 0xa436, 0x814e);
1540 rge_write_phy_ocp(sc, 0xa438, 0x84a6);
1541 rge_write_phy_ocp(sc, 0xa436, 0x8163);
1542 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00;
1543 rge_write_phy_ocp(sc, 0xa438, val | 0x0600);
1544 rge_write_phy_ocp(sc, 0xa436, 0x816a);
1545 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00;
1546 rge_write_phy_ocp(sc, 0xa438, val | 0x0500);
1547 rge_write_phy_ocp(sc, 0xa436, 0x8171);
1548 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00;
1549 rge_write_phy_ocp(sc, 0xa438, val | 0x1f00);
1550
1551 val = rge_read_phy_ocp(sc, 0xbc3a) & ~0x000f;
1552 rge_write_phy_ocp(sc, 0xbc3a, val | 0x0006);
1553 for (i = 0; i < 10; i++) {
1554 rge_write_phy_ocp(sc, 0xa436, 0x8064 + i * 3);
1555 RGE_PHY_CLRBIT(sc, 0xa438, 0x0700);
1556 }
1557 val = rge_read_phy_ocp(sc, 0xbfa0) & ~0xff70;
1558 rge_write_phy_ocp(sc, 0xbfa0, val | 0x5500);
1559 rge_write_phy_ocp(sc, 0xbfa2, 0x9d00);
1560 rge_write_phy_ocp(sc, 0xa436, 0x8165);
1561 val = rge_read_phy_ocp(sc, 0xa438) & ~0x0700;
1562 rge_write_phy_ocp(sc, 0xa438, val | 0x0200);
1563
1564 rge_write_phy_ocp(sc, 0xa436, 0x8019);
1565 RGE_PHY_SETBIT(sc, 0xa438, 0x0100);
1566 rge_write_phy_ocp(sc, 0xa436, 0x8fe3);
1567 rge_write_phy_ocp(sc, 0xa438, 0x0005);
1568 rge_write_phy_ocp(sc, 0xa438, 0x0000);
1569 rge_write_phy_ocp(sc, 0xa438, 0x00ed);
1570 rge_write_phy_ocp(sc, 0xa438, 0x0502);
1571 rge_write_phy_ocp(sc, 0xa438, 0x0b00);
1572 rge_write_phy_ocp(sc, 0xa438, 0xd401);
1573 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00;
1574 rge_write_phy_ocp(sc, 0xa438, val | 0x2900);
1575
1576 rge_write_phy_ocp(sc, 0xa436, 0x8018);
1577 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00;
1578 rge_write_phy_ocp(sc, 0xa438, val | 0x1700);
1579
1580 rge_write_phy_ocp(sc, 0xa436, 0x815b);
1581 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00;
1582 rge_write_phy_ocp(sc, 0xa438, val | 0x1700);
1583
1584 RGE_PHY_CLRBIT(sc, 0xa4e0, 0x8000);
1585 RGE_PHY_CLRBIT(sc, 0xa5d4, 0x0020);
1586 RGE_PHY_CLRBIT(sc, 0xa654, 0x0800);
1587 RGE_PHY_SETBIT(sc, 0xa430, 0x1001);
1588 RGE_PHY_SETBIT(sc, 0xa442, 0x0080);
1589 }
1590
1591 static void
rge_phy_config_mac_r25d_2(struct rge_softc * sc)1592 rge_phy_config_mac_r25d_2(struct rge_softc *sc)
1593 {
1594 uint16_t val;
1595
1596 rge_phy_config_mcu(sc, RGE_MAC_R25D_2_RCODE_VER);
1597
1598 RGE_PHY_SETBIT(sc, 0xa442, 0x0800);
1599
1600 rge_patch_phy_mcu(sc, 1);
1601 val = rge_read_phy_ocp(sc, 0xbcd8) & ~0xc000;
1602 rge_write_phy_ocp(sc, 0xbcd8, val | 0x4000);
1603 RGE_PHY_SETBIT(sc, 0xbcd8, 0xc000);
1604 val = rge_read_phy_ocp(sc, 0xbcd8) & ~0xc000;
1605 rge_write_phy_ocp(sc, 0xbcd8, val | 0x4000);
1606 val = rge_read_phy_ocp(sc, 0xbc80) & ~0x001f;
1607 rge_write_phy_ocp(sc, 0xbc80, val | 0x0004);
1608 RGE_PHY_SETBIT(sc, 0xbc82, 0xe000);
1609 RGE_PHY_SETBIT(sc, 0xbc82, 0x1c00);
1610 val = rge_read_phy_ocp(sc, 0xbc80) & ~0x001f;
1611 rge_write_phy_ocp(sc, 0xbc80, val | 0x0005);
1612 val = rge_read_phy_ocp(sc, 0xbc82) & ~0x00e0;
1613 rge_write_phy_ocp(sc, 0xbc82, val | 0x0040);
1614 RGE_PHY_SETBIT(sc, 0xbc82, 0x001c);
1615 RGE_PHY_CLRBIT(sc, 0xbcd8, 0xc000);
1616 val = rge_read_phy_ocp(sc, 0xbcd8) & ~0xc000;
1617 rge_write_phy_ocp(sc, 0xbcd8, val | 0x8000);
1618 RGE_PHY_CLRBIT(sc, 0xbcd8, 0xc000);
1619 rge_patch_phy_mcu(sc, 0);
1620
1621 val = rge_read_phy_ocp(sc, 0xac7e) & ~0x01fc;
1622 rge_write_phy_ocp(sc, 0xac7e, val | 0x00b4);
1623 rge_write_phy_ocp(sc, 0xb87c, 0x8105);
1624 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
1625 rge_write_phy_ocp(sc, 0xb87e, val | 0x7a00);
1626 rge_write_phy_ocp(sc, 0xb87c, 0x8117);
1627 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
1628 rge_write_phy_ocp(sc, 0xb87e, val | 0x3a00);
1629 rge_write_phy_ocp(sc, 0xb87c, 0x8103);
1630 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
1631 rge_write_phy_ocp(sc, 0xb87e, val | 0x7400);
1632 rge_write_phy_ocp(sc, 0xb87c, 0x8115);
1633 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
1634 rge_write_phy_ocp(sc, 0xb87e, val | 0x3400);
1635 rge_write_phy_ocp(sc, 0xb87c, 0x8feb);
1636 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
1637 rge_write_phy_ocp(sc, 0xb87e, val | 0x0500);
1638 rge_write_phy_ocp(sc, 0xb87c, 0x8fea);
1639 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
1640 rge_write_phy_ocp(sc, 0xb87e, val | 0x0700);
1641 rge_write_phy_ocp(sc, 0xb87c, 0x80d6);
1642 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
1643 rge_write_phy_ocp(sc, 0xb87e, val | 0xef00);
1644 RGE_PHY_CLRBIT(sc, 0xa5d4, 0x0020);
1645 RGE_PHY_CLRBIT(sc, 0xa654, 0x0800);
1646 RGE_PHY_CLRBIT(sc, 0xa448, 0x0400);
1647 RGE_PHY_CLRBIT(sc, 0xa586, 0x0400);
1648 RGE_PHY_SETBIT(sc, 0xa430, 0x1001);
1649 RGE_PHY_SETBIT(sc, 0xa442, 0x0080);
1650 }
1651
1652 static void
rge_phy_config_mcu(struct rge_softc * sc,uint16_t rcodever)1653 rge_phy_config_mcu(struct rge_softc *sc, uint16_t rcodever)
1654 {
1655 if (sc->rge_rcodever != rcodever) {
1656 int i;
1657
1658 rge_patch_phy_mcu(sc, 1);
1659
1660 if (sc->rge_type == MAC_R25) {
1661 rge_write_phy_ocp(sc, 0xa436, 0x8024);
1662 rge_write_phy_ocp(sc, 0xa438, 0x8601);
1663 rge_write_phy_ocp(sc, 0xa436, 0xb82e);
1664 rge_write_phy_ocp(sc, 0xa438, 0x0001);
1665
1666 RGE_PHY_SETBIT(sc, 0xb820, 0x0080);
1667
1668 for (i = 0; i < nitems(mac_r25_mcu); i++)
1669 rge_write_phy_ocp(sc,
1670 mac_r25_mcu[i].reg, mac_r25_mcu[i].val);
1671
1672 RGE_PHY_CLRBIT(sc, 0xb820, 0x0080);
1673
1674 rge_write_phy_ocp(sc, 0xa436, 0);
1675 rge_write_phy_ocp(sc, 0xa438, 0);
1676 RGE_PHY_CLRBIT(sc, 0xb82e, 0x0001);
1677 rge_write_phy_ocp(sc, 0xa436, 0x8024);
1678 rge_write_phy_ocp(sc, 0xa438, 0);
1679 } else if (sc->rge_type == MAC_R25B) {
1680 for (i = 0; i < nitems(mac_r25b_mcu); i++)
1681 rge_write_phy_ocp(sc,
1682 mac_r25b_mcu[i].reg, mac_r25b_mcu[i].val);
1683 } else if (sc->rge_type == MAC_R25D_1) {
1684 for (i = 0; i < 2403; i++)
1685 rge_write_phy_ocp(sc,
1686 mac_r25d_1_mcu[i].reg,
1687 mac_r25d_1_mcu[i].val);
1688 rge_patch_phy_mcu(sc, 0);
1689
1690 rge_patch_phy_mcu(sc, 1);
1691 for (; i < 2528; i++)
1692 rge_write_phy_ocp(sc,
1693 mac_r25d_1_mcu[i].reg,
1694 mac_r25d_1_mcu[i].val);
1695 rge_patch_phy_mcu(sc, 0);
1696
1697 rge_patch_phy_mcu(sc, 1);
1698 for (; i < nitems(mac_r25d_1_mcu); i++)
1699 rge_write_phy_ocp(sc,
1700 mac_r25d_1_mcu[i].reg,
1701 mac_r25d_1_mcu[i].val);
1702 } else if (sc->rge_type == MAC_R25D_2) {
1703 for (i = 0; i < 1269; i++)
1704 rge_write_phy_ocp(sc,
1705 mac_r25d_2_mcu[i].reg,
1706 mac_r25d_2_mcu[i].val);
1707 rge_patch_phy_mcu(sc, 0);
1708
1709 rge_patch_phy_mcu(sc, 1);
1710 for (; i < nitems(mac_r25d_2_mcu); i++)
1711 rge_write_phy_ocp(sc,
1712 mac_r25d_2_mcu[i].reg,
1713 mac_r25d_2_mcu[i].val);
1714 } else if (sc->rge_type == MAC_R26_1) {
1715 for (i = 0; i < 6989; i++)
1716 rge_write_phy_ocp(sc,
1717 mac_r26_1_mcu[i].reg, mac_r26_1_mcu[i].val);
1718 rge_patch_phy_mcu(sc, 0);
1719
1720 rge_patch_phy_mcu(sc, 1);
1721 for (; i < nitems(mac_r26_1_mcu); i++)
1722 rge_write_phy_ocp(sc,
1723 mac_r26_1_mcu[i].reg, mac_r26_1_mcu[i].val);
1724 } else if (sc->rge_type == MAC_R26_2) {
1725 for (i = 0; i < nitems(mac_r26_2_mcu); i++)
1726 rge_write_phy_ocp(sc,
1727 mac_r26_2_mcu[i].reg, mac_r26_2_mcu[i].val);
1728 } else if (sc->rge_type == MAC_R27) {
1729 for (i = 0; i < 1887; i++)
1730 rge_write_phy_ocp(sc,
1731 mac_r27_mcu[i].reg, mac_r27_mcu[i].val);
1732 rge_patch_phy_mcu(sc, 0);
1733
1734 rge_patch_phy_mcu(sc, 1);
1735 for (; i < nitems(mac_r27_mcu); i++)
1736 rge_write_phy_ocp(sc,
1737 mac_r27_mcu[i].reg, mac_r27_mcu[i].val);
1738 }
1739
1740 rge_patch_phy_mcu(sc, 0);
1741
1742 /* Write ram code version. */
1743 rge_write_phy_ocp(sc, 0xa436, 0x801e);
1744 rge_write_phy_ocp(sc, 0xa438, rcodever);
1745 }
1746 }
1747
1748 void
rge_set_macaddr(struct rge_softc * sc,const uint8_t * addr)1749 rge_set_macaddr(struct rge_softc *sc, const uint8_t *addr)
1750 {
1751 RGE_SETBIT_1(sc, RGE_EECMD, RGE_EECMD_WRITECFG);
1752 RGE_WRITE_4(sc, RGE_MAC0,
1753 addr[3] << 24 | addr[2] << 16 | addr[1] << 8 | addr[0]);
1754 RGE_WRITE_4(sc, RGE_MAC4,
1755 addr[5] << 8 | addr[4]);
1756 RGE_CLRBIT_1(sc, RGE_EECMD, RGE_EECMD_WRITECFG);
1757 }
1758
1759 /**
1760 * @brief Read the mac address from the NIC EEPROM.
1761 *
1762 * Note this also calls rge_set_macaddr() which programs
1763 * it into the PPROM; I'm not sure why.
1764 *
1765 * Must be called with the driver lock held.
1766 */
1767 void
rge_get_macaddr(struct rge_softc * sc,uint8_t * addr)1768 rge_get_macaddr(struct rge_softc *sc, uint8_t *addr)
1769 {
1770 int i;
1771
1772 RGE_ASSERT_LOCKED(sc);
1773
1774 for (i = 0; i < ETHER_ADDR_LEN; i++)
1775 addr[i] = RGE_READ_1(sc, RGE_MAC0 + i);
1776
1777 *(uint32_t *)&addr[0] = RGE_READ_4(sc, RGE_ADDR0);
1778 *(uint16_t *)&addr[4] = RGE_READ_2(sc, RGE_ADDR1);
1779
1780 rge_set_macaddr(sc, addr);
1781 }
1782
1783 /**
1784 * @brief MAC hardware initialisation
1785 *
1786 * Must be called with the driver lock held.
1787 */
1788 static void
rge_hw_init(struct rge_softc * sc)1789 rge_hw_init(struct rge_softc *sc)
1790 {
1791 uint16_t reg;
1792
1793 RGE_ASSERT_LOCKED(sc);
1794
1795 rge_disable_aspm_clkreq(sc);
1796 RGE_CLRBIT_1(sc, 0xf1, 0x80);
1797
1798 /* Disable UPS. */
1799 RGE_MAC_CLRBIT(sc, 0xd40a, 0x0010);
1800
1801 /* Disable MAC MCU. */
1802 rge_disable_aspm_clkreq(sc);
1803 rge_write_mac_ocp(sc, 0xfc48, 0);
1804 for (reg = 0xfc28; reg < 0xfc48; reg += 2)
1805 rge_write_mac_ocp(sc, reg, 0);
1806 DELAY(3000);
1807 rge_write_mac_ocp(sc, 0xfc26, 0);
1808
1809 if (RGE_TYPE_R26(sc) || sc->rge_type == MAC_R27)
1810 rge_mac_config_ext_mcu(sc, sc->rge_type);
1811 else
1812 rge_mac_config_mcu(sc, sc->rge_type);
1813
1814 /* Disable PHY power saving. */
1815 if (sc->rge_type == MAC_R25)
1816 rge_disable_phy_ocp_pwrsave(sc);
1817
1818 /* Set PCIe uncorrectable error status. */
1819 rge_write_csi(sc, 0x108,
1820 rge_read_csi(sc, 0x108) | 0x00100000);
1821 }
1822
1823 void
rge_hw_reset(struct rge_softc * sc)1824 rge_hw_reset(struct rge_softc *sc)
1825 {
1826 /* Disable interrupts */
1827 RGE_WRITE_4(sc, RGE_IMR, 0);
1828 RGE_WRITE_4(sc, RGE_ISR, RGE_READ_4(sc, RGE_ISR));
1829
1830 /* Clear timer interrupts. */
1831 RGE_WRITE_4(sc, RGE_TIMERINT0, 0);
1832 RGE_WRITE_4(sc, RGE_TIMERINT1, 0);
1833 RGE_WRITE_4(sc, RGE_TIMERINT2, 0);
1834 RGE_WRITE_4(sc, RGE_TIMERINT3, 0);
1835
1836 rge_reset(sc);
1837 }
1838
1839 static void
rge_disable_phy_ocp_pwrsave(struct rge_softc * sc)1840 rge_disable_phy_ocp_pwrsave(struct rge_softc *sc)
1841 {
1842 if (rge_read_phy_ocp(sc, 0xc416) != 0x0500) {
1843 rge_patch_phy_mcu(sc, 1);
1844 rge_write_phy_ocp(sc, 0xc416, 0);
1845 rge_write_phy_ocp(sc, 0xc416, 0x0500);
1846 rge_patch_phy_mcu(sc, 0);
1847 }
1848 }
1849
1850 static void
rge_patch_phy_mcu(struct rge_softc * sc,int set)1851 rge_patch_phy_mcu(struct rge_softc *sc, int set)
1852 {
1853 int i;
1854
1855 if (set)
1856 RGE_PHY_SETBIT(sc, 0xb820, 0x0010);
1857 else
1858 RGE_PHY_CLRBIT(sc, 0xb820, 0x0010);
1859
1860 for (i = 0; i < 1000; i++) {
1861 if (set) {
1862 if ((rge_read_phy_ocp(sc, 0xb800) & 0x0040) != 0)
1863 break;
1864 } else {
1865 if (!(rge_read_phy_ocp(sc, 0xb800) & 0x0040))
1866 break;
1867 }
1868 DELAY(100);
1869 }
1870 if (i == 1000)
1871 RGE_PRINT_ERROR(sc, "timeout waiting to patch phy mcu\n");
1872 }
1873
1874 void
rge_config_imtype(struct rge_softc * sc,int imtype)1875 rge_config_imtype(struct rge_softc *sc, int imtype)
1876 {
1877 switch (imtype) {
1878 case RGE_IMTYPE_NONE:
1879 sc->rge_intrs = RGE_INTRS;
1880 break;
1881 case RGE_IMTYPE_SIM:
1882 sc->rge_intrs = RGE_INTRS_TIMER;
1883 break;
1884 default:
1885 RGE_PRINT_ERROR(sc, "unknown imtype %d", imtype);
1886 }
1887 }
1888
1889 void
rge_disable_aspm_clkreq(struct rge_softc * sc)1890 rge_disable_aspm_clkreq(struct rge_softc *sc)
1891 {
1892 int unlock = 1;
1893
1894 if ((RGE_READ_1(sc, RGE_EECMD) & RGE_EECMD_WRITECFG) ==
1895 RGE_EECMD_WRITECFG)
1896 unlock = 0;
1897
1898 if (unlock)
1899 RGE_SETBIT_1(sc, RGE_EECMD, RGE_EECMD_WRITECFG);
1900
1901 if (RGE_TYPE_R26(sc) || sc->rge_type == MAC_R27)
1902 RGE_CLRBIT_1(sc, RGE_INT_CFG0, 0x08);
1903 else
1904 RGE_CLRBIT_1(sc, RGE_CFG2, RGE_CFG2_CLKREQ_EN);
1905 RGE_CLRBIT_1(sc, RGE_CFG5, RGE_CFG5_PME_STS);
1906
1907 if (unlock)
1908 RGE_CLRBIT_1(sc, RGE_EECMD, RGE_EECMD_WRITECFG);
1909 }
1910
1911 static void
rge_disable_hw_im(struct rge_softc * sc)1912 rge_disable_hw_im(struct rge_softc *sc)
1913 {
1914 RGE_WRITE_2(sc, RGE_IM, 0);
1915 }
1916
1917 static void
rge_disable_sim_im(struct rge_softc * sc)1918 rge_disable_sim_im(struct rge_softc *sc)
1919 {
1920 RGE_WRITE_4(sc, RGE_TIMERINT0, 0);
1921 sc->rge_timerintr = 0;
1922 }
1923
1924 static void
rge_setup_sim_im(struct rge_softc * sc)1925 rge_setup_sim_im(struct rge_softc *sc)
1926 {
1927 RGE_WRITE_4(sc, RGE_TIMERINT0, 0x2600);
1928 RGE_WRITE_4(sc, RGE_TIMERCNT, 1);
1929 sc->rge_timerintr = 1;
1930 }
1931
1932 void
rge_setup_intr(struct rge_softc * sc,int imtype)1933 rge_setup_intr(struct rge_softc *sc, int imtype)
1934 {
1935 rge_config_imtype(sc, imtype);
1936
1937 /* Enable interrupts. */
1938 RGE_WRITE_4(sc, RGE_IMR, sc->rge_intrs);
1939
1940 switch (imtype) {
1941 case RGE_IMTYPE_NONE:
1942 rge_disable_sim_im(sc);
1943 rge_disable_hw_im(sc);
1944 break;
1945 case RGE_IMTYPE_SIM:
1946 rge_disable_hw_im(sc);
1947 rge_setup_sim_im(sc);
1948 break;
1949 default:
1950 RGE_PRINT_ERROR(sc, "unknown imtype %d", imtype);
1951 }
1952 }
1953
1954 static void
rge_switch_mcu_ram_page(struct rge_softc * sc,int page)1955 rge_switch_mcu_ram_page(struct rge_softc *sc, int page)
1956 {
1957 uint16_t val;
1958
1959 val = rge_read_mac_ocp(sc, 0xe446) & ~0x0003;
1960 val |= page;
1961 rge_write_mac_ocp(sc, 0xe446, val);
1962 }
1963
1964 static int
rge_exit_oob(struct rge_softc * sc)1965 rge_exit_oob(struct rge_softc *sc)
1966 {
1967 int error, i;
1968
1969 /* Disable RealWoW. */
1970 rge_write_mac_ocp(sc, 0xc0bc, 0x00ff);
1971
1972 if ((error = rge_reset(sc)) != 0)
1973 return error;
1974
1975 /* Disable OOB. */
1976 RGE_CLRBIT_1(sc, RGE_MCUCMD, RGE_MCUCMD_IS_OOB);
1977
1978 RGE_MAC_CLRBIT(sc, 0xe8de, 0x4000);
1979
1980 for (i = 0; i < 10; i++) {
1981 DELAY(100);
1982 if (RGE_READ_2(sc, RGE_TWICMD) & 0x0200)
1983 break;
1984 }
1985
1986 rge_write_mac_ocp(sc, 0xc0aa, 0x07d0);
1987 rge_write_mac_ocp(sc, 0xc0a6, 0x01b5);
1988 rge_write_mac_ocp(sc, 0xc01e, 0x5555);
1989
1990 for (i = 0; i < 10; i++) {
1991 DELAY(100);
1992 if (RGE_READ_2(sc, RGE_TWICMD) & 0x0200)
1993 break;
1994 }
1995
1996 if (rge_read_mac_ocp(sc, 0xd42c) & 0x0100) {
1997 for (i = 0; i < RGE_TIMEOUT; i++) {
1998 if ((rge_read_phy_ocp(sc, 0xa420) & 0x0007) == 2)
1999 break;
2000 DELAY(1000);
2001 }
2002 RGE_MAC_CLRBIT(sc, 0xd42c, 0x0100);
2003 if (sc->rge_type != MAC_R25)
2004 RGE_PHY_CLRBIT(sc, 0xa466, 0x0001);
2005 RGE_PHY_CLRBIT(sc, 0xa468, 0x000a);
2006 }
2007
2008 return 0;
2009 }
2010
2011 void
rge_write_csi(struct rge_softc * sc,uint32_t reg,uint32_t val)2012 rge_write_csi(struct rge_softc *sc, uint32_t reg, uint32_t val)
2013 {
2014 int i;
2015
2016 RGE_WRITE_4(sc, RGE_CSIDR, val);
2017 RGE_WRITE_4(sc, RGE_CSIAR, (reg & RGE_CSIAR_ADDR_MASK) |
2018 (RGE_CSIAR_BYTE_EN << RGE_CSIAR_BYTE_EN_SHIFT) | RGE_CSIAR_BUSY);
2019
2020 for (i = 0; i < 20000; i++) {
2021 DELAY(1);
2022 if (!(RGE_READ_4(sc, RGE_CSIAR) & RGE_CSIAR_BUSY))
2023 break;
2024 }
2025
2026 DELAY(20);
2027 }
2028
2029 uint32_t
rge_read_csi(struct rge_softc * sc,uint32_t reg)2030 rge_read_csi(struct rge_softc *sc, uint32_t reg)
2031 {
2032 int i;
2033
2034 RGE_WRITE_4(sc, RGE_CSIAR, (reg & RGE_CSIAR_ADDR_MASK) |
2035 (RGE_CSIAR_BYTE_EN << RGE_CSIAR_BYTE_EN_SHIFT));
2036
2037 for (i = 0; i < 20000; i++) {
2038 DELAY(1);
2039 if (RGE_READ_4(sc, RGE_CSIAR) & RGE_CSIAR_BUSY)
2040 break;
2041 }
2042
2043 DELAY(20);
2044
2045 return (RGE_READ_4(sc, RGE_CSIDR));
2046 }
2047
2048 void
rge_write_mac_ocp(struct rge_softc * sc,uint16_t reg,uint16_t val)2049 rge_write_mac_ocp(struct rge_softc *sc, uint16_t reg, uint16_t val)
2050 {
2051 uint32_t tmp;
2052
2053 tmp = (reg >> 1) << RGE_MACOCP_ADDR_SHIFT;
2054 tmp += val;
2055 tmp |= RGE_MACOCP_BUSY;
2056 RGE_WRITE_4(sc, RGE_MACOCP, tmp);
2057 }
2058
2059 uint16_t
rge_read_mac_ocp(struct rge_softc * sc,uint16_t reg)2060 rge_read_mac_ocp(struct rge_softc *sc, uint16_t reg)
2061 {
2062 uint32_t val;
2063
2064 val = (reg >> 1) << RGE_MACOCP_ADDR_SHIFT;
2065 RGE_WRITE_4(sc, RGE_MACOCP, val);
2066
2067 return (RGE_READ_4(sc, RGE_MACOCP) & RGE_MACOCP_DATA_MASK);
2068 }
2069
2070 static void
rge_write_ephy(struct rge_softc * sc,uint16_t reg,uint16_t val)2071 rge_write_ephy(struct rge_softc *sc, uint16_t reg, uint16_t val)
2072 {
2073 uint32_t tmp;
2074 int i;
2075
2076 tmp = (reg & RGE_EPHYAR_ADDR_MASK) << RGE_EPHYAR_ADDR_SHIFT;
2077 tmp |= RGE_EPHYAR_BUSY | (val & RGE_EPHYAR_DATA_MASK);
2078 RGE_WRITE_4(sc, RGE_EPHYAR, tmp);
2079
2080 for (i = 0; i < 20000; i++) {
2081 DELAY(1);
2082 if (!(RGE_READ_4(sc, RGE_EPHYAR) & RGE_EPHYAR_BUSY))
2083 break;
2084 }
2085
2086 DELAY(20);
2087 }
2088
2089 static uint16_t
rge_read_ephy(struct rge_softc * sc,uint16_t reg)2090 rge_read_ephy(struct rge_softc *sc, uint16_t reg)
2091 {
2092 uint32_t val;
2093 int i;
2094
2095 val = (reg & RGE_EPHYAR_ADDR_MASK) << RGE_EPHYAR_ADDR_SHIFT;
2096 RGE_WRITE_4(sc, RGE_EPHYAR, val);
2097
2098 for (i = 0; i < 20000; i++) {
2099 DELAY(1);
2100 val = RGE_READ_4(sc, RGE_EPHYAR);
2101 if (val & RGE_EPHYAR_BUSY)
2102 break;
2103 }
2104
2105 DELAY(20);
2106
2107 return (val & RGE_EPHYAR_DATA_MASK);
2108 }
2109
2110 static uint16_t
rge_check_ephy_ext_add(struct rge_softc * sc,uint16_t reg)2111 rge_check_ephy_ext_add(struct rge_softc *sc, uint16_t reg)
2112 {
2113 uint16_t val;
2114
2115 val = (reg >> 12);
2116 rge_write_ephy(sc, RGE_EPHYAR_EXT_ADDR, val);
2117
2118 return reg & 0x0fff;
2119 }
2120
2121 static void
rge_r27_write_ephy(struct rge_softc * sc,uint16_t reg,uint16_t val)2122 rge_r27_write_ephy(struct rge_softc *sc, uint16_t reg, uint16_t val)
2123 {
2124 rge_write_ephy(sc, rge_check_ephy_ext_add(sc, reg), val);
2125 }
2126
2127 void
rge_write_phy(struct rge_softc * sc,uint16_t addr,uint16_t reg,uint16_t val)2128 rge_write_phy(struct rge_softc *sc, uint16_t addr, uint16_t reg, uint16_t val)
2129 {
2130 uint16_t off, phyaddr;
2131
2132 phyaddr = addr ? addr : RGE_PHYBASE + (reg / 8);
2133 phyaddr <<= 4;
2134
2135 off = addr ? reg : 0x10 + (reg % 8);
2136
2137 phyaddr += (off - 16) << 1;
2138
2139 rge_write_phy_ocp(sc, phyaddr, val);
2140 }
2141
2142 uint16_t
rge_read_phy(struct rge_softc * sc,uint16_t addr,uint16_t reg)2143 rge_read_phy(struct rge_softc *sc, uint16_t addr, uint16_t reg)
2144 {
2145 uint16_t off, phyaddr;
2146
2147 phyaddr = addr ? addr : RGE_PHYBASE + (reg / 8);
2148 phyaddr <<= 4;
2149
2150 off = addr ? reg : 0x10 + (reg % 8);
2151
2152 phyaddr += (off - 16) << 1;
2153
2154 return (rge_read_phy_ocp(sc, phyaddr));
2155 }
2156
2157 void
rge_write_phy_ocp(struct rge_softc * sc,uint16_t reg,uint16_t val)2158 rge_write_phy_ocp(struct rge_softc *sc, uint16_t reg, uint16_t val)
2159 {
2160 uint32_t tmp;
2161 int i;
2162
2163 tmp = (reg >> 1) << RGE_PHYOCP_ADDR_SHIFT;
2164 tmp |= RGE_PHYOCP_BUSY | val;
2165 RGE_WRITE_4(sc, RGE_PHYOCP, tmp);
2166
2167 for (i = 0; i < 20000; i++) {
2168 DELAY(1);
2169 if (!(RGE_READ_4(sc, RGE_PHYOCP) & RGE_PHYOCP_BUSY))
2170 break;
2171 }
2172 }
2173
2174 uint16_t
rge_read_phy_ocp(struct rge_softc * sc,uint16_t reg)2175 rge_read_phy_ocp(struct rge_softc *sc, uint16_t reg)
2176 {
2177 uint32_t val;
2178 int i;
2179
2180 val = (reg >> 1) << RGE_PHYOCP_ADDR_SHIFT;
2181 RGE_WRITE_4(sc, RGE_PHYOCP, val);
2182
2183 for (i = 0; i < 20000; i++) {
2184 DELAY(1);
2185 val = RGE_READ_4(sc, RGE_PHYOCP);
2186 if (val & RGE_PHYOCP_BUSY)
2187 break;
2188 }
2189
2190 return (val & RGE_PHYOCP_DATA_MASK);
2191 }
2192
2193 int
rge_get_link_status(struct rge_softc * sc)2194 rge_get_link_status(struct rge_softc *sc)
2195 {
2196 return ((RGE_READ_2(sc, RGE_PHYSTAT) & RGE_PHYSTAT_LINK) ? 1 : 0);
2197 }
2198
2199 void
rge_wol_config(struct rge_softc * sc,int enable)2200 rge_wol_config(struct rge_softc *sc, int enable)
2201 {
2202 if (enable)
2203 RGE_MAC_SETBIT(sc, 0xc0b6, 0x0001);
2204 else
2205 RGE_MAC_CLRBIT(sc, 0xc0b6, 0x0001);
2206
2207 /* Enable config register write. */
2208 RGE_SETBIT_1(sc, RGE_EECMD, RGE_EECMD_WRITECFG);
2209
2210 /* Clear all WOL bits, then set as requested. */
2211 RGE_CLRBIT_1(sc, RGE_CFG3, RGE_CFG3_WOL_LINK | RGE_CFG3_WOL_MAGIC);
2212 RGE_CLRBIT_1(sc, RGE_CFG5, RGE_CFG5_WOL_LANWAKE |
2213 RGE_CFG5_WOL_UCAST | RGE_CFG5_WOL_MCAST | RGE_CFG5_WOL_BCAST);
2214 if (enable) {
2215 RGE_SETBIT_1(sc, RGE_CFG3, RGE_CFG3_WOL_MAGIC);
2216 RGE_SETBIT_1(sc, RGE_CFG5, RGE_CFG5_WOL_LANWAKE);
2217 }
2218
2219 /* Config register write done. */
2220 RGE_CLRBIT_1(sc, RGE_EECMD, RGE_EECMD_WRITECFG);
2221
2222 if (enable) {
2223 /* Disable RXDV gate so WOL packets can reach the NIC. */
2224 RGE_CLRBIT_1(sc, RGE_PPSW, 0x08);
2225 DELAY(2000);
2226
2227 /* Enable power management. */
2228 RGE_SETBIT_1(sc, RGE_CFG1, RGE_CFG1_PM_EN);
2229 RGE_SETBIT_1(sc, RGE_CFG2, RGE_CFG2_PMSTS_EN);
2230 }
2231 }
2232
2233