xref: /linux/include/linux/mlx5/mlx5_ifc.h (revision 8be4d31cb8aaeea27bde4b7ddb26e28a89062ebf) 
1 /*
2  * Copyright (c) 2013-2015, Mellanox Technologies, Ltd.  All rights reserved.
3  *
4  * This software is available to you under a choice of one of two
5  * licenses.  You may choose to be licensed under the terms of the GNU
6  * General Public License (GPL) Version 2, available from the file
7  * COPYING in the main directory of this source tree, or the
8  * OpenIB.org BSD license below:
9  *
10  *     Redistribution and use in source and binary forms, with or
11  *     without modification, are permitted provided that the following
12  *     conditions are met:
13  *
14  *      - Redistributions of source code must retain the above
15  *        copyright notice, this list of conditions and the following
16  *        disclaimer.
17  *
18  *      - Redistributions in binary form must reproduce the above
19  *        copyright notice, this list of conditions and the following
20  *        disclaimer in the documentation and/or other materials
21  *        provided with the distribution.
22  *
23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30  * SOFTWARE.
31 */
32 #ifndef MLX5_IFC_H
33 #define MLX5_IFC_H
34 
35 #include "mlx5_ifc_fpga.h"
36 
37 enum {
38 	MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS                   = 0x0,
39 	MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED             = 0x1,
40 	MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED           = 0x2,
41 	MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED                  = 0x3,
42 	MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED                    = 0x13,
43 	MLX5_EVENT_TYPE_CODING_SRQ_LIMIT                           = 0x14,
44 	MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED          = 0x1c,
45 	MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION            = 0x1d,
46 	MLX5_EVENT_TYPE_CODING_CQ_ERROR                            = 0x4,
47 	MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR         = 0x5,
48 	MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED               = 0x7,
49 	MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT                    = 0xc,
50 	MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR      = 0x10,
51 	MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR     = 0x11,
52 	MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR        = 0x12,
53 	MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR                      = 0x8,
54 	MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE                   = 0x9,
55 	MLX5_EVENT_TYPE_CODING_GPIO_EVENT                          = 0x15,
56 	MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19,
57 	MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a,
58 	MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT                      = 0x1b,
59 	MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT         = 0x1f,
60 	MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION        = 0xa,
61 	MLX5_EVENT_TYPE_CODING_PAGE_REQUEST                        = 0xb,
62 	MLX5_EVENT_TYPE_CODING_FPGA_ERROR                          = 0x20,
63 	MLX5_EVENT_TYPE_CODING_FPGA_QP_ERROR                       = 0x21
64 };
65 
66 enum {
67 	MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE        = 0x0,
68 	MLX5_SET_HCA_CAP_OP_MOD_ETHERNET_OFFLOADS     = 0x1,
69 	MLX5_SET_HCA_CAP_OP_MOD_ODP                   = 0x2,
70 	MLX5_SET_HCA_CAP_OP_MOD_ATOMIC                = 0x3,
71 	MLX5_SET_HCA_CAP_OP_MOD_ROCE                  = 0x4,
72 	MLX5_SET_HCA_CAP_OP_MOD_IPSEC                 = 0x15,
73 	MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE2       = 0x20,
74 	MLX5_SET_HCA_CAP_OP_MOD_PORT_SELECTION        = 0x25,
75 };
76 
77 enum {
78 	MLX5_SHARED_RESOURCE_UID = 0xffff,
79 };
80 
81 enum {
82 	MLX5_OBJ_TYPE_SW_ICM = 0x0008,
83 	MLX5_OBJ_TYPE_GENEVE_TLV_OPT = 0x000b,
84 	MLX5_OBJ_TYPE_VIRTIO_NET_Q = 0x000d,
85 	MLX5_OBJ_TYPE_VIRTIO_Q_COUNTERS = 0x001c,
86 	MLX5_OBJ_TYPE_MATCH_DEFINER = 0x0018,
87 	MLX5_OBJ_TYPE_HEADER_MODIFY_ARGUMENT  = 0x23,
88 	MLX5_OBJ_TYPE_STC = 0x0040,
89 	MLX5_OBJ_TYPE_RTC = 0x0041,
90 	MLX5_OBJ_TYPE_STE = 0x0042,
91 	MLX5_OBJ_TYPE_MODIFY_HDR_PATTERN = 0x0043,
92 	MLX5_OBJ_TYPE_PAGE_TRACK = 0x46,
93 	MLX5_OBJ_TYPE_MKEY = 0xff01,
94 	MLX5_OBJ_TYPE_QP = 0xff02,
95 	MLX5_OBJ_TYPE_PSV = 0xff03,
96 	MLX5_OBJ_TYPE_RMP = 0xff04,
97 	MLX5_OBJ_TYPE_XRC_SRQ = 0xff05,
98 	MLX5_OBJ_TYPE_RQ = 0xff06,
99 	MLX5_OBJ_TYPE_SQ = 0xff07,
100 	MLX5_OBJ_TYPE_TIR = 0xff08,
101 	MLX5_OBJ_TYPE_TIS = 0xff09,
102 	MLX5_OBJ_TYPE_DCT = 0xff0a,
103 	MLX5_OBJ_TYPE_XRQ = 0xff0b,
104 	MLX5_OBJ_TYPE_RQT = 0xff0e,
105 	MLX5_OBJ_TYPE_FLOW_COUNTER = 0xff0f,
106 	MLX5_OBJ_TYPE_CQ = 0xff10,
107 	MLX5_OBJ_TYPE_FT_ALIAS = 0xff15,
108 };
109 
110 enum {
111 	MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM = (1ULL << MLX5_OBJ_TYPE_SW_ICM),
112 	MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT = (1ULL << 11),
113 	MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q = (1ULL << 13),
114 	MLX5_GENERAL_OBJ_TYPES_CAP_HEADER_MODIFY_ARGUMENT =
115 		(1ULL << MLX5_OBJ_TYPE_HEADER_MODIFY_ARGUMENT),
116 	MLX5_GENERAL_OBJ_TYPES_CAP_MACSEC_OFFLOAD = (1ULL << 39),
117 };
118 
119 enum {
120 	MLX5_CMD_OP_QUERY_HCA_CAP                 = 0x100,
121 	MLX5_CMD_OP_QUERY_ADAPTER                 = 0x101,
122 	MLX5_CMD_OP_INIT_HCA                      = 0x102,
123 	MLX5_CMD_OP_TEARDOWN_HCA                  = 0x103,
124 	MLX5_CMD_OP_ENABLE_HCA                    = 0x104,
125 	MLX5_CMD_OP_DISABLE_HCA                   = 0x105,
126 	MLX5_CMD_OP_QUERY_PAGES                   = 0x107,
127 	MLX5_CMD_OP_MANAGE_PAGES                  = 0x108,
128 	MLX5_CMD_OP_SET_HCA_CAP                   = 0x109,
129 	MLX5_CMD_OP_QUERY_ISSI                    = 0x10a,
130 	MLX5_CMD_OP_SET_ISSI                      = 0x10b,
131 	MLX5_CMD_OP_SET_DRIVER_VERSION            = 0x10d,
132 	MLX5_CMD_OP_QUERY_SF_PARTITION            = 0x111,
133 	MLX5_CMD_OP_ALLOC_SF                      = 0x113,
134 	MLX5_CMD_OP_DEALLOC_SF                    = 0x114,
135 	MLX5_CMD_OP_SUSPEND_VHCA                  = 0x115,
136 	MLX5_CMD_OP_RESUME_VHCA                   = 0x116,
137 	MLX5_CMD_OP_QUERY_VHCA_MIGRATION_STATE    = 0x117,
138 	MLX5_CMD_OP_SAVE_VHCA_STATE               = 0x118,
139 	MLX5_CMD_OP_LOAD_VHCA_STATE               = 0x119,
140 	MLX5_CMD_OP_CREATE_MKEY                   = 0x200,
141 	MLX5_CMD_OP_QUERY_MKEY                    = 0x201,
142 	MLX5_CMD_OP_DESTROY_MKEY                  = 0x202,
143 	MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS        = 0x203,
144 	MLX5_CMD_OP_PAGE_FAULT_RESUME             = 0x204,
145 	MLX5_CMD_OP_ALLOC_MEMIC                   = 0x205,
146 	MLX5_CMD_OP_DEALLOC_MEMIC                 = 0x206,
147 	MLX5_CMD_OP_MODIFY_MEMIC                  = 0x207,
148 	MLX5_CMD_OP_CREATE_EQ                     = 0x301,
149 	MLX5_CMD_OP_DESTROY_EQ                    = 0x302,
150 	MLX5_CMD_OP_QUERY_EQ                      = 0x303,
151 	MLX5_CMD_OP_GEN_EQE                       = 0x304,
152 	MLX5_CMD_OP_CREATE_CQ                     = 0x400,
153 	MLX5_CMD_OP_DESTROY_CQ                    = 0x401,
154 	MLX5_CMD_OP_QUERY_CQ                      = 0x402,
155 	MLX5_CMD_OP_MODIFY_CQ                     = 0x403,
156 	MLX5_CMD_OP_CREATE_QP                     = 0x500,
157 	MLX5_CMD_OP_DESTROY_QP                    = 0x501,
158 	MLX5_CMD_OP_RST2INIT_QP                   = 0x502,
159 	MLX5_CMD_OP_INIT2RTR_QP                   = 0x503,
160 	MLX5_CMD_OP_RTR2RTS_QP                    = 0x504,
161 	MLX5_CMD_OP_RTS2RTS_QP                    = 0x505,
162 	MLX5_CMD_OP_SQERR2RTS_QP                  = 0x506,
163 	MLX5_CMD_OP_2ERR_QP                       = 0x507,
164 	MLX5_CMD_OP_2RST_QP                       = 0x50a,
165 	MLX5_CMD_OP_QUERY_QP                      = 0x50b,
166 	MLX5_CMD_OP_SQD_RTS_QP                    = 0x50c,
167 	MLX5_CMD_OP_INIT2INIT_QP                  = 0x50e,
168 	MLX5_CMD_OP_CREATE_PSV                    = 0x600,
169 	MLX5_CMD_OP_DESTROY_PSV                   = 0x601,
170 	MLX5_CMD_OP_CREATE_SRQ                    = 0x700,
171 	MLX5_CMD_OP_DESTROY_SRQ                   = 0x701,
172 	MLX5_CMD_OP_QUERY_SRQ                     = 0x702,
173 	MLX5_CMD_OP_ARM_RQ                        = 0x703,
174 	MLX5_CMD_OP_CREATE_XRC_SRQ                = 0x705,
175 	MLX5_CMD_OP_DESTROY_XRC_SRQ               = 0x706,
176 	MLX5_CMD_OP_QUERY_XRC_SRQ                 = 0x707,
177 	MLX5_CMD_OP_ARM_XRC_SRQ                   = 0x708,
178 	MLX5_CMD_OP_CREATE_DCT                    = 0x710,
179 	MLX5_CMD_OP_DESTROY_DCT                   = 0x711,
180 	MLX5_CMD_OP_DRAIN_DCT                     = 0x712,
181 	MLX5_CMD_OP_QUERY_DCT                     = 0x713,
182 	MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION     = 0x714,
183 	MLX5_CMD_OP_CREATE_XRQ                    = 0x717,
184 	MLX5_CMD_OP_DESTROY_XRQ                   = 0x718,
185 	MLX5_CMD_OP_QUERY_XRQ                     = 0x719,
186 	MLX5_CMD_OP_ARM_XRQ                       = 0x71a,
187 	MLX5_CMD_OP_QUERY_XRQ_DC_PARAMS_ENTRY     = 0x725,
188 	MLX5_CMD_OP_SET_XRQ_DC_PARAMS_ENTRY       = 0x726,
189 	MLX5_CMD_OP_QUERY_XRQ_ERROR_PARAMS        = 0x727,
190 	MLX5_CMD_OP_RELEASE_XRQ_ERROR             = 0x729,
191 	MLX5_CMD_OP_MODIFY_XRQ                    = 0x72a,
192 	MLX5_CMD_OP_QUERY_ESW_FUNCTIONS           = 0x740,
193 	MLX5_CMD_OP_QUERY_VPORT_STATE             = 0x750,
194 	MLX5_CMD_OP_MODIFY_VPORT_STATE            = 0x751,
195 	MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT       = 0x752,
196 	MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT      = 0x753,
197 	MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT       = 0x754,
198 	MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT      = 0x755,
199 	MLX5_CMD_OP_QUERY_ROCE_ADDRESS            = 0x760,
200 	MLX5_CMD_OP_SET_ROCE_ADDRESS              = 0x761,
201 	MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT       = 0x762,
202 	MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT      = 0x763,
203 	MLX5_CMD_OP_QUERY_HCA_VPORT_GID           = 0x764,
204 	MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY          = 0x765,
205 	MLX5_CMD_OP_QUERY_VNIC_ENV                = 0x76f,
206 	MLX5_CMD_OP_QUERY_VPORT_COUNTER           = 0x770,
207 	MLX5_CMD_OP_ALLOC_Q_COUNTER               = 0x771,
208 	MLX5_CMD_OP_DEALLOC_Q_COUNTER             = 0x772,
209 	MLX5_CMD_OP_QUERY_Q_COUNTER               = 0x773,
210 	MLX5_CMD_OP_SET_MONITOR_COUNTER           = 0x774,
211 	MLX5_CMD_OP_ARM_MONITOR_COUNTER           = 0x775,
212 	MLX5_CMD_OP_SET_PP_RATE_LIMIT             = 0x780,
213 	MLX5_CMD_OP_QUERY_RATE_LIMIT              = 0x781,
214 	MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT      = 0x782,
215 	MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT     = 0x783,
216 	MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT       = 0x784,
217 	MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT      = 0x785,
218 	MLX5_CMD_OP_CREATE_QOS_PARA_VPORT         = 0x786,
219 	MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT        = 0x787,
220 	MLX5_CMD_OP_ALLOC_PD                      = 0x800,
221 	MLX5_CMD_OP_DEALLOC_PD                    = 0x801,
222 	MLX5_CMD_OP_ALLOC_UAR                     = 0x802,
223 	MLX5_CMD_OP_DEALLOC_UAR                   = 0x803,
224 	MLX5_CMD_OP_CONFIG_INT_MODERATION         = 0x804,
225 	MLX5_CMD_OP_ACCESS_REG                    = 0x805,
226 	MLX5_CMD_OP_ATTACH_TO_MCG                 = 0x806,
227 	MLX5_CMD_OP_DETACH_FROM_MCG               = 0x807,
228 	MLX5_CMD_OP_GET_DROPPED_PACKET_LOG        = 0x80a,
229 	MLX5_CMD_OP_MAD_IFC                       = 0x50d,
230 	MLX5_CMD_OP_QUERY_MAD_DEMUX               = 0x80b,
231 	MLX5_CMD_OP_SET_MAD_DEMUX                 = 0x80c,
232 	MLX5_CMD_OP_NOP                           = 0x80d,
233 	MLX5_CMD_OP_ALLOC_XRCD                    = 0x80e,
234 	MLX5_CMD_OP_DEALLOC_XRCD                  = 0x80f,
235 	MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN        = 0x816,
236 	MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN      = 0x817,
237 	MLX5_CMD_OP_QUERY_CONG_STATUS             = 0x822,
238 	MLX5_CMD_OP_MODIFY_CONG_STATUS            = 0x823,
239 	MLX5_CMD_OP_QUERY_CONG_PARAMS             = 0x824,
240 	MLX5_CMD_OP_MODIFY_CONG_PARAMS            = 0x825,
241 	MLX5_CMD_OP_QUERY_CONG_STATISTICS         = 0x826,
242 	MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT           = 0x827,
243 	MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT        = 0x828,
244 	MLX5_CMD_OP_SET_L2_TABLE_ENTRY            = 0x829,
245 	MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY          = 0x82a,
246 	MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY         = 0x82b,
247 	MLX5_CMD_OP_SET_WOL_ROL                   = 0x830,
248 	MLX5_CMD_OP_QUERY_WOL_ROL                 = 0x831,
249 	MLX5_CMD_OP_CREATE_LAG                    = 0x840,
250 	MLX5_CMD_OP_MODIFY_LAG                    = 0x841,
251 	MLX5_CMD_OP_QUERY_LAG                     = 0x842,
252 	MLX5_CMD_OP_DESTROY_LAG                   = 0x843,
253 	MLX5_CMD_OP_CREATE_VPORT_LAG              = 0x844,
254 	MLX5_CMD_OP_DESTROY_VPORT_LAG             = 0x845,
255 	MLX5_CMD_OP_CREATE_TIR                    = 0x900,
256 	MLX5_CMD_OP_MODIFY_TIR                    = 0x901,
257 	MLX5_CMD_OP_DESTROY_TIR                   = 0x902,
258 	MLX5_CMD_OP_QUERY_TIR                     = 0x903,
259 	MLX5_CMD_OP_CREATE_SQ                     = 0x904,
260 	MLX5_CMD_OP_MODIFY_SQ                     = 0x905,
261 	MLX5_CMD_OP_DESTROY_SQ                    = 0x906,
262 	MLX5_CMD_OP_QUERY_SQ                      = 0x907,
263 	MLX5_CMD_OP_CREATE_RQ                     = 0x908,
264 	MLX5_CMD_OP_MODIFY_RQ                     = 0x909,
265 	MLX5_CMD_OP_SET_DELAY_DROP_PARAMS         = 0x910,
266 	MLX5_CMD_OP_DESTROY_RQ                    = 0x90a,
267 	MLX5_CMD_OP_QUERY_RQ                      = 0x90b,
268 	MLX5_CMD_OP_CREATE_RMP                    = 0x90c,
269 	MLX5_CMD_OP_MODIFY_RMP                    = 0x90d,
270 	MLX5_CMD_OP_DESTROY_RMP                   = 0x90e,
271 	MLX5_CMD_OP_QUERY_RMP                     = 0x90f,
272 	MLX5_CMD_OP_CREATE_TIS                    = 0x912,
273 	MLX5_CMD_OP_MODIFY_TIS                    = 0x913,
274 	MLX5_CMD_OP_DESTROY_TIS                   = 0x914,
275 	MLX5_CMD_OP_QUERY_TIS                     = 0x915,
276 	MLX5_CMD_OP_CREATE_RQT                    = 0x916,
277 	MLX5_CMD_OP_MODIFY_RQT                    = 0x917,
278 	MLX5_CMD_OP_DESTROY_RQT                   = 0x918,
279 	MLX5_CMD_OP_QUERY_RQT                     = 0x919,
280 	MLX5_CMD_OP_SET_FLOW_TABLE_ROOT		  = 0x92f,
281 	MLX5_CMD_OP_CREATE_FLOW_TABLE             = 0x930,
282 	MLX5_CMD_OP_DESTROY_FLOW_TABLE            = 0x931,
283 	MLX5_CMD_OP_QUERY_FLOW_TABLE              = 0x932,
284 	MLX5_CMD_OP_CREATE_FLOW_GROUP             = 0x933,
285 	MLX5_CMD_OP_DESTROY_FLOW_GROUP            = 0x934,
286 	MLX5_CMD_OP_QUERY_FLOW_GROUP              = 0x935,
287 	MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY          = 0x936,
288 	MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY        = 0x937,
289 	MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY       = 0x938,
290 	MLX5_CMD_OP_ALLOC_FLOW_COUNTER            = 0x939,
291 	MLX5_CMD_OP_DEALLOC_FLOW_COUNTER          = 0x93a,
292 	MLX5_CMD_OP_QUERY_FLOW_COUNTER            = 0x93b,
293 	MLX5_CMD_OP_MODIFY_FLOW_TABLE             = 0x93c,
294 	MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT = 0x93d,
295 	MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT = 0x93e,
296 	MLX5_CMD_OP_QUERY_PACKET_REFORMAT_CONTEXT = 0x93f,
297 	MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT   = 0x940,
298 	MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941,
299 	MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT   = 0x942,
300 	MLX5_CMD_OP_FPGA_CREATE_QP                = 0x960,
301 	MLX5_CMD_OP_FPGA_MODIFY_QP                = 0x961,
302 	MLX5_CMD_OP_FPGA_QUERY_QP                 = 0x962,
303 	MLX5_CMD_OP_FPGA_DESTROY_QP               = 0x963,
304 	MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS        = 0x964,
305 	MLX5_CMD_OP_CREATE_GENERAL_OBJECT         = 0xa00,
306 	MLX5_CMD_OP_MODIFY_GENERAL_OBJECT         = 0xa01,
307 	MLX5_CMD_OP_QUERY_GENERAL_OBJECT          = 0xa02,
308 	MLX5_CMD_OP_DESTROY_GENERAL_OBJECT        = 0xa03,
309 	MLX5_CMD_OP_CREATE_UCTX                   = 0xa04,
310 	MLX5_CMD_OP_DESTROY_UCTX                  = 0xa06,
311 	MLX5_CMD_OP_CREATE_UMEM                   = 0xa08,
312 	MLX5_CMD_OP_DESTROY_UMEM                  = 0xa0a,
313 	MLX5_CMD_OP_SYNC_STEERING                 = 0xb00,
314 	MLX5_CMD_OP_QUERY_VHCA_STATE              = 0xb0d,
315 	MLX5_CMD_OP_MODIFY_VHCA_STATE             = 0xb0e,
316 	MLX5_CMD_OP_SYNC_CRYPTO                   = 0xb12,
317 	MLX5_CMD_OP_ALLOW_OTHER_VHCA_ACCESS       = 0xb16,
318 	MLX5_CMD_OP_GENERATE_WQE                  = 0xb17,
319 	MLX5_CMD_OPCODE_QUERY_VUID                = 0xb22,
320 	MLX5_CMD_OP_MAX
321 };
322 
323 /* Valid range for general commands that don't work over an object */
324 enum {
325 	MLX5_CMD_OP_GENERAL_START = 0xb00,
326 	MLX5_CMD_OP_GENERAL_END = 0xd00,
327 };
328 
329 enum {
330 	MLX5_FT_NIC_RX_2_NIC_RX_RDMA = BIT(0),
331 	MLX5_FT_NIC_TX_RDMA_2_NIC_TX = BIT(1),
332 };
333 
334 enum {
335 	MLX5_CMD_OP_MOD_UPDATE_HEADER_MODIFY_ARGUMENT = 0x1,
336 };
337 
338 struct mlx5_ifc_flow_table_fields_supported_bits {
339 	u8         outer_dmac[0x1];
340 	u8         outer_smac[0x1];
341 	u8         outer_ether_type[0x1];
342 	u8         outer_ip_version[0x1];
343 	u8         outer_first_prio[0x1];
344 	u8         outer_first_cfi[0x1];
345 	u8         outer_first_vid[0x1];
346 	u8         outer_ipv4_ttl[0x1];
347 	u8         outer_second_prio[0x1];
348 	u8         outer_second_cfi[0x1];
349 	u8         outer_second_vid[0x1];
350 	u8         reserved_at_b[0x1];
351 	u8         outer_sip[0x1];
352 	u8         outer_dip[0x1];
353 	u8         outer_frag[0x1];
354 	u8         outer_ip_protocol[0x1];
355 	u8         outer_ip_ecn[0x1];
356 	u8         outer_ip_dscp[0x1];
357 	u8         outer_udp_sport[0x1];
358 	u8         outer_udp_dport[0x1];
359 	u8         outer_tcp_sport[0x1];
360 	u8         outer_tcp_dport[0x1];
361 	u8         outer_tcp_flags[0x1];
362 	u8         outer_gre_protocol[0x1];
363 	u8         outer_gre_key[0x1];
364 	u8         outer_vxlan_vni[0x1];
365 	u8         outer_geneve_vni[0x1];
366 	u8         outer_geneve_oam[0x1];
367 	u8         outer_geneve_protocol_type[0x1];
368 	u8         outer_geneve_opt_len[0x1];
369 	u8         source_vhca_port[0x1];
370 	u8         source_eswitch_port[0x1];
371 
372 	u8         inner_dmac[0x1];
373 	u8         inner_smac[0x1];
374 	u8         inner_ether_type[0x1];
375 	u8         inner_ip_version[0x1];
376 	u8         inner_first_prio[0x1];
377 	u8         inner_first_cfi[0x1];
378 	u8         inner_first_vid[0x1];
379 	u8         reserved_at_27[0x1];
380 	u8         inner_second_prio[0x1];
381 	u8         inner_second_cfi[0x1];
382 	u8         inner_second_vid[0x1];
383 	u8         reserved_at_2b[0x1];
384 	u8         inner_sip[0x1];
385 	u8         inner_dip[0x1];
386 	u8         inner_frag[0x1];
387 	u8         inner_ip_protocol[0x1];
388 	u8         inner_ip_ecn[0x1];
389 	u8         inner_ip_dscp[0x1];
390 	u8         inner_udp_sport[0x1];
391 	u8         inner_udp_dport[0x1];
392 	u8         inner_tcp_sport[0x1];
393 	u8         inner_tcp_dport[0x1];
394 	u8         inner_tcp_flags[0x1];
395 	u8         reserved_at_37[0x9];
396 
397 	u8         geneve_tlv_option_0_data[0x1];
398 	u8         geneve_tlv_option_0_exist[0x1];
399 	u8         reserved_at_42[0x3];
400 	u8         outer_first_mpls_over_udp[0x4];
401 	u8         outer_first_mpls_over_gre[0x4];
402 	u8         inner_first_mpls[0x4];
403 	u8         outer_first_mpls[0x4];
404 	u8         reserved_at_55[0x2];
405 	u8	   outer_esp_spi[0x1];
406 	u8         reserved_at_58[0x2];
407 	u8         bth_dst_qp[0x1];
408 	u8         reserved_at_5b[0x5];
409 
410 	u8         reserved_at_60[0x18];
411 	u8         metadata_reg_c_7[0x1];
412 	u8         metadata_reg_c_6[0x1];
413 	u8         metadata_reg_c_5[0x1];
414 	u8         metadata_reg_c_4[0x1];
415 	u8         metadata_reg_c_3[0x1];
416 	u8         metadata_reg_c_2[0x1];
417 	u8         metadata_reg_c_1[0x1];
418 	u8         metadata_reg_c_0[0x1];
419 };
420 
421 /* Table 2170 - Flow Table Fields Supported 2 Format */
422 struct mlx5_ifc_flow_table_fields_supported_2_bits {
423 	u8         inner_l4_type_ext[0x1];
424 	u8         outer_l4_type_ext[0x1];
425 	u8         inner_l4_type[0x1];
426 	u8         outer_l4_type[0x1];
427 	u8         reserved_at_4[0xa];
428 	u8         bth_opcode[0x1];
429 	u8         reserved_at_f[0x1];
430 	u8         tunnel_header_0_1[0x1];
431 	u8         reserved_at_11[0xf];
432 
433 	u8         reserved_at_20[0xf];
434 	u8         ipsec_next_header[0x1];
435 	u8         reserved_at_30[0x10];
436 
437 	u8         reserved_at_40[0x40];
438 };
439 
440 struct mlx5_ifc_flow_table_prop_layout_bits {
441 	u8         ft_support[0x1];
442 	u8         reserved_at_1[0x1];
443 	u8         flow_counter[0x1];
444 	u8	   flow_modify_en[0x1];
445 	u8         modify_root[0x1];
446 	u8         identified_miss_table_mode[0x1];
447 	u8         flow_table_modify[0x1];
448 	u8         reformat[0x1];
449 	u8         decap[0x1];
450 	u8         reset_root_to_default[0x1];
451 	u8         pop_vlan[0x1];
452 	u8         push_vlan[0x1];
453 	u8         reserved_at_c[0x1];
454 	u8         pop_vlan_2[0x1];
455 	u8         push_vlan_2[0x1];
456 	u8	   reformat_and_vlan_action[0x1];
457 	u8	   reserved_at_10[0x1];
458 	u8         sw_owner[0x1];
459 	u8	   reformat_l3_tunnel_to_l2[0x1];
460 	u8	   reformat_l2_to_l3_tunnel[0x1];
461 	u8	   reformat_and_modify_action[0x1];
462 	u8	   ignore_flow_level[0x1];
463 	u8         reserved_at_16[0x1];
464 	u8	   table_miss_action_domain[0x1];
465 	u8         termination_table[0x1];
466 	u8         reformat_and_fwd_to_table[0x1];
467 	u8         reserved_at_1a[0x2];
468 	u8         ipsec_encrypt[0x1];
469 	u8         ipsec_decrypt[0x1];
470 	u8         sw_owner_v2[0x1];
471 	u8         reserved_at_1f[0x1];
472 
473 	u8         termination_table_raw_traffic[0x1];
474 	u8         reserved_at_21[0x1];
475 	u8         log_max_ft_size[0x6];
476 	u8         log_max_modify_header_context[0x8];
477 	u8         max_modify_header_actions[0x8];
478 	u8         max_ft_level[0x8];
479 
480 	u8         reformat_add_esp_trasport[0x1];
481 	u8         reformat_l2_to_l3_esp_tunnel[0x1];
482 	u8         reformat_add_esp_transport_over_udp[0x1];
483 	u8         reformat_del_esp_trasport[0x1];
484 	u8         reformat_l3_esp_tunnel_to_l2[0x1];
485 	u8         reformat_del_esp_transport_over_udp[0x1];
486 	u8         execute_aso[0x1];
487 	u8         reserved_at_47[0x19];
488 
489 	u8         reserved_at_60[0x2];
490 	u8         reformat_insert[0x1];
491 	u8         reformat_remove[0x1];
492 	u8         macsec_encrypt[0x1];
493 	u8         macsec_decrypt[0x1];
494 	u8         reserved_at_66[0x2];
495 	u8         reformat_add_macsec[0x1];
496 	u8         reformat_remove_macsec[0x1];
497 	u8         reparse[0x1];
498 	u8         reserved_at_6b[0x1];
499 	u8         cross_vhca_object[0x1];
500 	u8         reformat_l2_to_l3_audp_tunnel[0x1];
501 	u8         reformat_l3_audp_tunnel_to_l2[0x1];
502 	u8         ignore_flow_level_rtc_valid[0x1];
503 	u8         reserved_at_70[0x8];
504 	u8         log_max_ft_num[0x8];
505 
506 	u8         reserved_at_80[0x10];
507 	u8         log_max_flow_counter[0x8];
508 	u8         log_max_destination[0x8];
509 
510 	u8         reserved_at_a0[0x18];
511 	u8         log_max_flow[0x8];
512 
513 	u8         reserved_at_c0[0x40];
514 
515 	struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
516 
517 	struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
518 };
519 
520 struct mlx5_ifc_odp_per_transport_service_cap_bits {
521 	u8         send[0x1];
522 	u8         receive[0x1];
523 	u8         write[0x1];
524 	u8         read[0x1];
525 	u8         atomic[0x1];
526 	u8         srq_receive[0x1];
527 	u8         reserved_at_6[0x1a];
528 };
529 
530 struct mlx5_ifc_ipv4_layout_bits {
531 	u8         reserved_at_0[0x60];
532 
533 	u8         ipv4[0x20];
534 };
535 
536 struct mlx5_ifc_ipv6_layout_bits {
537 	u8         ipv6[16][0x8];
538 };
539 
540 struct mlx5_ifc_ipv6_simple_layout_bits {
541 	u8         ipv6_127_96[0x20];
542 	u8         ipv6_95_64[0x20];
543 	u8         ipv6_63_32[0x20];
544 	u8         ipv6_31_0[0x20];
545 };
546 
547 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits {
548 	struct mlx5_ifc_ipv6_simple_layout_bits ipv6_simple_layout;
549 	struct mlx5_ifc_ipv6_layout_bits ipv6_layout;
550 	struct mlx5_ifc_ipv4_layout_bits ipv4_layout;
551 	u8         reserved_at_0[0x80];
552 };
553 
554 enum {
555 	MLX5_PACKET_L4_TYPE_NONE,
556 	MLX5_PACKET_L4_TYPE_TCP,
557 	MLX5_PACKET_L4_TYPE_UDP,
558 };
559 
560 enum {
561 	MLX5_PACKET_L4_TYPE_EXT_NONE,
562 	MLX5_PACKET_L4_TYPE_EXT_TCP,
563 	MLX5_PACKET_L4_TYPE_EXT_UDP,
564 	MLX5_PACKET_L4_TYPE_EXT_ICMP,
565 };
566 
567 struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
568 	u8         smac_47_16[0x20];
569 
570 	u8         smac_15_0[0x10];
571 	u8         ethertype[0x10];
572 
573 	u8         dmac_47_16[0x20];
574 
575 	u8         dmac_15_0[0x10];
576 	u8         first_prio[0x3];
577 	u8         first_cfi[0x1];
578 	u8         first_vid[0xc];
579 
580 	u8         ip_protocol[0x8];
581 	u8         ip_dscp[0x6];
582 	u8         ip_ecn[0x2];
583 	u8         cvlan_tag[0x1];
584 	u8         svlan_tag[0x1];
585 	u8         frag[0x1];
586 	u8         ip_version[0x4];
587 	u8         tcp_flags[0x9];
588 
589 	u8         tcp_sport[0x10];
590 	u8         tcp_dport[0x10];
591 
592 	u8         l4_type[0x2];
593 	u8         l4_type_ext[0x4];
594 	u8         reserved_at_c6[0xa];
595 	u8         ipv4_ihl[0x4];
596 	u8         reserved_at_d4[0x4];
597 	u8         ttl_hoplimit[0x8];
598 
599 	u8         udp_sport[0x10];
600 	u8         udp_dport[0x10];
601 
602 	union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
603 
604 	union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
605 };
606 
607 struct mlx5_ifc_nvgre_key_bits {
608 	u8 hi[0x18];
609 	u8 lo[0x8];
610 };
611 
612 union mlx5_ifc_gre_key_bits {
613 	struct mlx5_ifc_nvgre_key_bits nvgre;
614 	u8 key[0x20];
615 };
616 
617 struct mlx5_ifc_fte_match_set_misc_bits {
618 	u8         gre_c_present[0x1];
619 	u8         reserved_at_1[0x1];
620 	u8         gre_k_present[0x1];
621 	u8         gre_s_present[0x1];
622 	u8         source_vhca_port[0x4];
623 	u8         source_sqn[0x18];
624 
625 	u8         source_eswitch_owner_vhca_id[0x10];
626 	u8         source_port[0x10];
627 
628 	u8         outer_second_prio[0x3];
629 	u8         outer_second_cfi[0x1];
630 	u8         outer_second_vid[0xc];
631 	u8         inner_second_prio[0x3];
632 	u8         inner_second_cfi[0x1];
633 	u8         inner_second_vid[0xc];
634 
635 	u8         outer_second_cvlan_tag[0x1];
636 	u8         inner_second_cvlan_tag[0x1];
637 	u8         outer_second_svlan_tag[0x1];
638 	u8         inner_second_svlan_tag[0x1];
639 	u8         reserved_at_64[0xc];
640 	u8         gre_protocol[0x10];
641 
642 	union mlx5_ifc_gre_key_bits gre_key;
643 
644 	u8         vxlan_vni[0x18];
645 	u8         bth_opcode[0x8];
646 
647 	u8         geneve_vni[0x18];
648 	u8         reserved_at_d8[0x6];
649 	u8         geneve_tlv_option_0_exist[0x1];
650 	u8         geneve_oam[0x1];
651 
652 	u8         reserved_at_e0[0xc];
653 	u8         outer_ipv6_flow_label[0x14];
654 
655 	u8         reserved_at_100[0xc];
656 	u8         inner_ipv6_flow_label[0x14];
657 
658 	u8         reserved_at_120[0xa];
659 	u8         geneve_opt_len[0x6];
660 	u8         geneve_protocol_type[0x10];
661 
662 	u8         reserved_at_140[0x8];
663 	u8         bth_dst_qp[0x18];
664 	u8	   inner_esp_spi[0x20];
665 	u8	   outer_esp_spi[0x20];
666 	u8         reserved_at_1a0[0x60];
667 };
668 
669 struct mlx5_ifc_fte_match_mpls_bits {
670 	u8         mpls_label[0x14];
671 	u8         mpls_exp[0x3];
672 	u8         mpls_s_bos[0x1];
673 	u8         mpls_ttl[0x8];
674 };
675 
676 struct mlx5_ifc_fte_match_set_misc2_bits {
677 	struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls;
678 
679 	struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls;
680 
681 	struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre;
682 
683 	struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp;
684 
685 	u8         metadata_reg_c_7[0x20];
686 
687 	u8         metadata_reg_c_6[0x20];
688 
689 	u8         metadata_reg_c_5[0x20];
690 
691 	u8         metadata_reg_c_4[0x20];
692 
693 	u8         metadata_reg_c_3[0x20];
694 
695 	u8         metadata_reg_c_2[0x20];
696 
697 	u8         metadata_reg_c_1[0x20];
698 
699 	u8         metadata_reg_c_0[0x20];
700 
701 	u8         metadata_reg_a[0x20];
702 
703 	u8         reserved_at_1a0[0x8];
704 	u8         macsec_syndrome[0x8];
705 	u8         ipsec_syndrome[0x8];
706 	u8         ipsec_next_header[0x8];
707 
708 	u8         reserved_at_1c0[0x40];
709 };
710 
711 struct mlx5_ifc_fte_match_set_misc3_bits {
712 	u8         inner_tcp_seq_num[0x20];
713 
714 	u8         outer_tcp_seq_num[0x20];
715 
716 	u8         inner_tcp_ack_num[0x20];
717 
718 	u8         outer_tcp_ack_num[0x20];
719 
720 	u8	   reserved_at_80[0x8];
721 	u8         outer_vxlan_gpe_vni[0x18];
722 
723 	u8         outer_vxlan_gpe_next_protocol[0x8];
724 	u8         outer_vxlan_gpe_flags[0x8];
725 	u8	   reserved_at_b0[0x10];
726 
727 	u8	   icmp_header_data[0x20];
728 
729 	u8	   icmpv6_header_data[0x20];
730 
731 	u8	   icmp_type[0x8];
732 	u8	   icmp_code[0x8];
733 	u8	   icmpv6_type[0x8];
734 	u8	   icmpv6_code[0x8];
735 
736 	u8         geneve_tlv_option_0_data[0x20];
737 
738 	u8	   gtpu_teid[0x20];
739 
740 	u8	   gtpu_msg_type[0x8];
741 	u8	   gtpu_msg_flags[0x8];
742 	u8	   reserved_at_170[0x10];
743 
744 	u8	   gtpu_dw_2[0x20];
745 
746 	u8	   gtpu_first_ext_dw_0[0x20];
747 
748 	u8	   gtpu_dw_0[0x20];
749 
750 	u8	   reserved_at_1e0[0x20];
751 };
752 
753 struct mlx5_ifc_fte_match_set_misc4_bits {
754 	u8         prog_sample_field_value_0[0x20];
755 
756 	u8         prog_sample_field_id_0[0x20];
757 
758 	u8         prog_sample_field_value_1[0x20];
759 
760 	u8         prog_sample_field_id_1[0x20];
761 
762 	u8         prog_sample_field_value_2[0x20];
763 
764 	u8         prog_sample_field_id_2[0x20];
765 
766 	u8         prog_sample_field_value_3[0x20];
767 
768 	u8         prog_sample_field_id_3[0x20];
769 
770 	u8         reserved_at_100[0x100];
771 };
772 
773 struct mlx5_ifc_fte_match_set_misc5_bits {
774 	u8         macsec_tag_0[0x20];
775 
776 	u8         macsec_tag_1[0x20];
777 
778 	u8         macsec_tag_2[0x20];
779 
780 	u8         macsec_tag_3[0x20];
781 
782 	u8         tunnel_header_0[0x20];
783 
784 	u8         tunnel_header_1[0x20];
785 
786 	u8         tunnel_header_2[0x20];
787 
788 	u8         tunnel_header_3[0x20];
789 
790 	u8         reserved_at_100[0x100];
791 };
792 
793 struct mlx5_ifc_cmd_pas_bits {
794 	u8         pa_h[0x20];
795 
796 	u8         pa_l[0x14];
797 	u8         reserved_at_34[0xc];
798 };
799 
800 struct mlx5_ifc_uint64_bits {
801 	u8         hi[0x20];
802 
803 	u8         lo[0x20];
804 };
805 
806 enum {
807 	MLX5_ADS_STAT_RATE_NO_LIMIT  = 0x0,
808 	MLX5_ADS_STAT_RATE_2_5GBPS   = 0x7,
809 	MLX5_ADS_STAT_RATE_10GBPS    = 0x8,
810 	MLX5_ADS_STAT_RATE_30GBPS    = 0x9,
811 	MLX5_ADS_STAT_RATE_5GBPS     = 0xa,
812 	MLX5_ADS_STAT_RATE_20GBPS    = 0xb,
813 	MLX5_ADS_STAT_RATE_40GBPS    = 0xc,
814 	MLX5_ADS_STAT_RATE_60GBPS    = 0xd,
815 	MLX5_ADS_STAT_RATE_80GBPS    = 0xe,
816 	MLX5_ADS_STAT_RATE_120GBPS   = 0xf,
817 };
818 
819 struct mlx5_ifc_ads_bits {
820 	u8         fl[0x1];
821 	u8         free_ar[0x1];
822 	u8         reserved_at_2[0xe];
823 	u8         pkey_index[0x10];
824 
825 	u8         plane_index[0x8];
826 	u8         grh[0x1];
827 	u8         mlid[0x7];
828 	u8         rlid[0x10];
829 
830 	u8         ack_timeout[0x5];
831 	u8         reserved_at_45[0x3];
832 	u8         src_addr_index[0x8];
833 	u8         reserved_at_50[0x4];
834 	u8         stat_rate[0x4];
835 	u8         hop_limit[0x8];
836 
837 	u8         reserved_at_60[0x4];
838 	u8         tclass[0x8];
839 	u8         flow_label[0x14];
840 
841 	u8         rgid_rip[16][0x8];
842 
843 	u8         reserved_at_100[0x4];
844 	u8         f_dscp[0x1];
845 	u8         f_ecn[0x1];
846 	u8         reserved_at_106[0x1];
847 	u8         f_eth_prio[0x1];
848 	u8         ecn[0x2];
849 	u8         dscp[0x6];
850 	u8         udp_sport[0x10];
851 
852 	u8         dei_cfi[0x1];
853 	u8         eth_prio[0x3];
854 	u8         sl[0x4];
855 	u8         vhca_port_num[0x8];
856 	u8         rmac_47_32[0x10];
857 
858 	u8         rmac_31_0[0x20];
859 };
860 
861 struct mlx5_ifc_flow_table_nic_cap_bits {
862 	u8         nic_rx_multi_path_tirs[0x1];
863 	u8         nic_rx_multi_path_tirs_fts[0x1];
864 	u8         allow_sniffer_and_nic_rx_shared_tir[0x1];
865 	u8	   reserved_at_3[0x4];
866 	u8	   sw_owner_reformat_supported[0x1];
867 	u8	   reserved_at_8[0x18];
868 
869 	u8	   encap_general_header[0x1];
870 	u8	   reserved_at_21[0xa];
871 	u8	   log_max_packet_reformat_context[0x5];
872 	u8	   reserved_at_30[0x6];
873 	u8	   max_encap_header_size[0xa];
874 	u8	   reserved_at_40[0x1c0];
875 
876 	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
877 
878 	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_rdma;
879 
880 	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
881 
882 	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
883 
884 	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_rdma;
885 
886 	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
887 
888 	u8         reserved_at_e00[0x600];
889 
890 	struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_receive;
891 
892 	u8         reserved_at_1480[0x80];
893 
894 	struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_receive_rdma;
895 
896 	u8         reserved_at_1580[0x280];
897 
898 	struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_transmit_rdma;
899 
900 	u8         reserved_at_1880[0x780];
901 
902 	u8         sw_steering_nic_rx_action_drop_icm_address[0x40];
903 
904 	u8         sw_steering_nic_tx_action_drop_icm_address[0x40];
905 
906 	u8         sw_steering_nic_tx_action_allow_icm_address[0x40];
907 
908 	u8         reserved_at_20c0[0x5f40];
909 };
910 
911 struct mlx5_ifc_port_selection_cap_bits {
912 	u8         reserved_at_0[0x10];
913 	u8         port_select_flow_table[0x1];
914 	u8         reserved_at_11[0x1];
915 	u8         port_select_flow_table_bypass[0x1];
916 	u8         reserved_at_13[0xd];
917 
918 	u8         reserved_at_20[0x1e0];
919 
920 	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_port_selection;
921 
922 	struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_port_selection;
923 
924 	u8         reserved_at_480[0x7b80];
925 };
926 
927 enum {
928 	MLX5_FDB_TO_VPORT_REG_C_0 = 0x01,
929 	MLX5_FDB_TO_VPORT_REG_C_1 = 0x02,
930 	MLX5_FDB_TO_VPORT_REG_C_2 = 0x04,
931 	MLX5_FDB_TO_VPORT_REG_C_3 = 0x08,
932 	MLX5_FDB_TO_VPORT_REG_C_4 = 0x10,
933 	MLX5_FDB_TO_VPORT_REG_C_5 = 0x20,
934 	MLX5_FDB_TO_VPORT_REG_C_6 = 0x40,
935 	MLX5_FDB_TO_VPORT_REG_C_7 = 0x80,
936 };
937 
938 struct mlx5_ifc_flow_table_eswitch_cap_bits {
939 	u8      fdb_to_vport_reg_c_id[0x8];
940 	u8      reserved_at_8[0x5];
941 	u8      fdb_uplink_hairpin[0x1];
942 	u8      fdb_multi_path_any_table_limit_regc[0x1];
943 	u8      reserved_at_f[0x1];
944 	u8      fdb_dynamic_tunnel[0x1];
945 	u8      reserved_at_11[0x1];
946 	u8      fdb_multi_path_any_table[0x1];
947 	u8      reserved_at_13[0x2];
948 	u8      fdb_modify_header_fwd_to_table[0x1];
949 	u8      fdb_ipv4_ttl_modify[0x1];
950 	u8      flow_source[0x1];
951 	u8      reserved_at_18[0x2];
952 	u8      multi_fdb_encap[0x1];
953 	u8      egress_acl_forward_to_vport[0x1];
954 	u8      fdb_multi_path_to_table[0x1];
955 	u8      reserved_at_1d[0x3];
956 
957 	u8      reserved_at_20[0x1e0];
958 
959 	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb;
960 
961 	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress;
962 
963 	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;
964 
965 	u8      reserved_at_800[0xC00];
966 
967 	struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_esw_fdb;
968 
969 	struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_bitmask_support_2_esw_fdb;
970 
971 	u8      reserved_at_1500[0x300];
972 
973 	u8      sw_steering_fdb_action_drop_icm_address_rx[0x40];
974 
975 	u8      sw_steering_fdb_action_drop_icm_address_tx[0x40];
976 
977 	u8      sw_steering_uplink_icm_address_rx[0x40];
978 
979 	u8      sw_steering_uplink_icm_address_tx[0x40];
980 
981 	u8      reserved_at_1900[0x6700];
982 };
983 
984 struct mlx5_ifc_wqe_based_flow_table_cap_bits {
985 	u8         reserved_at_0[0x3];
986 	u8         log_max_num_ste[0x5];
987 	u8         reserved_at_8[0x3];
988 	u8         log_max_num_stc[0x5];
989 	u8         reserved_at_10[0x3];
990 	u8         log_max_num_rtc[0x5];
991 	u8         reserved_at_18[0x3];
992 	u8         log_max_num_header_modify_pattern[0x5];
993 
994 	u8         rtc_hash_split_table[0x1];
995 	u8         rtc_linear_lookup_table[0x1];
996 	u8         reserved_at_22[0x1];
997 	u8         stc_alloc_log_granularity[0x5];
998 	u8         reserved_at_28[0x3];
999 	u8         stc_alloc_log_max[0x5];
1000 	u8         reserved_at_30[0x3];
1001 	u8         ste_alloc_log_granularity[0x5];
1002 	u8         reserved_at_38[0x3];
1003 	u8         ste_alloc_log_max[0x5];
1004 
1005 	u8         reserved_at_40[0xb];
1006 	u8         rtc_reparse_mode[0x5];
1007 	u8         reserved_at_50[0x3];
1008 	u8         rtc_index_mode[0x5];
1009 	u8         reserved_at_58[0x3];
1010 	u8         rtc_log_depth_max[0x5];
1011 
1012 	u8         reserved_at_60[0x10];
1013 	u8         ste_format[0x10];
1014 
1015 	u8         stc_action_type[0x80];
1016 
1017 	u8         header_insert_type[0x10];
1018 	u8         header_remove_type[0x10];
1019 
1020 	u8         trivial_match_definer[0x20];
1021 
1022 	u8         reserved_at_140[0x1b];
1023 	u8         rtc_max_num_hash_definer_gen_wqe[0x5];
1024 
1025 	u8         reserved_at_160[0x18];
1026 	u8         access_index_mode[0x8];
1027 
1028 	u8         reserved_at_180[0x10];
1029 	u8         ste_format_gen_wqe[0x10];
1030 
1031 	u8         linear_match_definer_reg_c3[0x20];
1032 
1033 	u8         fdb_jump_to_tir_stc[0x1];
1034 	u8         reserved_at_1c1[0x1f];
1035 };
1036 
1037 struct mlx5_ifc_esw_cap_bits {
1038 	u8         reserved_at_0[0x1d];
1039 	u8         merged_eswitch[0x1];
1040 	u8         reserved_at_1e[0x2];
1041 
1042 	u8         reserved_at_20[0x40];
1043 
1044 	u8         esw_manager_vport_number_valid[0x1];
1045 	u8         reserved_at_61[0xf];
1046 	u8         esw_manager_vport_number[0x10];
1047 
1048 	u8         reserved_at_80[0x780];
1049 };
1050 
1051 enum {
1052 	MLX5_COUNTER_SOURCE_ESWITCH = 0x0,
1053 	MLX5_COUNTER_FLOW_ESWITCH   = 0x1,
1054 };
1055 
1056 struct mlx5_ifc_e_switch_cap_bits {
1057 	u8         vport_svlan_strip[0x1];
1058 	u8         vport_cvlan_strip[0x1];
1059 	u8         vport_svlan_insert[0x1];
1060 	u8         vport_cvlan_insert_if_not_exist[0x1];
1061 	u8         vport_cvlan_insert_overwrite[0x1];
1062 	u8         reserved_at_5[0x1];
1063 	u8         vport_cvlan_insert_always[0x1];
1064 	u8         esw_shared_ingress_acl[0x1];
1065 	u8         esw_uplink_ingress_acl[0x1];
1066 	u8         root_ft_on_other_esw[0x1];
1067 	u8         reserved_at_a[0xf];
1068 	u8         esw_functions_changed[0x1];
1069 	u8         reserved_at_1a[0x1];
1070 	u8         ecpf_vport_exists[0x1];
1071 	u8         counter_eswitch_affinity[0x1];
1072 	u8         merged_eswitch[0x1];
1073 	u8         nic_vport_node_guid_modify[0x1];
1074 	u8         nic_vport_port_guid_modify[0x1];
1075 
1076 	u8         vxlan_encap_decap[0x1];
1077 	u8         nvgre_encap_decap[0x1];
1078 	u8         reserved_at_22[0x1];
1079 	u8         log_max_fdb_encap_uplink[0x5];
1080 	u8         reserved_at_21[0x3];
1081 	u8         log_max_packet_reformat_context[0x5];
1082 	u8         reserved_2b[0x6];
1083 	u8         max_encap_header_size[0xa];
1084 
1085 	u8         reserved_at_40[0xb];
1086 	u8         log_max_esw_sf[0x5];
1087 	u8         esw_sf_base_id[0x10];
1088 
1089 	u8         reserved_at_60[0x7a0];
1090 
1091 };
1092 
1093 struct mlx5_ifc_qos_cap_bits {
1094 	u8         packet_pacing[0x1];
1095 	u8         esw_scheduling[0x1];
1096 	u8         esw_bw_share[0x1];
1097 	u8         esw_rate_limit[0x1];
1098 	u8         reserved_at_4[0x1];
1099 	u8         packet_pacing_burst_bound[0x1];
1100 	u8         packet_pacing_typical_size[0x1];
1101 	u8         reserved_at_7[0x1];
1102 	u8         nic_sq_scheduling[0x1];
1103 	u8         nic_bw_share[0x1];
1104 	u8         nic_rate_limit[0x1];
1105 	u8         packet_pacing_uid[0x1];
1106 	u8         log_esw_max_sched_depth[0x4];
1107 	u8         reserved_at_10[0x10];
1108 
1109 	u8         reserved_at_20[0x9];
1110 	u8         esw_cross_esw_sched[0x1];
1111 	u8         reserved_at_2a[0x1];
1112 	u8         log_max_qos_nic_queue_group[0x5];
1113 	u8         reserved_at_30[0x10];
1114 
1115 	u8         packet_pacing_max_rate[0x20];
1116 
1117 	u8         packet_pacing_min_rate[0x20];
1118 
1119 	u8         reserved_at_80[0xb];
1120 	u8         log_esw_max_rate_limit[0x5];
1121 	u8         packet_pacing_rate_table_size[0x10];
1122 
1123 	u8         esw_element_type[0x10];
1124 	u8         esw_tsar_type[0x10];
1125 
1126 	u8         reserved_at_c0[0x10];
1127 	u8         max_qos_para_vport[0x10];
1128 
1129 	u8         max_tsar_bw_share[0x20];
1130 
1131 	u8         nic_element_type[0x10];
1132 	u8         nic_tsar_type[0x10];
1133 
1134 	u8         reserved_at_120[0x3];
1135 	u8         log_meter_aso_granularity[0x5];
1136 	u8         reserved_at_128[0x3];
1137 	u8         log_meter_aso_max_alloc[0x5];
1138 	u8         reserved_at_130[0x3];
1139 	u8         log_max_num_meter_aso[0x5];
1140 	u8         reserved_at_138[0x8];
1141 
1142 	u8         reserved_at_140[0x6c0];
1143 };
1144 
1145 struct mlx5_ifc_debug_cap_bits {
1146 	u8         core_dump_general[0x1];
1147 	u8         core_dump_qp[0x1];
1148 	u8         reserved_at_2[0x7];
1149 	u8         resource_dump[0x1];
1150 	u8         reserved_at_a[0x16];
1151 
1152 	u8         reserved_at_20[0x2];
1153 	u8         stall_detect[0x1];
1154 	u8         reserved_at_23[0x1d];
1155 
1156 	u8         reserved_at_40[0x7c0];
1157 };
1158 
1159 struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
1160 	u8         csum_cap[0x1];
1161 	u8         vlan_cap[0x1];
1162 	u8         lro_cap[0x1];
1163 	u8         lro_psh_flag[0x1];
1164 	u8         lro_time_stamp[0x1];
1165 	u8         reserved_at_5[0x2];
1166 	u8         wqe_vlan_insert[0x1];
1167 	u8         self_lb_en_modifiable[0x1];
1168 	u8         reserved_at_9[0x2];
1169 	u8         max_lso_cap[0x5];
1170 	u8         multi_pkt_send_wqe[0x2];
1171 	u8	   wqe_inline_mode[0x2];
1172 	u8         rss_ind_tbl_cap[0x4];
1173 	u8         reg_umr_sq[0x1];
1174 	u8         scatter_fcs[0x1];
1175 	u8         enhanced_multi_pkt_send_wqe[0x1];
1176 	u8         tunnel_lso_const_out_ip_id[0x1];
1177 	u8         tunnel_lro_gre[0x1];
1178 	u8         tunnel_lro_vxlan[0x1];
1179 	u8         tunnel_stateless_gre[0x1];
1180 	u8         tunnel_stateless_vxlan[0x1];
1181 
1182 	u8         swp[0x1];
1183 	u8         swp_csum[0x1];
1184 	u8         swp_lso[0x1];
1185 	u8         cqe_checksum_full[0x1];
1186 	u8         tunnel_stateless_geneve_tx[0x1];
1187 	u8         tunnel_stateless_mpls_over_udp[0x1];
1188 	u8         tunnel_stateless_mpls_over_gre[0x1];
1189 	u8         tunnel_stateless_vxlan_gpe[0x1];
1190 	u8         tunnel_stateless_ipv4_over_vxlan[0x1];
1191 	u8         tunnel_stateless_ip_over_ip[0x1];
1192 	u8         insert_trailer[0x1];
1193 	u8         reserved_at_2b[0x1];
1194 	u8         tunnel_stateless_ip_over_ip_rx[0x1];
1195 	u8         tunnel_stateless_ip_over_ip_tx[0x1];
1196 	u8         reserved_at_2e[0x2];
1197 	u8         max_vxlan_udp_ports[0x8];
1198 	u8         swp_csum_l4_partial[0x1];
1199 	u8         reserved_at_39[0x5];
1200 	u8         max_geneve_opt_len[0x1];
1201 	u8         tunnel_stateless_geneve_rx[0x1];
1202 
1203 	u8         reserved_at_40[0x10];
1204 	u8         lro_min_mss_size[0x10];
1205 
1206 	u8         reserved_at_60[0x120];
1207 
1208 	u8         lro_timer_supported_periods[4][0x20];
1209 
1210 	u8         reserved_at_200[0x600];
1211 };
1212 
1213 enum {
1214 	MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING               = 0x0,
1215 	MLX5_TIMESTAMP_FORMAT_CAP_REAL_TIME                  = 0x1,
1216 	MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME = 0x2,
1217 };
1218 
1219 struct mlx5_ifc_roce_cap_bits {
1220 	u8         roce_apm[0x1];
1221 	u8         reserved_at_1[0x3];
1222 	u8         sw_r_roce_src_udp_port[0x1];
1223 	u8         fl_rc_qp_when_roce_disabled[0x1];
1224 	u8         fl_rc_qp_when_roce_enabled[0x1];
1225 	u8         roce_cc_general[0x1];
1226 	u8	   qp_ooo_transmit_default[0x1];
1227 	u8         reserved_at_9[0x15];
1228 	u8	   qp_ts_format[0x2];
1229 
1230 	u8         reserved_at_20[0x60];
1231 
1232 	u8         reserved_at_80[0xc];
1233 	u8         l3_type[0x4];
1234 	u8         reserved_at_90[0x8];
1235 	u8         roce_version[0x8];
1236 
1237 	u8         reserved_at_a0[0x10];
1238 	u8         r_roce_dest_udp_port[0x10];
1239 
1240 	u8         r_roce_max_src_udp_port[0x10];
1241 	u8         r_roce_min_src_udp_port[0x10];
1242 
1243 	u8         reserved_at_e0[0x10];
1244 	u8         roce_address_table_size[0x10];
1245 
1246 	u8         reserved_at_100[0x700];
1247 };
1248 
1249 struct mlx5_ifc_sync_steering_in_bits {
1250 	u8         opcode[0x10];
1251 	u8         uid[0x10];
1252 
1253 	u8         reserved_at_20[0x10];
1254 	u8         op_mod[0x10];
1255 
1256 	u8         reserved_at_40[0xc0];
1257 };
1258 
1259 struct mlx5_ifc_sync_steering_out_bits {
1260 	u8         status[0x8];
1261 	u8         reserved_at_8[0x18];
1262 
1263 	u8         syndrome[0x20];
1264 
1265 	u8         reserved_at_40[0x40];
1266 };
1267 
1268 struct mlx5_ifc_sync_crypto_in_bits {
1269 	u8         opcode[0x10];
1270 	u8         uid[0x10];
1271 
1272 	u8         reserved_at_20[0x10];
1273 	u8         op_mod[0x10];
1274 
1275 	u8         reserved_at_40[0x20];
1276 
1277 	u8         reserved_at_60[0x10];
1278 	u8         crypto_type[0x10];
1279 
1280 	u8         reserved_at_80[0x80];
1281 };
1282 
1283 struct mlx5_ifc_sync_crypto_out_bits {
1284 	u8         status[0x8];
1285 	u8         reserved_at_8[0x18];
1286 
1287 	u8         syndrome[0x20];
1288 
1289 	u8         reserved_at_40[0x40];
1290 };
1291 
1292 struct mlx5_ifc_device_mem_cap_bits {
1293 	u8         memic[0x1];
1294 	u8         reserved_at_1[0x1f];
1295 
1296 	u8         reserved_at_20[0xb];
1297 	u8         log_min_memic_alloc_size[0x5];
1298 	u8         reserved_at_30[0x8];
1299 	u8	   log_max_memic_addr_alignment[0x8];
1300 
1301 	u8         memic_bar_start_addr[0x40];
1302 
1303 	u8         memic_bar_size[0x20];
1304 
1305 	u8         max_memic_size[0x20];
1306 
1307 	u8         steering_sw_icm_start_address[0x40];
1308 
1309 	u8         reserved_at_100[0x8];
1310 	u8         log_header_modify_sw_icm_size[0x8];
1311 	u8         reserved_at_110[0x2];
1312 	u8         log_sw_icm_alloc_granularity[0x6];
1313 	u8         log_steering_sw_icm_size[0x8];
1314 
1315 	u8         log_indirect_encap_sw_icm_size[0x8];
1316 	u8         reserved_at_128[0x10];
1317 	u8         log_header_modify_pattern_sw_icm_size[0x8];
1318 
1319 	u8         header_modify_sw_icm_start_address[0x40];
1320 
1321 	u8         reserved_at_180[0x40];
1322 
1323 	u8         header_modify_pattern_sw_icm_start_address[0x40];
1324 
1325 	u8         memic_operations[0x20];
1326 
1327 	u8         reserved_at_220[0x20];
1328 
1329 	u8         indirect_encap_sw_icm_start_address[0x40];
1330 
1331 	u8         reserved_at_280[0x580];
1332 };
1333 
1334 struct mlx5_ifc_device_event_cap_bits {
1335 	u8         user_affiliated_events[4][0x40];
1336 
1337 	u8         user_unaffiliated_events[4][0x40];
1338 };
1339 
1340 struct mlx5_ifc_virtio_emulation_cap_bits {
1341 	u8         desc_tunnel_offload_type[0x1];
1342 	u8         eth_frame_offload_type[0x1];
1343 	u8         virtio_version_1_0[0x1];
1344 	u8         device_features_bits_mask[0xd];
1345 	u8         event_mode[0x8];
1346 	u8         virtio_queue_type[0x8];
1347 
1348 	u8         max_tunnel_desc[0x10];
1349 	u8         reserved_at_30[0x3];
1350 	u8         log_doorbell_stride[0x5];
1351 	u8         reserved_at_38[0x3];
1352 	u8         log_doorbell_bar_size[0x5];
1353 
1354 	u8         doorbell_bar_offset[0x40];
1355 
1356 	u8         max_emulated_devices[0x8];
1357 	u8         max_num_virtio_queues[0x18];
1358 
1359 	u8         reserved_at_a0[0x20];
1360 
1361 	u8	   reserved_at_c0[0x13];
1362 	u8         desc_group_mkey_supported[0x1];
1363 	u8         freeze_to_rdy_supported[0x1];
1364 	u8         reserved_at_d5[0xb];
1365 
1366 	u8         reserved_at_e0[0x20];
1367 
1368 	u8         umem_1_buffer_param_a[0x20];
1369 
1370 	u8         umem_1_buffer_param_b[0x20];
1371 
1372 	u8         umem_2_buffer_param_a[0x20];
1373 
1374 	u8         umem_2_buffer_param_b[0x20];
1375 
1376 	u8         umem_3_buffer_param_a[0x20];
1377 
1378 	u8         umem_3_buffer_param_b[0x20];
1379 
1380 	u8         reserved_at_1c0[0x640];
1381 };
1382 
1383 enum {
1384 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE     = 0x0,
1385 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES    = 0x2,
1386 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES    = 0x4,
1387 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES    = 0x8,
1388 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES   = 0x10,
1389 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES   = 0x20,
1390 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES   = 0x40,
1391 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES  = 0x80,
1392 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES  = 0x100,
1393 };
1394 
1395 enum {
1396 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE     = 0x1,
1397 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES    = 0x2,
1398 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES    = 0x4,
1399 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES    = 0x8,
1400 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES   = 0x10,
1401 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES   = 0x20,
1402 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES   = 0x40,
1403 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES  = 0x80,
1404 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES  = 0x100,
1405 };
1406 
1407 struct mlx5_ifc_atomic_caps_bits {
1408 	u8         reserved_at_0[0x40];
1409 
1410 	u8         atomic_req_8B_endianness_mode[0x2];
1411 	u8         reserved_at_42[0x4];
1412 	u8         supported_atomic_req_8B_endianness_mode_1[0x1];
1413 
1414 	u8         reserved_at_47[0x19];
1415 
1416 	u8         reserved_at_60[0x20];
1417 
1418 	u8         reserved_at_80[0x10];
1419 	u8         atomic_operations[0x10];
1420 
1421 	u8         reserved_at_a0[0x10];
1422 	u8         atomic_size_qp[0x10];
1423 
1424 	u8         reserved_at_c0[0x10];
1425 	u8         atomic_size_dc[0x10];
1426 
1427 	u8         reserved_at_e0[0x720];
1428 };
1429 
1430 struct mlx5_ifc_odp_scheme_cap_bits {
1431 	u8         reserved_at_0[0x40];
1432 
1433 	u8         sig[0x1];
1434 	u8         reserved_at_41[0x4];
1435 	u8         page_prefetch[0x1];
1436 	u8         reserved_at_46[0x1a];
1437 
1438 	u8         reserved_at_60[0x20];
1439 
1440 	struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
1441 
1442 	struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
1443 
1444 	struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
1445 
1446 	struct mlx5_ifc_odp_per_transport_service_cap_bits xrc_odp_caps;
1447 
1448 	struct mlx5_ifc_odp_per_transport_service_cap_bits dc_odp_caps;
1449 
1450 	u8         reserved_at_120[0xe0];
1451 };
1452 
1453 struct mlx5_ifc_odp_cap_bits {
1454 	struct mlx5_ifc_odp_scheme_cap_bits transport_page_fault_scheme_cap;
1455 
1456 	struct mlx5_ifc_odp_scheme_cap_bits memory_page_fault_scheme_cap;
1457 
1458 	u8         reserved_at_400[0x200];
1459 
1460 	u8         mem_page_fault[0x1];
1461 	u8         reserved_at_601[0x1f];
1462 
1463 	u8         reserved_at_620[0x1e0];
1464 };
1465 
1466 struct mlx5_ifc_tls_cap_bits {
1467 	u8         tls_1_2_aes_gcm_128[0x1];
1468 	u8         tls_1_3_aes_gcm_128[0x1];
1469 	u8         tls_1_2_aes_gcm_256[0x1];
1470 	u8         tls_1_3_aes_gcm_256[0x1];
1471 	u8         reserved_at_4[0x1c];
1472 
1473 	u8         reserved_at_20[0x7e0];
1474 };
1475 
1476 struct mlx5_ifc_ipsec_cap_bits {
1477 	u8         ipsec_full_offload[0x1];
1478 	u8         ipsec_crypto_offload[0x1];
1479 	u8         ipsec_esn[0x1];
1480 	u8         ipsec_crypto_esp_aes_gcm_256_encrypt[0x1];
1481 	u8         ipsec_crypto_esp_aes_gcm_128_encrypt[0x1];
1482 	u8         ipsec_crypto_esp_aes_gcm_256_decrypt[0x1];
1483 	u8         ipsec_crypto_esp_aes_gcm_128_decrypt[0x1];
1484 	u8         reserved_at_7[0x4];
1485 	u8         log_max_ipsec_offload[0x5];
1486 	u8         reserved_at_10[0x10];
1487 
1488 	u8         min_log_ipsec_full_replay_window[0x8];
1489 	u8         max_log_ipsec_full_replay_window[0x8];
1490 	u8         reserved_at_30[0x7d0];
1491 };
1492 
1493 struct mlx5_ifc_macsec_cap_bits {
1494 	u8    macsec_epn[0x1];
1495 	u8    reserved_at_1[0x2];
1496 	u8    macsec_crypto_esp_aes_gcm_256_encrypt[0x1];
1497 	u8    macsec_crypto_esp_aes_gcm_128_encrypt[0x1];
1498 	u8    macsec_crypto_esp_aes_gcm_256_decrypt[0x1];
1499 	u8    macsec_crypto_esp_aes_gcm_128_decrypt[0x1];
1500 	u8    reserved_at_7[0x4];
1501 	u8    log_max_macsec_offload[0x5];
1502 	u8    reserved_at_10[0x10];
1503 
1504 	u8    min_log_macsec_full_replay_window[0x8];
1505 	u8    max_log_macsec_full_replay_window[0x8];
1506 	u8    reserved_at_30[0x10];
1507 
1508 	u8    reserved_at_40[0x7c0];
1509 };
1510 
1511 enum {
1512 	MLX5_WQ_TYPE_LINKED_LIST  = 0x0,
1513 	MLX5_WQ_TYPE_CYCLIC       = 0x1,
1514 	MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2,
1515 	MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3,
1516 };
1517 
1518 enum {
1519 	MLX5_WQ_END_PAD_MODE_NONE   = 0x0,
1520 	MLX5_WQ_END_PAD_MODE_ALIGN  = 0x1,
1521 };
1522 
1523 enum {
1524 	MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES    = 0x0,
1525 	MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES   = 0x1,
1526 	MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES   = 0x2,
1527 	MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES   = 0x3,
1528 	MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES  = 0x4,
1529 };
1530 
1531 enum {
1532 	MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES  = 0x0,
1533 	MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES  = 0x1,
1534 	MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES  = 0x2,
1535 	MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES   = 0x3,
1536 	MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES   = 0x4,
1537 	MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES   = 0x5,
1538 };
1539 
1540 enum {
1541 	MLX5_CMD_HCA_CAP_PORT_TYPE_IB        = 0x0,
1542 	MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET  = 0x1,
1543 };
1544 
1545 enum {
1546 	MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED       = 0x0,
1547 	MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE  = 0x1,
1548 	MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED        = 0x3,
1549 };
1550 
1551 enum {
1552 	MLX5_CAP_PORT_TYPE_IB  = 0x0,
1553 	MLX5_CAP_PORT_TYPE_ETH = 0x1,
1554 };
1555 
1556 enum {
1557 	MLX5_CAP_UMR_FENCE_STRONG	= 0x0,
1558 	MLX5_CAP_UMR_FENCE_SMALL	= 0x1,
1559 	MLX5_CAP_UMR_FENCE_NONE		= 0x2,
1560 };
1561 
1562 enum {
1563 	MLX5_FLEX_IPV4_OVER_VXLAN_ENABLED	= 1 << 0,
1564 	MLX5_FLEX_IPV6_OVER_VXLAN_ENABLED	= 1 << 1,
1565 	MLX5_FLEX_IPV6_OVER_IP_ENABLED		= 1 << 2,
1566 	MLX5_FLEX_PARSER_GENEVE_ENABLED		= 1 << 3,
1567 	MLX5_FLEX_PARSER_MPLS_OVER_GRE_ENABLED	= 1 << 4,
1568 	MLX5_FLEX_PARSER_MPLS_OVER_UDP_ENABLED	= 1 << 5,
1569 	MLX5_FLEX_P_BIT_VXLAN_GPE_ENABLED	= 1 << 6,
1570 	MLX5_FLEX_PARSER_VXLAN_GPE_ENABLED	= 1 << 7,
1571 	MLX5_FLEX_PARSER_ICMP_V4_ENABLED	= 1 << 8,
1572 	MLX5_FLEX_PARSER_ICMP_V6_ENABLED	= 1 << 9,
1573 	MLX5_FLEX_PARSER_GENEVE_TLV_OPTION_0_ENABLED = 1 << 10,
1574 	MLX5_FLEX_PARSER_GTPU_ENABLED		= 1 << 11,
1575 	MLX5_FLEX_PARSER_GTPU_DW_2_ENABLED	= 1 << 16,
1576 	MLX5_FLEX_PARSER_GTPU_FIRST_EXT_DW_0_ENABLED = 1 << 17,
1577 	MLX5_FLEX_PARSER_GTPU_DW_0_ENABLED	= 1 << 18,
1578 	MLX5_FLEX_PARSER_GTPU_TEID_ENABLED	= 1 << 19,
1579 };
1580 
1581 enum {
1582 	MLX5_UCTX_CAP_RAW_TX = 1UL << 0,
1583 	MLX5_UCTX_CAP_INTERNAL_DEV_RES = 1UL << 1,
1584 	MLX5_UCTX_CAP_RDMA_CTRL = 1UL << 3,
1585 	MLX5_UCTX_CAP_RDMA_CTRL_OTHER_VHCA = 1UL << 4,
1586 };
1587 
1588 #define MLX5_FC_BULK_SIZE_FACTOR 128
1589 
1590 enum mlx5_fc_bulk_alloc_bitmask {
1591 	MLX5_FC_BULK_128   = (1 << 0),
1592 	MLX5_FC_BULK_256   = (1 << 1),
1593 	MLX5_FC_BULK_512   = (1 << 2),
1594 	MLX5_FC_BULK_1024  = (1 << 3),
1595 	MLX5_FC_BULK_2048  = (1 << 4),
1596 	MLX5_FC_BULK_4096  = (1 << 5),
1597 	MLX5_FC_BULK_8192  = (1 << 6),
1598 	MLX5_FC_BULK_16384 = (1 << 7),
1599 };
1600 
1601 #define MLX5_FC_BULK_NUM_FCS(fc_enum) (MLX5_FC_BULK_SIZE_FACTOR * (fc_enum))
1602 
1603 #define MLX5_FT_MAX_MULTIPATH_LEVEL 63
1604 
1605 enum {
1606 	MLX5_STEERING_FORMAT_CONNECTX_5   = 0,
1607 	MLX5_STEERING_FORMAT_CONNECTX_6DX = 1,
1608 	MLX5_STEERING_FORMAT_CONNECTX_7   = 2,
1609 	MLX5_STEERING_FORMAT_CONNECTX_8   = 3,
1610 };
1611 
1612 struct mlx5_ifc_cmd_hca_cap_bits {
1613 	u8         reserved_at_0[0x6];
1614 	u8         page_request_disable[0x1];
1615 	u8         abs_native_port_num[0x1];
1616 	u8         reserved_at_8[0x8];
1617 	u8         shared_object_to_user_object_allowed[0x1];
1618 	u8         reserved_at_13[0xe];
1619 	u8         vhca_resource_manager[0x1];
1620 
1621 	u8         hca_cap_2[0x1];
1622 	u8         create_lag_when_not_master_up[0x1];
1623 	u8         dtor[0x1];
1624 	u8         event_on_vhca_state_teardown_request[0x1];
1625 	u8         event_on_vhca_state_in_use[0x1];
1626 	u8         event_on_vhca_state_active[0x1];
1627 	u8         event_on_vhca_state_allocated[0x1];
1628 	u8         event_on_vhca_state_invalid[0x1];
1629 	u8         reserved_at_28[0x8];
1630 	u8         vhca_id[0x10];
1631 
1632 	u8         reserved_at_40[0x40];
1633 
1634 	u8         log_max_srq_sz[0x8];
1635 	u8         log_max_qp_sz[0x8];
1636 	u8         event_cap[0x1];
1637 	u8         reserved_at_91[0x2];
1638 	u8         isolate_vl_tc_new[0x1];
1639 	u8         reserved_at_94[0x4];
1640 	u8         prio_tag_required[0x1];
1641 	u8         reserved_at_99[0x2];
1642 	u8         log_max_qp[0x5];
1643 
1644 	u8         reserved_at_a0[0x3];
1645 	u8	   ece_support[0x1];
1646 	u8	   reserved_at_a4[0x5];
1647 	u8         reg_c_preserve[0x1];
1648 	u8         reserved_at_aa[0x1];
1649 	u8         log_max_srq[0x5];
1650 	u8         reserved_at_b0[0x1];
1651 	u8         uplink_follow[0x1];
1652 	u8         ts_cqe_to_dest_cqn[0x1];
1653 	u8         reserved_at_b3[0x6];
1654 	u8         go_back_n[0x1];
1655 	u8         reserved_at_ba[0x6];
1656 
1657 	u8         max_sgl_for_optimized_performance[0x8];
1658 	u8         log_max_cq_sz[0x8];
1659 	u8         relaxed_ordering_write_umr[0x1];
1660 	u8         relaxed_ordering_read_umr[0x1];
1661 	u8         reserved_at_d2[0x7];
1662 	u8         virtio_net_device_emualtion_manager[0x1];
1663 	u8         virtio_blk_device_emualtion_manager[0x1];
1664 	u8         log_max_cq[0x5];
1665 
1666 	u8         log_max_eq_sz[0x8];
1667 	u8         relaxed_ordering_write[0x1];
1668 	u8         relaxed_ordering_read_pci_enabled[0x1];
1669 	u8         log_max_mkey[0x6];
1670 	u8         reserved_at_f0[0x6];
1671 	u8	   terminate_scatter_list_mkey[0x1];
1672 	u8	   repeated_mkey[0x1];
1673 	u8         dump_fill_mkey[0x1];
1674 	u8         reserved_at_f9[0x2];
1675 	u8         fast_teardown[0x1];
1676 	u8         log_max_eq[0x4];
1677 
1678 	u8         max_indirection[0x8];
1679 	u8         fixed_buffer_size[0x1];
1680 	u8         log_max_mrw_sz[0x7];
1681 	u8         force_teardown[0x1];
1682 	u8         reserved_at_111[0x1];
1683 	u8         log_max_bsf_list_size[0x6];
1684 	u8         umr_extended_translation_offset[0x1];
1685 	u8         null_mkey[0x1];
1686 	u8         log_max_klm_list_size[0x6];
1687 
1688 	u8         reserved_at_120[0x2];
1689 	u8	   qpc_extension[0x1];
1690 	u8	   reserved_at_123[0x7];
1691 	u8         log_max_ra_req_dc[0x6];
1692 	u8         reserved_at_130[0x2];
1693 	u8         eth_wqe_too_small[0x1];
1694 	u8         reserved_at_133[0x6];
1695 	u8         vnic_env_cq_overrun[0x1];
1696 	u8         log_max_ra_res_dc[0x6];
1697 
1698 	u8         reserved_at_140[0x5];
1699 	u8         release_all_pages[0x1];
1700 	u8         must_not_use[0x1];
1701 	u8         reserved_at_147[0x2];
1702 	u8         roce_accl[0x1];
1703 	u8         log_max_ra_req_qp[0x6];
1704 	u8         reserved_at_150[0xa];
1705 	u8         log_max_ra_res_qp[0x6];
1706 
1707 	u8         end_pad[0x1];
1708 	u8         cc_query_allowed[0x1];
1709 	u8         cc_modify_allowed[0x1];
1710 	u8         start_pad[0x1];
1711 	u8         cache_line_128byte[0x1];
1712 	u8         reserved_at_165[0x4];
1713 	u8         rts2rts_qp_counters_set_id[0x1];
1714 	u8         reserved_at_16a[0x2];
1715 	u8         vnic_env_int_rq_oob[0x1];
1716 	u8         sbcam_reg[0x1];
1717 	u8         reserved_at_16e[0x1];
1718 	u8         qcam_reg[0x1];
1719 	u8         gid_table_size[0x10];
1720 
1721 	u8         out_of_seq_cnt[0x1];
1722 	u8         vport_counters[0x1];
1723 	u8         retransmission_q_counters[0x1];
1724 	u8         debug[0x1];
1725 	u8         modify_rq_counter_set_id[0x1];
1726 	u8         rq_delay_drop[0x1];
1727 	u8         max_qp_cnt[0xa];
1728 	u8         pkey_table_size[0x10];
1729 
1730 	u8         vport_group_manager[0x1];
1731 	u8         vhca_group_manager[0x1];
1732 	u8         ib_virt[0x1];
1733 	u8         eth_virt[0x1];
1734 	u8         vnic_env_queue_counters[0x1];
1735 	u8         ets[0x1];
1736 	u8         nic_flow_table[0x1];
1737 	u8         eswitch_manager[0x1];
1738 	u8         device_memory[0x1];
1739 	u8         mcam_reg[0x1];
1740 	u8         pcam_reg[0x1];
1741 	u8         local_ca_ack_delay[0x5];
1742 	u8         port_module_event[0x1];
1743 	u8         enhanced_error_q_counters[0x1];
1744 	u8         ports_check[0x1];
1745 	u8         reserved_at_1b3[0x1];
1746 	u8         disable_link_up[0x1];
1747 	u8         beacon_led[0x1];
1748 	u8         port_type[0x2];
1749 	u8         num_ports[0x8];
1750 
1751 	u8         reserved_at_1c0[0x1];
1752 	u8         pps[0x1];
1753 	u8         pps_modify[0x1];
1754 	u8         log_max_msg[0x5];
1755 	u8         reserved_at_1c8[0x4];
1756 	u8         max_tc[0x4];
1757 	u8         temp_warn_event[0x1];
1758 	u8         dcbx[0x1];
1759 	u8         general_notification_event[0x1];
1760 	u8         reserved_at_1d3[0x2];
1761 	u8         fpga[0x1];
1762 	u8         rol_s[0x1];
1763 	u8         rol_g[0x1];
1764 	u8         reserved_at_1d8[0x1];
1765 	u8         wol_s[0x1];
1766 	u8         wol_g[0x1];
1767 	u8         wol_a[0x1];
1768 	u8         wol_b[0x1];
1769 	u8         wol_m[0x1];
1770 	u8         wol_u[0x1];
1771 	u8         wol_p[0x1];
1772 
1773 	u8         stat_rate_support[0x10];
1774 	u8         reserved_at_1f0[0x1];
1775 	u8         pci_sync_for_fw_update_event[0x1];
1776 	u8         reserved_at_1f2[0x6];
1777 	u8         init2_lag_tx_port_affinity[0x1];
1778 	u8         reserved_at_1fa[0x2];
1779 	u8         wqe_based_flow_table_update_cap[0x1];
1780 	u8         cqe_version[0x4];
1781 
1782 	u8         compact_address_vector[0x1];
1783 	u8         striding_rq[0x1];
1784 	u8         reserved_at_202[0x1];
1785 	u8         ipoib_enhanced_offloads[0x1];
1786 	u8         ipoib_basic_offloads[0x1];
1787 	u8         reserved_at_205[0x1];
1788 	u8         repeated_block_disabled[0x1];
1789 	u8         umr_modify_entity_size_disabled[0x1];
1790 	u8         umr_modify_atomic_disabled[0x1];
1791 	u8         umr_indirect_mkey_disabled[0x1];
1792 	u8         umr_fence[0x2];
1793 	u8         dc_req_scat_data_cqe[0x1];
1794 	u8         reserved_at_20d[0x2];
1795 	u8         drain_sigerr[0x1];
1796 	u8         cmdif_checksum[0x2];
1797 	u8         sigerr_cqe[0x1];
1798 	u8         reserved_at_213[0x1];
1799 	u8         wq_signature[0x1];
1800 	u8         sctr_data_cqe[0x1];
1801 	u8         reserved_at_216[0x1];
1802 	u8         sho[0x1];
1803 	u8         tph[0x1];
1804 	u8         rf[0x1];
1805 	u8         dct[0x1];
1806 	u8         qos[0x1];
1807 	u8         eth_net_offloads[0x1];
1808 	u8         roce[0x1];
1809 	u8         atomic[0x1];
1810 	u8         reserved_at_21f[0x1];
1811 
1812 	u8         cq_oi[0x1];
1813 	u8         cq_resize[0x1];
1814 	u8         cq_moderation[0x1];
1815 	u8         cq_period_mode_modify[0x1];
1816 	u8         reserved_at_224[0x2];
1817 	u8         cq_eq_remap[0x1];
1818 	u8         pg[0x1];
1819 	u8         block_lb_mc[0x1];
1820 	u8         reserved_at_229[0x1];
1821 	u8         scqe_break_moderation[0x1];
1822 	u8         cq_period_start_from_cqe[0x1];
1823 	u8         cd[0x1];
1824 	u8         reserved_at_22d[0x1];
1825 	u8         apm[0x1];
1826 	u8         vector_calc[0x1];
1827 	u8         umr_ptr_rlky[0x1];
1828 	u8	   imaicl[0x1];
1829 	u8	   qp_packet_based[0x1];
1830 	u8         reserved_at_233[0x3];
1831 	u8         qkv[0x1];
1832 	u8         pkv[0x1];
1833 	u8         set_deth_sqpn[0x1];
1834 	u8         reserved_at_239[0x3];
1835 	u8         xrc[0x1];
1836 	u8         ud[0x1];
1837 	u8         uc[0x1];
1838 	u8         rc[0x1];
1839 
1840 	u8         uar_4k[0x1];
1841 	u8         reserved_at_241[0x7];
1842 	u8         fl_rc_qp_when_roce_disabled[0x1];
1843 	u8         regexp_params[0x1];
1844 	u8         uar_sz[0x6];
1845 	u8         port_selection_cap[0x1];
1846 	u8         nic_cap_reg[0x1];
1847 	u8         umem_uid_0[0x1];
1848 	u8         reserved_at_253[0x5];
1849 	u8         log_pg_sz[0x8];
1850 
1851 	u8         bf[0x1];
1852 	u8         driver_version[0x1];
1853 	u8         pad_tx_eth_packet[0x1];
1854 	u8         reserved_at_263[0x3];
1855 	u8         mkey_by_name[0x1];
1856 	u8         reserved_at_267[0x4];
1857 
1858 	u8         log_bf_reg_size[0x5];
1859 
1860 	u8         disciplined_fr_counter[0x1];
1861 	u8         reserved_at_271[0x2];
1862 	u8	   qp_error_syndrome[0x1];
1863 	u8	   reserved_at_274[0x2];
1864 	u8         lag_dct[0x2];
1865 	u8         lag_tx_port_affinity[0x1];
1866 	u8         lag_native_fdb_selection[0x1];
1867 	u8         reserved_at_27a[0x1];
1868 	u8         lag_master[0x1];
1869 	u8         num_lag_ports[0x4];
1870 
1871 	u8         reserved_at_280[0x10];
1872 	u8         max_wqe_sz_sq[0x10];
1873 
1874 	u8         reserved_at_2a0[0xb];
1875 	u8         shampo[0x1];
1876 	u8         reserved_at_2ac[0x4];
1877 	u8         max_wqe_sz_rq[0x10];
1878 
1879 	u8         max_flow_counter_31_16[0x10];
1880 	u8         max_wqe_sz_sq_dc[0x10];
1881 
1882 	u8         reserved_at_2e0[0x7];
1883 	u8         max_qp_mcg[0x19];
1884 
1885 	u8         reserved_at_300[0x10];
1886 	u8         flow_counter_bulk_alloc[0x8];
1887 	u8         log_max_mcg[0x8];
1888 
1889 	u8         reserved_at_320[0x3];
1890 	u8         log_max_transport_domain[0x5];
1891 	u8         reserved_at_328[0x2];
1892 	u8	   relaxed_ordering_read[0x1];
1893 	u8         log_max_pd[0x5];
1894 	u8         dp_ordering_ooo_all_ud[0x1];
1895 	u8         dp_ordering_ooo_all_uc[0x1];
1896 	u8         dp_ordering_ooo_all_xrc[0x1];
1897 	u8         dp_ordering_ooo_all_dc[0x1];
1898 	u8         dp_ordering_ooo_all_rc[0x1];
1899 	u8         pcie_reset_using_hotreset_method[0x1];
1900 	u8         pci_sync_for_fw_update_with_driver_unload[0x1];
1901 	u8         vnic_env_cnt_steering_fail[0x1];
1902 	u8         vport_counter_local_loopback[0x1];
1903 	u8         q_counter_aggregation[0x1];
1904 	u8         q_counter_other_vport[0x1];
1905 	u8         log_max_xrcd[0x5];
1906 
1907 	u8         nic_receive_steering_discard[0x1];
1908 	u8         receive_discard_vport_down[0x1];
1909 	u8         transmit_discard_vport_down[0x1];
1910 	u8         eq_overrun_count[0x1];
1911 	u8         reserved_at_344[0x1];
1912 	u8         invalid_command_count[0x1];
1913 	u8         quota_exceeded_count[0x1];
1914 	u8         reserved_at_347[0x1];
1915 	u8         log_max_flow_counter_bulk[0x8];
1916 	u8         max_flow_counter_15_0[0x10];
1917 
1918 
1919 	u8         reserved_at_360[0x3];
1920 	u8         log_max_rq[0x5];
1921 	u8         reserved_at_368[0x3];
1922 	u8         log_max_sq[0x5];
1923 	u8         reserved_at_370[0x3];
1924 	u8         log_max_tir[0x5];
1925 	u8         reserved_at_378[0x3];
1926 	u8         log_max_tis[0x5];
1927 
1928 	u8         basic_cyclic_rcv_wqe[0x1];
1929 	u8         reserved_at_381[0x2];
1930 	u8         log_max_rmp[0x5];
1931 	u8         reserved_at_388[0x3];
1932 	u8         log_max_rqt[0x5];
1933 	u8         reserved_at_390[0x3];
1934 	u8         log_max_rqt_size[0x5];
1935 	u8         reserved_at_398[0x3];
1936 	u8         log_max_tis_per_sq[0x5];
1937 
1938 	u8         ext_stride_num_range[0x1];
1939 	u8         roce_rw_supported[0x1];
1940 	u8         log_max_current_uc_list_wr_supported[0x1];
1941 	u8         log_max_stride_sz_rq[0x5];
1942 	u8         reserved_at_3a8[0x3];
1943 	u8         log_min_stride_sz_rq[0x5];
1944 	u8         reserved_at_3b0[0x3];
1945 	u8         log_max_stride_sz_sq[0x5];
1946 	u8         reserved_at_3b8[0x3];
1947 	u8         log_min_stride_sz_sq[0x5];
1948 
1949 	u8         hairpin[0x1];
1950 	u8         reserved_at_3c1[0x2];
1951 	u8         log_max_hairpin_queues[0x5];
1952 	u8         reserved_at_3c8[0x3];
1953 	u8         log_max_hairpin_wq_data_sz[0x5];
1954 	u8         reserved_at_3d0[0x3];
1955 	u8         log_max_hairpin_num_packets[0x5];
1956 	u8         reserved_at_3d8[0x3];
1957 	u8         log_max_wq_sz[0x5];
1958 
1959 	u8         nic_vport_change_event[0x1];
1960 	u8         disable_local_lb_uc[0x1];
1961 	u8         disable_local_lb_mc[0x1];
1962 	u8         log_min_hairpin_wq_data_sz[0x5];
1963 	u8         reserved_at_3e8[0x1];
1964 	u8         silent_mode[0x1];
1965 	u8         vhca_state[0x1];
1966 	u8         log_max_vlan_list[0x5];
1967 	u8         reserved_at_3f0[0x3];
1968 	u8         log_max_current_mc_list[0x5];
1969 	u8         reserved_at_3f8[0x3];
1970 	u8         log_max_current_uc_list[0x5];
1971 
1972 	u8         general_obj_types[0x40];
1973 
1974 	u8         sq_ts_format[0x2];
1975 	u8         rq_ts_format[0x2];
1976 	u8         steering_format_version[0x4];
1977 	u8         create_qp_start_hint[0x18];
1978 
1979 	u8         reserved_at_460[0x1];
1980 	u8         ats[0x1];
1981 	u8         cross_vhca_rqt[0x1];
1982 	u8         log_max_uctx[0x5];
1983 	u8         reserved_at_468[0x1];
1984 	u8         crypto[0x1];
1985 	u8         ipsec_offload[0x1];
1986 	u8         log_max_umem[0x5];
1987 	u8         max_num_eqs[0x10];
1988 
1989 	u8         reserved_at_480[0x1];
1990 	u8         tls_tx[0x1];
1991 	u8         tls_rx[0x1];
1992 	u8         log_max_l2_table[0x5];
1993 	u8         reserved_at_488[0x8];
1994 	u8         log_uar_page_sz[0x10];
1995 
1996 	u8         reserved_at_4a0[0x20];
1997 	u8         device_frequency_mhz[0x20];
1998 	u8         device_frequency_khz[0x20];
1999 
2000 	u8         reserved_at_500[0x20];
2001 	u8	   num_of_uars_per_page[0x20];
2002 
2003 	u8         flex_parser_protocols[0x20];
2004 
2005 	u8         max_geneve_tlv_options[0x8];
2006 	u8         reserved_at_568[0x3];
2007 	u8         max_geneve_tlv_option_data_len[0x5];
2008 	u8         reserved_at_570[0x1];
2009 	u8         adv_rdma[0x1];
2010 	u8         reserved_at_572[0x7];
2011 	u8         adv_virtualization[0x1];
2012 	u8         reserved_at_57a[0x6];
2013 
2014 	u8	   reserved_at_580[0xb];
2015 	u8	   log_max_dci_stream_channels[0x5];
2016 	u8	   reserved_at_590[0x3];
2017 	u8	   log_max_dci_errored_streams[0x5];
2018 	u8	   reserved_at_598[0x8];
2019 
2020 	u8         reserved_at_5a0[0x10];
2021 	u8         enhanced_cqe_compression[0x1];
2022 	u8         reserved_at_5b1[0x1];
2023 	u8         crossing_vhca_mkey[0x1];
2024 	u8         log_max_dek[0x5];
2025 	u8         reserved_at_5b8[0x4];
2026 	u8         mini_cqe_resp_stride_index[0x1];
2027 	u8         cqe_128_always[0x1];
2028 	u8         cqe_compression_128[0x1];
2029 	u8         cqe_compression[0x1];
2030 
2031 	u8         cqe_compression_timeout[0x10];
2032 	u8         cqe_compression_max_num[0x10];
2033 
2034 	u8         reserved_at_5e0[0x8];
2035 	u8         flex_parser_id_gtpu_dw_0[0x4];
2036 	u8         reserved_at_5ec[0x4];
2037 	u8         tag_matching[0x1];
2038 	u8         rndv_offload_rc[0x1];
2039 	u8         rndv_offload_dc[0x1];
2040 	u8         log_tag_matching_list_sz[0x5];
2041 	u8         reserved_at_5f8[0x3];
2042 	u8         log_max_xrq[0x5];
2043 
2044 	u8	   affiliate_nic_vport_criteria[0x8];
2045 	u8	   native_port_num[0x8];
2046 	u8	   num_vhca_ports[0x8];
2047 	u8         flex_parser_id_gtpu_teid[0x4];
2048 	u8         reserved_at_61c[0x2];
2049 	u8	   sw_owner_id[0x1];
2050 	u8         reserved_at_61f[0x1];
2051 
2052 	u8         max_num_of_monitor_counters[0x10];
2053 	u8         num_ppcnt_monitor_counters[0x10];
2054 
2055 	u8         max_num_sf[0x10];
2056 	u8         num_q_monitor_counters[0x10];
2057 
2058 	u8         reserved_at_660[0x20];
2059 
2060 	u8         sf[0x1];
2061 	u8         sf_set_partition[0x1];
2062 	u8         reserved_at_682[0x1];
2063 	u8         log_max_sf[0x5];
2064 	u8         apu[0x1];
2065 	u8         reserved_at_689[0x4];
2066 	u8         migration[0x1];
2067 	u8         reserved_at_68e[0x2];
2068 	u8         log_min_sf_size[0x8];
2069 	u8         max_num_sf_partitions[0x8];
2070 
2071 	u8         uctx_cap[0x20];
2072 
2073 	u8         reserved_at_6c0[0x4];
2074 	u8         flex_parser_id_geneve_tlv_option_0[0x4];
2075 	u8         flex_parser_id_icmp_dw1[0x4];
2076 	u8         flex_parser_id_icmp_dw0[0x4];
2077 	u8         flex_parser_id_icmpv6_dw1[0x4];
2078 	u8         flex_parser_id_icmpv6_dw0[0x4];
2079 	u8         flex_parser_id_outer_first_mpls_over_gre[0x4];
2080 	u8         flex_parser_id_outer_first_mpls_over_udp_label[0x4];
2081 
2082 	u8         max_num_match_definer[0x10];
2083 	u8	   sf_base_id[0x10];
2084 
2085 	u8         flex_parser_id_gtpu_dw_2[0x4];
2086 	u8         flex_parser_id_gtpu_first_ext_dw_0[0x4];
2087 	u8	   num_total_dynamic_vf_msix[0x18];
2088 	u8	   reserved_at_720[0x14];
2089 	u8	   dynamic_msix_table_size[0xc];
2090 	u8	   reserved_at_740[0xc];
2091 	u8	   min_dynamic_vf_msix_table_size[0x4];
2092 	u8	   reserved_at_750[0x2];
2093 	u8	   data_direct[0x1];
2094 	u8	   reserved_at_753[0x1];
2095 	u8	   max_dynamic_vf_msix_table_size[0xc];
2096 
2097 	u8         reserved_at_760[0x3];
2098 	u8         log_max_num_header_modify_argument[0x5];
2099 	u8         log_header_modify_argument_granularity_offset[0x4];
2100 	u8         log_header_modify_argument_granularity[0x4];
2101 	u8         reserved_at_770[0x3];
2102 	u8         log_header_modify_argument_max_alloc[0x5];
2103 	u8         reserved_at_778[0x8];
2104 
2105 	u8	   vhca_tunnel_commands[0x40];
2106 	u8         match_definer_format_supported[0x40];
2107 };
2108 
2109 enum {
2110 	MLX5_CROSS_VHCA_OBJ_TO_OBJ_SUPPORTED_LOCAL_FLOW_TABLE_TO_REMOTE_FLOW_TABLE_MISS  = 0x80000,
2111 	MLX5_CROSS_VHCA_OBJ_TO_OBJ_SUPPORTED_LOCAL_FLOW_TABLE_ROOT_TO_REMOTE_FLOW_TABLE  = (1ULL << 20),
2112 };
2113 
2114 enum {
2115 	MLX5_ALLOWED_OBJ_FOR_OTHER_VHCA_ACCESS_FLOW_TABLE       = 0x200,
2116 };
2117 
2118 struct mlx5_ifc_cmd_hca_cap_2_bits {
2119 	u8	   reserved_at_0[0x80];
2120 
2121 	u8         migratable[0x1];
2122 	u8         reserved_at_81[0x7];
2123 	u8         dp_ordering_force[0x1];
2124 	u8         reserved_at_89[0x9];
2125 	u8         query_vuid[0x1];
2126 	u8         reserved_at_93[0x5];
2127 	u8         umr_log_entity_size_5[0x1];
2128 	u8         reserved_at_99[0x7];
2129 
2130 	u8	   max_reformat_insert_size[0x8];
2131 	u8	   max_reformat_insert_offset[0x8];
2132 	u8	   max_reformat_remove_size[0x8];
2133 	u8	   max_reformat_remove_offset[0x8];
2134 
2135 	u8	   reserved_at_c0[0x8];
2136 	u8	   migration_multi_load[0x1];
2137 	u8	   migration_tracking_state[0x1];
2138 	u8	   multiplane_qp_ud[0x1];
2139 	u8	   reserved_at_cb[0x5];
2140 	u8	   migration_in_chunks[0x1];
2141 	u8	   reserved_at_d1[0x1];
2142 	u8	   sf_eq_usage[0x1];
2143 	u8	   reserved_at_d3[0x5];
2144 	u8	   multiplane[0x1];
2145 	u8	   reserved_at_d9[0x7];
2146 
2147 	u8	   cross_vhca_object_to_object_supported[0x20];
2148 
2149 	u8	   allowed_object_for_other_vhca_access[0x40];
2150 
2151 	u8	   reserved_at_140[0x60];
2152 
2153 	u8	   flow_table_type_2_type[0x8];
2154 	u8	   reserved_at_1a8[0x2];
2155 	u8         format_select_dw_8_6_ext[0x1];
2156 	u8	   log_min_mkey_entity_size[0x5];
2157 	u8	   reserved_at_1b0[0x10];
2158 
2159 	u8	   general_obj_types_127_64[0x40];
2160 	u8	   reserved_at_200[0x20];
2161 
2162 	u8	   reserved_at_220[0x1];
2163 	u8	   sw_vhca_id_valid[0x1];
2164 	u8	   sw_vhca_id[0xe];
2165 	u8	   reserved_at_230[0x10];
2166 
2167 	u8	   reserved_at_240[0xb];
2168 	u8	   ts_cqe_metadata_size2wqe_counter[0x5];
2169 	u8	   reserved_at_250[0x10];
2170 
2171 	u8	   reserved_at_260[0x20];
2172 
2173 	u8	   format_select_dw_gtpu_dw_0[0x8];
2174 	u8	   format_select_dw_gtpu_dw_1[0x8];
2175 	u8	   format_select_dw_gtpu_dw_2[0x8];
2176 	u8	   format_select_dw_gtpu_first_ext_dw_0[0x8];
2177 
2178 	u8	   generate_wqe_type[0x20];
2179 
2180 	u8	   reserved_at_2c0[0xc0];
2181 
2182 	u8	   reserved_at_380[0xb];
2183 	u8	   min_mkey_log_entity_size_fixed_buffer[0x5];
2184 	u8	   ec_vf_vport_base[0x10];
2185 
2186 	u8	   reserved_at_3a0[0x2];
2187 	u8	   max_mkey_log_entity_size_fixed_buffer[0x6];
2188 	u8	   reserved_at_3a8[0x2];
2189 	u8	   max_mkey_log_entity_size_mtt[0x6];
2190 	u8	   max_rqt_vhca_id[0x10];
2191 
2192 	u8	   reserved_at_3c0[0x20];
2193 
2194 	u8	   reserved_at_3e0[0x10];
2195 	u8	   pcc_ifa2[0x1];
2196 	u8	   reserved_at_3f1[0xf];
2197 
2198 	u8	   reserved_at_400[0x1];
2199 	u8	   min_mkey_log_entity_size_fixed_buffer_valid[0x1];
2200 	u8	   reserved_at_402[0xe];
2201 	u8	   return_reg_id[0x10];
2202 
2203 	u8	   reserved_at_420[0x1c];
2204 	u8	   flow_table_hash_type[0x4];
2205 
2206 	u8	   reserved_at_440[0x8];
2207 	u8	   max_num_eqs_24b[0x18];
2208 	u8	   reserved_at_460[0x3a0];
2209 };
2210 
2211 enum mlx5_ifc_flow_destination_type {
2212 	MLX5_IFC_FLOW_DESTINATION_TYPE_VPORT        = 0x0,
2213 	MLX5_IFC_FLOW_DESTINATION_TYPE_FLOW_TABLE   = 0x1,
2214 	MLX5_IFC_FLOW_DESTINATION_TYPE_TIR          = 0x2,
2215 	MLX5_IFC_FLOW_DESTINATION_TYPE_FLOW_SAMPLER = 0x6,
2216 	MLX5_IFC_FLOW_DESTINATION_TYPE_UPLINK       = 0x8,
2217 	MLX5_IFC_FLOW_DESTINATION_TYPE_TABLE_TYPE   = 0xA,
2218 };
2219 
2220 enum mlx5_flow_table_miss_action {
2221 	MLX5_FLOW_TABLE_MISS_ACTION_DEF,
2222 	MLX5_FLOW_TABLE_MISS_ACTION_FWD,
2223 	MLX5_FLOW_TABLE_MISS_ACTION_SWITCH_DOMAIN,
2224 };
2225 
2226 struct mlx5_ifc_dest_format_struct_bits {
2227 	u8         destination_type[0x8];
2228 	u8         destination_id[0x18];
2229 
2230 	u8         destination_eswitch_owner_vhca_id_valid[0x1];
2231 	u8         packet_reformat[0x1];
2232 	u8         reserved_at_22[0x6];
2233 	u8         destination_table_type[0x8];
2234 	u8         destination_eswitch_owner_vhca_id[0x10];
2235 };
2236 
2237 struct mlx5_ifc_flow_counter_list_bits {
2238 	u8         flow_counter_id[0x20];
2239 
2240 	u8         reserved_at_20[0x20];
2241 };
2242 
2243 struct mlx5_ifc_extended_dest_format_bits {
2244 	struct mlx5_ifc_dest_format_struct_bits destination_entry;
2245 
2246 	u8         packet_reformat_id[0x20];
2247 
2248 	u8         reserved_at_60[0x20];
2249 };
2250 
2251 union mlx5_ifc_dest_format_flow_counter_list_auto_bits {
2252 	struct mlx5_ifc_extended_dest_format_bits extended_dest_format;
2253 	struct mlx5_ifc_flow_counter_list_bits flow_counter_list;
2254 };
2255 
2256 struct mlx5_ifc_fte_match_param_bits {
2257 	struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
2258 
2259 	struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
2260 
2261 	struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
2262 
2263 	struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2;
2264 
2265 	struct mlx5_ifc_fte_match_set_misc3_bits misc_parameters_3;
2266 
2267 	struct mlx5_ifc_fte_match_set_misc4_bits misc_parameters_4;
2268 
2269 	struct mlx5_ifc_fte_match_set_misc5_bits misc_parameters_5;
2270 
2271 	u8         reserved_at_e00[0x200];
2272 };
2273 
2274 enum {
2275 	MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP     = 0x0,
2276 	MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP     = 0x1,
2277 	MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT   = 0x2,
2278 	MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT   = 0x3,
2279 	MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI  = 0x4,
2280 };
2281 
2282 struct mlx5_ifc_rx_hash_field_select_bits {
2283 	u8         l3_prot_type[0x1];
2284 	u8         l4_prot_type[0x1];
2285 	u8         selected_fields[0x1e];
2286 };
2287 
2288 enum {
2289 	MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST  = 0x0,
2290 	MLX5_WQ_WQ_TYPE_WQ_CYCLIC       = 0x1,
2291 };
2292 
2293 enum {
2294 	MLX5_WQ_END_PADDING_MODE_END_PAD_NONE   = 0x0,
2295 	MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN  = 0x1,
2296 };
2297 
2298 struct mlx5_ifc_wq_bits {
2299 	u8         wq_type[0x4];
2300 	u8         wq_signature[0x1];
2301 	u8         end_padding_mode[0x2];
2302 	u8         cd_slave[0x1];
2303 	u8         reserved_at_8[0x18];
2304 
2305 	u8         hds_skip_first_sge[0x1];
2306 	u8         log2_hds_buf_size[0x3];
2307 	u8         reserved_at_24[0x7];
2308 	u8         page_offset[0x5];
2309 	u8         lwm[0x10];
2310 
2311 	u8         reserved_at_40[0x8];
2312 	u8         pd[0x18];
2313 
2314 	u8         reserved_at_60[0x8];
2315 	u8         uar_page[0x18];
2316 
2317 	u8         dbr_addr[0x40];
2318 
2319 	u8         hw_counter[0x20];
2320 
2321 	u8         sw_counter[0x20];
2322 
2323 	u8         reserved_at_100[0xc];
2324 	u8         log_wq_stride[0x4];
2325 	u8         reserved_at_110[0x3];
2326 	u8         log_wq_pg_sz[0x5];
2327 	u8         reserved_at_118[0x3];
2328 	u8         log_wq_sz[0x5];
2329 
2330 	u8         dbr_umem_valid[0x1];
2331 	u8         wq_umem_valid[0x1];
2332 	u8         reserved_at_122[0x1];
2333 	u8         log_hairpin_num_packets[0x5];
2334 	u8         reserved_at_128[0x3];
2335 	u8         log_hairpin_data_sz[0x5];
2336 
2337 	u8         reserved_at_130[0x4];
2338 	u8         log_wqe_num_of_strides[0x4];
2339 	u8         two_byte_shift_en[0x1];
2340 	u8         reserved_at_139[0x4];
2341 	u8         log_wqe_stride_size[0x3];
2342 
2343 	u8         dbr_umem_id[0x20];
2344 	u8         wq_umem_id[0x20];
2345 
2346 	u8         wq_umem_offset[0x40];
2347 
2348 	u8         headers_mkey[0x20];
2349 
2350 	u8         shampo_enable[0x1];
2351 	u8         reserved_at_1e1[0x1];
2352 	u8         shampo_mode[0x2];
2353 	u8         reserved_at_1e4[0x1];
2354 	u8         log_reservation_size[0x3];
2355 	u8         reserved_at_1e8[0x5];
2356 	u8         log_max_num_of_packets_per_reservation[0x3];
2357 	u8         reserved_at_1f0[0x6];
2358 	u8         log_headers_entry_size[0x2];
2359 	u8         reserved_at_1f8[0x4];
2360 	u8         log_headers_buffer_entry_num[0x4];
2361 
2362 	u8         reserved_at_200[0x400];
2363 
2364 	struct mlx5_ifc_cmd_pas_bits pas[];
2365 };
2366 
2367 struct mlx5_ifc_rq_num_bits {
2368 	u8         reserved_at_0[0x8];
2369 	u8         rq_num[0x18];
2370 };
2371 
2372 struct mlx5_ifc_rq_vhca_bits {
2373 	u8         reserved_at_0[0x8];
2374 	u8         rq_num[0x18];
2375 	u8         reserved_at_20[0x10];
2376 	u8         rq_vhca_id[0x10];
2377 };
2378 
2379 struct mlx5_ifc_mac_address_layout_bits {
2380 	u8         reserved_at_0[0x10];
2381 	u8         mac_addr_47_32[0x10];
2382 
2383 	u8         mac_addr_31_0[0x20];
2384 };
2385 
2386 struct mlx5_ifc_vlan_layout_bits {
2387 	u8         reserved_at_0[0x14];
2388 	u8         vlan[0x0c];
2389 
2390 	u8         reserved_at_20[0x20];
2391 };
2392 
2393 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
2394 	u8         reserved_at_0[0xa0];
2395 
2396 	u8         min_time_between_cnps[0x20];
2397 
2398 	u8         reserved_at_c0[0x12];
2399 	u8         cnp_dscp[0x6];
2400 	u8         reserved_at_d8[0x4];
2401 	u8         cnp_prio_mode[0x1];
2402 	u8         cnp_802p_prio[0x3];
2403 
2404 	u8         reserved_at_e0[0x720];
2405 };
2406 
2407 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
2408 	u8         reserved_at_0[0x60];
2409 
2410 	u8         reserved_at_60[0x4];
2411 	u8         clamp_tgt_rate[0x1];
2412 	u8         reserved_at_65[0x3];
2413 	u8         clamp_tgt_rate_after_time_inc[0x1];
2414 	u8         reserved_at_69[0x17];
2415 
2416 	u8         reserved_at_80[0x20];
2417 
2418 	u8         rpg_time_reset[0x20];
2419 
2420 	u8         rpg_byte_reset[0x20];
2421 
2422 	u8         rpg_threshold[0x20];
2423 
2424 	u8         rpg_max_rate[0x20];
2425 
2426 	u8         rpg_ai_rate[0x20];
2427 
2428 	u8         rpg_hai_rate[0x20];
2429 
2430 	u8         rpg_gd[0x20];
2431 
2432 	u8         rpg_min_dec_fac[0x20];
2433 
2434 	u8         rpg_min_rate[0x20];
2435 
2436 	u8         reserved_at_1c0[0xe0];
2437 
2438 	u8         rate_to_set_on_first_cnp[0x20];
2439 
2440 	u8         dce_tcp_g[0x20];
2441 
2442 	u8         dce_tcp_rtt[0x20];
2443 
2444 	u8         rate_reduce_monitor_period[0x20];
2445 
2446 	u8         reserved_at_320[0x20];
2447 
2448 	u8         initial_alpha_value[0x20];
2449 
2450 	u8         reserved_at_360[0x4a0];
2451 };
2452 
2453 struct mlx5_ifc_cong_control_r_roce_general_bits {
2454 	u8         reserved_at_0[0x80];
2455 
2456 	u8         reserved_at_80[0x10];
2457 	u8         rtt_resp_dscp_valid[0x1];
2458 	u8         reserved_at_91[0x9];
2459 	u8         rtt_resp_dscp[0x6];
2460 
2461 	u8         reserved_at_a0[0x760];
2462 };
2463 
2464 struct mlx5_ifc_cong_control_802_1qau_rp_bits {
2465 	u8         reserved_at_0[0x80];
2466 
2467 	u8         rppp_max_rps[0x20];
2468 
2469 	u8         rpg_time_reset[0x20];
2470 
2471 	u8         rpg_byte_reset[0x20];
2472 
2473 	u8         rpg_threshold[0x20];
2474 
2475 	u8         rpg_max_rate[0x20];
2476 
2477 	u8         rpg_ai_rate[0x20];
2478 
2479 	u8         rpg_hai_rate[0x20];
2480 
2481 	u8         rpg_gd[0x20];
2482 
2483 	u8         rpg_min_dec_fac[0x20];
2484 
2485 	u8         rpg_min_rate[0x20];
2486 
2487 	u8         reserved_at_1c0[0x640];
2488 };
2489 
2490 enum {
2491 	MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE    = 0x1,
2492 	MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET    = 0x2,
2493 	MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE  = 0x4,
2494 };
2495 
2496 struct mlx5_ifc_resize_field_select_bits {
2497 	u8         resize_field_select[0x20];
2498 };
2499 
2500 struct mlx5_ifc_resource_dump_bits {
2501 	u8         more_dump[0x1];
2502 	u8         inline_dump[0x1];
2503 	u8         reserved_at_2[0xa];
2504 	u8         seq_num[0x4];
2505 	u8         segment_type[0x10];
2506 
2507 	u8         reserved_at_20[0x10];
2508 	u8         vhca_id[0x10];
2509 
2510 	u8         index1[0x20];
2511 
2512 	u8         index2[0x20];
2513 
2514 	u8         num_of_obj1[0x10];
2515 	u8         num_of_obj2[0x10];
2516 
2517 	u8         reserved_at_a0[0x20];
2518 
2519 	u8         device_opaque[0x40];
2520 
2521 	u8         mkey[0x20];
2522 
2523 	u8         size[0x20];
2524 
2525 	u8         address[0x40];
2526 
2527 	u8         inline_data[52][0x20];
2528 };
2529 
2530 struct mlx5_ifc_resource_dump_menu_record_bits {
2531 	u8         reserved_at_0[0x4];
2532 	u8         num_of_obj2_supports_active[0x1];
2533 	u8         num_of_obj2_supports_all[0x1];
2534 	u8         must_have_num_of_obj2[0x1];
2535 	u8         support_num_of_obj2[0x1];
2536 	u8         num_of_obj1_supports_active[0x1];
2537 	u8         num_of_obj1_supports_all[0x1];
2538 	u8         must_have_num_of_obj1[0x1];
2539 	u8         support_num_of_obj1[0x1];
2540 	u8         must_have_index2[0x1];
2541 	u8         support_index2[0x1];
2542 	u8         must_have_index1[0x1];
2543 	u8         support_index1[0x1];
2544 	u8         segment_type[0x10];
2545 
2546 	u8         segment_name[4][0x20];
2547 
2548 	u8         index1_name[4][0x20];
2549 
2550 	u8         index2_name[4][0x20];
2551 };
2552 
2553 struct mlx5_ifc_resource_dump_segment_header_bits {
2554 	u8         length_dw[0x10];
2555 	u8         segment_type[0x10];
2556 };
2557 
2558 struct mlx5_ifc_resource_dump_command_segment_bits {
2559 	struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2560 
2561 	u8         segment_called[0x10];
2562 	u8         vhca_id[0x10];
2563 
2564 	u8         index1[0x20];
2565 
2566 	u8         index2[0x20];
2567 
2568 	u8         num_of_obj1[0x10];
2569 	u8         num_of_obj2[0x10];
2570 };
2571 
2572 struct mlx5_ifc_resource_dump_error_segment_bits {
2573 	struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2574 
2575 	u8         reserved_at_20[0x10];
2576 	u8         syndrome_id[0x10];
2577 
2578 	u8         reserved_at_40[0x40];
2579 
2580 	u8         error[8][0x20];
2581 };
2582 
2583 struct mlx5_ifc_resource_dump_info_segment_bits {
2584 	struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2585 
2586 	u8         reserved_at_20[0x18];
2587 	u8         dump_version[0x8];
2588 
2589 	u8         hw_version[0x20];
2590 
2591 	u8         fw_version[0x20];
2592 };
2593 
2594 struct mlx5_ifc_resource_dump_menu_segment_bits {
2595 	struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2596 
2597 	u8         reserved_at_20[0x10];
2598 	u8         num_of_records[0x10];
2599 
2600 	struct mlx5_ifc_resource_dump_menu_record_bits record[];
2601 };
2602 
2603 struct mlx5_ifc_resource_dump_resource_segment_bits {
2604 	struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2605 
2606 	u8         reserved_at_20[0x20];
2607 
2608 	u8         index1[0x20];
2609 
2610 	u8         index2[0x20];
2611 
2612 	u8         payload[][0x20];
2613 };
2614 
2615 struct mlx5_ifc_resource_dump_terminate_segment_bits {
2616 	struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2617 };
2618 
2619 struct mlx5_ifc_menu_resource_dump_response_bits {
2620 	struct mlx5_ifc_resource_dump_info_segment_bits info;
2621 	struct mlx5_ifc_resource_dump_command_segment_bits cmd;
2622 	struct mlx5_ifc_resource_dump_menu_segment_bits menu;
2623 	struct mlx5_ifc_resource_dump_terminate_segment_bits terminate;
2624 };
2625 
2626 enum {
2627 	MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD     = 0x1,
2628 	MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT  = 0x2,
2629 	MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI            = 0x4,
2630 	MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN         = 0x8,
2631 };
2632 
2633 struct mlx5_ifc_modify_field_select_bits {
2634 	u8         modify_field_select[0x20];
2635 };
2636 
2637 struct mlx5_ifc_field_select_r_roce_np_bits {
2638 	u8         field_select_r_roce_np[0x20];
2639 };
2640 
2641 struct mlx5_ifc_field_select_r_roce_rp_bits {
2642 	u8         field_select_r_roce_rp[0x20];
2643 };
2644 
2645 enum {
2646 	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS     = 0x4,
2647 	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET   = 0x8,
2648 	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET   = 0x10,
2649 	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD    = 0x20,
2650 	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE     = 0x40,
2651 	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE      = 0x80,
2652 	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE     = 0x100,
2653 	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD           = 0x200,
2654 	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC  = 0x400,
2655 	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE     = 0x800,
2656 };
2657 
2658 struct mlx5_ifc_field_select_802_1qau_rp_bits {
2659 	u8         field_select_8021qaurp[0x20];
2660 };
2661 
2662 struct mlx5_ifc_phys_layer_recovery_cntrs_bits {
2663 	u8         total_successful_recovery_events[0x20];
2664 
2665 	u8         reserved_at_20[0x7a0];
2666 };
2667 
2668 struct mlx5_ifc_phys_layer_cntrs_bits {
2669 	u8         time_since_last_clear_high[0x20];
2670 
2671 	u8         time_since_last_clear_low[0x20];
2672 
2673 	u8         symbol_errors_high[0x20];
2674 
2675 	u8         symbol_errors_low[0x20];
2676 
2677 	u8         sync_headers_errors_high[0x20];
2678 
2679 	u8         sync_headers_errors_low[0x20];
2680 
2681 	u8         edpl_bip_errors_lane0_high[0x20];
2682 
2683 	u8         edpl_bip_errors_lane0_low[0x20];
2684 
2685 	u8         edpl_bip_errors_lane1_high[0x20];
2686 
2687 	u8         edpl_bip_errors_lane1_low[0x20];
2688 
2689 	u8         edpl_bip_errors_lane2_high[0x20];
2690 
2691 	u8         edpl_bip_errors_lane2_low[0x20];
2692 
2693 	u8         edpl_bip_errors_lane3_high[0x20];
2694 
2695 	u8         edpl_bip_errors_lane3_low[0x20];
2696 
2697 	u8         fc_fec_corrected_blocks_lane0_high[0x20];
2698 
2699 	u8         fc_fec_corrected_blocks_lane0_low[0x20];
2700 
2701 	u8         fc_fec_corrected_blocks_lane1_high[0x20];
2702 
2703 	u8         fc_fec_corrected_blocks_lane1_low[0x20];
2704 
2705 	u8         fc_fec_corrected_blocks_lane2_high[0x20];
2706 
2707 	u8         fc_fec_corrected_blocks_lane2_low[0x20];
2708 
2709 	u8         fc_fec_corrected_blocks_lane3_high[0x20];
2710 
2711 	u8         fc_fec_corrected_blocks_lane3_low[0x20];
2712 
2713 	u8         fc_fec_uncorrectable_blocks_lane0_high[0x20];
2714 
2715 	u8         fc_fec_uncorrectable_blocks_lane0_low[0x20];
2716 
2717 	u8         fc_fec_uncorrectable_blocks_lane1_high[0x20];
2718 
2719 	u8         fc_fec_uncorrectable_blocks_lane1_low[0x20];
2720 
2721 	u8         fc_fec_uncorrectable_blocks_lane2_high[0x20];
2722 
2723 	u8         fc_fec_uncorrectable_blocks_lane2_low[0x20];
2724 
2725 	u8         fc_fec_uncorrectable_blocks_lane3_high[0x20];
2726 
2727 	u8         fc_fec_uncorrectable_blocks_lane3_low[0x20];
2728 
2729 	u8         rs_fec_corrected_blocks_high[0x20];
2730 
2731 	u8         rs_fec_corrected_blocks_low[0x20];
2732 
2733 	u8         rs_fec_uncorrectable_blocks_high[0x20];
2734 
2735 	u8         rs_fec_uncorrectable_blocks_low[0x20];
2736 
2737 	u8         rs_fec_no_errors_blocks_high[0x20];
2738 
2739 	u8         rs_fec_no_errors_blocks_low[0x20];
2740 
2741 	u8         rs_fec_single_error_blocks_high[0x20];
2742 
2743 	u8         rs_fec_single_error_blocks_low[0x20];
2744 
2745 	u8         rs_fec_corrected_symbols_total_high[0x20];
2746 
2747 	u8         rs_fec_corrected_symbols_total_low[0x20];
2748 
2749 	u8         rs_fec_corrected_symbols_lane0_high[0x20];
2750 
2751 	u8         rs_fec_corrected_symbols_lane0_low[0x20];
2752 
2753 	u8         rs_fec_corrected_symbols_lane1_high[0x20];
2754 
2755 	u8         rs_fec_corrected_symbols_lane1_low[0x20];
2756 
2757 	u8         rs_fec_corrected_symbols_lane2_high[0x20];
2758 
2759 	u8         rs_fec_corrected_symbols_lane2_low[0x20];
2760 
2761 	u8         rs_fec_corrected_symbols_lane3_high[0x20];
2762 
2763 	u8         rs_fec_corrected_symbols_lane3_low[0x20];
2764 
2765 	u8         link_down_events[0x20];
2766 
2767 	u8         successful_recovery_events[0x20];
2768 
2769 	u8         reserved_at_640[0x180];
2770 };
2771 
2772 struct mlx5_ifc_phys_layer_statistical_cntrs_bits {
2773 	u8         time_since_last_clear_high[0x20];
2774 
2775 	u8         time_since_last_clear_low[0x20];
2776 
2777 	u8         phy_received_bits_high[0x20];
2778 
2779 	u8         phy_received_bits_low[0x20];
2780 
2781 	u8         phy_symbol_errors_high[0x20];
2782 
2783 	u8         phy_symbol_errors_low[0x20];
2784 
2785 	u8         phy_corrected_bits_high[0x20];
2786 
2787 	u8         phy_corrected_bits_low[0x20];
2788 
2789 	u8         phy_corrected_bits_lane0_high[0x20];
2790 
2791 	u8         phy_corrected_bits_lane0_low[0x20];
2792 
2793 	u8         phy_corrected_bits_lane1_high[0x20];
2794 
2795 	u8         phy_corrected_bits_lane1_low[0x20];
2796 
2797 	u8         phy_corrected_bits_lane2_high[0x20];
2798 
2799 	u8         phy_corrected_bits_lane2_low[0x20];
2800 
2801 	u8         phy_corrected_bits_lane3_high[0x20];
2802 
2803 	u8         phy_corrected_bits_lane3_low[0x20];
2804 
2805 	u8         reserved_at_200[0x5c0];
2806 };
2807 
2808 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits {
2809 	u8	   symbol_error_counter[0x10];
2810 
2811 	u8         link_error_recovery_counter[0x8];
2812 
2813 	u8         link_downed_counter[0x8];
2814 
2815 	u8         port_rcv_errors[0x10];
2816 
2817 	u8         port_rcv_remote_physical_errors[0x10];
2818 
2819 	u8         port_rcv_switch_relay_errors[0x10];
2820 
2821 	u8         port_xmit_discards[0x10];
2822 
2823 	u8         port_xmit_constraint_errors[0x8];
2824 
2825 	u8         port_rcv_constraint_errors[0x8];
2826 
2827 	u8         reserved_at_70[0x8];
2828 
2829 	u8         link_overrun_errors[0x8];
2830 
2831 	u8	   reserved_at_80[0x10];
2832 
2833 	u8         vl_15_dropped[0x10];
2834 
2835 	u8	   reserved_at_a0[0x80];
2836 
2837 	u8         port_xmit_wait[0x20];
2838 };
2839 
2840 struct mlx5_ifc_ib_ext_port_cntrs_grp_data_layout_bits {
2841 	u8         reserved_at_0[0x300];
2842 
2843 	u8         port_xmit_data_high[0x20];
2844 
2845 	u8         port_xmit_data_low[0x20];
2846 
2847 	u8         port_rcv_data_high[0x20];
2848 
2849 	u8         port_rcv_data_low[0x20];
2850 
2851 	u8         port_xmit_pkts_high[0x20];
2852 
2853 	u8         port_xmit_pkts_low[0x20];
2854 
2855 	u8         port_rcv_pkts_high[0x20];
2856 
2857 	u8         port_rcv_pkts_low[0x20];
2858 
2859 	u8         reserved_at_400[0x80];
2860 
2861 	u8         port_unicast_xmit_pkts_high[0x20];
2862 
2863 	u8         port_unicast_xmit_pkts_low[0x20];
2864 
2865 	u8         port_multicast_xmit_pkts_high[0x20];
2866 
2867 	u8         port_multicast_xmit_pkts_low[0x20];
2868 
2869 	u8         port_unicast_rcv_pkts_high[0x20];
2870 
2871 	u8         port_unicast_rcv_pkts_low[0x20];
2872 
2873 	u8         port_multicast_rcv_pkts_high[0x20];
2874 
2875 	u8         port_multicast_rcv_pkts_low[0x20];
2876 
2877 	u8         reserved_at_580[0x240];
2878 };
2879 
2880 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits {
2881 	u8         transmit_queue_high[0x20];
2882 
2883 	u8         transmit_queue_low[0x20];
2884 
2885 	u8         no_buffer_discard_uc_high[0x20];
2886 
2887 	u8         no_buffer_discard_uc_low[0x20];
2888 
2889 	u8         reserved_at_80[0x740];
2890 };
2891 
2892 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits {
2893 	u8         wred_discard_high[0x20];
2894 
2895 	u8         wred_discard_low[0x20];
2896 
2897 	u8         ecn_marked_tc_high[0x20];
2898 
2899 	u8         ecn_marked_tc_low[0x20];
2900 
2901 	u8         reserved_at_80[0x740];
2902 };
2903 
2904 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
2905 	u8         rx_octets_high[0x20];
2906 
2907 	u8         rx_octets_low[0x20];
2908 
2909 	u8         reserved_at_40[0xc0];
2910 
2911 	u8         rx_frames_high[0x20];
2912 
2913 	u8         rx_frames_low[0x20];
2914 
2915 	u8         tx_octets_high[0x20];
2916 
2917 	u8         tx_octets_low[0x20];
2918 
2919 	u8         reserved_at_180[0xc0];
2920 
2921 	u8         tx_frames_high[0x20];
2922 
2923 	u8         tx_frames_low[0x20];
2924 
2925 	u8         rx_pause_high[0x20];
2926 
2927 	u8         rx_pause_low[0x20];
2928 
2929 	u8         rx_pause_duration_high[0x20];
2930 
2931 	u8         rx_pause_duration_low[0x20];
2932 
2933 	u8         tx_pause_high[0x20];
2934 
2935 	u8         tx_pause_low[0x20];
2936 
2937 	u8         tx_pause_duration_high[0x20];
2938 
2939 	u8         tx_pause_duration_low[0x20];
2940 
2941 	u8         rx_pause_transition_high[0x20];
2942 
2943 	u8         rx_pause_transition_low[0x20];
2944 
2945 	u8         rx_discards_high[0x20];
2946 
2947 	u8         rx_discards_low[0x20];
2948 
2949 	u8         device_stall_minor_watermark_cnt_high[0x20];
2950 
2951 	u8         device_stall_minor_watermark_cnt_low[0x20];
2952 
2953 	u8         device_stall_critical_watermark_cnt_high[0x20];
2954 
2955 	u8         device_stall_critical_watermark_cnt_low[0x20];
2956 
2957 	u8         reserved_at_480[0x340];
2958 };
2959 
2960 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
2961 	u8         port_transmit_wait_high[0x20];
2962 
2963 	u8         port_transmit_wait_low[0x20];
2964 
2965 	u8         reserved_at_40[0x100];
2966 
2967 	u8         rx_buffer_almost_full_high[0x20];
2968 
2969 	u8         rx_buffer_almost_full_low[0x20];
2970 
2971 	u8         rx_buffer_full_high[0x20];
2972 
2973 	u8         rx_buffer_full_low[0x20];
2974 
2975 	u8         rx_icrc_encapsulated_high[0x20];
2976 
2977 	u8         rx_icrc_encapsulated_low[0x20];
2978 
2979 	u8         reserved_at_200[0x5c0];
2980 };
2981 
2982 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
2983 	u8         dot3stats_alignment_errors_high[0x20];
2984 
2985 	u8         dot3stats_alignment_errors_low[0x20];
2986 
2987 	u8         dot3stats_fcs_errors_high[0x20];
2988 
2989 	u8         dot3stats_fcs_errors_low[0x20];
2990 
2991 	u8         dot3stats_single_collision_frames_high[0x20];
2992 
2993 	u8         dot3stats_single_collision_frames_low[0x20];
2994 
2995 	u8         dot3stats_multiple_collision_frames_high[0x20];
2996 
2997 	u8         dot3stats_multiple_collision_frames_low[0x20];
2998 
2999 	u8         dot3stats_sqe_test_errors_high[0x20];
3000 
3001 	u8         dot3stats_sqe_test_errors_low[0x20];
3002 
3003 	u8         dot3stats_deferred_transmissions_high[0x20];
3004 
3005 	u8         dot3stats_deferred_transmissions_low[0x20];
3006 
3007 	u8         dot3stats_late_collisions_high[0x20];
3008 
3009 	u8         dot3stats_late_collisions_low[0x20];
3010 
3011 	u8         dot3stats_excessive_collisions_high[0x20];
3012 
3013 	u8         dot3stats_excessive_collisions_low[0x20];
3014 
3015 	u8         dot3stats_internal_mac_transmit_errors_high[0x20];
3016 
3017 	u8         dot3stats_internal_mac_transmit_errors_low[0x20];
3018 
3019 	u8         dot3stats_carrier_sense_errors_high[0x20];
3020 
3021 	u8         dot3stats_carrier_sense_errors_low[0x20];
3022 
3023 	u8         dot3stats_frame_too_longs_high[0x20];
3024 
3025 	u8         dot3stats_frame_too_longs_low[0x20];
3026 
3027 	u8         dot3stats_internal_mac_receive_errors_high[0x20];
3028 
3029 	u8         dot3stats_internal_mac_receive_errors_low[0x20];
3030 
3031 	u8         dot3stats_symbol_errors_high[0x20];
3032 
3033 	u8         dot3stats_symbol_errors_low[0x20];
3034 
3035 	u8         dot3control_in_unknown_opcodes_high[0x20];
3036 
3037 	u8         dot3control_in_unknown_opcodes_low[0x20];
3038 
3039 	u8         dot3in_pause_frames_high[0x20];
3040 
3041 	u8         dot3in_pause_frames_low[0x20];
3042 
3043 	u8         dot3out_pause_frames_high[0x20];
3044 
3045 	u8         dot3out_pause_frames_low[0x20];
3046 
3047 	u8         reserved_at_400[0x3c0];
3048 };
3049 
3050 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
3051 	u8         ether_stats_drop_events_high[0x20];
3052 
3053 	u8         ether_stats_drop_events_low[0x20];
3054 
3055 	u8         ether_stats_octets_high[0x20];
3056 
3057 	u8         ether_stats_octets_low[0x20];
3058 
3059 	u8         ether_stats_pkts_high[0x20];
3060 
3061 	u8         ether_stats_pkts_low[0x20];
3062 
3063 	u8         ether_stats_broadcast_pkts_high[0x20];
3064 
3065 	u8         ether_stats_broadcast_pkts_low[0x20];
3066 
3067 	u8         ether_stats_multicast_pkts_high[0x20];
3068 
3069 	u8         ether_stats_multicast_pkts_low[0x20];
3070 
3071 	u8         ether_stats_crc_align_errors_high[0x20];
3072 
3073 	u8         ether_stats_crc_align_errors_low[0x20];
3074 
3075 	u8         ether_stats_undersize_pkts_high[0x20];
3076 
3077 	u8         ether_stats_undersize_pkts_low[0x20];
3078 
3079 	u8         ether_stats_oversize_pkts_high[0x20];
3080 
3081 	u8         ether_stats_oversize_pkts_low[0x20];
3082 
3083 	u8         ether_stats_fragments_high[0x20];
3084 
3085 	u8         ether_stats_fragments_low[0x20];
3086 
3087 	u8         ether_stats_jabbers_high[0x20];
3088 
3089 	u8         ether_stats_jabbers_low[0x20];
3090 
3091 	u8         ether_stats_collisions_high[0x20];
3092 
3093 	u8         ether_stats_collisions_low[0x20];
3094 
3095 	u8         ether_stats_pkts64octets_high[0x20];
3096 
3097 	u8         ether_stats_pkts64octets_low[0x20];
3098 
3099 	u8         ether_stats_pkts65to127octets_high[0x20];
3100 
3101 	u8         ether_stats_pkts65to127octets_low[0x20];
3102 
3103 	u8         ether_stats_pkts128to255octets_high[0x20];
3104 
3105 	u8         ether_stats_pkts128to255octets_low[0x20];
3106 
3107 	u8         ether_stats_pkts256to511octets_high[0x20];
3108 
3109 	u8         ether_stats_pkts256to511octets_low[0x20];
3110 
3111 	u8         ether_stats_pkts512to1023octets_high[0x20];
3112 
3113 	u8         ether_stats_pkts512to1023octets_low[0x20];
3114 
3115 	u8         ether_stats_pkts1024to1518octets_high[0x20];
3116 
3117 	u8         ether_stats_pkts1024to1518octets_low[0x20];
3118 
3119 	u8         ether_stats_pkts1519to2047octets_high[0x20];
3120 
3121 	u8         ether_stats_pkts1519to2047octets_low[0x20];
3122 
3123 	u8         ether_stats_pkts2048to4095octets_high[0x20];
3124 
3125 	u8         ether_stats_pkts2048to4095octets_low[0x20];
3126 
3127 	u8         ether_stats_pkts4096to8191octets_high[0x20];
3128 
3129 	u8         ether_stats_pkts4096to8191octets_low[0x20];
3130 
3131 	u8         ether_stats_pkts8192to10239octets_high[0x20];
3132 
3133 	u8         ether_stats_pkts8192to10239octets_low[0x20];
3134 
3135 	u8         reserved_at_540[0x280];
3136 };
3137 
3138 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
3139 	u8         if_in_octets_high[0x20];
3140 
3141 	u8         if_in_octets_low[0x20];
3142 
3143 	u8         if_in_ucast_pkts_high[0x20];
3144 
3145 	u8         if_in_ucast_pkts_low[0x20];
3146 
3147 	u8         if_in_discards_high[0x20];
3148 
3149 	u8         if_in_discards_low[0x20];
3150 
3151 	u8         if_in_errors_high[0x20];
3152 
3153 	u8         if_in_errors_low[0x20];
3154 
3155 	u8         if_in_unknown_protos_high[0x20];
3156 
3157 	u8         if_in_unknown_protos_low[0x20];
3158 
3159 	u8         if_out_octets_high[0x20];
3160 
3161 	u8         if_out_octets_low[0x20];
3162 
3163 	u8         if_out_ucast_pkts_high[0x20];
3164 
3165 	u8         if_out_ucast_pkts_low[0x20];
3166 
3167 	u8         if_out_discards_high[0x20];
3168 
3169 	u8         if_out_discards_low[0x20];
3170 
3171 	u8         if_out_errors_high[0x20];
3172 
3173 	u8         if_out_errors_low[0x20];
3174 
3175 	u8         if_in_multicast_pkts_high[0x20];
3176 
3177 	u8         if_in_multicast_pkts_low[0x20];
3178 
3179 	u8         if_in_broadcast_pkts_high[0x20];
3180 
3181 	u8         if_in_broadcast_pkts_low[0x20];
3182 
3183 	u8         if_out_multicast_pkts_high[0x20];
3184 
3185 	u8         if_out_multicast_pkts_low[0x20];
3186 
3187 	u8         if_out_broadcast_pkts_high[0x20];
3188 
3189 	u8         if_out_broadcast_pkts_low[0x20];
3190 
3191 	u8         reserved_at_340[0x480];
3192 };
3193 
3194 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
3195 	u8         a_frames_transmitted_ok_high[0x20];
3196 
3197 	u8         a_frames_transmitted_ok_low[0x20];
3198 
3199 	u8         a_frames_received_ok_high[0x20];
3200 
3201 	u8         a_frames_received_ok_low[0x20];
3202 
3203 	u8         a_frame_check_sequence_errors_high[0x20];
3204 
3205 	u8         a_frame_check_sequence_errors_low[0x20];
3206 
3207 	u8         a_alignment_errors_high[0x20];
3208 
3209 	u8         a_alignment_errors_low[0x20];
3210 
3211 	u8         a_octets_transmitted_ok_high[0x20];
3212 
3213 	u8         a_octets_transmitted_ok_low[0x20];
3214 
3215 	u8         a_octets_received_ok_high[0x20];
3216 
3217 	u8         a_octets_received_ok_low[0x20];
3218 
3219 	u8         a_multicast_frames_xmitted_ok_high[0x20];
3220 
3221 	u8         a_multicast_frames_xmitted_ok_low[0x20];
3222 
3223 	u8         a_broadcast_frames_xmitted_ok_high[0x20];
3224 
3225 	u8         a_broadcast_frames_xmitted_ok_low[0x20];
3226 
3227 	u8         a_multicast_frames_received_ok_high[0x20];
3228 
3229 	u8         a_multicast_frames_received_ok_low[0x20];
3230 
3231 	u8         a_broadcast_frames_received_ok_high[0x20];
3232 
3233 	u8         a_broadcast_frames_received_ok_low[0x20];
3234 
3235 	u8         a_in_range_length_errors_high[0x20];
3236 
3237 	u8         a_in_range_length_errors_low[0x20];
3238 
3239 	u8         a_out_of_range_length_field_high[0x20];
3240 
3241 	u8         a_out_of_range_length_field_low[0x20];
3242 
3243 	u8         a_frame_too_long_errors_high[0x20];
3244 
3245 	u8         a_frame_too_long_errors_low[0x20];
3246 
3247 	u8         a_symbol_error_during_carrier_high[0x20];
3248 
3249 	u8         a_symbol_error_during_carrier_low[0x20];
3250 
3251 	u8         a_mac_control_frames_transmitted_high[0x20];
3252 
3253 	u8         a_mac_control_frames_transmitted_low[0x20];
3254 
3255 	u8         a_mac_control_frames_received_high[0x20];
3256 
3257 	u8         a_mac_control_frames_received_low[0x20];
3258 
3259 	u8         a_unsupported_opcodes_received_high[0x20];
3260 
3261 	u8         a_unsupported_opcodes_received_low[0x20];
3262 
3263 	u8         a_pause_mac_ctrl_frames_received_high[0x20];
3264 
3265 	u8         a_pause_mac_ctrl_frames_received_low[0x20];
3266 
3267 	u8         a_pause_mac_ctrl_frames_transmitted_high[0x20];
3268 
3269 	u8         a_pause_mac_ctrl_frames_transmitted_low[0x20];
3270 
3271 	u8         reserved_at_4c0[0x300];
3272 };
3273 
3274 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits {
3275 	u8         life_time_counter_high[0x20];
3276 
3277 	u8         life_time_counter_low[0x20];
3278 
3279 	u8         rx_errors[0x20];
3280 
3281 	u8         tx_errors[0x20];
3282 
3283 	u8         l0_to_recovery_eieos[0x20];
3284 
3285 	u8         l0_to_recovery_ts[0x20];
3286 
3287 	u8         l0_to_recovery_framing[0x20];
3288 
3289 	u8         l0_to_recovery_retrain[0x20];
3290 
3291 	u8         crc_error_dllp[0x20];
3292 
3293 	u8         crc_error_tlp[0x20];
3294 
3295 	u8         tx_overflow_buffer_pkt_high[0x20];
3296 
3297 	u8         tx_overflow_buffer_pkt_low[0x20];
3298 
3299 	u8         outbound_stalled_reads[0x20];
3300 
3301 	u8         outbound_stalled_writes[0x20];
3302 
3303 	u8         outbound_stalled_reads_events[0x20];
3304 
3305 	u8         outbound_stalled_writes_events[0x20];
3306 
3307 	u8         reserved_at_200[0x5c0];
3308 };
3309 
3310 struct mlx5_ifc_cmd_inter_comp_event_bits {
3311 	u8         command_completion_vector[0x20];
3312 
3313 	u8         reserved_at_20[0xc0];
3314 };
3315 
3316 struct mlx5_ifc_stall_vl_event_bits {
3317 	u8         reserved_at_0[0x18];
3318 	u8         port_num[0x1];
3319 	u8         reserved_at_19[0x3];
3320 	u8         vl[0x4];
3321 
3322 	u8         reserved_at_20[0xa0];
3323 };
3324 
3325 struct mlx5_ifc_db_bf_congestion_event_bits {
3326 	u8         event_subtype[0x8];
3327 	u8         reserved_at_8[0x8];
3328 	u8         congestion_level[0x8];
3329 	u8         reserved_at_18[0x8];
3330 
3331 	u8         reserved_at_20[0xa0];
3332 };
3333 
3334 struct mlx5_ifc_gpio_event_bits {
3335 	u8         reserved_at_0[0x60];
3336 
3337 	u8         gpio_event_hi[0x20];
3338 
3339 	u8         gpio_event_lo[0x20];
3340 
3341 	u8         reserved_at_a0[0x40];
3342 };
3343 
3344 struct mlx5_ifc_port_state_change_event_bits {
3345 	u8         reserved_at_0[0x40];
3346 
3347 	u8         port_num[0x4];
3348 	u8         reserved_at_44[0x1c];
3349 
3350 	u8         reserved_at_60[0x80];
3351 };
3352 
3353 struct mlx5_ifc_dropped_packet_logged_bits {
3354 	u8         reserved_at_0[0xe0];
3355 };
3356 
3357 struct mlx5_ifc_nic_cap_reg_bits {
3358 	u8	   reserved_at_0[0x1a];
3359 	u8	   vhca_icm_ctrl[0x1];
3360 	u8	   reserved_at_1b[0x5];
3361 
3362 	u8	   reserved_at_20[0x60];
3363 };
3364 
3365 struct mlx5_ifc_default_timeout_bits {
3366 	u8         to_multiplier[0x3];
3367 	u8         reserved_at_3[0x9];
3368 	u8         to_value[0x14];
3369 };
3370 
3371 struct mlx5_ifc_dtor_reg_bits {
3372 	u8         reserved_at_0[0x20];
3373 
3374 	struct mlx5_ifc_default_timeout_bits pcie_toggle_to;
3375 
3376 	u8         reserved_at_40[0x60];
3377 
3378 	struct mlx5_ifc_default_timeout_bits health_poll_to;
3379 
3380 	struct mlx5_ifc_default_timeout_bits full_crdump_to;
3381 
3382 	struct mlx5_ifc_default_timeout_bits fw_reset_to;
3383 
3384 	struct mlx5_ifc_default_timeout_bits flush_on_err_to;
3385 
3386 	struct mlx5_ifc_default_timeout_bits pci_sync_update_to;
3387 
3388 	struct mlx5_ifc_default_timeout_bits tear_down_to;
3389 
3390 	struct mlx5_ifc_default_timeout_bits fsm_reactivate_to;
3391 
3392 	struct mlx5_ifc_default_timeout_bits reclaim_pages_to;
3393 
3394 	struct mlx5_ifc_default_timeout_bits reclaim_vfs_pages_to;
3395 
3396 	struct mlx5_ifc_default_timeout_bits reset_unload_to;
3397 
3398 	u8         reserved_at_1c0[0x20];
3399 };
3400 
3401 struct mlx5_ifc_vhca_icm_ctrl_reg_bits {
3402 	u8	   vhca_id_valid[0x1];
3403 	u8	   reserved_at_1[0xf];
3404 	u8	   vhca_id[0x10];
3405 
3406 	u8	   reserved_at_20[0xa0];
3407 
3408 	u8	   cur_alloc_icm[0x20];
3409 
3410 	u8	   reserved_at_e0[0x120];
3411 };
3412 
3413 enum {
3414 	MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN                 = 0x1,
3415 	MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR  = 0x2,
3416 };
3417 
3418 struct mlx5_ifc_cq_error_bits {
3419 	u8         reserved_at_0[0x8];
3420 	u8         cqn[0x18];
3421 
3422 	u8         reserved_at_20[0x20];
3423 
3424 	u8         reserved_at_40[0x18];
3425 	u8         syndrome[0x8];
3426 
3427 	u8         reserved_at_60[0x80];
3428 };
3429 
3430 struct mlx5_ifc_rdma_page_fault_event_bits {
3431 	u8         bytes_committed[0x20];
3432 
3433 	u8         r_key[0x20];
3434 
3435 	u8         reserved_at_40[0x10];
3436 	u8         packet_len[0x10];
3437 
3438 	u8         rdma_op_len[0x20];
3439 
3440 	u8         rdma_va[0x40];
3441 
3442 	u8         reserved_at_c0[0x5];
3443 	u8         rdma[0x1];
3444 	u8         write[0x1];
3445 	u8         requestor[0x1];
3446 	u8         qp_number[0x18];
3447 };
3448 
3449 struct mlx5_ifc_wqe_associated_page_fault_event_bits {
3450 	u8         bytes_committed[0x20];
3451 
3452 	u8         reserved_at_20[0x10];
3453 	u8         wqe_index[0x10];
3454 
3455 	u8         reserved_at_40[0x10];
3456 	u8         len[0x10];
3457 
3458 	u8         reserved_at_60[0x60];
3459 
3460 	u8         reserved_at_c0[0x5];
3461 	u8         rdma[0x1];
3462 	u8         write_read[0x1];
3463 	u8         requestor[0x1];
3464 	u8         qpn[0x18];
3465 };
3466 
3467 struct mlx5_ifc_qp_events_bits {
3468 	u8         reserved_at_0[0xa0];
3469 
3470 	u8         type[0x8];
3471 	u8         reserved_at_a8[0x18];
3472 
3473 	u8         reserved_at_c0[0x8];
3474 	u8         qpn_rqn_sqn[0x18];
3475 };
3476 
3477 struct mlx5_ifc_dct_events_bits {
3478 	u8         reserved_at_0[0xc0];
3479 
3480 	u8         reserved_at_c0[0x8];
3481 	u8         dct_number[0x18];
3482 };
3483 
3484 struct mlx5_ifc_comp_event_bits {
3485 	u8         reserved_at_0[0xc0];
3486 
3487 	u8         reserved_at_c0[0x8];
3488 	u8         cq_number[0x18];
3489 };
3490 
3491 enum {
3492 	MLX5_QPC_STATE_RST        = 0x0,
3493 	MLX5_QPC_STATE_INIT       = 0x1,
3494 	MLX5_QPC_STATE_RTR        = 0x2,
3495 	MLX5_QPC_STATE_RTS        = 0x3,
3496 	MLX5_QPC_STATE_SQER       = 0x4,
3497 	MLX5_QPC_STATE_ERR        = 0x6,
3498 	MLX5_QPC_STATE_SQD        = 0x7,
3499 	MLX5_QPC_STATE_SUSPENDED  = 0x9,
3500 };
3501 
3502 enum {
3503 	MLX5_QPC_ST_RC            = 0x0,
3504 	MLX5_QPC_ST_UC            = 0x1,
3505 	MLX5_QPC_ST_UD            = 0x2,
3506 	MLX5_QPC_ST_XRC           = 0x3,
3507 	MLX5_QPC_ST_DCI           = 0x5,
3508 	MLX5_QPC_ST_QP0           = 0x7,
3509 	MLX5_QPC_ST_QP1           = 0x8,
3510 	MLX5_QPC_ST_RAW_DATAGRAM  = 0x9,
3511 	MLX5_QPC_ST_REG_UMR       = 0xc,
3512 };
3513 
3514 enum {
3515 	MLX5_QPC_PM_STATE_ARMED     = 0x0,
3516 	MLX5_QPC_PM_STATE_REARM     = 0x1,
3517 	MLX5_QPC_PM_STATE_RESERVED  = 0x2,
3518 	MLX5_QPC_PM_STATE_MIGRATED  = 0x3,
3519 };
3520 
3521 enum {
3522 	MLX5_QPC_OFFLOAD_TYPE_RNDV  = 0x1,
3523 };
3524 
3525 enum {
3526 	MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS                = 0x0,
3527 	MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT  = 0x1,
3528 };
3529 
3530 enum {
3531 	MLX5_QPC_MTU_256_BYTES        = 0x1,
3532 	MLX5_QPC_MTU_512_BYTES        = 0x2,
3533 	MLX5_QPC_MTU_1K_BYTES         = 0x3,
3534 	MLX5_QPC_MTU_2K_BYTES         = 0x4,
3535 	MLX5_QPC_MTU_4K_BYTES         = 0x5,
3536 	MLX5_QPC_MTU_RAW_ETHERNET_QP  = 0x7,
3537 };
3538 
3539 enum {
3540 	MLX5_QPC_ATOMIC_MODE_IB_SPEC     = 0x1,
3541 	MLX5_QPC_ATOMIC_MODE_ONLY_8B     = 0x2,
3542 	MLX5_QPC_ATOMIC_MODE_UP_TO_8B    = 0x3,
3543 	MLX5_QPC_ATOMIC_MODE_UP_TO_16B   = 0x4,
3544 	MLX5_QPC_ATOMIC_MODE_UP_TO_32B   = 0x5,
3545 	MLX5_QPC_ATOMIC_MODE_UP_TO_64B   = 0x6,
3546 	MLX5_QPC_ATOMIC_MODE_UP_TO_128B  = 0x7,
3547 	MLX5_QPC_ATOMIC_MODE_UP_TO_256B  = 0x8,
3548 };
3549 
3550 enum {
3551 	MLX5_QPC_CS_REQ_DISABLE    = 0x0,
3552 	MLX5_QPC_CS_REQ_UP_TO_32B  = 0x11,
3553 	MLX5_QPC_CS_REQ_UP_TO_64B  = 0x22,
3554 };
3555 
3556 enum {
3557 	MLX5_QPC_CS_RES_DISABLE    = 0x0,
3558 	MLX5_QPC_CS_RES_UP_TO_32B  = 0x1,
3559 	MLX5_QPC_CS_RES_UP_TO_64B  = 0x2,
3560 };
3561 
3562 enum {
3563 	MLX5_TIMESTAMP_FORMAT_FREE_RUNNING = 0x0,
3564 	MLX5_TIMESTAMP_FORMAT_DEFAULT      = 0x1,
3565 	MLX5_TIMESTAMP_FORMAT_REAL_TIME    = 0x2,
3566 };
3567 
3568 struct mlx5_ifc_qpc_bits {
3569 	u8         state[0x4];
3570 	u8         lag_tx_port_affinity[0x4];
3571 	u8         st[0x8];
3572 	u8         reserved_at_10[0x2];
3573 	u8	   isolate_vl_tc[0x1];
3574 	u8         pm_state[0x2];
3575 	u8         reserved_at_15[0x1];
3576 	u8         req_e2e_credit_mode[0x2];
3577 	u8         offload_type[0x4];
3578 	u8         end_padding_mode[0x2];
3579 	u8         reserved_at_1e[0x2];
3580 
3581 	u8         wq_signature[0x1];
3582 	u8         block_lb_mc[0x1];
3583 	u8         atomic_like_write_en[0x1];
3584 	u8         latency_sensitive[0x1];
3585 	u8         reserved_at_24[0x1];
3586 	u8         drain_sigerr[0x1];
3587 	u8         reserved_at_26[0x1];
3588 	u8         dp_ordering_force[0x1];
3589 	u8         pd[0x18];
3590 
3591 	u8         mtu[0x3];
3592 	u8         log_msg_max[0x5];
3593 	u8         reserved_at_48[0x1];
3594 	u8         log_rq_size[0x4];
3595 	u8         log_rq_stride[0x3];
3596 	u8         no_sq[0x1];
3597 	u8         log_sq_size[0x4];
3598 	u8         reserved_at_55[0x1];
3599 	u8	   retry_mode[0x2];
3600 	u8	   ts_format[0x2];
3601 	u8         reserved_at_5a[0x1];
3602 	u8         rlky[0x1];
3603 	u8         ulp_stateless_offload_mode[0x4];
3604 
3605 	u8         counter_set_id[0x8];
3606 	u8         uar_page[0x18];
3607 
3608 	u8         reserved_at_80[0x8];
3609 	u8         user_index[0x18];
3610 
3611 	u8         reserved_at_a0[0x3];
3612 	u8         log_page_size[0x5];
3613 	u8         remote_qpn[0x18];
3614 
3615 	struct mlx5_ifc_ads_bits primary_address_path;
3616 
3617 	struct mlx5_ifc_ads_bits secondary_address_path;
3618 
3619 	u8         log_ack_req_freq[0x4];
3620 	u8         reserved_at_384[0x4];
3621 	u8         log_sra_max[0x3];
3622 	u8         reserved_at_38b[0x2];
3623 	u8         retry_count[0x3];
3624 	u8         rnr_retry[0x3];
3625 	u8         reserved_at_393[0x1];
3626 	u8         fre[0x1];
3627 	u8         cur_rnr_retry[0x3];
3628 	u8         cur_retry_count[0x3];
3629 	u8         reserved_at_39b[0x5];
3630 
3631 	u8         reserved_at_3a0[0x20];
3632 
3633 	u8         reserved_at_3c0[0x8];
3634 	u8         next_send_psn[0x18];
3635 
3636 	u8         reserved_at_3e0[0x3];
3637 	u8	   log_num_dci_stream_channels[0x5];
3638 	u8         cqn_snd[0x18];
3639 
3640 	u8         reserved_at_400[0x3];
3641 	u8	   log_num_dci_errored_streams[0x5];
3642 	u8         deth_sqpn[0x18];
3643 
3644 	u8         reserved_at_420[0x20];
3645 
3646 	u8         reserved_at_440[0x8];
3647 	u8         last_acked_psn[0x18];
3648 
3649 	u8         reserved_at_460[0x8];
3650 	u8         ssn[0x18];
3651 
3652 	u8         reserved_at_480[0x8];
3653 	u8         log_rra_max[0x3];
3654 	u8         reserved_at_48b[0x1];
3655 	u8         atomic_mode[0x4];
3656 	u8         rre[0x1];
3657 	u8         rwe[0x1];
3658 	u8         rae[0x1];
3659 	u8         reserved_at_493[0x1];
3660 	u8         page_offset[0x6];
3661 	u8         reserved_at_49a[0x2];
3662 	u8         dp_ordering_1[0x1];
3663 	u8         cd_slave_receive[0x1];
3664 	u8         cd_slave_send[0x1];
3665 	u8         cd_master[0x1];
3666 
3667 	u8         reserved_at_4a0[0x3];
3668 	u8         min_rnr_nak[0x5];
3669 	u8         next_rcv_psn[0x18];
3670 
3671 	u8         reserved_at_4c0[0x8];
3672 	u8         xrcd[0x18];
3673 
3674 	u8         reserved_at_4e0[0x8];
3675 	u8         cqn_rcv[0x18];
3676 
3677 	u8         dbr_addr[0x40];
3678 
3679 	u8         q_key[0x20];
3680 
3681 	u8         reserved_at_560[0x5];
3682 	u8         rq_type[0x3];
3683 	u8         srqn_rmpn_xrqn[0x18];
3684 
3685 	u8         reserved_at_580[0x8];
3686 	u8         rmsn[0x18];
3687 
3688 	u8         hw_sq_wqebb_counter[0x10];
3689 	u8         sw_sq_wqebb_counter[0x10];
3690 
3691 	u8         hw_rq_counter[0x20];
3692 
3693 	u8         sw_rq_counter[0x20];
3694 
3695 	u8         reserved_at_600[0x20];
3696 
3697 	u8         reserved_at_620[0xf];
3698 	u8         cgs[0x1];
3699 	u8         cs_req[0x8];
3700 	u8         cs_res[0x8];
3701 
3702 	u8         dc_access_key[0x40];
3703 
3704 	u8         reserved_at_680[0x3];
3705 	u8         dbr_umem_valid[0x1];
3706 
3707 	u8         reserved_at_684[0xbc];
3708 };
3709 
3710 struct mlx5_ifc_roce_addr_layout_bits {
3711 	u8         source_l3_address[16][0x8];
3712 
3713 	u8         reserved_at_80[0x3];
3714 	u8         vlan_valid[0x1];
3715 	u8         vlan_id[0xc];
3716 	u8         source_mac_47_32[0x10];
3717 
3718 	u8         source_mac_31_0[0x20];
3719 
3720 	u8         reserved_at_c0[0x14];
3721 	u8         roce_l3_type[0x4];
3722 	u8         roce_version[0x8];
3723 
3724 	u8         reserved_at_e0[0x20];
3725 };
3726 
3727 struct mlx5_ifc_crypto_cap_bits {
3728 	u8    reserved_at_0[0x3];
3729 	u8    synchronize_dek[0x1];
3730 	u8    int_kek_manual[0x1];
3731 	u8    int_kek_auto[0x1];
3732 	u8    reserved_at_6[0x1a];
3733 
3734 	u8    reserved_at_20[0x3];
3735 	u8    log_dek_max_alloc[0x5];
3736 	u8    reserved_at_28[0x3];
3737 	u8    log_max_num_deks[0x5];
3738 	u8    reserved_at_30[0x10];
3739 
3740 	u8    reserved_at_40[0x20];
3741 
3742 	u8    reserved_at_60[0x3];
3743 	u8    log_dek_granularity[0x5];
3744 	u8    reserved_at_68[0x3];
3745 	u8    log_max_num_int_kek[0x5];
3746 	u8    sw_wrapped_dek[0x10];
3747 
3748 	u8    reserved_at_80[0x780];
3749 };
3750 
3751 struct mlx5_ifc_shampo_cap_bits {
3752 	u8    reserved_at_0[0x3];
3753 	u8    shampo_log_max_reservation_size[0x5];
3754 	u8    reserved_at_8[0x3];
3755 	u8    shampo_log_min_reservation_size[0x5];
3756 	u8    shampo_min_mss_size[0x10];
3757 
3758 	u8    shampo_header_split[0x1];
3759 	u8    shampo_header_split_data_merge[0x1];
3760 	u8    reserved_at_22[0x1];
3761 	u8    shampo_log_max_headers_entry_size[0x5];
3762 	u8    reserved_at_28[0x18];
3763 
3764 	u8    reserved_at_40[0x7c0];
3765 };
3766 
3767 union mlx5_ifc_hca_cap_union_bits {
3768 	struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
3769 	struct mlx5_ifc_cmd_hca_cap_2_bits cmd_hca_cap_2;
3770 	struct mlx5_ifc_odp_cap_bits odp_cap;
3771 	struct mlx5_ifc_atomic_caps_bits atomic_caps;
3772 	struct mlx5_ifc_roce_cap_bits roce_cap;
3773 	struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
3774 	struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
3775 	struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;
3776 	struct mlx5_ifc_wqe_based_flow_table_cap_bits wqe_based_flow_table_cap;
3777 	struct mlx5_ifc_esw_cap_bits esw_cap;
3778 	struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
3779 	struct mlx5_ifc_port_selection_cap_bits port_selection_cap;
3780 	struct mlx5_ifc_qos_cap_bits qos_cap;
3781 	struct mlx5_ifc_debug_cap_bits debug_cap;
3782 	struct mlx5_ifc_fpga_cap_bits fpga_cap;
3783 	struct mlx5_ifc_tls_cap_bits tls_cap;
3784 	struct mlx5_ifc_device_mem_cap_bits device_mem_cap;
3785 	struct mlx5_ifc_virtio_emulation_cap_bits virtio_emulation_cap;
3786 	struct mlx5_ifc_macsec_cap_bits macsec_cap;
3787 	struct mlx5_ifc_crypto_cap_bits crypto_cap;
3788 	struct mlx5_ifc_ipsec_cap_bits ipsec_cap;
3789 	u8         reserved_at_0[0x8000];
3790 };
3791 
3792 enum {
3793 	MLX5_FLOW_CONTEXT_ACTION_ALLOW     = 0x1,
3794 	MLX5_FLOW_CONTEXT_ACTION_DROP      = 0x2,
3795 	MLX5_FLOW_CONTEXT_ACTION_FWD_DEST  = 0x4,
3796 	MLX5_FLOW_CONTEXT_ACTION_COUNT     = 0x8,
3797 	MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT = 0x10,
3798 	MLX5_FLOW_CONTEXT_ACTION_DECAP     = 0x20,
3799 	MLX5_FLOW_CONTEXT_ACTION_MOD_HDR   = 0x40,
3800 	MLX5_FLOW_CONTEXT_ACTION_VLAN_POP  = 0x80,
3801 	MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100,
3802 	MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2  = 0x400,
3803 	MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2 = 0x800,
3804 	MLX5_FLOW_CONTEXT_ACTION_CRYPTO_DECRYPT = 0x1000,
3805 	MLX5_FLOW_CONTEXT_ACTION_CRYPTO_ENCRYPT = 0x2000,
3806 	MLX5_FLOW_CONTEXT_ACTION_EXECUTE_ASO = 0x4000,
3807 };
3808 
3809 enum {
3810 	MLX5_FLOW_CONTEXT_FLOW_SOURCE_ANY_VPORT         = 0x0,
3811 	MLX5_FLOW_CONTEXT_FLOW_SOURCE_UPLINK            = 0x1,
3812 	MLX5_FLOW_CONTEXT_FLOW_SOURCE_LOCAL_VPORT       = 0x2,
3813 };
3814 
3815 enum {
3816 	MLX5_FLOW_CONTEXT_ENCRYPT_DECRYPT_TYPE_IPSEC   = 0x0,
3817 	MLX5_FLOW_CONTEXT_ENCRYPT_DECRYPT_TYPE_MACSEC  = 0x1,
3818 };
3819 
3820 struct mlx5_ifc_vlan_bits {
3821 	u8         ethtype[0x10];
3822 	u8         prio[0x3];
3823 	u8         cfi[0x1];
3824 	u8         vid[0xc];
3825 };
3826 
3827 enum {
3828 	MLX5_FLOW_METER_COLOR_RED	= 0x0,
3829 	MLX5_FLOW_METER_COLOR_YELLOW	= 0x1,
3830 	MLX5_FLOW_METER_COLOR_GREEN	= 0x2,
3831 	MLX5_FLOW_METER_COLOR_UNDEFINED	= 0x3,
3832 };
3833 
3834 enum {
3835 	MLX5_EXE_ASO_FLOW_METER		= 0x2,
3836 };
3837 
3838 struct mlx5_ifc_exe_aso_ctrl_flow_meter_bits {
3839 	u8        return_reg_id[0x4];
3840 	u8        aso_type[0x4];
3841 	u8        reserved_at_8[0x14];
3842 	u8        action[0x1];
3843 	u8        init_color[0x2];
3844 	u8        meter_id[0x1];
3845 };
3846 
3847 union mlx5_ifc_exe_aso_ctrl {
3848 	struct mlx5_ifc_exe_aso_ctrl_flow_meter_bits exe_aso_ctrl_flow_meter;
3849 };
3850 
3851 struct mlx5_ifc_execute_aso_bits {
3852 	u8        valid[0x1];
3853 	u8        reserved_at_1[0x7];
3854 	u8        aso_object_id[0x18];
3855 
3856 	union mlx5_ifc_exe_aso_ctrl exe_aso_ctrl;
3857 };
3858 
3859 struct mlx5_ifc_flow_context_bits {
3860 	struct mlx5_ifc_vlan_bits push_vlan;
3861 
3862 	u8         group_id[0x20];
3863 
3864 	u8         reserved_at_40[0x8];
3865 	u8         flow_tag[0x18];
3866 
3867 	u8         reserved_at_60[0x10];
3868 	u8         action[0x10];
3869 
3870 	u8         extended_destination[0x1];
3871 	u8         uplink_hairpin_en[0x1];
3872 	u8         flow_source[0x2];
3873 	u8         encrypt_decrypt_type[0x4];
3874 	u8         destination_list_size[0x18];
3875 
3876 	u8         reserved_at_a0[0x8];
3877 	u8         flow_counter_list_size[0x18];
3878 
3879 	u8         packet_reformat_id[0x20];
3880 
3881 	u8         modify_header_id[0x20];
3882 
3883 	struct mlx5_ifc_vlan_bits push_vlan_2;
3884 
3885 	u8         encrypt_decrypt_obj_id[0x20];
3886 	u8         reserved_at_140[0xc0];
3887 
3888 	struct mlx5_ifc_fte_match_param_bits match_value;
3889 
3890 	struct mlx5_ifc_execute_aso_bits execute_aso[4];
3891 
3892 	u8         reserved_at_1300[0x500];
3893 
3894 	union mlx5_ifc_dest_format_flow_counter_list_auto_bits destination[];
3895 };
3896 
3897 enum {
3898 	MLX5_XRC_SRQC_STATE_GOOD   = 0x0,
3899 	MLX5_XRC_SRQC_STATE_ERROR  = 0x1,
3900 };
3901 
3902 struct mlx5_ifc_xrc_srqc_bits {
3903 	u8         state[0x4];
3904 	u8         log_xrc_srq_size[0x4];
3905 	u8         reserved_at_8[0x18];
3906 
3907 	u8         wq_signature[0x1];
3908 	u8         cont_srq[0x1];
3909 	u8         reserved_at_22[0x1];
3910 	u8         rlky[0x1];
3911 	u8         basic_cyclic_rcv_wqe[0x1];
3912 	u8         log_rq_stride[0x3];
3913 	u8         xrcd[0x18];
3914 
3915 	u8         page_offset[0x6];
3916 	u8         reserved_at_46[0x1];
3917 	u8         dbr_umem_valid[0x1];
3918 	u8         cqn[0x18];
3919 
3920 	u8         reserved_at_60[0x20];
3921 
3922 	u8         user_index_equal_xrc_srqn[0x1];
3923 	u8         reserved_at_81[0x1];
3924 	u8         log_page_size[0x6];
3925 	u8         user_index[0x18];
3926 
3927 	u8         reserved_at_a0[0x20];
3928 
3929 	u8         reserved_at_c0[0x8];
3930 	u8         pd[0x18];
3931 
3932 	u8         lwm[0x10];
3933 	u8         wqe_cnt[0x10];
3934 
3935 	u8         reserved_at_100[0x40];
3936 
3937 	u8         db_record_addr_h[0x20];
3938 
3939 	u8         db_record_addr_l[0x1e];
3940 	u8         reserved_at_17e[0x2];
3941 
3942 	u8         reserved_at_180[0x80];
3943 };
3944 
3945 struct mlx5_ifc_vnic_diagnostic_statistics_bits {
3946 	u8         counter_error_queues[0x20];
3947 
3948 	u8         total_error_queues[0x20];
3949 
3950 	u8         send_queue_priority_update_flow[0x20];
3951 
3952 	u8         reserved_at_60[0x20];
3953 
3954 	u8         nic_receive_steering_discard[0x40];
3955 
3956 	u8         receive_discard_vport_down[0x40];
3957 
3958 	u8         transmit_discard_vport_down[0x40];
3959 
3960 	u8         async_eq_overrun[0x20];
3961 
3962 	u8         comp_eq_overrun[0x20];
3963 
3964 	u8         reserved_at_180[0x20];
3965 
3966 	u8         invalid_command[0x20];
3967 
3968 	u8         quota_exceeded_command[0x20];
3969 
3970 	u8         internal_rq_out_of_buffer[0x20];
3971 
3972 	u8         cq_overrun[0x20];
3973 
3974 	u8         eth_wqe_too_small[0x20];
3975 
3976 	u8         reserved_at_220[0xc0];
3977 
3978 	u8         generated_pkt_steering_fail[0x40];
3979 
3980 	u8         handled_pkt_steering_fail[0x40];
3981 
3982 	u8         reserved_at_360[0xc80];
3983 };
3984 
3985 struct mlx5_ifc_traffic_counter_bits {
3986 	u8         packets[0x40];
3987 
3988 	u8         octets[0x40];
3989 };
3990 
3991 struct mlx5_ifc_tisc_bits {
3992 	u8         strict_lag_tx_port_affinity[0x1];
3993 	u8         tls_en[0x1];
3994 	u8         reserved_at_2[0x2];
3995 	u8         lag_tx_port_affinity[0x04];
3996 
3997 	u8         reserved_at_8[0x4];
3998 	u8         prio[0x4];
3999 	u8         reserved_at_10[0x10];
4000 
4001 	u8         reserved_at_20[0x100];
4002 
4003 	u8         reserved_at_120[0x8];
4004 	u8         transport_domain[0x18];
4005 
4006 	u8         reserved_at_140[0x8];
4007 	u8         underlay_qpn[0x18];
4008 
4009 	u8         reserved_at_160[0x8];
4010 	u8         pd[0x18];
4011 
4012 	u8         reserved_at_180[0x380];
4013 };
4014 
4015 enum {
4016 	MLX5_TIRC_DISP_TYPE_DIRECT    = 0x0,
4017 	MLX5_TIRC_DISP_TYPE_INDIRECT  = 0x1,
4018 };
4019 
4020 enum {
4021 	MLX5_TIRC_PACKET_MERGE_MASK_IPV4_LRO  = BIT(0),
4022 	MLX5_TIRC_PACKET_MERGE_MASK_IPV6_LRO  = BIT(1),
4023 };
4024 
4025 enum {
4026 	MLX5_RX_HASH_FN_NONE           = 0x0,
4027 	MLX5_RX_HASH_FN_INVERTED_XOR8  = 0x1,
4028 	MLX5_RX_HASH_FN_TOEPLITZ       = 0x2,
4029 };
4030 
4031 enum {
4032 	MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST    = 0x1,
4033 	MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST  = 0x2,
4034 };
4035 
4036 struct mlx5_ifc_tirc_bits {
4037 	u8         reserved_at_0[0x20];
4038 
4039 	u8         disp_type[0x4];
4040 	u8         tls_en[0x1];
4041 	u8         reserved_at_25[0x1b];
4042 
4043 	u8         reserved_at_40[0x40];
4044 
4045 	u8         reserved_at_80[0x4];
4046 	u8         lro_timeout_period_usecs[0x10];
4047 	u8         packet_merge_mask[0x4];
4048 	u8         lro_max_ip_payload_size[0x8];
4049 
4050 	u8         reserved_at_a0[0x40];
4051 
4052 	u8         reserved_at_e0[0x8];
4053 	u8         inline_rqn[0x18];
4054 
4055 	u8         rx_hash_symmetric[0x1];
4056 	u8         reserved_at_101[0x1];
4057 	u8         tunneled_offload_en[0x1];
4058 	u8         reserved_at_103[0x5];
4059 	u8         indirect_table[0x18];
4060 
4061 	u8         rx_hash_fn[0x4];
4062 	u8         reserved_at_124[0x2];
4063 	u8         self_lb_block[0x2];
4064 	u8         transport_domain[0x18];
4065 
4066 	u8         rx_hash_toeplitz_key[10][0x20];
4067 
4068 	struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
4069 
4070 	struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
4071 
4072 	u8         reserved_at_2c0[0x4c0];
4073 };
4074 
4075 enum {
4076 	MLX5_SRQC_STATE_GOOD   = 0x0,
4077 	MLX5_SRQC_STATE_ERROR  = 0x1,
4078 };
4079 
4080 struct mlx5_ifc_srqc_bits {
4081 	u8         state[0x4];
4082 	u8         log_srq_size[0x4];
4083 	u8         reserved_at_8[0x18];
4084 
4085 	u8         wq_signature[0x1];
4086 	u8         cont_srq[0x1];
4087 	u8         reserved_at_22[0x1];
4088 	u8         rlky[0x1];
4089 	u8         reserved_at_24[0x1];
4090 	u8         log_rq_stride[0x3];
4091 	u8         xrcd[0x18];
4092 
4093 	u8         page_offset[0x6];
4094 	u8         reserved_at_46[0x2];
4095 	u8         cqn[0x18];
4096 
4097 	u8         reserved_at_60[0x20];
4098 
4099 	u8         reserved_at_80[0x2];
4100 	u8         log_page_size[0x6];
4101 	u8         reserved_at_88[0x18];
4102 
4103 	u8         reserved_at_a0[0x20];
4104 
4105 	u8         reserved_at_c0[0x8];
4106 	u8         pd[0x18];
4107 
4108 	u8         lwm[0x10];
4109 	u8         wqe_cnt[0x10];
4110 
4111 	u8         reserved_at_100[0x40];
4112 
4113 	u8         dbr_addr[0x40];
4114 
4115 	u8         reserved_at_180[0x80];
4116 };
4117 
4118 enum {
4119 	MLX5_SQC_STATE_RST  = 0x0,
4120 	MLX5_SQC_STATE_RDY  = 0x1,
4121 	MLX5_SQC_STATE_ERR  = 0x3,
4122 };
4123 
4124 struct mlx5_ifc_sqc_bits {
4125 	u8         rlky[0x1];
4126 	u8         cd_master[0x1];
4127 	u8         fre[0x1];
4128 	u8         flush_in_error_en[0x1];
4129 	u8         allow_multi_pkt_send_wqe[0x1];
4130 	u8	   min_wqe_inline_mode[0x3];
4131 	u8         state[0x4];
4132 	u8         reg_umr[0x1];
4133 	u8         allow_swp[0x1];
4134 	u8         hairpin[0x1];
4135 	u8         non_wire[0x1];
4136 	u8         reserved_at_10[0xa];
4137 	u8	   ts_format[0x2];
4138 	u8	   reserved_at_1c[0x4];
4139 
4140 	u8         reserved_at_20[0x8];
4141 	u8         user_index[0x18];
4142 
4143 	u8         reserved_at_40[0x8];
4144 	u8         cqn[0x18];
4145 
4146 	u8         reserved_at_60[0x8];
4147 	u8         hairpin_peer_rq[0x18];
4148 
4149 	u8         reserved_at_80[0x10];
4150 	u8         hairpin_peer_vhca[0x10];
4151 
4152 	u8         reserved_at_a0[0x20];
4153 
4154 	u8         reserved_at_c0[0x8];
4155 	u8         ts_cqe_to_dest_cqn[0x18];
4156 
4157 	u8         reserved_at_e0[0x10];
4158 	u8         packet_pacing_rate_limit_index[0x10];
4159 	u8         tis_lst_sz[0x10];
4160 	u8         qos_queue_group_id[0x10];
4161 
4162 	u8         reserved_at_120[0x40];
4163 
4164 	u8         reserved_at_160[0x8];
4165 	u8         tis_num_0[0x18];
4166 
4167 	struct mlx5_ifc_wq_bits wq;
4168 };
4169 
4170 enum {
4171 	SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0,
4172 	SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1,
4173 	SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2,
4174 	SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3,
4175 	SCHEDULING_CONTEXT_ELEMENT_TYPE_QUEUE_GROUP = 0x4,
4176 	SCHEDULING_CONTEXT_ELEMENT_TYPE_RATE_LIMIT = 0x5,
4177 };
4178 
4179 enum {
4180 	ELEMENT_TYPE_CAP_MASK_TSAR		= 1 << 0,
4181 	ELEMENT_TYPE_CAP_MASK_VPORT		= 1 << 1,
4182 	ELEMENT_TYPE_CAP_MASK_VPORT_TC		= 1 << 2,
4183 	ELEMENT_TYPE_CAP_MASK_PARA_VPORT_TC	= 1 << 3,
4184 	ELEMENT_TYPE_CAP_MASK_QUEUE_GROUP	= 1 << 4,
4185 	ELEMENT_TYPE_CAP_MASK_RATE_LIMIT	= 1 << 5,
4186 };
4187 
4188 enum {
4189 	TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0,
4190 	TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1,
4191 	TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2,
4192 	TSAR_ELEMENT_TSAR_TYPE_TC_ARB = 0x3,
4193 };
4194 
4195 enum {
4196 	TSAR_TYPE_CAP_MASK_DWRR		= 1 << 0,
4197 	TSAR_TYPE_CAP_MASK_ROUND_ROBIN	= 1 << 1,
4198 	TSAR_TYPE_CAP_MASK_ETS		= 1 << 2,
4199 	TSAR_TYPE_CAP_MASK_TC_ARB       = 1 << 3,
4200 };
4201 
4202 struct mlx5_ifc_tsar_element_bits {
4203 	u8         traffic_class[0x4];
4204 	u8         reserved_at_4[0x4];
4205 	u8         tsar_type[0x8];
4206 	u8         reserved_at_10[0x10];
4207 };
4208 
4209 struct mlx5_ifc_vport_element_bits {
4210 	u8         reserved_at_0[0x4];
4211 	u8         eswitch_owner_vhca_id_valid[0x1];
4212 	u8         eswitch_owner_vhca_id[0xb];
4213 	u8         vport_number[0x10];
4214 };
4215 
4216 struct mlx5_ifc_vport_tc_element_bits {
4217 	u8         traffic_class[0x4];
4218 	u8         eswitch_owner_vhca_id_valid[0x1];
4219 	u8         eswitch_owner_vhca_id[0xb];
4220 	u8         vport_number[0x10];
4221 };
4222 
4223 union mlx5_ifc_element_attributes_bits {
4224 	struct mlx5_ifc_tsar_element_bits tsar;
4225 	struct mlx5_ifc_vport_element_bits vport;
4226 	struct mlx5_ifc_vport_tc_element_bits vport_tc;
4227 	u8 reserved_at_0[0x20];
4228 };
4229 
4230 struct mlx5_ifc_scheduling_context_bits {
4231 	u8         element_type[0x8];
4232 	u8         reserved_at_8[0x18];
4233 
4234 	union mlx5_ifc_element_attributes_bits element_attributes;
4235 
4236 	u8         parent_element_id[0x20];
4237 
4238 	u8         reserved_at_60[0x40];
4239 
4240 	u8         bw_share[0x20];
4241 
4242 	u8         max_average_bw[0x20];
4243 
4244 	u8         max_bw_obj_id[0x20];
4245 
4246 	u8         reserved_at_100[0x100];
4247 };
4248 
4249 struct mlx5_ifc_rqtc_bits {
4250 	u8    reserved_at_0[0xa0];
4251 
4252 	u8    reserved_at_a0[0x5];
4253 	u8    list_q_type[0x3];
4254 	u8    reserved_at_a8[0x8];
4255 	u8    rqt_max_size[0x10];
4256 
4257 	u8    rq_vhca_id_format[0x1];
4258 	u8    reserved_at_c1[0xf];
4259 	u8    rqt_actual_size[0x10];
4260 
4261 	u8    reserved_at_e0[0x6a0];
4262 
4263 	union {
4264 		DECLARE_FLEX_ARRAY(struct mlx5_ifc_rq_num_bits, rq_num);
4265 		DECLARE_FLEX_ARRAY(struct mlx5_ifc_rq_vhca_bits, rq_vhca);
4266 	};
4267 };
4268 
4269 enum {
4270 	MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE  = 0x0,
4271 	MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP     = 0x1,
4272 };
4273 
4274 enum {
4275 	MLX5_RQC_STATE_RST  = 0x0,
4276 	MLX5_RQC_STATE_RDY  = 0x1,
4277 	MLX5_RQC_STATE_ERR  = 0x3,
4278 };
4279 
4280 enum {
4281 	MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_BYTE    = 0x0,
4282 	MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_STRIDE  = 0x1,
4283 	MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_PAGE    = 0x2,
4284 };
4285 
4286 enum {
4287 	MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_NO_MATCH    = 0x0,
4288 	MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_EXTENDED    = 0x1,
4289 	MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_FIVE_TUPLE  = 0x2,
4290 };
4291 
4292 struct mlx5_ifc_rqc_bits {
4293 	u8         rlky[0x1];
4294 	u8	   delay_drop_en[0x1];
4295 	u8         scatter_fcs[0x1];
4296 	u8         vsd[0x1];
4297 	u8         mem_rq_type[0x4];
4298 	u8         state[0x4];
4299 	u8         reserved_at_c[0x1];
4300 	u8         flush_in_error_en[0x1];
4301 	u8         hairpin[0x1];
4302 	u8         reserved_at_f[0xb];
4303 	u8	   ts_format[0x2];
4304 	u8	   reserved_at_1c[0x4];
4305 
4306 	u8         reserved_at_20[0x8];
4307 	u8         user_index[0x18];
4308 
4309 	u8         reserved_at_40[0x8];
4310 	u8         cqn[0x18];
4311 
4312 	u8         counter_set_id[0x8];
4313 	u8         reserved_at_68[0x18];
4314 
4315 	u8         reserved_at_80[0x8];
4316 	u8         rmpn[0x18];
4317 
4318 	u8         reserved_at_a0[0x8];
4319 	u8         hairpin_peer_sq[0x18];
4320 
4321 	u8         reserved_at_c0[0x10];
4322 	u8         hairpin_peer_vhca[0x10];
4323 
4324 	u8         reserved_at_e0[0x46];
4325 	u8         shampo_no_match_alignment_granularity[0x2];
4326 	u8         reserved_at_128[0x6];
4327 	u8         shampo_match_criteria_type[0x2];
4328 	u8         reservation_timeout[0x10];
4329 
4330 	u8         reserved_at_140[0x40];
4331 
4332 	struct mlx5_ifc_wq_bits wq;
4333 };
4334 
4335 enum {
4336 	MLX5_RMPC_STATE_RDY  = 0x1,
4337 	MLX5_RMPC_STATE_ERR  = 0x3,
4338 };
4339 
4340 struct mlx5_ifc_rmpc_bits {
4341 	u8         reserved_at_0[0x8];
4342 	u8         state[0x4];
4343 	u8         reserved_at_c[0x14];
4344 
4345 	u8         basic_cyclic_rcv_wqe[0x1];
4346 	u8         reserved_at_21[0x1f];
4347 
4348 	u8         reserved_at_40[0x140];
4349 
4350 	struct mlx5_ifc_wq_bits wq;
4351 };
4352 
4353 enum {
4354 	VHCA_ID_TYPE_HW = 0,
4355 	VHCA_ID_TYPE_SW = 1,
4356 };
4357 
4358 struct mlx5_ifc_nic_vport_context_bits {
4359 	u8         reserved_at_0[0x5];
4360 	u8         min_wqe_inline_mode[0x3];
4361 	u8         reserved_at_8[0x15];
4362 	u8         disable_mc_local_lb[0x1];
4363 	u8         disable_uc_local_lb[0x1];
4364 	u8         roce_en[0x1];
4365 
4366 	u8         arm_change_event[0x1];
4367 	u8         reserved_at_21[0x1a];
4368 	u8         event_on_mtu[0x1];
4369 	u8         event_on_promisc_change[0x1];
4370 	u8         event_on_vlan_change[0x1];
4371 	u8         event_on_mc_address_change[0x1];
4372 	u8         event_on_uc_address_change[0x1];
4373 
4374 	u8         vhca_id_type[0x1];
4375 	u8         reserved_at_41[0xb];
4376 	u8	   affiliation_criteria[0x4];
4377 	u8	   affiliated_vhca_id[0x10];
4378 
4379 	u8	   reserved_at_60[0xa0];
4380 
4381 	u8	   reserved_at_100[0x1];
4382 	u8         sd_group[0x3];
4383 	u8	   reserved_at_104[0x1c];
4384 
4385 	u8	   reserved_at_120[0x10];
4386 	u8         mtu[0x10];
4387 
4388 	u8         system_image_guid[0x40];
4389 	u8         port_guid[0x40];
4390 	u8         node_guid[0x40];
4391 
4392 	u8         reserved_at_200[0x140];
4393 	u8         qkey_violation_counter[0x10];
4394 	u8         reserved_at_350[0x430];
4395 
4396 	u8         promisc_uc[0x1];
4397 	u8         promisc_mc[0x1];
4398 	u8         promisc_all[0x1];
4399 	u8         reserved_at_783[0x2];
4400 	u8         allowed_list_type[0x3];
4401 	u8         reserved_at_788[0xc];
4402 	u8         allowed_list_size[0xc];
4403 
4404 	struct mlx5_ifc_mac_address_layout_bits permanent_address;
4405 
4406 	u8         reserved_at_7e0[0x20];
4407 
4408 	u8         current_uc_mac_address[][0x40];
4409 };
4410 
4411 enum {
4412 	MLX5_MKC_ACCESS_MODE_PA    = 0x0,
4413 	MLX5_MKC_ACCESS_MODE_MTT   = 0x1,
4414 	MLX5_MKC_ACCESS_MODE_KLMS  = 0x2,
4415 	MLX5_MKC_ACCESS_MODE_KSM   = 0x3,
4416 	MLX5_MKC_ACCESS_MODE_SW_ICM = 0x4,
4417 	MLX5_MKC_ACCESS_MODE_MEMIC = 0x5,
4418 	MLX5_MKC_ACCESS_MODE_CROSSING = 0x6,
4419 };
4420 
4421 struct mlx5_ifc_mkc_bits {
4422 	u8         reserved_at_0[0x1];
4423 	u8         free[0x1];
4424 	u8         reserved_at_2[0x1];
4425 	u8         access_mode_4_2[0x3];
4426 	u8         reserved_at_6[0x7];
4427 	u8         relaxed_ordering_write[0x1];
4428 	u8         reserved_at_e[0x1];
4429 	u8         small_fence_on_rdma_read_response[0x1];
4430 	u8         umr_en[0x1];
4431 	u8         a[0x1];
4432 	u8         rw[0x1];
4433 	u8         rr[0x1];
4434 	u8         lw[0x1];
4435 	u8         lr[0x1];
4436 	u8         access_mode_1_0[0x2];
4437 	u8         reserved_at_18[0x2];
4438 	u8         ma_translation_mode[0x2];
4439 	u8         reserved_at_1c[0x4];
4440 
4441 	u8         qpn[0x18];
4442 	u8         mkey_7_0[0x8];
4443 
4444 	u8         reserved_at_40[0x20];
4445 
4446 	u8         length64[0x1];
4447 	u8         bsf_en[0x1];
4448 	u8         sync_umr[0x1];
4449 	u8         reserved_at_63[0x2];
4450 	u8         expected_sigerr_count[0x1];
4451 	u8         reserved_at_66[0x1];
4452 	u8         en_rinval[0x1];
4453 	u8         pd[0x18];
4454 
4455 	u8         start_addr[0x40];
4456 
4457 	u8         len[0x40];
4458 
4459 	u8         bsf_octword_size[0x20];
4460 
4461 	u8         reserved_at_120[0x60];
4462 
4463 	u8         crossing_target_vhca_id[0x10];
4464 	u8         reserved_at_190[0x10];
4465 
4466 	u8         translations_octword_size[0x20];
4467 
4468 	u8         reserved_at_1c0[0x19];
4469 	u8         relaxed_ordering_read[0x1];
4470 	u8         log_page_size[0x6];
4471 
4472 	u8         reserved_at_1e0[0x20];
4473 };
4474 
4475 struct mlx5_ifc_pkey_bits {
4476 	u8         reserved_at_0[0x10];
4477 	u8         pkey[0x10];
4478 };
4479 
4480 struct mlx5_ifc_array128_auto_bits {
4481 	u8         array128_auto[16][0x8];
4482 };
4483 
4484 struct mlx5_ifc_hca_vport_context_bits {
4485 	u8         field_select[0x20];
4486 
4487 	u8         reserved_at_20[0xe0];
4488 
4489 	u8         sm_virt_aware[0x1];
4490 	u8         has_smi[0x1];
4491 	u8         has_raw[0x1];
4492 	u8         grh_required[0x1];
4493 	u8         reserved_at_104[0x4];
4494 	u8         num_port_plane[0x8];
4495 	u8         port_physical_state[0x4];
4496 	u8         vport_state_policy[0x4];
4497 	u8         port_state[0x4];
4498 	u8         vport_state[0x4];
4499 
4500 	u8         reserved_at_120[0x20];
4501 
4502 	u8         system_image_guid[0x40];
4503 
4504 	u8         port_guid[0x40];
4505 
4506 	u8         node_guid[0x40];
4507 
4508 	u8         cap_mask1[0x20];
4509 
4510 	u8         cap_mask1_field_select[0x20];
4511 
4512 	u8         cap_mask2[0x20];
4513 
4514 	u8         cap_mask2_field_select[0x20];
4515 
4516 	u8         reserved_at_280[0x80];
4517 
4518 	u8         lid[0x10];
4519 	u8         reserved_at_310[0x4];
4520 	u8         init_type_reply[0x4];
4521 	u8         lmc[0x3];
4522 	u8         subnet_timeout[0x5];
4523 
4524 	u8         sm_lid[0x10];
4525 	u8         sm_sl[0x4];
4526 	u8         reserved_at_334[0xc];
4527 
4528 	u8         qkey_violation_counter[0x10];
4529 	u8         pkey_violation_counter[0x10];
4530 
4531 	u8         reserved_at_360[0xca0];
4532 };
4533 
4534 struct mlx5_ifc_esw_vport_context_bits {
4535 	u8         fdb_to_vport_reg_c[0x1];
4536 	u8         reserved_at_1[0x2];
4537 	u8         vport_svlan_strip[0x1];
4538 	u8         vport_cvlan_strip[0x1];
4539 	u8         vport_svlan_insert[0x1];
4540 	u8         vport_cvlan_insert[0x2];
4541 	u8         fdb_to_vport_reg_c_id[0x8];
4542 	u8         reserved_at_10[0x10];
4543 
4544 	u8         reserved_at_20[0x20];
4545 
4546 	u8         svlan_cfi[0x1];
4547 	u8         svlan_pcp[0x3];
4548 	u8         svlan_id[0xc];
4549 	u8         cvlan_cfi[0x1];
4550 	u8         cvlan_pcp[0x3];
4551 	u8         cvlan_id[0xc];
4552 
4553 	u8         reserved_at_60[0x720];
4554 
4555 	u8         sw_steering_vport_icm_address_rx[0x40];
4556 
4557 	u8         sw_steering_vport_icm_address_tx[0x40];
4558 };
4559 
4560 enum {
4561 	MLX5_EQC_STATUS_OK                = 0x0,
4562 	MLX5_EQC_STATUS_EQ_WRITE_FAILURE  = 0xa,
4563 };
4564 
4565 enum {
4566 	MLX5_EQC_ST_ARMED  = 0x9,
4567 	MLX5_EQC_ST_FIRED  = 0xa,
4568 };
4569 
4570 struct mlx5_ifc_eqc_bits {
4571 	u8         status[0x4];
4572 	u8         reserved_at_4[0x9];
4573 	u8         ec[0x1];
4574 	u8         oi[0x1];
4575 	u8         reserved_at_f[0x5];
4576 	u8         st[0x4];
4577 	u8         reserved_at_18[0x8];
4578 
4579 	u8         reserved_at_20[0x20];
4580 
4581 	u8         reserved_at_40[0x14];
4582 	u8         page_offset[0x6];
4583 	u8         reserved_at_5a[0x6];
4584 
4585 	u8         reserved_at_60[0x3];
4586 	u8         log_eq_size[0x5];
4587 	u8         uar_page[0x18];
4588 
4589 	u8         reserved_at_80[0x20];
4590 
4591 	u8         reserved_at_a0[0x14];
4592 	u8         intr[0xc];
4593 
4594 	u8         reserved_at_c0[0x3];
4595 	u8         log_page_size[0x5];
4596 	u8         reserved_at_c8[0x18];
4597 
4598 	u8         reserved_at_e0[0x60];
4599 
4600 	u8         reserved_at_140[0x8];
4601 	u8         consumer_counter[0x18];
4602 
4603 	u8         reserved_at_160[0x8];
4604 	u8         producer_counter[0x18];
4605 
4606 	u8         reserved_at_180[0x80];
4607 };
4608 
4609 enum {
4610 	MLX5_DCTC_STATE_ACTIVE    = 0x0,
4611 	MLX5_DCTC_STATE_DRAINING  = 0x1,
4612 	MLX5_DCTC_STATE_DRAINED   = 0x2,
4613 };
4614 
4615 enum {
4616 	MLX5_DCTC_CS_RES_DISABLE    = 0x0,
4617 	MLX5_DCTC_CS_RES_NA         = 0x1,
4618 	MLX5_DCTC_CS_RES_UP_TO_64B  = 0x2,
4619 };
4620 
4621 enum {
4622 	MLX5_DCTC_MTU_256_BYTES  = 0x1,
4623 	MLX5_DCTC_MTU_512_BYTES  = 0x2,
4624 	MLX5_DCTC_MTU_1K_BYTES   = 0x3,
4625 	MLX5_DCTC_MTU_2K_BYTES   = 0x4,
4626 	MLX5_DCTC_MTU_4K_BYTES   = 0x5,
4627 };
4628 
4629 struct mlx5_ifc_dctc_bits {
4630 	u8         reserved_at_0[0x4];
4631 	u8         state[0x4];
4632 	u8         reserved_at_8[0x18];
4633 
4634 	u8         reserved_at_20[0x7];
4635 	u8         dp_ordering_force[0x1];
4636 	u8         user_index[0x18];
4637 
4638 	u8         reserved_at_40[0x8];
4639 	u8         cqn[0x18];
4640 
4641 	u8         counter_set_id[0x8];
4642 	u8         atomic_mode[0x4];
4643 	u8         rre[0x1];
4644 	u8         rwe[0x1];
4645 	u8         rae[0x1];
4646 	u8         atomic_like_write_en[0x1];
4647 	u8         latency_sensitive[0x1];
4648 	u8         rlky[0x1];
4649 	u8         free_ar[0x1];
4650 	u8         reserved_at_73[0x1];
4651 	u8         dp_ordering_1[0x1];
4652 	u8         reserved_at_75[0xb];
4653 
4654 	u8         reserved_at_80[0x8];
4655 	u8         cs_res[0x8];
4656 	u8         reserved_at_90[0x3];
4657 	u8         min_rnr_nak[0x5];
4658 	u8         reserved_at_98[0x8];
4659 
4660 	u8         reserved_at_a0[0x8];
4661 	u8         srqn_xrqn[0x18];
4662 
4663 	u8         reserved_at_c0[0x8];
4664 	u8         pd[0x18];
4665 
4666 	u8         tclass[0x8];
4667 	u8         reserved_at_e8[0x4];
4668 	u8         flow_label[0x14];
4669 
4670 	u8         dc_access_key[0x40];
4671 
4672 	u8         reserved_at_140[0x5];
4673 	u8         mtu[0x3];
4674 	u8         port[0x8];
4675 	u8         pkey_index[0x10];
4676 
4677 	u8         reserved_at_160[0x8];
4678 	u8         my_addr_index[0x8];
4679 	u8         reserved_at_170[0x8];
4680 	u8         hop_limit[0x8];
4681 
4682 	u8         dc_access_key_violation_count[0x20];
4683 
4684 	u8         reserved_at_1a0[0x14];
4685 	u8         dei_cfi[0x1];
4686 	u8         eth_prio[0x3];
4687 	u8         ecn[0x2];
4688 	u8         dscp[0x6];
4689 
4690 	u8         reserved_at_1c0[0x20];
4691 	u8         ece[0x20];
4692 };
4693 
4694 enum {
4695 	MLX5_CQC_STATUS_OK             = 0x0,
4696 	MLX5_CQC_STATUS_CQ_OVERFLOW    = 0x9,
4697 	MLX5_CQC_STATUS_CQ_WRITE_FAIL  = 0xa,
4698 };
4699 
4700 enum {
4701 	MLX5_CQC_CQE_SZ_64_BYTES   = 0x0,
4702 	MLX5_CQC_CQE_SZ_128_BYTES  = 0x1,
4703 };
4704 
4705 enum {
4706 	MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED  = 0x6,
4707 	MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED            = 0x9,
4708 	MLX5_CQC_ST_FIRED                                 = 0xa,
4709 };
4710 
4711 enum mlx5_cq_period_mode {
4712 	MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0,
4713 	MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1,
4714 	MLX5_CQ_PERIOD_NUM_MODES,
4715 };
4716 
4717 struct mlx5_ifc_cqc_bits {
4718 	u8         status[0x4];
4719 	u8         reserved_at_4[0x2];
4720 	u8         dbr_umem_valid[0x1];
4721 	u8         apu_cq[0x1];
4722 	u8         cqe_sz[0x3];
4723 	u8         cc[0x1];
4724 	u8         reserved_at_c[0x1];
4725 	u8         scqe_break_moderation_en[0x1];
4726 	u8         oi[0x1];
4727 	u8         cq_period_mode[0x2];
4728 	u8         cqe_comp_en[0x1];
4729 	u8         mini_cqe_res_format[0x2];
4730 	u8         st[0x4];
4731 	u8         reserved_at_18[0x6];
4732 	u8         cqe_compression_layout[0x2];
4733 
4734 	u8         reserved_at_20[0x20];
4735 
4736 	u8         reserved_at_40[0x14];
4737 	u8         page_offset[0x6];
4738 	u8         reserved_at_5a[0x6];
4739 
4740 	u8         reserved_at_60[0x3];
4741 	u8         log_cq_size[0x5];
4742 	u8         uar_page[0x18];
4743 
4744 	u8         reserved_at_80[0x4];
4745 	u8         cq_period[0xc];
4746 	u8         cq_max_count[0x10];
4747 
4748 	u8         c_eqn_or_apu_element[0x20];
4749 
4750 	u8         reserved_at_c0[0x3];
4751 	u8         log_page_size[0x5];
4752 	u8         reserved_at_c8[0x18];
4753 
4754 	u8         reserved_at_e0[0x20];
4755 
4756 	u8         reserved_at_100[0x8];
4757 	u8         last_notified_index[0x18];
4758 
4759 	u8         reserved_at_120[0x8];
4760 	u8         last_solicit_index[0x18];
4761 
4762 	u8         reserved_at_140[0x8];
4763 	u8         consumer_counter[0x18];
4764 
4765 	u8         reserved_at_160[0x8];
4766 	u8         producer_counter[0x18];
4767 
4768 	u8         reserved_at_180[0x40];
4769 
4770 	u8         dbr_addr[0x40];
4771 };
4772 
4773 union mlx5_ifc_cong_control_roce_ecn_auto_bits {
4774 	struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
4775 	struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
4776 	struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
4777 	struct mlx5_ifc_cong_control_r_roce_general_bits cong_control_r_roce_general;
4778 	u8         reserved_at_0[0x800];
4779 };
4780 
4781 struct mlx5_ifc_query_adapter_param_block_bits {
4782 	u8         reserved_at_0[0xc0];
4783 
4784 	u8         reserved_at_c0[0x8];
4785 	u8         ieee_vendor_id[0x18];
4786 
4787 	u8         reserved_at_e0[0x10];
4788 	u8         vsd_vendor_id[0x10];
4789 
4790 	u8         vsd[208][0x8];
4791 
4792 	u8         vsd_contd_psid[16][0x8];
4793 };
4794 
4795 enum {
4796 	MLX5_XRQC_STATE_GOOD   = 0x0,
4797 	MLX5_XRQC_STATE_ERROR  = 0x1,
4798 };
4799 
4800 enum {
4801 	MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0,
4802 	MLX5_XRQC_TOPOLOGY_TAG_MATCHING        = 0x1,
4803 };
4804 
4805 enum {
4806 	MLX5_XRQC_OFFLOAD_RNDV = 0x1,
4807 };
4808 
4809 struct mlx5_ifc_tag_matching_topology_context_bits {
4810 	u8         log_matching_list_sz[0x4];
4811 	u8         reserved_at_4[0xc];
4812 	u8         append_next_index[0x10];
4813 
4814 	u8         sw_phase_cnt[0x10];
4815 	u8         hw_phase_cnt[0x10];
4816 
4817 	u8         reserved_at_40[0x40];
4818 };
4819 
4820 struct mlx5_ifc_xrqc_bits {
4821 	u8         state[0x4];
4822 	u8         rlkey[0x1];
4823 	u8         reserved_at_5[0xf];
4824 	u8         topology[0x4];
4825 	u8         reserved_at_18[0x4];
4826 	u8         offload[0x4];
4827 
4828 	u8         reserved_at_20[0x8];
4829 	u8         user_index[0x18];
4830 
4831 	u8         reserved_at_40[0x8];
4832 	u8         cqn[0x18];
4833 
4834 	u8         reserved_at_60[0xa0];
4835 
4836 	struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context;
4837 
4838 	u8         reserved_at_180[0x280];
4839 
4840 	struct mlx5_ifc_wq_bits wq;
4841 };
4842 
4843 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
4844 	struct mlx5_ifc_modify_field_select_bits modify_field_select;
4845 	struct mlx5_ifc_resize_field_select_bits resize_field_select;
4846 	u8         reserved_at_0[0x20];
4847 };
4848 
4849 union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
4850 	struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
4851 	struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
4852 	struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
4853 	u8         reserved_at_0[0x20];
4854 };
4855 
4856 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
4857 	struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
4858 	struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
4859 	struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
4860 	struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
4861 	struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
4862 	struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
4863 	struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout;
4864 	struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout;
4865 	struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
4866 	struct mlx5_ifc_ib_ext_port_cntrs_grp_data_layout_bits ib_ext_port_cntrs_grp_data_layout;
4867 	struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
4868 	struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs;
4869 	struct mlx5_ifc_phys_layer_recovery_cntrs_bits phys_layer_recovery_cntrs;
4870 	u8         reserved_at_0[0x7c0];
4871 };
4872 
4873 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits {
4874 	struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout;
4875 	u8         reserved_at_0[0x7c0];
4876 };
4877 
4878 union mlx5_ifc_event_auto_bits {
4879 	struct mlx5_ifc_comp_event_bits comp_event;
4880 	struct mlx5_ifc_dct_events_bits dct_events;
4881 	struct mlx5_ifc_qp_events_bits qp_events;
4882 	struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
4883 	struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
4884 	struct mlx5_ifc_cq_error_bits cq_error;
4885 	struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
4886 	struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
4887 	struct mlx5_ifc_gpio_event_bits gpio_event;
4888 	struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
4889 	struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
4890 	struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
4891 	u8         reserved_at_0[0xe0];
4892 };
4893 
4894 struct mlx5_ifc_health_buffer_bits {
4895 	u8         reserved_at_0[0x100];
4896 
4897 	u8         assert_existptr[0x20];
4898 
4899 	u8         assert_callra[0x20];
4900 
4901 	u8         reserved_at_140[0x20];
4902 
4903 	u8         time[0x20];
4904 
4905 	u8         fw_version[0x20];
4906 
4907 	u8         hw_id[0x20];
4908 
4909 	u8         rfr[0x1];
4910 	u8         reserved_at_1c1[0x3];
4911 	u8         valid[0x1];
4912 	u8         severity[0x3];
4913 	u8         reserved_at_1c8[0x18];
4914 
4915 	u8         irisc_index[0x8];
4916 	u8         synd[0x8];
4917 	u8         ext_synd[0x10];
4918 };
4919 
4920 struct mlx5_ifc_register_loopback_control_bits {
4921 	u8         no_lb[0x1];
4922 	u8         reserved_at_1[0x7];
4923 	u8         port[0x8];
4924 	u8         reserved_at_10[0x10];
4925 
4926 	u8         reserved_at_20[0x60];
4927 };
4928 
4929 enum {
4930 	MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0,
4931 	MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1,
4932 };
4933 
4934 struct mlx5_ifc_teardown_hca_out_bits {
4935 	u8         status[0x8];
4936 	u8         reserved_at_8[0x18];
4937 
4938 	u8         syndrome[0x20];
4939 
4940 	u8         reserved_at_40[0x3f];
4941 
4942 	u8         state[0x1];
4943 };
4944 
4945 enum {
4946 	MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE  = 0x0,
4947 	MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE     = 0x1,
4948 	MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN = 0x2,
4949 };
4950 
4951 struct mlx5_ifc_teardown_hca_in_bits {
4952 	u8         opcode[0x10];
4953 	u8         reserved_at_10[0x10];
4954 
4955 	u8         reserved_at_20[0x10];
4956 	u8         op_mod[0x10];
4957 
4958 	u8         reserved_at_40[0x10];
4959 	u8         profile[0x10];
4960 
4961 	u8         reserved_at_60[0x20];
4962 };
4963 
4964 struct mlx5_ifc_sqerr2rts_qp_out_bits {
4965 	u8         status[0x8];
4966 	u8         reserved_at_8[0x18];
4967 
4968 	u8         syndrome[0x20];
4969 
4970 	u8         reserved_at_40[0x40];
4971 };
4972 
4973 struct mlx5_ifc_sqerr2rts_qp_in_bits {
4974 	u8         opcode[0x10];
4975 	u8         uid[0x10];
4976 
4977 	u8         reserved_at_20[0x10];
4978 	u8         op_mod[0x10];
4979 
4980 	u8         reserved_at_40[0x8];
4981 	u8         qpn[0x18];
4982 
4983 	u8         reserved_at_60[0x20];
4984 
4985 	u8         opt_param_mask[0x20];
4986 
4987 	u8         reserved_at_a0[0x20];
4988 
4989 	struct mlx5_ifc_qpc_bits qpc;
4990 
4991 	u8         reserved_at_800[0x80];
4992 };
4993 
4994 struct mlx5_ifc_sqd2rts_qp_out_bits {
4995 	u8         status[0x8];
4996 	u8         reserved_at_8[0x18];
4997 
4998 	u8         syndrome[0x20];
4999 
5000 	u8         reserved_at_40[0x40];
5001 };
5002 
5003 struct mlx5_ifc_sqd2rts_qp_in_bits {
5004 	u8         opcode[0x10];
5005 	u8         uid[0x10];
5006 
5007 	u8         reserved_at_20[0x10];
5008 	u8         op_mod[0x10];
5009 
5010 	u8         reserved_at_40[0x8];
5011 	u8         qpn[0x18];
5012 
5013 	u8         reserved_at_60[0x20];
5014 
5015 	u8         opt_param_mask[0x20];
5016 
5017 	u8         reserved_at_a0[0x20];
5018 
5019 	struct mlx5_ifc_qpc_bits qpc;
5020 
5021 	u8         reserved_at_800[0x80];
5022 };
5023 
5024 struct mlx5_ifc_set_roce_address_out_bits {
5025 	u8         status[0x8];
5026 	u8         reserved_at_8[0x18];
5027 
5028 	u8         syndrome[0x20];
5029 
5030 	u8         reserved_at_40[0x40];
5031 };
5032 
5033 struct mlx5_ifc_set_roce_address_in_bits {
5034 	u8         opcode[0x10];
5035 	u8         reserved_at_10[0x10];
5036 
5037 	u8         reserved_at_20[0x10];
5038 	u8         op_mod[0x10];
5039 
5040 	u8         roce_address_index[0x10];
5041 	u8         reserved_at_50[0xc];
5042 	u8	   vhca_port_num[0x4];
5043 
5044 	u8         reserved_at_60[0x20];
5045 
5046 	struct mlx5_ifc_roce_addr_layout_bits roce_address;
5047 };
5048 
5049 struct mlx5_ifc_set_mad_demux_out_bits {
5050 	u8         status[0x8];
5051 	u8         reserved_at_8[0x18];
5052 
5053 	u8         syndrome[0x20];
5054 
5055 	u8         reserved_at_40[0x40];
5056 };
5057 
5058 enum {
5059 	MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL   = 0x0,
5060 	MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE  = 0x2,
5061 };
5062 
5063 struct mlx5_ifc_set_mad_demux_in_bits {
5064 	u8         opcode[0x10];
5065 	u8         reserved_at_10[0x10];
5066 
5067 	u8         reserved_at_20[0x10];
5068 	u8         op_mod[0x10];
5069 
5070 	u8         reserved_at_40[0x20];
5071 
5072 	u8         reserved_at_60[0x6];
5073 	u8         demux_mode[0x2];
5074 	u8         reserved_at_68[0x18];
5075 };
5076 
5077 struct mlx5_ifc_set_l2_table_entry_out_bits {
5078 	u8         status[0x8];
5079 	u8         reserved_at_8[0x18];
5080 
5081 	u8         syndrome[0x20];
5082 
5083 	u8         reserved_at_40[0x40];
5084 };
5085 
5086 struct mlx5_ifc_set_l2_table_entry_in_bits {
5087 	u8         opcode[0x10];
5088 	u8         reserved_at_10[0x10];
5089 
5090 	u8         reserved_at_20[0x10];
5091 	u8         op_mod[0x10];
5092 
5093 	u8         reserved_at_40[0x60];
5094 
5095 	u8         reserved_at_a0[0x8];
5096 	u8         table_index[0x18];
5097 
5098 	u8         reserved_at_c0[0x20];
5099 
5100 	u8         reserved_at_e0[0x10];
5101 	u8         silent_mode_valid[0x1];
5102 	u8         silent_mode[0x1];
5103 	u8         reserved_at_f2[0x1];
5104 	u8         vlan_valid[0x1];
5105 	u8         vlan[0xc];
5106 
5107 	struct mlx5_ifc_mac_address_layout_bits mac_address;
5108 
5109 	u8         reserved_at_140[0xc0];
5110 };
5111 
5112 struct mlx5_ifc_set_issi_out_bits {
5113 	u8         status[0x8];
5114 	u8         reserved_at_8[0x18];
5115 
5116 	u8         syndrome[0x20];
5117 
5118 	u8         reserved_at_40[0x40];
5119 };
5120 
5121 struct mlx5_ifc_set_issi_in_bits {
5122 	u8         opcode[0x10];
5123 	u8         reserved_at_10[0x10];
5124 
5125 	u8         reserved_at_20[0x10];
5126 	u8         op_mod[0x10];
5127 
5128 	u8         reserved_at_40[0x10];
5129 	u8         current_issi[0x10];
5130 
5131 	u8         reserved_at_60[0x20];
5132 };
5133 
5134 struct mlx5_ifc_set_hca_cap_out_bits {
5135 	u8         status[0x8];
5136 	u8         reserved_at_8[0x18];
5137 
5138 	u8         syndrome[0x20];
5139 
5140 	u8         reserved_at_40[0x40];
5141 };
5142 
5143 struct mlx5_ifc_set_hca_cap_in_bits {
5144 	u8         opcode[0x10];
5145 	u8         reserved_at_10[0x10];
5146 
5147 	u8         reserved_at_20[0x10];
5148 	u8         op_mod[0x10];
5149 
5150 	u8         other_function[0x1];
5151 	u8         ec_vf_function[0x1];
5152 	u8         reserved_at_42[0xe];
5153 	u8         function_id[0x10];
5154 
5155 	u8         reserved_at_60[0x20];
5156 
5157 	union mlx5_ifc_hca_cap_union_bits capability;
5158 };
5159 
5160 enum {
5161 	MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION    = 0x0,
5162 	MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG  = 0x1,
5163 	MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST    = 0x2,
5164 	MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS    = 0x3,
5165 	MLX5_SET_FTE_MODIFY_ENABLE_MASK_IPSEC_OBJ_ID    = 0x4
5166 };
5167 
5168 struct mlx5_ifc_set_fte_out_bits {
5169 	u8         status[0x8];
5170 	u8         reserved_at_8[0x18];
5171 
5172 	u8         syndrome[0x20];
5173 
5174 	u8         reserved_at_40[0x40];
5175 };
5176 
5177 struct mlx5_ifc_set_fte_in_bits {
5178 	u8         opcode[0x10];
5179 	u8         reserved_at_10[0x10];
5180 
5181 	u8         reserved_at_20[0x10];
5182 	u8         op_mod[0x10];
5183 
5184 	u8         other_vport[0x1];
5185 	u8         reserved_at_41[0xf];
5186 	u8         vport_number[0x10];
5187 
5188 	u8         reserved_at_60[0x20];
5189 
5190 	u8         table_type[0x8];
5191 	u8         reserved_at_88[0x18];
5192 
5193 	u8         reserved_at_a0[0x8];
5194 	u8         table_id[0x18];
5195 
5196 	u8         ignore_flow_level[0x1];
5197 	u8         reserved_at_c1[0x17];
5198 	u8         modify_enable_mask[0x8];
5199 
5200 	u8         reserved_at_e0[0x20];
5201 
5202 	u8         flow_index[0x20];
5203 
5204 	u8         reserved_at_120[0xe0];
5205 
5206 	struct mlx5_ifc_flow_context_bits flow_context;
5207 };
5208 
5209 struct mlx5_ifc_dest_format_bits {
5210 	u8         destination_type[0x8];
5211 	u8         destination_id[0x18];
5212 
5213 	u8         destination_eswitch_owner_vhca_id_valid[0x1];
5214 	u8         packet_reformat[0x1];
5215 	u8         reserved_at_22[0xe];
5216 	u8         destination_eswitch_owner_vhca_id[0x10];
5217 };
5218 
5219 struct mlx5_ifc_rts2rts_qp_out_bits {
5220 	u8         status[0x8];
5221 	u8         reserved_at_8[0x18];
5222 
5223 	u8         syndrome[0x20];
5224 
5225 	u8         reserved_at_40[0x20];
5226 	u8         ece[0x20];
5227 };
5228 
5229 struct mlx5_ifc_rts2rts_qp_in_bits {
5230 	u8         opcode[0x10];
5231 	u8         uid[0x10];
5232 
5233 	u8         reserved_at_20[0x10];
5234 	u8         op_mod[0x10];
5235 
5236 	u8         reserved_at_40[0x8];
5237 	u8         qpn[0x18];
5238 
5239 	u8         reserved_at_60[0x20];
5240 
5241 	u8         opt_param_mask[0x20];
5242 
5243 	u8         ece[0x20];
5244 
5245 	struct mlx5_ifc_qpc_bits qpc;
5246 
5247 	u8         reserved_at_800[0x80];
5248 };
5249 
5250 struct mlx5_ifc_rtr2rts_qp_out_bits {
5251 	u8         status[0x8];
5252 	u8         reserved_at_8[0x18];
5253 
5254 	u8         syndrome[0x20];
5255 
5256 	u8         reserved_at_40[0x20];
5257 	u8         ece[0x20];
5258 };
5259 
5260 struct mlx5_ifc_rtr2rts_qp_in_bits {
5261 	u8         opcode[0x10];
5262 	u8         uid[0x10];
5263 
5264 	u8         reserved_at_20[0x10];
5265 	u8         op_mod[0x10];
5266 
5267 	u8         reserved_at_40[0x8];
5268 	u8         qpn[0x18];
5269 
5270 	u8         reserved_at_60[0x20];
5271 
5272 	u8         opt_param_mask[0x20];
5273 
5274 	u8         ece[0x20];
5275 
5276 	struct mlx5_ifc_qpc_bits qpc;
5277 
5278 	u8         reserved_at_800[0x80];
5279 };
5280 
5281 struct mlx5_ifc_rst2init_qp_out_bits {
5282 	u8         status[0x8];
5283 	u8         reserved_at_8[0x18];
5284 
5285 	u8         syndrome[0x20];
5286 
5287 	u8         reserved_at_40[0x20];
5288 	u8         ece[0x20];
5289 };
5290 
5291 struct mlx5_ifc_rst2init_qp_in_bits {
5292 	u8         opcode[0x10];
5293 	u8         uid[0x10];
5294 
5295 	u8         reserved_at_20[0x10];
5296 	u8         op_mod[0x10];
5297 
5298 	u8         reserved_at_40[0x8];
5299 	u8         qpn[0x18];
5300 
5301 	u8         reserved_at_60[0x20];
5302 
5303 	u8         opt_param_mask[0x20];
5304 
5305 	u8         ece[0x20];
5306 
5307 	struct mlx5_ifc_qpc_bits qpc;
5308 
5309 	u8         reserved_at_800[0x80];
5310 };
5311 
5312 struct mlx5_ifc_query_xrq_out_bits {
5313 	u8         status[0x8];
5314 	u8         reserved_at_8[0x18];
5315 
5316 	u8         syndrome[0x20];
5317 
5318 	u8         reserved_at_40[0x40];
5319 
5320 	struct mlx5_ifc_xrqc_bits xrq_context;
5321 };
5322 
5323 struct mlx5_ifc_query_xrq_in_bits {
5324 	u8         opcode[0x10];
5325 	u8         reserved_at_10[0x10];
5326 
5327 	u8         reserved_at_20[0x10];
5328 	u8         op_mod[0x10];
5329 
5330 	u8         reserved_at_40[0x8];
5331 	u8         xrqn[0x18];
5332 
5333 	u8         reserved_at_60[0x20];
5334 };
5335 
5336 struct mlx5_ifc_query_xrc_srq_out_bits {
5337 	u8         status[0x8];
5338 	u8         reserved_at_8[0x18];
5339 
5340 	u8         syndrome[0x20];
5341 
5342 	u8         reserved_at_40[0x40];
5343 
5344 	struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
5345 
5346 	u8         reserved_at_280[0x600];
5347 
5348 	u8         pas[][0x40];
5349 };
5350 
5351 struct mlx5_ifc_query_xrc_srq_in_bits {
5352 	u8         opcode[0x10];
5353 	u8         reserved_at_10[0x10];
5354 
5355 	u8         reserved_at_20[0x10];
5356 	u8         op_mod[0x10];
5357 
5358 	u8         reserved_at_40[0x8];
5359 	u8         xrc_srqn[0x18];
5360 
5361 	u8         reserved_at_60[0x20];
5362 };
5363 
5364 enum {
5365 	MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN  = 0x0,
5366 	MLX5_QUERY_VPORT_STATE_OUT_STATE_UP    = 0x1,
5367 };
5368 
5369 struct mlx5_ifc_query_vport_state_out_bits {
5370 	u8         status[0x8];
5371 	u8         reserved_at_8[0x18];
5372 
5373 	u8         syndrome[0x20];
5374 
5375 	u8         reserved_at_40[0x20];
5376 
5377 	u8         reserved_at_60[0x18];
5378 	u8         admin_state[0x4];
5379 	u8         state[0x4];
5380 };
5381 
5382 struct mlx5_ifc_array1024_auto_bits {
5383 	u8         array1024_auto[32][0x20];
5384 };
5385 
5386 struct mlx5_ifc_query_vuid_in_bits {
5387 	u8         opcode[0x10];
5388 	u8         uid[0x10];
5389 
5390 	u8         reserved_at_20[0x40];
5391 
5392 	u8         query_vfs_vuid[0x1];
5393 	u8         data_direct[0x1];
5394 	u8         reserved_at_62[0xe];
5395 	u8         vhca_id[0x10];
5396 };
5397 
5398 struct mlx5_ifc_query_vuid_out_bits {
5399 	u8        status[0x8];
5400 	u8        reserved_at_8[0x18];
5401 
5402 	u8        syndrome[0x20];
5403 
5404 	u8        reserved_at_40[0x1a0];
5405 
5406 	u8        reserved_at_1e0[0x10];
5407 	u8        num_of_entries[0x10];
5408 
5409 	struct mlx5_ifc_array1024_auto_bits vuid[];
5410 };
5411 
5412 enum {
5413 	MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT  = 0x0,
5414 	MLX5_VPORT_STATE_OP_MOD_ESW_VPORT   = 0x1,
5415 	MLX5_VPORT_STATE_OP_MOD_UPLINK      = 0x2,
5416 };
5417 
5418 struct mlx5_ifc_arm_monitor_counter_in_bits {
5419 	u8         opcode[0x10];
5420 	u8         uid[0x10];
5421 
5422 	u8         reserved_at_20[0x10];
5423 	u8         op_mod[0x10];
5424 
5425 	u8         reserved_at_40[0x20];
5426 
5427 	u8         reserved_at_60[0x20];
5428 };
5429 
5430 struct mlx5_ifc_arm_monitor_counter_out_bits {
5431 	u8         status[0x8];
5432 	u8         reserved_at_8[0x18];
5433 
5434 	u8         syndrome[0x20];
5435 
5436 	u8         reserved_at_40[0x40];
5437 };
5438 
5439 enum {
5440 	MLX5_QUERY_MONITOR_CNT_TYPE_PPCNT     = 0x0,
5441 	MLX5_QUERY_MONITOR_CNT_TYPE_Q_COUNTER = 0x1,
5442 };
5443 
5444 enum mlx5_monitor_counter_ppcnt {
5445 	MLX5_QUERY_MONITOR_PPCNT_IN_RANGE_LENGTH_ERRORS      = 0x0,
5446 	MLX5_QUERY_MONITOR_PPCNT_OUT_OF_RANGE_LENGTH_FIELD   = 0x1,
5447 	MLX5_QUERY_MONITOR_PPCNT_FRAME_TOO_LONG_ERRORS       = 0x2,
5448 	MLX5_QUERY_MONITOR_PPCNT_FRAME_CHECK_SEQUENCE_ERRORS = 0x3,
5449 	MLX5_QUERY_MONITOR_PPCNT_ALIGNMENT_ERRORS            = 0x4,
5450 	MLX5_QUERY_MONITOR_PPCNT_IF_OUT_DISCARDS             = 0x5,
5451 };
5452 
5453 enum {
5454 	MLX5_QUERY_MONITOR_Q_COUNTER_RX_OUT_OF_BUFFER     = 0x4,
5455 };
5456 
5457 struct mlx5_ifc_monitor_counter_output_bits {
5458 	u8         reserved_at_0[0x4];
5459 	u8         type[0x4];
5460 	u8         reserved_at_8[0x8];
5461 	u8         counter[0x10];
5462 
5463 	u8         counter_group_id[0x20];
5464 };
5465 
5466 #define MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 (6)
5467 #define MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1    (1)
5468 #define MLX5_CMD_SET_MONITOR_NUM_COUNTER (MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 +\
5469 					  MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1)
5470 
5471 struct mlx5_ifc_set_monitor_counter_in_bits {
5472 	u8         opcode[0x10];
5473 	u8         uid[0x10];
5474 
5475 	u8         reserved_at_20[0x10];
5476 	u8         op_mod[0x10];
5477 
5478 	u8         reserved_at_40[0x10];
5479 	u8         num_of_counters[0x10];
5480 
5481 	u8         reserved_at_60[0x20];
5482 
5483 	struct mlx5_ifc_monitor_counter_output_bits monitor_counter[MLX5_CMD_SET_MONITOR_NUM_COUNTER];
5484 };
5485 
5486 struct mlx5_ifc_set_monitor_counter_out_bits {
5487 	u8         status[0x8];
5488 	u8         reserved_at_8[0x18];
5489 
5490 	u8         syndrome[0x20];
5491 
5492 	u8         reserved_at_40[0x40];
5493 };
5494 
5495 struct mlx5_ifc_query_vport_state_in_bits {
5496 	u8         opcode[0x10];
5497 	u8         reserved_at_10[0x10];
5498 
5499 	u8         reserved_at_20[0x10];
5500 	u8         op_mod[0x10];
5501 
5502 	u8         other_vport[0x1];
5503 	u8         reserved_at_41[0xf];
5504 	u8         vport_number[0x10];
5505 
5506 	u8         reserved_at_60[0x20];
5507 };
5508 
5509 struct mlx5_ifc_query_vnic_env_out_bits {
5510 	u8         status[0x8];
5511 	u8         reserved_at_8[0x18];
5512 
5513 	u8         syndrome[0x20];
5514 
5515 	u8         reserved_at_40[0x40];
5516 
5517 	struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env;
5518 };
5519 
5520 enum {
5521 	MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS  = 0x0,
5522 };
5523 
5524 struct mlx5_ifc_query_vnic_env_in_bits {
5525 	u8         opcode[0x10];
5526 	u8         reserved_at_10[0x10];
5527 
5528 	u8         reserved_at_20[0x10];
5529 	u8         op_mod[0x10];
5530 
5531 	u8         other_vport[0x1];
5532 	u8         reserved_at_41[0xf];
5533 	u8         vport_number[0x10];
5534 
5535 	u8         reserved_at_60[0x20];
5536 };
5537 
5538 struct mlx5_ifc_query_vport_counter_out_bits {
5539 	u8         status[0x8];
5540 	u8         reserved_at_8[0x18];
5541 
5542 	u8         syndrome[0x20];
5543 
5544 	u8         reserved_at_40[0x40];
5545 
5546 	struct mlx5_ifc_traffic_counter_bits received_errors;
5547 
5548 	struct mlx5_ifc_traffic_counter_bits transmit_errors;
5549 
5550 	struct mlx5_ifc_traffic_counter_bits received_ib_unicast;
5551 
5552 	struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast;
5553 
5554 	struct mlx5_ifc_traffic_counter_bits received_ib_multicast;
5555 
5556 	struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast;
5557 
5558 	struct mlx5_ifc_traffic_counter_bits received_eth_broadcast;
5559 
5560 	struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast;
5561 
5562 	struct mlx5_ifc_traffic_counter_bits received_eth_unicast;
5563 
5564 	struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast;
5565 
5566 	struct mlx5_ifc_traffic_counter_bits received_eth_multicast;
5567 
5568 	struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast;
5569 
5570 	struct mlx5_ifc_traffic_counter_bits local_loopback;
5571 
5572 	u8         reserved_at_700[0x980];
5573 };
5574 
5575 enum {
5576 	MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS  = 0x0,
5577 };
5578 
5579 struct mlx5_ifc_query_vport_counter_in_bits {
5580 	u8         opcode[0x10];
5581 	u8         reserved_at_10[0x10];
5582 
5583 	u8         reserved_at_20[0x10];
5584 	u8         op_mod[0x10];
5585 
5586 	u8         other_vport[0x1];
5587 	u8         reserved_at_41[0xb];
5588 	u8	   port_num[0x4];
5589 	u8         vport_number[0x10];
5590 
5591 	u8         reserved_at_60[0x60];
5592 
5593 	u8         clear[0x1];
5594 	u8         reserved_at_c1[0x1f];
5595 
5596 	u8         reserved_at_e0[0x20];
5597 };
5598 
5599 struct mlx5_ifc_query_tis_out_bits {
5600 	u8         status[0x8];
5601 	u8         reserved_at_8[0x18];
5602 
5603 	u8         syndrome[0x20];
5604 
5605 	u8         reserved_at_40[0x40];
5606 
5607 	struct mlx5_ifc_tisc_bits tis_context;
5608 };
5609 
5610 struct mlx5_ifc_query_tis_in_bits {
5611 	u8         opcode[0x10];
5612 	u8         reserved_at_10[0x10];
5613 
5614 	u8         reserved_at_20[0x10];
5615 	u8         op_mod[0x10];
5616 
5617 	u8         reserved_at_40[0x8];
5618 	u8         tisn[0x18];
5619 
5620 	u8         reserved_at_60[0x20];
5621 };
5622 
5623 struct mlx5_ifc_query_tir_out_bits {
5624 	u8         status[0x8];
5625 	u8         reserved_at_8[0x18];
5626 
5627 	u8         syndrome[0x20];
5628 
5629 	u8         reserved_at_40[0xc0];
5630 
5631 	struct mlx5_ifc_tirc_bits tir_context;
5632 };
5633 
5634 struct mlx5_ifc_query_tir_in_bits {
5635 	u8         opcode[0x10];
5636 	u8         reserved_at_10[0x10];
5637 
5638 	u8         reserved_at_20[0x10];
5639 	u8         op_mod[0x10];
5640 
5641 	u8         reserved_at_40[0x8];
5642 	u8         tirn[0x18];
5643 
5644 	u8         reserved_at_60[0x20];
5645 };
5646 
5647 struct mlx5_ifc_query_srq_out_bits {
5648 	u8         status[0x8];
5649 	u8         reserved_at_8[0x18];
5650 
5651 	u8         syndrome[0x20];
5652 
5653 	u8         reserved_at_40[0x40];
5654 
5655 	struct mlx5_ifc_srqc_bits srq_context_entry;
5656 
5657 	u8         reserved_at_280[0x600];
5658 
5659 	u8         pas[][0x40];
5660 };
5661 
5662 struct mlx5_ifc_query_srq_in_bits {
5663 	u8         opcode[0x10];
5664 	u8         reserved_at_10[0x10];
5665 
5666 	u8         reserved_at_20[0x10];
5667 	u8         op_mod[0x10];
5668 
5669 	u8         reserved_at_40[0x8];
5670 	u8         srqn[0x18];
5671 
5672 	u8         reserved_at_60[0x20];
5673 };
5674 
5675 struct mlx5_ifc_query_sq_out_bits {
5676 	u8         status[0x8];
5677 	u8         reserved_at_8[0x18];
5678 
5679 	u8         syndrome[0x20];
5680 
5681 	u8         reserved_at_40[0xc0];
5682 
5683 	struct mlx5_ifc_sqc_bits sq_context;
5684 };
5685 
5686 struct mlx5_ifc_query_sq_in_bits {
5687 	u8         opcode[0x10];
5688 	u8         reserved_at_10[0x10];
5689 
5690 	u8         reserved_at_20[0x10];
5691 	u8         op_mod[0x10];
5692 
5693 	u8         reserved_at_40[0x8];
5694 	u8         sqn[0x18];
5695 
5696 	u8         reserved_at_60[0x20];
5697 };
5698 
5699 struct mlx5_ifc_query_special_contexts_out_bits {
5700 	u8         status[0x8];
5701 	u8         reserved_at_8[0x18];
5702 
5703 	u8         syndrome[0x20];
5704 
5705 	u8         dump_fill_mkey[0x20];
5706 
5707 	u8         resd_lkey[0x20];
5708 
5709 	u8         null_mkey[0x20];
5710 
5711 	u8	   terminate_scatter_list_mkey[0x20];
5712 
5713 	u8	   repeated_mkey[0x20];
5714 
5715 	u8         reserved_at_a0[0x20];
5716 };
5717 
5718 struct mlx5_ifc_query_special_contexts_in_bits {
5719 	u8         opcode[0x10];
5720 	u8         reserved_at_10[0x10];
5721 
5722 	u8         reserved_at_20[0x10];
5723 	u8         op_mod[0x10];
5724 
5725 	u8         reserved_at_40[0x40];
5726 };
5727 
5728 struct mlx5_ifc_query_scheduling_element_out_bits {
5729 	u8         opcode[0x10];
5730 	u8         reserved_at_10[0x10];
5731 
5732 	u8         reserved_at_20[0x10];
5733 	u8         op_mod[0x10];
5734 
5735 	u8         reserved_at_40[0xc0];
5736 
5737 	struct mlx5_ifc_scheduling_context_bits scheduling_context;
5738 
5739 	u8         reserved_at_300[0x100];
5740 };
5741 
5742 enum {
5743 	SCHEDULING_HIERARCHY_E_SWITCH = 0x2,
5744 	SCHEDULING_HIERARCHY_NIC = 0x3,
5745 };
5746 
5747 struct mlx5_ifc_query_scheduling_element_in_bits {
5748 	u8         opcode[0x10];
5749 	u8         reserved_at_10[0x10];
5750 
5751 	u8         reserved_at_20[0x10];
5752 	u8         op_mod[0x10];
5753 
5754 	u8         scheduling_hierarchy[0x8];
5755 	u8         reserved_at_48[0x18];
5756 
5757 	u8         scheduling_element_id[0x20];
5758 
5759 	u8         reserved_at_80[0x180];
5760 };
5761 
5762 struct mlx5_ifc_query_rqt_out_bits {
5763 	u8         status[0x8];
5764 	u8         reserved_at_8[0x18];
5765 
5766 	u8         syndrome[0x20];
5767 
5768 	u8         reserved_at_40[0xc0];
5769 
5770 	struct mlx5_ifc_rqtc_bits rqt_context;
5771 };
5772 
5773 struct mlx5_ifc_query_rqt_in_bits {
5774 	u8         opcode[0x10];
5775 	u8         reserved_at_10[0x10];
5776 
5777 	u8         reserved_at_20[0x10];
5778 	u8         op_mod[0x10];
5779 
5780 	u8         reserved_at_40[0x8];
5781 	u8         rqtn[0x18];
5782 
5783 	u8         reserved_at_60[0x20];
5784 };
5785 
5786 struct mlx5_ifc_query_rq_out_bits {
5787 	u8         status[0x8];
5788 	u8         reserved_at_8[0x18];
5789 
5790 	u8         syndrome[0x20];
5791 
5792 	u8         reserved_at_40[0xc0];
5793 
5794 	struct mlx5_ifc_rqc_bits rq_context;
5795 };
5796 
5797 struct mlx5_ifc_query_rq_in_bits {
5798 	u8         opcode[0x10];
5799 	u8         reserved_at_10[0x10];
5800 
5801 	u8         reserved_at_20[0x10];
5802 	u8         op_mod[0x10];
5803 
5804 	u8         reserved_at_40[0x8];
5805 	u8         rqn[0x18];
5806 
5807 	u8         reserved_at_60[0x20];
5808 };
5809 
5810 struct mlx5_ifc_query_roce_address_out_bits {
5811 	u8         status[0x8];
5812 	u8         reserved_at_8[0x18];
5813 
5814 	u8         syndrome[0x20];
5815 
5816 	u8         reserved_at_40[0x40];
5817 
5818 	struct mlx5_ifc_roce_addr_layout_bits roce_address;
5819 };
5820 
5821 struct mlx5_ifc_query_roce_address_in_bits {
5822 	u8         opcode[0x10];
5823 	u8         reserved_at_10[0x10];
5824 
5825 	u8         reserved_at_20[0x10];
5826 	u8         op_mod[0x10];
5827 
5828 	u8         roce_address_index[0x10];
5829 	u8         reserved_at_50[0xc];
5830 	u8	   vhca_port_num[0x4];
5831 
5832 	u8         reserved_at_60[0x20];
5833 };
5834 
5835 struct mlx5_ifc_query_rmp_out_bits {
5836 	u8         status[0x8];
5837 	u8         reserved_at_8[0x18];
5838 
5839 	u8         syndrome[0x20];
5840 
5841 	u8         reserved_at_40[0xc0];
5842 
5843 	struct mlx5_ifc_rmpc_bits rmp_context;
5844 };
5845 
5846 struct mlx5_ifc_query_rmp_in_bits {
5847 	u8         opcode[0x10];
5848 	u8         reserved_at_10[0x10];
5849 
5850 	u8         reserved_at_20[0x10];
5851 	u8         op_mod[0x10];
5852 
5853 	u8         reserved_at_40[0x8];
5854 	u8         rmpn[0x18];
5855 
5856 	u8         reserved_at_60[0x20];
5857 };
5858 
5859 struct mlx5_ifc_cqe_error_syndrome_bits {
5860 	u8         hw_error_syndrome[0x8];
5861 	u8         hw_syndrome_type[0x4];
5862 	u8         reserved_at_c[0x4];
5863 	u8         vendor_error_syndrome[0x8];
5864 	u8         syndrome[0x8];
5865 };
5866 
5867 struct mlx5_ifc_qp_context_extension_bits {
5868 	u8         reserved_at_0[0x60];
5869 
5870 	struct mlx5_ifc_cqe_error_syndrome_bits error_syndrome;
5871 
5872 	u8         reserved_at_80[0x580];
5873 };
5874 
5875 struct mlx5_ifc_qpc_extension_and_pas_list_in_bits {
5876 	struct mlx5_ifc_qp_context_extension_bits qpc_data_extension;
5877 
5878 	u8         pas[0][0x40];
5879 };
5880 
5881 struct mlx5_ifc_qp_pas_list_in_bits {
5882 	struct mlx5_ifc_cmd_pas_bits pas[0];
5883 };
5884 
5885 union mlx5_ifc_qp_pas_or_qpc_ext_and_pas_bits {
5886 	struct mlx5_ifc_qp_pas_list_in_bits qp_pas_list;
5887 	struct mlx5_ifc_qpc_extension_and_pas_list_in_bits qpc_ext_and_pas_list;
5888 };
5889 
5890 struct mlx5_ifc_query_qp_out_bits {
5891 	u8         status[0x8];
5892 	u8         reserved_at_8[0x18];
5893 
5894 	u8         syndrome[0x20];
5895 
5896 	u8         reserved_at_40[0x40];
5897 
5898 	u8         opt_param_mask[0x20];
5899 
5900 	u8         ece[0x20];
5901 
5902 	struct mlx5_ifc_qpc_bits qpc;
5903 
5904 	u8         reserved_at_800[0x80];
5905 
5906 	union mlx5_ifc_qp_pas_or_qpc_ext_and_pas_bits qp_pas_or_qpc_ext_and_pas;
5907 };
5908 
5909 struct mlx5_ifc_query_qp_in_bits {
5910 	u8         opcode[0x10];
5911 	u8         reserved_at_10[0x10];
5912 
5913 	u8         reserved_at_20[0x10];
5914 	u8         op_mod[0x10];
5915 
5916 	u8         qpc_ext[0x1];
5917 	u8         reserved_at_41[0x7];
5918 	u8         qpn[0x18];
5919 
5920 	u8         reserved_at_60[0x20];
5921 };
5922 
5923 struct mlx5_ifc_query_q_counter_out_bits {
5924 	u8         status[0x8];
5925 	u8         reserved_at_8[0x18];
5926 
5927 	u8         syndrome[0x20];
5928 
5929 	u8         reserved_at_40[0x40];
5930 
5931 	u8         rx_write_requests[0x20];
5932 
5933 	u8         reserved_at_a0[0x20];
5934 
5935 	u8         rx_read_requests[0x20];
5936 
5937 	u8         reserved_at_e0[0x20];
5938 
5939 	u8         rx_atomic_requests[0x20];
5940 
5941 	u8         reserved_at_120[0x20];
5942 
5943 	u8         rx_dct_connect[0x20];
5944 
5945 	u8         reserved_at_160[0x20];
5946 
5947 	u8         out_of_buffer[0x20];
5948 
5949 	u8         reserved_at_1a0[0x20];
5950 
5951 	u8         out_of_sequence[0x20];
5952 
5953 	u8         reserved_at_1e0[0x20];
5954 
5955 	u8         duplicate_request[0x20];
5956 
5957 	u8         reserved_at_220[0x20];
5958 
5959 	u8         rnr_nak_retry_err[0x20];
5960 
5961 	u8         reserved_at_260[0x20];
5962 
5963 	u8         packet_seq_err[0x20];
5964 
5965 	u8         reserved_at_2a0[0x20];
5966 
5967 	u8         implied_nak_seq_err[0x20];
5968 
5969 	u8         reserved_at_2e0[0x20];
5970 
5971 	u8         local_ack_timeout_err[0x20];
5972 
5973 	u8         reserved_at_320[0x60];
5974 
5975 	u8         req_rnr_retries_exceeded[0x20];
5976 
5977 	u8         reserved_at_3a0[0x20];
5978 
5979 	u8         resp_local_length_error[0x20];
5980 
5981 	u8         req_local_length_error[0x20];
5982 
5983 	u8         resp_local_qp_error[0x20];
5984 
5985 	u8         local_operation_error[0x20];
5986 
5987 	u8         resp_local_protection[0x20];
5988 
5989 	u8         req_local_protection[0x20];
5990 
5991 	u8         resp_cqe_error[0x20];
5992 
5993 	u8         req_cqe_error[0x20];
5994 
5995 	u8         req_mw_binding[0x20];
5996 
5997 	u8         req_bad_response[0x20];
5998 
5999 	u8         req_remote_invalid_request[0x20];
6000 
6001 	u8         resp_remote_invalid_request[0x20];
6002 
6003 	u8         req_remote_access_errors[0x20];
6004 
6005 	u8	   resp_remote_access_errors[0x20];
6006 
6007 	u8         req_remote_operation_errors[0x20];
6008 
6009 	u8         req_transport_retries_exceeded[0x20];
6010 
6011 	u8         cq_overflow[0x20];
6012 
6013 	u8         resp_cqe_flush_error[0x20];
6014 
6015 	u8         req_cqe_flush_error[0x20];
6016 
6017 	u8         reserved_at_620[0x20];
6018 
6019 	u8         roce_adp_retrans[0x20];
6020 
6021 	u8         roce_adp_retrans_to[0x20];
6022 
6023 	u8         roce_slow_restart[0x20];
6024 
6025 	u8         roce_slow_restart_cnps[0x20];
6026 
6027 	u8         roce_slow_restart_trans[0x20];
6028 
6029 	u8         reserved_at_6e0[0x120];
6030 };
6031 
6032 struct mlx5_ifc_query_q_counter_in_bits {
6033 	u8         opcode[0x10];
6034 	u8         reserved_at_10[0x10];
6035 
6036 	u8         reserved_at_20[0x10];
6037 	u8         op_mod[0x10];
6038 
6039 	u8         other_vport[0x1];
6040 	u8         reserved_at_41[0xf];
6041 	u8         vport_number[0x10];
6042 
6043 	u8         reserved_at_60[0x60];
6044 
6045 	u8         clear[0x1];
6046 	u8         aggregate[0x1];
6047 	u8         reserved_at_c2[0x1e];
6048 
6049 	u8         reserved_at_e0[0x18];
6050 	u8         counter_set_id[0x8];
6051 };
6052 
6053 struct mlx5_ifc_query_pages_out_bits {
6054 	u8         status[0x8];
6055 	u8         reserved_at_8[0x18];
6056 
6057 	u8         syndrome[0x20];
6058 
6059 	u8         embedded_cpu_function[0x1];
6060 	u8         reserved_at_41[0xf];
6061 	u8         function_id[0x10];
6062 
6063 	u8         num_pages[0x20];
6064 };
6065 
6066 enum {
6067 	MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES     = 0x1,
6068 	MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES     = 0x2,
6069 	MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES  = 0x3,
6070 };
6071 
6072 struct mlx5_ifc_query_pages_in_bits {
6073 	u8         opcode[0x10];
6074 	u8         reserved_at_10[0x10];
6075 
6076 	u8         reserved_at_20[0x10];
6077 	u8         op_mod[0x10];
6078 
6079 	u8         embedded_cpu_function[0x1];
6080 	u8         reserved_at_41[0xf];
6081 	u8         function_id[0x10];
6082 
6083 	u8         reserved_at_60[0x20];
6084 };
6085 
6086 struct mlx5_ifc_query_nic_vport_context_out_bits {
6087 	u8         status[0x8];
6088 	u8         reserved_at_8[0x18];
6089 
6090 	u8         syndrome[0x20];
6091 
6092 	u8         reserved_at_40[0x40];
6093 
6094 	struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
6095 };
6096 
6097 struct mlx5_ifc_query_nic_vport_context_in_bits {
6098 	u8         opcode[0x10];
6099 	u8         reserved_at_10[0x10];
6100 
6101 	u8         reserved_at_20[0x10];
6102 	u8         op_mod[0x10];
6103 
6104 	u8         other_vport[0x1];
6105 	u8         reserved_at_41[0xf];
6106 	u8         vport_number[0x10];
6107 
6108 	u8         reserved_at_60[0x5];
6109 	u8         allowed_list_type[0x3];
6110 	u8         reserved_at_68[0x18];
6111 };
6112 
6113 struct mlx5_ifc_query_mkey_out_bits {
6114 	u8         status[0x8];
6115 	u8         reserved_at_8[0x18];
6116 
6117 	u8         syndrome[0x20];
6118 
6119 	u8         reserved_at_40[0x40];
6120 
6121 	struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
6122 
6123 	u8         reserved_at_280[0x600];
6124 
6125 	u8         bsf0_klm0_pas_mtt0_1[16][0x8];
6126 
6127 	u8         bsf1_klm1_pas_mtt2_3[16][0x8];
6128 };
6129 
6130 struct mlx5_ifc_query_mkey_in_bits {
6131 	u8         opcode[0x10];
6132 	u8         reserved_at_10[0x10];
6133 
6134 	u8         reserved_at_20[0x10];
6135 	u8         op_mod[0x10];
6136 
6137 	u8         reserved_at_40[0x8];
6138 	u8         mkey_index[0x18];
6139 
6140 	u8         pg_access[0x1];
6141 	u8         reserved_at_61[0x1f];
6142 };
6143 
6144 struct mlx5_ifc_query_mad_demux_out_bits {
6145 	u8         status[0x8];
6146 	u8         reserved_at_8[0x18];
6147 
6148 	u8         syndrome[0x20];
6149 
6150 	u8         reserved_at_40[0x40];
6151 
6152 	u8         mad_dumux_parameters_block[0x20];
6153 };
6154 
6155 struct mlx5_ifc_query_mad_demux_in_bits {
6156 	u8         opcode[0x10];
6157 	u8         reserved_at_10[0x10];
6158 
6159 	u8         reserved_at_20[0x10];
6160 	u8         op_mod[0x10];
6161 
6162 	u8         reserved_at_40[0x40];
6163 };
6164 
6165 struct mlx5_ifc_query_l2_table_entry_out_bits {
6166 	u8         status[0x8];
6167 	u8         reserved_at_8[0x18];
6168 
6169 	u8         syndrome[0x20];
6170 
6171 	u8         reserved_at_40[0xa0];
6172 
6173 	u8         reserved_at_e0[0x13];
6174 	u8         vlan_valid[0x1];
6175 	u8         vlan[0xc];
6176 
6177 	struct mlx5_ifc_mac_address_layout_bits mac_address;
6178 
6179 	u8         reserved_at_140[0xc0];
6180 };
6181 
6182 struct mlx5_ifc_query_l2_table_entry_in_bits {
6183 	u8         opcode[0x10];
6184 	u8         reserved_at_10[0x10];
6185 
6186 	u8         reserved_at_20[0x10];
6187 	u8         op_mod[0x10];
6188 
6189 	u8         reserved_at_40[0x60];
6190 
6191 	u8         reserved_at_a0[0x8];
6192 	u8         table_index[0x18];
6193 
6194 	u8         reserved_at_c0[0x140];
6195 };
6196 
6197 struct mlx5_ifc_query_issi_out_bits {
6198 	u8         status[0x8];
6199 	u8         reserved_at_8[0x18];
6200 
6201 	u8         syndrome[0x20];
6202 
6203 	u8         reserved_at_40[0x10];
6204 	u8         current_issi[0x10];
6205 
6206 	u8         reserved_at_60[0xa0];
6207 
6208 	u8         reserved_at_100[76][0x8];
6209 	u8         supported_issi_dw0[0x20];
6210 };
6211 
6212 struct mlx5_ifc_query_issi_in_bits {
6213 	u8         opcode[0x10];
6214 	u8         reserved_at_10[0x10];
6215 
6216 	u8         reserved_at_20[0x10];
6217 	u8         op_mod[0x10];
6218 
6219 	u8         reserved_at_40[0x40];
6220 };
6221 
6222 struct mlx5_ifc_set_driver_version_out_bits {
6223 	u8         status[0x8];
6224 	u8         reserved_0[0x18];
6225 
6226 	u8         syndrome[0x20];
6227 	u8         reserved_1[0x40];
6228 };
6229 
6230 struct mlx5_ifc_set_driver_version_in_bits {
6231 	u8         opcode[0x10];
6232 	u8         reserved_0[0x10];
6233 
6234 	u8         reserved_1[0x10];
6235 	u8         op_mod[0x10];
6236 
6237 	u8         reserved_2[0x40];
6238 	u8         driver_version[64][0x8];
6239 };
6240 
6241 struct mlx5_ifc_query_hca_vport_pkey_out_bits {
6242 	u8         status[0x8];
6243 	u8         reserved_at_8[0x18];
6244 
6245 	u8         syndrome[0x20];
6246 
6247 	u8         reserved_at_40[0x40];
6248 
6249 	struct mlx5_ifc_pkey_bits pkey[];
6250 };
6251 
6252 struct mlx5_ifc_query_hca_vport_pkey_in_bits {
6253 	u8         opcode[0x10];
6254 	u8         reserved_at_10[0x10];
6255 
6256 	u8         reserved_at_20[0x10];
6257 	u8         op_mod[0x10];
6258 
6259 	u8         other_vport[0x1];
6260 	u8         reserved_at_41[0xb];
6261 	u8         port_num[0x4];
6262 	u8         vport_number[0x10];
6263 
6264 	u8         reserved_at_60[0x10];
6265 	u8         pkey_index[0x10];
6266 };
6267 
6268 enum {
6269 	MLX5_HCA_VPORT_SEL_PORT_GUID	= 1 << 0,
6270 	MLX5_HCA_VPORT_SEL_NODE_GUID	= 1 << 1,
6271 	MLX5_HCA_VPORT_SEL_STATE_POLICY	= 1 << 2,
6272 };
6273 
6274 struct mlx5_ifc_query_hca_vport_gid_out_bits {
6275 	u8         status[0x8];
6276 	u8         reserved_at_8[0x18];
6277 
6278 	u8         syndrome[0x20];
6279 
6280 	u8         reserved_at_40[0x20];
6281 
6282 	u8         gids_num[0x10];
6283 	u8         reserved_at_70[0x10];
6284 
6285 	struct mlx5_ifc_array128_auto_bits gid[];
6286 };
6287 
6288 struct mlx5_ifc_query_hca_vport_gid_in_bits {
6289 	u8         opcode[0x10];
6290 	u8         reserved_at_10[0x10];
6291 
6292 	u8         reserved_at_20[0x10];
6293 	u8         op_mod[0x10];
6294 
6295 	u8         other_vport[0x1];
6296 	u8         reserved_at_41[0xb];
6297 	u8         port_num[0x4];
6298 	u8         vport_number[0x10];
6299 
6300 	u8         reserved_at_60[0x10];
6301 	u8         gid_index[0x10];
6302 };
6303 
6304 struct mlx5_ifc_query_hca_vport_context_out_bits {
6305 	u8         status[0x8];
6306 	u8         reserved_at_8[0x18];
6307 
6308 	u8         syndrome[0x20];
6309 
6310 	u8         reserved_at_40[0x40];
6311 
6312 	struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
6313 };
6314 
6315 struct mlx5_ifc_query_hca_vport_context_in_bits {
6316 	u8         opcode[0x10];
6317 	u8         reserved_at_10[0x10];
6318 
6319 	u8         reserved_at_20[0x10];
6320 	u8         op_mod[0x10];
6321 
6322 	u8         other_vport[0x1];
6323 	u8         reserved_at_41[0xb];
6324 	u8         port_num[0x4];
6325 	u8         vport_number[0x10];
6326 
6327 	u8         reserved_at_60[0x20];
6328 };
6329 
6330 struct mlx5_ifc_query_hca_cap_out_bits {
6331 	u8         status[0x8];
6332 	u8         reserved_at_8[0x18];
6333 
6334 	u8         syndrome[0x20];
6335 
6336 	u8         reserved_at_40[0x40];
6337 
6338 	union mlx5_ifc_hca_cap_union_bits capability;
6339 };
6340 
6341 struct mlx5_ifc_query_hca_cap_in_bits {
6342 	u8         opcode[0x10];
6343 	u8         reserved_at_10[0x10];
6344 
6345 	u8         reserved_at_20[0x10];
6346 	u8         op_mod[0x10];
6347 
6348 	u8         other_function[0x1];
6349 	u8         ec_vf_function[0x1];
6350 	u8         reserved_at_42[0xe];
6351 	u8         function_id[0x10];
6352 
6353 	u8         reserved_at_60[0x20];
6354 };
6355 
6356 struct mlx5_ifc_other_hca_cap_bits {
6357 	u8         roce[0x1];
6358 	u8         reserved_at_1[0x27f];
6359 };
6360 
6361 struct mlx5_ifc_query_other_hca_cap_out_bits {
6362 	u8         status[0x8];
6363 	u8         reserved_at_8[0x18];
6364 
6365 	u8         syndrome[0x20];
6366 
6367 	u8         reserved_at_40[0x40];
6368 
6369 	struct     mlx5_ifc_other_hca_cap_bits other_capability;
6370 };
6371 
6372 struct mlx5_ifc_query_other_hca_cap_in_bits {
6373 	u8         opcode[0x10];
6374 	u8         reserved_at_10[0x10];
6375 
6376 	u8         reserved_at_20[0x10];
6377 	u8         op_mod[0x10];
6378 
6379 	u8         reserved_at_40[0x10];
6380 	u8         function_id[0x10];
6381 
6382 	u8         reserved_at_60[0x20];
6383 };
6384 
6385 struct mlx5_ifc_modify_other_hca_cap_out_bits {
6386 	u8         status[0x8];
6387 	u8         reserved_at_8[0x18];
6388 
6389 	u8         syndrome[0x20];
6390 
6391 	u8         reserved_at_40[0x40];
6392 };
6393 
6394 struct mlx5_ifc_modify_other_hca_cap_in_bits {
6395 	u8         opcode[0x10];
6396 	u8         reserved_at_10[0x10];
6397 
6398 	u8         reserved_at_20[0x10];
6399 	u8         op_mod[0x10];
6400 
6401 	u8         reserved_at_40[0x10];
6402 	u8         function_id[0x10];
6403 	u8         field_select[0x20];
6404 
6405 	struct     mlx5_ifc_other_hca_cap_bits other_capability;
6406 };
6407 
6408 struct mlx5_ifc_sw_owner_icm_root_params_bits {
6409 	u8         sw_owner_icm_root_1[0x40];
6410 
6411 	u8         sw_owner_icm_root_0[0x40];
6412 };
6413 
6414 struct mlx5_ifc_rtc_params_bits {
6415 	u8         rtc_id_0[0x20];
6416 
6417 	u8         rtc_id_1[0x20];
6418 
6419 	u8         reserved_at_40[0x40];
6420 };
6421 
6422 struct mlx5_ifc_flow_table_context_bits {
6423 	u8         reformat_en[0x1];
6424 	u8         decap_en[0x1];
6425 	u8         sw_owner[0x1];
6426 	u8         termination_table[0x1];
6427 	u8         table_miss_action[0x4];
6428 	u8         level[0x8];
6429 	u8         rtc_valid[0x1];
6430 	u8         reserved_at_11[0x7];
6431 	u8         log_size[0x8];
6432 
6433 	u8         reserved_at_20[0x8];
6434 	u8         table_miss_id[0x18];
6435 
6436 	u8         reserved_at_40[0x8];
6437 	u8         lag_master_next_table_id[0x18];
6438 
6439 	u8         reserved_at_60[0x60];
6440 
6441 	union {
6442 		struct mlx5_ifc_sw_owner_icm_root_params_bits sws;
6443 		struct mlx5_ifc_rtc_params_bits hws;
6444 	};
6445 };
6446 
6447 struct mlx5_ifc_query_flow_table_out_bits {
6448 	u8         status[0x8];
6449 	u8         reserved_at_8[0x18];
6450 
6451 	u8         syndrome[0x20];
6452 
6453 	u8         reserved_at_40[0x80];
6454 
6455 	struct mlx5_ifc_flow_table_context_bits flow_table_context;
6456 };
6457 
6458 struct mlx5_ifc_query_flow_table_in_bits {
6459 	u8         opcode[0x10];
6460 	u8         reserved_at_10[0x10];
6461 
6462 	u8         reserved_at_20[0x10];
6463 	u8         op_mod[0x10];
6464 
6465 	u8         reserved_at_40[0x40];
6466 
6467 	u8         table_type[0x8];
6468 	u8         reserved_at_88[0x18];
6469 
6470 	u8         reserved_at_a0[0x8];
6471 	u8         table_id[0x18];
6472 
6473 	u8         reserved_at_c0[0x140];
6474 };
6475 
6476 struct mlx5_ifc_query_fte_out_bits {
6477 	u8         status[0x8];
6478 	u8         reserved_at_8[0x18];
6479 
6480 	u8         syndrome[0x20];
6481 
6482 	u8         reserved_at_40[0x1c0];
6483 
6484 	struct mlx5_ifc_flow_context_bits flow_context;
6485 };
6486 
6487 struct mlx5_ifc_query_fte_in_bits {
6488 	u8         opcode[0x10];
6489 	u8         reserved_at_10[0x10];
6490 
6491 	u8         reserved_at_20[0x10];
6492 	u8         op_mod[0x10];
6493 
6494 	u8         reserved_at_40[0x40];
6495 
6496 	u8         table_type[0x8];
6497 	u8         reserved_at_88[0x18];
6498 
6499 	u8         reserved_at_a0[0x8];
6500 	u8         table_id[0x18];
6501 
6502 	u8         reserved_at_c0[0x40];
6503 
6504 	u8         flow_index[0x20];
6505 
6506 	u8         reserved_at_120[0xe0];
6507 };
6508 
6509 struct mlx5_ifc_match_definer_format_0_bits {
6510 	u8         reserved_at_0[0x100];
6511 
6512 	u8         metadata_reg_c_0[0x20];
6513 
6514 	u8         metadata_reg_c_1[0x20];
6515 
6516 	u8         outer_dmac_47_16[0x20];
6517 
6518 	u8         outer_dmac_15_0[0x10];
6519 	u8         outer_ethertype[0x10];
6520 
6521 	u8         reserved_at_180[0x1];
6522 	u8         sx_sniffer[0x1];
6523 	u8         functional_lb[0x1];
6524 	u8         outer_ip_frag[0x1];
6525 	u8         outer_qp_type[0x2];
6526 	u8         outer_encap_type[0x2];
6527 	u8         port_number[0x2];
6528 	u8         outer_l3_type[0x2];
6529 	u8         outer_l4_type[0x2];
6530 	u8         outer_first_vlan_type[0x2];
6531 	u8         outer_first_vlan_prio[0x3];
6532 	u8         outer_first_vlan_cfi[0x1];
6533 	u8         outer_first_vlan_vid[0xc];
6534 
6535 	u8         outer_l4_type_ext[0x4];
6536 	u8         reserved_at_1a4[0x2];
6537 	u8         outer_ipsec_layer[0x2];
6538 	u8         outer_l2_type[0x2];
6539 	u8         force_lb[0x1];
6540 	u8         outer_l2_ok[0x1];
6541 	u8         outer_l3_ok[0x1];
6542 	u8         outer_l4_ok[0x1];
6543 	u8         outer_second_vlan_type[0x2];
6544 	u8         outer_second_vlan_prio[0x3];
6545 	u8         outer_second_vlan_cfi[0x1];
6546 	u8         outer_second_vlan_vid[0xc];
6547 
6548 	u8         outer_smac_47_16[0x20];
6549 
6550 	u8         outer_smac_15_0[0x10];
6551 	u8         inner_ipv4_checksum_ok[0x1];
6552 	u8         inner_l4_checksum_ok[0x1];
6553 	u8         outer_ipv4_checksum_ok[0x1];
6554 	u8         outer_l4_checksum_ok[0x1];
6555 	u8         inner_l3_ok[0x1];
6556 	u8         inner_l4_ok[0x1];
6557 	u8         outer_l3_ok_duplicate[0x1];
6558 	u8         outer_l4_ok_duplicate[0x1];
6559 	u8         outer_tcp_cwr[0x1];
6560 	u8         outer_tcp_ece[0x1];
6561 	u8         outer_tcp_urg[0x1];
6562 	u8         outer_tcp_ack[0x1];
6563 	u8         outer_tcp_psh[0x1];
6564 	u8         outer_tcp_rst[0x1];
6565 	u8         outer_tcp_syn[0x1];
6566 	u8         outer_tcp_fin[0x1];
6567 };
6568 
6569 struct mlx5_ifc_match_definer_format_22_bits {
6570 	u8         reserved_at_0[0x100];
6571 
6572 	u8         outer_ip_src_addr[0x20];
6573 
6574 	u8         outer_ip_dest_addr[0x20];
6575 
6576 	u8         outer_l4_sport[0x10];
6577 	u8         outer_l4_dport[0x10];
6578 
6579 	u8         reserved_at_160[0x1];
6580 	u8         sx_sniffer[0x1];
6581 	u8         functional_lb[0x1];
6582 	u8         outer_ip_frag[0x1];
6583 	u8         outer_qp_type[0x2];
6584 	u8         outer_encap_type[0x2];
6585 	u8         port_number[0x2];
6586 	u8         outer_l3_type[0x2];
6587 	u8         outer_l4_type[0x2];
6588 	u8         outer_first_vlan_type[0x2];
6589 	u8         outer_first_vlan_prio[0x3];
6590 	u8         outer_first_vlan_cfi[0x1];
6591 	u8         outer_first_vlan_vid[0xc];
6592 
6593 	u8         metadata_reg_c_0[0x20];
6594 
6595 	u8         outer_dmac_47_16[0x20];
6596 
6597 	u8         outer_smac_47_16[0x20];
6598 
6599 	u8         outer_smac_15_0[0x10];
6600 	u8         outer_dmac_15_0[0x10];
6601 };
6602 
6603 struct mlx5_ifc_match_definer_format_23_bits {
6604 	u8         reserved_at_0[0x100];
6605 
6606 	u8         inner_ip_src_addr[0x20];
6607 
6608 	u8         inner_ip_dest_addr[0x20];
6609 
6610 	u8         inner_l4_sport[0x10];
6611 	u8         inner_l4_dport[0x10];
6612 
6613 	u8         reserved_at_160[0x1];
6614 	u8         sx_sniffer[0x1];
6615 	u8         functional_lb[0x1];
6616 	u8         inner_ip_frag[0x1];
6617 	u8         inner_qp_type[0x2];
6618 	u8         inner_encap_type[0x2];
6619 	u8         port_number[0x2];
6620 	u8         inner_l3_type[0x2];
6621 	u8         inner_l4_type[0x2];
6622 	u8         inner_first_vlan_type[0x2];
6623 	u8         inner_first_vlan_prio[0x3];
6624 	u8         inner_first_vlan_cfi[0x1];
6625 	u8         inner_first_vlan_vid[0xc];
6626 
6627 	u8         tunnel_header_0[0x20];
6628 
6629 	u8         inner_dmac_47_16[0x20];
6630 
6631 	u8         inner_smac_47_16[0x20];
6632 
6633 	u8         inner_smac_15_0[0x10];
6634 	u8         inner_dmac_15_0[0x10];
6635 };
6636 
6637 struct mlx5_ifc_match_definer_format_29_bits {
6638 	u8         reserved_at_0[0xc0];
6639 
6640 	u8         outer_ip_dest_addr[0x80];
6641 
6642 	u8         outer_ip_src_addr[0x80];
6643 
6644 	u8         outer_l4_sport[0x10];
6645 	u8         outer_l4_dport[0x10];
6646 
6647 	u8         reserved_at_1e0[0x20];
6648 };
6649 
6650 struct mlx5_ifc_match_definer_format_30_bits {
6651 	u8         reserved_at_0[0xa0];
6652 
6653 	u8         outer_ip_dest_addr[0x80];
6654 
6655 	u8         outer_ip_src_addr[0x80];
6656 
6657 	u8         outer_dmac_47_16[0x20];
6658 
6659 	u8         outer_smac_47_16[0x20];
6660 
6661 	u8         outer_smac_15_0[0x10];
6662 	u8         outer_dmac_15_0[0x10];
6663 };
6664 
6665 struct mlx5_ifc_match_definer_format_31_bits {
6666 	u8         reserved_at_0[0xc0];
6667 
6668 	u8         inner_ip_dest_addr[0x80];
6669 
6670 	u8         inner_ip_src_addr[0x80];
6671 
6672 	u8         inner_l4_sport[0x10];
6673 	u8         inner_l4_dport[0x10];
6674 
6675 	u8         reserved_at_1e0[0x20];
6676 };
6677 
6678 struct mlx5_ifc_match_definer_format_32_bits {
6679 	u8         reserved_at_0[0xa0];
6680 
6681 	u8         inner_ip_dest_addr[0x80];
6682 
6683 	u8         inner_ip_src_addr[0x80];
6684 
6685 	u8         inner_dmac_47_16[0x20];
6686 
6687 	u8         inner_smac_47_16[0x20];
6688 
6689 	u8         inner_smac_15_0[0x10];
6690 	u8         inner_dmac_15_0[0x10];
6691 };
6692 
6693 enum {
6694 	MLX5_IFC_DEFINER_FORMAT_ID_SELECT = 61,
6695 };
6696 
6697 #define MLX5_IFC_DEFINER_FORMAT_OFFSET_UNUSED 0x0
6698 #define MLX5_IFC_DEFINER_FORMAT_OFFSET_OUTER_ETH_PKT_LEN 0x48
6699 #define MLX5_IFC_DEFINER_DW_SELECTORS_NUM 9
6700 #define MLX5_IFC_DEFINER_BYTE_SELECTORS_NUM 8
6701 
6702 struct mlx5_ifc_match_definer_match_mask_bits {
6703 	u8         reserved_at_1c0[5][0x20];
6704 	u8         match_dw_8[0x20];
6705 	u8         match_dw_7[0x20];
6706 	u8         match_dw_6[0x20];
6707 	u8         match_dw_5[0x20];
6708 	u8         match_dw_4[0x20];
6709 	u8         match_dw_3[0x20];
6710 	u8         match_dw_2[0x20];
6711 	u8         match_dw_1[0x20];
6712 	u8         match_dw_0[0x20];
6713 
6714 	u8         match_byte_7[0x8];
6715 	u8         match_byte_6[0x8];
6716 	u8         match_byte_5[0x8];
6717 	u8         match_byte_4[0x8];
6718 
6719 	u8         match_byte_3[0x8];
6720 	u8         match_byte_2[0x8];
6721 	u8         match_byte_1[0x8];
6722 	u8         match_byte_0[0x8];
6723 };
6724 
6725 struct mlx5_ifc_match_definer_bits {
6726 	u8         modify_field_select[0x40];
6727 
6728 	u8         reserved_at_40[0x40];
6729 
6730 	u8         reserved_at_80[0x10];
6731 	u8         format_id[0x10];
6732 
6733 	u8         reserved_at_a0[0x60];
6734 
6735 	u8         format_select_dw3[0x8];
6736 	u8         format_select_dw2[0x8];
6737 	u8         format_select_dw1[0x8];
6738 	u8         format_select_dw0[0x8];
6739 
6740 	u8         format_select_dw7[0x8];
6741 	u8         format_select_dw6[0x8];
6742 	u8         format_select_dw5[0x8];
6743 	u8         format_select_dw4[0x8];
6744 
6745 	u8         reserved_at_100[0x18];
6746 	u8         format_select_dw8[0x8];
6747 
6748 	u8         reserved_at_120[0x20];
6749 
6750 	u8         format_select_byte3[0x8];
6751 	u8         format_select_byte2[0x8];
6752 	u8         format_select_byte1[0x8];
6753 	u8         format_select_byte0[0x8];
6754 
6755 	u8         format_select_byte7[0x8];
6756 	u8         format_select_byte6[0x8];
6757 	u8         format_select_byte5[0x8];
6758 	u8         format_select_byte4[0x8];
6759 
6760 	u8         reserved_at_180[0x40];
6761 
6762 	union {
6763 		struct {
6764 			u8         match_mask[16][0x20];
6765 		};
6766 		struct mlx5_ifc_match_definer_match_mask_bits match_mask_format;
6767 	};
6768 };
6769 
6770 struct mlx5_ifc_general_obj_create_param_bits {
6771 	u8         alias_object[0x1];
6772 	u8         reserved_at_1[0x2];
6773 	u8         log_obj_range[0x5];
6774 	u8         reserved_at_8[0x18];
6775 };
6776 
6777 struct mlx5_ifc_general_obj_query_param_bits {
6778 	u8         alias_object[0x1];
6779 	u8         obj_offset[0x1f];
6780 };
6781 
6782 struct mlx5_ifc_general_obj_in_cmd_hdr_bits {
6783 	u8         opcode[0x10];
6784 	u8         uid[0x10];
6785 
6786 	u8         vhca_tunnel_id[0x10];
6787 	u8         obj_type[0x10];
6788 
6789 	u8         obj_id[0x20];
6790 
6791 	union {
6792 		struct mlx5_ifc_general_obj_create_param_bits create;
6793 		struct mlx5_ifc_general_obj_query_param_bits query;
6794 	} op_param;
6795 };
6796 
6797 struct mlx5_ifc_general_obj_out_cmd_hdr_bits {
6798 	u8         status[0x8];
6799 	u8         reserved_at_8[0x18];
6800 
6801 	u8         syndrome[0x20];
6802 
6803 	u8         obj_id[0x20];
6804 
6805 	u8         reserved_at_60[0x20];
6806 };
6807 
6808 struct mlx5_ifc_allow_other_vhca_access_in_bits {
6809 	u8 opcode[0x10];
6810 	u8 uid[0x10];
6811 	u8 reserved_at_20[0x10];
6812 	u8 op_mod[0x10];
6813 	u8 reserved_at_40[0x50];
6814 	u8 object_type_to_be_accessed[0x10];
6815 	u8 object_id_to_be_accessed[0x20];
6816 	u8 reserved_at_c0[0x40];
6817 	union {
6818 		u8 access_key_raw[0x100];
6819 		u8 access_key[8][0x20];
6820 	};
6821 };
6822 
6823 struct mlx5_ifc_allow_other_vhca_access_out_bits {
6824 	u8 status[0x8];
6825 	u8 reserved_at_8[0x18];
6826 	u8 syndrome[0x20];
6827 	u8 reserved_at_40[0x40];
6828 };
6829 
6830 struct mlx5_ifc_modify_header_arg_bits {
6831 	u8         reserved_at_0[0x80];
6832 
6833 	u8         reserved_at_80[0x8];
6834 	u8         access_pd[0x18];
6835 };
6836 
6837 struct mlx5_ifc_create_modify_header_arg_in_bits {
6838 	struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
6839 	struct mlx5_ifc_modify_header_arg_bits arg;
6840 };
6841 
6842 struct mlx5_ifc_create_match_definer_in_bits {
6843 	struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
6844 
6845 	struct mlx5_ifc_match_definer_bits obj_context;
6846 };
6847 
6848 struct mlx5_ifc_create_match_definer_out_bits {
6849 	struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr;
6850 };
6851 
6852 struct mlx5_ifc_alias_context_bits {
6853 	u8 vhca_id_to_be_accessed[0x10];
6854 	u8 reserved_at_10[0xd];
6855 	u8 status[0x3];
6856 	u8 object_id_to_be_accessed[0x20];
6857 	u8 reserved_at_40[0x40];
6858 	union {
6859 		u8 access_key_raw[0x100];
6860 		u8 access_key[8][0x20];
6861 	};
6862 	u8 metadata[0x80];
6863 };
6864 
6865 struct mlx5_ifc_create_alias_obj_in_bits {
6866 	struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
6867 	struct mlx5_ifc_alias_context_bits alias_ctx;
6868 };
6869 
6870 enum {
6871 	MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS    = 0x0,
6872 	MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS  = 0x1,
6873 	MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS    = 0x2,
6874 	MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3,
6875 	MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_3 = 0x4,
6876 	MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_4 = 0x5,
6877 	MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_5 = 0x6,
6878 };
6879 
6880 struct mlx5_ifc_query_flow_group_out_bits {
6881 	u8         status[0x8];
6882 	u8         reserved_at_8[0x18];
6883 
6884 	u8         syndrome[0x20];
6885 
6886 	u8         reserved_at_40[0xa0];
6887 
6888 	u8         start_flow_index[0x20];
6889 
6890 	u8         reserved_at_100[0x20];
6891 
6892 	u8         end_flow_index[0x20];
6893 
6894 	u8         reserved_at_140[0xa0];
6895 
6896 	u8         reserved_at_1e0[0x18];
6897 	u8         match_criteria_enable[0x8];
6898 
6899 	struct mlx5_ifc_fte_match_param_bits match_criteria;
6900 
6901 	u8         reserved_at_1200[0xe00];
6902 };
6903 
6904 struct mlx5_ifc_query_flow_group_in_bits {
6905 	u8         opcode[0x10];
6906 	u8         reserved_at_10[0x10];
6907 
6908 	u8         reserved_at_20[0x10];
6909 	u8         op_mod[0x10];
6910 
6911 	u8         reserved_at_40[0x40];
6912 
6913 	u8         table_type[0x8];
6914 	u8         reserved_at_88[0x18];
6915 
6916 	u8         reserved_at_a0[0x8];
6917 	u8         table_id[0x18];
6918 
6919 	u8         group_id[0x20];
6920 
6921 	u8         reserved_at_e0[0x120];
6922 };
6923 
6924 struct mlx5_ifc_query_flow_counter_out_bits {
6925 	u8         status[0x8];
6926 	u8         reserved_at_8[0x18];
6927 
6928 	u8         syndrome[0x20];
6929 
6930 	u8         reserved_at_40[0x40];
6931 
6932 	struct mlx5_ifc_traffic_counter_bits flow_statistics[];
6933 };
6934 
6935 struct mlx5_ifc_query_flow_counter_in_bits {
6936 	u8         opcode[0x10];
6937 	u8         reserved_at_10[0x10];
6938 
6939 	u8         reserved_at_20[0x10];
6940 	u8         op_mod[0x10];
6941 
6942 	u8         reserved_at_40[0x80];
6943 
6944 	u8         clear[0x1];
6945 	u8         reserved_at_c1[0xf];
6946 	u8         num_of_counters[0x10];
6947 
6948 	u8         flow_counter_id[0x20];
6949 };
6950 
6951 struct mlx5_ifc_query_esw_vport_context_out_bits {
6952 	u8         status[0x8];
6953 	u8         reserved_at_8[0x18];
6954 
6955 	u8         syndrome[0x20];
6956 
6957 	u8         reserved_at_40[0x40];
6958 
6959 	struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
6960 };
6961 
6962 struct mlx5_ifc_query_esw_vport_context_in_bits {
6963 	u8         opcode[0x10];
6964 	u8         reserved_at_10[0x10];
6965 
6966 	u8         reserved_at_20[0x10];
6967 	u8         op_mod[0x10];
6968 
6969 	u8         other_vport[0x1];
6970 	u8         reserved_at_41[0xf];
6971 	u8         vport_number[0x10];
6972 
6973 	u8         reserved_at_60[0x20];
6974 };
6975 
6976 struct mlx5_ifc_modify_esw_vport_context_out_bits {
6977 	u8         status[0x8];
6978 	u8         reserved_at_8[0x18];
6979 
6980 	u8         syndrome[0x20];
6981 
6982 	u8         reserved_at_40[0x40];
6983 };
6984 
6985 struct mlx5_ifc_esw_vport_context_fields_select_bits {
6986 	u8         reserved_at_0[0x1b];
6987 	u8         fdb_to_vport_reg_c_id[0x1];
6988 	u8         vport_cvlan_insert[0x1];
6989 	u8         vport_svlan_insert[0x1];
6990 	u8         vport_cvlan_strip[0x1];
6991 	u8         vport_svlan_strip[0x1];
6992 };
6993 
6994 struct mlx5_ifc_modify_esw_vport_context_in_bits {
6995 	u8         opcode[0x10];
6996 	u8         reserved_at_10[0x10];
6997 
6998 	u8         reserved_at_20[0x10];
6999 	u8         op_mod[0x10];
7000 
7001 	u8         other_vport[0x1];
7002 	u8         reserved_at_41[0xf];
7003 	u8         vport_number[0x10];
7004 
7005 	struct mlx5_ifc_esw_vport_context_fields_select_bits field_select;
7006 
7007 	struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
7008 };
7009 
7010 struct mlx5_ifc_query_eq_out_bits {
7011 	u8         status[0x8];
7012 	u8         reserved_at_8[0x18];
7013 
7014 	u8         syndrome[0x20];
7015 
7016 	u8         reserved_at_40[0x40];
7017 
7018 	struct mlx5_ifc_eqc_bits eq_context_entry;
7019 
7020 	u8         reserved_at_280[0x40];
7021 
7022 	u8         event_bitmask[0x40];
7023 
7024 	u8         reserved_at_300[0x580];
7025 
7026 	u8         pas[][0x40];
7027 };
7028 
7029 struct mlx5_ifc_query_eq_in_bits {
7030 	u8         opcode[0x10];
7031 	u8         reserved_at_10[0x10];
7032 
7033 	u8         reserved_at_20[0x10];
7034 	u8         op_mod[0x10];
7035 
7036 	u8         reserved_at_40[0x18];
7037 	u8         eq_number[0x8];
7038 
7039 	u8         reserved_at_60[0x20];
7040 };
7041 
7042 struct mlx5_ifc_packet_reformat_context_in_bits {
7043 	u8         reformat_type[0x8];
7044 	u8         reserved_at_8[0x4];
7045 	u8         reformat_param_0[0x4];
7046 	u8         reserved_at_10[0x6];
7047 	u8         reformat_data_size[0xa];
7048 
7049 	u8         reformat_param_1[0x8];
7050 	u8         reserved_at_28[0x8];
7051 	u8         reformat_data[2][0x8];
7052 
7053 	u8         more_reformat_data[][0x8];
7054 };
7055 
7056 struct mlx5_ifc_query_packet_reformat_context_out_bits {
7057 	u8         status[0x8];
7058 	u8         reserved_at_8[0x18];
7059 
7060 	u8         syndrome[0x20];
7061 
7062 	u8         reserved_at_40[0xa0];
7063 
7064 	struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context[];
7065 };
7066 
7067 struct mlx5_ifc_query_packet_reformat_context_in_bits {
7068 	u8         opcode[0x10];
7069 	u8         reserved_at_10[0x10];
7070 
7071 	u8         reserved_at_20[0x10];
7072 	u8         op_mod[0x10];
7073 
7074 	u8         packet_reformat_id[0x20];
7075 
7076 	u8         reserved_at_60[0xa0];
7077 };
7078 
7079 struct mlx5_ifc_alloc_packet_reformat_context_out_bits {
7080 	u8         status[0x8];
7081 	u8         reserved_at_8[0x18];
7082 
7083 	u8         syndrome[0x20];
7084 
7085 	u8         packet_reformat_id[0x20];
7086 
7087 	u8         reserved_at_60[0x20];
7088 };
7089 
7090 enum {
7091 	MLX5_REFORMAT_CONTEXT_ANCHOR_MAC_START = 0x1,
7092 	MLX5_REFORMAT_CONTEXT_ANCHOR_VLAN_START = 0x2,
7093 	MLX5_REFORMAT_CONTEXT_ANCHOR_IP_START = 0x7,
7094 	MLX5_REFORMAT_CONTEXT_ANCHOR_TCP_UDP_START = 0x9,
7095 };
7096 
7097 enum mlx5_reformat_ctx_type {
7098 	MLX5_REFORMAT_TYPE_L2_TO_VXLAN = 0x0,
7099 	MLX5_REFORMAT_TYPE_L2_TO_NVGRE = 0x1,
7100 	MLX5_REFORMAT_TYPE_L2_TO_L2_TUNNEL = 0x2,
7101 	MLX5_REFORMAT_TYPE_L3_TUNNEL_TO_L2 = 0x3,
7102 	MLX5_REFORMAT_TYPE_L2_TO_L3_TUNNEL = 0x4,
7103 	MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_IPV4 = 0x5,
7104 	MLX5_REFORMAT_TYPE_L2_TO_L3_ESP_TUNNEL = 0x6,
7105 	MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_UDPV4 = 0x7,
7106 	MLX5_REFORMAT_TYPE_DEL_ESP_TRANSPORT = 0x8,
7107 	MLX5_REFORMAT_TYPE_L3_ESP_TUNNEL_TO_L2 = 0x9,
7108 	MLX5_REFORMAT_TYPE_DEL_ESP_TRANSPORT_OVER_UDP = 0xa,
7109 	MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_IPV6 = 0xb,
7110 	MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_UDPV6 = 0xc,
7111 	MLX5_REFORMAT_TYPE_INSERT_HDR = 0xf,
7112 	MLX5_REFORMAT_TYPE_REMOVE_HDR = 0x10,
7113 	MLX5_REFORMAT_TYPE_ADD_MACSEC = 0x11,
7114 	MLX5_REFORMAT_TYPE_DEL_MACSEC = 0x12,
7115 };
7116 
7117 struct mlx5_ifc_alloc_packet_reformat_context_in_bits {
7118 	u8         opcode[0x10];
7119 	u8         reserved_at_10[0x10];
7120 
7121 	u8         reserved_at_20[0x10];
7122 	u8         op_mod[0x10];
7123 
7124 	u8         reserved_at_40[0xa0];
7125 
7126 	struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context;
7127 };
7128 
7129 struct mlx5_ifc_dealloc_packet_reformat_context_out_bits {
7130 	u8         status[0x8];
7131 	u8         reserved_at_8[0x18];
7132 
7133 	u8         syndrome[0x20];
7134 
7135 	u8         reserved_at_40[0x40];
7136 };
7137 
7138 struct mlx5_ifc_dealloc_packet_reformat_context_in_bits {
7139 	u8         opcode[0x10];
7140 	u8         reserved_at_10[0x10];
7141 
7142 	u8         reserved_20[0x10];
7143 	u8         op_mod[0x10];
7144 
7145 	u8         packet_reformat_id[0x20];
7146 
7147 	u8         reserved_60[0x20];
7148 };
7149 
7150 struct mlx5_ifc_set_action_in_bits {
7151 	u8         action_type[0x4];
7152 	u8         field[0xc];
7153 	u8         reserved_at_10[0x3];
7154 	u8         offset[0x5];
7155 	u8         reserved_at_18[0x3];
7156 	u8         length[0x5];
7157 
7158 	u8         data[0x20];
7159 };
7160 
7161 struct mlx5_ifc_add_action_in_bits {
7162 	u8         action_type[0x4];
7163 	u8         field[0xc];
7164 	u8         reserved_at_10[0x10];
7165 
7166 	u8         data[0x20];
7167 };
7168 
7169 struct mlx5_ifc_copy_action_in_bits {
7170 	u8         action_type[0x4];
7171 	u8         src_field[0xc];
7172 	u8         reserved_at_10[0x3];
7173 	u8         src_offset[0x5];
7174 	u8         reserved_at_18[0x3];
7175 	u8         length[0x5];
7176 
7177 	u8         reserved_at_20[0x4];
7178 	u8         dst_field[0xc];
7179 	u8         reserved_at_30[0x3];
7180 	u8         dst_offset[0x5];
7181 	u8         reserved_at_38[0x8];
7182 };
7183 
7184 union mlx5_ifc_set_add_copy_action_in_auto_bits {
7185 	struct mlx5_ifc_set_action_in_bits  set_action_in;
7186 	struct mlx5_ifc_add_action_in_bits  add_action_in;
7187 	struct mlx5_ifc_copy_action_in_bits copy_action_in;
7188 	u8         reserved_at_0[0x40];
7189 };
7190 
7191 enum {
7192 	MLX5_ACTION_TYPE_SET   = 0x1,
7193 	MLX5_ACTION_TYPE_ADD   = 0x2,
7194 	MLX5_ACTION_TYPE_COPY  = 0x3,
7195 };
7196 
7197 enum {
7198 	MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16    = 0x1,
7199 	MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0     = 0x2,
7200 	MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE     = 0x3,
7201 	MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16    = 0x4,
7202 	MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0     = 0x5,
7203 	MLX5_ACTION_IN_FIELD_OUT_IP_DSCP       = 0x6,
7204 	MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS     = 0x7,
7205 	MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT     = 0x8,
7206 	MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT     = 0x9,
7207 	MLX5_ACTION_IN_FIELD_OUT_IP_TTL        = 0xa,
7208 	MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT     = 0xb,
7209 	MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT     = 0xc,
7210 	MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96  = 0xd,
7211 	MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64   = 0xe,
7212 	MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32   = 0xf,
7213 	MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0    = 0x10,
7214 	MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96  = 0x11,
7215 	MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64   = 0x12,
7216 	MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32   = 0x13,
7217 	MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0    = 0x14,
7218 	MLX5_ACTION_IN_FIELD_OUT_SIPV4         = 0x15,
7219 	MLX5_ACTION_IN_FIELD_OUT_DIPV4         = 0x16,
7220 	MLX5_ACTION_IN_FIELD_OUT_FIRST_VID     = 0x17,
7221 	MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47,
7222 	MLX5_ACTION_IN_FIELD_METADATA_REG_A    = 0x49,
7223 	MLX5_ACTION_IN_FIELD_METADATA_REG_B    = 0x50,
7224 	MLX5_ACTION_IN_FIELD_METADATA_REG_C_0  = 0x51,
7225 	MLX5_ACTION_IN_FIELD_METADATA_REG_C_1  = 0x52,
7226 	MLX5_ACTION_IN_FIELD_METADATA_REG_C_2  = 0x53,
7227 	MLX5_ACTION_IN_FIELD_METADATA_REG_C_3  = 0x54,
7228 	MLX5_ACTION_IN_FIELD_METADATA_REG_C_4  = 0x55,
7229 	MLX5_ACTION_IN_FIELD_METADATA_REG_C_5  = 0x56,
7230 	MLX5_ACTION_IN_FIELD_METADATA_REG_C_6  = 0x57,
7231 	MLX5_ACTION_IN_FIELD_METADATA_REG_C_7  = 0x58,
7232 	MLX5_ACTION_IN_FIELD_OUT_TCP_SEQ_NUM   = 0x59,
7233 	MLX5_ACTION_IN_FIELD_OUT_TCP_ACK_NUM   = 0x5B,
7234 	MLX5_ACTION_IN_FIELD_IPSEC_SYNDROME    = 0x5D,
7235 	MLX5_ACTION_IN_FIELD_OUT_EMD_47_32     = 0x6F,
7236 	MLX5_ACTION_IN_FIELD_OUT_EMD_31_0      = 0x70,
7237 };
7238 
7239 struct mlx5_ifc_alloc_modify_header_context_out_bits {
7240 	u8         status[0x8];
7241 	u8         reserved_at_8[0x18];
7242 
7243 	u8         syndrome[0x20];
7244 
7245 	u8         modify_header_id[0x20];
7246 
7247 	u8         reserved_at_60[0x20];
7248 };
7249 
7250 struct mlx5_ifc_alloc_modify_header_context_in_bits {
7251 	u8         opcode[0x10];
7252 	u8         reserved_at_10[0x10];
7253 
7254 	u8         reserved_at_20[0x10];
7255 	u8         op_mod[0x10];
7256 
7257 	u8         reserved_at_40[0x20];
7258 
7259 	u8         table_type[0x8];
7260 	u8         reserved_at_68[0x10];
7261 	u8         num_of_actions[0x8];
7262 
7263 	union mlx5_ifc_set_add_copy_action_in_auto_bits actions[];
7264 };
7265 
7266 struct mlx5_ifc_dealloc_modify_header_context_out_bits {
7267 	u8         status[0x8];
7268 	u8         reserved_at_8[0x18];
7269 
7270 	u8         syndrome[0x20];
7271 
7272 	u8         reserved_at_40[0x40];
7273 };
7274 
7275 struct mlx5_ifc_dealloc_modify_header_context_in_bits {
7276 	u8         opcode[0x10];
7277 	u8         reserved_at_10[0x10];
7278 
7279 	u8         reserved_at_20[0x10];
7280 	u8         op_mod[0x10];
7281 
7282 	u8         modify_header_id[0x20];
7283 
7284 	u8         reserved_at_60[0x20];
7285 };
7286 
7287 struct mlx5_ifc_query_modify_header_context_in_bits {
7288 	u8         opcode[0x10];
7289 	u8         uid[0x10];
7290 
7291 	u8         reserved_at_20[0x10];
7292 	u8         op_mod[0x10];
7293 
7294 	u8         modify_header_id[0x20];
7295 
7296 	u8         reserved_at_60[0xa0];
7297 };
7298 
7299 struct mlx5_ifc_query_dct_out_bits {
7300 	u8         status[0x8];
7301 	u8         reserved_at_8[0x18];
7302 
7303 	u8         syndrome[0x20];
7304 
7305 	u8         reserved_at_40[0x40];
7306 
7307 	struct mlx5_ifc_dctc_bits dct_context_entry;
7308 
7309 	u8         reserved_at_280[0x180];
7310 };
7311 
7312 struct mlx5_ifc_query_dct_in_bits {
7313 	u8         opcode[0x10];
7314 	u8         reserved_at_10[0x10];
7315 
7316 	u8         reserved_at_20[0x10];
7317 	u8         op_mod[0x10];
7318 
7319 	u8         reserved_at_40[0x8];
7320 	u8         dctn[0x18];
7321 
7322 	u8         reserved_at_60[0x20];
7323 };
7324 
7325 struct mlx5_ifc_query_cq_out_bits {
7326 	u8         status[0x8];
7327 	u8         reserved_at_8[0x18];
7328 
7329 	u8         syndrome[0x20];
7330 
7331 	u8         reserved_at_40[0x40];
7332 
7333 	struct mlx5_ifc_cqc_bits cq_context;
7334 
7335 	u8         reserved_at_280[0x600];
7336 
7337 	u8         pas[][0x40];
7338 };
7339 
7340 struct mlx5_ifc_query_cq_in_bits {
7341 	u8         opcode[0x10];
7342 	u8         reserved_at_10[0x10];
7343 
7344 	u8         reserved_at_20[0x10];
7345 	u8         op_mod[0x10];
7346 
7347 	u8         reserved_at_40[0x8];
7348 	u8         cqn[0x18];
7349 
7350 	u8         reserved_at_60[0x20];
7351 };
7352 
7353 struct mlx5_ifc_query_cong_status_out_bits {
7354 	u8         status[0x8];
7355 	u8         reserved_at_8[0x18];
7356 
7357 	u8         syndrome[0x20];
7358 
7359 	u8         reserved_at_40[0x20];
7360 
7361 	u8         enable[0x1];
7362 	u8         tag_enable[0x1];
7363 	u8         reserved_at_62[0x1e];
7364 };
7365 
7366 struct mlx5_ifc_query_cong_status_in_bits {
7367 	u8         opcode[0x10];
7368 	u8         reserved_at_10[0x10];
7369 
7370 	u8         reserved_at_20[0x10];
7371 	u8         op_mod[0x10];
7372 
7373 	u8         reserved_at_40[0x18];
7374 	u8         priority[0x4];
7375 	u8         cong_protocol[0x4];
7376 
7377 	u8         reserved_at_60[0x20];
7378 };
7379 
7380 struct mlx5_ifc_query_cong_statistics_out_bits {
7381 	u8         status[0x8];
7382 	u8         reserved_at_8[0x18];
7383 
7384 	u8         syndrome[0x20];
7385 
7386 	u8         reserved_at_40[0x40];
7387 
7388 	u8         rp_cur_flows[0x20];
7389 
7390 	u8         sum_flows[0x20];
7391 
7392 	u8         rp_cnp_ignored_high[0x20];
7393 
7394 	u8         rp_cnp_ignored_low[0x20];
7395 
7396 	u8         rp_cnp_handled_high[0x20];
7397 
7398 	u8         rp_cnp_handled_low[0x20];
7399 
7400 	u8         reserved_at_140[0x100];
7401 
7402 	u8         time_stamp_high[0x20];
7403 
7404 	u8         time_stamp_low[0x20];
7405 
7406 	u8         accumulators_period[0x20];
7407 
7408 	u8         np_ecn_marked_roce_packets_high[0x20];
7409 
7410 	u8         np_ecn_marked_roce_packets_low[0x20];
7411 
7412 	u8         np_cnp_sent_high[0x20];
7413 
7414 	u8         np_cnp_sent_low[0x20];
7415 
7416 	u8         reserved_at_320[0x560];
7417 };
7418 
7419 struct mlx5_ifc_query_cong_statistics_in_bits {
7420 	u8         opcode[0x10];
7421 	u8         reserved_at_10[0x10];
7422 
7423 	u8         reserved_at_20[0x10];
7424 	u8         op_mod[0x10];
7425 
7426 	u8         clear[0x1];
7427 	u8         reserved_at_41[0x1f];
7428 
7429 	u8         reserved_at_60[0x20];
7430 };
7431 
7432 struct mlx5_ifc_query_cong_params_out_bits {
7433 	u8         status[0x8];
7434 	u8         reserved_at_8[0x18];
7435 
7436 	u8         syndrome[0x20];
7437 
7438 	u8         reserved_at_40[0x40];
7439 
7440 	union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
7441 };
7442 
7443 struct mlx5_ifc_query_cong_params_in_bits {
7444 	u8         opcode[0x10];
7445 	u8         reserved_at_10[0x10];
7446 
7447 	u8         reserved_at_20[0x10];
7448 	u8         op_mod[0x10];
7449 
7450 	u8         reserved_at_40[0x1c];
7451 	u8         cong_protocol[0x4];
7452 
7453 	u8         reserved_at_60[0x20];
7454 };
7455 
7456 struct mlx5_ifc_query_adapter_out_bits {
7457 	u8         status[0x8];
7458 	u8         reserved_at_8[0x18];
7459 
7460 	u8         syndrome[0x20];
7461 
7462 	u8         reserved_at_40[0x40];
7463 
7464 	struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct;
7465 };
7466 
7467 struct mlx5_ifc_query_adapter_in_bits {
7468 	u8         opcode[0x10];
7469 	u8         reserved_at_10[0x10];
7470 
7471 	u8         reserved_at_20[0x10];
7472 	u8         op_mod[0x10];
7473 
7474 	u8         reserved_at_40[0x40];
7475 };
7476 
7477 struct mlx5_ifc_qp_2rst_out_bits {
7478 	u8         status[0x8];
7479 	u8         reserved_at_8[0x18];
7480 
7481 	u8         syndrome[0x20];
7482 
7483 	u8         reserved_at_40[0x40];
7484 };
7485 
7486 struct mlx5_ifc_qp_2rst_in_bits {
7487 	u8         opcode[0x10];
7488 	u8         uid[0x10];
7489 
7490 	u8         reserved_at_20[0x10];
7491 	u8         op_mod[0x10];
7492 
7493 	u8         reserved_at_40[0x8];
7494 	u8         qpn[0x18];
7495 
7496 	u8         reserved_at_60[0x20];
7497 };
7498 
7499 struct mlx5_ifc_qp_2err_out_bits {
7500 	u8         status[0x8];
7501 	u8         reserved_at_8[0x18];
7502 
7503 	u8         syndrome[0x20];
7504 
7505 	u8         reserved_at_40[0x40];
7506 };
7507 
7508 struct mlx5_ifc_qp_2err_in_bits {
7509 	u8         opcode[0x10];
7510 	u8         uid[0x10];
7511 
7512 	u8         reserved_at_20[0x10];
7513 	u8         op_mod[0x10];
7514 
7515 	u8         reserved_at_40[0x8];
7516 	u8         qpn[0x18];
7517 
7518 	u8         reserved_at_60[0x20];
7519 };
7520 
7521 struct mlx5_ifc_trans_page_fault_info_bits {
7522 	u8         error[0x1];
7523 	u8         reserved_at_1[0x4];
7524 	u8         page_fault_type[0x3];
7525 	u8         wq_number[0x18];
7526 
7527 	u8         reserved_at_20[0x8];
7528 	u8         fault_token[0x18];
7529 };
7530 
7531 struct mlx5_ifc_mem_page_fault_info_bits {
7532 	u8          error[0x1];
7533 	u8          reserved_at_1[0xf];
7534 	u8          fault_token_47_32[0x10];
7535 
7536 	u8          fault_token_31_0[0x20];
7537 };
7538 
7539 union mlx5_ifc_page_fault_resume_in_page_fault_info_auto_bits {
7540 	struct mlx5_ifc_trans_page_fault_info_bits trans_page_fault_info;
7541 	struct mlx5_ifc_mem_page_fault_info_bits mem_page_fault_info;
7542 	u8          reserved_at_0[0x40];
7543 };
7544 
7545 struct mlx5_ifc_page_fault_resume_out_bits {
7546 	u8         status[0x8];
7547 	u8         reserved_at_8[0x18];
7548 
7549 	u8         syndrome[0x20];
7550 
7551 	u8         reserved_at_40[0x40];
7552 };
7553 
7554 struct mlx5_ifc_page_fault_resume_in_bits {
7555 	u8         opcode[0x10];
7556 	u8         reserved_at_10[0x10];
7557 
7558 	u8         reserved_at_20[0x10];
7559 	u8         op_mod[0x10];
7560 
7561 	union mlx5_ifc_page_fault_resume_in_page_fault_info_auto_bits
7562 		page_fault_info;
7563 };
7564 
7565 struct mlx5_ifc_nop_out_bits {
7566 	u8         status[0x8];
7567 	u8         reserved_at_8[0x18];
7568 
7569 	u8         syndrome[0x20];
7570 
7571 	u8         reserved_at_40[0x40];
7572 };
7573 
7574 struct mlx5_ifc_nop_in_bits {
7575 	u8         opcode[0x10];
7576 	u8         reserved_at_10[0x10];
7577 
7578 	u8         reserved_at_20[0x10];
7579 	u8         op_mod[0x10];
7580 
7581 	u8         reserved_at_40[0x40];
7582 };
7583 
7584 struct mlx5_ifc_modify_vport_state_out_bits {
7585 	u8         status[0x8];
7586 	u8         reserved_at_8[0x18];
7587 
7588 	u8         syndrome[0x20];
7589 
7590 	u8         reserved_at_40[0x40];
7591 };
7592 
7593 struct mlx5_ifc_modify_vport_state_in_bits {
7594 	u8         opcode[0x10];
7595 	u8         reserved_at_10[0x10];
7596 
7597 	u8         reserved_at_20[0x10];
7598 	u8         op_mod[0x10];
7599 
7600 	u8         other_vport[0x1];
7601 	u8         reserved_at_41[0xf];
7602 	u8         vport_number[0x10];
7603 
7604 	u8         reserved_at_60[0x18];
7605 	u8         admin_state[0x4];
7606 	u8         reserved_at_7c[0x4];
7607 };
7608 
7609 struct mlx5_ifc_modify_tis_out_bits {
7610 	u8         status[0x8];
7611 	u8         reserved_at_8[0x18];
7612 
7613 	u8         syndrome[0x20];
7614 
7615 	u8         reserved_at_40[0x40];
7616 };
7617 
7618 struct mlx5_ifc_modify_tis_bitmask_bits {
7619 	u8         reserved_at_0[0x20];
7620 
7621 	u8         reserved_at_20[0x1d];
7622 	u8         lag_tx_port_affinity[0x1];
7623 	u8         strict_lag_tx_port_affinity[0x1];
7624 	u8         prio[0x1];
7625 };
7626 
7627 struct mlx5_ifc_modify_tis_in_bits {
7628 	u8         opcode[0x10];
7629 	u8         uid[0x10];
7630 
7631 	u8         reserved_at_20[0x10];
7632 	u8         op_mod[0x10];
7633 
7634 	u8         reserved_at_40[0x8];
7635 	u8         tisn[0x18];
7636 
7637 	u8         reserved_at_60[0x20];
7638 
7639 	struct mlx5_ifc_modify_tis_bitmask_bits bitmask;
7640 
7641 	u8         reserved_at_c0[0x40];
7642 
7643 	struct mlx5_ifc_tisc_bits ctx;
7644 };
7645 
7646 struct mlx5_ifc_modify_tir_bitmask_bits {
7647 	u8	   reserved_at_0[0x20];
7648 
7649 	u8         reserved_at_20[0x1b];
7650 	u8         self_lb_en[0x1];
7651 	u8         reserved_at_3c[0x1];
7652 	u8         hash[0x1];
7653 	u8         reserved_at_3e[0x1];
7654 	u8         packet_merge[0x1];
7655 };
7656 
7657 struct mlx5_ifc_modify_tir_out_bits {
7658 	u8         status[0x8];
7659 	u8         reserved_at_8[0x18];
7660 
7661 	u8         syndrome[0x20];
7662 
7663 	u8         reserved_at_40[0x40];
7664 };
7665 
7666 struct mlx5_ifc_modify_tir_in_bits {
7667 	u8         opcode[0x10];
7668 	u8         uid[0x10];
7669 
7670 	u8         reserved_at_20[0x10];
7671 	u8         op_mod[0x10];
7672 
7673 	u8         reserved_at_40[0x8];
7674 	u8         tirn[0x18];
7675 
7676 	u8         reserved_at_60[0x20];
7677 
7678 	struct mlx5_ifc_modify_tir_bitmask_bits bitmask;
7679 
7680 	u8         reserved_at_c0[0x40];
7681 
7682 	struct mlx5_ifc_tirc_bits ctx;
7683 };
7684 
7685 struct mlx5_ifc_modify_sq_out_bits {
7686 	u8         status[0x8];
7687 	u8         reserved_at_8[0x18];
7688 
7689 	u8         syndrome[0x20];
7690 
7691 	u8         reserved_at_40[0x40];
7692 };
7693 
7694 struct mlx5_ifc_modify_sq_in_bits {
7695 	u8         opcode[0x10];
7696 	u8         uid[0x10];
7697 
7698 	u8         reserved_at_20[0x10];
7699 	u8         op_mod[0x10];
7700 
7701 	u8         sq_state[0x4];
7702 	u8         reserved_at_44[0x4];
7703 	u8         sqn[0x18];
7704 
7705 	u8         reserved_at_60[0x20];
7706 
7707 	u8         modify_bitmask[0x40];
7708 
7709 	u8         reserved_at_c0[0x40];
7710 
7711 	struct mlx5_ifc_sqc_bits ctx;
7712 };
7713 
7714 struct mlx5_ifc_modify_scheduling_element_out_bits {
7715 	u8         status[0x8];
7716 	u8         reserved_at_8[0x18];
7717 
7718 	u8         syndrome[0x20];
7719 
7720 	u8         reserved_at_40[0x1c0];
7721 };
7722 
7723 enum {
7724 	MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1,
7725 	MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2,
7726 };
7727 
7728 struct mlx5_ifc_modify_scheduling_element_in_bits {
7729 	u8         opcode[0x10];
7730 	u8         reserved_at_10[0x10];
7731 
7732 	u8         reserved_at_20[0x10];
7733 	u8         op_mod[0x10];
7734 
7735 	u8         scheduling_hierarchy[0x8];
7736 	u8         reserved_at_48[0x18];
7737 
7738 	u8         scheduling_element_id[0x20];
7739 
7740 	u8         reserved_at_80[0x20];
7741 
7742 	u8         modify_bitmask[0x20];
7743 
7744 	u8         reserved_at_c0[0x40];
7745 
7746 	struct mlx5_ifc_scheduling_context_bits scheduling_context;
7747 
7748 	u8         reserved_at_300[0x100];
7749 };
7750 
7751 struct mlx5_ifc_modify_rqt_out_bits {
7752 	u8         status[0x8];
7753 	u8         reserved_at_8[0x18];
7754 
7755 	u8         syndrome[0x20];
7756 
7757 	u8         reserved_at_40[0x40];
7758 };
7759 
7760 struct mlx5_ifc_rqt_bitmask_bits {
7761 	u8	   reserved_at_0[0x20];
7762 
7763 	u8         reserved_at_20[0x1f];
7764 	u8         rqn_list[0x1];
7765 };
7766 
7767 struct mlx5_ifc_modify_rqt_in_bits {
7768 	u8         opcode[0x10];
7769 	u8         uid[0x10];
7770 
7771 	u8         reserved_at_20[0x10];
7772 	u8         op_mod[0x10];
7773 
7774 	u8         reserved_at_40[0x8];
7775 	u8         rqtn[0x18];
7776 
7777 	u8         reserved_at_60[0x20];
7778 
7779 	struct mlx5_ifc_rqt_bitmask_bits bitmask;
7780 
7781 	u8         reserved_at_c0[0x40];
7782 
7783 	struct mlx5_ifc_rqtc_bits ctx;
7784 };
7785 
7786 struct mlx5_ifc_modify_rq_out_bits {
7787 	u8         status[0x8];
7788 	u8         reserved_at_8[0x18];
7789 
7790 	u8         syndrome[0x20];
7791 
7792 	u8         reserved_at_40[0x40];
7793 };
7794 
7795 enum {
7796 	MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1,
7797 	MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2,
7798 	MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3,
7799 };
7800 
7801 struct mlx5_ifc_modify_rq_in_bits {
7802 	u8         opcode[0x10];
7803 	u8         uid[0x10];
7804 
7805 	u8         reserved_at_20[0x10];
7806 	u8         op_mod[0x10];
7807 
7808 	u8         rq_state[0x4];
7809 	u8         reserved_at_44[0x4];
7810 	u8         rqn[0x18];
7811 
7812 	u8         reserved_at_60[0x20];
7813 
7814 	u8         modify_bitmask[0x40];
7815 
7816 	u8         reserved_at_c0[0x40];
7817 
7818 	struct mlx5_ifc_rqc_bits ctx;
7819 };
7820 
7821 struct mlx5_ifc_modify_rmp_out_bits {
7822 	u8         status[0x8];
7823 	u8         reserved_at_8[0x18];
7824 
7825 	u8         syndrome[0x20];
7826 
7827 	u8         reserved_at_40[0x40];
7828 };
7829 
7830 struct mlx5_ifc_rmp_bitmask_bits {
7831 	u8	   reserved_at_0[0x20];
7832 
7833 	u8         reserved_at_20[0x1f];
7834 	u8         lwm[0x1];
7835 };
7836 
7837 struct mlx5_ifc_modify_rmp_in_bits {
7838 	u8         opcode[0x10];
7839 	u8         uid[0x10];
7840 
7841 	u8         reserved_at_20[0x10];
7842 	u8         op_mod[0x10];
7843 
7844 	u8         rmp_state[0x4];
7845 	u8         reserved_at_44[0x4];
7846 	u8         rmpn[0x18];
7847 
7848 	u8         reserved_at_60[0x20];
7849 
7850 	struct mlx5_ifc_rmp_bitmask_bits bitmask;
7851 
7852 	u8         reserved_at_c0[0x40];
7853 
7854 	struct mlx5_ifc_rmpc_bits ctx;
7855 };
7856 
7857 struct mlx5_ifc_modify_nic_vport_context_out_bits {
7858 	u8         status[0x8];
7859 	u8         reserved_at_8[0x18];
7860 
7861 	u8         syndrome[0x20];
7862 
7863 	u8         reserved_at_40[0x40];
7864 };
7865 
7866 struct mlx5_ifc_modify_nic_vport_field_select_bits {
7867 	u8         reserved_at_0[0x12];
7868 	u8	   affiliation[0x1];
7869 	u8	   reserved_at_13[0x1];
7870 	u8         disable_uc_local_lb[0x1];
7871 	u8         disable_mc_local_lb[0x1];
7872 	u8         node_guid[0x1];
7873 	u8         port_guid[0x1];
7874 	u8         min_inline[0x1];
7875 	u8         mtu[0x1];
7876 	u8         change_event[0x1];
7877 	u8         promisc[0x1];
7878 	u8         permanent_address[0x1];
7879 	u8         addresses_list[0x1];
7880 	u8         roce_en[0x1];
7881 	u8         reserved_at_1f[0x1];
7882 };
7883 
7884 struct mlx5_ifc_modify_nic_vport_context_in_bits {
7885 	u8         opcode[0x10];
7886 	u8         reserved_at_10[0x10];
7887 
7888 	u8         reserved_at_20[0x10];
7889 	u8         op_mod[0x10];
7890 
7891 	u8         other_vport[0x1];
7892 	u8         reserved_at_41[0xf];
7893 	u8         vport_number[0x10];
7894 
7895 	struct mlx5_ifc_modify_nic_vport_field_select_bits field_select;
7896 
7897 	u8         reserved_at_80[0x780];
7898 
7899 	struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
7900 };
7901 
7902 struct mlx5_ifc_modify_hca_vport_context_out_bits {
7903 	u8         status[0x8];
7904 	u8         reserved_at_8[0x18];
7905 
7906 	u8         syndrome[0x20];
7907 
7908 	u8         reserved_at_40[0x40];
7909 };
7910 
7911 struct mlx5_ifc_modify_hca_vport_context_in_bits {
7912 	u8         opcode[0x10];
7913 	u8         reserved_at_10[0x10];
7914 
7915 	u8         reserved_at_20[0x10];
7916 	u8         op_mod[0x10];
7917 
7918 	u8         other_vport[0x1];
7919 	u8         reserved_at_41[0xb];
7920 	u8         port_num[0x4];
7921 	u8         vport_number[0x10];
7922 
7923 	u8         reserved_at_60[0x20];
7924 
7925 	struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
7926 };
7927 
7928 struct mlx5_ifc_modify_cq_out_bits {
7929 	u8         status[0x8];
7930 	u8         reserved_at_8[0x18];
7931 
7932 	u8         syndrome[0x20];
7933 
7934 	u8         reserved_at_40[0x40];
7935 };
7936 
7937 enum {
7938 	MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ  = 0x0,
7939 	MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ  = 0x1,
7940 };
7941 
7942 struct mlx5_ifc_modify_cq_in_bits {
7943 	u8         opcode[0x10];
7944 	u8         uid[0x10];
7945 
7946 	u8         reserved_at_20[0x10];
7947 	u8         op_mod[0x10];
7948 
7949 	u8         reserved_at_40[0x8];
7950 	u8         cqn[0x18];
7951 
7952 	union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select;
7953 
7954 	struct mlx5_ifc_cqc_bits cq_context;
7955 
7956 	u8         reserved_at_280[0x60];
7957 
7958 	u8         cq_umem_valid[0x1];
7959 	u8         reserved_at_2e1[0x1f];
7960 
7961 	u8         reserved_at_300[0x580];
7962 
7963 	u8         pas[][0x40];
7964 };
7965 
7966 struct mlx5_ifc_modify_cong_status_out_bits {
7967 	u8         status[0x8];
7968 	u8         reserved_at_8[0x18];
7969 
7970 	u8         syndrome[0x20];
7971 
7972 	u8         reserved_at_40[0x40];
7973 };
7974 
7975 struct mlx5_ifc_modify_cong_status_in_bits {
7976 	u8         opcode[0x10];
7977 	u8         reserved_at_10[0x10];
7978 
7979 	u8         reserved_at_20[0x10];
7980 	u8         op_mod[0x10];
7981 
7982 	u8         reserved_at_40[0x18];
7983 	u8         priority[0x4];
7984 	u8         cong_protocol[0x4];
7985 
7986 	u8         enable[0x1];
7987 	u8         tag_enable[0x1];
7988 	u8         reserved_at_62[0x1e];
7989 };
7990 
7991 struct mlx5_ifc_modify_cong_params_out_bits {
7992 	u8         status[0x8];
7993 	u8         reserved_at_8[0x18];
7994 
7995 	u8         syndrome[0x20];
7996 
7997 	u8         reserved_at_40[0x40];
7998 };
7999 
8000 struct mlx5_ifc_modify_cong_params_in_bits {
8001 	u8         opcode[0x10];
8002 	u8         reserved_at_10[0x10];
8003 
8004 	u8         reserved_at_20[0x10];
8005 	u8         op_mod[0x10];
8006 
8007 	u8         reserved_at_40[0x1c];
8008 	u8         cong_protocol[0x4];
8009 
8010 	union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select;
8011 
8012 	u8         reserved_at_80[0x80];
8013 
8014 	union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
8015 };
8016 
8017 struct mlx5_ifc_manage_pages_out_bits {
8018 	u8         status[0x8];
8019 	u8         reserved_at_8[0x18];
8020 
8021 	u8         syndrome[0x20];
8022 
8023 	u8         output_num_entries[0x20];
8024 
8025 	u8         reserved_at_60[0x20];
8026 
8027 	u8         pas[][0x40];
8028 };
8029 
8030 enum {
8031 	MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL     = 0x0,
8032 	MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS  = 0x1,
8033 	MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES    = 0x2,
8034 };
8035 
8036 struct mlx5_ifc_manage_pages_in_bits {
8037 	u8         opcode[0x10];
8038 	u8         reserved_at_10[0x10];
8039 
8040 	u8         reserved_at_20[0x10];
8041 	u8         op_mod[0x10];
8042 
8043 	u8         embedded_cpu_function[0x1];
8044 	u8         reserved_at_41[0xf];
8045 	u8         function_id[0x10];
8046 
8047 	u8         input_num_entries[0x20];
8048 
8049 	u8         pas[][0x40];
8050 };
8051 
8052 struct mlx5_ifc_mad_ifc_out_bits {
8053 	u8         status[0x8];
8054 	u8         reserved_at_8[0x18];
8055 
8056 	u8         syndrome[0x20];
8057 
8058 	u8         reserved_at_40[0x40];
8059 
8060 	u8         response_mad_packet[256][0x8];
8061 };
8062 
8063 struct mlx5_ifc_mad_ifc_in_bits {
8064 	u8         opcode[0x10];
8065 	u8         reserved_at_10[0x10];
8066 
8067 	u8         reserved_at_20[0x10];
8068 	u8         op_mod[0x10];
8069 
8070 	u8         remote_lid[0x10];
8071 	u8         plane_index[0x8];
8072 	u8         port[0x8];
8073 
8074 	u8         reserved_at_60[0x20];
8075 
8076 	u8         mad[256][0x8];
8077 };
8078 
8079 struct mlx5_ifc_init_hca_out_bits {
8080 	u8         status[0x8];
8081 	u8         reserved_at_8[0x18];
8082 
8083 	u8         syndrome[0x20];
8084 
8085 	u8         reserved_at_40[0x40];
8086 };
8087 
8088 struct mlx5_ifc_init_hca_in_bits {
8089 	u8         opcode[0x10];
8090 	u8         reserved_at_10[0x10];
8091 
8092 	u8         reserved_at_20[0x10];
8093 	u8         op_mod[0x10];
8094 
8095 	u8         reserved_at_40[0x20];
8096 
8097 	u8         reserved_at_60[0x2];
8098 	u8         sw_vhca_id[0xe];
8099 	u8         reserved_at_70[0x10];
8100 
8101 	u8	   sw_owner_id[4][0x20];
8102 };
8103 
8104 struct mlx5_ifc_init2rtr_qp_out_bits {
8105 	u8         status[0x8];
8106 	u8         reserved_at_8[0x18];
8107 
8108 	u8         syndrome[0x20];
8109 
8110 	u8         reserved_at_40[0x20];
8111 	u8         ece[0x20];
8112 };
8113 
8114 struct mlx5_ifc_init2rtr_qp_in_bits {
8115 	u8         opcode[0x10];
8116 	u8         uid[0x10];
8117 
8118 	u8         reserved_at_20[0x10];
8119 	u8         op_mod[0x10];
8120 
8121 	u8         reserved_at_40[0x8];
8122 	u8         qpn[0x18];
8123 
8124 	u8         reserved_at_60[0x20];
8125 
8126 	u8         opt_param_mask[0x20];
8127 
8128 	u8         ece[0x20];
8129 
8130 	struct mlx5_ifc_qpc_bits qpc;
8131 
8132 	u8         reserved_at_800[0x80];
8133 };
8134 
8135 struct mlx5_ifc_init2init_qp_out_bits {
8136 	u8         status[0x8];
8137 	u8         reserved_at_8[0x18];
8138 
8139 	u8         syndrome[0x20];
8140 
8141 	u8         reserved_at_40[0x20];
8142 	u8         ece[0x20];
8143 };
8144 
8145 struct mlx5_ifc_init2init_qp_in_bits {
8146 	u8         opcode[0x10];
8147 	u8         uid[0x10];
8148 
8149 	u8         reserved_at_20[0x10];
8150 	u8         op_mod[0x10];
8151 
8152 	u8         reserved_at_40[0x8];
8153 	u8         qpn[0x18];
8154 
8155 	u8         reserved_at_60[0x20];
8156 
8157 	u8         opt_param_mask[0x20];
8158 
8159 	u8         ece[0x20];
8160 
8161 	struct mlx5_ifc_qpc_bits qpc;
8162 
8163 	u8         reserved_at_800[0x80];
8164 };
8165 
8166 struct mlx5_ifc_get_dropped_packet_log_out_bits {
8167 	u8         status[0x8];
8168 	u8         reserved_at_8[0x18];
8169 
8170 	u8         syndrome[0x20];
8171 
8172 	u8         reserved_at_40[0x40];
8173 
8174 	u8         packet_headers_log[128][0x8];
8175 
8176 	u8         packet_syndrome[64][0x8];
8177 };
8178 
8179 struct mlx5_ifc_get_dropped_packet_log_in_bits {
8180 	u8         opcode[0x10];
8181 	u8         reserved_at_10[0x10];
8182 
8183 	u8         reserved_at_20[0x10];
8184 	u8         op_mod[0x10];
8185 
8186 	u8         reserved_at_40[0x40];
8187 };
8188 
8189 struct mlx5_ifc_gen_eqe_in_bits {
8190 	u8         opcode[0x10];
8191 	u8         reserved_at_10[0x10];
8192 
8193 	u8         reserved_at_20[0x10];
8194 	u8         op_mod[0x10];
8195 
8196 	u8         reserved_at_40[0x18];
8197 	u8         eq_number[0x8];
8198 
8199 	u8         reserved_at_60[0x20];
8200 
8201 	u8         eqe[64][0x8];
8202 };
8203 
8204 struct mlx5_ifc_gen_eq_out_bits {
8205 	u8         status[0x8];
8206 	u8         reserved_at_8[0x18];
8207 
8208 	u8         syndrome[0x20];
8209 
8210 	u8         reserved_at_40[0x40];
8211 };
8212 
8213 struct mlx5_ifc_enable_hca_out_bits {
8214 	u8         status[0x8];
8215 	u8         reserved_at_8[0x18];
8216 
8217 	u8         syndrome[0x20];
8218 
8219 	u8         reserved_at_40[0x20];
8220 };
8221 
8222 struct mlx5_ifc_enable_hca_in_bits {
8223 	u8         opcode[0x10];
8224 	u8         reserved_at_10[0x10];
8225 
8226 	u8         reserved_at_20[0x10];
8227 	u8         op_mod[0x10];
8228 
8229 	u8         embedded_cpu_function[0x1];
8230 	u8         reserved_at_41[0xf];
8231 	u8         function_id[0x10];
8232 
8233 	u8         reserved_at_60[0x20];
8234 };
8235 
8236 struct mlx5_ifc_drain_dct_out_bits {
8237 	u8         status[0x8];
8238 	u8         reserved_at_8[0x18];
8239 
8240 	u8         syndrome[0x20];
8241 
8242 	u8         reserved_at_40[0x40];
8243 };
8244 
8245 struct mlx5_ifc_drain_dct_in_bits {
8246 	u8         opcode[0x10];
8247 	u8         uid[0x10];
8248 
8249 	u8         reserved_at_20[0x10];
8250 	u8         op_mod[0x10];
8251 
8252 	u8         reserved_at_40[0x8];
8253 	u8         dctn[0x18];
8254 
8255 	u8         reserved_at_60[0x20];
8256 };
8257 
8258 struct mlx5_ifc_disable_hca_out_bits {
8259 	u8         status[0x8];
8260 	u8         reserved_at_8[0x18];
8261 
8262 	u8         syndrome[0x20];
8263 
8264 	u8         reserved_at_40[0x20];
8265 };
8266 
8267 struct mlx5_ifc_disable_hca_in_bits {
8268 	u8         opcode[0x10];
8269 	u8         reserved_at_10[0x10];
8270 
8271 	u8         reserved_at_20[0x10];
8272 	u8         op_mod[0x10];
8273 
8274 	u8         embedded_cpu_function[0x1];
8275 	u8         reserved_at_41[0xf];
8276 	u8         function_id[0x10];
8277 
8278 	u8         reserved_at_60[0x20];
8279 };
8280 
8281 struct mlx5_ifc_detach_from_mcg_out_bits {
8282 	u8         status[0x8];
8283 	u8         reserved_at_8[0x18];
8284 
8285 	u8         syndrome[0x20];
8286 
8287 	u8         reserved_at_40[0x40];
8288 };
8289 
8290 struct mlx5_ifc_detach_from_mcg_in_bits {
8291 	u8         opcode[0x10];
8292 	u8         uid[0x10];
8293 
8294 	u8         reserved_at_20[0x10];
8295 	u8         op_mod[0x10];
8296 
8297 	u8         reserved_at_40[0x8];
8298 	u8         qpn[0x18];
8299 
8300 	u8         reserved_at_60[0x20];
8301 
8302 	u8         multicast_gid[16][0x8];
8303 };
8304 
8305 struct mlx5_ifc_destroy_xrq_out_bits {
8306 	u8         status[0x8];
8307 	u8         reserved_at_8[0x18];
8308 
8309 	u8         syndrome[0x20];
8310 
8311 	u8         reserved_at_40[0x40];
8312 };
8313 
8314 struct mlx5_ifc_destroy_xrq_in_bits {
8315 	u8         opcode[0x10];
8316 	u8         uid[0x10];
8317 
8318 	u8         reserved_at_20[0x10];
8319 	u8         op_mod[0x10];
8320 
8321 	u8         reserved_at_40[0x8];
8322 	u8         xrqn[0x18];
8323 
8324 	u8         reserved_at_60[0x20];
8325 };
8326 
8327 struct mlx5_ifc_destroy_xrc_srq_out_bits {
8328 	u8         status[0x8];
8329 	u8         reserved_at_8[0x18];
8330 
8331 	u8         syndrome[0x20];
8332 
8333 	u8         reserved_at_40[0x40];
8334 };
8335 
8336 struct mlx5_ifc_destroy_xrc_srq_in_bits {
8337 	u8         opcode[0x10];
8338 	u8         uid[0x10];
8339 
8340 	u8         reserved_at_20[0x10];
8341 	u8         op_mod[0x10];
8342 
8343 	u8         reserved_at_40[0x8];
8344 	u8         xrc_srqn[0x18];
8345 
8346 	u8         reserved_at_60[0x20];
8347 };
8348 
8349 struct mlx5_ifc_destroy_tis_out_bits {
8350 	u8         status[0x8];
8351 	u8         reserved_at_8[0x18];
8352 
8353 	u8         syndrome[0x20];
8354 
8355 	u8         reserved_at_40[0x40];
8356 };
8357 
8358 struct mlx5_ifc_destroy_tis_in_bits {
8359 	u8         opcode[0x10];
8360 	u8         uid[0x10];
8361 
8362 	u8         reserved_at_20[0x10];
8363 	u8         op_mod[0x10];
8364 
8365 	u8         reserved_at_40[0x8];
8366 	u8         tisn[0x18];
8367 
8368 	u8         reserved_at_60[0x20];
8369 };
8370 
8371 struct mlx5_ifc_destroy_tir_out_bits {
8372 	u8         status[0x8];
8373 	u8         reserved_at_8[0x18];
8374 
8375 	u8         syndrome[0x20];
8376 
8377 	u8         reserved_at_40[0x40];
8378 };
8379 
8380 struct mlx5_ifc_destroy_tir_in_bits {
8381 	u8         opcode[0x10];
8382 	u8         uid[0x10];
8383 
8384 	u8         reserved_at_20[0x10];
8385 	u8         op_mod[0x10];
8386 
8387 	u8         reserved_at_40[0x8];
8388 	u8         tirn[0x18];
8389 
8390 	u8         reserved_at_60[0x20];
8391 };
8392 
8393 struct mlx5_ifc_destroy_srq_out_bits {
8394 	u8         status[0x8];
8395 	u8         reserved_at_8[0x18];
8396 
8397 	u8         syndrome[0x20];
8398 
8399 	u8         reserved_at_40[0x40];
8400 };
8401 
8402 struct mlx5_ifc_destroy_srq_in_bits {
8403 	u8         opcode[0x10];
8404 	u8         uid[0x10];
8405 
8406 	u8         reserved_at_20[0x10];
8407 	u8         op_mod[0x10];
8408 
8409 	u8         reserved_at_40[0x8];
8410 	u8         srqn[0x18];
8411 
8412 	u8         reserved_at_60[0x20];
8413 };
8414 
8415 struct mlx5_ifc_destroy_sq_out_bits {
8416 	u8         status[0x8];
8417 	u8         reserved_at_8[0x18];
8418 
8419 	u8         syndrome[0x20];
8420 
8421 	u8         reserved_at_40[0x40];
8422 };
8423 
8424 struct mlx5_ifc_destroy_sq_in_bits {
8425 	u8         opcode[0x10];
8426 	u8         uid[0x10];
8427 
8428 	u8         reserved_at_20[0x10];
8429 	u8         op_mod[0x10];
8430 
8431 	u8         reserved_at_40[0x8];
8432 	u8         sqn[0x18];
8433 
8434 	u8         reserved_at_60[0x20];
8435 };
8436 
8437 struct mlx5_ifc_destroy_scheduling_element_out_bits {
8438 	u8         status[0x8];
8439 	u8         reserved_at_8[0x18];
8440 
8441 	u8         syndrome[0x20];
8442 
8443 	u8         reserved_at_40[0x1c0];
8444 };
8445 
8446 struct mlx5_ifc_destroy_scheduling_element_in_bits {
8447 	u8         opcode[0x10];
8448 	u8         reserved_at_10[0x10];
8449 
8450 	u8         reserved_at_20[0x10];
8451 	u8         op_mod[0x10];
8452 
8453 	u8         scheduling_hierarchy[0x8];
8454 	u8         reserved_at_48[0x18];
8455 
8456 	u8         scheduling_element_id[0x20];
8457 
8458 	u8         reserved_at_80[0x180];
8459 };
8460 
8461 struct mlx5_ifc_destroy_rqt_out_bits {
8462 	u8         status[0x8];
8463 	u8         reserved_at_8[0x18];
8464 
8465 	u8         syndrome[0x20];
8466 
8467 	u8         reserved_at_40[0x40];
8468 };
8469 
8470 struct mlx5_ifc_destroy_rqt_in_bits {
8471 	u8         opcode[0x10];
8472 	u8         uid[0x10];
8473 
8474 	u8         reserved_at_20[0x10];
8475 	u8         op_mod[0x10];
8476 
8477 	u8         reserved_at_40[0x8];
8478 	u8         rqtn[0x18];
8479 
8480 	u8         reserved_at_60[0x20];
8481 };
8482 
8483 struct mlx5_ifc_destroy_rq_out_bits {
8484 	u8         status[0x8];
8485 	u8         reserved_at_8[0x18];
8486 
8487 	u8         syndrome[0x20];
8488 
8489 	u8         reserved_at_40[0x40];
8490 };
8491 
8492 struct mlx5_ifc_destroy_rq_in_bits {
8493 	u8         opcode[0x10];
8494 	u8         uid[0x10];
8495 
8496 	u8         reserved_at_20[0x10];
8497 	u8         op_mod[0x10];
8498 
8499 	u8         reserved_at_40[0x8];
8500 	u8         rqn[0x18];
8501 
8502 	u8         reserved_at_60[0x20];
8503 };
8504 
8505 struct mlx5_ifc_set_delay_drop_params_in_bits {
8506 	u8         opcode[0x10];
8507 	u8         reserved_at_10[0x10];
8508 
8509 	u8         reserved_at_20[0x10];
8510 	u8         op_mod[0x10];
8511 
8512 	u8         reserved_at_40[0x20];
8513 
8514 	u8         reserved_at_60[0x10];
8515 	u8         delay_drop_timeout[0x10];
8516 };
8517 
8518 struct mlx5_ifc_set_delay_drop_params_out_bits {
8519 	u8         status[0x8];
8520 	u8         reserved_at_8[0x18];
8521 
8522 	u8         syndrome[0x20];
8523 
8524 	u8         reserved_at_40[0x40];
8525 };
8526 
8527 struct mlx5_ifc_destroy_rmp_out_bits {
8528 	u8         status[0x8];
8529 	u8         reserved_at_8[0x18];
8530 
8531 	u8         syndrome[0x20];
8532 
8533 	u8         reserved_at_40[0x40];
8534 };
8535 
8536 struct mlx5_ifc_destroy_rmp_in_bits {
8537 	u8         opcode[0x10];
8538 	u8         uid[0x10];
8539 
8540 	u8         reserved_at_20[0x10];
8541 	u8         op_mod[0x10];
8542 
8543 	u8         reserved_at_40[0x8];
8544 	u8         rmpn[0x18];
8545 
8546 	u8         reserved_at_60[0x20];
8547 };
8548 
8549 struct mlx5_ifc_destroy_qp_out_bits {
8550 	u8         status[0x8];
8551 	u8         reserved_at_8[0x18];
8552 
8553 	u8         syndrome[0x20];
8554 
8555 	u8         reserved_at_40[0x40];
8556 };
8557 
8558 struct mlx5_ifc_destroy_qp_in_bits {
8559 	u8         opcode[0x10];
8560 	u8         uid[0x10];
8561 
8562 	u8         reserved_at_20[0x10];
8563 	u8         op_mod[0x10];
8564 
8565 	u8         reserved_at_40[0x8];
8566 	u8         qpn[0x18];
8567 
8568 	u8         reserved_at_60[0x20];
8569 };
8570 
8571 struct mlx5_ifc_destroy_psv_out_bits {
8572 	u8         status[0x8];
8573 	u8         reserved_at_8[0x18];
8574 
8575 	u8         syndrome[0x20];
8576 
8577 	u8         reserved_at_40[0x40];
8578 };
8579 
8580 struct mlx5_ifc_destroy_psv_in_bits {
8581 	u8         opcode[0x10];
8582 	u8         reserved_at_10[0x10];
8583 
8584 	u8         reserved_at_20[0x10];
8585 	u8         op_mod[0x10];
8586 
8587 	u8         reserved_at_40[0x8];
8588 	u8         psvn[0x18];
8589 
8590 	u8         reserved_at_60[0x20];
8591 };
8592 
8593 struct mlx5_ifc_destroy_mkey_out_bits {
8594 	u8         status[0x8];
8595 	u8         reserved_at_8[0x18];
8596 
8597 	u8         syndrome[0x20];
8598 
8599 	u8         reserved_at_40[0x40];
8600 };
8601 
8602 struct mlx5_ifc_destroy_mkey_in_bits {
8603 	u8         opcode[0x10];
8604 	u8         uid[0x10];
8605 
8606 	u8         reserved_at_20[0x10];
8607 	u8         op_mod[0x10];
8608 
8609 	u8         reserved_at_40[0x8];
8610 	u8         mkey_index[0x18];
8611 
8612 	u8         reserved_at_60[0x20];
8613 };
8614 
8615 struct mlx5_ifc_destroy_flow_table_out_bits {
8616 	u8         status[0x8];
8617 	u8         reserved_at_8[0x18];
8618 
8619 	u8         syndrome[0x20];
8620 
8621 	u8         reserved_at_40[0x40];
8622 };
8623 
8624 struct mlx5_ifc_destroy_flow_table_in_bits {
8625 	u8         opcode[0x10];
8626 	u8         reserved_at_10[0x10];
8627 
8628 	u8         reserved_at_20[0x10];
8629 	u8         op_mod[0x10];
8630 
8631 	u8         other_vport[0x1];
8632 	u8         reserved_at_41[0xf];
8633 	u8         vport_number[0x10];
8634 
8635 	u8         reserved_at_60[0x20];
8636 
8637 	u8         table_type[0x8];
8638 	u8         reserved_at_88[0x18];
8639 
8640 	u8         reserved_at_a0[0x8];
8641 	u8         table_id[0x18];
8642 
8643 	u8         reserved_at_c0[0x140];
8644 };
8645 
8646 struct mlx5_ifc_destroy_flow_group_out_bits {
8647 	u8         status[0x8];
8648 	u8         reserved_at_8[0x18];
8649 
8650 	u8         syndrome[0x20];
8651 
8652 	u8         reserved_at_40[0x40];
8653 };
8654 
8655 struct mlx5_ifc_destroy_flow_group_in_bits {
8656 	u8         opcode[0x10];
8657 	u8         reserved_at_10[0x10];
8658 
8659 	u8         reserved_at_20[0x10];
8660 	u8         op_mod[0x10];
8661 
8662 	u8         other_vport[0x1];
8663 	u8         reserved_at_41[0xf];
8664 	u8         vport_number[0x10];
8665 
8666 	u8         reserved_at_60[0x20];
8667 
8668 	u8         table_type[0x8];
8669 	u8         reserved_at_88[0x18];
8670 
8671 	u8         reserved_at_a0[0x8];
8672 	u8         table_id[0x18];
8673 
8674 	u8         group_id[0x20];
8675 
8676 	u8         reserved_at_e0[0x120];
8677 };
8678 
8679 struct mlx5_ifc_destroy_eq_out_bits {
8680 	u8         status[0x8];
8681 	u8         reserved_at_8[0x18];
8682 
8683 	u8         syndrome[0x20];
8684 
8685 	u8         reserved_at_40[0x40];
8686 };
8687 
8688 struct mlx5_ifc_destroy_eq_in_bits {
8689 	u8         opcode[0x10];
8690 	u8         reserved_at_10[0x10];
8691 
8692 	u8         reserved_at_20[0x10];
8693 	u8         op_mod[0x10];
8694 
8695 	u8         reserved_at_40[0x18];
8696 	u8         eq_number[0x8];
8697 
8698 	u8         reserved_at_60[0x20];
8699 };
8700 
8701 struct mlx5_ifc_destroy_dct_out_bits {
8702 	u8         status[0x8];
8703 	u8         reserved_at_8[0x18];
8704 
8705 	u8         syndrome[0x20];
8706 
8707 	u8         reserved_at_40[0x40];
8708 };
8709 
8710 struct mlx5_ifc_destroy_dct_in_bits {
8711 	u8         opcode[0x10];
8712 	u8         uid[0x10];
8713 
8714 	u8         reserved_at_20[0x10];
8715 	u8         op_mod[0x10];
8716 
8717 	u8         reserved_at_40[0x8];
8718 	u8         dctn[0x18];
8719 
8720 	u8         reserved_at_60[0x20];
8721 };
8722 
8723 struct mlx5_ifc_destroy_cq_out_bits {
8724 	u8         status[0x8];
8725 	u8         reserved_at_8[0x18];
8726 
8727 	u8         syndrome[0x20];
8728 
8729 	u8         reserved_at_40[0x40];
8730 };
8731 
8732 struct mlx5_ifc_destroy_cq_in_bits {
8733 	u8         opcode[0x10];
8734 	u8         uid[0x10];
8735 
8736 	u8         reserved_at_20[0x10];
8737 	u8         op_mod[0x10];
8738 
8739 	u8         reserved_at_40[0x8];
8740 	u8         cqn[0x18];
8741 
8742 	u8         reserved_at_60[0x20];
8743 };
8744 
8745 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits {
8746 	u8         status[0x8];
8747 	u8         reserved_at_8[0x18];
8748 
8749 	u8         syndrome[0x20];
8750 
8751 	u8         reserved_at_40[0x40];
8752 };
8753 
8754 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits {
8755 	u8         opcode[0x10];
8756 	u8         reserved_at_10[0x10];
8757 
8758 	u8         reserved_at_20[0x10];
8759 	u8         op_mod[0x10];
8760 
8761 	u8         reserved_at_40[0x20];
8762 
8763 	u8         reserved_at_60[0x10];
8764 	u8         vxlan_udp_port[0x10];
8765 };
8766 
8767 struct mlx5_ifc_delete_l2_table_entry_out_bits {
8768 	u8         status[0x8];
8769 	u8         reserved_at_8[0x18];
8770 
8771 	u8         syndrome[0x20];
8772 
8773 	u8         reserved_at_40[0x40];
8774 };
8775 
8776 struct mlx5_ifc_delete_l2_table_entry_in_bits {
8777 	u8         opcode[0x10];
8778 	u8         reserved_at_10[0x10];
8779 
8780 	u8         reserved_at_20[0x10];
8781 	u8         op_mod[0x10];
8782 
8783 	u8         reserved_at_40[0x60];
8784 
8785 	u8         reserved_at_a0[0x8];
8786 	u8         table_index[0x18];
8787 
8788 	u8         reserved_at_c0[0x140];
8789 };
8790 
8791 struct mlx5_ifc_delete_fte_out_bits {
8792 	u8         status[0x8];
8793 	u8         reserved_at_8[0x18];
8794 
8795 	u8         syndrome[0x20];
8796 
8797 	u8         reserved_at_40[0x40];
8798 };
8799 
8800 struct mlx5_ifc_delete_fte_in_bits {
8801 	u8         opcode[0x10];
8802 	u8         reserved_at_10[0x10];
8803 
8804 	u8         reserved_at_20[0x10];
8805 	u8         op_mod[0x10];
8806 
8807 	u8         other_vport[0x1];
8808 	u8         reserved_at_41[0xf];
8809 	u8         vport_number[0x10];
8810 
8811 	u8         reserved_at_60[0x20];
8812 
8813 	u8         table_type[0x8];
8814 	u8         reserved_at_88[0x18];
8815 
8816 	u8         reserved_at_a0[0x8];
8817 	u8         table_id[0x18];
8818 
8819 	u8         reserved_at_c0[0x40];
8820 
8821 	u8         flow_index[0x20];
8822 
8823 	u8         reserved_at_120[0xe0];
8824 };
8825 
8826 struct mlx5_ifc_dealloc_xrcd_out_bits {
8827 	u8         status[0x8];
8828 	u8         reserved_at_8[0x18];
8829 
8830 	u8         syndrome[0x20];
8831 
8832 	u8         reserved_at_40[0x40];
8833 };
8834 
8835 struct mlx5_ifc_dealloc_xrcd_in_bits {
8836 	u8         opcode[0x10];
8837 	u8         uid[0x10];
8838 
8839 	u8         reserved_at_20[0x10];
8840 	u8         op_mod[0x10];
8841 
8842 	u8         reserved_at_40[0x8];
8843 	u8         xrcd[0x18];
8844 
8845 	u8         reserved_at_60[0x20];
8846 };
8847 
8848 struct mlx5_ifc_dealloc_uar_out_bits {
8849 	u8         status[0x8];
8850 	u8         reserved_at_8[0x18];
8851 
8852 	u8         syndrome[0x20];
8853 
8854 	u8         reserved_at_40[0x40];
8855 };
8856 
8857 struct mlx5_ifc_dealloc_uar_in_bits {
8858 	u8         opcode[0x10];
8859 	u8         uid[0x10];
8860 
8861 	u8         reserved_at_20[0x10];
8862 	u8         op_mod[0x10];
8863 
8864 	u8         reserved_at_40[0x8];
8865 	u8         uar[0x18];
8866 
8867 	u8         reserved_at_60[0x20];
8868 };
8869 
8870 struct mlx5_ifc_dealloc_transport_domain_out_bits {
8871 	u8         status[0x8];
8872 	u8         reserved_at_8[0x18];
8873 
8874 	u8         syndrome[0x20];
8875 
8876 	u8         reserved_at_40[0x40];
8877 };
8878 
8879 struct mlx5_ifc_dealloc_transport_domain_in_bits {
8880 	u8         opcode[0x10];
8881 	u8         uid[0x10];
8882 
8883 	u8         reserved_at_20[0x10];
8884 	u8         op_mod[0x10];
8885 
8886 	u8         reserved_at_40[0x8];
8887 	u8         transport_domain[0x18];
8888 
8889 	u8         reserved_at_60[0x20];
8890 };
8891 
8892 struct mlx5_ifc_dealloc_q_counter_out_bits {
8893 	u8         status[0x8];
8894 	u8         reserved_at_8[0x18];
8895 
8896 	u8         syndrome[0x20];
8897 
8898 	u8         reserved_at_40[0x40];
8899 };
8900 
8901 struct mlx5_ifc_dealloc_q_counter_in_bits {
8902 	u8         opcode[0x10];
8903 	u8         reserved_at_10[0x10];
8904 
8905 	u8         reserved_at_20[0x10];
8906 	u8         op_mod[0x10];
8907 
8908 	u8         reserved_at_40[0x18];
8909 	u8         counter_set_id[0x8];
8910 
8911 	u8         reserved_at_60[0x20];
8912 };
8913 
8914 struct mlx5_ifc_dealloc_pd_out_bits {
8915 	u8         status[0x8];
8916 	u8         reserved_at_8[0x18];
8917 
8918 	u8         syndrome[0x20];
8919 
8920 	u8         reserved_at_40[0x40];
8921 };
8922 
8923 struct mlx5_ifc_dealloc_pd_in_bits {
8924 	u8         opcode[0x10];
8925 	u8         uid[0x10];
8926 
8927 	u8         reserved_at_20[0x10];
8928 	u8         op_mod[0x10];
8929 
8930 	u8         reserved_at_40[0x8];
8931 	u8         pd[0x18];
8932 
8933 	u8         reserved_at_60[0x20];
8934 };
8935 
8936 struct mlx5_ifc_dealloc_flow_counter_out_bits {
8937 	u8         status[0x8];
8938 	u8         reserved_at_8[0x18];
8939 
8940 	u8         syndrome[0x20];
8941 
8942 	u8         reserved_at_40[0x40];
8943 };
8944 
8945 struct mlx5_ifc_dealloc_flow_counter_in_bits {
8946 	u8         opcode[0x10];
8947 	u8         reserved_at_10[0x10];
8948 
8949 	u8         reserved_at_20[0x10];
8950 	u8         op_mod[0x10];
8951 
8952 	u8         flow_counter_id[0x20];
8953 
8954 	u8         reserved_at_60[0x20];
8955 };
8956 
8957 struct mlx5_ifc_create_xrq_out_bits {
8958 	u8         status[0x8];
8959 	u8         reserved_at_8[0x18];
8960 
8961 	u8         syndrome[0x20];
8962 
8963 	u8         reserved_at_40[0x8];
8964 	u8         xrqn[0x18];
8965 
8966 	u8         reserved_at_60[0x20];
8967 };
8968 
8969 struct mlx5_ifc_create_xrq_in_bits {
8970 	u8         opcode[0x10];
8971 	u8         uid[0x10];
8972 
8973 	u8         reserved_at_20[0x10];
8974 	u8         op_mod[0x10];
8975 
8976 	u8         reserved_at_40[0x40];
8977 
8978 	struct mlx5_ifc_xrqc_bits xrq_context;
8979 };
8980 
8981 struct mlx5_ifc_create_xrc_srq_out_bits {
8982 	u8         status[0x8];
8983 	u8         reserved_at_8[0x18];
8984 
8985 	u8         syndrome[0x20];
8986 
8987 	u8         reserved_at_40[0x8];
8988 	u8         xrc_srqn[0x18];
8989 
8990 	u8         reserved_at_60[0x20];
8991 };
8992 
8993 struct mlx5_ifc_create_xrc_srq_in_bits {
8994 	u8         opcode[0x10];
8995 	u8         uid[0x10];
8996 
8997 	u8         reserved_at_20[0x10];
8998 	u8         op_mod[0x10];
8999 
9000 	u8         reserved_at_40[0x40];
9001 
9002 	struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
9003 
9004 	u8         reserved_at_280[0x60];
9005 
9006 	u8         xrc_srq_umem_valid[0x1];
9007 	u8         reserved_at_2e1[0x1f];
9008 
9009 	u8         reserved_at_300[0x580];
9010 
9011 	u8         pas[][0x40];
9012 };
9013 
9014 struct mlx5_ifc_create_tis_out_bits {
9015 	u8         status[0x8];
9016 	u8         reserved_at_8[0x18];
9017 
9018 	u8         syndrome[0x20];
9019 
9020 	u8         reserved_at_40[0x8];
9021 	u8         tisn[0x18];
9022 
9023 	u8         reserved_at_60[0x20];
9024 };
9025 
9026 struct mlx5_ifc_create_tis_in_bits {
9027 	u8         opcode[0x10];
9028 	u8         uid[0x10];
9029 
9030 	u8         reserved_at_20[0x10];
9031 	u8         op_mod[0x10];
9032 
9033 	u8         reserved_at_40[0xc0];
9034 
9035 	struct mlx5_ifc_tisc_bits ctx;
9036 };
9037 
9038 struct mlx5_ifc_create_tir_out_bits {
9039 	u8         status[0x8];
9040 	u8         icm_address_63_40[0x18];
9041 
9042 	u8         syndrome[0x20];
9043 
9044 	u8         icm_address_39_32[0x8];
9045 	u8         tirn[0x18];
9046 
9047 	u8         icm_address_31_0[0x20];
9048 };
9049 
9050 struct mlx5_ifc_create_tir_in_bits {
9051 	u8         opcode[0x10];
9052 	u8         uid[0x10];
9053 
9054 	u8         reserved_at_20[0x10];
9055 	u8         op_mod[0x10];
9056 
9057 	u8         reserved_at_40[0xc0];
9058 
9059 	struct mlx5_ifc_tirc_bits ctx;
9060 };
9061 
9062 struct mlx5_ifc_create_srq_out_bits {
9063 	u8         status[0x8];
9064 	u8         reserved_at_8[0x18];
9065 
9066 	u8         syndrome[0x20];
9067 
9068 	u8         reserved_at_40[0x8];
9069 	u8         srqn[0x18];
9070 
9071 	u8         reserved_at_60[0x20];
9072 };
9073 
9074 struct mlx5_ifc_create_srq_in_bits {
9075 	u8         opcode[0x10];
9076 	u8         uid[0x10];
9077 
9078 	u8         reserved_at_20[0x10];
9079 	u8         op_mod[0x10];
9080 
9081 	u8         reserved_at_40[0x40];
9082 
9083 	struct mlx5_ifc_srqc_bits srq_context_entry;
9084 
9085 	u8         reserved_at_280[0x600];
9086 
9087 	u8         pas[][0x40];
9088 };
9089 
9090 struct mlx5_ifc_create_sq_out_bits {
9091 	u8         status[0x8];
9092 	u8         reserved_at_8[0x18];
9093 
9094 	u8         syndrome[0x20];
9095 
9096 	u8         reserved_at_40[0x8];
9097 	u8         sqn[0x18];
9098 
9099 	u8         reserved_at_60[0x20];
9100 };
9101 
9102 struct mlx5_ifc_create_sq_in_bits {
9103 	u8         opcode[0x10];
9104 	u8         uid[0x10];
9105 
9106 	u8         reserved_at_20[0x10];
9107 	u8         op_mod[0x10];
9108 
9109 	u8         reserved_at_40[0xc0];
9110 
9111 	struct mlx5_ifc_sqc_bits ctx;
9112 };
9113 
9114 struct mlx5_ifc_create_scheduling_element_out_bits {
9115 	u8         status[0x8];
9116 	u8         reserved_at_8[0x18];
9117 
9118 	u8         syndrome[0x20];
9119 
9120 	u8         reserved_at_40[0x40];
9121 
9122 	u8         scheduling_element_id[0x20];
9123 
9124 	u8         reserved_at_a0[0x160];
9125 };
9126 
9127 struct mlx5_ifc_create_scheduling_element_in_bits {
9128 	u8         opcode[0x10];
9129 	u8         reserved_at_10[0x10];
9130 
9131 	u8         reserved_at_20[0x10];
9132 	u8         op_mod[0x10];
9133 
9134 	u8         scheduling_hierarchy[0x8];
9135 	u8         reserved_at_48[0x18];
9136 
9137 	u8         reserved_at_60[0xa0];
9138 
9139 	struct mlx5_ifc_scheduling_context_bits scheduling_context;
9140 
9141 	u8         reserved_at_300[0x100];
9142 };
9143 
9144 struct mlx5_ifc_create_rqt_out_bits {
9145 	u8         status[0x8];
9146 	u8         reserved_at_8[0x18];
9147 
9148 	u8         syndrome[0x20];
9149 
9150 	u8         reserved_at_40[0x8];
9151 	u8         rqtn[0x18];
9152 
9153 	u8         reserved_at_60[0x20];
9154 };
9155 
9156 struct mlx5_ifc_create_rqt_in_bits {
9157 	u8         opcode[0x10];
9158 	u8         uid[0x10];
9159 
9160 	u8         reserved_at_20[0x10];
9161 	u8         op_mod[0x10];
9162 
9163 	u8         reserved_at_40[0xc0];
9164 
9165 	struct mlx5_ifc_rqtc_bits rqt_context;
9166 };
9167 
9168 struct mlx5_ifc_create_rq_out_bits {
9169 	u8         status[0x8];
9170 	u8         reserved_at_8[0x18];
9171 
9172 	u8         syndrome[0x20];
9173 
9174 	u8         reserved_at_40[0x8];
9175 	u8         rqn[0x18];
9176 
9177 	u8         reserved_at_60[0x20];
9178 };
9179 
9180 struct mlx5_ifc_create_rq_in_bits {
9181 	u8         opcode[0x10];
9182 	u8         uid[0x10];
9183 
9184 	u8         reserved_at_20[0x10];
9185 	u8         op_mod[0x10];
9186 
9187 	u8         reserved_at_40[0xc0];
9188 
9189 	struct mlx5_ifc_rqc_bits ctx;
9190 };
9191 
9192 struct mlx5_ifc_create_rmp_out_bits {
9193 	u8         status[0x8];
9194 	u8         reserved_at_8[0x18];
9195 
9196 	u8         syndrome[0x20];
9197 
9198 	u8         reserved_at_40[0x8];
9199 	u8         rmpn[0x18];
9200 
9201 	u8         reserved_at_60[0x20];
9202 };
9203 
9204 struct mlx5_ifc_create_rmp_in_bits {
9205 	u8         opcode[0x10];
9206 	u8         uid[0x10];
9207 
9208 	u8         reserved_at_20[0x10];
9209 	u8         op_mod[0x10];
9210 
9211 	u8         reserved_at_40[0xc0];
9212 
9213 	struct mlx5_ifc_rmpc_bits ctx;
9214 };
9215 
9216 struct mlx5_ifc_create_qp_out_bits {
9217 	u8         status[0x8];
9218 	u8         reserved_at_8[0x18];
9219 
9220 	u8         syndrome[0x20];
9221 
9222 	u8         reserved_at_40[0x8];
9223 	u8         qpn[0x18];
9224 
9225 	u8         ece[0x20];
9226 };
9227 
9228 struct mlx5_ifc_create_qp_in_bits {
9229 	u8         opcode[0x10];
9230 	u8         uid[0x10];
9231 
9232 	u8         reserved_at_20[0x10];
9233 	u8         op_mod[0x10];
9234 
9235 	u8         qpc_ext[0x1];
9236 	u8         reserved_at_41[0x7];
9237 	u8         input_qpn[0x18];
9238 
9239 	u8         reserved_at_60[0x20];
9240 	u8         opt_param_mask[0x20];
9241 
9242 	u8         ece[0x20];
9243 
9244 	struct mlx5_ifc_qpc_bits qpc;
9245 
9246 	u8         wq_umem_offset[0x40];
9247 
9248 	u8         wq_umem_id[0x20];
9249 
9250 	u8         wq_umem_valid[0x1];
9251 	u8         reserved_at_861[0x1f];
9252 
9253 	u8         pas[][0x40];
9254 };
9255 
9256 struct mlx5_ifc_create_psv_out_bits {
9257 	u8         status[0x8];
9258 	u8         reserved_at_8[0x18];
9259 
9260 	u8         syndrome[0x20];
9261 
9262 	u8         reserved_at_40[0x40];
9263 
9264 	u8         reserved_at_80[0x8];
9265 	u8         psv0_index[0x18];
9266 
9267 	u8         reserved_at_a0[0x8];
9268 	u8         psv1_index[0x18];
9269 
9270 	u8         reserved_at_c0[0x8];
9271 	u8         psv2_index[0x18];
9272 
9273 	u8         reserved_at_e0[0x8];
9274 	u8         psv3_index[0x18];
9275 };
9276 
9277 struct mlx5_ifc_create_psv_in_bits {
9278 	u8         opcode[0x10];
9279 	u8         reserved_at_10[0x10];
9280 
9281 	u8         reserved_at_20[0x10];
9282 	u8         op_mod[0x10];
9283 
9284 	u8         num_psv[0x4];
9285 	u8         reserved_at_44[0x4];
9286 	u8         pd[0x18];
9287 
9288 	u8         reserved_at_60[0x20];
9289 };
9290 
9291 struct mlx5_ifc_create_mkey_out_bits {
9292 	u8         status[0x8];
9293 	u8         reserved_at_8[0x18];
9294 
9295 	u8         syndrome[0x20];
9296 
9297 	u8         reserved_at_40[0x8];
9298 	u8         mkey_index[0x18];
9299 
9300 	u8         reserved_at_60[0x20];
9301 };
9302 
9303 struct mlx5_ifc_create_mkey_in_bits {
9304 	u8         opcode[0x10];
9305 	u8         uid[0x10];
9306 
9307 	u8         reserved_at_20[0x10];
9308 	u8         op_mod[0x10];
9309 
9310 	u8         reserved_at_40[0x20];
9311 
9312 	u8         pg_access[0x1];
9313 	u8         mkey_umem_valid[0x1];
9314 	u8         data_direct[0x1];
9315 	u8         reserved_at_63[0x1d];
9316 
9317 	struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
9318 
9319 	u8         reserved_at_280[0x80];
9320 
9321 	u8         translations_octword_actual_size[0x20];
9322 
9323 	u8         reserved_at_320[0x560];
9324 
9325 	u8         klm_pas_mtt[][0x20];
9326 };
9327 
9328 enum {
9329 	MLX5_FLOW_TABLE_TYPE_NIC_RX		= 0x0,
9330 	MLX5_FLOW_TABLE_TYPE_NIC_TX		= 0x1,
9331 	MLX5_FLOW_TABLE_TYPE_ESW_EGRESS_ACL	= 0x2,
9332 	MLX5_FLOW_TABLE_TYPE_ESW_INGRESS_ACL	= 0x3,
9333 	MLX5_FLOW_TABLE_TYPE_FDB		= 0X4,
9334 	MLX5_FLOW_TABLE_TYPE_SNIFFER_RX		= 0X5,
9335 	MLX5_FLOW_TABLE_TYPE_SNIFFER_TX		= 0X6,
9336 };
9337 
9338 struct mlx5_ifc_create_flow_table_out_bits {
9339 	u8         status[0x8];
9340 	u8         icm_address_63_40[0x18];
9341 
9342 	u8         syndrome[0x20];
9343 
9344 	u8         icm_address_39_32[0x8];
9345 	u8         table_id[0x18];
9346 
9347 	u8         icm_address_31_0[0x20];
9348 };
9349 
9350 struct mlx5_ifc_create_flow_table_in_bits {
9351 	u8         opcode[0x10];
9352 	u8         uid[0x10];
9353 
9354 	u8         reserved_at_20[0x10];
9355 	u8         op_mod[0x10];
9356 
9357 	u8         other_vport[0x1];
9358 	u8         reserved_at_41[0xf];
9359 	u8         vport_number[0x10];
9360 
9361 	u8         reserved_at_60[0x20];
9362 
9363 	u8         table_type[0x8];
9364 	u8         reserved_at_88[0x18];
9365 
9366 	u8         reserved_at_a0[0x20];
9367 
9368 	struct mlx5_ifc_flow_table_context_bits flow_table_context;
9369 };
9370 
9371 struct mlx5_ifc_create_flow_group_out_bits {
9372 	u8         status[0x8];
9373 	u8         reserved_at_8[0x18];
9374 
9375 	u8         syndrome[0x20];
9376 
9377 	u8         reserved_at_40[0x8];
9378 	u8         group_id[0x18];
9379 
9380 	u8         reserved_at_60[0x20];
9381 };
9382 
9383 enum {
9384 	MLX5_CREATE_FLOW_GROUP_IN_GROUP_TYPE_TCAM_SUBTABLE  = 0x0,
9385 	MLX5_CREATE_FLOW_GROUP_IN_GROUP_TYPE_HASH_SPLIT     = 0x1,
9386 };
9387 
9388 enum {
9389 	MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS     = 0x0,
9390 	MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS   = 0x1,
9391 	MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS     = 0x2,
9392 	MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3,
9393 };
9394 
9395 struct mlx5_ifc_create_flow_group_in_bits {
9396 	u8         opcode[0x10];
9397 	u8         reserved_at_10[0x10];
9398 
9399 	u8         reserved_at_20[0x10];
9400 	u8         op_mod[0x10];
9401 
9402 	u8         other_vport[0x1];
9403 	u8         reserved_at_41[0xf];
9404 	u8         vport_number[0x10];
9405 
9406 	u8         reserved_at_60[0x20];
9407 
9408 	u8         table_type[0x8];
9409 	u8         reserved_at_88[0x4];
9410 	u8         group_type[0x4];
9411 	u8         reserved_at_90[0x10];
9412 
9413 	u8         reserved_at_a0[0x8];
9414 	u8         table_id[0x18];
9415 
9416 	u8         source_eswitch_owner_vhca_id_valid[0x1];
9417 
9418 	u8         reserved_at_c1[0x1f];
9419 
9420 	u8         start_flow_index[0x20];
9421 
9422 	u8         reserved_at_100[0x20];
9423 
9424 	u8         end_flow_index[0x20];
9425 
9426 	u8         reserved_at_140[0x10];
9427 	u8         match_definer_id[0x10];
9428 
9429 	u8         reserved_at_160[0x80];
9430 
9431 	u8         reserved_at_1e0[0x18];
9432 	u8         match_criteria_enable[0x8];
9433 
9434 	struct mlx5_ifc_fte_match_param_bits match_criteria;
9435 
9436 	u8         reserved_at_1200[0xe00];
9437 };
9438 
9439 struct mlx5_ifc_create_eq_out_bits {
9440 	u8         status[0x8];
9441 	u8         reserved_at_8[0x18];
9442 
9443 	u8         syndrome[0x20];
9444 
9445 	u8         reserved_at_40[0x18];
9446 	u8         eq_number[0x8];
9447 
9448 	u8         reserved_at_60[0x20];
9449 };
9450 
9451 struct mlx5_ifc_create_eq_in_bits {
9452 	u8         opcode[0x10];
9453 	u8         uid[0x10];
9454 
9455 	u8         reserved_at_20[0x10];
9456 	u8         op_mod[0x10];
9457 
9458 	u8         reserved_at_40[0x40];
9459 
9460 	struct mlx5_ifc_eqc_bits eq_context_entry;
9461 
9462 	u8         reserved_at_280[0x40];
9463 
9464 	u8         event_bitmask[4][0x40];
9465 
9466 	u8         reserved_at_3c0[0x4c0];
9467 
9468 	u8         pas[][0x40];
9469 };
9470 
9471 struct mlx5_ifc_create_dct_out_bits {
9472 	u8         status[0x8];
9473 	u8         reserved_at_8[0x18];
9474 
9475 	u8         syndrome[0x20];
9476 
9477 	u8         reserved_at_40[0x8];
9478 	u8         dctn[0x18];
9479 
9480 	u8         ece[0x20];
9481 };
9482 
9483 struct mlx5_ifc_create_dct_in_bits {
9484 	u8         opcode[0x10];
9485 	u8         uid[0x10];
9486 
9487 	u8         reserved_at_20[0x10];
9488 	u8         op_mod[0x10];
9489 
9490 	u8         reserved_at_40[0x40];
9491 
9492 	struct mlx5_ifc_dctc_bits dct_context_entry;
9493 
9494 	u8         reserved_at_280[0x180];
9495 };
9496 
9497 struct mlx5_ifc_create_cq_out_bits {
9498 	u8         status[0x8];
9499 	u8         reserved_at_8[0x18];
9500 
9501 	u8         syndrome[0x20];
9502 
9503 	u8         reserved_at_40[0x8];
9504 	u8         cqn[0x18];
9505 
9506 	u8         reserved_at_60[0x20];
9507 };
9508 
9509 struct mlx5_ifc_create_cq_in_bits {
9510 	u8         opcode[0x10];
9511 	u8         uid[0x10];
9512 
9513 	u8         reserved_at_20[0x10];
9514 	u8         op_mod[0x10];
9515 
9516 	u8         reserved_at_40[0x40];
9517 
9518 	struct mlx5_ifc_cqc_bits cq_context;
9519 
9520 	u8         reserved_at_280[0x60];
9521 
9522 	u8         cq_umem_valid[0x1];
9523 	u8         reserved_at_2e1[0x59f];
9524 
9525 	u8         pas[][0x40];
9526 };
9527 
9528 struct mlx5_ifc_config_int_moderation_out_bits {
9529 	u8         status[0x8];
9530 	u8         reserved_at_8[0x18];
9531 
9532 	u8         syndrome[0x20];
9533 
9534 	u8         reserved_at_40[0x4];
9535 	u8         min_delay[0xc];
9536 	u8         int_vector[0x10];
9537 
9538 	u8         reserved_at_60[0x20];
9539 };
9540 
9541 enum {
9542 	MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE  = 0x0,
9543 	MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ   = 0x1,
9544 };
9545 
9546 struct mlx5_ifc_config_int_moderation_in_bits {
9547 	u8         opcode[0x10];
9548 	u8         reserved_at_10[0x10];
9549 
9550 	u8         reserved_at_20[0x10];
9551 	u8         op_mod[0x10];
9552 
9553 	u8         reserved_at_40[0x4];
9554 	u8         min_delay[0xc];
9555 	u8         int_vector[0x10];
9556 
9557 	u8         reserved_at_60[0x20];
9558 };
9559 
9560 struct mlx5_ifc_attach_to_mcg_out_bits {
9561 	u8         status[0x8];
9562 	u8         reserved_at_8[0x18];
9563 
9564 	u8         syndrome[0x20];
9565 
9566 	u8         reserved_at_40[0x40];
9567 };
9568 
9569 struct mlx5_ifc_attach_to_mcg_in_bits {
9570 	u8         opcode[0x10];
9571 	u8         uid[0x10];
9572 
9573 	u8         reserved_at_20[0x10];
9574 	u8         op_mod[0x10];
9575 
9576 	u8         reserved_at_40[0x8];
9577 	u8         qpn[0x18];
9578 
9579 	u8         reserved_at_60[0x20];
9580 
9581 	u8         multicast_gid[16][0x8];
9582 };
9583 
9584 struct mlx5_ifc_arm_xrq_out_bits {
9585 	u8         status[0x8];
9586 	u8         reserved_at_8[0x18];
9587 
9588 	u8         syndrome[0x20];
9589 
9590 	u8         reserved_at_40[0x40];
9591 };
9592 
9593 struct mlx5_ifc_arm_xrq_in_bits {
9594 	u8         opcode[0x10];
9595 	u8         reserved_at_10[0x10];
9596 
9597 	u8         reserved_at_20[0x10];
9598 	u8         op_mod[0x10];
9599 
9600 	u8         reserved_at_40[0x8];
9601 	u8         xrqn[0x18];
9602 
9603 	u8         reserved_at_60[0x10];
9604 	u8         lwm[0x10];
9605 };
9606 
9607 struct mlx5_ifc_arm_xrc_srq_out_bits {
9608 	u8         status[0x8];
9609 	u8         reserved_at_8[0x18];
9610 
9611 	u8         syndrome[0x20];
9612 
9613 	u8         reserved_at_40[0x40];
9614 };
9615 
9616 enum {
9617 	MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ  = 0x1,
9618 };
9619 
9620 struct mlx5_ifc_arm_xrc_srq_in_bits {
9621 	u8         opcode[0x10];
9622 	u8         uid[0x10];
9623 
9624 	u8         reserved_at_20[0x10];
9625 	u8         op_mod[0x10];
9626 
9627 	u8         reserved_at_40[0x8];
9628 	u8         xrc_srqn[0x18];
9629 
9630 	u8         reserved_at_60[0x10];
9631 	u8         lwm[0x10];
9632 };
9633 
9634 struct mlx5_ifc_arm_rq_out_bits {
9635 	u8         status[0x8];
9636 	u8         reserved_at_8[0x18];
9637 
9638 	u8         syndrome[0x20];
9639 
9640 	u8         reserved_at_40[0x40];
9641 };
9642 
9643 enum {
9644 	MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1,
9645 	MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2,
9646 };
9647 
9648 struct mlx5_ifc_arm_rq_in_bits {
9649 	u8         opcode[0x10];
9650 	u8         uid[0x10];
9651 
9652 	u8         reserved_at_20[0x10];
9653 	u8         op_mod[0x10];
9654 
9655 	u8         reserved_at_40[0x8];
9656 	u8         srq_number[0x18];
9657 
9658 	u8         reserved_at_60[0x10];
9659 	u8         lwm[0x10];
9660 };
9661 
9662 struct mlx5_ifc_arm_dct_out_bits {
9663 	u8         status[0x8];
9664 	u8         reserved_at_8[0x18];
9665 
9666 	u8         syndrome[0x20];
9667 
9668 	u8         reserved_at_40[0x40];
9669 };
9670 
9671 struct mlx5_ifc_arm_dct_in_bits {
9672 	u8         opcode[0x10];
9673 	u8         reserved_at_10[0x10];
9674 
9675 	u8         reserved_at_20[0x10];
9676 	u8         op_mod[0x10];
9677 
9678 	u8         reserved_at_40[0x8];
9679 	u8         dct_number[0x18];
9680 
9681 	u8         reserved_at_60[0x20];
9682 };
9683 
9684 struct mlx5_ifc_alloc_xrcd_out_bits {
9685 	u8         status[0x8];
9686 	u8         reserved_at_8[0x18];
9687 
9688 	u8         syndrome[0x20];
9689 
9690 	u8         reserved_at_40[0x8];
9691 	u8         xrcd[0x18];
9692 
9693 	u8         reserved_at_60[0x20];
9694 };
9695 
9696 struct mlx5_ifc_alloc_xrcd_in_bits {
9697 	u8         opcode[0x10];
9698 	u8         uid[0x10];
9699 
9700 	u8         reserved_at_20[0x10];
9701 	u8         op_mod[0x10];
9702 
9703 	u8         reserved_at_40[0x40];
9704 };
9705 
9706 struct mlx5_ifc_alloc_uar_out_bits {
9707 	u8         status[0x8];
9708 	u8         reserved_at_8[0x18];
9709 
9710 	u8         syndrome[0x20];
9711 
9712 	u8         reserved_at_40[0x8];
9713 	u8         uar[0x18];
9714 
9715 	u8         reserved_at_60[0x20];
9716 };
9717 
9718 struct mlx5_ifc_alloc_uar_in_bits {
9719 	u8         opcode[0x10];
9720 	u8         uid[0x10];
9721 
9722 	u8         reserved_at_20[0x10];
9723 	u8         op_mod[0x10];
9724 
9725 	u8         reserved_at_40[0x40];
9726 };
9727 
9728 struct mlx5_ifc_alloc_transport_domain_out_bits {
9729 	u8         status[0x8];
9730 	u8         reserved_at_8[0x18];
9731 
9732 	u8         syndrome[0x20];
9733 
9734 	u8         reserved_at_40[0x8];
9735 	u8         transport_domain[0x18];
9736 
9737 	u8         reserved_at_60[0x20];
9738 };
9739 
9740 struct mlx5_ifc_alloc_transport_domain_in_bits {
9741 	u8         opcode[0x10];
9742 	u8         uid[0x10];
9743 
9744 	u8         reserved_at_20[0x10];
9745 	u8         op_mod[0x10];
9746 
9747 	u8         reserved_at_40[0x40];
9748 };
9749 
9750 struct mlx5_ifc_alloc_q_counter_out_bits {
9751 	u8         status[0x8];
9752 	u8         reserved_at_8[0x18];
9753 
9754 	u8         syndrome[0x20];
9755 
9756 	u8         reserved_at_40[0x18];
9757 	u8         counter_set_id[0x8];
9758 
9759 	u8         reserved_at_60[0x20];
9760 };
9761 
9762 struct mlx5_ifc_alloc_q_counter_in_bits {
9763 	u8         opcode[0x10];
9764 	u8         uid[0x10];
9765 
9766 	u8         reserved_at_20[0x10];
9767 	u8         op_mod[0x10];
9768 
9769 	u8         reserved_at_40[0x40];
9770 };
9771 
9772 struct mlx5_ifc_alloc_pd_out_bits {
9773 	u8         status[0x8];
9774 	u8         reserved_at_8[0x18];
9775 
9776 	u8         syndrome[0x20];
9777 
9778 	u8         reserved_at_40[0x8];
9779 	u8         pd[0x18];
9780 
9781 	u8         reserved_at_60[0x20];
9782 };
9783 
9784 struct mlx5_ifc_alloc_pd_in_bits {
9785 	u8         opcode[0x10];
9786 	u8         uid[0x10];
9787 
9788 	u8         reserved_at_20[0x10];
9789 	u8         op_mod[0x10];
9790 
9791 	u8         reserved_at_40[0x40];
9792 };
9793 
9794 struct mlx5_ifc_alloc_flow_counter_out_bits {
9795 	u8         status[0x8];
9796 	u8         reserved_at_8[0x18];
9797 
9798 	u8         syndrome[0x20];
9799 
9800 	u8         flow_counter_id[0x20];
9801 
9802 	u8         reserved_at_60[0x20];
9803 };
9804 
9805 struct mlx5_ifc_alloc_flow_counter_in_bits {
9806 	u8         opcode[0x10];
9807 	u8         reserved_at_10[0x10];
9808 
9809 	u8         reserved_at_20[0x10];
9810 	u8         op_mod[0x10];
9811 
9812 	u8         reserved_at_40[0x33];
9813 	u8         flow_counter_bulk_log_size[0x5];
9814 	u8         flow_counter_bulk[0x8];
9815 };
9816 
9817 struct mlx5_ifc_add_vxlan_udp_dport_out_bits {
9818 	u8         status[0x8];
9819 	u8         reserved_at_8[0x18];
9820 
9821 	u8         syndrome[0x20];
9822 
9823 	u8         reserved_at_40[0x40];
9824 };
9825 
9826 struct mlx5_ifc_add_vxlan_udp_dport_in_bits {
9827 	u8         opcode[0x10];
9828 	u8         reserved_at_10[0x10];
9829 
9830 	u8         reserved_at_20[0x10];
9831 	u8         op_mod[0x10];
9832 
9833 	u8         reserved_at_40[0x20];
9834 
9835 	u8         reserved_at_60[0x10];
9836 	u8         vxlan_udp_port[0x10];
9837 };
9838 
9839 struct mlx5_ifc_set_pp_rate_limit_out_bits {
9840 	u8         status[0x8];
9841 	u8         reserved_at_8[0x18];
9842 
9843 	u8         syndrome[0x20];
9844 
9845 	u8         reserved_at_40[0x40];
9846 };
9847 
9848 struct mlx5_ifc_set_pp_rate_limit_context_bits {
9849 	u8         rate_limit[0x20];
9850 
9851 	u8	   burst_upper_bound[0x20];
9852 
9853 	u8         reserved_at_40[0x10];
9854 	u8	   typical_packet_size[0x10];
9855 
9856 	u8         reserved_at_60[0x120];
9857 };
9858 
9859 struct mlx5_ifc_set_pp_rate_limit_in_bits {
9860 	u8         opcode[0x10];
9861 	u8         uid[0x10];
9862 
9863 	u8         reserved_at_20[0x10];
9864 	u8         op_mod[0x10];
9865 
9866 	u8         reserved_at_40[0x10];
9867 	u8         rate_limit_index[0x10];
9868 
9869 	u8         reserved_at_60[0x20];
9870 
9871 	struct mlx5_ifc_set_pp_rate_limit_context_bits ctx;
9872 };
9873 
9874 struct mlx5_ifc_access_register_out_bits {
9875 	u8         status[0x8];
9876 	u8         reserved_at_8[0x18];
9877 
9878 	u8         syndrome[0x20];
9879 
9880 	u8         reserved_at_40[0x40];
9881 
9882 	u8         register_data[][0x20];
9883 };
9884 
9885 enum {
9886 	MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE  = 0x0,
9887 	MLX5_ACCESS_REGISTER_IN_OP_MOD_READ   = 0x1,
9888 };
9889 
9890 struct mlx5_ifc_access_register_in_bits {
9891 	u8         opcode[0x10];
9892 	u8         reserved_at_10[0x10];
9893 
9894 	u8         reserved_at_20[0x10];
9895 	u8         op_mod[0x10];
9896 
9897 	u8         reserved_at_40[0x10];
9898 	u8         register_id[0x10];
9899 
9900 	u8         argument[0x20];
9901 
9902 	u8         register_data[][0x20];
9903 };
9904 
9905 struct mlx5_ifc_sltp_reg_bits {
9906 	u8         status[0x4];
9907 	u8         version[0x4];
9908 	u8         local_port[0x8];
9909 	u8         pnat[0x2];
9910 	u8         reserved_at_12[0x2];
9911 	u8         lane[0x4];
9912 	u8         reserved_at_18[0x8];
9913 
9914 	u8         reserved_at_20[0x20];
9915 
9916 	u8         reserved_at_40[0x7];
9917 	u8         polarity[0x1];
9918 	u8         ob_tap0[0x8];
9919 	u8         ob_tap1[0x8];
9920 	u8         ob_tap2[0x8];
9921 
9922 	u8         reserved_at_60[0xc];
9923 	u8         ob_preemp_mode[0x4];
9924 	u8         ob_reg[0x8];
9925 	u8         ob_bias[0x8];
9926 
9927 	u8         reserved_at_80[0x20];
9928 };
9929 
9930 struct mlx5_ifc_slrg_reg_bits {
9931 	u8         status[0x4];
9932 	u8         version[0x4];
9933 	u8         local_port[0x8];
9934 	u8         pnat[0x2];
9935 	u8         reserved_at_12[0x2];
9936 	u8         lane[0x4];
9937 	u8         reserved_at_18[0x8];
9938 
9939 	u8         time_to_link_up[0x10];
9940 	u8         reserved_at_30[0xc];
9941 	u8         grade_lane_speed[0x4];
9942 
9943 	u8         grade_version[0x8];
9944 	u8         grade[0x18];
9945 
9946 	u8         reserved_at_60[0x4];
9947 	u8         height_grade_type[0x4];
9948 	u8         height_grade[0x18];
9949 
9950 	u8         height_dz[0x10];
9951 	u8         height_dv[0x10];
9952 
9953 	u8         reserved_at_a0[0x10];
9954 	u8         height_sigma[0x10];
9955 
9956 	u8         reserved_at_c0[0x20];
9957 
9958 	u8         reserved_at_e0[0x4];
9959 	u8         phase_grade_type[0x4];
9960 	u8         phase_grade[0x18];
9961 
9962 	u8         reserved_at_100[0x8];
9963 	u8         phase_eo_pos[0x8];
9964 	u8         reserved_at_110[0x8];
9965 	u8         phase_eo_neg[0x8];
9966 
9967 	u8         ffe_set_tested[0x10];
9968 	u8         test_errors_per_lane[0x10];
9969 };
9970 
9971 struct mlx5_ifc_pvlc_reg_bits {
9972 	u8         reserved_at_0[0x8];
9973 	u8         local_port[0x8];
9974 	u8         reserved_at_10[0x10];
9975 
9976 	u8         reserved_at_20[0x1c];
9977 	u8         vl_hw_cap[0x4];
9978 
9979 	u8         reserved_at_40[0x1c];
9980 	u8         vl_admin[0x4];
9981 
9982 	u8         reserved_at_60[0x1c];
9983 	u8         vl_operational[0x4];
9984 };
9985 
9986 struct mlx5_ifc_pude_reg_bits {
9987 	u8         swid[0x8];
9988 	u8         local_port[0x8];
9989 	u8         reserved_at_10[0x4];
9990 	u8         admin_status[0x4];
9991 	u8         reserved_at_18[0x4];
9992 	u8         oper_status[0x4];
9993 
9994 	u8         reserved_at_20[0x60];
9995 };
9996 
9997 enum {
9998 	MLX5_PTYS_CONNECTOR_TYPE_PORT_DA = 0x7,
9999 };
10000 
10001 struct mlx5_ifc_ptys_reg_bits {
10002 	u8         reserved_at_0[0x1];
10003 	u8         an_disable_admin[0x1];
10004 	u8         an_disable_cap[0x1];
10005 	u8         reserved_at_3[0x5];
10006 	u8         local_port[0x8];
10007 	u8         reserved_at_10[0x8];
10008 	u8         plane_ind[0x4];
10009 	u8         reserved_at_1c[0x1];
10010 	u8         proto_mask[0x3];
10011 
10012 	u8         an_status[0x4];
10013 	u8         reserved_at_24[0xc];
10014 	u8         data_rate_oper[0x10];
10015 
10016 	u8         ext_eth_proto_capability[0x20];
10017 
10018 	u8         eth_proto_capability[0x20];
10019 
10020 	u8         ib_link_width_capability[0x10];
10021 	u8         ib_proto_capability[0x10];
10022 
10023 	u8         ext_eth_proto_admin[0x20];
10024 
10025 	u8         eth_proto_admin[0x20];
10026 
10027 	u8         ib_link_width_admin[0x10];
10028 	u8         ib_proto_admin[0x10];
10029 
10030 	u8         ext_eth_proto_oper[0x20];
10031 
10032 	u8         eth_proto_oper[0x20];
10033 
10034 	u8         ib_link_width_oper[0x10];
10035 	u8         ib_proto_oper[0x10];
10036 
10037 	u8         reserved_at_160[0x8];
10038 	u8         lane_rate_oper[0x14];
10039 	u8         connector_type[0x4];
10040 
10041 	u8         eth_proto_lp_advertise[0x20];
10042 
10043 	u8         reserved_at_1a0[0x60];
10044 };
10045 
10046 struct mlx5_ifc_mlcr_reg_bits {
10047 	u8         reserved_at_0[0x8];
10048 	u8         local_port[0x8];
10049 	u8         reserved_at_10[0x20];
10050 
10051 	u8         beacon_duration[0x10];
10052 	u8         reserved_at_40[0x10];
10053 
10054 	u8         beacon_remain[0x10];
10055 };
10056 
10057 struct mlx5_ifc_ptas_reg_bits {
10058 	u8         reserved_at_0[0x20];
10059 
10060 	u8         algorithm_options[0x10];
10061 	u8         reserved_at_30[0x4];
10062 	u8         repetitions_mode[0x4];
10063 	u8         num_of_repetitions[0x8];
10064 
10065 	u8         grade_version[0x8];
10066 	u8         height_grade_type[0x4];
10067 	u8         phase_grade_type[0x4];
10068 	u8         height_grade_weight[0x8];
10069 	u8         phase_grade_weight[0x8];
10070 
10071 	u8         gisim_measure_bits[0x10];
10072 	u8         adaptive_tap_measure_bits[0x10];
10073 
10074 	u8         ber_bath_high_error_threshold[0x10];
10075 	u8         ber_bath_mid_error_threshold[0x10];
10076 
10077 	u8         ber_bath_low_error_threshold[0x10];
10078 	u8         one_ratio_high_threshold[0x10];
10079 
10080 	u8         one_ratio_high_mid_threshold[0x10];
10081 	u8         one_ratio_low_mid_threshold[0x10];
10082 
10083 	u8         one_ratio_low_threshold[0x10];
10084 	u8         ndeo_error_threshold[0x10];
10085 
10086 	u8         mixer_offset_step_size[0x10];
10087 	u8         reserved_at_110[0x8];
10088 	u8         mix90_phase_for_voltage_bath[0x8];
10089 
10090 	u8         mixer_offset_start[0x10];
10091 	u8         mixer_offset_end[0x10];
10092 
10093 	u8         reserved_at_140[0x15];
10094 	u8         ber_test_time[0xb];
10095 };
10096 
10097 struct mlx5_ifc_pspa_reg_bits {
10098 	u8         swid[0x8];
10099 	u8         local_port[0x8];
10100 	u8         sub_port[0x8];
10101 	u8         reserved_at_18[0x8];
10102 
10103 	u8         reserved_at_20[0x20];
10104 };
10105 
10106 struct mlx5_ifc_pqdr_reg_bits {
10107 	u8         reserved_at_0[0x8];
10108 	u8         local_port[0x8];
10109 	u8         reserved_at_10[0x5];
10110 	u8         prio[0x3];
10111 	u8         reserved_at_18[0x6];
10112 	u8         mode[0x2];
10113 
10114 	u8         reserved_at_20[0x20];
10115 
10116 	u8         reserved_at_40[0x10];
10117 	u8         min_threshold[0x10];
10118 
10119 	u8         reserved_at_60[0x10];
10120 	u8         max_threshold[0x10];
10121 
10122 	u8         reserved_at_80[0x10];
10123 	u8         mark_probability_denominator[0x10];
10124 
10125 	u8         reserved_at_a0[0x60];
10126 };
10127 
10128 struct mlx5_ifc_ppsc_reg_bits {
10129 	u8         reserved_at_0[0x8];
10130 	u8         local_port[0x8];
10131 	u8         reserved_at_10[0x10];
10132 
10133 	u8         reserved_at_20[0x60];
10134 
10135 	u8         reserved_at_80[0x1c];
10136 	u8         wrps_admin[0x4];
10137 
10138 	u8         reserved_at_a0[0x1c];
10139 	u8         wrps_status[0x4];
10140 
10141 	u8         reserved_at_c0[0x8];
10142 	u8         up_threshold[0x8];
10143 	u8         reserved_at_d0[0x8];
10144 	u8         down_threshold[0x8];
10145 
10146 	u8         reserved_at_e0[0x20];
10147 
10148 	u8         reserved_at_100[0x1c];
10149 	u8         srps_admin[0x4];
10150 
10151 	u8         reserved_at_120[0x1c];
10152 	u8         srps_status[0x4];
10153 
10154 	u8         reserved_at_140[0x40];
10155 };
10156 
10157 struct mlx5_ifc_pplr_reg_bits {
10158 	u8         reserved_at_0[0x8];
10159 	u8         local_port[0x8];
10160 	u8         reserved_at_10[0x10];
10161 
10162 	u8         reserved_at_20[0x8];
10163 	u8         lb_cap[0x8];
10164 	u8         reserved_at_30[0x8];
10165 	u8         lb_en[0x8];
10166 };
10167 
10168 struct mlx5_ifc_pplm_reg_bits {
10169 	u8         reserved_at_0[0x8];
10170 	u8	   local_port[0x8];
10171 	u8	   reserved_at_10[0x10];
10172 
10173 	u8	   reserved_at_20[0x20];
10174 
10175 	u8	   port_profile_mode[0x8];
10176 	u8	   static_port_profile[0x8];
10177 	u8	   active_port_profile[0x8];
10178 	u8	   reserved_at_58[0x8];
10179 
10180 	u8	   retransmission_active[0x8];
10181 	u8	   fec_mode_active[0x18];
10182 
10183 	u8	   rs_fec_correction_bypass_cap[0x4];
10184 	u8	   reserved_at_84[0x8];
10185 	u8	   fec_override_cap_56g[0x4];
10186 	u8	   fec_override_cap_100g[0x4];
10187 	u8	   fec_override_cap_50g[0x4];
10188 	u8	   fec_override_cap_25g[0x4];
10189 	u8	   fec_override_cap_10g_40g[0x4];
10190 
10191 	u8	   rs_fec_correction_bypass_admin[0x4];
10192 	u8	   reserved_at_a4[0x8];
10193 	u8	   fec_override_admin_56g[0x4];
10194 	u8	   fec_override_admin_100g[0x4];
10195 	u8	   fec_override_admin_50g[0x4];
10196 	u8	   fec_override_admin_25g[0x4];
10197 	u8	   fec_override_admin_10g_40g[0x4];
10198 
10199 	u8         fec_override_cap_400g_8x[0x10];
10200 	u8         fec_override_cap_200g_4x[0x10];
10201 
10202 	u8         fec_override_cap_100g_2x[0x10];
10203 	u8         fec_override_cap_50g_1x[0x10];
10204 
10205 	u8         fec_override_admin_400g_8x[0x10];
10206 	u8         fec_override_admin_200g_4x[0x10];
10207 
10208 	u8         fec_override_admin_100g_2x[0x10];
10209 	u8         fec_override_admin_50g_1x[0x10];
10210 
10211 	u8         fec_override_cap_800g_8x[0x10];
10212 	u8         fec_override_cap_400g_4x[0x10];
10213 
10214 	u8         fec_override_cap_200g_2x[0x10];
10215 	u8         fec_override_cap_100g_1x[0x10];
10216 
10217 	u8         reserved_at_180[0xa0];
10218 
10219 	u8         fec_override_admin_800g_8x[0x10];
10220 	u8         fec_override_admin_400g_4x[0x10];
10221 
10222 	u8         fec_override_admin_200g_2x[0x10];
10223 	u8         fec_override_admin_100g_1x[0x10];
10224 
10225 	u8         reserved_at_260[0x60];
10226 
10227 	u8         fec_override_cap_1600g_8x[0x10];
10228 	u8         fec_override_cap_800g_4x[0x10];
10229 
10230 	u8         fec_override_cap_400g_2x[0x10];
10231 	u8         fec_override_cap_200g_1x[0x10];
10232 
10233 	u8         fec_override_admin_1600g_8x[0x10];
10234 	u8         fec_override_admin_800g_4x[0x10];
10235 
10236 	u8         fec_override_admin_400g_2x[0x10];
10237 	u8         fec_override_admin_200g_1x[0x10];
10238 
10239 	u8         reserved_at_340[0x80];
10240 };
10241 
10242 struct mlx5_ifc_ppcnt_reg_bits {
10243 	u8         swid[0x8];
10244 	u8         local_port[0x8];
10245 	u8         pnat[0x2];
10246 	u8         reserved_at_12[0x8];
10247 	u8         grp[0x6];
10248 
10249 	u8         clr[0x1];
10250 	u8         reserved_at_21[0x13];
10251 	u8         plane_ind[0x4];
10252 	u8         reserved_at_38[0x3];
10253 	u8         prio_tc[0x5];
10254 
10255 	union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set;
10256 };
10257 
10258 struct mlx5_ifc_mpein_reg_bits {
10259 	u8         reserved_at_0[0x2];
10260 	u8         depth[0x6];
10261 	u8         pcie_index[0x8];
10262 	u8         node[0x8];
10263 	u8         reserved_at_18[0x8];
10264 
10265 	u8         capability_mask[0x20];
10266 
10267 	u8         reserved_at_40[0x8];
10268 	u8         link_width_enabled[0x8];
10269 	u8         link_speed_enabled[0x10];
10270 
10271 	u8         lane0_physical_position[0x8];
10272 	u8         link_width_active[0x8];
10273 	u8         link_speed_active[0x10];
10274 
10275 	u8         num_of_pfs[0x10];
10276 	u8         num_of_vfs[0x10];
10277 
10278 	u8         bdf0[0x10];
10279 	u8         reserved_at_b0[0x10];
10280 
10281 	u8         max_read_request_size[0x4];
10282 	u8         max_payload_size[0x4];
10283 	u8         reserved_at_c8[0x5];
10284 	u8         pwr_status[0x3];
10285 	u8         port_type[0x4];
10286 	u8         reserved_at_d4[0xb];
10287 	u8         lane_reversal[0x1];
10288 
10289 	u8         reserved_at_e0[0x14];
10290 	u8         pci_power[0xc];
10291 
10292 	u8         reserved_at_100[0x20];
10293 
10294 	u8         device_status[0x10];
10295 	u8         port_state[0x8];
10296 	u8         reserved_at_138[0x8];
10297 
10298 	u8         reserved_at_140[0x10];
10299 	u8         receiver_detect_result[0x10];
10300 
10301 	u8         reserved_at_160[0x20];
10302 };
10303 
10304 struct mlx5_ifc_mpcnt_reg_bits {
10305 	u8         reserved_at_0[0x8];
10306 	u8         pcie_index[0x8];
10307 	u8         reserved_at_10[0xa];
10308 	u8         grp[0x6];
10309 
10310 	u8         clr[0x1];
10311 	u8         reserved_at_21[0x1f];
10312 
10313 	union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set;
10314 };
10315 
10316 struct mlx5_ifc_ppad_reg_bits {
10317 	u8         reserved_at_0[0x3];
10318 	u8         single_mac[0x1];
10319 	u8         reserved_at_4[0x4];
10320 	u8         local_port[0x8];
10321 	u8         mac_47_32[0x10];
10322 
10323 	u8         mac_31_0[0x20];
10324 
10325 	u8         reserved_at_40[0x40];
10326 };
10327 
10328 struct mlx5_ifc_pmtu_reg_bits {
10329 	u8         reserved_at_0[0x8];
10330 	u8         local_port[0x8];
10331 	u8         reserved_at_10[0x10];
10332 
10333 	u8         max_mtu[0x10];
10334 	u8         reserved_at_30[0x10];
10335 
10336 	u8         admin_mtu[0x10];
10337 	u8         reserved_at_50[0x10];
10338 
10339 	u8         oper_mtu[0x10];
10340 	u8         reserved_at_70[0x10];
10341 };
10342 
10343 struct mlx5_ifc_pmpr_reg_bits {
10344 	u8         reserved_at_0[0x8];
10345 	u8         module[0x8];
10346 	u8         reserved_at_10[0x10];
10347 
10348 	u8         reserved_at_20[0x18];
10349 	u8         attenuation_5g[0x8];
10350 
10351 	u8         reserved_at_40[0x18];
10352 	u8         attenuation_7g[0x8];
10353 
10354 	u8         reserved_at_60[0x18];
10355 	u8         attenuation_12g[0x8];
10356 };
10357 
10358 struct mlx5_ifc_pmpe_reg_bits {
10359 	u8         reserved_at_0[0x8];
10360 	u8         module[0x8];
10361 	u8         reserved_at_10[0xc];
10362 	u8         module_status[0x4];
10363 
10364 	u8         reserved_at_20[0x60];
10365 };
10366 
10367 struct mlx5_ifc_pmpc_reg_bits {
10368 	u8         module_state_updated[32][0x8];
10369 };
10370 
10371 struct mlx5_ifc_pmlpn_reg_bits {
10372 	u8         reserved_at_0[0x4];
10373 	u8         mlpn_status[0x4];
10374 	u8         local_port[0x8];
10375 	u8         reserved_at_10[0x10];
10376 
10377 	u8         e[0x1];
10378 	u8         reserved_at_21[0x1f];
10379 };
10380 
10381 struct mlx5_ifc_pmlp_reg_bits {
10382 	u8         rxtx[0x1];
10383 	u8         reserved_at_1[0x7];
10384 	u8         local_port[0x8];
10385 	u8         reserved_at_10[0x8];
10386 	u8         width[0x8];
10387 
10388 	u8         lane0_module_mapping[0x20];
10389 
10390 	u8         lane1_module_mapping[0x20];
10391 
10392 	u8         lane2_module_mapping[0x20];
10393 
10394 	u8         lane3_module_mapping[0x20];
10395 
10396 	u8         reserved_at_a0[0x160];
10397 };
10398 
10399 struct mlx5_ifc_pmaos_reg_bits {
10400 	u8         reserved_at_0[0x8];
10401 	u8         module[0x8];
10402 	u8         reserved_at_10[0x4];
10403 	u8         admin_status[0x4];
10404 	u8         reserved_at_18[0x4];
10405 	u8         oper_status[0x4];
10406 
10407 	u8         ase[0x1];
10408 	u8         ee[0x1];
10409 	u8         reserved_at_22[0x1c];
10410 	u8         e[0x2];
10411 
10412 	u8         reserved_at_40[0x40];
10413 };
10414 
10415 struct mlx5_ifc_plpc_reg_bits {
10416 	u8         reserved_at_0[0x4];
10417 	u8         profile_id[0xc];
10418 	u8         reserved_at_10[0x4];
10419 	u8         proto_mask[0x4];
10420 	u8         reserved_at_18[0x8];
10421 
10422 	u8         reserved_at_20[0x10];
10423 	u8         lane_speed[0x10];
10424 
10425 	u8         reserved_at_40[0x17];
10426 	u8         lpbf[0x1];
10427 	u8         fec_mode_policy[0x8];
10428 
10429 	u8         retransmission_capability[0x8];
10430 	u8         fec_mode_capability[0x18];
10431 
10432 	u8         retransmission_support_admin[0x8];
10433 	u8         fec_mode_support_admin[0x18];
10434 
10435 	u8         retransmission_request_admin[0x8];
10436 	u8         fec_mode_request_admin[0x18];
10437 
10438 	u8         reserved_at_c0[0x80];
10439 };
10440 
10441 struct mlx5_ifc_plib_reg_bits {
10442 	u8         reserved_at_0[0x8];
10443 	u8         local_port[0x8];
10444 	u8         reserved_at_10[0x8];
10445 	u8         ib_port[0x8];
10446 
10447 	u8         reserved_at_20[0x60];
10448 };
10449 
10450 struct mlx5_ifc_plbf_reg_bits {
10451 	u8         reserved_at_0[0x8];
10452 	u8         local_port[0x8];
10453 	u8         reserved_at_10[0xd];
10454 	u8         lbf_mode[0x3];
10455 
10456 	u8         reserved_at_20[0x20];
10457 };
10458 
10459 struct mlx5_ifc_pipg_reg_bits {
10460 	u8         reserved_at_0[0x8];
10461 	u8         local_port[0x8];
10462 	u8         reserved_at_10[0x10];
10463 
10464 	u8         dic[0x1];
10465 	u8         reserved_at_21[0x19];
10466 	u8         ipg[0x4];
10467 	u8         reserved_at_3e[0x2];
10468 };
10469 
10470 struct mlx5_ifc_pifr_reg_bits {
10471 	u8         reserved_at_0[0x8];
10472 	u8         local_port[0x8];
10473 	u8         reserved_at_10[0x10];
10474 
10475 	u8         reserved_at_20[0xe0];
10476 
10477 	u8         port_filter[8][0x20];
10478 
10479 	u8         port_filter_update_en[8][0x20];
10480 };
10481 
10482 enum {
10483 	MLX5_BUF_OWNERSHIP_UNKNOWN	= 0x0,
10484 	MLX5_BUF_OWNERSHIP_FW_OWNED	= 0x1,
10485 	MLX5_BUF_OWNERSHIP_SW_OWNED	= 0x2,
10486 };
10487 
10488 struct mlx5_ifc_pfcc_reg_bits {
10489 	u8         reserved_at_0[0x4];
10490 	u8	   buf_ownership[0x2];
10491 	u8	   reserved_at_6[0x2];
10492 	u8         local_port[0x8];
10493 	u8         reserved_at_10[0xa];
10494 	u8	   cable_length_mask[0x1];
10495 	u8         ppan_mask_n[0x1];
10496 	u8         minor_stall_mask[0x1];
10497 	u8         critical_stall_mask[0x1];
10498 	u8         reserved_at_1e[0x2];
10499 
10500 	u8         ppan[0x4];
10501 	u8         reserved_at_24[0x4];
10502 	u8         prio_mask_tx[0x8];
10503 	u8         reserved_at_30[0x8];
10504 	u8         prio_mask_rx[0x8];
10505 
10506 	u8         pptx[0x1];
10507 	u8         aptx[0x1];
10508 	u8         pptx_mask_n[0x1];
10509 	u8         reserved_at_43[0x5];
10510 	u8         pfctx[0x8];
10511 	u8         reserved_at_50[0x10];
10512 
10513 	u8         pprx[0x1];
10514 	u8         aprx[0x1];
10515 	u8         pprx_mask_n[0x1];
10516 	u8         reserved_at_63[0x5];
10517 	u8         pfcrx[0x8];
10518 	u8         reserved_at_70[0x10];
10519 
10520 	u8         device_stall_minor_watermark[0x10];
10521 	u8         device_stall_critical_watermark[0x10];
10522 
10523 	u8	   reserved_at_a0[0x18];
10524 	u8	   cable_length[0x8];
10525 
10526 	u8         reserved_at_c0[0x40];
10527 };
10528 
10529 struct mlx5_ifc_pelc_reg_bits {
10530 	u8         op[0x4];
10531 	u8         reserved_at_4[0x4];
10532 	u8         local_port[0x8];
10533 	u8         reserved_at_10[0x10];
10534 
10535 	u8         op_admin[0x8];
10536 	u8         op_capability[0x8];
10537 	u8         op_request[0x8];
10538 	u8         op_active[0x8];
10539 
10540 	u8         admin[0x40];
10541 
10542 	u8         capability[0x40];
10543 
10544 	u8         request[0x40];
10545 
10546 	u8         active[0x40];
10547 
10548 	u8         reserved_at_140[0x80];
10549 };
10550 
10551 struct mlx5_ifc_peir_reg_bits {
10552 	u8         reserved_at_0[0x8];
10553 	u8         local_port[0x8];
10554 	u8         reserved_at_10[0x10];
10555 
10556 	u8         reserved_at_20[0xc];
10557 	u8         error_count[0x4];
10558 	u8         reserved_at_30[0x10];
10559 
10560 	u8         reserved_at_40[0xc];
10561 	u8         lane[0x4];
10562 	u8         reserved_at_50[0x8];
10563 	u8         error_type[0x8];
10564 };
10565 
10566 struct mlx5_ifc_mpegc_reg_bits {
10567 	u8         reserved_at_0[0x30];
10568 	u8         field_select[0x10];
10569 
10570 	u8         tx_overflow_sense[0x1];
10571 	u8         mark_cqe[0x1];
10572 	u8         mark_cnp[0x1];
10573 	u8         reserved_at_43[0x1b];
10574 	u8         tx_lossy_overflow_oper[0x2];
10575 
10576 	u8         reserved_at_60[0x100];
10577 };
10578 
10579 struct mlx5_ifc_mpir_reg_bits {
10580 	u8         sdm[0x1];
10581 	u8         reserved_at_1[0x1b];
10582 	u8         host_buses[0x4];
10583 
10584 	u8         reserved_at_20[0x20];
10585 
10586 	u8         local_port[0x8];
10587 	u8         reserved_at_28[0x18];
10588 
10589 	u8         reserved_at_60[0x20];
10590 };
10591 
10592 enum {
10593 	MLX5_MTUTC_FREQ_ADJ_UNITS_PPB          = 0x0,
10594 	MLX5_MTUTC_FREQ_ADJ_UNITS_SCALED_PPM   = 0x1,
10595 };
10596 
10597 enum {
10598 	MLX5_MTUTC_OPERATION_SET_TIME_IMMEDIATE   = 0x1,
10599 	MLX5_MTUTC_OPERATION_ADJUST_TIME          = 0x2,
10600 	MLX5_MTUTC_OPERATION_ADJUST_FREQ_UTC      = 0x3,
10601 };
10602 
10603 struct mlx5_ifc_mtutc_reg_bits {
10604 	u8         reserved_at_0[0x5];
10605 	u8         freq_adj_units[0x3];
10606 	u8         reserved_at_8[0x3];
10607 	u8         log_max_freq_adjustment[0x5];
10608 
10609 	u8         reserved_at_10[0xc];
10610 	u8         operation[0x4];
10611 
10612 	u8         freq_adjustment[0x20];
10613 
10614 	u8         reserved_at_40[0x40];
10615 
10616 	u8         utc_sec[0x20];
10617 
10618 	u8         reserved_at_a0[0x2];
10619 	u8         utc_nsec[0x1e];
10620 
10621 	u8         time_adjustment[0x20];
10622 };
10623 
10624 struct mlx5_ifc_pcam_enhanced_features_bits {
10625 	u8         reserved_at_0[0x10];
10626 	u8         ppcnt_recovery_counters[0x1];
10627 	u8         reserved_at_11[0x7];
10628 	u8	   cable_length[0x1];
10629 	u8	   reserved_at_19[0x4];
10630 	u8         fec_200G_per_lane_in_pplm[0x1];
10631 	u8         reserved_at_1e[0x2a];
10632 	u8         fec_100G_per_lane_in_pplm[0x1];
10633 	u8         reserved_at_49[0xa];
10634 	u8	   buffer_ownership[0x1];
10635 	u8	   resereved_at_54[0x14];
10636 	u8         fec_50G_per_lane_in_pplm[0x1];
10637 	u8         reserved_at_69[0x4];
10638 	u8         rx_icrc_encapsulated_counter[0x1];
10639 	u8	   reserved_at_6e[0x4];
10640 	u8         ptys_extended_ethernet[0x1];
10641 	u8	   reserved_at_73[0x3];
10642 	u8         pfcc_mask[0x1];
10643 	u8         reserved_at_77[0x3];
10644 	u8         per_lane_error_counters[0x1];
10645 	u8         rx_buffer_fullness_counters[0x1];
10646 	u8         ptys_connector_type[0x1];
10647 	u8         reserved_at_7d[0x1];
10648 	u8         ppcnt_discard_group[0x1];
10649 	u8         ppcnt_statistical_group[0x1];
10650 };
10651 
10652 struct mlx5_ifc_pcam_regs_5000_to_507f_bits {
10653 	u8         port_access_reg_cap_mask_127_to_96[0x20];
10654 	u8         port_access_reg_cap_mask_95_to_64[0x20];
10655 
10656 	u8         port_access_reg_cap_mask_63_to_36[0x1c];
10657 	u8         pplm[0x1];
10658 	u8         port_access_reg_cap_mask_34_to_32[0x3];
10659 
10660 	u8         port_access_reg_cap_mask_31_to_13[0x13];
10661 	u8         pbmc[0x1];
10662 	u8         pptb[0x1];
10663 	u8         port_access_reg_cap_mask_10_to_09[0x2];
10664 	u8         ppcnt[0x1];
10665 	u8         port_access_reg_cap_mask_07_to_00[0x8];
10666 };
10667 
10668 struct mlx5_ifc_pcam_reg_bits {
10669 	u8         reserved_at_0[0x8];
10670 	u8         feature_group[0x8];
10671 	u8         reserved_at_10[0x8];
10672 	u8         access_reg_group[0x8];
10673 
10674 	u8         reserved_at_20[0x20];
10675 
10676 	union {
10677 		struct mlx5_ifc_pcam_regs_5000_to_507f_bits regs_5000_to_507f;
10678 		u8         reserved_at_0[0x80];
10679 	} port_access_reg_cap_mask;
10680 
10681 	u8         reserved_at_c0[0x80];
10682 
10683 	union {
10684 		struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features;
10685 		u8         reserved_at_0[0x80];
10686 	} feature_cap_mask;
10687 
10688 	u8         reserved_at_1c0[0xc0];
10689 };
10690 
10691 struct mlx5_ifc_mcam_enhanced_features_bits {
10692 	u8         reserved_at_0[0x50];
10693 	u8         mtutc_freq_adj_units[0x1];
10694 	u8         mtutc_time_adjustment_extended_range[0x1];
10695 	u8         reserved_at_52[0xb];
10696 	u8         mcia_32dwords[0x1];
10697 	u8         out_pulse_duration_ns[0x1];
10698 	u8         npps_period[0x1];
10699 	u8         reserved_at_60[0xa];
10700 	u8         reset_state[0x1];
10701 	u8         ptpcyc2realtime_modify[0x1];
10702 	u8         reserved_at_6c[0x2];
10703 	u8         pci_status_and_power[0x1];
10704 	u8         reserved_at_6f[0x5];
10705 	u8         mark_tx_action_cnp[0x1];
10706 	u8         mark_tx_action_cqe[0x1];
10707 	u8         dynamic_tx_overflow[0x1];
10708 	u8         reserved_at_77[0x4];
10709 	u8         pcie_outbound_stalled[0x1];
10710 	u8         tx_overflow_buffer_pkt[0x1];
10711 	u8         mtpps_enh_out_per_adj[0x1];
10712 	u8         mtpps_fs[0x1];
10713 	u8         pcie_performance_group[0x1];
10714 };
10715 
10716 struct mlx5_ifc_mcam_access_reg_bits {
10717 	u8         reserved_at_0[0x1c];
10718 	u8         mcda[0x1];
10719 	u8         mcc[0x1];
10720 	u8         mcqi[0x1];
10721 	u8         mcqs[0x1];
10722 
10723 	u8         regs_95_to_90[0x6];
10724 	u8         mpir[0x1];
10725 	u8         regs_88_to_87[0x2];
10726 	u8         mpegc[0x1];
10727 	u8         mtutc[0x1];
10728 	u8         regs_84_to_68[0x11];
10729 	u8         tracer_registers[0x4];
10730 
10731 	u8         regs_63_to_46[0x12];
10732 	u8         mrtc[0x1];
10733 	u8         regs_44_to_41[0x4];
10734 	u8         mfrl[0x1];
10735 	u8         regs_39_to_32[0x8];
10736 
10737 	u8         regs_31_to_11[0x15];
10738 	u8         mtmp[0x1];
10739 	u8         regs_9_to_0[0xa];
10740 };
10741 
10742 struct mlx5_ifc_mcam_access_reg_bits1 {
10743 	u8         regs_127_to_96[0x20];
10744 
10745 	u8         regs_95_to_64[0x20];
10746 
10747 	u8         regs_63_to_32[0x20];
10748 
10749 	u8         regs_31_to_0[0x20];
10750 };
10751 
10752 struct mlx5_ifc_mcam_access_reg_bits2 {
10753 	u8         regs_127_to_99[0x1d];
10754 	u8         mirc[0x1];
10755 	u8         regs_97_to_96[0x2];
10756 
10757 	u8         regs_95_to_87[0x09];
10758 	u8         synce_registers[0x2];
10759 	u8         regs_84_to_64[0x15];
10760 
10761 	u8         regs_63_to_32[0x20];
10762 
10763 	u8         regs_31_to_0[0x20];
10764 };
10765 
10766 struct mlx5_ifc_mcam_access_reg_bits3 {
10767 	u8         regs_127_to_96[0x20];
10768 
10769 	u8         regs_95_to_64[0x20];
10770 
10771 	u8         regs_63_to_32[0x20];
10772 
10773 	u8         regs_31_to_3[0x1d];
10774 	u8         mrtcq[0x1];
10775 	u8         mtctr[0x1];
10776 	u8         mtptm[0x1];
10777 };
10778 
10779 struct mlx5_ifc_mcam_reg_bits {
10780 	u8         reserved_at_0[0x8];
10781 	u8         feature_group[0x8];
10782 	u8         reserved_at_10[0x8];
10783 	u8         access_reg_group[0x8];
10784 
10785 	u8         reserved_at_20[0x20];
10786 
10787 	union {
10788 		struct mlx5_ifc_mcam_access_reg_bits access_regs;
10789 		struct mlx5_ifc_mcam_access_reg_bits1 access_regs1;
10790 		struct mlx5_ifc_mcam_access_reg_bits2 access_regs2;
10791 		struct mlx5_ifc_mcam_access_reg_bits3 access_regs3;
10792 		u8         reserved_at_0[0x80];
10793 	} mng_access_reg_cap_mask;
10794 
10795 	u8         reserved_at_c0[0x80];
10796 
10797 	union {
10798 		struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features;
10799 		u8         reserved_at_0[0x80];
10800 	} mng_feature_cap_mask;
10801 
10802 	u8         reserved_at_1c0[0x80];
10803 };
10804 
10805 struct mlx5_ifc_qcam_access_reg_cap_mask {
10806 	u8         qcam_access_reg_cap_mask_127_to_20[0x6C];
10807 	u8         qpdpm[0x1];
10808 	u8         qcam_access_reg_cap_mask_18_to_4[0x0F];
10809 	u8         qdpm[0x1];
10810 	u8         qpts[0x1];
10811 	u8         qcap[0x1];
10812 	u8         qcam_access_reg_cap_mask_0[0x1];
10813 };
10814 
10815 struct mlx5_ifc_qcam_qos_feature_cap_mask {
10816 	u8         qcam_qos_feature_cap_mask_127_to_1[0x7F];
10817 	u8         qpts_trust_both[0x1];
10818 };
10819 
10820 struct mlx5_ifc_qcam_reg_bits {
10821 	u8         reserved_at_0[0x8];
10822 	u8         feature_group[0x8];
10823 	u8         reserved_at_10[0x8];
10824 	u8         access_reg_group[0x8];
10825 	u8         reserved_at_20[0x20];
10826 
10827 	union {
10828 		struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap;
10829 		u8  reserved_at_0[0x80];
10830 	} qos_access_reg_cap_mask;
10831 
10832 	u8         reserved_at_c0[0x80];
10833 
10834 	union {
10835 		struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap;
10836 		u8  reserved_at_0[0x80];
10837 	} qos_feature_cap_mask;
10838 
10839 	u8         reserved_at_1c0[0x80];
10840 };
10841 
10842 struct mlx5_ifc_core_dump_reg_bits {
10843 	u8         reserved_at_0[0x18];
10844 	u8         core_dump_type[0x8];
10845 
10846 	u8         reserved_at_20[0x30];
10847 	u8         vhca_id[0x10];
10848 
10849 	u8         reserved_at_60[0x8];
10850 	u8         qpn[0x18];
10851 	u8         reserved_at_80[0x180];
10852 };
10853 
10854 struct mlx5_ifc_pcap_reg_bits {
10855 	u8         reserved_at_0[0x8];
10856 	u8         local_port[0x8];
10857 	u8         reserved_at_10[0x10];
10858 
10859 	u8         port_capability_mask[4][0x20];
10860 };
10861 
10862 struct mlx5_ifc_paos_reg_bits {
10863 	u8         swid[0x8];
10864 	u8         local_port[0x8];
10865 	u8         reserved_at_10[0x4];
10866 	u8         admin_status[0x4];
10867 	u8         reserved_at_18[0x4];
10868 	u8         oper_status[0x4];
10869 
10870 	u8         ase[0x1];
10871 	u8         ee[0x1];
10872 	u8         reserved_at_22[0x1c];
10873 	u8         e[0x2];
10874 
10875 	u8         reserved_at_40[0x40];
10876 };
10877 
10878 struct mlx5_ifc_pamp_reg_bits {
10879 	u8         reserved_at_0[0x8];
10880 	u8         opamp_group[0x8];
10881 	u8         reserved_at_10[0xc];
10882 	u8         opamp_group_type[0x4];
10883 
10884 	u8         start_index[0x10];
10885 	u8         reserved_at_30[0x4];
10886 	u8         num_of_indices[0xc];
10887 
10888 	u8         index_data[18][0x10];
10889 };
10890 
10891 struct mlx5_ifc_pcmr_reg_bits {
10892 	u8         reserved_at_0[0x8];
10893 	u8         local_port[0x8];
10894 	u8         reserved_at_10[0x10];
10895 
10896 	u8         entropy_force_cap[0x1];
10897 	u8         entropy_calc_cap[0x1];
10898 	u8         entropy_gre_calc_cap[0x1];
10899 	u8         reserved_at_23[0xf];
10900 	u8         rx_ts_over_crc_cap[0x1];
10901 	u8         reserved_at_33[0xb];
10902 	u8         fcs_cap[0x1];
10903 	u8         reserved_at_3f[0x1];
10904 
10905 	u8         entropy_force[0x1];
10906 	u8         entropy_calc[0x1];
10907 	u8         entropy_gre_calc[0x1];
10908 	u8         reserved_at_43[0xf];
10909 	u8         rx_ts_over_crc[0x1];
10910 	u8         reserved_at_53[0xb];
10911 	u8         fcs_chk[0x1];
10912 	u8         reserved_at_5f[0x1];
10913 };
10914 
10915 struct mlx5_ifc_lane_2_module_mapping_bits {
10916 	u8         reserved_at_0[0x4];
10917 	u8         rx_lane[0x4];
10918 	u8         reserved_at_8[0x4];
10919 	u8         tx_lane[0x4];
10920 	u8         reserved_at_10[0x8];
10921 	u8         module[0x8];
10922 };
10923 
10924 struct mlx5_ifc_bufferx_reg_bits {
10925 	u8         reserved_at_0[0x6];
10926 	u8         lossy[0x1];
10927 	u8         epsb[0x1];
10928 	u8         reserved_at_8[0x8];
10929 	u8         size[0x10];
10930 
10931 	u8         xoff_threshold[0x10];
10932 	u8         xon_threshold[0x10];
10933 };
10934 
10935 struct mlx5_ifc_set_node_in_bits {
10936 	u8         node_description[64][0x8];
10937 };
10938 
10939 struct mlx5_ifc_register_power_settings_bits {
10940 	u8         reserved_at_0[0x18];
10941 	u8         power_settings_level[0x8];
10942 
10943 	u8         reserved_at_20[0x60];
10944 };
10945 
10946 struct mlx5_ifc_register_host_endianness_bits {
10947 	u8         he[0x1];
10948 	u8         reserved_at_1[0x1f];
10949 
10950 	u8         reserved_at_20[0x60];
10951 };
10952 
10953 struct mlx5_ifc_umr_pointer_desc_argument_bits {
10954 	u8         reserved_at_0[0x20];
10955 
10956 	u8         mkey[0x20];
10957 
10958 	u8         addressh_63_32[0x20];
10959 
10960 	u8         addressl_31_0[0x20];
10961 };
10962 
10963 struct mlx5_ifc_ud_adrs_vector_bits {
10964 	u8         dc_key[0x40];
10965 
10966 	u8         ext[0x1];
10967 	u8         reserved_at_41[0x7];
10968 	u8         destination_qp_dct[0x18];
10969 
10970 	u8         static_rate[0x4];
10971 	u8         sl_eth_prio[0x4];
10972 	u8         fl[0x1];
10973 	u8         mlid[0x7];
10974 	u8         rlid_udp_sport[0x10];
10975 
10976 	u8         reserved_at_80[0x20];
10977 
10978 	u8         rmac_47_16[0x20];
10979 
10980 	u8         rmac_15_0[0x10];
10981 	u8         tclass[0x8];
10982 	u8         hop_limit[0x8];
10983 
10984 	u8         reserved_at_e0[0x1];
10985 	u8         grh[0x1];
10986 	u8         reserved_at_e2[0x2];
10987 	u8         src_addr_index[0x8];
10988 	u8         flow_label[0x14];
10989 
10990 	u8         rgid_rip[16][0x8];
10991 };
10992 
10993 struct mlx5_ifc_pages_req_event_bits {
10994 	u8         reserved_at_0[0x10];
10995 	u8         function_id[0x10];
10996 
10997 	u8         num_pages[0x20];
10998 
10999 	u8         reserved_at_40[0xa0];
11000 };
11001 
11002 struct mlx5_ifc_eqe_bits {
11003 	u8         reserved_at_0[0x8];
11004 	u8         event_type[0x8];
11005 	u8         reserved_at_10[0x8];
11006 	u8         event_sub_type[0x8];
11007 
11008 	u8         reserved_at_20[0xe0];
11009 
11010 	union mlx5_ifc_event_auto_bits event_data;
11011 
11012 	u8         reserved_at_1e0[0x10];
11013 	u8         signature[0x8];
11014 	u8         reserved_at_1f8[0x7];
11015 	u8         owner[0x1];
11016 };
11017 
11018 enum {
11019 	MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT  = 0x7,
11020 };
11021 
11022 struct mlx5_ifc_cmd_queue_entry_bits {
11023 	u8         type[0x8];
11024 	u8         reserved_at_8[0x18];
11025 
11026 	u8         input_length[0x20];
11027 
11028 	u8         input_mailbox_pointer_63_32[0x20];
11029 
11030 	u8         input_mailbox_pointer_31_9[0x17];
11031 	u8         reserved_at_77[0x9];
11032 
11033 	u8         command_input_inline_data[16][0x8];
11034 
11035 	u8         command_output_inline_data[16][0x8];
11036 
11037 	u8         output_mailbox_pointer_63_32[0x20];
11038 
11039 	u8         output_mailbox_pointer_31_9[0x17];
11040 	u8         reserved_at_1b7[0x9];
11041 
11042 	u8         output_length[0x20];
11043 
11044 	u8         token[0x8];
11045 	u8         signature[0x8];
11046 	u8         reserved_at_1f0[0x8];
11047 	u8         status[0x7];
11048 	u8         ownership[0x1];
11049 };
11050 
11051 struct mlx5_ifc_cmd_out_bits {
11052 	u8         status[0x8];
11053 	u8         reserved_at_8[0x18];
11054 
11055 	u8         syndrome[0x20];
11056 
11057 	u8         command_output[0x20];
11058 };
11059 
11060 struct mlx5_ifc_cmd_in_bits {
11061 	u8         opcode[0x10];
11062 	u8         reserved_at_10[0x10];
11063 
11064 	u8         reserved_at_20[0x10];
11065 	u8         op_mod[0x10];
11066 
11067 	u8         command[][0x20];
11068 };
11069 
11070 struct mlx5_ifc_cmd_if_box_bits {
11071 	u8         mailbox_data[512][0x8];
11072 
11073 	u8         reserved_at_1000[0x180];
11074 
11075 	u8         next_pointer_63_32[0x20];
11076 
11077 	u8         next_pointer_31_10[0x16];
11078 	u8         reserved_at_11b6[0xa];
11079 
11080 	u8         block_number[0x20];
11081 
11082 	u8         reserved_at_11e0[0x8];
11083 	u8         token[0x8];
11084 	u8         ctrl_signature[0x8];
11085 	u8         signature[0x8];
11086 };
11087 
11088 struct mlx5_ifc_mtt_bits {
11089 	u8         ptag_63_32[0x20];
11090 
11091 	u8         ptag_31_8[0x18];
11092 	u8         reserved_at_38[0x6];
11093 	u8         wr_en[0x1];
11094 	u8         rd_en[0x1];
11095 };
11096 
11097 struct mlx5_ifc_query_wol_rol_out_bits {
11098 	u8         status[0x8];
11099 	u8         reserved_at_8[0x18];
11100 
11101 	u8         syndrome[0x20];
11102 
11103 	u8         reserved_at_40[0x10];
11104 	u8         rol_mode[0x8];
11105 	u8         wol_mode[0x8];
11106 
11107 	u8         reserved_at_60[0x20];
11108 };
11109 
11110 struct mlx5_ifc_query_wol_rol_in_bits {
11111 	u8         opcode[0x10];
11112 	u8         reserved_at_10[0x10];
11113 
11114 	u8         reserved_at_20[0x10];
11115 	u8         op_mod[0x10];
11116 
11117 	u8         reserved_at_40[0x40];
11118 };
11119 
11120 struct mlx5_ifc_set_wol_rol_out_bits {
11121 	u8         status[0x8];
11122 	u8         reserved_at_8[0x18];
11123 
11124 	u8         syndrome[0x20];
11125 
11126 	u8         reserved_at_40[0x40];
11127 };
11128 
11129 struct mlx5_ifc_set_wol_rol_in_bits {
11130 	u8         opcode[0x10];
11131 	u8         reserved_at_10[0x10];
11132 
11133 	u8         reserved_at_20[0x10];
11134 	u8         op_mod[0x10];
11135 
11136 	u8         rol_mode_valid[0x1];
11137 	u8         wol_mode_valid[0x1];
11138 	u8         reserved_at_42[0xe];
11139 	u8         rol_mode[0x8];
11140 	u8         wol_mode[0x8];
11141 
11142 	u8         reserved_at_60[0x20];
11143 };
11144 
11145 enum {
11146 	MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER  = 0x0,
11147 	MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED     = 0x1,
11148 	MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC  = 0x2,
11149 	MLX5_INITIAL_SEG_NIC_INTERFACE_SW_RESET     = 0x7,
11150 };
11151 
11152 enum {
11153 	MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER  = 0x0,
11154 	MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED     = 0x1,
11155 	MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC  = 0x2,
11156 };
11157 
11158 enum {
11159 	MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR              = 0x1,
11160 	MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC                   = 0x7,
11161 	MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR                 = 0x8,
11162 	MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR                   = 0x9,
11163 	MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR            = 0xa,
11164 	MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR                 = 0xb,
11165 	MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN  = 0xc,
11166 	MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR                    = 0xd,
11167 	MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV                       = 0xe,
11168 	MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR                    = 0xf,
11169 	MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR                = 0x10,
11170 	MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PCI_POISONED_ERR         = 0x12,
11171 	MLX5_INITIAL_SEG_HEALTH_SYNDROME_TRUST_LOCKDOWN_ERR           = 0x13,
11172 };
11173 
11174 struct mlx5_ifc_initial_seg_bits {
11175 	u8         fw_rev_minor[0x10];
11176 	u8         fw_rev_major[0x10];
11177 
11178 	u8         cmd_interface_rev[0x10];
11179 	u8         fw_rev_subminor[0x10];
11180 
11181 	u8         reserved_at_40[0x40];
11182 
11183 	u8         cmdq_phy_addr_63_32[0x20];
11184 
11185 	u8         cmdq_phy_addr_31_12[0x14];
11186 	u8         reserved_at_b4[0x2];
11187 	u8         nic_interface[0x2];
11188 	u8         log_cmdq_size[0x4];
11189 	u8         log_cmdq_stride[0x4];
11190 
11191 	u8         command_doorbell_vector[0x20];
11192 
11193 	u8         reserved_at_e0[0xf00];
11194 
11195 	u8         initializing[0x1];
11196 	u8         reserved_at_fe1[0x4];
11197 	u8         nic_interface_supported[0x3];
11198 	u8         embedded_cpu[0x1];
11199 	u8         reserved_at_fe9[0x17];
11200 
11201 	struct mlx5_ifc_health_buffer_bits health_buffer;
11202 
11203 	u8         no_dram_nic_offset[0x20];
11204 
11205 	u8         reserved_at_1220[0x6e40];
11206 
11207 	u8         reserved_at_8060[0x1f];
11208 	u8         clear_int[0x1];
11209 
11210 	u8         health_syndrome[0x8];
11211 	u8         health_counter[0x18];
11212 
11213 	u8         reserved_at_80a0[0x17fc0];
11214 };
11215 
11216 struct mlx5_ifc_mtpps_reg_bits {
11217 	u8         reserved_at_0[0xc];
11218 	u8         cap_number_of_pps_pins[0x4];
11219 	u8         reserved_at_10[0x4];
11220 	u8         cap_max_num_of_pps_in_pins[0x4];
11221 	u8         reserved_at_18[0x4];
11222 	u8         cap_max_num_of_pps_out_pins[0x4];
11223 
11224 	u8         reserved_at_20[0x13];
11225 	u8         cap_log_min_npps_period[0x5];
11226 	u8         reserved_at_38[0x3];
11227 	u8         cap_log_min_out_pulse_duration_ns[0x5];
11228 
11229 	u8         reserved_at_40[0x4];
11230 	u8         cap_pin_3_mode[0x4];
11231 	u8         reserved_at_48[0x4];
11232 	u8         cap_pin_2_mode[0x4];
11233 	u8         reserved_at_50[0x4];
11234 	u8         cap_pin_1_mode[0x4];
11235 	u8         reserved_at_58[0x4];
11236 	u8         cap_pin_0_mode[0x4];
11237 
11238 	u8         reserved_at_60[0x4];
11239 	u8         cap_pin_7_mode[0x4];
11240 	u8         reserved_at_68[0x4];
11241 	u8         cap_pin_6_mode[0x4];
11242 	u8         reserved_at_70[0x4];
11243 	u8         cap_pin_5_mode[0x4];
11244 	u8         reserved_at_78[0x4];
11245 	u8         cap_pin_4_mode[0x4];
11246 
11247 	u8         field_select[0x20];
11248 	u8         reserved_at_a0[0x20];
11249 
11250 	u8         npps_period[0x40];
11251 
11252 	u8         enable[0x1];
11253 	u8         reserved_at_101[0xb];
11254 	u8         pattern[0x4];
11255 	u8         reserved_at_110[0x4];
11256 	u8         pin_mode[0x4];
11257 	u8         pin[0x8];
11258 
11259 	u8         reserved_at_120[0x2];
11260 	u8         out_pulse_duration_ns[0x1e];
11261 
11262 	u8         time_stamp[0x40];
11263 
11264 	u8         out_pulse_duration[0x10];
11265 	u8         out_periodic_adjustment[0x10];
11266 	u8         enhanced_out_periodic_adjustment[0x20];
11267 
11268 	u8         reserved_at_1c0[0x20];
11269 };
11270 
11271 struct mlx5_ifc_mtppse_reg_bits {
11272 	u8         reserved_at_0[0x18];
11273 	u8         pin[0x8];
11274 	u8         event_arm[0x1];
11275 	u8         reserved_at_21[0x1b];
11276 	u8         event_generation_mode[0x4];
11277 	u8         reserved_at_40[0x40];
11278 };
11279 
11280 struct mlx5_ifc_mcqs_reg_bits {
11281 	u8         last_index_flag[0x1];
11282 	u8         reserved_at_1[0x7];
11283 	u8         fw_device[0x8];
11284 	u8         component_index[0x10];
11285 
11286 	u8         reserved_at_20[0x10];
11287 	u8         identifier[0x10];
11288 
11289 	u8         reserved_at_40[0x17];
11290 	u8         component_status[0x5];
11291 	u8         component_update_state[0x4];
11292 
11293 	u8         last_update_state_changer_type[0x4];
11294 	u8         last_update_state_changer_host_id[0x4];
11295 	u8         reserved_at_68[0x18];
11296 };
11297 
11298 struct mlx5_ifc_mcqi_cap_bits {
11299 	u8         supported_info_bitmask[0x20];
11300 
11301 	u8         component_size[0x20];
11302 
11303 	u8         max_component_size[0x20];
11304 
11305 	u8         log_mcda_word_size[0x4];
11306 	u8         reserved_at_64[0xc];
11307 	u8         mcda_max_write_size[0x10];
11308 
11309 	u8         rd_en[0x1];
11310 	u8         reserved_at_81[0x1];
11311 	u8         match_chip_id[0x1];
11312 	u8         match_psid[0x1];
11313 	u8         check_user_timestamp[0x1];
11314 	u8         match_base_guid_mac[0x1];
11315 	u8         reserved_at_86[0x1a];
11316 };
11317 
11318 struct mlx5_ifc_mcqi_version_bits {
11319 	u8         reserved_at_0[0x2];
11320 	u8         build_time_valid[0x1];
11321 	u8         user_defined_time_valid[0x1];
11322 	u8         reserved_at_4[0x14];
11323 	u8         version_string_length[0x8];
11324 
11325 	u8         version[0x20];
11326 
11327 	u8         build_time[0x40];
11328 
11329 	u8         user_defined_time[0x40];
11330 
11331 	u8         build_tool_version[0x20];
11332 
11333 	u8         reserved_at_e0[0x20];
11334 
11335 	u8         version_string[92][0x8];
11336 };
11337 
11338 struct mlx5_ifc_mcqi_activation_method_bits {
11339 	u8         pending_server_ac_power_cycle[0x1];
11340 	u8         pending_server_dc_power_cycle[0x1];
11341 	u8         pending_server_reboot[0x1];
11342 	u8         pending_fw_reset[0x1];
11343 	u8         auto_activate[0x1];
11344 	u8         all_hosts_sync[0x1];
11345 	u8         device_hw_reset[0x1];
11346 	u8         reserved_at_7[0x19];
11347 };
11348 
11349 union mlx5_ifc_mcqi_reg_data_bits {
11350 	struct mlx5_ifc_mcqi_cap_bits               mcqi_caps;
11351 	struct mlx5_ifc_mcqi_version_bits           mcqi_version;
11352 	struct mlx5_ifc_mcqi_activation_method_bits mcqi_activation_mathod;
11353 };
11354 
11355 struct mlx5_ifc_mcqi_reg_bits {
11356 	u8         read_pending_component[0x1];
11357 	u8         reserved_at_1[0xf];
11358 	u8         component_index[0x10];
11359 
11360 	u8         reserved_at_20[0x20];
11361 
11362 	u8         reserved_at_40[0x1b];
11363 	u8         info_type[0x5];
11364 
11365 	u8         info_size[0x20];
11366 
11367 	u8         offset[0x20];
11368 
11369 	u8         reserved_at_a0[0x10];
11370 	u8         data_size[0x10];
11371 
11372 	union mlx5_ifc_mcqi_reg_data_bits data[];
11373 };
11374 
11375 struct mlx5_ifc_mcc_reg_bits {
11376 	u8         reserved_at_0[0x4];
11377 	u8         time_elapsed_since_last_cmd[0xc];
11378 	u8         reserved_at_10[0x8];
11379 	u8         instruction[0x8];
11380 
11381 	u8         reserved_at_20[0x10];
11382 	u8         component_index[0x10];
11383 
11384 	u8         reserved_at_40[0x8];
11385 	u8         update_handle[0x18];
11386 
11387 	u8         handle_owner_type[0x4];
11388 	u8         handle_owner_host_id[0x4];
11389 	u8         reserved_at_68[0x1];
11390 	u8         control_progress[0x7];
11391 	u8         error_code[0x8];
11392 	u8         reserved_at_78[0x4];
11393 	u8         control_state[0x4];
11394 
11395 	u8         component_size[0x20];
11396 
11397 	u8         reserved_at_a0[0x60];
11398 };
11399 
11400 struct mlx5_ifc_mcda_reg_bits {
11401 	u8         reserved_at_0[0x8];
11402 	u8         update_handle[0x18];
11403 
11404 	u8         offset[0x20];
11405 
11406 	u8         reserved_at_40[0x10];
11407 	u8         size[0x10];
11408 
11409 	u8         reserved_at_60[0x20];
11410 
11411 	u8         data[][0x20];
11412 };
11413 
11414 enum {
11415 	MLX5_MFRL_REG_PCI_RESET_METHOD_LINK_TOGGLE = 0,
11416 	MLX5_MFRL_REG_PCI_RESET_METHOD_HOT_RESET = 1,
11417 };
11418 
11419 enum {
11420 	MLX5_MFRL_REG_RESET_STATE_IDLE = 0,
11421 	MLX5_MFRL_REG_RESET_STATE_IN_NEGOTIATION = 1,
11422 	MLX5_MFRL_REG_RESET_STATE_RESET_IN_PROGRESS = 2,
11423 	MLX5_MFRL_REG_RESET_STATE_NEG_TIMEOUT = 3,
11424 	MLX5_MFRL_REG_RESET_STATE_NACK = 4,
11425 	MLX5_MFRL_REG_RESET_STATE_UNLOAD_TIMEOUT = 5,
11426 };
11427 
11428 enum {
11429 	MLX5_MFRL_REG_RESET_TYPE_FULL_CHIP = BIT(0),
11430 	MLX5_MFRL_REG_RESET_TYPE_NET_PORT_ALIVE = BIT(1),
11431 };
11432 
11433 enum {
11434 	MLX5_MFRL_REG_RESET_LEVEL0 = BIT(0),
11435 	MLX5_MFRL_REG_RESET_LEVEL3 = BIT(3),
11436 	MLX5_MFRL_REG_RESET_LEVEL6 = BIT(6),
11437 };
11438 
11439 struct mlx5_ifc_mfrl_reg_bits {
11440 	u8         reserved_at_0[0x20];
11441 
11442 	u8         reserved_at_20[0x2];
11443 	u8         pci_sync_for_fw_update_start[0x1];
11444 	u8         pci_sync_for_fw_update_resp[0x2];
11445 	u8         rst_type_sel[0x3];
11446 	u8         pci_reset_req_method[0x3];
11447 	u8         reserved_at_2b[0x1];
11448 	u8         reset_state[0x4];
11449 	u8         reset_type[0x8];
11450 	u8         reset_level[0x8];
11451 };
11452 
11453 struct mlx5_ifc_mirc_reg_bits {
11454 	u8         reserved_at_0[0x18];
11455 	u8         status_code[0x8];
11456 
11457 	u8         reserved_at_20[0x20];
11458 };
11459 
11460 struct mlx5_ifc_pddr_monitor_opcode_bits {
11461 	u8         reserved_at_0[0x10];
11462 	u8         monitor_opcode[0x10];
11463 };
11464 
11465 union mlx5_ifc_pddr_troubleshooting_page_status_opcode_auto_bits {
11466 	struct mlx5_ifc_pddr_monitor_opcode_bits pddr_monitor_opcode;
11467 	u8         reserved_at_0[0x20];
11468 };
11469 
11470 enum {
11471 	/* Monitor opcodes */
11472 	MLX5_PDDR_REG_TRBLSH_GROUP_OPCODE_MONITOR = 0x0,
11473 };
11474 
11475 struct mlx5_ifc_pddr_troubleshooting_page_bits {
11476 	u8         reserved_at_0[0x10];
11477 	u8         group_opcode[0x10];
11478 
11479 	union mlx5_ifc_pddr_troubleshooting_page_status_opcode_auto_bits status_opcode;
11480 
11481 	u8         reserved_at_40[0x20];
11482 
11483 	u8         status_message[59][0x20];
11484 };
11485 
11486 union mlx5_ifc_pddr_reg_page_data_auto_bits {
11487 	struct mlx5_ifc_pddr_troubleshooting_page_bits pddr_troubleshooting_page;
11488 	u8         reserved_at_0[0x7c0];
11489 };
11490 
11491 enum {
11492 	MLX5_PDDR_REG_PAGE_SELECT_TROUBLESHOOTING_INFO_PAGE      = 0x1,
11493 };
11494 
11495 struct mlx5_ifc_pddr_reg_bits {
11496 	u8         reserved_at_0[0x8];
11497 	u8         local_port[0x8];
11498 	u8         pnat[0x2];
11499 	u8         reserved_at_12[0xe];
11500 
11501 	u8         reserved_at_20[0x18];
11502 	u8         page_select[0x8];
11503 
11504 	union mlx5_ifc_pddr_reg_page_data_auto_bits page_data;
11505 };
11506 
11507 struct mlx5_ifc_mrtc_reg_bits {
11508 	u8         time_synced[0x1];
11509 	u8         reserved_at_1[0x1f];
11510 
11511 	u8         reserved_at_20[0x20];
11512 
11513 	u8         time_h[0x20];
11514 
11515 	u8         time_l[0x20];
11516 };
11517 
11518 struct mlx5_ifc_mtcap_reg_bits {
11519 	u8         reserved_at_0[0x19];
11520 	u8         sensor_count[0x7];
11521 
11522 	u8         reserved_at_20[0x20];
11523 
11524 	u8         sensor_map[0x40];
11525 };
11526 
11527 struct mlx5_ifc_mtmp_reg_bits {
11528 	u8         reserved_at_0[0x14];
11529 	u8         sensor_index[0xc];
11530 
11531 	u8         reserved_at_20[0x10];
11532 	u8         temperature[0x10];
11533 
11534 	u8         mte[0x1];
11535 	u8         mtr[0x1];
11536 	u8         reserved_at_42[0xe];
11537 	u8         max_temperature[0x10];
11538 
11539 	u8         tee[0x2];
11540 	u8         reserved_at_62[0xe];
11541 	u8         temp_threshold_hi[0x10];
11542 
11543 	u8         reserved_at_80[0x10];
11544 	u8         temp_threshold_lo[0x10];
11545 
11546 	u8         reserved_at_a0[0x20];
11547 
11548 	u8         sensor_name_hi[0x20];
11549 	u8         sensor_name_lo[0x20];
11550 };
11551 
11552 struct mlx5_ifc_mtptm_reg_bits {
11553 	u8         reserved_at_0[0x10];
11554 	u8         psta[0x1];
11555 	u8         reserved_at_11[0xf];
11556 
11557 	u8         reserved_at_20[0x60];
11558 };
11559 
11560 enum {
11561 	MLX5_MTCTR_REQUEST_NOP = 0x0,
11562 	MLX5_MTCTR_REQUEST_PTM_ROOT_CLOCK = 0x1,
11563 	MLX5_MTCTR_REQUEST_FREE_RUNNING_COUNTER = 0x2,
11564 	MLX5_MTCTR_REQUEST_REAL_TIME_CLOCK = 0x3,
11565 };
11566 
11567 struct mlx5_ifc_mtctr_reg_bits {
11568 	u8         first_clock_timestamp_request[0x8];
11569 	u8         second_clock_timestamp_request[0x8];
11570 	u8         reserved_at_10[0x10];
11571 
11572 	u8         first_clock_valid[0x1];
11573 	u8         second_clock_valid[0x1];
11574 	u8         reserved_at_22[0x1e];
11575 
11576 	u8         first_clock_timestamp[0x40];
11577 	u8         second_clock_timestamp[0x40];
11578 };
11579 
11580 union mlx5_ifc_ports_control_registers_document_bits {
11581 	struct mlx5_ifc_bufferx_reg_bits bufferx_reg;
11582 	struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
11583 	struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
11584 	struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
11585 	struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
11586 	struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
11587 	struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
11588 	struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout;
11589 	struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout;
11590 	struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping;
11591 	struct mlx5_ifc_pamp_reg_bits pamp_reg;
11592 	struct mlx5_ifc_paos_reg_bits paos_reg;
11593 	struct mlx5_ifc_pcap_reg_bits pcap_reg;
11594 	struct mlx5_ifc_pddr_monitor_opcode_bits pddr_monitor_opcode;
11595 	struct mlx5_ifc_pddr_reg_bits pddr_reg;
11596 	struct mlx5_ifc_pddr_troubleshooting_page_bits pddr_troubleshooting_page;
11597 	struct mlx5_ifc_peir_reg_bits peir_reg;
11598 	struct mlx5_ifc_pelc_reg_bits pelc_reg;
11599 	struct mlx5_ifc_pfcc_reg_bits pfcc_reg;
11600 	struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
11601 	struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
11602 	struct mlx5_ifc_pifr_reg_bits pifr_reg;
11603 	struct mlx5_ifc_pipg_reg_bits pipg_reg;
11604 	struct mlx5_ifc_plbf_reg_bits plbf_reg;
11605 	struct mlx5_ifc_plib_reg_bits plib_reg;
11606 	struct mlx5_ifc_plpc_reg_bits plpc_reg;
11607 	struct mlx5_ifc_pmaos_reg_bits pmaos_reg;
11608 	struct mlx5_ifc_pmlp_reg_bits pmlp_reg;
11609 	struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg;
11610 	struct mlx5_ifc_pmpc_reg_bits pmpc_reg;
11611 	struct mlx5_ifc_pmpe_reg_bits pmpe_reg;
11612 	struct mlx5_ifc_pmpr_reg_bits pmpr_reg;
11613 	struct mlx5_ifc_pmtu_reg_bits pmtu_reg;
11614 	struct mlx5_ifc_ppad_reg_bits ppad_reg;
11615 	struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg;
11616 	struct mlx5_ifc_mpein_reg_bits mpein_reg;
11617 	struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg;
11618 	struct mlx5_ifc_pplm_reg_bits pplm_reg;
11619 	struct mlx5_ifc_pplr_reg_bits pplr_reg;
11620 	struct mlx5_ifc_ppsc_reg_bits ppsc_reg;
11621 	struct mlx5_ifc_pqdr_reg_bits pqdr_reg;
11622 	struct mlx5_ifc_pspa_reg_bits pspa_reg;
11623 	struct mlx5_ifc_ptas_reg_bits ptas_reg;
11624 	struct mlx5_ifc_ptys_reg_bits ptys_reg;
11625 	struct mlx5_ifc_mlcr_reg_bits mlcr_reg;
11626 	struct mlx5_ifc_pude_reg_bits pude_reg;
11627 	struct mlx5_ifc_pvlc_reg_bits pvlc_reg;
11628 	struct mlx5_ifc_slrg_reg_bits slrg_reg;
11629 	struct mlx5_ifc_sltp_reg_bits sltp_reg;
11630 	struct mlx5_ifc_mtpps_reg_bits mtpps_reg;
11631 	struct mlx5_ifc_mtppse_reg_bits mtppse_reg;
11632 	struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg;
11633 	struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits;
11634 	struct mlx5_ifc_fpga_cap_bits fpga_cap_bits;
11635 	struct mlx5_ifc_mcqi_reg_bits mcqi_reg;
11636 	struct mlx5_ifc_mcc_reg_bits mcc_reg;
11637 	struct mlx5_ifc_mcda_reg_bits mcda_reg;
11638 	struct mlx5_ifc_mirc_reg_bits mirc_reg;
11639 	struct mlx5_ifc_mfrl_reg_bits mfrl_reg;
11640 	struct mlx5_ifc_mtutc_reg_bits mtutc_reg;
11641 	struct mlx5_ifc_mrtc_reg_bits mrtc_reg;
11642 	struct mlx5_ifc_mtcap_reg_bits mtcap_reg;
11643 	struct mlx5_ifc_mtmp_reg_bits mtmp_reg;
11644 	struct mlx5_ifc_mtptm_reg_bits mtptm_reg;
11645 	struct mlx5_ifc_mtctr_reg_bits mtctr_reg;
11646 	u8         reserved_at_0[0x60e0];
11647 };
11648 
11649 union mlx5_ifc_debug_enhancements_document_bits {
11650 	struct mlx5_ifc_health_buffer_bits health_buffer;
11651 	u8         reserved_at_0[0x200];
11652 };
11653 
11654 union mlx5_ifc_uplink_pci_interface_document_bits {
11655 	struct mlx5_ifc_initial_seg_bits initial_seg;
11656 	u8         reserved_at_0[0x20060];
11657 };
11658 
11659 struct mlx5_ifc_set_flow_table_root_out_bits {
11660 	u8         status[0x8];
11661 	u8         reserved_at_8[0x18];
11662 
11663 	u8         syndrome[0x20];
11664 
11665 	u8         reserved_at_40[0x40];
11666 };
11667 
11668 struct mlx5_ifc_set_flow_table_root_in_bits {
11669 	u8         opcode[0x10];
11670 	u8         reserved_at_10[0x10];
11671 
11672 	u8         reserved_at_20[0x10];
11673 	u8         op_mod[0x10];
11674 
11675 	u8         other_vport[0x1];
11676 	u8         reserved_at_41[0xf];
11677 	u8         vport_number[0x10];
11678 
11679 	u8         reserved_at_60[0x20];
11680 
11681 	u8         table_type[0x8];
11682 	u8         reserved_at_88[0x7];
11683 	u8         table_of_other_vport[0x1];
11684 	u8         table_vport_number[0x10];
11685 
11686 	u8         reserved_at_a0[0x8];
11687 	u8         table_id[0x18];
11688 
11689 	u8         reserved_at_c0[0x8];
11690 	u8         underlay_qpn[0x18];
11691 	u8         table_eswitch_owner_vhca_id_valid[0x1];
11692 	u8         reserved_at_e1[0xf];
11693 	u8         table_eswitch_owner_vhca_id[0x10];
11694 	u8         reserved_at_100[0x100];
11695 };
11696 
11697 enum {
11698 	MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID     = (1UL << 0),
11699 	MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15),
11700 };
11701 
11702 struct mlx5_ifc_modify_flow_table_out_bits {
11703 	u8         status[0x8];
11704 	u8         reserved_at_8[0x18];
11705 
11706 	u8         syndrome[0x20];
11707 
11708 	u8         reserved_at_40[0x40];
11709 };
11710 
11711 struct mlx5_ifc_modify_flow_table_in_bits {
11712 	u8         opcode[0x10];
11713 	u8         reserved_at_10[0x10];
11714 
11715 	u8         reserved_at_20[0x10];
11716 	u8         op_mod[0x10];
11717 
11718 	u8         other_vport[0x1];
11719 	u8         reserved_at_41[0xf];
11720 	u8         vport_number[0x10];
11721 
11722 	u8         reserved_at_60[0x10];
11723 	u8         modify_field_select[0x10];
11724 
11725 	u8         table_type[0x8];
11726 	u8         reserved_at_88[0x18];
11727 
11728 	u8         reserved_at_a0[0x8];
11729 	u8         table_id[0x18];
11730 
11731 	struct mlx5_ifc_flow_table_context_bits flow_table_context;
11732 };
11733 
11734 struct mlx5_ifc_ets_tcn_config_reg_bits {
11735 	u8         g[0x1];
11736 	u8         b[0x1];
11737 	u8         r[0x1];
11738 	u8         reserved_at_3[0x9];
11739 	u8         group[0x4];
11740 	u8         reserved_at_10[0x9];
11741 	u8         bw_allocation[0x7];
11742 
11743 	u8         reserved_at_20[0xc];
11744 	u8         max_bw_units[0x4];
11745 	u8         reserved_at_30[0x8];
11746 	u8         max_bw_value[0x8];
11747 };
11748 
11749 struct mlx5_ifc_ets_global_config_reg_bits {
11750 	u8         reserved_at_0[0x2];
11751 	u8         r[0x1];
11752 	u8         reserved_at_3[0x1d];
11753 
11754 	u8         reserved_at_20[0xc];
11755 	u8         max_bw_units[0x4];
11756 	u8         reserved_at_30[0x8];
11757 	u8         max_bw_value[0x8];
11758 };
11759 
11760 struct mlx5_ifc_qetc_reg_bits {
11761 	u8                                         reserved_at_0[0x8];
11762 	u8                                         port_number[0x8];
11763 	u8                                         reserved_at_10[0x30];
11764 
11765 	struct mlx5_ifc_ets_tcn_config_reg_bits    tc_configuration[0x8];
11766 	struct mlx5_ifc_ets_global_config_reg_bits global_configuration;
11767 };
11768 
11769 struct mlx5_ifc_qpdpm_dscp_reg_bits {
11770 	u8         e[0x1];
11771 	u8         reserved_at_01[0x0b];
11772 	u8         prio[0x04];
11773 };
11774 
11775 struct mlx5_ifc_qpdpm_reg_bits {
11776 	u8                                     reserved_at_0[0x8];
11777 	u8                                     local_port[0x8];
11778 	u8                                     reserved_at_10[0x10];
11779 	struct mlx5_ifc_qpdpm_dscp_reg_bits    dscp[64];
11780 };
11781 
11782 struct mlx5_ifc_qpts_reg_bits {
11783 	u8         reserved_at_0[0x8];
11784 	u8         local_port[0x8];
11785 	u8         reserved_at_10[0x2d];
11786 	u8         trust_state[0x3];
11787 };
11788 
11789 struct mlx5_ifc_pptb_reg_bits {
11790 	u8         reserved_at_0[0x2];
11791 	u8         mm[0x2];
11792 	u8         reserved_at_4[0x4];
11793 	u8         local_port[0x8];
11794 	u8         reserved_at_10[0x6];
11795 	u8         cm[0x1];
11796 	u8         um[0x1];
11797 	u8         pm[0x8];
11798 
11799 	u8         prio_x_buff[0x20];
11800 
11801 	u8         pm_msb[0x8];
11802 	u8         reserved_at_48[0x10];
11803 	u8         ctrl_buff[0x4];
11804 	u8         untagged_buff[0x4];
11805 };
11806 
11807 struct mlx5_ifc_sbcam_reg_bits {
11808 	u8         reserved_at_0[0x8];
11809 	u8         feature_group[0x8];
11810 	u8         reserved_at_10[0x8];
11811 	u8         access_reg_group[0x8];
11812 
11813 	u8         reserved_at_20[0x20];
11814 
11815 	u8         sb_access_reg_cap_mask[4][0x20];
11816 
11817 	u8         reserved_at_c0[0x80];
11818 
11819 	u8         sb_feature_cap_mask[4][0x20];
11820 
11821 	u8         reserved_at_1c0[0x40];
11822 
11823 	u8         cap_total_buffer_size[0x20];
11824 
11825 	u8         cap_cell_size[0x10];
11826 	u8         cap_max_pg_buffers[0x8];
11827 	u8         cap_num_pool_supported[0x8];
11828 
11829 	u8         reserved_at_240[0x8];
11830 	u8         cap_sbsr_stat_size[0x8];
11831 	u8         cap_max_tclass_data[0x8];
11832 	u8         cap_max_cpu_ingress_tclass_sb[0x8];
11833 };
11834 
11835 struct mlx5_ifc_pbmc_reg_bits {
11836 	u8         reserved_at_0[0x8];
11837 	u8         local_port[0x8];
11838 	u8         reserved_at_10[0x10];
11839 
11840 	u8         xoff_timer_value[0x10];
11841 	u8         xoff_refresh[0x10];
11842 
11843 	u8         reserved_at_40[0x9];
11844 	u8         fullness_threshold[0x7];
11845 	u8         port_buffer_size[0x10];
11846 
11847 	struct mlx5_ifc_bufferx_reg_bits buffer[10];
11848 
11849 	u8         reserved_at_2e0[0x80];
11850 };
11851 
11852 struct mlx5_ifc_sbpr_reg_bits {
11853 	u8         desc[0x1];
11854 	u8         snap[0x1];
11855 	u8         reserved_at_2[0x4];
11856 	u8         dir[0x2];
11857 	u8         reserved_at_8[0x14];
11858 	u8         pool[0x4];
11859 
11860 	u8         infi_size[0x1];
11861 	u8         reserved_at_21[0x7];
11862 	u8         size[0x18];
11863 
11864 	u8         reserved_at_40[0x1c];
11865 	u8         mode[0x4];
11866 
11867 	u8         reserved_at_60[0x8];
11868 	u8         buff_occupancy[0x18];
11869 
11870 	u8         clr[0x1];
11871 	u8         reserved_at_81[0x7];
11872 	u8         max_buff_occupancy[0x18];
11873 
11874 	u8         reserved_at_a0[0x8];
11875 	u8         ext_buff_occupancy[0x18];
11876 };
11877 
11878 struct mlx5_ifc_sbcm_reg_bits {
11879 	u8         desc[0x1];
11880 	u8         snap[0x1];
11881 	u8         reserved_at_2[0x6];
11882 	u8         local_port[0x8];
11883 	u8         pnat[0x2];
11884 	u8         pg_buff[0x6];
11885 	u8         reserved_at_18[0x6];
11886 	u8         dir[0x2];
11887 
11888 	u8         reserved_at_20[0x1f];
11889 	u8         exc[0x1];
11890 
11891 	u8         reserved_at_40[0x40];
11892 
11893 	u8         reserved_at_80[0x8];
11894 	u8         buff_occupancy[0x18];
11895 
11896 	u8         clr[0x1];
11897 	u8         reserved_at_a1[0x7];
11898 	u8         max_buff_occupancy[0x18];
11899 
11900 	u8         reserved_at_c0[0x8];
11901 	u8         min_buff[0x18];
11902 
11903 	u8         infi_max[0x1];
11904 	u8         reserved_at_e1[0x7];
11905 	u8         max_buff[0x18];
11906 
11907 	u8         reserved_at_100[0x20];
11908 
11909 	u8         reserved_at_120[0x1c];
11910 	u8         pool[0x4];
11911 };
11912 
11913 struct mlx5_ifc_qtct_reg_bits {
11914 	u8         reserved_at_0[0x8];
11915 	u8         port_number[0x8];
11916 	u8         reserved_at_10[0xd];
11917 	u8         prio[0x3];
11918 
11919 	u8         reserved_at_20[0x1d];
11920 	u8         tclass[0x3];
11921 };
11922 
11923 struct mlx5_ifc_mcia_reg_bits {
11924 	u8         l[0x1];
11925 	u8         reserved_at_1[0x7];
11926 	u8         module[0x8];
11927 	u8         reserved_at_10[0x8];
11928 	u8         status[0x8];
11929 
11930 	u8         i2c_device_address[0x8];
11931 	u8         page_number[0x8];
11932 	u8         device_address[0x10];
11933 
11934 	u8         reserved_at_40[0x10];
11935 	u8         size[0x10];
11936 
11937 	u8         reserved_at_60[0x20];
11938 
11939 	u8         dword_0[0x20];
11940 	u8         dword_1[0x20];
11941 	u8         dword_2[0x20];
11942 	u8         dword_3[0x20];
11943 	u8         dword_4[0x20];
11944 	u8         dword_5[0x20];
11945 	u8         dword_6[0x20];
11946 	u8         dword_7[0x20];
11947 	u8         dword_8[0x20];
11948 	u8         dword_9[0x20];
11949 	u8         dword_10[0x20];
11950 	u8         dword_11[0x20];
11951 };
11952 
11953 struct mlx5_ifc_dcbx_param_bits {
11954 	u8         dcbx_cee_cap[0x1];
11955 	u8         dcbx_ieee_cap[0x1];
11956 	u8         dcbx_standby_cap[0x1];
11957 	u8         reserved_at_3[0x5];
11958 	u8         port_number[0x8];
11959 	u8         reserved_at_10[0xa];
11960 	u8         max_application_table_size[6];
11961 	u8         reserved_at_20[0x15];
11962 	u8         version_oper[0x3];
11963 	u8         reserved_at_38[5];
11964 	u8         version_admin[0x3];
11965 	u8         willing_admin[0x1];
11966 	u8         reserved_at_41[0x3];
11967 	u8         pfc_cap_oper[0x4];
11968 	u8         reserved_at_48[0x4];
11969 	u8         pfc_cap_admin[0x4];
11970 	u8         reserved_at_50[0x4];
11971 	u8         num_of_tc_oper[0x4];
11972 	u8         reserved_at_58[0x4];
11973 	u8         num_of_tc_admin[0x4];
11974 	u8         remote_willing[0x1];
11975 	u8         reserved_at_61[3];
11976 	u8         remote_pfc_cap[4];
11977 	u8         reserved_at_68[0x14];
11978 	u8         remote_num_of_tc[0x4];
11979 	u8         reserved_at_80[0x18];
11980 	u8         error[0x8];
11981 	u8         reserved_at_a0[0x160];
11982 };
11983 
11984 enum {
11985 	MLX5_LAG_PORT_SELECT_MODE_QUEUE_AFFINITY = 0,
11986 	MLX5_LAG_PORT_SELECT_MODE_PORT_SELECT_FT = 1,
11987 	MLX5_LAG_PORT_SELECT_MODE_PORT_SELECT_MPESW = 2,
11988 };
11989 
11990 struct mlx5_ifc_lagc_bits {
11991 	u8         fdb_selection_mode[0x1];
11992 	u8         reserved_at_1[0x14];
11993 	u8         port_select_mode[0x3];
11994 	u8         reserved_at_18[0x5];
11995 	u8         lag_state[0x3];
11996 
11997 	u8         reserved_at_20[0xc];
11998 	u8         active_port[0x4];
11999 	u8         reserved_at_30[0x4];
12000 	u8         tx_remap_affinity_2[0x4];
12001 	u8         reserved_at_38[0x4];
12002 	u8         tx_remap_affinity_1[0x4];
12003 };
12004 
12005 struct mlx5_ifc_create_lag_out_bits {
12006 	u8         status[0x8];
12007 	u8         reserved_at_8[0x18];
12008 
12009 	u8         syndrome[0x20];
12010 
12011 	u8         reserved_at_40[0x40];
12012 };
12013 
12014 struct mlx5_ifc_create_lag_in_bits {
12015 	u8         opcode[0x10];
12016 	u8         reserved_at_10[0x10];
12017 
12018 	u8         reserved_at_20[0x10];
12019 	u8         op_mod[0x10];
12020 
12021 	struct mlx5_ifc_lagc_bits ctx;
12022 };
12023 
12024 struct mlx5_ifc_modify_lag_out_bits {
12025 	u8         status[0x8];
12026 	u8         reserved_at_8[0x18];
12027 
12028 	u8         syndrome[0x20];
12029 
12030 	u8         reserved_at_40[0x40];
12031 };
12032 
12033 struct mlx5_ifc_modify_lag_in_bits {
12034 	u8         opcode[0x10];
12035 	u8         reserved_at_10[0x10];
12036 
12037 	u8         reserved_at_20[0x10];
12038 	u8         op_mod[0x10];
12039 
12040 	u8         reserved_at_40[0x20];
12041 	u8         field_select[0x20];
12042 
12043 	struct mlx5_ifc_lagc_bits ctx;
12044 };
12045 
12046 struct mlx5_ifc_query_lag_out_bits {
12047 	u8         status[0x8];
12048 	u8         reserved_at_8[0x18];
12049 
12050 	u8         syndrome[0x20];
12051 
12052 	struct mlx5_ifc_lagc_bits ctx;
12053 };
12054 
12055 struct mlx5_ifc_query_lag_in_bits {
12056 	u8         opcode[0x10];
12057 	u8         reserved_at_10[0x10];
12058 
12059 	u8         reserved_at_20[0x10];
12060 	u8         op_mod[0x10];
12061 
12062 	u8         reserved_at_40[0x40];
12063 };
12064 
12065 struct mlx5_ifc_destroy_lag_out_bits {
12066 	u8         status[0x8];
12067 	u8         reserved_at_8[0x18];
12068 
12069 	u8         syndrome[0x20];
12070 
12071 	u8         reserved_at_40[0x40];
12072 };
12073 
12074 struct mlx5_ifc_destroy_lag_in_bits {
12075 	u8         opcode[0x10];
12076 	u8         reserved_at_10[0x10];
12077 
12078 	u8         reserved_at_20[0x10];
12079 	u8         op_mod[0x10];
12080 
12081 	u8         reserved_at_40[0x40];
12082 };
12083 
12084 struct mlx5_ifc_create_vport_lag_out_bits {
12085 	u8         status[0x8];
12086 	u8         reserved_at_8[0x18];
12087 
12088 	u8         syndrome[0x20];
12089 
12090 	u8         reserved_at_40[0x40];
12091 };
12092 
12093 struct mlx5_ifc_create_vport_lag_in_bits {
12094 	u8         opcode[0x10];
12095 	u8         reserved_at_10[0x10];
12096 
12097 	u8         reserved_at_20[0x10];
12098 	u8         op_mod[0x10];
12099 
12100 	u8         reserved_at_40[0x40];
12101 };
12102 
12103 struct mlx5_ifc_destroy_vport_lag_out_bits {
12104 	u8         status[0x8];
12105 	u8         reserved_at_8[0x18];
12106 
12107 	u8         syndrome[0x20];
12108 
12109 	u8         reserved_at_40[0x40];
12110 };
12111 
12112 struct mlx5_ifc_destroy_vport_lag_in_bits {
12113 	u8         opcode[0x10];
12114 	u8         reserved_at_10[0x10];
12115 
12116 	u8         reserved_at_20[0x10];
12117 	u8         op_mod[0x10];
12118 
12119 	u8         reserved_at_40[0x40];
12120 };
12121 
12122 enum {
12123 	MLX5_MODIFY_MEMIC_OP_MOD_ALLOC,
12124 	MLX5_MODIFY_MEMIC_OP_MOD_DEALLOC,
12125 };
12126 
12127 struct mlx5_ifc_modify_memic_in_bits {
12128 	u8         opcode[0x10];
12129 	u8         uid[0x10];
12130 
12131 	u8         reserved_at_20[0x10];
12132 	u8         op_mod[0x10];
12133 
12134 	u8         reserved_at_40[0x20];
12135 
12136 	u8         reserved_at_60[0x18];
12137 	u8         memic_operation_type[0x8];
12138 
12139 	u8         memic_start_addr[0x40];
12140 
12141 	u8         reserved_at_c0[0x140];
12142 };
12143 
12144 struct mlx5_ifc_modify_memic_out_bits {
12145 	u8         status[0x8];
12146 	u8         reserved_at_8[0x18];
12147 
12148 	u8         syndrome[0x20];
12149 
12150 	u8         reserved_at_40[0x40];
12151 
12152 	u8         memic_operation_addr[0x40];
12153 
12154 	u8         reserved_at_c0[0x140];
12155 };
12156 
12157 struct mlx5_ifc_alloc_memic_in_bits {
12158 	u8         opcode[0x10];
12159 	u8         reserved_at_10[0x10];
12160 
12161 	u8         reserved_at_20[0x10];
12162 	u8         op_mod[0x10];
12163 
12164 	u8         reserved_at_30[0x20];
12165 
12166 	u8	   reserved_at_40[0x18];
12167 	u8	   log_memic_addr_alignment[0x8];
12168 
12169 	u8         range_start_addr[0x40];
12170 
12171 	u8         range_size[0x20];
12172 
12173 	u8         memic_size[0x20];
12174 };
12175 
12176 struct mlx5_ifc_alloc_memic_out_bits {
12177 	u8         status[0x8];
12178 	u8         reserved_at_8[0x18];
12179 
12180 	u8         syndrome[0x20];
12181 
12182 	u8         memic_start_addr[0x40];
12183 };
12184 
12185 struct mlx5_ifc_dealloc_memic_in_bits {
12186 	u8         opcode[0x10];
12187 	u8         reserved_at_10[0x10];
12188 
12189 	u8         reserved_at_20[0x10];
12190 	u8         op_mod[0x10];
12191 
12192 	u8         reserved_at_40[0x40];
12193 
12194 	u8         memic_start_addr[0x40];
12195 
12196 	u8         memic_size[0x20];
12197 
12198 	u8         reserved_at_e0[0x20];
12199 };
12200 
12201 struct mlx5_ifc_dealloc_memic_out_bits {
12202 	u8         status[0x8];
12203 	u8         reserved_at_8[0x18];
12204 
12205 	u8         syndrome[0x20];
12206 
12207 	u8         reserved_at_40[0x40];
12208 };
12209 
12210 struct mlx5_ifc_umem_bits {
12211 	u8         reserved_at_0[0x80];
12212 
12213 	u8         ats[0x1];
12214 	u8         reserved_at_81[0x1a];
12215 	u8         log_page_size[0x5];
12216 
12217 	u8         page_offset[0x20];
12218 
12219 	u8         num_of_mtt[0x40];
12220 
12221 	struct mlx5_ifc_mtt_bits  mtt[];
12222 };
12223 
12224 struct mlx5_ifc_uctx_bits {
12225 	u8         cap[0x20];
12226 
12227 	u8         reserved_at_20[0x160];
12228 };
12229 
12230 struct mlx5_ifc_sw_icm_bits {
12231 	u8         modify_field_select[0x40];
12232 
12233 	u8	   reserved_at_40[0x18];
12234 	u8         log_sw_icm_size[0x8];
12235 
12236 	u8         reserved_at_60[0x20];
12237 
12238 	u8         sw_icm_start_addr[0x40];
12239 
12240 	u8         reserved_at_c0[0x140];
12241 };
12242 
12243 struct mlx5_ifc_geneve_tlv_option_bits {
12244 	u8         modify_field_select[0x40];
12245 
12246 	u8         reserved_at_40[0x18];
12247 	u8         geneve_option_fte_index[0x8];
12248 
12249 	u8         option_class[0x10];
12250 	u8         option_type[0x8];
12251 	u8         reserved_at_78[0x3];
12252 	u8         option_data_length[0x5];
12253 
12254 	u8         reserved_at_80[0x180];
12255 };
12256 
12257 struct mlx5_ifc_create_umem_in_bits {
12258 	u8         opcode[0x10];
12259 	u8         uid[0x10];
12260 
12261 	u8         reserved_at_20[0x10];
12262 	u8         op_mod[0x10];
12263 
12264 	u8         reserved_at_40[0x40];
12265 
12266 	struct mlx5_ifc_umem_bits  umem;
12267 };
12268 
12269 struct mlx5_ifc_create_umem_out_bits {
12270 	u8         status[0x8];
12271 	u8         reserved_at_8[0x18];
12272 
12273 	u8         syndrome[0x20];
12274 
12275 	u8         reserved_at_40[0x8];
12276 	u8         umem_id[0x18];
12277 
12278 	u8         reserved_at_60[0x20];
12279 };
12280 
12281 struct mlx5_ifc_destroy_umem_in_bits {
12282 	u8        opcode[0x10];
12283 	u8        uid[0x10];
12284 
12285 	u8        reserved_at_20[0x10];
12286 	u8        op_mod[0x10];
12287 
12288 	u8        reserved_at_40[0x8];
12289 	u8        umem_id[0x18];
12290 
12291 	u8        reserved_at_60[0x20];
12292 };
12293 
12294 struct mlx5_ifc_destroy_umem_out_bits {
12295 	u8        status[0x8];
12296 	u8        reserved_at_8[0x18];
12297 
12298 	u8        syndrome[0x20];
12299 
12300 	u8        reserved_at_40[0x40];
12301 };
12302 
12303 struct mlx5_ifc_create_uctx_in_bits {
12304 	u8         opcode[0x10];
12305 	u8         reserved_at_10[0x10];
12306 
12307 	u8         reserved_at_20[0x10];
12308 	u8         op_mod[0x10];
12309 
12310 	u8         reserved_at_40[0x40];
12311 
12312 	struct mlx5_ifc_uctx_bits  uctx;
12313 };
12314 
12315 struct mlx5_ifc_create_uctx_out_bits {
12316 	u8         status[0x8];
12317 	u8         reserved_at_8[0x18];
12318 
12319 	u8         syndrome[0x20];
12320 
12321 	u8         reserved_at_40[0x10];
12322 	u8         uid[0x10];
12323 
12324 	u8         reserved_at_60[0x20];
12325 };
12326 
12327 struct mlx5_ifc_destroy_uctx_in_bits {
12328 	u8         opcode[0x10];
12329 	u8         reserved_at_10[0x10];
12330 
12331 	u8         reserved_at_20[0x10];
12332 	u8         op_mod[0x10];
12333 
12334 	u8         reserved_at_40[0x10];
12335 	u8         uid[0x10];
12336 
12337 	u8         reserved_at_60[0x20];
12338 };
12339 
12340 struct mlx5_ifc_destroy_uctx_out_bits {
12341 	u8         status[0x8];
12342 	u8         reserved_at_8[0x18];
12343 
12344 	u8         syndrome[0x20];
12345 
12346 	u8          reserved_at_40[0x40];
12347 };
12348 
12349 struct mlx5_ifc_create_sw_icm_in_bits {
12350 	struct mlx5_ifc_general_obj_in_cmd_hdr_bits   hdr;
12351 	struct mlx5_ifc_sw_icm_bits		      sw_icm;
12352 };
12353 
12354 struct mlx5_ifc_create_geneve_tlv_option_in_bits {
12355 	struct mlx5_ifc_general_obj_in_cmd_hdr_bits   hdr;
12356 	struct mlx5_ifc_geneve_tlv_option_bits        geneve_tlv_opt;
12357 };
12358 
12359 struct mlx5_ifc_mtrc_string_db_param_bits {
12360 	u8         string_db_base_address[0x20];
12361 
12362 	u8         reserved_at_20[0x8];
12363 	u8         string_db_size[0x18];
12364 };
12365 
12366 struct mlx5_ifc_mtrc_cap_bits {
12367 	u8         trace_owner[0x1];
12368 	u8         trace_to_memory[0x1];
12369 	u8         reserved_at_2[0x4];
12370 	u8         trc_ver[0x2];
12371 	u8         reserved_at_8[0x14];
12372 	u8         num_string_db[0x4];
12373 
12374 	u8         first_string_trace[0x8];
12375 	u8         num_string_trace[0x8];
12376 	u8         reserved_at_30[0x28];
12377 
12378 	u8         log_max_trace_buffer_size[0x8];
12379 
12380 	u8         reserved_at_60[0x20];
12381 
12382 	struct mlx5_ifc_mtrc_string_db_param_bits string_db_param[8];
12383 
12384 	u8         reserved_at_280[0x180];
12385 };
12386 
12387 struct mlx5_ifc_mtrc_conf_bits {
12388 	u8         reserved_at_0[0x1c];
12389 	u8         trace_mode[0x4];
12390 	u8         reserved_at_20[0x18];
12391 	u8         log_trace_buffer_size[0x8];
12392 	u8         trace_mkey[0x20];
12393 	u8         reserved_at_60[0x3a0];
12394 };
12395 
12396 struct mlx5_ifc_mtrc_stdb_bits {
12397 	u8         string_db_index[0x4];
12398 	u8         reserved_at_4[0x4];
12399 	u8         read_size[0x18];
12400 	u8         start_offset[0x20];
12401 	u8         string_db_data[];
12402 };
12403 
12404 struct mlx5_ifc_mtrc_ctrl_bits {
12405 	u8         trace_status[0x2];
12406 	u8         reserved_at_2[0x2];
12407 	u8         arm_event[0x1];
12408 	u8         reserved_at_5[0xb];
12409 	u8         modify_field_select[0x10];
12410 	u8         reserved_at_20[0x2b];
12411 	u8         current_timestamp52_32[0x15];
12412 	u8         current_timestamp31_0[0x20];
12413 	u8         reserved_at_80[0x180];
12414 };
12415 
12416 struct mlx5_ifc_host_params_context_bits {
12417 	u8         host_number[0x8];
12418 	u8         reserved_at_8[0x5];
12419 	u8         host_pf_not_exist[0x1];
12420 	u8         reserved_at_14[0x1];
12421 	u8         host_pf_disabled[0x1];
12422 	u8         host_num_of_vfs[0x10];
12423 
12424 	u8         host_total_vfs[0x10];
12425 	u8         host_pci_bus[0x10];
12426 
12427 	u8         reserved_at_40[0x10];
12428 	u8         host_pci_device[0x10];
12429 
12430 	u8         reserved_at_60[0x10];
12431 	u8         host_pci_function[0x10];
12432 
12433 	u8         reserved_at_80[0x180];
12434 };
12435 
12436 struct mlx5_ifc_query_esw_functions_in_bits {
12437 	u8         opcode[0x10];
12438 	u8         reserved_at_10[0x10];
12439 
12440 	u8         reserved_at_20[0x10];
12441 	u8         op_mod[0x10];
12442 
12443 	u8         reserved_at_40[0x40];
12444 };
12445 
12446 struct mlx5_ifc_query_esw_functions_out_bits {
12447 	u8         status[0x8];
12448 	u8         reserved_at_8[0x18];
12449 
12450 	u8         syndrome[0x20];
12451 
12452 	u8         reserved_at_40[0x40];
12453 
12454 	struct mlx5_ifc_host_params_context_bits host_params_context;
12455 
12456 	u8         reserved_at_280[0x180];
12457 	u8         host_sf_enable[][0x40];
12458 };
12459 
12460 struct mlx5_ifc_sf_partition_bits {
12461 	u8         reserved_at_0[0x10];
12462 	u8         log_num_sf[0x8];
12463 	u8         log_sf_bar_size[0x8];
12464 };
12465 
12466 struct mlx5_ifc_query_sf_partitions_out_bits {
12467 	u8         status[0x8];
12468 	u8         reserved_at_8[0x18];
12469 
12470 	u8         syndrome[0x20];
12471 
12472 	u8         reserved_at_40[0x18];
12473 	u8         num_sf_partitions[0x8];
12474 
12475 	u8         reserved_at_60[0x20];
12476 
12477 	struct mlx5_ifc_sf_partition_bits sf_partition[];
12478 };
12479 
12480 struct mlx5_ifc_query_sf_partitions_in_bits {
12481 	u8         opcode[0x10];
12482 	u8         reserved_at_10[0x10];
12483 
12484 	u8         reserved_at_20[0x10];
12485 	u8         op_mod[0x10];
12486 
12487 	u8         reserved_at_40[0x40];
12488 };
12489 
12490 struct mlx5_ifc_dealloc_sf_out_bits {
12491 	u8         status[0x8];
12492 	u8         reserved_at_8[0x18];
12493 
12494 	u8         syndrome[0x20];
12495 
12496 	u8         reserved_at_40[0x40];
12497 };
12498 
12499 struct mlx5_ifc_dealloc_sf_in_bits {
12500 	u8         opcode[0x10];
12501 	u8         reserved_at_10[0x10];
12502 
12503 	u8         reserved_at_20[0x10];
12504 	u8         op_mod[0x10];
12505 
12506 	u8         reserved_at_40[0x10];
12507 	u8         function_id[0x10];
12508 
12509 	u8         reserved_at_60[0x20];
12510 };
12511 
12512 struct mlx5_ifc_alloc_sf_out_bits {
12513 	u8         status[0x8];
12514 	u8         reserved_at_8[0x18];
12515 
12516 	u8         syndrome[0x20];
12517 
12518 	u8         reserved_at_40[0x40];
12519 };
12520 
12521 struct mlx5_ifc_alloc_sf_in_bits {
12522 	u8         opcode[0x10];
12523 	u8         reserved_at_10[0x10];
12524 
12525 	u8         reserved_at_20[0x10];
12526 	u8         op_mod[0x10];
12527 
12528 	u8         reserved_at_40[0x10];
12529 	u8         function_id[0x10];
12530 
12531 	u8         reserved_at_60[0x20];
12532 };
12533 
12534 struct mlx5_ifc_affiliated_event_header_bits {
12535 	u8         reserved_at_0[0x10];
12536 	u8         obj_type[0x10];
12537 
12538 	u8         obj_id[0x20];
12539 };
12540 
12541 enum {
12542 	MLX5_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = 0xc,
12543 	MLX5_GENERAL_OBJECT_TYPES_IPSEC = 0x13,
12544 	MLX5_GENERAL_OBJECT_TYPES_SAMPLER = 0x20,
12545 	MLX5_GENERAL_OBJECT_TYPES_FLOW_METER_ASO = 0x24,
12546 	MLX5_GENERAL_OBJECT_TYPES_MACSEC = 0x27,
12547 	MLX5_GENERAL_OBJECT_TYPES_INT_KEK = 0x47,
12548 	MLX5_GENERAL_OBJECT_TYPES_RDMA_CTRL = 0x53,
12549 	MLX5_GENERAL_OBJECT_TYPES_PCIE_CONG_EVENT = 0x58,
12550 	MLX5_GENERAL_OBJECT_TYPES_FLOW_TABLE_ALIAS = 0xff15,
12551 };
12552 
12553 enum {
12554 	MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY =
12555 		BIT_ULL(MLX5_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY),
12556 	MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_IPSEC =
12557 		BIT_ULL(MLX5_GENERAL_OBJECT_TYPES_IPSEC),
12558 	MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_SAMPLER =
12559 		BIT_ULL(MLX5_GENERAL_OBJECT_TYPES_SAMPLER),
12560 	MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_FLOW_METER_ASO =
12561 		BIT_ULL(MLX5_GENERAL_OBJECT_TYPES_FLOW_METER_ASO),
12562 };
12563 
12564 enum {
12565 	MLX5_HCA_CAP_2_GENERAL_OBJECT_TYPES_RDMA_CTRL =
12566 		BIT_ULL(MLX5_GENERAL_OBJECT_TYPES_RDMA_CTRL - 0x40),
12567 	MLX5_HCA_CAP_2_GENERAL_OBJECT_TYPES_PCIE_CONG_EVENT =
12568 		BIT_ULL(MLX5_GENERAL_OBJECT_TYPES_PCIE_CONG_EVENT - 0x40),
12569 };
12570 
12571 enum {
12572 	MLX5_IPSEC_OBJECT_ICV_LEN_16B,
12573 };
12574 
12575 enum {
12576 	MLX5_IPSEC_ASO_REG_C_0_1 = 0x0,
12577 	MLX5_IPSEC_ASO_REG_C_2_3 = 0x1,
12578 	MLX5_IPSEC_ASO_REG_C_4_5 = 0x2,
12579 	MLX5_IPSEC_ASO_REG_C_6_7 = 0x3,
12580 };
12581 
12582 enum {
12583 	MLX5_IPSEC_ASO_MODE              = 0x0,
12584 	MLX5_IPSEC_ASO_REPLAY_PROTECTION = 0x1,
12585 	MLX5_IPSEC_ASO_INC_SN            = 0x2,
12586 };
12587 
12588 enum {
12589 	MLX5_IPSEC_ASO_REPLAY_WIN_32BIT  = 0x0,
12590 	MLX5_IPSEC_ASO_REPLAY_WIN_64BIT  = 0x1,
12591 	MLX5_IPSEC_ASO_REPLAY_WIN_128BIT = 0x2,
12592 	MLX5_IPSEC_ASO_REPLAY_WIN_256BIT = 0x3,
12593 };
12594 
12595 struct mlx5_ifc_ipsec_aso_bits {
12596 	u8         valid[0x1];
12597 	u8         reserved_at_201[0x1];
12598 	u8         mode[0x2];
12599 	u8         window_sz[0x2];
12600 	u8         soft_lft_arm[0x1];
12601 	u8         hard_lft_arm[0x1];
12602 	u8         remove_flow_enable[0x1];
12603 	u8         esn_event_arm[0x1];
12604 	u8         reserved_at_20a[0x16];
12605 
12606 	u8         remove_flow_pkt_cnt[0x20];
12607 
12608 	u8         remove_flow_soft_lft[0x20];
12609 
12610 	u8         reserved_at_260[0x80];
12611 
12612 	u8         mode_parameter[0x20];
12613 
12614 	u8         replay_protection_window[0x100];
12615 };
12616 
12617 struct mlx5_ifc_ipsec_obj_bits {
12618 	u8         modify_field_select[0x40];
12619 	u8         full_offload[0x1];
12620 	u8         reserved_at_41[0x1];
12621 	u8         esn_en[0x1];
12622 	u8         esn_overlap[0x1];
12623 	u8         reserved_at_44[0x2];
12624 	u8         icv_length[0x2];
12625 	u8         reserved_at_48[0x4];
12626 	u8         aso_return_reg[0x4];
12627 	u8         reserved_at_50[0x10];
12628 
12629 	u8         esn_msb[0x20];
12630 
12631 	u8         reserved_at_80[0x8];
12632 	u8         dekn[0x18];
12633 
12634 	u8         salt[0x20];
12635 
12636 	u8         implicit_iv[0x40];
12637 
12638 	u8         reserved_at_100[0x8];
12639 	u8         ipsec_aso_access_pd[0x18];
12640 	u8         reserved_at_120[0xe0];
12641 
12642 	struct mlx5_ifc_ipsec_aso_bits ipsec_aso;
12643 };
12644 
12645 struct mlx5_ifc_create_ipsec_obj_in_bits {
12646 	struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
12647 	struct mlx5_ifc_ipsec_obj_bits ipsec_object;
12648 };
12649 
12650 enum {
12651 	MLX5_MODIFY_IPSEC_BITMASK_ESN_OVERLAP = BIT(0),
12652 	MLX5_MODIFY_IPSEC_BITMASK_ESN_MSB = BIT(1),
12653 };
12654 
12655 struct mlx5_ifc_query_ipsec_obj_out_bits {
12656 	struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr;
12657 	struct mlx5_ifc_ipsec_obj_bits ipsec_object;
12658 };
12659 
12660 struct mlx5_ifc_modify_ipsec_obj_in_bits {
12661 	struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
12662 	struct mlx5_ifc_ipsec_obj_bits ipsec_object;
12663 };
12664 
12665 enum {
12666 	MLX5_MACSEC_ASO_REPLAY_PROTECTION = 0x1,
12667 };
12668 
12669 enum {
12670 	MLX5_MACSEC_ASO_REPLAY_WIN_32BIT  = 0x0,
12671 	MLX5_MACSEC_ASO_REPLAY_WIN_64BIT  = 0x1,
12672 	MLX5_MACSEC_ASO_REPLAY_WIN_128BIT = 0x2,
12673 	MLX5_MACSEC_ASO_REPLAY_WIN_256BIT = 0x3,
12674 };
12675 
12676 #define MLX5_MACSEC_ASO_INC_SN  0x2
12677 #define MLX5_MACSEC_ASO_REG_C_4_5 0x2
12678 
12679 struct mlx5_ifc_macsec_aso_bits {
12680 	u8    valid[0x1];
12681 	u8    reserved_at_1[0x1];
12682 	u8    mode[0x2];
12683 	u8    window_size[0x2];
12684 	u8    soft_lifetime_arm[0x1];
12685 	u8    hard_lifetime_arm[0x1];
12686 	u8    remove_flow_enable[0x1];
12687 	u8    epn_event_arm[0x1];
12688 	u8    reserved_at_a[0x16];
12689 
12690 	u8    remove_flow_packet_count[0x20];
12691 
12692 	u8    remove_flow_soft_lifetime[0x20];
12693 
12694 	u8    reserved_at_60[0x80];
12695 
12696 	u8    mode_parameter[0x20];
12697 
12698 	u8    replay_protection_window[8][0x20];
12699 };
12700 
12701 struct mlx5_ifc_macsec_offload_obj_bits {
12702 	u8    modify_field_select[0x40];
12703 
12704 	u8    confidentiality_en[0x1];
12705 	u8    reserved_at_41[0x1];
12706 	u8    epn_en[0x1];
12707 	u8    epn_overlap[0x1];
12708 	u8    reserved_at_44[0x2];
12709 	u8    confidentiality_offset[0x2];
12710 	u8    reserved_at_48[0x4];
12711 	u8    aso_return_reg[0x4];
12712 	u8    reserved_at_50[0x10];
12713 
12714 	u8    epn_msb[0x20];
12715 
12716 	u8    reserved_at_80[0x8];
12717 	u8    dekn[0x18];
12718 
12719 	u8    reserved_at_a0[0x20];
12720 
12721 	u8    sci[0x40];
12722 
12723 	u8    reserved_at_100[0x8];
12724 	u8    macsec_aso_access_pd[0x18];
12725 
12726 	u8    reserved_at_120[0x60];
12727 
12728 	u8    salt[3][0x20];
12729 
12730 	u8    reserved_at_1e0[0x20];
12731 
12732 	struct mlx5_ifc_macsec_aso_bits macsec_aso;
12733 };
12734 
12735 struct mlx5_ifc_create_macsec_obj_in_bits {
12736 	struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
12737 	struct mlx5_ifc_macsec_offload_obj_bits macsec_object;
12738 };
12739 
12740 struct mlx5_ifc_modify_macsec_obj_in_bits {
12741 	struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
12742 	struct mlx5_ifc_macsec_offload_obj_bits macsec_object;
12743 };
12744 
12745 enum {
12746 	MLX5_MODIFY_MACSEC_BITMASK_EPN_OVERLAP = BIT(0),
12747 	MLX5_MODIFY_MACSEC_BITMASK_EPN_MSB = BIT(1),
12748 };
12749 
12750 struct mlx5_ifc_query_macsec_obj_out_bits {
12751 	struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr;
12752 	struct mlx5_ifc_macsec_offload_obj_bits macsec_object;
12753 };
12754 
12755 struct mlx5_ifc_wrapped_dek_bits {
12756 	u8         gcm_iv[0x60];
12757 
12758 	u8         reserved_at_60[0x20];
12759 
12760 	u8         const0[0x1];
12761 	u8         key_size[0x1];
12762 	u8         reserved_at_82[0x2];
12763 	u8         key2_invalid[0x1];
12764 	u8         reserved_at_85[0x3];
12765 	u8         pd[0x18];
12766 
12767 	u8         key_purpose[0x5];
12768 	u8         reserved_at_a5[0x13];
12769 	u8         kek_id[0x8];
12770 
12771 	u8         reserved_at_c0[0x40];
12772 
12773 	u8         key1[0x8][0x20];
12774 
12775 	u8         key2[0x8][0x20];
12776 
12777 	u8         reserved_at_300[0x40];
12778 
12779 	u8         const1[0x1];
12780 	u8         reserved_at_341[0x1f];
12781 
12782 	u8         reserved_at_360[0x20];
12783 
12784 	u8         auth_tag[0x80];
12785 };
12786 
12787 struct mlx5_ifc_encryption_key_obj_bits {
12788 	u8         modify_field_select[0x40];
12789 
12790 	u8         state[0x8];
12791 	u8         sw_wrapped[0x1];
12792 	u8         reserved_at_49[0xb];
12793 	u8         key_size[0x4];
12794 	u8         reserved_at_58[0x4];
12795 	u8         key_purpose[0x4];
12796 
12797 	u8         reserved_at_60[0x8];
12798 	u8         pd[0x18];
12799 
12800 	u8         reserved_at_80[0x100];
12801 
12802 	u8         opaque[0x40];
12803 
12804 	u8         reserved_at_1c0[0x40];
12805 
12806 	u8         key[8][0x80];
12807 
12808 	u8         sw_wrapped_dek[8][0x80];
12809 
12810 	u8         reserved_at_a00[0x600];
12811 };
12812 
12813 struct mlx5_ifc_create_encryption_key_in_bits {
12814 	struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
12815 	struct mlx5_ifc_encryption_key_obj_bits encryption_key_object;
12816 };
12817 
12818 struct mlx5_ifc_modify_encryption_key_in_bits {
12819 	struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
12820 	struct mlx5_ifc_encryption_key_obj_bits encryption_key_object;
12821 };
12822 
12823 enum {
12824 	MLX5_FLOW_METER_MODE_BYTES_IP_LENGTH		= 0x0,
12825 	MLX5_FLOW_METER_MODE_BYTES_CALC_WITH_L2		= 0x1,
12826 	MLX5_FLOW_METER_MODE_BYTES_CALC_WITH_L2_IPG	= 0x2,
12827 	MLX5_FLOW_METER_MODE_NUM_PACKETS		= 0x3,
12828 };
12829 
12830 struct mlx5_ifc_flow_meter_parameters_bits {
12831 	u8         valid[0x1];
12832 	u8         bucket_overflow[0x1];
12833 	u8         start_color[0x2];
12834 	u8         both_buckets_on_green[0x1];
12835 	u8         reserved_at_5[0x1];
12836 	u8         meter_mode[0x2];
12837 	u8         reserved_at_8[0x18];
12838 
12839 	u8         reserved_at_20[0x20];
12840 
12841 	u8         reserved_at_40[0x3];
12842 	u8         cbs_exponent[0x5];
12843 	u8         cbs_mantissa[0x8];
12844 	u8         reserved_at_50[0x3];
12845 	u8         cir_exponent[0x5];
12846 	u8         cir_mantissa[0x8];
12847 
12848 	u8         reserved_at_60[0x20];
12849 
12850 	u8         reserved_at_80[0x3];
12851 	u8         ebs_exponent[0x5];
12852 	u8         ebs_mantissa[0x8];
12853 	u8         reserved_at_90[0x3];
12854 	u8         eir_exponent[0x5];
12855 	u8         eir_mantissa[0x8];
12856 
12857 	u8         reserved_at_a0[0x60];
12858 };
12859 
12860 struct mlx5_ifc_flow_meter_aso_obj_bits {
12861 	u8         modify_field_select[0x40];
12862 
12863 	u8         reserved_at_40[0x40];
12864 
12865 	u8         reserved_at_80[0x8];
12866 	u8         meter_aso_access_pd[0x18];
12867 
12868 	u8         reserved_at_a0[0x160];
12869 
12870 	struct mlx5_ifc_flow_meter_parameters_bits flow_meter_parameters[2];
12871 };
12872 
12873 struct mlx5_ifc_create_flow_meter_aso_obj_in_bits {
12874 	struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
12875 	struct mlx5_ifc_flow_meter_aso_obj_bits flow_meter_aso_obj;
12876 };
12877 
12878 struct mlx5_ifc_int_kek_obj_bits {
12879 	u8         modify_field_select[0x40];
12880 
12881 	u8         state[0x8];
12882 	u8         auto_gen[0x1];
12883 	u8         reserved_at_49[0xb];
12884 	u8         key_size[0x4];
12885 	u8         reserved_at_58[0x8];
12886 
12887 	u8         reserved_at_60[0x8];
12888 	u8         pd[0x18];
12889 
12890 	u8         reserved_at_80[0x180];
12891 	u8         key[8][0x80];
12892 
12893 	u8         reserved_at_600[0x200];
12894 };
12895 
12896 struct mlx5_ifc_create_int_kek_obj_in_bits {
12897 	struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
12898 	struct mlx5_ifc_int_kek_obj_bits int_kek_object;
12899 };
12900 
12901 struct mlx5_ifc_create_int_kek_obj_out_bits {
12902 	struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr;
12903 	struct mlx5_ifc_int_kek_obj_bits int_kek_object;
12904 };
12905 
12906 struct mlx5_ifc_sampler_obj_bits {
12907 	u8         modify_field_select[0x40];
12908 
12909 	u8         table_type[0x8];
12910 	u8         level[0x8];
12911 	u8         reserved_at_50[0xf];
12912 	u8         ignore_flow_level[0x1];
12913 
12914 	u8         sample_ratio[0x20];
12915 
12916 	u8         reserved_at_80[0x8];
12917 	u8         sample_table_id[0x18];
12918 
12919 	u8         reserved_at_a0[0x8];
12920 	u8         default_table_id[0x18];
12921 
12922 	u8         sw_steering_icm_address_rx[0x40];
12923 	u8         sw_steering_icm_address_tx[0x40];
12924 
12925 	u8         reserved_at_140[0xa0];
12926 };
12927 
12928 struct mlx5_ifc_create_sampler_obj_in_bits {
12929 	struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
12930 	struct mlx5_ifc_sampler_obj_bits sampler_object;
12931 };
12932 
12933 struct mlx5_ifc_query_sampler_obj_out_bits {
12934 	struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr;
12935 	struct mlx5_ifc_sampler_obj_bits sampler_object;
12936 };
12937 
12938 enum {
12939 	MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_128 = 0x0,
12940 	MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_256 = 0x1,
12941 };
12942 
12943 enum {
12944 	MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_PURPOSE_TLS = 0x1,
12945 	MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_PURPOSE_IPSEC = 0x2,
12946 	MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_PURPOSE_MACSEC = 0x4,
12947 };
12948 
12949 struct mlx5_ifc_tls_static_params_bits {
12950 	u8         const_2[0x2];
12951 	u8         tls_version[0x4];
12952 	u8         const_1[0x2];
12953 	u8         reserved_at_8[0x14];
12954 	u8         encryption_standard[0x4];
12955 
12956 	u8         reserved_at_20[0x20];
12957 
12958 	u8         initial_record_number[0x40];
12959 
12960 	u8         resync_tcp_sn[0x20];
12961 
12962 	u8         gcm_iv[0x20];
12963 
12964 	u8         implicit_iv[0x40];
12965 
12966 	u8         reserved_at_100[0x8];
12967 	u8         dek_index[0x18];
12968 
12969 	u8         reserved_at_120[0xe0];
12970 };
12971 
12972 struct mlx5_ifc_tls_progress_params_bits {
12973 	u8         next_record_tcp_sn[0x20];
12974 
12975 	u8         hw_resync_tcp_sn[0x20];
12976 
12977 	u8         record_tracker_state[0x2];
12978 	u8         auth_state[0x2];
12979 	u8         reserved_at_44[0x4];
12980 	u8         hw_offset_record_number[0x18];
12981 };
12982 
12983 enum {
12984 	MLX5_MTT_PERM_READ	= 1 << 0,
12985 	MLX5_MTT_PERM_WRITE	= 1 << 1,
12986 	MLX5_MTT_PERM_RW	= MLX5_MTT_PERM_READ | MLX5_MTT_PERM_WRITE,
12987 };
12988 
12989 enum {
12990 	MLX5_SUSPEND_VHCA_IN_OP_MOD_SUSPEND_INITIATOR  = 0x0,
12991 	MLX5_SUSPEND_VHCA_IN_OP_MOD_SUSPEND_RESPONDER  = 0x1,
12992 };
12993 
12994 struct mlx5_ifc_suspend_vhca_in_bits {
12995 	u8         opcode[0x10];
12996 	u8         uid[0x10];
12997 
12998 	u8         reserved_at_20[0x10];
12999 	u8         op_mod[0x10];
13000 
13001 	u8         reserved_at_40[0x10];
13002 	u8         vhca_id[0x10];
13003 
13004 	u8         reserved_at_60[0x20];
13005 };
13006 
13007 struct mlx5_ifc_suspend_vhca_out_bits {
13008 	u8         status[0x8];
13009 	u8         reserved_at_8[0x18];
13010 
13011 	u8         syndrome[0x20];
13012 
13013 	u8         reserved_at_40[0x40];
13014 };
13015 
13016 enum {
13017 	MLX5_RESUME_VHCA_IN_OP_MOD_RESUME_RESPONDER  = 0x0,
13018 	MLX5_RESUME_VHCA_IN_OP_MOD_RESUME_INITIATOR  = 0x1,
13019 };
13020 
13021 struct mlx5_ifc_resume_vhca_in_bits {
13022 	u8         opcode[0x10];
13023 	u8         uid[0x10];
13024 
13025 	u8         reserved_at_20[0x10];
13026 	u8         op_mod[0x10];
13027 
13028 	u8         reserved_at_40[0x10];
13029 	u8         vhca_id[0x10];
13030 
13031 	u8         reserved_at_60[0x20];
13032 };
13033 
13034 struct mlx5_ifc_resume_vhca_out_bits {
13035 	u8         status[0x8];
13036 	u8         reserved_at_8[0x18];
13037 
13038 	u8         syndrome[0x20];
13039 
13040 	u8         reserved_at_40[0x40];
13041 };
13042 
13043 struct mlx5_ifc_query_vhca_migration_state_in_bits {
13044 	u8         opcode[0x10];
13045 	u8         uid[0x10];
13046 
13047 	u8         reserved_at_20[0x10];
13048 	u8         op_mod[0x10];
13049 
13050 	u8         incremental[0x1];
13051 	u8         chunk[0x1];
13052 	u8         reserved_at_42[0xe];
13053 	u8         vhca_id[0x10];
13054 
13055 	u8         reserved_at_60[0x20];
13056 };
13057 
13058 struct mlx5_ifc_query_vhca_migration_state_out_bits {
13059 	u8         status[0x8];
13060 	u8         reserved_at_8[0x18];
13061 
13062 	u8         syndrome[0x20];
13063 
13064 	u8         reserved_at_40[0x40];
13065 
13066 	u8         required_umem_size[0x20];
13067 
13068 	u8         reserved_at_a0[0x20];
13069 
13070 	u8         remaining_total_size[0x40];
13071 
13072 	u8         reserved_at_100[0x100];
13073 };
13074 
13075 struct mlx5_ifc_save_vhca_state_in_bits {
13076 	u8         opcode[0x10];
13077 	u8         uid[0x10];
13078 
13079 	u8         reserved_at_20[0x10];
13080 	u8         op_mod[0x10];
13081 
13082 	u8         incremental[0x1];
13083 	u8         set_track[0x1];
13084 	u8         reserved_at_42[0xe];
13085 	u8         vhca_id[0x10];
13086 
13087 	u8         reserved_at_60[0x20];
13088 
13089 	u8         va[0x40];
13090 
13091 	u8         mkey[0x20];
13092 
13093 	u8         size[0x20];
13094 };
13095 
13096 struct mlx5_ifc_save_vhca_state_out_bits {
13097 	u8         status[0x8];
13098 	u8         reserved_at_8[0x18];
13099 
13100 	u8         syndrome[0x20];
13101 
13102 	u8         actual_image_size[0x20];
13103 
13104 	u8         next_required_umem_size[0x20];
13105 };
13106 
13107 struct mlx5_ifc_load_vhca_state_in_bits {
13108 	u8         opcode[0x10];
13109 	u8         uid[0x10];
13110 
13111 	u8         reserved_at_20[0x10];
13112 	u8         op_mod[0x10];
13113 
13114 	u8         reserved_at_40[0x10];
13115 	u8         vhca_id[0x10];
13116 
13117 	u8         reserved_at_60[0x20];
13118 
13119 	u8         va[0x40];
13120 
13121 	u8         mkey[0x20];
13122 
13123 	u8         size[0x20];
13124 };
13125 
13126 struct mlx5_ifc_load_vhca_state_out_bits {
13127 	u8         status[0x8];
13128 	u8         reserved_at_8[0x18];
13129 
13130 	u8         syndrome[0x20];
13131 
13132 	u8         reserved_at_40[0x40];
13133 };
13134 
13135 struct mlx5_ifc_adv_rdma_cap_bits {
13136 	u8         rdma_transport_manager[0x1];
13137 	u8         rdma_transport_manager_other_eswitch[0x1];
13138 	u8         reserved_at_2[0x1e];
13139 
13140 	u8         rcx_type[0x8];
13141 	u8         reserved_at_28[0x2];
13142 	u8         ps_entry_log_max_value[0x6];
13143 	u8         reserved_at_30[0x6];
13144 	u8         qp_max_ps_num_entry[0xa];
13145 
13146 	u8         mp_max_num_queues[0x8];
13147 	u8         ps_user_context_max_log_size[0x8];
13148 	u8         message_based_qp_and_striding_wq[0x8];
13149 	u8         reserved_at_58[0x8];
13150 
13151 	u8         max_receive_send_message_size_stride[0x10];
13152 	u8         reserved_at_70[0x10];
13153 
13154 	u8         max_receive_send_message_size_byte[0x20];
13155 
13156 	u8         reserved_at_a0[0x160];
13157 
13158 	struct mlx5_ifc_flow_table_prop_layout_bits rdma_transport_rx_flow_table_properties;
13159 
13160 	struct mlx5_ifc_flow_table_prop_layout_bits rdma_transport_tx_flow_table_properties;
13161 
13162 	struct mlx5_ifc_flow_table_fields_supported_2_bits rdma_transport_rx_ft_field_support_2;
13163 
13164 	struct mlx5_ifc_flow_table_fields_supported_2_bits rdma_transport_tx_ft_field_support_2;
13165 
13166 	struct mlx5_ifc_flow_table_fields_supported_2_bits rdma_transport_rx_ft_field_bitmask_support_2;
13167 
13168 	struct mlx5_ifc_flow_table_fields_supported_2_bits rdma_transport_tx_ft_field_bitmask_support_2;
13169 
13170 	u8         reserved_at_800[0x3800];
13171 };
13172 
13173 struct mlx5_ifc_adv_virtualization_cap_bits {
13174 	u8         reserved_at_0[0x3];
13175 	u8         pg_track_log_max_num[0x5];
13176 	u8         pg_track_max_num_range[0x8];
13177 	u8         pg_track_log_min_addr_space[0x8];
13178 	u8         pg_track_log_max_addr_space[0x8];
13179 
13180 	u8         reserved_at_20[0x3];
13181 	u8         pg_track_log_min_msg_size[0x5];
13182 	u8         reserved_at_28[0x3];
13183 	u8         pg_track_log_max_msg_size[0x5];
13184 	u8         reserved_at_30[0x3];
13185 	u8         pg_track_log_min_page_size[0x5];
13186 	u8         reserved_at_38[0x3];
13187 	u8         pg_track_log_max_page_size[0x5];
13188 
13189 	u8         reserved_at_40[0x7c0];
13190 };
13191 
13192 struct mlx5_ifc_page_track_report_entry_bits {
13193 	u8         dirty_address_high[0x20];
13194 
13195 	u8         dirty_address_low[0x20];
13196 };
13197 
13198 enum {
13199 	MLX5_PAGE_TRACK_STATE_TRACKING,
13200 	MLX5_PAGE_TRACK_STATE_REPORTING,
13201 	MLX5_PAGE_TRACK_STATE_ERROR,
13202 };
13203 
13204 struct mlx5_ifc_page_track_range_bits {
13205 	u8         start_address[0x40];
13206 
13207 	u8         length[0x40];
13208 };
13209 
13210 struct mlx5_ifc_page_track_bits {
13211 	u8         modify_field_select[0x40];
13212 
13213 	u8         reserved_at_40[0x10];
13214 	u8         vhca_id[0x10];
13215 
13216 	u8         reserved_at_60[0x20];
13217 
13218 	u8         state[0x4];
13219 	u8         track_type[0x4];
13220 	u8         log_addr_space_size[0x8];
13221 	u8         reserved_at_90[0x3];
13222 	u8         log_page_size[0x5];
13223 	u8         reserved_at_98[0x3];
13224 	u8         log_msg_size[0x5];
13225 
13226 	u8         reserved_at_a0[0x8];
13227 	u8         reporting_qpn[0x18];
13228 
13229 	u8         reserved_at_c0[0x18];
13230 	u8         num_ranges[0x8];
13231 
13232 	u8         reserved_at_e0[0x20];
13233 
13234 	u8         range_start_address[0x40];
13235 
13236 	u8         length[0x40];
13237 
13238 	struct     mlx5_ifc_page_track_range_bits track_range[0];
13239 };
13240 
13241 struct mlx5_ifc_create_page_track_obj_in_bits {
13242 	struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
13243 	struct mlx5_ifc_page_track_bits obj_context;
13244 };
13245 
13246 struct mlx5_ifc_modify_page_track_obj_in_bits {
13247 	struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
13248 	struct mlx5_ifc_page_track_bits obj_context;
13249 };
13250 
13251 struct mlx5_ifc_query_page_track_obj_out_bits {
13252 	struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr;
13253 	struct mlx5_ifc_page_track_bits obj_context;
13254 };
13255 
13256 struct mlx5_ifc_msecq_reg_bits {
13257 	u8         reserved_at_0[0x20];
13258 
13259 	u8         reserved_at_20[0x12];
13260 	u8         network_option[0x2];
13261 	u8         local_ssm_code[0x4];
13262 	u8         local_enhanced_ssm_code[0x8];
13263 
13264 	u8         local_clock_identity[0x40];
13265 
13266 	u8         reserved_at_80[0x180];
13267 };
13268 
13269 enum {
13270 	MLX5_MSEES_FIELD_SELECT_ENABLE			= BIT(0),
13271 	MLX5_MSEES_FIELD_SELECT_ADMIN_STATUS		= BIT(1),
13272 	MLX5_MSEES_FIELD_SELECT_ADMIN_FREQ_MEASURE	= BIT(2),
13273 };
13274 
13275 enum mlx5_msees_admin_status {
13276 	MLX5_MSEES_ADMIN_STATUS_FREE_RUNNING		= 0x0,
13277 	MLX5_MSEES_ADMIN_STATUS_TRACK			= 0x1,
13278 };
13279 
13280 enum mlx5_msees_oper_status {
13281 	MLX5_MSEES_OPER_STATUS_FREE_RUNNING		= 0x0,
13282 	MLX5_MSEES_OPER_STATUS_SELF_TRACK		= 0x1,
13283 	MLX5_MSEES_OPER_STATUS_OTHER_TRACK		= 0x2,
13284 	MLX5_MSEES_OPER_STATUS_HOLDOVER			= 0x3,
13285 	MLX5_MSEES_OPER_STATUS_FAIL_HOLDOVER		= 0x4,
13286 	MLX5_MSEES_OPER_STATUS_FAIL_FREE_RUNNING	= 0x5,
13287 };
13288 
13289 enum mlx5_msees_failure_reason {
13290 	MLX5_MSEES_FAILURE_REASON_UNDEFINED_ERROR		= 0x0,
13291 	MLX5_MSEES_FAILURE_REASON_PORT_DOWN			= 0x1,
13292 	MLX5_MSEES_FAILURE_REASON_TOO_HIGH_FREQUENCY_DIFF	= 0x2,
13293 	MLX5_MSEES_FAILURE_REASON_NET_SYNCHRONIZER_DEVICE_ERROR	= 0x3,
13294 	MLX5_MSEES_FAILURE_REASON_LACK_OF_RESOURCES		= 0x4,
13295 };
13296 
13297 struct mlx5_ifc_msees_reg_bits {
13298 	u8         reserved_at_0[0x8];
13299 	u8         local_port[0x8];
13300 	u8         pnat[0x2];
13301 	u8         lp_msb[0x2];
13302 	u8         reserved_at_14[0xc];
13303 
13304 	u8         field_select[0x20];
13305 
13306 	u8         admin_status[0x4];
13307 	u8         oper_status[0x4];
13308 	u8         ho_acq[0x1];
13309 	u8         reserved_at_49[0xc];
13310 	u8         admin_freq_measure[0x1];
13311 	u8         oper_freq_measure[0x1];
13312 	u8         failure_reason[0x9];
13313 
13314 	u8         frequency_diff[0x20];
13315 
13316 	u8         reserved_at_80[0x180];
13317 };
13318 
13319 struct mlx5_ifc_mrtcq_reg_bits {
13320 	u8         reserved_at_0[0x40];
13321 
13322 	u8         rt_clock_identity[0x40];
13323 
13324 	u8         reserved_at_80[0x180];
13325 };
13326 
13327 struct mlx5_ifc_pcie_cong_event_obj_bits {
13328 	u8         modify_select_field[0x40];
13329 
13330 	u8         inbound_event_en[0x1];
13331 	u8         outbound_event_en[0x1];
13332 	u8         reserved_at_42[0x1e];
13333 
13334 	u8         reserved_at_60[0x1];
13335 	u8         inbound_cong_state[0x3];
13336 	u8         reserved_at_64[0x1];
13337 	u8         outbound_cong_state[0x3];
13338 	u8         reserved_at_68[0x18];
13339 
13340 	u8         inbound_cong_low_threshold[0x10];
13341 	u8         inbound_cong_high_threshold[0x10];
13342 
13343 	u8         outbound_cong_low_threshold[0x10];
13344 	u8         outbound_cong_high_threshold[0x10];
13345 
13346 	u8         reserved_at_e0[0x340];
13347 };
13348 
13349 struct mlx5_ifc_pcie_cong_event_cmd_in_bits {
13350 	struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
13351 	struct mlx5_ifc_pcie_cong_event_obj_bits cong_obj;
13352 };
13353 
13354 struct mlx5_ifc_pcie_cong_event_cmd_out_bits {
13355 	struct mlx5_ifc_general_obj_out_cmd_hdr_bits hdr;
13356 	struct mlx5_ifc_pcie_cong_event_obj_bits cong_obj;
13357 };
13358 
13359 enum mlx5e_pcie_cong_event_mod_field {
13360 	MLX5_PCIE_CONG_EVENT_MOD_EVENT_EN = BIT(0),
13361 	MLX5_PCIE_CONG_EVENT_MOD_THRESH   = BIT(2),
13362 };
13363 
13364 #endif /* MLX5_IFC_H */
13365