1 /******************************************************************************
2 SPDX-License-Identifier: BSD-3-Clause
3
4 Copyright (c) 2001-2020, Intel Corporation
5 All rights reserved.
6
7 Redistribution and use in source and binary forms, with or without
8 modification, are permitted provided that the following conditions are met:
9
10 1. Redistributions of source code must retain the above copyright notice,
11 this list of conditions and the following disclaimer.
12
13 2. Redistributions in binary form must reproduce the above copyright
14 notice, this list of conditions and the following disclaimer in the
15 documentation and/or other materials provided with the distribution.
16
17 3. Neither the name of the Intel Corporation nor the names of its
18 contributors may be used to endorse or promote products derived from
19 this software without specific prior written permission.
20
21 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
25 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 POSSIBILITY OF SUCH DAMAGE.
32
33 ******************************************************************************/
34
35 #include "e1000_api.h"
36
37 static s32 e1000_wait_autoneg(struct e1000_hw *hw);
38 static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset,
39 u16 *data, bool read, bool page_set);
40 static u32 e1000_get_phy_addr_for_hv_page(u32 page);
41 static s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset,
42 u16 *data, bool read);
43
44 /* Cable length tables */
45 static const u16 e1000_m88_cable_length_table[] = {
46 0, 50, 80, 110, 140, 140, E1000_CABLE_LENGTH_UNDEFINED };
47 #define M88E1000_CABLE_LENGTH_TABLE_SIZE \
48 (sizeof(e1000_m88_cable_length_table) / \
49 sizeof(e1000_m88_cable_length_table[0]))
50
51 static const u16 e1000_igp_2_cable_length_table[] = {
52 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21, 0, 0, 0, 3,
53 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41, 6, 10, 14, 18, 22,
54 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61, 21, 26, 31, 35, 40,
55 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82, 40, 45, 51, 56, 61,
56 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104, 60, 66, 72, 77, 82,
57 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121, 83, 89, 95,
58 100, 105, 109, 113, 116, 119, 122, 124, 104, 109, 114, 118, 121,
59 124};
60 #define IGP02E1000_CABLE_LENGTH_TABLE_SIZE \
61 (sizeof(e1000_igp_2_cable_length_table) / \
62 sizeof(e1000_igp_2_cable_length_table[0]))
63
64 /**
65 * e1000_init_phy_ops_generic - Initialize PHY function pointers
66 * @hw: pointer to the HW structure
67 *
68 * Setups up the function pointers to no-op functions
69 **/
e1000_init_phy_ops_generic(struct e1000_hw * hw)70 void e1000_init_phy_ops_generic(struct e1000_hw *hw)
71 {
72 struct e1000_phy_info *phy = &hw->phy;
73 DEBUGFUNC("e1000_init_phy_ops_generic");
74
75 /* Initialize function pointers */
76 phy->ops.init_params = e1000_null_ops_generic;
77 phy->ops.acquire = e1000_null_ops_generic;
78 phy->ops.check_polarity = e1000_null_ops_generic;
79 phy->ops.check_reset_block = e1000_null_ops_generic;
80 phy->ops.commit = e1000_null_ops_generic;
81 phy->ops.force_speed_duplex = e1000_null_ops_generic;
82 phy->ops.get_cfg_done = e1000_null_ops_generic;
83 phy->ops.get_cable_length = e1000_null_ops_generic;
84 phy->ops.get_info = e1000_null_ops_generic;
85 phy->ops.set_page = e1000_null_set_page;
86 phy->ops.read_reg = e1000_null_read_reg;
87 phy->ops.read_reg_locked = e1000_null_read_reg;
88 phy->ops.read_reg_page = e1000_null_read_reg;
89 phy->ops.release = e1000_null_phy_generic;
90 phy->ops.reset = e1000_null_ops_generic;
91 phy->ops.set_d0_lplu_state = e1000_null_lplu_state;
92 phy->ops.set_d3_lplu_state = e1000_null_lplu_state;
93 phy->ops.write_reg = e1000_null_write_reg;
94 phy->ops.write_reg_locked = e1000_null_write_reg;
95 phy->ops.write_reg_page = e1000_null_write_reg;
96 phy->ops.power_up = e1000_null_phy_generic;
97 phy->ops.power_down = e1000_null_phy_generic;
98 phy->ops.read_i2c_byte = e1000_read_i2c_byte_null;
99 phy->ops.write_i2c_byte = e1000_write_i2c_byte_null;
100 phy->ops.cfg_on_link_up = e1000_null_ops_generic;
101 }
102
103 /**
104 * e1000_null_set_page - No-op function, return 0
105 * @hw: pointer to the HW structure
106 * @data: dummy variable
107 **/
e1000_null_set_page(struct e1000_hw E1000_UNUSEDARG * hw,u16 E1000_UNUSEDARG data)108 s32 e1000_null_set_page(struct e1000_hw E1000_UNUSEDARG *hw,
109 u16 E1000_UNUSEDARG data)
110 {
111 DEBUGFUNC("e1000_null_set_page");
112 return E1000_SUCCESS;
113 }
114
115 /**
116 * e1000_null_read_reg - No-op function, return 0
117 * @hw: pointer to the HW structure
118 * @offset: dummy variable
119 * @data: dummy variable
120 **/
e1000_null_read_reg(struct e1000_hw E1000_UNUSEDARG * hw,u32 E1000_UNUSEDARG offset,u16 E1000_UNUSEDARG * data)121 s32 e1000_null_read_reg(struct e1000_hw E1000_UNUSEDARG *hw,
122 u32 E1000_UNUSEDARG offset, u16 E1000_UNUSEDARG *data)
123 {
124 DEBUGFUNC("e1000_null_read_reg");
125 return E1000_SUCCESS;
126 }
127
128 /**
129 * e1000_null_phy_generic - No-op function, return void
130 * @hw: pointer to the HW structure
131 **/
e1000_null_phy_generic(struct e1000_hw E1000_UNUSEDARG * hw)132 void e1000_null_phy_generic(struct e1000_hw E1000_UNUSEDARG *hw)
133 {
134 DEBUGFUNC("e1000_null_phy_generic");
135 return;
136 }
137
138 /**
139 * e1000_null_lplu_state - No-op function, return 0
140 * @hw: pointer to the HW structure
141 * @active: dummy variable
142 **/
e1000_null_lplu_state(struct e1000_hw E1000_UNUSEDARG * hw,bool E1000_UNUSEDARG active)143 s32 e1000_null_lplu_state(struct e1000_hw E1000_UNUSEDARG *hw,
144 bool E1000_UNUSEDARG active)
145 {
146 DEBUGFUNC("e1000_null_lplu_state");
147 return E1000_SUCCESS;
148 }
149
150 /**
151 * e1000_null_write_reg - No-op function, return 0
152 * @hw: pointer to the HW structure
153 * @offset: dummy variable
154 * @data: dummy variable
155 **/
e1000_null_write_reg(struct e1000_hw E1000_UNUSEDARG * hw,u32 E1000_UNUSEDARG offset,u16 E1000_UNUSEDARG data)156 s32 e1000_null_write_reg(struct e1000_hw E1000_UNUSEDARG *hw,
157 u32 E1000_UNUSEDARG offset, u16 E1000_UNUSEDARG data)
158 {
159 DEBUGFUNC("e1000_null_write_reg");
160 return E1000_SUCCESS;
161 }
162
163 /**
164 * e1000_read_i2c_byte_null - No-op function, return 0
165 * @hw: pointer to hardware structure
166 * @byte_offset: byte offset to write
167 * @dev_addr: device address
168 * @data: data value read
169 *
170 **/
e1000_read_i2c_byte_null(struct e1000_hw E1000_UNUSEDARG * hw,u8 E1000_UNUSEDARG byte_offset,u8 E1000_UNUSEDARG dev_addr,u8 E1000_UNUSEDARG * data)171 s32 e1000_read_i2c_byte_null(struct e1000_hw E1000_UNUSEDARG *hw,
172 u8 E1000_UNUSEDARG byte_offset,
173 u8 E1000_UNUSEDARG dev_addr,
174 u8 E1000_UNUSEDARG *data)
175 {
176 DEBUGFUNC("e1000_read_i2c_byte_null");
177 return E1000_SUCCESS;
178 }
179
180 /**
181 * e1000_write_i2c_byte_null - No-op function, return 0
182 * @hw: pointer to hardware structure
183 * @byte_offset: byte offset to write
184 * @dev_addr: device address
185 * @data: data value to write
186 *
187 **/
e1000_write_i2c_byte_null(struct e1000_hw E1000_UNUSEDARG * hw,u8 E1000_UNUSEDARG byte_offset,u8 E1000_UNUSEDARG dev_addr,u8 E1000_UNUSEDARG data)188 s32 e1000_write_i2c_byte_null(struct e1000_hw E1000_UNUSEDARG *hw,
189 u8 E1000_UNUSEDARG byte_offset,
190 u8 E1000_UNUSEDARG dev_addr,
191 u8 E1000_UNUSEDARG data)
192 {
193 DEBUGFUNC("e1000_write_i2c_byte_null");
194 return E1000_SUCCESS;
195 }
196
197 /**
198 * e1000_check_reset_block_generic - Check if PHY reset is blocked
199 * @hw: pointer to the HW structure
200 *
201 * Read the PHY management control register and check whether a PHY reset
202 * is blocked. If a reset is not blocked return E1000_SUCCESS, otherwise
203 * return E1000_BLK_PHY_RESET (12).
204 **/
e1000_check_reset_block_generic(struct e1000_hw * hw)205 s32 e1000_check_reset_block_generic(struct e1000_hw *hw)
206 {
207 u32 manc;
208
209 DEBUGFUNC("e1000_check_reset_block");
210
211 manc = E1000_READ_REG(hw, E1000_MANC);
212
213 return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ?
214 E1000_BLK_PHY_RESET : E1000_SUCCESS;
215 }
216
217 /**
218 * e1000_get_phy_id - Retrieve the PHY ID and revision
219 * @hw: pointer to the HW structure
220 *
221 * Reads the PHY registers and stores the PHY ID and possibly the PHY
222 * revision in the hardware structure.
223 **/
e1000_get_phy_id(struct e1000_hw * hw)224 s32 e1000_get_phy_id(struct e1000_hw *hw)
225 {
226 struct e1000_phy_info *phy = &hw->phy;
227 s32 ret_val = E1000_SUCCESS;
228 u16 phy_id;
229 u16 retry_count = 0;
230
231 DEBUGFUNC("e1000_get_phy_id");
232
233 if (!phy->ops.read_reg)
234 return E1000_SUCCESS;
235
236 while (retry_count < 2) {
237 ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id);
238 if (ret_val)
239 return ret_val;
240
241 phy->id = (u32)phy_id << 16;
242 usec_delay(20);
243 ret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id);
244 if (ret_val)
245 return ret_val;
246
247 phy->id |= (u32)(phy_id & PHY_REVISION_MASK);
248 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);
249
250 if (phy->id != 0 && phy->id != PHY_REVISION_MASK)
251 return E1000_SUCCESS;
252
253 retry_count++;
254 }
255
256 return E1000_SUCCESS;
257 }
258
259 /**
260 * e1000_phy_reset_dsp_generic - Reset PHY DSP
261 * @hw: pointer to the HW structure
262 *
263 * Reset the digital signal processor.
264 **/
e1000_phy_reset_dsp_generic(struct e1000_hw * hw)265 s32 e1000_phy_reset_dsp_generic(struct e1000_hw *hw)
266 {
267 s32 ret_val;
268
269 DEBUGFUNC("e1000_phy_reset_dsp_generic");
270
271 if (!hw->phy.ops.write_reg)
272 return E1000_SUCCESS;
273
274 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xC1);
275 if (ret_val)
276 return ret_val;
277
278 return hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0);
279 }
280
281 void
e1000_disable_phy_retry_mechanism(struct e1000_hw * hw,u32 * phy_retries_original)282 e1000_disable_phy_retry_mechanism(struct e1000_hw *hw,
283 u32 *phy_retries_original)
284 {
285
286 DEBUGFUNC("e1000_disable_phy_retry_mechanism");
287
288 *phy_retries_original = hw->phy.current_retry_counter;
289 hw->phy.current_retry_counter = 0;
290 }
291
292 void
e1000_enable_phy_retry_mechanism(struct e1000_hw * hw,u32 phy_retries_original)293 e1000_enable_phy_retry_mechanism(struct e1000_hw *hw,
294 u32 phy_retries_original)
295 {
296
297 DEBUGFUNC("e1000_enable_phy_retry_mechanism");
298
299 hw->phy.current_retry_counter = phy_retries_original;
300 }
301
302 /**
303 * e1000_read_phy_reg_mdic - Read MDI control register
304 * @hw: pointer to the HW structure
305 * @offset: register offset to be read
306 * @data: pointer to the read data
307 *
308 * Reads the MDI control register in the PHY at offset and stores the
309 * information read to data.
310 **/
e1000_read_phy_reg_mdic(struct e1000_hw * hw,u32 offset,u16 * data)311 s32 e1000_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data)
312 {
313 struct e1000_phy_info *phy = &hw->phy;
314 u32 i, mdic = 0, retry_counter;
315 bool success;
316
317 DEBUGFUNC("e1000_read_phy_reg_mdic");
318
319 if (offset > MAX_PHY_REG_ADDRESS) {
320 DEBUGOUT1("PHY Address %d is out of range\n", offset);
321 return -E1000_ERR_PARAM;
322 }
323
324 /* Set up and execute the transaction once, plus any configured
325 * retries. Newer PCH generations can transiently fail MDIC
326 * transactions while the MAC and PHY clocks synchronize.
327 */
328 for (retry_counter = 0;
329 retry_counter <= phy->current_retry_counter; retry_counter++) {
330 success = true;
331 mdic = ((offset << E1000_MDIC_REG_SHIFT) |
332 (phy->addr << E1000_MDIC_PHY_SHIFT) |
333 E1000_MDIC_OP_READ);
334 E1000_WRITE_REG(hw, E1000_MDIC, mdic);
335
336 /* Poll the ready bit to see if the MDI read completed.
337 * Increasing the timeout avoided failures seen in testing.
338 */
339 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
340 usec_delay_irq(50);
341 mdic = E1000_READ_REG(hw, E1000_MDIC);
342 if (mdic & E1000_MDIC_READY)
343 break;
344 }
345 if (!(mdic & E1000_MDIC_READY)) {
346 DEBUGOUT("MDI Read did not complete\n");
347 success = false;
348 }
349 if (mdic & E1000_MDIC_ERROR) {
350 DEBUGOUT("MDI Error\n");
351 success = false;
352 }
353 if (((mdic & E1000_MDIC_REG_MASK) >>
354 E1000_MDIC_REG_SHIFT) != offset) {
355 DEBUGOUT2("MDI Read offset error - requested %d, "
356 "returned %d\n", offset,
357 (mdic & E1000_MDIC_REG_MASK) >>
358 E1000_MDIC_REG_SHIFT);
359 success = false;
360 }
361
362 /* Avoid duplicate data in the next MDIC transaction. */
363 if (hw->mac.type == e1000_pch2lan)
364 usec_delay_irq(100);
365
366 if (success) {
367 *data = (u16)mdic;
368 return E1000_SUCCESS;
369 }
370 if (retry_counter != phy->current_retry_counter) {
371 DEBUGOUT("Retrying PHY transaction\n");
372 msec_delay_irq(10);
373 }
374 }
375
376 return -E1000_ERR_PHY;
377 }
378
379 /**
380 * e1000_write_phy_reg_mdic - Write MDI control register
381 * @hw: pointer to the HW structure
382 * @offset: register offset to write to
383 * @data: data to write to register at offset
384 *
385 * Writes data to MDI control register in the PHY at offset.
386 **/
e1000_write_phy_reg_mdic(struct e1000_hw * hw,u32 offset,u16 data)387 s32 e1000_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data)
388 {
389 struct e1000_phy_info *phy = &hw->phy;
390 u32 i, mdic = 0, retry_counter;
391 bool success;
392
393 DEBUGFUNC("e1000_write_phy_reg_mdic");
394
395 if (offset > MAX_PHY_REG_ADDRESS) {
396 DEBUGOUT1("PHY Address %d is out of range\n", offset);
397 return -E1000_ERR_PARAM;
398 }
399
400 for (retry_counter = 0;
401 retry_counter <= phy->current_retry_counter; retry_counter++) {
402 success = true;
403 mdic = ((u32)data |
404 (offset << E1000_MDIC_REG_SHIFT) |
405 (phy->addr << E1000_MDIC_PHY_SHIFT) |
406 E1000_MDIC_OP_WRITE);
407 E1000_WRITE_REG(hw, E1000_MDIC, mdic);
408
409 /* Poll the ready bit to see if the MDI write completed.
410 * Increasing the timeout avoided failures seen in testing.
411 */
412 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
413 usec_delay_irq(50);
414 mdic = E1000_READ_REG(hw, E1000_MDIC);
415 if (mdic & E1000_MDIC_READY)
416 break;
417 }
418 if (!(mdic & E1000_MDIC_READY)) {
419 DEBUGOUT("MDI Write did not complete\n");
420 success = false;
421 }
422 if (mdic & E1000_MDIC_ERROR) {
423 DEBUGOUT("MDI Error\n");
424 success = false;
425 }
426 if (((mdic & E1000_MDIC_REG_MASK) >>
427 E1000_MDIC_REG_SHIFT) != offset) {
428 DEBUGOUT2("MDI Write offset error - requested %d, "
429 "returned %d\n", offset,
430 (mdic & E1000_MDIC_REG_MASK) >>
431 E1000_MDIC_REG_SHIFT);
432 success = false;
433 }
434
435 /* Avoid duplicate data in the next MDIC transaction. */
436 if (hw->mac.type == e1000_pch2lan)
437 usec_delay_irq(100);
438
439 if (success)
440 return E1000_SUCCESS;
441 if (retry_counter != phy->current_retry_counter) {
442 DEBUGOUT("Retrying PHY transaction\n");
443 msec_delay_irq(10);
444 }
445 }
446
447 return -E1000_ERR_PHY;
448 }
449
450 /**
451 * e1000_read_phy_reg_i2c - Read PHY register using i2c
452 * @hw: pointer to the HW structure
453 * @offset: register offset to be read
454 * @data: pointer to the read data
455 *
456 * Reads the PHY register at offset using the i2c interface and stores the
457 * retrieved information in data.
458 **/
e1000_read_phy_reg_i2c(struct e1000_hw * hw,u32 offset,u16 * data)459 s32 e1000_read_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 *data)
460 {
461 struct e1000_phy_info *phy = &hw->phy;
462 u32 i, i2ccmd = 0;
463
464 DEBUGFUNC("e1000_read_phy_reg_i2c");
465
466 /* Set up Op-code, Phy Address, and register address in the I2CCMD
467 * register. The MAC will take care of interfacing with the
468 * PHY to retrieve the desired data.
469 */
470 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |
471 (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) |
472 (E1000_I2CCMD_OPCODE_READ));
473
474 E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd);
475
476 /* Poll the ready bit to see if the I2C read completed */
477 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {
478 usec_delay(50);
479 i2ccmd = E1000_READ_REG(hw, E1000_I2CCMD);
480 if (i2ccmd & E1000_I2CCMD_READY)
481 break;
482 }
483 if (!(i2ccmd & E1000_I2CCMD_READY)) {
484 DEBUGOUT("I2CCMD Read did not complete\n");
485 return -E1000_ERR_PHY;
486 }
487 if (i2ccmd & E1000_I2CCMD_ERROR) {
488 DEBUGOUT("I2CCMD Error bit set\n");
489 return -E1000_ERR_PHY;
490 }
491
492 /* Need to byte-swap the 16-bit value. */
493 *data = ((i2ccmd >> 8) & 0x00FF) | ((i2ccmd << 8) & 0xFF00);
494
495 return E1000_SUCCESS;
496 }
497
498 /**
499 * e1000_write_phy_reg_i2c - Write PHY register using i2c
500 * @hw: pointer to the HW structure
501 * @offset: register offset to write to
502 * @data: data to write at register offset
503 *
504 * Writes the data to PHY register at the offset using the i2c interface.
505 **/
e1000_write_phy_reg_i2c(struct e1000_hw * hw,u32 offset,u16 data)506 s32 e1000_write_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 data)
507 {
508 struct e1000_phy_info *phy = &hw->phy;
509 u32 i, i2ccmd = 0;
510 u16 phy_data_swapped;
511
512 DEBUGFUNC("e1000_write_phy_reg_i2c");
513
514 /* Prevent overwriting SFP I2C EEPROM which is at A0 address.*/
515 if ((hw->phy.addr == 0) || (hw->phy.addr > 7)) {
516 DEBUGOUT1("PHY I2C Address %d is out of range.\n",
517 hw->phy.addr);
518 return -E1000_ERR_CONFIG;
519 }
520
521 /* Swap the data bytes for the I2C interface */
522 phy_data_swapped = ((data >> 8) & 0x00FF) | ((data << 8) & 0xFF00);
523
524 /* Set up Op-code, Phy Address, and register address in the I2CCMD
525 * register. The MAC will take care of interfacing with the
526 * PHY to retrieve the desired data.
527 */
528 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |
529 (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) |
530 E1000_I2CCMD_OPCODE_WRITE |
531 phy_data_swapped);
532
533 E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd);
534
535 /* Poll the ready bit to see if the I2C read completed */
536 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {
537 usec_delay(50);
538 i2ccmd = E1000_READ_REG(hw, E1000_I2CCMD);
539 if (i2ccmd & E1000_I2CCMD_READY)
540 break;
541 }
542 if (!(i2ccmd & E1000_I2CCMD_READY)) {
543 DEBUGOUT("I2CCMD Write did not complete\n");
544 return -E1000_ERR_PHY;
545 }
546 if (i2ccmd & E1000_I2CCMD_ERROR) {
547 DEBUGOUT("I2CCMD Error bit set\n");
548 return -E1000_ERR_PHY;
549 }
550
551 return E1000_SUCCESS;
552 }
553
554 /**
555 * e1000_read_sfp_data_byte - Reads SFP module data.
556 * @hw: pointer to the HW structure
557 * @offset: byte location offset to be read
558 * @data: read data buffer pointer
559 *
560 * Reads one byte from SFP module data stored
561 * in SFP resided EEPROM memory or SFP diagnostic area.
562 * Function should be called with
563 * E1000_I2CCMD_SFP_DATA_ADDR(<byte offset>) for SFP module database access
564 * E1000_I2CCMD_SFP_DIAG_ADDR(<byte offset>) for SFP diagnostics parameters
565 * access
566 **/
e1000_read_sfp_data_byte(struct e1000_hw * hw,u16 offset,u8 * data)567 s32 e1000_read_sfp_data_byte(struct e1000_hw *hw, u16 offset, u8 *data)
568 {
569 u32 i = 0;
570 u32 i2ccmd = 0;
571 u32 data_local = 0;
572
573 DEBUGFUNC("e1000_read_sfp_data_byte");
574
575 if (offset > E1000_I2CCMD_SFP_DIAG_ADDR(255)) {
576 DEBUGOUT("I2CCMD command address exceeds upper limit\n");
577 return -E1000_ERR_PHY;
578 }
579
580 /* Set up Op-code, EEPROM Address,in the I2CCMD
581 * register. The MAC will take care of interfacing with the
582 * EEPROM to retrieve the desired data.
583 */
584 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |
585 E1000_I2CCMD_OPCODE_READ);
586
587 E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd);
588
589 /* Poll the ready bit to see if the I2C read completed */
590 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {
591 usec_delay(50);
592 data_local = E1000_READ_REG(hw, E1000_I2CCMD);
593 if (data_local & E1000_I2CCMD_READY)
594 break;
595 }
596 if (!(data_local & E1000_I2CCMD_READY)) {
597 DEBUGOUT("I2CCMD Read did not complete\n");
598 return -E1000_ERR_PHY;
599 }
600 if (data_local & E1000_I2CCMD_ERROR) {
601 DEBUGOUT("I2CCMD Error bit set\n");
602 return -E1000_ERR_PHY;
603 }
604 *data = (u8) data_local & 0xFF;
605
606 return E1000_SUCCESS;
607 }
608
609 /**
610 * e1000_write_sfp_data_byte - Writes SFP module data.
611 * @hw: pointer to the HW structure
612 * @offset: byte location offset to write to
613 * @data: data to write
614 *
615 * Writes one byte to SFP module data stored
616 * in SFP resided EEPROM memory or SFP diagnostic area.
617 * Function should be called with
618 * E1000_I2CCMD_SFP_DATA_ADDR(<byte offset>) for SFP module database access
619 * E1000_I2CCMD_SFP_DIAG_ADDR(<byte offset>) for SFP diagnostics parameters
620 * access
621 **/
e1000_write_sfp_data_byte(struct e1000_hw * hw,u16 offset,u8 data)622 s32 e1000_write_sfp_data_byte(struct e1000_hw *hw, u16 offset, u8 data)
623 {
624 u32 i = 0;
625 u32 i2ccmd = 0;
626 u32 data_local = 0;
627
628 DEBUGFUNC("e1000_write_sfp_data_byte");
629
630 if (offset > E1000_I2CCMD_SFP_DIAG_ADDR(255)) {
631 DEBUGOUT("I2CCMD command address exceeds upper limit\n");
632 return -E1000_ERR_PHY;
633 }
634 /* The programming interface is 16 bits wide
635 * so we need to read the whole word first
636 * then update appropriate byte lane and write
637 * the updated word back.
638 */
639 /* Set up Op-code, EEPROM Address,in the I2CCMD
640 * register. The MAC will take care of interfacing
641 * with an EEPROM to write the data given.
642 */
643 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |
644 E1000_I2CCMD_OPCODE_READ);
645 /* Set a command to read single word */
646 E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd);
647 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {
648 usec_delay(50);
649 /* Poll the ready bit to see if lastly
650 * launched I2C operation completed
651 */
652 i2ccmd = E1000_READ_REG(hw, E1000_I2CCMD);
653 if (i2ccmd & E1000_I2CCMD_READY) {
654 /* Check if this is READ or WRITE phase */
655 if ((i2ccmd & E1000_I2CCMD_OPCODE_READ) ==
656 E1000_I2CCMD_OPCODE_READ) {
657 /* Write the selected byte
658 * lane and update whole word
659 */
660 data_local = i2ccmd & 0xFF00;
661 data_local |= (u32)data;
662 i2ccmd = ((offset <<
663 E1000_I2CCMD_REG_ADDR_SHIFT) |
664 E1000_I2CCMD_OPCODE_WRITE | data_local);
665 E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd);
666 } else {
667 break;
668 }
669 }
670 }
671 if (!(i2ccmd & E1000_I2CCMD_READY)) {
672 DEBUGOUT("I2CCMD Write did not complete\n");
673 return -E1000_ERR_PHY;
674 }
675 if (i2ccmd & E1000_I2CCMD_ERROR) {
676 DEBUGOUT("I2CCMD Error bit set\n");
677 return -E1000_ERR_PHY;
678 }
679 return E1000_SUCCESS;
680 }
681
682 /**
683 * e1000_read_phy_reg_m88 - Read m88 PHY register
684 * @hw: pointer to the HW structure
685 * @offset: register offset to be read
686 * @data: pointer to the read data
687 *
688 * Acquires semaphore, if necessary, then reads the PHY register at offset
689 * and storing the retrieved information in data. Release any acquired
690 * semaphores before exiting.
691 **/
e1000_read_phy_reg_m88(struct e1000_hw * hw,u32 offset,u16 * data)692 s32 e1000_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data)
693 {
694 s32 ret_val;
695
696 DEBUGFUNC("e1000_read_phy_reg_m88");
697
698 if (!hw->phy.ops.acquire)
699 return E1000_SUCCESS;
700
701 ret_val = hw->phy.ops.acquire(hw);
702 if (ret_val)
703 return ret_val;
704
705 ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
706 data);
707
708 hw->phy.ops.release(hw);
709
710 return ret_val;
711 }
712
713 /**
714 * e1000_write_phy_reg_m88 - Write m88 PHY register
715 * @hw: pointer to the HW structure
716 * @offset: register offset to write to
717 * @data: data to write at register offset
718 *
719 * Acquires semaphore, if necessary, then writes the data to PHY register
720 * at the offset. Release any acquired semaphores before exiting.
721 **/
e1000_write_phy_reg_m88(struct e1000_hw * hw,u32 offset,u16 data)722 s32 e1000_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data)
723 {
724 s32 ret_val;
725
726 DEBUGFUNC("e1000_write_phy_reg_m88");
727
728 if (!hw->phy.ops.acquire)
729 return E1000_SUCCESS;
730
731 ret_val = hw->phy.ops.acquire(hw);
732 if (ret_val)
733 return ret_val;
734
735 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
736 data);
737
738 hw->phy.ops.release(hw);
739
740 return ret_val;
741 }
742
743 /**
744 * e1000_set_page_igp - Set page as on IGP-like PHY(s)
745 * @hw: pointer to the HW structure
746 * @page: page to set (shifted left when necessary)
747 *
748 * Sets PHY page required for PHY register access. Assumes semaphore is
749 * already acquired. Note, this function sets phy.addr to 1 so the caller
750 * must set it appropriately (if necessary) after this function returns.
751 **/
e1000_set_page_igp(struct e1000_hw * hw,u16 page)752 s32 e1000_set_page_igp(struct e1000_hw *hw, u16 page)
753 {
754 DEBUGFUNC("e1000_set_page_igp");
755
756 DEBUGOUT1("Setting page 0x%x\n", page);
757
758 hw->phy.addr = 1;
759
760 return e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, page);
761 }
762
763 /**
764 * __e1000_read_phy_reg_igp - Read igp PHY register
765 * @hw: pointer to the HW structure
766 * @offset: register offset to be read
767 * @data: pointer to the read data
768 * @locked: semaphore has already been acquired or not
769 *
770 * Acquires semaphore, if necessary, then reads the PHY register at offset
771 * and stores the retrieved information in data. Release any acquired
772 * semaphores before exiting.
773 **/
__e1000_read_phy_reg_igp(struct e1000_hw * hw,u32 offset,u16 * data,bool locked)774 static s32 __e1000_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data,
775 bool locked)
776 {
777 s32 ret_val = E1000_SUCCESS;
778
779 DEBUGFUNC("__e1000_read_phy_reg_igp");
780
781 if (!locked) {
782 if (!hw->phy.ops.acquire)
783 return E1000_SUCCESS;
784
785 ret_val = hw->phy.ops.acquire(hw);
786 if (ret_val)
787 return ret_val;
788 }
789
790 if (offset > MAX_PHY_MULTI_PAGE_REG)
791 ret_val = e1000_write_phy_reg_mdic(hw,
792 IGP01E1000_PHY_PAGE_SELECT,
793 (u16)offset);
794 if (!ret_val)
795 ret_val = e1000_read_phy_reg_mdic(hw,
796 MAX_PHY_REG_ADDRESS & offset,
797 data);
798 if (!locked)
799 hw->phy.ops.release(hw);
800
801 return ret_val;
802 }
803
804 /**
805 * e1000_read_phy_reg_igp - Read igp PHY register
806 * @hw: pointer to the HW structure
807 * @offset: register offset to be read
808 * @data: pointer to the read data
809 *
810 * Acquires semaphore then reads the PHY register at offset and stores the
811 * retrieved information in data.
812 * Release the acquired semaphore before exiting.
813 **/
e1000_read_phy_reg_igp(struct e1000_hw * hw,u32 offset,u16 * data)814 s32 e1000_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data)
815 {
816 return __e1000_read_phy_reg_igp(hw, offset, data, false);
817 }
818
819 /**
820 * e1000_read_phy_reg_igp_locked - Read igp PHY register
821 * @hw: pointer to the HW structure
822 * @offset: register offset to be read
823 * @data: pointer to the read data
824 *
825 * Reads the PHY register at offset and stores the retrieved information
826 * in data. Assumes semaphore already acquired.
827 **/
e1000_read_phy_reg_igp_locked(struct e1000_hw * hw,u32 offset,u16 * data)828 s32 e1000_read_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 *data)
829 {
830 return __e1000_read_phy_reg_igp(hw, offset, data, true);
831 }
832
833 /**
834 * e1000_write_phy_reg_igp - Write igp PHY register
835 * @hw: pointer to the HW structure
836 * @offset: register offset to write to
837 * @data: data to write at register offset
838 * @locked: semaphore has already been acquired or not
839 *
840 * Acquires semaphore, if necessary, then writes the data to PHY register
841 * at the offset. Release any acquired semaphores before exiting.
842 **/
__e1000_write_phy_reg_igp(struct e1000_hw * hw,u32 offset,u16 data,bool locked)843 static s32 __e1000_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data,
844 bool locked)
845 {
846 s32 ret_val = E1000_SUCCESS;
847
848 DEBUGFUNC("e1000_write_phy_reg_igp");
849
850 if (!locked) {
851 if (!hw->phy.ops.acquire)
852 return E1000_SUCCESS;
853
854 ret_val = hw->phy.ops.acquire(hw);
855 if (ret_val)
856 return ret_val;
857 }
858
859 if (offset > MAX_PHY_MULTI_PAGE_REG)
860 ret_val = e1000_write_phy_reg_mdic(hw,
861 IGP01E1000_PHY_PAGE_SELECT,
862 (u16)offset);
863 if (!ret_val)
864 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS &
865 offset,
866 data);
867 if (!locked)
868 hw->phy.ops.release(hw);
869
870 return ret_val;
871 }
872
873 /**
874 * e1000_write_phy_reg_igp - Write igp PHY register
875 * @hw: pointer to the HW structure
876 * @offset: register offset to write to
877 * @data: data to write at register offset
878 *
879 * Acquires semaphore then writes the data to PHY register
880 * at the offset. Release any acquired semaphores before exiting.
881 **/
e1000_write_phy_reg_igp(struct e1000_hw * hw,u32 offset,u16 data)882 s32 e1000_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data)
883 {
884 return __e1000_write_phy_reg_igp(hw, offset, data, false);
885 }
886
887 /**
888 * e1000_write_phy_reg_igp_locked - Write igp PHY register
889 * @hw: pointer to the HW structure
890 * @offset: register offset to write to
891 * @data: data to write at register offset
892 *
893 * Writes the data to PHY register at the offset.
894 * Assumes semaphore already acquired.
895 **/
e1000_write_phy_reg_igp_locked(struct e1000_hw * hw,u32 offset,u16 data)896 s32 e1000_write_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 data)
897 {
898 return __e1000_write_phy_reg_igp(hw, offset, data, true);
899 }
900
901 /**
902 * __e1000_read_kmrn_reg - Read kumeran register
903 * @hw: pointer to the HW structure
904 * @offset: register offset to be read
905 * @data: pointer to the read data
906 * @locked: semaphore has already been acquired or not
907 *
908 * Acquires semaphore, if necessary. Then reads the PHY register at offset
909 * using the kumeran interface. The information retrieved is stored in data.
910 * Release any acquired semaphores before exiting.
911 **/
__e1000_read_kmrn_reg(struct e1000_hw * hw,u32 offset,u16 * data,bool locked)912 static s32 __e1000_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data,
913 bool locked)
914 {
915 u32 kmrnctrlsta;
916
917 DEBUGFUNC("__e1000_read_kmrn_reg");
918
919 if (!locked) {
920 s32 ret_val = E1000_SUCCESS;
921
922 if (!hw->phy.ops.acquire)
923 return E1000_SUCCESS;
924
925 ret_val = hw->phy.ops.acquire(hw);
926 if (ret_val)
927 return ret_val;
928 }
929
930 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
931 E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN;
932 E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta);
933 E1000_WRITE_FLUSH(hw);
934
935 usec_delay(2);
936
937 kmrnctrlsta = E1000_READ_REG(hw, E1000_KMRNCTRLSTA);
938 *data = (u16)kmrnctrlsta;
939
940 if (!locked)
941 hw->phy.ops.release(hw);
942
943 return E1000_SUCCESS;
944 }
945
946 /**
947 * e1000_read_kmrn_reg_generic - Read kumeran register
948 * @hw: pointer to the HW structure
949 * @offset: register offset to be read
950 * @data: pointer to the read data
951 *
952 * Acquires semaphore then reads the PHY register at offset using the
953 * kumeran interface. The information retrieved is stored in data.
954 * Release the acquired semaphore before exiting.
955 **/
e1000_read_kmrn_reg_generic(struct e1000_hw * hw,u32 offset,u16 * data)956 s32 e1000_read_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 *data)
957 {
958 return __e1000_read_kmrn_reg(hw, offset, data, false);
959 }
960
961 /**
962 * e1000_read_kmrn_reg_locked - Read kumeran register
963 * @hw: pointer to the HW structure
964 * @offset: register offset to be read
965 * @data: pointer to the read data
966 *
967 * Reads the PHY register at offset using the kumeran interface. The
968 * information retrieved is stored in data.
969 * Assumes semaphore already acquired.
970 **/
e1000_read_kmrn_reg_locked(struct e1000_hw * hw,u32 offset,u16 * data)971 s32 e1000_read_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 *data)
972 {
973 return __e1000_read_kmrn_reg(hw, offset, data, true);
974 }
975
976 /**
977 * __e1000_write_kmrn_reg - Write kumeran register
978 * @hw: pointer to the HW structure
979 * @offset: register offset to write to
980 * @data: data to write at register offset
981 * @locked: semaphore has already been acquired or not
982 *
983 * Acquires semaphore, if necessary. Then write the data to PHY register
984 * at the offset using the kumeran interface. Release any acquired semaphores
985 * before exiting.
986 **/
__e1000_write_kmrn_reg(struct e1000_hw * hw,u32 offset,u16 data,bool locked)987 static s32 __e1000_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data,
988 bool locked)
989 {
990 u32 kmrnctrlsta;
991
992 DEBUGFUNC("e1000_write_kmrn_reg_generic");
993
994 if (!locked) {
995 s32 ret_val = E1000_SUCCESS;
996
997 if (!hw->phy.ops.acquire)
998 return E1000_SUCCESS;
999
1000 ret_val = hw->phy.ops.acquire(hw);
1001 if (ret_val)
1002 return ret_val;
1003 }
1004
1005 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
1006 E1000_KMRNCTRLSTA_OFFSET) | data;
1007 E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta);
1008 E1000_WRITE_FLUSH(hw);
1009
1010 usec_delay(2);
1011
1012 if (!locked)
1013 hw->phy.ops.release(hw);
1014
1015 return E1000_SUCCESS;
1016 }
1017
1018 /**
1019 * e1000_write_kmrn_reg_generic - Write kumeran register
1020 * @hw: pointer to the HW structure
1021 * @offset: register offset to write to
1022 * @data: data to write at register offset
1023 *
1024 * Acquires semaphore then writes the data to the PHY register at the offset
1025 * using the kumeran interface. Release the acquired semaphore before exiting.
1026 **/
e1000_write_kmrn_reg_generic(struct e1000_hw * hw,u32 offset,u16 data)1027 s32 e1000_write_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 data)
1028 {
1029 return __e1000_write_kmrn_reg(hw, offset, data, false);
1030 }
1031
1032 /**
1033 * e1000_write_kmrn_reg_locked - Write kumeran register
1034 * @hw: pointer to the HW structure
1035 * @offset: register offset to write to
1036 * @data: data to write at register offset
1037 *
1038 * Write the data to PHY register at the offset using the kumeran interface.
1039 * Assumes semaphore already acquired.
1040 **/
e1000_write_kmrn_reg_locked(struct e1000_hw * hw,u32 offset,u16 data)1041 s32 e1000_write_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 data)
1042 {
1043 return __e1000_write_kmrn_reg(hw, offset, data, true);
1044 }
1045
1046 /**
1047 * e1000_set_master_slave_mode - Setup PHY for Master/slave mode
1048 * @hw: pointer to the HW structure
1049 *
1050 * Sets up Master/slave mode
1051 **/
e1000_set_master_slave_mode(struct e1000_hw * hw)1052 static s32 e1000_set_master_slave_mode(struct e1000_hw *hw)
1053 {
1054 s32 ret_val;
1055 u16 phy_data;
1056
1057 /* Resolve Master/Slave mode */
1058 ret_val = hw->phy.ops.read_reg(hw, PHY_1000T_CTRL, &phy_data);
1059 if (ret_val)
1060 return ret_val;
1061
1062 /* load defaults for future use */
1063 hw->phy.original_ms_type = (phy_data & CR_1000T_MS_ENABLE) ?
1064 ((phy_data & CR_1000T_MS_VALUE) ?
1065 e1000_ms_force_master :
1066 e1000_ms_force_slave) : e1000_ms_auto;
1067
1068 switch (hw->phy.ms_type) {
1069 case e1000_ms_force_master:
1070 phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
1071 break;
1072 case e1000_ms_force_slave:
1073 phy_data |= CR_1000T_MS_ENABLE;
1074 phy_data &= ~(CR_1000T_MS_VALUE);
1075 break;
1076 case e1000_ms_auto:
1077 phy_data &= ~CR_1000T_MS_ENABLE;
1078 break;
1079 default:
1080 break;
1081 }
1082
1083 return hw->phy.ops.write_reg(hw, PHY_1000T_CTRL, phy_data);
1084 }
1085
1086 /**
1087 * e1000_copper_link_setup_82577 - Setup 82577 PHY for copper link
1088 * @hw: pointer to the HW structure
1089 *
1090 * Sets up Carrier-sense on Transmit and downshift values.
1091 **/
e1000_copper_link_setup_82577(struct e1000_hw * hw)1092 s32 e1000_copper_link_setup_82577(struct e1000_hw *hw)
1093 {
1094 s32 ret_val;
1095 u16 phy_data;
1096
1097 DEBUGFUNC("e1000_copper_link_setup_82577");
1098
1099 if (hw->phy.type == e1000_phy_82580) {
1100 ret_val = hw->phy.ops.reset(hw);
1101 if (ret_val) {
1102 DEBUGOUT("Error resetting the PHY.\n");
1103 return ret_val;
1104 }
1105 }
1106
1107 /* Enable CRS on Tx. This must be set for half-duplex operation. */
1108 ret_val = hw->phy.ops.read_reg(hw, I82577_CFG_REG, &phy_data);
1109 if (ret_val)
1110 return ret_val;
1111
1112 phy_data |= I82577_CFG_ASSERT_CRS_ON_TX;
1113
1114 /* Enable downshift */
1115 phy_data |= I82577_CFG_ENABLE_DOWNSHIFT;
1116
1117 ret_val = hw->phy.ops.write_reg(hw, I82577_CFG_REG, phy_data);
1118 if (ret_val)
1119 return ret_val;
1120
1121 /* Set MDI/MDIX mode */
1122 ret_val = hw->phy.ops.read_reg(hw, I82577_PHY_CTRL_2, &phy_data);
1123 if (ret_val)
1124 return ret_val;
1125 phy_data &= ~I82577_PHY_CTRL2_MDIX_CFG_MASK;
1126 /* Options:
1127 * 0 - Auto (default)
1128 * 1 - MDI mode
1129 * 2 - MDI-X mode
1130 */
1131 switch (hw->phy.mdix) {
1132 case 1:
1133 break;
1134 case 2:
1135 phy_data |= I82577_PHY_CTRL2_MANUAL_MDIX;
1136 break;
1137 case 0:
1138 /* FALLTHROUGH */
1139 default:
1140 phy_data |= I82577_PHY_CTRL2_AUTO_MDI_MDIX;
1141 break;
1142 }
1143 ret_val = hw->phy.ops.write_reg(hw, I82577_PHY_CTRL_2, phy_data);
1144 if (ret_val)
1145 return ret_val;
1146
1147 return e1000_set_master_slave_mode(hw);
1148 }
1149
1150 /**
1151 * e1000_copper_link_setup_m88 - Setup m88 PHY's for copper link
1152 * @hw: pointer to the HW structure
1153 *
1154 * Sets up MDI/MDI-X and polarity for m88 PHY's. If necessary, transmit clock
1155 * and downshift values are set also.
1156 **/
e1000_copper_link_setup_m88(struct e1000_hw * hw)1157 s32 e1000_copper_link_setup_m88(struct e1000_hw *hw)
1158 {
1159 struct e1000_phy_info *phy = &hw->phy;
1160 s32 ret_val;
1161 u16 phy_data;
1162
1163 DEBUGFUNC("e1000_copper_link_setup_m88");
1164
1165
1166 /* Enable CRS on Tx. This must be set for half-duplex operation. */
1167 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1168 if (ret_val)
1169 return ret_val;
1170
1171 /* For BM PHY this bit is downshift enable */
1172 if (phy->type != e1000_phy_bm)
1173 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1174
1175 /* Options:
1176 * MDI/MDI-X = 0 (default)
1177 * 0 - Auto for all speeds
1178 * 1 - MDI mode
1179 * 2 - MDI-X mode
1180 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
1181 */
1182 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1183
1184 switch (phy->mdix) {
1185 case 1:
1186 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
1187 break;
1188 case 2:
1189 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
1190 break;
1191 case 3:
1192 phy_data |= M88E1000_PSCR_AUTO_X_1000T;
1193 break;
1194 case 0:
1195 /* FALLTHROUGH */
1196 default:
1197 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
1198 break;
1199 }
1200
1201 /* Options:
1202 * disable_polarity_correction = 0 (default)
1203 * Automatic Correction for Reversed Cable Polarity
1204 * 0 - Disabled
1205 * 1 - Enabled
1206 */
1207 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
1208 if (phy->disable_polarity_correction)
1209 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
1210
1211 /* Enable downshift on BM (disabled by default) */
1212 if (phy->type == e1000_phy_bm) {
1213 /* For 82574/82583, first disable then enable downshift */
1214 if (phy->id == BME1000_E_PHY_ID_R2) {
1215 phy_data &= ~BME1000_PSCR_ENABLE_DOWNSHIFT;
1216 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL,
1217 phy_data);
1218 if (ret_val)
1219 return ret_val;
1220 /* Commit the changes. */
1221 ret_val = phy->ops.commit(hw);
1222 if (ret_val) {
1223 DEBUGOUT("Error committing the PHY changes\n");
1224 return ret_val;
1225 }
1226 }
1227
1228 phy_data |= BME1000_PSCR_ENABLE_DOWNSHIFT;
1229 }
1230
1231 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1232 if (ret_val)
1233 return ret_val;
1234
1235 if ((phy->type == e1000_phy_m88) &&
1236 (phy->revision < E1000_REVISION_4) &&
1237 (phy->id != BME1000_E_PHY_ID_R2)) {
1238 /* Force TX_CLK in the Extended PHY Specific Control Register
1239 * to 25MHz clock.
1240 */
1241 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
1242 &phy_data);
1243 if (ret_val)
1244 return ret_val;
1245
1246 phy_data |= M88E1000_EPSCR_TX_CLK_25;
1247
1248 if ((phy->revision == E1000_REVISION_2) &&
1249 (phy->id == M88E1111_I_PHY_ID)) {
1250 /* 82573L PHY - set the downshift counter to 5x. */
1251 phy_data &= ~M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK;
1252 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
1253 } else {
1254 /* Configure Master and Slave downshift values */
1255 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
1256 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
1257 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
1258 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
1259 }
1260 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
1261 phy_data);
1262 if (ret_val)
1263 return ret_val;
1264 }
1265
1266 if ((phy->type == e1000_phy_bm) && (phy->id == BME1000_E_PHY_ID_R2)) {
1267 /* Set PHY page 0, register 29 to 0x0003 */
1268 ret_val = phy->ops.write_reg(hw, 29, 0x0003);
1269 if (ret_val)
1270 return ret_val;
1271
1272 /* Set PHY page 0, register 30 to 0x0000 */
1273 ret_val = phy->ops.write_reg(hw, 30, 0x0000);
1274 if (ret_val)
1275 return ret_val;
1276 }
1277
1278 /* Commit the changes. */
1279 ret_val = phy->ops.commit(hw);
1280 if (ret_val) {
1281 DEBUGOUT("Error committing the PHY changes\n");
1282 return ret_val;
1283 }
1284
1285 if (phy->type == e1000_phy_82578) {
1286 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
1287 &phy_data);
1288 if (ret_val)
1289 return ret_val;
1290
1291 /* 82578 PHY - set the downshift count to 1x. */
1292 phy_data |= I82578_EPSCR_DOWNSHIFT_ENABLE;
1293 phy_data &= ~I82578_EPSCR_DOWNSHIFT_COUNTER_MASK;
1294 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
1295 phy_data);
1296 if (ret_val)
1297 return ret_val;
1298 }
1299
1300 return E1000_SUCCESS;
1301 }
1302
1303 /**
1304 * e1000_copper_link_setup_m88_gen2 - Setup m88 PHY's for copper link
1305 * @hw: pointer to the HW structure
1306 *
1307 * Sets up MDI/MDI-X and polarity for i347-AT4, m88e1322 and m88e1112 PHY's.
1308 * Also enables and sets the downshift parameters.
1309 **/
e1000_copper_link_setup_m88_gen2(struct e1000_hw * hw)1310 s32 e1000_copper_link_setup_m88_gen2(struct e1000_hw *hw)
1311 {
1312 struct e1000_phy_info *phy = &hw->phy;
1313 s32 ret_val;
1314 u16 phy_data;
1315
1316 DEBUGFUNC("e1000_copper_link_setup_m88_gen2");
1317
1318
1319 /* Enable CRS on Tx. This must be set for half-duplex operation. */
1320 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1321 if (ret_val)
1322 return ret_val;
1323
1324 /* Options:
1325 * MDI/MDI-X = 0 (default)
1326 * 0 - Auto for all speeds
1327 * 1 - MDI mode
1328 * 2 - MDI-X mode
1329 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
1330 */
1331 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1332
1333 switch (phy->mdix) {
1334 case 1:
1335 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
1336 break;
1337 case 2:
1338 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
1339 break;
1340 case 3:
1341 /* M88E1112 does not support this mode) */
1342 if (phy->id != M88E1112_E_PHY_ID) {
1343 phy_data |= M88E1000_PSCR_AUTO_X_1000T;
1344 break;
1345 }
1346 /* FALLTHROUGH */
1347 case 0:
1348 /* FALLTHROUGH */
1349 default:
1350 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
1351 break;
1352 }
1353
1354 /* Options:
1355 * disable_polarity_correction = 0 (default)
1356 * Automatic Correction for Reversed Cable Polarity
1357 * 0 - Disabled
1358 * 1 - Enabled
1359 */
1360 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
1361 if (phy->disable_polarity_correction)
1362 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
1363
1364 /* Enable downshift and setting it to X6 */
1365 if (phy->id == M88E1543_E_PHY_ID) {
1366 phy_data &= ~I347AT4_PSCR_DOWNSHIFT_ENABLE;
1367 ret_val =
1368 phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1369 if (ret_val)
1370 return ret_val;
1371
1372 ret_val = phy->ops.commit(hw);
1373 if (ret_val) {
1374 DEBUGOUT("Error committing the PHY changes\n");
1375 return ret_val;
1376 }
1377 }
1378
1379 phy_data &= ~I347AT4_PSCR_DOWNSHIFT_MASK;
1380 phy_data |= I347AT4_PSCR_DOWNSHIFT_6X;
1381 phy_data |= I347AT4_PSCR_DOWNSHIFT_ENABLE;
1382
1383 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1384 if (ret_val)
1385 return ret_val;
1386
1387 /* Commit the changes. */
1388 ret_val = phy->ops.commit(hw);
1389 if (ret_val) {
1390 DEBUGOUT("Error committing the PHY changes\n");
1391 return ret_val;
1392 }
1393
1394 ret_val = e1000_set_master_slave_mode(hw);
1395 if (ret_val)
1396 return ret_val;
1397
1398 return E1000_SUCCESS;
1399 }
1400
1401 /**
1402 * e1000_copper_link_setup_igp - Setup igp PHY's for copper link
1403 * @hw: pointer to the HW structure
1404 *
1405 * Sets up LPLU, MDI/MDI-X, polarity, Smartspeed and Master/Slave config for
1406 * igp PHY's.
1407 **/
e1000_copper_link_setup_igp(struct e1000_hw * hw)1408 s32 e1000_copper_link_setup_igp(struct e1000_hw *hw)
1409 {
1410 struct e1000_phy_info *phy = &hw->phy;
1411 s32 ret_val;
1412 u16 data;
1413
1414 DEBUGFUNC("e1000_copper_link_setup_igp");
1415
1416
1417 ret_val = hw->phy.ops.reset(hw);
1418 if (ret_val) {
1419 DEBUGOUT("Error resetting the PHY.\n");
1420 return ret_val;
1421 }
1422
1423 /* Wait 100ms for MAC to configure PHY from NVM settings, to avoid
1424 * timeout issues when LFS is enabled.
1425 */
1426 msec_delay(100);
1427
1428 /* The NVM settings will configure LPLU in D3 for
1429 * non-IGP1 PHYs.
1430 */
1431 if (phy->type == e1000_phy_igp) {
1432 /* disable lplu d3 during driver init */
1433 ret_val = hw->phy.ops.set_d3_lplu_state(hw, false);
1434 if (ret_val) {
1435 DEBUGOUT("Error Disabling LPLU D3\n");
1436 return ret_val;
1437 }
1438 }
1439
1440 /* disable lplu d0 during driver init */
1441 if (hw->phy.ops.set_d0_lplu_state) {
1442 ret_val = hw->phy.ops.set_d0_lplu_state(hw, false);
1443 if (ret_val) {
1444 DEBUGOUT("Error Disabling LPLU D0\n");
1445 return ret_val;
1446 }
1447 }
1448 /* Configure mdi-mdix settings */
1449 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &data);
1450 if (ret_val)
1451 return ret_val;
1452
1453 data &= ~IGP01E1000_PSCR_AUTO_MDIX;
1454
1455 switch (phy->mdix) {
1456 case 1:
1457 data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1458 break;
1459 case 2:
1460 data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
1461 break;
1462 case 0:
1463 /* FALLTHROUGH */
1464 default:
1465 data |= IGP01E1000_PSCR_AUTO_MDIX;
1466 break;
1467 }
1468 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, data);
1469 if (ret_val)
1470 return ret_val;
1471
1472 /* set auto-master slave resolution settings */
1473 if (hw->mac.autoneg) {
1474 /* when autonegotiation advertisement is only 1000Mbps then we
1475 * should disable SmartSpeed and enable Auto MasterSlave
1476 * resolution as hardware default.
1477 */
1478 if (phy->autoneg_advertised == ADVERTISE_1000_FULL) {
1479 /* Disable SmartSpeed */
1480 ret_val = phy->ops.read_reg(hw,
1481 IGP01E1000_PHY_PORT_CONFIG,
1482 &data);
1483 if (ret_val)
1484 return ret_val;
1485
1486 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1487 ret_val = phy->ops.write_reg(hw,
1488 IGP01E1000_PHY_PORT_CONFIG,
1489 data);
1490 if (ret_val)
1491 return ret_val;
1492
1493 /* Set auto Master/Slave resolution process */
1494 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, &data);
1495 if (ret_val)
1496 return ret_val;
1497
1498 data &= ~CR_1000T_MS_ENABLE;
1499 ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL, data);
1500 if (ret_val)
1501 return ret_val;
1502 }
1503
1504 ret_val = e1000_set_master_slave_mode(hw);
1505 }
1506
1507 return ret_val;
1508 }
1509
1510 /**
1511 * e1000_phy_setup_autoneg - Configure PHY for auto-negotiation
1512 * @hw: pointer to the HW structure
1513 *
1514 * Reads the MII auto-neg advertisement register and/or the 1000T control
1515 * register and if the PHY is already setup for auto-negotiation, then
1516 * return successful. Otherwise, setup advertisement and flow control to
1517 * the appropriate values for the wanted auto-negotiation.
1518 **/
e1000_phy_setup_autoneg(struct e1000_hw * hw)1519 s32 e1000_phy_setup_autoneg(struct e1000_hw *hw)
1520 {
1521 struct e1000_phy_info *phy = &hw->phy;
1522 s32 ret_val;
1523 u16 mii_autoneg_adv_reg;
1524 u16 mii_1000t_ctrl_reg = 0;
1525
1526 DEBUGFUNC("e1000_phy_setup_autoneg");
1527
1528 phy->autoneg_advertised &= phy->autoneg_mask;
1529
1530 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
1531 ret_val = phy->ops.read_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
1532 if (ret_val)
1533 return ret_val;
1534
1535 if (phy->autoneg_mask & ADVERTISE_1000_FULL) {
1536 /* Read the MII 1000Base-T Control Register (Address 9). */
1537 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL,
1538 &mii_1000t_ctrl_reg);
1539 if (ret_val)
1540 return ret_val;
1541 }
1542
1543 /* Need to parse both autoneg_advertised and fc and set up
1544 * the appropriate PHY registers. First we will parse for
1545 * autoneg_advertised software override. Since we can advertise
1546 * a plethora of combinations, we need to check each bit
1547 * individually.
1548 */
1549
1550 /* First we clear all the 10/100 mb speed bits in the Auto-Neg
1551 * Advertisement Register (Address 4) and the 1000 mb speed bits in
1552 * the 1000Base-T Control Register (Address 9).
1553 */
1554 mii_autoneg_adv_reg &= ~(NWAY_AR_100TX_FD_CAPS |
1555 NWAY_AR_100TX_HD_CAPS |
1556 NWAY_AR_10T_FD_CAPS |
1557 NWAY_AR_10T_HD_CAPS);
1558 mii_1000t_ctrl_reg &= ~(CR_1000T_HD_CAPS | CR_1000T_FD_CAPS);
1559
1560 DEBUGOUT1("autoneg_advertised %x\n", phy->autoneg_advertised);
1561
1562 /* Do we want to advertise 10 Mb Half Duplex? */
1563 if (phy->autoneg_advertised & ADVERTISE_10_HALF) {
1564 DEBUGOUT("Advertise 10mb Half duplex\n");
1565 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
1566 }
1567
1568 /* Do we want to advertise 10 Mb Full Duplex? */
1569 if (phy->autoneg_advertised & ADVERTISE_10_FULL) {
1570 DEBUGOUT("Advertise 10mb Full duplex\n");
1571 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
1572 }
1573
1574 /* Do we want to advertise 100 Mb Half Duplex? */
1575 if (phy->autoneg_advertised & ADVERTISE_100_HALF) {
1576 DEBUGOUT("Advertise 100mb Half duplex\n");
1577 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
1578 }
1579
1580 /* Do we want to advertise 100 Mb Full Duplex? */
1581 if (phy->autoneg_advertised & ADVERTISE_100_FULL) {
1582 DEBUGOUT("Advertise 100mb Full duplex\n");
1583 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
1584 }
1585
1586 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
1587 if (phy->autoneg_advertised & ADVERTISE_1000_HALF)
1588 DEBUGOUT("Advertise 1000mb Half duplex request denied!\n");
1589
1590 /* Do we want to advertise 1000 Mb Full Duplex? */
1591 if (phy->autoneg_advertised & ADVERTISE_1000_FULL) {
1592 DEBUGOUT("Advertise 1000mb Full duplex\n");
1593 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
1594 }
1595
1596 /* Check for a software override of the flow control settings, and
1597 * setup the PHY advertisement registers accordingly. If
1598 * auto-negotiation is enabled, then software will have to set the
1599 * "PAUSE" bits to the correct value in the Auto-Negotiation
1600 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-
1601 * negotiation.
1602 *
1603 * The possible values of the "fc" parameter are:
1604 * 0: Flow control is completely disabled
1605 * 1: Rx flow control is enabled (we can receive pause frames
1606 * but not send pause frames).
1607 * 2: Tx flow control is enabled (we can send pause frames
1608 * but we do not support receiving pause frames).
1609 * 3: Both Rx and Tx flow control (symmetric) are enabled.
1610 * other: No software override. The flow control configuration
1611 * in the EEPROM is used.
1612 */
1613 switch (hw->fc.current_mode) {
1614 case e1000_fc_none:
1615 /* Flow control (Rx & Tx) is completely disabled by a
1616 * software over-ride.
1617 */
1618 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1619 break;
1620 case e1000_fc_rx_pause:
1621 /* Rx Flow control is enabled, and Tx Flow control is
1622 * disabled, by a software over-ride.
1623 *
1624 * Since there really isn't a way to advertise that we are
1625 * capable of Rx Pause ONLY, we will advertise that we
1626 * support both symmetric and asymmetric Rx PAUSE. Later
1627 * (in e1000_config_fc_after_link_up) we will disable the
1628 * hw's ability to send PAUSE frames.
1629 */
1630 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1631 break;
1632 case e1000_fc_tx_pause:
1633 /* Tx Flow control is enabled, and Rx Flow control is
1634 * disabled, by a software over-ride.
1635 */
1636 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
1637 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
1638 break;
1639 case e1000_fc_full:
1640 /* Flow control (both Rx and Tx) is enabled by a software
1641 * over-ride.
1642 */
1643 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1644 break;
1645 default:
1646 DEBUGOUT("Flow control param set incorrectly\n");
1647 return -E1000_ERR_CONFIG;
1648 }
1649
1650 ret_val = phy->ops.write_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
1651 if (ret_val)
1652 return ret_val;
1653
1654 DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
1655
1656 if (phy->autoneg_mask & ADVERTISE_1000_FULL)
1657 ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL,
1658 mii_1000t_ctrl_reg);
1659
1660 return ret_val;
1661 }
1662
1663 /**
1664 * e1000_copper_link_autoneg - Setup/Enable autoneg for copper link
1665 * @hw: pointer to the HW structure
1666 *
1667 * Performs initial bounds checking on autoneg advertisement parameter, then
1668 * configure to advertise the full capability. Setup the PHY to autoneg
1669 * and restart the negotiation process between the link partner. If
1670 * autoneg_wait_to_complete, then wait for autoneg to complete before exiting.
1671 **/
e1000_copper_link_autoneg(struct e1000_hw * hw)1672 s32 e1000_copper_link_autoneg(struct e1000_hw *hw)
1673 {
1674 struct e1000_phy_info *phy = &hw->phy;
1675 s32 ret_val;
1676 u16 phy_ctrl;
1677
1678 DEBUGFUNC("e1000_copper_link_autoneg");
1679
1680 /* Perform some bounds checking on the autoneg advertisement
1681 * parameter.
1682 */
1683 phy->autoneg_advertised &= phy->autoneg_mask;
1684
1685 /* If autoneg_advertised is zero, we assume it was not defaulted
1686 * by the calling code so we set to advertise full capability.
1687 */
1688 if (!phy->autoneg_advertised)
1689 phy->autoneg_advertised = phy->autoneg_mask;
1690
1691 DEBUGOUT("Reconfiguring auto-neg advertisement params\n");
1692 ret_val = e1000_phy_setup_autoneg(hw);
1693 if (ret_val) {
1694 DEBUGOUT("Error Setting up Auto-Negotiation\n");
1695 return ret_val;
1696 }
1697 DEBUGOUT("Restarting Auto-Neg\n");
1698
1699 /* Restart auto-negotiation by setting the Auto Neg Enable bit and
1700 * the Auto Neg Restart bit in the PHY control register.
1701 */
1702 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_ctrl);
1703 if (ret_val)
1704 return ret_val;
1705
1706 phy_ctrl |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
1707 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_ctrl);
1708 if (ret_val)
1709 return ret_val;
1710
1711 /* Does the user want to wait for Auto-Neg to complete here, or
1712 * check at a later time (for example, callback routine).
1713 */
1714 if (phy->autoneg_wait_to_complete) {
1715 ret_val = e1000_wait_autoneg(hw);
1716 if (ret_val) {
1717 DEBUGOUT("Error while waiting for autoneg to complete\n");
1718 return ret_val;
1719 }
1720 }
1721
1722 hw->mac.get_link_status = true;
1723
1724 return ret_val;
1725 }
1726
1727 /**
1728 * e1000_setup_copper_link_generic - Configure copper link settings
1729 * @hw: pointer to the HW structure
1730 *
1731 * Calls the appropriate function to configure the link for auto-neg or forced
1732 * speed and duplex. Then we check for link, once link is established calls
1733 * to configure collision distance and flow control are called. If link is
1734 * not established, we return -E1000_ERR_PHY (-2).
1735 **/
e1000_setup_copper_link_generic(struct e1000_hw * hw)1736 s32 e1000_setup_copper_link_generic(struct e1000_hw *hw)
1737 {
1738 s32 ret_val;
1739 bool link = true;
1740
1741 DEBUGFUNC("e1000_setup_copper_link_generic");
1742
1743 if (hw->mac.autoneg) {
1744 /* Setup autoneg and flow control advertisement and perform
1745 * autonegotiation.
1746 */
1747 ret_val = e1000_copper_link_autoneg(hw);
1748 if (ret_val)
1749 return ret_val;
1750 } else {
1751 /* PHY will be set to 10H, 10F, 100H or 100F
1752 * depending on user settings.
1753 */
1754 DEBUGOUT("Forcing Speed and Duplex\n");
1755 ret_val = hw->phy.ops.force_speed_duplex(hw);
1756 if (ret_val) {
1757 DEBUGOUT("Error Forcing Speed and Duplex\n");
1758 return ret_val;
1759 }
1760 }
1761
1762 /* Check link status. Wait up to 100 microseconds for link to become
1763 * valid.
1764 */
1765 ret_val = e1000_phy_has_link_generic(hw, COPPER_LINK_UP_LIMIT, 10,
1766 &link);
1767 if (ret_val)
1768 return ret_val;
1769
1770 if (link) {
1771 DEBUGOUT("Valid link established!!!\n");
1772 hw->mac.ops.config_collision_dist(hw);
1773 ret_val = e1000_config_fc_after_link_up_generic(hw);
1774 } else {
1775 DEBUGOUT("Unable to establish link!!!\n");
1776 }
1777
1778 return ret_val;
1779 }
1780
1781 /**
1782 * e1000_phy_force_speed_duplex_igp - Force speed/duplex for igp PHY
1783 * @hw: pointer to the HW structure
1784 *
1785 * Calls the PHY setup function to force speed and duplex. Clears the
1786 * auto-crossover to force MDI manually. Waits for link and returns
1787 * successful if link up is successful, else -E1000_ERR_PHY (-2).
1788 **/
e1000_phy_force_speed_duplex_igp(struct e1000_hw * hw)1789 s32 e1000_phy_force_speed_duplex_igp(struct e1000_hw *hw)
1790 {
1791 struct e1000_phy_info *phy = &hw->phy;
1792 s32 ret_val;
1793 u16 phy_data;
1794 bool link;
1795
1796 DEBUGFUNC("e1000_phy_force_speed_duplex_igp");
1797
1798 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);
1799 if (ret_val)
1800 return ret_val;
1801
1802 e1000_phy_force_speed_duplex_setup(hw, &phy_data);
1803
1804 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);
1805 if (ret_val)
1806 return ret_val;
1807
1808 /* Clear Auto-Crossover to force MDI manually. IGP requires MDI
1809 * forced whenever speed and duplex are forced.
1810 */
1811 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
1812 if (ret_val)
1813 return ret_val;
1814
1815 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
1816 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1817
1818 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
1819 if (ret_val)
1820 return ret_val;
1821
1822 DEBUGOUT1("IGP PSCR: %X\n", phy_data);
1823
1824 usec_delay(1);
1825
1826 if (phy->autoneg_wait_to_complete) {
1827 DEBUGOUT("Waiting for forced speed/duplex link on IGP phy.\n");
1828
1829 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1830 100000, &link);
1831 if (ret_val)
1832 return ret_val;
1833
1834 if (!link)
1835 DEBUGOUT("Link taking longer than expected.\n");
1836
1837 /* Try once more */
1838 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1839 100000, &link);
1840 }
1841
1842 return ret_val;
1843 }
1844
1845 /**
1846 * e1000_phy_force_speed_duplex_m88 - Force speed/duplex for m88 PHY
1847 * @hw: pointer to the HW structure
1848 *
1849 * Calls the PHY setup function to force speed and duplex. Clears the
1850 * auto-crossover to force MDI manually. Resets the PHY to commit the
1851 * changes. If time expires while waiting for link up, we reset the DSP.
1852 * After reset, TX_CLK and CRS on Tx must be set. Return successful upon
1853 * successful completion, else return corresponding error code.
1854 **/
e1000_phy_force_speed_duplex_m88(struct e1000_hw * hw)1855 s32 e1000_phy_force_speed_duplex_m88(struct e1000_hw *hw)
1856 {
1857 struct e1000_phy_info *phy = &hw->phy;
1858 s32 ret_val;
1859 u16 phy_data;
1860 bool link;
1861
1862 DEBUGFUNC("e1000_phy_force_speed_duplex_m88");
1863
1864 /* I210 and I211 devices support Auto-Crossover in forced operation. */
1865 if (phy->type != e1000_phy_i210) {
1866 /* Clear Auto-Crossover to force MDI manually. M88E1000
1867 * requires MDI forced whenever speed and duplex are forced.
1868 */
1869 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL,
1870 &phy_data);
1871 if (ret_val)
1872 return ret_val;
1873
1874 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1875 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL,
1876 phy_data);
1877 if (ret_val)
1878 return ret_val;
1879
1880 DEBUGOUT1("M88E1000 PSCR: %X\n", phy_data);
1881 }
1882
1883 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);
1884 if (ret_val)
1885 return ret_val;
1886
1887 e1000_phy_force_speed_duplex_setup(hw, &phy_data);
1888
1889 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);
1890 if (ret_val)
1891 return ret_val;
1892
1893 /* Reset the phy to commit changes. */
1894 ret_val = hw->phy.ops.commit(hw);
1895 if (ret_val)
1896 return ret_val;
1897
1898 if (phy->autoneg_wait_to_complete) {
1899 DEBUGOUT("Waiting for forced speed/duplex link on M88 phy.\n");
1900
1901 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1902 100000, &link);
1903 if (ret_val)
1904 return ret_val;
1905
1906 if (!link) {
1907 bool reset_dsp = true;
1908
1909 switch (hw->phy.id) {
1910 case I347AT4_E_PHY_ID:
1911 case M88E1340M_E_PHY_ID:
1912 case M88E1112_E_PHY_ID:
1913 case M88E1543_E_PHY_ID:
1914 case M88E1512_E_PHY_ID:
1915 case I210_I_PHY_ID:
1916 reset_dsp = false;
1917 break;
1918 default:
1919 if (hw->phy.type != e1000_phy_m88)
1920 reset_dsp = false;
1921 break;
1922 }
1923
1924 if (!reset_dsp) {
1925 DEBUGOUT("Link taking longer than expected.\n");
1926 } else {
1927 /* We didn't get link.
1928 * Reset the DSP and cross our fingers.
1929 */
1930 ret_val = phy->ops.write_reg(hw,
1931 M88E1000_PHY_PAGE_SELECT,
1932 0x001d);
1933 if (ret_val)
1934 return ret_val;
1935 ret_val = e1000_phy_reset_dsp_generic(hw);
1936 if (ret_val)
1937 return ret_val;
1938 }
1939 }
1940
1941 /* Try once more */
1942 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1943 100000, &link);
1944 if (ret_val)
1945 return ret_val;
1946 }
1947
1948 if (hw->phy.type != e1000_phy_m88)
1949 return E1000_SUCCESS;
1950
1951 if (hw->phy.id == I347AT4_E_PHY_ID ||
1952 hw->phy.id == M88E1340M_E_PHY_ID ||
1953 hw->phy.id == M88E1112_E_PHY_ID)
1954 return E1000_SUCCESS;
1955 if (hw->phy.id == I210_I_PHY_ID)
1956 return E1000_SUCCESS;
1957 if ((hw->phy.id == M88E1543_E_PHY_ID) ||
1958 (hw->phy.id == M88E1512_E_PHY_ID))
1959 return E1000_SUCCESS;
1960 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
1961 if (ret_val)
1962 return ret_val;
1963
1964 /* Resetting the phy means we need to re-force TX_CLK in the
1965 * Extended PHY Specific Control Register to 25MHz clock from
1966 * the reset value of 2.5MHz.
1967 */
1968 phy_data |= M88E1000_EPSCR_TX_CLK_25;
1969 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
1970 if (ret_val)
1971 return ret_val;
1972
1973 /* In addition, we must re-enable CRS on Tx for both half and full
1974 * duplex.
1975 */
1976 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1977 if (ret_val)
1978 return ret_val;
1979
1980 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1981 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1982
1983 return ret_val;
1984 }
1985
1986 /**
1987 * e1000_phy_force_speed_duplex_ife - Force PHY speed & duplex
1988 * @hw: pointer to the HW structure
1989 *
1990 * Forces the speed and duplex settings of the PHY.
1991 * This is a function pointer entry point only called by
1992 * PHY setup routines.
1993 **/
e1000_phy_force_speed_duplex_ife(struct e1000_hw * hw)1994 s32 e1000_phy_force_speed_duplex_ife(struct e1000_hw *hw)
1995 {
1996 struct e1000_phy_info *phy = &hw->phy;
1997 s32 ret_val;
1998 u16 data;
1999 bool link;
2000
2001 DEBUGFUNC("e1000_phy_force_speed_duplex_ife");
2002
2003 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &data);
2004 if (ret_val)
2005 return ret_val;
2006
2007 e1000_phy_force_speed_duplex_setup(hw, &data);
2008
2009 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, data);
2010 if (ret_val)
2011 return ret_val;
2012
2013 /* Disable MDI-X support for 10/100 */
2014 ret_val = phy->ops.read_reg(hw, IFE_PHY_MDIX_CONTROL, &data);
2015 if (ret_val)
2016 return ret_val;
2017
2018 data &= ~IFE_PMC_AUTO_MDIX;
2019 data &= ~IFE_PMC_FORCE_MDIX;
2020
2021 ret_val = phy->ops.write_reg(hw, IFE_PHY_MDIX_CONTROL, data);
2022 if (ret_val)
2023 return ret_val;
2024
2025 DEBUGOUT1("IFE PMC: %X\n", data);
2026
2027 usec_delay(1);
2028
2029 if (phy->autoneg_wait_to_complete) {
2030 DEBUGOUT("Waiting for forced speed/duplex link on IFE phy.\n");
2031
2032 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
2033 100000, &link);
2034 if (ret_val)
2035 return ret_val;
2036
2037 if (!link)
2038 DEBUGOUT("Link taking longer than expected.\n");
2039
2040 /* Try once more */
2041 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
2042 100000, &link);
2043 if (ret_val)
2044 return ret_val;
2045 }
2046
2047 return E1000_SUCCESS;
2048 }
2049
2050 /**
2051 * e1000_phy_force_speed_duplex_setup - Configure forced PHY speed/duplex
2052 * @hw: pointer to the HW structure
2053 * @phy_ctrl: pointer to current value of PHY_CONTROL
2054 *
2055 * Forces speed and duplex on the PHY by doing the following: disable flow
2056 * control, force speed/duplex on the MAC, disable auto speed detection,
2057 * disable auto-negotiation, configure duplex, configure speed, configure
2058 * the collision distance, write configuration to CTRL register. The
2059 * caller must write to the PHY_CONTROL register for these settings to
2060 * take effect.
2061 **/
e1000_phy_force_speed_duplex_setup(struct e1000_hw * hw,u16 * phy_ctrl)2062 void e1000_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl)
2063 {
2064 struct e1000_mac_info *mac = &hw->mac;
2065 u32 ctrl;
2066
2067 DEBUGFUNC("e1000_phy_force_speed_duplex_setup");
2068
2069 /* Turn off flow control when forcing speed/duplex */
2070 hw->fc.current_mode = e1000_fc_none;
2071
2072 /* Force speed/duplex on the mac */
2073 ctrl = E1000_READ_REG(hw, E1000_CTRL);
2074 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
2075 ctrl &= ~E1000_CTRL_SPD_SEL;
2076
2077 /* Disable Auto Speed Detection */
2078 ctrl &= ~E1000_CTRL_ASDE;
2079
2080 /* Disable autoneg on the phy */
2081 *phy_ctrl &= ~MII_CR_AUTO_NEG_EN;
2082
2083 /* Forcing Full or Half Duplex? */
2084 if (mac->forced_speed_duplex & E1000_ALL_HALF_DUPLEX) {
2085 ctrl &= ~E1000_CTRL_FD;
2086 *phy_ctrl &= ~MII_CR_FULL_DUPLEX;
2087 DEBUGOUT("Half Duplex\n");
2088 } else {
2089 ctrl |= E1000_CTRL_FD;
2090 *phy_ctrl |= MII_CR_FULL_DUPLEX;
2091 DEBUGOUT("Full Duplex\n");
2092 }
2093
2094 /* Forcing 10mb or 100mb? */
2095 if (mac->forced_speed_duplex & E1000_ALL_100_SPEED) {
2096 ctrl |= E1000_CTRL_SPD_100;
2097 *phy_ctrl |= MII_CR_SPEED_100;
2098 *phy_ctrl &= ~MII_CR_SPEED_1000;
2099 DEBUGOUT("Forcing 100mb\n");
2100 } else {
2101 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
2102 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100);
2103 DEBUGOUT("Forcing 10mb\n");
2104 }
2105
2106 hw->mac.ops.config_collision_dist(hw);
2107
2108 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
2109 }
2110
2111 /**
2112 * e1000_set_d3_lplu_state_generic - Sets low power link up state for D3
2113 * @hw: pointer to the HW structure
2114 * @active: boolean used to enable/disable lplu
2115 *
2116 * Success returns 0, Failure returns 1
2117 *
2118 * The low power link up (lplu) state is set to the power management level D3
2119 * and SmartSpeed is disabled when active is true, else clear lplu for D3
2120 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU
2121 * is used during Dx states where the power conservation is most important.
2122 * During driver activity, SmartSpeed should be enabled so performance is
2123 * maintained.
2124 **/
e1000_set_d3_lplu_state_generic(struct e1000_hw * hw,bool active)2125 s32 e1000_set_d3_lplu_state_generic(struct e1000_hw *hw, bool active)
2126 {
2127 struct e1000_phy_info *phy = &hw->phy;
2128 s32 ret_val;
2129 u16 data;
2130
2131 DEBUGFUNC("e1000_set_d3_lplu_state_generic");
2132
2133 if (!hw->phy.ops.read_reg)
2134 return E1000_SUCCESS;
2135
2136 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
2137 if (ret_val)
2138 return ret_val;
2139
2140 if (!active) {
2141 data &= ~IGP02E1000_PM_D3_LPLU;
2142 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
2143 data);
2144 if (ret_val)
2145 return ret_val;
2146 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
2147 * during Dx states where the power conservation is most
2148 * important. During driver activity we should enable
2149 * SmartSpeed, so performance is maintained.
2150 */
2151 if (phy->smart_speed == e1000_smart_speed_on) {
2152 ret_val = phy->ops.read_reg(hw,
2153 IGP01E1000_PHY_PORT_CONFIG,
2154 &data);
2155 if (ret_val)
2156 return ret_val;
2157
2158 data |= IGP01E1000_PSCFR_SMART_SPEED;
2159 ret_val = phy->ops.write_reg(hw,
2160 IGP01E1000_PHY_PORT_CONFIG,
2161 data);
2162 if (ret_val)
2163 return ret_val;
2164 } else if (phy->smart_speed == e1000_smart_speed_off) {
2165 ret_val = phy->ops.read_reg(hw,
2166 IGP01E1000_PHY_PORT_CONFIG,
2167 &data);
2168 if (ret_val)
2169 return ret_val;
2170
2171 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2172 ret_val = phy->ops.write_reg(hw,
2173 IGP01E1000_PHY_PORT_CONFIG,
2174 data);
2175 if (ret_val)
2176 return ret_val;
2177 }
2178 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
2179 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
2180 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
2181 data |= IGP02E1000_PM_D3_LPLU;
2182 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
2183 data);
2184 if (ret_val)
2185 return ret_val;
2186
2187 /* When LPLU is enabled, we should disable SmartSpeed */
2188 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
2189 &data);
2190 if (ret_val)
2191 return ret_val;
2192
2193 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2194 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
2195 data);
2196 }
2197
2198 return ret_val;
2199 }
2200
2201 /**
2202 * e1000_check_downshift_generic - Checks whether a downshift in speed occurred
2203 * @hw: pointer to the HW structure
2204 *
2205 * Success returns 0, Failure returns 1
2206 *
2207 * A downshift is detected by querying the PHY link health.
2208 **/
e1000_check_downshift_generic(struct e1000_hw * hw)2209 s32 e1000_check_downshift_generic(struct e1000_hw *hw)
2210 {
2211 struct e1000_phy_info *phy = &hw->phy;
2212 s32 ret_val;
2213 u16 phy_data, offset, mask;
2214
2215 DEBUGFUNC("e1000_check_downshift_generic");
2216
2217 switch (phy->type) {
2218 case e1000_phy_i210:
2219 case e1000_phy_m88:
2220 case e1000_phy_gg82563:
2221 case e1000_phy_bm:
2222 case e1000_phy_82578:
2223 offset = M88E1000_PHY_SPEC_STATUS;
2224 mask = M88E1000_PSSR_DOWNSHIFT;
2225 break;
2226 case e1000_phy_igp:
2227 case e1000_phy_igp_2:
2228 case e1000_phy_igp_3:
2229 offset = IGP01E1000_PHY_LINK_HEALTH;
2230 mask = IGP01E1000_PLHR_SS_DOWNGRADE;
2231 break;
2232 default:
2233 /* speed downshift not supported */
2234 phy->speed_downgraded = false;
2235 return E1000_SUCCESS;
2236 }
2237
2238 ret_val = phy->ops.read_reg(hw, offset, &phy_data);
2239
2240 if (!ret_val)
2241 phy->speed_downgraded = !!(phy_data & mask);
2242
2243 return ret_val;
2244 }
2245
2246 /**
2247 * e1000_check_polarity_m88 - Checks the polarity.
2248 * @hw: pointer to the HW structure
2249 *
2250 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
2251 *
2252 * Polarity is determined based on the PHY specific status register.
2253 **/
e1000_check_polarity_m88(struct e1000_hw * hw)2254 s32 e1000_check_polarity_m88(struct e1000_hw *hw)
2255 {
2256 struct e1000_phy_info *phy = &hw->phy;
2257 s32 ret_val;
2258 u16 data;
2259
2260 DEBUGFUNC("e1000_check_polarity_m88");
2261
2262 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &data);
2263
2264 if (!ret_val)
2265 phy->cable_polarity = ((data & M88E1000_PSSR_REV_POLARITY)
2266 ? e1000_rev_polarity_reversed
2267 : e1000_rev_polarity_normal);
2268
2269 return ret_val;
2270 }
2271
2272 /**
2273 * e1000_check_polarity_igp - Checks the polarity.
2274 * @hw: pointer to the HW structure
2275 *
2276 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
2277 *
2278 * Polarity is determined based on the PHY port status register, and the
2279 * current speed (since there is no polarity at 100Mbps).
2280 **/
e1000_check_polarity_igp(struct e1000_hw * hw)2281 s32 e1000_check_polarity_igp(struct e1000_hw *hw)
2282 {
2283 struct e1000_phy_info *phy = &hw->phy;
2284 s32 ret_val;
2285 u16 data, offset, mask;
2286
2287 DEBUGFUNC("e1000_check_polarity_igp");
2288
2289 /* Polarity is determined based on the speed of
2290 * our connection.
2291 */
2292 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data);
2293 if (ret_val)
2294 return ret_val;
2295
2296 if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
2297 IGP01E1000_PSSR_SPEED_1000MBPS) {
2298 offset = IGP01E1000_PHY_PCS_INIT_REG;
2299 mask = IGP01E1000_PHY_POLARITY_MASK;
2300 } else {
2301 /* This really only applies to 10Mbps since
2302 * there is no polarity for 100Mbps (always 0).
2303 */
2304 offset = IGP01E1000_PHY_PORT_STATUS;
2305 mask = IGP01E1000_PSSR_POLARITY_REVERSED;
2306 }
2307
2308 ret_val = phy->ops.read_reg(hw, offset, &data);
2309
2310 if (!ret_val)
2311 phy->cable_polarity = ((data & mask)
2312 ? e1000_rev_polarity_reversed
2313 : e1000_rev_polarity_normal);
2314
2315 return ret_val;
2316 }
2317
2318 /**
2319 * e1000_check_polarity_ife - Check cable polarity for IFE PHY
2320 * @hw: pointer to the HW structure
2321 *
2322 * Polarity is determined on the polarity reversal feature being enabled.
2323 **/
e1000_check_polarity_ife(struct e1000_hw * hw)2324 s32 e1000_check_polarity_ife(struct e1000_hw *hw)
2325 {
2326 struct e1000_phy_info *phy = &hw->phy;
2327 s32 ret_val;
2328 u16 phy_data, offset, mask;
2329
2330 DEBUGFUNC("e1000_check_polarity_ife");
2331
2332 /* Polarity is determined based on the reversal feature being enabled.
2333 */
2334 if (phy->polarity_correction) {
2335 offset = IFE_PHY_EXTENDED_STATUS_CONTROL;
2336 mask = IFE_PESC_POLARITY_REVERSED;
2337 } else {
2338 offset = IFE_PHY_SPECIAL_CONTROL;
2339 mask = IFE_PSC_FORCE_POLARITY;
2340 }
2341
2342 ret_val = phy->ops.read_reg(hw, offset, &phy_data);
2343
2344 if (!ret_val)
2345 phy->cable_polarity = ((phy_data & mask)
2346 ? e1000_rev_polarity_reversed
2347 : e1000_rev_polarity_normal);
2348
2349 return ret_val;
2350 }
2351
2352 /**
2353 * e1000_wait_autoneg - Wait for auto-neg completion
2354 * @hw: pointer to the HW structure
2355 *
2356 * Waits for auto-negotiation to complete or for the auto-negotiation time
2357 * limit to expire, which ever happens first.
2358 **/
e1000_wait_autoneg(struct e1000_hw * hw)2359 static s32 e1000_wait_autoneg(struct e1000_hw *hw)
2360 {
2361 s32 ret_val = E1000_SUCCESS;
2362 u16 i, phy_status;
2363
2364 DEBUGFUNC("e1000_wait_autoneg");
2365
2366 if (!hw->phy.ops.read_reg)
2367 return E1000_SUCCESS;
2368
2369 /* Break after autoneg completes or PHY_AUTO_NEG_LIMIT expires. */
2370 for (i = PHY_AUTO_NEG_LIMIT; i > 0; i--) {
2371 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
2372 if (ret_val)
2373 break;
2374 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
2375 if (ret_val)
2376 break;
2377 if (phy_status & MII_SR_AUTONEG_COMPLETE)
2378 break;
2379 msec_delay(100);
2380 }
2381
2382 /* PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation
2383 * has completed.
2384 */
2385 return ret_val;
2386 }
2387
2388 /**
2389 * e1000_phy_has_link_generic - Polls PHY for link
2390 * @hw: pointer to the HW structure
2391 * @iterations: number of times to poll for link
2392 * @usec_interval: delay between polling attempts
2393 * @success: pointer to whether polling was successful or not
2394 *
2395 * Polls the PHY status register for link, 'iterations' number of times.
2396 **/
e1000_phy_has_link_generic(struct e1000_hw * hw,u32 iterations,u32 usec_interval,bool * success)2397 s32 e1000_phy_has_link_generic(struct e1000_hw *hw, u32 iterations,
2398 u32 usec_interval, bool *success)
2399 {
2400 s32 ret_val = E1000_SUCCESS;
2401 u16 phy_status;
2402 u32 i;
2403
2404 DEBUGFUNC("e1000_phy_has_link_generic");
2405
2406 if (!hw->phy.ops.read_reg)
2407 return E1000_SUCCESS;
2408
2409 for (i = 0; i < iterations; i++) {
2410 /* Some PHYs require the PHY_STATUS register to be read
2411 * twice due to the link bit being sticky. No harm doing
2412 * it across the board.
2413 */
2414 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
2415 if (ret_val) {
2416 /* If the first read fails, another entity may have
2417 * ownership of the resources, wait and try again to
2418 * see if they have relinquished the resources yet.
2419 */
2420 if (usec_interval >= 1000)
2421 msec_delay(usec_interval/1000);
2422 else
2423 usec_delay(usec_interval);
2424 }
2425 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
2426 if (ret_val)
2427 break;
2428 if (phy_status & MII_SR_LINK_STATUS)
2429 break;
2430 if (usec_interval >= 1000)
2431 msec_delay(usec_interval/1000);
2432 else
2433 usec_delay(usec_interval);
2434 }
2435
2436 *success = (i < iterations);
2437
2438 return ret_val;
2439 }
2440
2441 /**
2442 * e1000_get_cable_length_m88 - Determine cable length for m88 PHY
2443 * @hw: pointer to the HW structure
2444 *
2445 * Reads the PHY specific status register to retrieve the cable length
2446 * information. The cable length is determined by averaging the minimum and
2447 * maximum values to get the "average" cable length. The m88 PHY has four
2448 * possible cable length values, which are:
2449 * Register Value Cable Length
2450 * 0 < 50 meters
2451 * 1 50 - 80 meters
2452 * 2 80 - 110 meters
2453 * 3 110 - 140 meters
2454 * 4 > 140 meters
2455 **/
e1000_get_cable_length_m88(struct e1000_hw * hw)2456 s32 e1000_get_cable_length_m88(struct e1000_hw *hw)
2457 {
2458 struct e1000_phy_info *phy = &hw->phy;
2459 s32 ret_val;
2460 u16 phy_data, index;
2461
2462 DEBUGFUNC("e1000_get_cable_length_m88");
2463
2464 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
2465 if (ret_val)
2466 return ret_val;
2467
2468 index = ((phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
2469 M88E1000_PSSR_CABLE_LENGTH_SHIFT);
2470
2471 if (index >= M88E1000_CABLE_LENGTH_TABLE_SIZE - 1)
2472 return -E1000_ERR_PHY;
2473
2474 phy->min_cable_length = e1000_m88_cable_length_table[index];
2475 phy->max_cable_length = e1000_m88_cable_length_table[index + 1];
2476
2477 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
2478
2479 return E1000_SUCCESS;
2480 }
2481
e1000_get_cable_length_m88_gen2(struct e1000_hw * hw)2482 s32 e1000_get_cable_length_m88_gen2(struct e1000_hw *hw)
2483 {
2484 struct e1000_phy_info *phy = &hw->phy;
2485 s32 ret_val;
2486 u16 phy_data, phy_data2, is_cm;
2487 u16 index, default_page;
2488
2489 DEBUGFUNC("e1000_get_cable_length_m88_gen2");
2490
2491 switch (hw->phy.id) {
2492 case I210_I_PHY_ID:
2493 /* Get cable length from PHY Cable Diagnostics Control Reg */
2494 ret_val = phy->ops.read_reg(hw, (0x7 << GS40G_PAGE_SHIFT) +
2495 (I347AT4_PCDL + phy->addr),
2496 &phy_data);
2497 if (ret_val)
2498 return ret_val;
2499
2500 /* Check if the unit of cable length is meters or cm */
2501 ret_val = phy->ops.read_reg(hw, (0x7 << GS40G_PAGE_SHIFT) +
2502 I347AT4_PCDC, &phy_data2);
2503 if (ret_val)
2504 return ret_val;
2505
2506 is_cm = !(phy_data2 & I347AT4_PCDC_CABLE_LENGTH_UNIT);
2507
2508 /* Populate the phy structure with cable length in meters */
2509 phy->min_cable_length = phy_data / (is_cm ? 100 : 1);
2510 phy->max_cable_length = phy_data / (is_cm ? 100 : 1);
2511 phy->cable_length = phy_data / (is_cm ? 100 : 1);
2512 break;
2513 case M88E1543_E_PHY_ID:
2514 case M88E1512_E_PHY_ID:
2515 case M88E1340M_E_PHY_ID:
2516 case I347AT4_E_PHY_ID:
2517 /* Remember the original page select and set it to 7 */
2518 ret_val = phy->ops.read_reg(hw, I347AT4_PAGE_SELECT,
2519 &default_page);
2520 if (ret_val)
2521 return ret_val;
2522
2523 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 0x07);
2524 if (ret_val)
2525 return ret_val;
2526
2527 /* Get cable length from PHY Cable Diagnostics Control Reg */
2528 ret_val = phy->ops.read_reg(hw, (I347AT4_PCDL + phy->addr),
2529 &phy_data);
2530 if (ret_val)
2531 return ret_val;
2532
2533 /* Check if the unit of cable length is meters or cm */
2534 ret_val = phy->ops.read_reg(hw, I347AT4_PCDC, &phy_data2);
2535 if (ret_val)
2536 return ret_val;
2537
2538 is_cm = !(phy_data2 & I347AT4_PCDC_CABLE_LENGTH_UNIT);
2539
2540 /* Populate the phy structure with cable length in meters */
2541 phy->min_cable_length = phy_data / (is_cm ? 100 : 1);
2542 phy->max_cable_length = phy_data / (is_cm ? 100 : 1);
2543 phy->cable_length = phy_data / (is_cm ? 100 : 1);
2544
2545 /* Reset the page select to its original value */
2546 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT,
2547 default_page);
2548 if (ret_val)
2549 return ret_val;
2550 break;
2551
2552 case M88E1112_E_PHY_ID:
2553 /* Remember the original page select and set it to 5 */
2554 ret_val = phy->ops.read_reg(hw, I347AT4_PAGE_SELECT,
2555 &default_page);
2556 if (ret_val)
2557 return ret_val;
2558
2559 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 0x05);
2560 if (ret_val)
2561 return ret_val;
2562
2563 ret_val = phy->ops.read_reg(hw, M88E1112_VCT_DSP_DISTANCE,
2564 &phy_data);
2565 if (ret_val)
2566 return ret_val;
2567
2568 index = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
2569 M88E1000_PSSR_CABLE_LENGTH_SHIFT;
2570
2571 if (index >= M88E1000_CABLE_LENGTH_TABLE_SIZE - 1)
2572 return -E1000_ERR_PHY;
2573
2574 phy->min_cable_length = e1000_m88_cable_length_table[index];
2575 phy->max_cable_length = e1000_m88_cable_length_table[index + 1];
2576
2577 phy->cable_length = (phy->min_cable_length +
2578 phy->max_cable_length) / 2;
2579
2580 /* Reset the page select to its original value */
2581 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT,
2582 default_page);
2583 if (ret_val)
2584 return ret_val;
2585
2586 break;
2587 default:
2588 return -E1000_ERR_PHY;
2589 }
2590
2591 return ret_val;
2592 }
2593
2594 /**
2595 * e1000_get_cable_length_igp_2 - Determine cable length for igp2 PHY
2596 * @hw: pointer to the HW structure
2597 *
2598 * The automatic gain control (agc) normalizes the amplitude of the
2599 * received signal, adjusting for the attenuation produced by the
2600 * cable. By reading the AGC registers, which represent the
2601 * combination of coarse and fine gain value, the value can be put
2602 * into a lookup table to obtain the approximate cable length
2603 * for each channel.
2604 **/
e1000_get_cable_length_igp_2(struct e1000_hw * hw)2605 s32 e1000_get_cable_length_igp_2(struct e1000_hw *hw)
2606 {
2607 struct e1000_phy_info *phy = &hw->phy;
2608 s32 ret_val;
2609 u16 phy_data, i, agc_value = 0;
2610 u16 cur_agc_index, max_agc_index = 0;
2611 u16 min_agc_index = IGP02E1000_CABLE_LENGTH_TABLE_SIZE - 1;
2612 static const u16 agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] = {
2613 IGP02E1000_PHY_AGC_A,
2614 IGP02E1000_PHY_AGC_B,
2615 IGP02E1000_PHY_AGC_C,
2616 IGP02E1000_PHY_AGC_D
2617 };
2618
2619 DEBUGFUNC("e1000_get_cable_length_igp_2");
2620
2621 /* Read the AGC registers for all channels */
2622 for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) {
2623 ret_val = phy->ops.read_reg(hw, agc_reg_array[i], &phy_data);
2624 if (ret_val)
2625 return ret_val;
2626
2627 /* Getting bits 15:9, which represent the combination of
2628 * coarse and fine gain values. The result is a number
2629 * that can be put into the lookup table to obtain the
2630 * approximate cable length.
2631 */
2632 cur_agc_index = ((phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) &
2633 IGP02E1000_AGC_LENGTH_MASK);
2634
2635 /* Array index bound check. */
2636 if ((cur_agc_index >= IGP02E1000_CABLE_LENGTH_TABLE_SIZE) ||
2637 (cur_agc_index == 0))
2638 return -E1000_ERR_PHY;
2639
2640 /* Remove min & max AGC values from calculation. */
2641 if (e1000_igp_2_cable_length_table[min_agc_index] >
2642 e1000_igp_2_cable_length_table[cur_agc_index])
2643 min_agc_index = cur_agc_index;
2644 if (e1000_igp_2_cable_length_table[max_agc_index] <
2645 e1000_igp_2_cable_length_table[cur_agc_index])
2646 max_agc_index = cur_agc_index;
2647
2648 agc_value += e1000_igp_2_cable_length_table[cur_agc_index];
2649 }
2650
2651 agc_value -= (e1000_igp_2_cable_length_table[min_agc_index] +
2652 e1000_igp_2_cable_length_table[max_agc_index]);
2653 agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2);
2654
2655 /* Calculate cable length with the error range of +/- 10 meters. */
2656 phy->min_cable_length = (((agc_value - IGP02E1000_AGC_RANGE) > 0) ?
2657 (agc_value - IGP02E1000_AGC_RANGE) : 0);
2658 phy->max_cable_length = agc_value + IGP02E1000_AGC_RANGE;
2659
2660 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
2661
2662 return E1000_SUCCESS;
2663 }
2664
2665 /**
2666 * e1000_get_phy_info_m88 - Retrieve PHY information
2667 * @hw: pointer to the HW structure
2668 *
2669 * Valid for only copper links. Read the PHY status register (sticky read)
2670 * to verify that link is up. Read the PHY special control register to
2671 * determine the polarity and 10base-T extended distance. Read the PHY
2672 * special status register to determine MDI/MDIx and current speed. If
2673 * speed is 1000, then determine cable length, local and remote receiver.
2674 **/
e1000_get_phy_info_m88(struct e1000_hw * hw)2675 s32 e1000_get_phy_info_m88(struct e1000_hw *hw)
2676 {
2677 struct e1000_phy_info *phy = &hw->phy;
2678 s32 ret_val;
2679 u16 phy_data;
2680 bool link;
2681
2682 DEBUGFUNC("e1000_get_phy_info_m88");
2683
2684 if (phy->media_type != e1000_media_type_copper) {
2685 DEBUGOUT("Phy info is only valid for copper media\n");
2686 return -E1000_ERR_CONFIG;
2687 }
2688
2689 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
2690 if (ret_val)
2691 return ret_val;
2692
2693 if (!link) {
2694 DEBUGOUT("Phy info is only valid if link is up\n");
2695 return -E1000_ERR_CONFIG;
2696 }
2697
2698 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
2699 if (ret_val)
2700 return ret_val;
2701
2702 phy->polarity_correction = !!(phy_data &
2703 M88E1000_PSCR_POLARITY_REVERSAL);
2704
2705 ret_val = e1000_check_polarity_m88(hw);
2706 if (ret_val)
2707 return ret_val;
2708
2709 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
2710 if (ret_val)
2711 return ret_val;
2712
2713 phy->is_mdix = !!(phy_data & M88E1000_PSSR_MDIX);
2714
2715 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) {
2716 ret_val = hw->phy.ops.get_cable_length(hw);
2717 if (ret_val)
2718 return ret_val;
2719
2720 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &phy_data);
2721 if (ret_val)
2722 return ret_val;
2723
2724 phy->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS)
2725 ? e1000_1000t_rx_status_ok
2726 : e1000_1000t_rx_status_not_ok;
2727
2728 phy->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS)
2729 ? e1000_1000t_rx_status_ok
2730 : e1000_1000t_rx_status_not_ok;
2731 } else {
2732 /* Set values to "undefined" */
2733 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2734 phy->local_rx = e1000_1000t_rx_status_undefined;
2735 phy->remote_rx = e1000_1000t_rx_status_undefined;
2736 }
2737
2738 return ret_val;
2739 }
2740
2741 /**
2742 * e1000_get_phy_info_igp - Retrieve igp PHY information
2743 * @hw: pointer to the HW structure
2744 *
2745 * Read PHY status to determine if link is up. If link is up, then
2746 * set/determine 10base-T extended distance and polarity correction. Read
2747 * PHY port status to determine MDI/MDIx and speed. Based on the speed,
2748 * determine on the cable length, local and remote receiver.
2749 **/
e1000_get_phy_info_igp(struct e1000_hw * hw)2750 s32 e1000_get_phy_info_igp(struct e1000_hw *hw)
2751 {
2752 struct e1000_phy_info *phy = &hw->phy;
2753 s32 ret_val;
2754 u16 data;
2755 bool link;
2756
2757 DEBUGFUNC("e1000_get_phy_info_igp");
2758
2759 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
2760 if (ret_val)
2761 return ret_val;
2762
2763 if (!link) {
2764 DEBUGOUT("Phy info is only valid if link is up\n");
2765 return -E1000_ERR_CONFIG;
2766 }
2767
2768 phy->polarity_correction = true;
2769
2770 ret_val = e1000_check_polarity_igp(hw);
2771 if (ret_val)
2772 return ret_val;
2773
2774 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data);
2775 if (ret_val)
2776 return ret_val;
2777
2778 phy->is_mdix = !!(data & IGP01E1000_PSSR_MDIX);
2779
2780 if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
2781 IGP01E1000_PSSR_SPEED_1000MBPS) {
2782 ret_val = phy->ops.get_cable_length(hw);
2783 if (ret_val)
2784 return ret_val;
2785
2786 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data);
2787 if (ret_val)
2788 return ret_val;
2789
2790 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS)
2791 ? e1000_1000t_rx_status_ok
2792 : e1000_1000t_rx_status_not_ok;
2793
2794 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS)
2795 ? e1000_1000t_rx_status_ok
2796 : e1000_1000t_rx_status_not_ok;
2797 } else {
2798 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2799 phy->local_rx = e1000_1000t_rx_status_undefined;
2800 phy->remote_rx = e1000_1000t_rx_status_undefined;
2801 }
2802
2803 return ret_val;
2804 }
2805
2806 /**
2807 * e1000_get_phy_info_ife - Retrieves various IFE PHY states
2808 * @hw: pointer to the HW structure
2809 *
2810 * Populates "phy" structure with various feature states.
2811 **/
e1000_get_phy_info_ife(struct e1000_hw * hw)2812 s32 e1000_get_phy_info_ife(struct e1000_hw *hw)
2813 {
2814 struct e1000_phy_info *phy = &hw->phy;
2815 s32 ret_val;
2816 u16 data;
2817 bool link;
2818
2819 DEBUGFUNC("e1000_get_phy_info_ife");
2820
2821 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
2822 if (ret_val)
2823 return ret_val;
2824
2825 if (!link) {
2826 DEBUGOUT("Phy info is only valid if link is up\n");
2827 return -E1000_ERR_CONFIG;
2828 }
2829
2830 ret_val = phy->ops.read_reg(hw, IFE_PHY_SPECIAL_CONTROL, &data);
2831 if (ret_val)
2832 return ret_val;
2833 phy->polarity_correction = !(data & IFE_PSC_AUTO_POLARITY_DISABLE);
2834
2835 if (phy->polarity_correction) {
2836 ret_val = e1000_check_polarity_ife(hw);
2837 if (ret_val)
2838 return ret_val;
2839 } else {
2840 /* Polarity is forced */
2841 phy->cable_polarity = ((data & IFE_PSC_FORCE_POLARITY)
2842 ? e1000_rev_polarity_reversed
2843 : e1000_rev_polarity_normal);
2844 }
2845
2846 ret_val = phy->ops.read_reg(hw, IFE_PHY_MDIX_CONTROL, &data);
2847 if (ret_val)
2848 return ret_val;
2849
2850 phy->is_mdix = !!(data & IFE_PMC_MDIX_STATUS);
2851
2852 /* The following parameters are undefined for 10/100 operation. */
2853 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2854 phy->local_rx = e1000_1000t_rx_status_undefined;
2855 phy->remote_rx = e1000_1000t_rx_status_undefined;
2856
2857 return E1000_SUCCESS;
2858 }
2859
2860 /**
2861 * e1000_phy_sw_reset_generic - PHY software reset
2862 * @hw: pointer to the HW structure
2863 *
2864 * Does a software reset of the PHY by reading the PHY control register and
2865 * setting/write the control register reset bit to the PHY.
2866 **/
e1000_phy_sw_reset_generic(struct e1000_hw * hw)2867 s32 e1000_phy_sw_reset_generic(struct e1000_hw *hw)
2868 {
2869 s32 ret_val;
2870 u16 phy_ctrl;
2871
2872 DEBUGFUNC("e1000_phy_sw_reset_generic");
2873
2874 if (!hw->phy.ops.read_reg)
2875 return E1000_SUCCESS;
2876
2877 ret_val = hw->phy.ops.read_reg(hw, PHY_CONTROL, &phy_ctrl);
2878 if (ret_val)
2879 return ret_val;
2880
2881 phy_ctrl |= MII_CR_RESET;
2882 ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL, phy_ctrl);
2883 if (ret_val)
2884 return ret_val;
2885
2886 usec_delay(1);
2887
2888 return ret_val;
2889 }
2890
2891 /**
2892 * e1000_phy_hw_reset_generic - PHY hardware reset
2893 * @hw: pointer to the HW structure
2894 *
2895 * Verify the reset block is not blocking us from resetting. Acquire
2896 * semaphore (if necessary) and read/set/write the device control reset
2897 * bit in the PHY. Wait the appropriate delay time for the device to
2898 * reset and release the semaphore (if necessary).
2899 **/
e1000_phy_hw_reset_generic(struct e1000_hw * hw)2900 s32 e1000_phy_hw_reset_generic(struct e1000_hw *hw)
2901 {
2902 struct e1000_phy_info *phy = &hw->phy;
2903 s32 ret_val;
2904 u32 ctrl;
2905
2906 DEBUGFUNC("e1000_phy_hw_reset_generic");
2907
2908 if (phy->ops.check_reset_block) {
2909 ret_val = phy->ops.check_reset_block(hw);
2910 if (ret_val)
2911 return E1000_SUCCESS;
2912 }
2913
2914 ret_val = phy->ops.acquire(hw);
2915 if (ret_val)
2916 return ret_val;
2917
2918 ctrl = E1000_READ_REG(hw, E1000_CTRL);
2919 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_PHY_RST);
2920 E1000_WRITE_FLUSH(hw);
2921
2922 usec_delay(phy->reset_delay_us);
2923
2924 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
2925 E1000_WRITE_FLUSH(hw);
2926
2927 usec_delay(150);
2928
2929 phy->ops.release(hw);
2930
2931 return phy->ops.get_cfg_done(hw);
2932 }
2933
2934 /**
2935 * e1000_get_cfg_done_generic - Generic configuration done
2936 * @hw: pointer to the HW structure
2937 *
2938 * Generic function to wait 10 milli-seconds for configuration to complete
2939 * and return success.
2940 **/
e1000_get_cfg_done_generic(struct e1000_hw E1000_UNUSEDARG * hw)2941 s32 e1000_get_cfg_done_generic(struct e1000_hw E1000_UNUSEDARG *hw)
2942 {
2943 DEBUGFUNC("e1000_get_cfg_done_generic");
2944
2945 msec_delay_irq(10);
2946
2947 return E1000_SUCCESS;
2948 }
2949
2950 /**
2951 * e1000_phy_init_script_igp3 - Inits the IGP3 PHY
2952 * @hw: pointer to the HW structure
2953 *
2954 * Initializes a Intel Gigabit PHY3 when an EEPROM is not present.
2955 **/
e1000_phy_init_script_igp3(struct e1000_hw * hw)2956 s32 e1000_phy_init_script_igp3(struct e1000_hw *hw)
2957 {
2958 DEBUGOUT("Running IGP 3 PHY init script\n");
2959
2960 /* PHY init IGP 3 */
2961 /* Enable rise/fall, 10-mode work in class-A */
2962 hw->phy.ops.write_reg(hw, 0x2F5B, 0x9018);
2963 /* Remove all caps from Replica path filter */
2964 hw->phy.ops.write_reg(hw, 0x2F52, 0x0000);
2965 /* Bias trimming for ADC, AFE and Driver (Default) */
2966 hw->phy.ops.write_reg(hw, 0x2FB1, 0x8B24);
2967 /* Increase Hybrid poly bias */
2968 hw->phy.ops.write_reg(hw, 0x2FB2, 0xF8F0);
2969 /* Add 4% to Tx amplitude in Gig mode */
2970 hw->phy.ops.write_reg(hw, 0x2010, 0x10B0);
2971 /* Disable trimming (TTT) */
2972 hw->phy.ops.write_reg(hw, 0x2011, 0x0000);
2973 /* Poly DC correction to 94.6% + 2% for all channels */
2974 hw->phy.ops.write_reg(hw, 0x20DD, 0x249A);
2975 /* ABS DC correction to 95.9% */
2976 hw->phy.ops.write_reg(hw, 0x20DE, 0x00D3);
2977 /* BG temp curve trim */
2978 hw->phy.ops.write_reg(hw, 0x28B4, 0x04CE);
2979 /* Increasing ADC OPAMP stage 1 currents to max */
2980 hw->phy.ops.write_reg(hw, 0x2F70, 0x29E4);
2981 /* Force 1000 ( required for enabling PHY regs configuration) */
2982 hw->phy.ops.write_reg(hw, 0x0000, 0x0140);
2983 /* Set upd_freq to 6 */
2984 hw->phy.ops.write_reg(hw, 0x1F30, 0x1606);
2985 /* Disable NPDFE */
2986 hw->phy.ops.write_reg(hw, 0x1F31, 0xB814);
2987 /* Disable adaptive fixed FFE (Default) */
2988 hw->phy.ops.write_reg(hw, 0x1F35, 0x002A);
2989 /* Enable FFE hysteresis */
2990 hw->phy.ops.write_reg(hw, 0x1F3E, 0x0067);
2991 /* Fixed FFE for short cable lengths */
2992 hw->phy.ops.write_reg(hw, 0x1F54, 0x0065);
2993 /* Fixed FFE for medium cable lengths */
2994 hw->phy.ops.write_reg(hw, 0x1F55, 0x002A);
2995 /* Fixed FFE for long cable lengths */
2996 hw->phy.ops.write_reg(hw, 0x1F56, 0x002A);
2997 /* Enable Adaptive Clip Threshold */
2998 hw->phy.ops.write_reg(hw, 0x1F72, 0x3FB0);
2999 /* AHT reset limit to 1 */
3000 hw->phy.ops.write_reg(hw, 0x1F76, 0xC0FF);
3001 /* Set AHT master delay to 127 msec */
3002 hw->phy.ops.write_reg(hw, 0x1F77, 0x1DEC);
3003 /* Set scan bits for AHT */
3004 hw->phy.ops.write_reg(hw, 0x1F78, 0xF9EF);
3005 /* Set AHT Preset bits */
3006 hw->phy.ops.write_reg(hw, 0x1F79, 0x0210);
3007 /* Change integ_factor of channel A to 3 */
3008 hw->phy.ops.write_reg(hw, 0x1895, 0x0003);
3009 /* Change prop_factor of channels BCD to 8 */
3010 hw->phy.ops.write_reg(hw, 0x1796, 0x0008);
3011 /* Change cg_icount + enable integbp for channels BCD */
3012 hw->phy.ops.write_reg(hw, 0x1798, 0xD008);
3013 /* Change cg_icount + enable integbp + change prop_factor_master
3014 * to 8 for channel A
3015 */
3016 hw->phy.ops.write_reg(hw, 0x1898, 0xD918);
3017 /* Disable AHT in Slave mode on channel A */
3018 hw->phy.ops.write_reg(hw, 0x187A, 0x0800);
3019 /* Enable LPLU and disable AN to 1000 in non-D0a states,
3020 * Enable SPD+B2B
3021 */
3022 hw->phy.ops.write_reg(hw, 0x0019, 0x008D);
3023 /* Enable restart AN on an1000_dis change */
3024 hw->phy.ops.write_reg(hw, 0x001B, 0x2080);
3025 /* Enable wh_fifo read clock in 10/100 modes */
3026 hw->phy.ops.write_reg(hw, 0x0014, 0x0045);
3027 /* Restart AN, Speed selection is 1000 */
3028 hw->phy.ops.write_reg(hw, 0x0000, 0x1340);
3029
3030 return E1000_SUCCESS;
3031 }
3032
3033 /**
3034 * e1000_get_phy_type_from_id - Get PHY type from id
3035 * @phy_id: phy_id read from the phy
3036 *
3037 * Returns the phy type from the id.
3038 **/
e1000_get_phy_type_from_id(u32 phy_id)3039 enum e1000_phy_type e1000_get_phy_type_from_id(u32 phy_id)
3040 {
3041 enum e1000_phy_type phy_type = e1000_phy_unknown;
3042
3043 switch (phy_id) {
3044 case M88E1000_I_PHY_ID:
3045 case M88E1000_E_PHY_ID:
3046 case M88E1111_I_PHY_ID:
3047 case M88E1011_I_PHY_ID:
3048 case M88E1543_E_PHY_ID:
3049 case M88E1512_E_PHY_ID:
3050 case I347AT4_E_PHY_ID:
3051 case M88E1112_E_PHY_ID:
3052 case M88E1340M_E_PHY_ID:
3053 phy_type = e1000_phy_m88;
3054 break;
3055 case IGP01E1000_I_PHY_ID: /* IGP 1 & 2 share this */
3056 phy_type = e1000_phy_igp_2;
3057 break;
3058 case GG82563_E_PHY_ID:
3059 phy_type = e1000_phy_gg82563;
3060 break;
3061 case IGP03E1000_E_PHY_ID:
3062 phy_type = e1000_phy_igp_3;
3063 break;
3064 case IFE_E_PHY_ID:
3065 case IFE_PLUS_E_PHY_ID:
3066 case IFE_C_E_PHY_ID:
3067 phy_type = e1000_phy_ife;
3068 break;
3069 case BME1000_E_PHY_ID:
3070 case BME1000_E_PHY_ID_R2:
3071 phy_type = e1000_phy_bm;
3072 break;
3073 case I82578_E_PHY_ID:
3074 phy_type = e1000_phy_82578;
3075 break;
3076 case I82577_E_PHY_ID:
3077 phy_type = e1000_phy_82577;
3078 break;
3079 case I82579_E_PHY_ID:
3080 phy_type = e1000_phy_82579;
3081 break;
3082 case I217_E_PHY_ID:
3083 phy_type = e1000_phy_i217;
3084 break;
3085 case I82580_I_PHY_ID:
3086 phy_type = e1000_phy_82580;
3087 break;
3088 case I210_I_PHY_ID:
3089 phy_type = e1000_phy_i210;
3090 break;
3091 default:
3092 phy_type = e1000_phy_unknown;
3093 break;
3094 }
3095 return phy_type;
3096 }
3097
3098 /**
3099 * e1000_determine_phy_address - Determines PHY address.
3100 * @hw: pointer to the HW structure
3101 *
3102 * This uses a trial and error method to loop through possible PHY
3103 * addresses. It tests each by reading the PHY ID registers and
3104 * checking for a match.
3105 **/
e1000_determine_phy_address(struct e1000_hw * hw)3106 s32 e1000_determine_phy_address(struct e1000_hw *hw)
3107 {
3108 u32 phy_addr = 0;
3109 u32 i;
3110 enum e1000_phy_type phy_type = e1000_phy_unknown;
3111
3112 hw->phy.id = phy_type;
3113
3114 for (phy_addr = 0; phy_addr < E1000_MAX_PHY_ADDR; phy_addr++) {
3115 hw->phy.addr = phy_addr;
3116 i = 0;
3117
3118 do {
3119 e1000_get_phy_id(hw);
3120 phy_type = e1000_get_phy_type_from_id(hw->phy.id);
3121
3122 /* If phy_type is valid, break - we found our
3123 * PHY address
3124 */
3125 if (phy_type != e1000_phy_unknown)
3126 return E1000_SUCCESS;
3127
3128 msec_delay(1);
3129 i++;
3130 } while (i < 10);
3131 }
3132
3133 return -E1000_ERR_PHY_TYPE;
3134 }
3135
3136 /**
3137 * e1000_get_phy_addr_for_bm_page - Retrieve PHY page address
3138 * @page: page to access
3139 * @reg: register to access
3140 *
3141 * Returns the phy address for the page requested.
3142 **/
e1000_get_phy_addr_for_bm_page(u32 page,u32 reg)3143 static u32 e1000_get_phy_addr_for_bm_page(u32 page, u32 reg)
3144 {
3145 u32 phy_addr = 2;
3146
3147 if ((page >= 768) || (page == 0 && reg == 25) || (reg == 31))
3148 phy_addr = 1;
3149
3150 return phy_addr;
3151 }
3152
3153 /**
3154 * e1000_write_phy_reg_bm - Write BM PHY register
3155 * @hw: pointer to the HW structure
3156 * @offset: register offset to write to
3157 * @data: data to write at register offset
3158 *
3159 * Acquires semaphore, if necessary, then writes the data to PHY register
3160 * at the offset. Release any acquired semaphores before exiting.
3161 **/
e1000_write_phy_reg_bm(struct e1000_hw * hw,u32 offset,u16 data)3162 s32 e1000_write_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 data)
3163 {
3164 s32 ret_val;
3165 u32 page = offset >> IGP_PAGE_SHIFT;
3166
3167 DEBUGFUNC("e1000_write_phy_reg_bm");
3168
3169 ret_val = hw->phy.ops.acquire(hw);
3170 if (ret_val)
3171 return ret_val;
3172
3173 /* Page 800 works differently than the rest so it has its own func */
3174 if (page == BM_WUC_PAGE) {
3175 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data,
3176 false, false);
3177 goto release;
3178 }
3179
3180 hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset);
3181
3182 if (offset > MAX_PHY_MULTI_PAGE_REG) {
3183 u32 page_shift, page_select;
3184
3185 /* Page select is register 31 for phy address 1 and 22 for
3186 * phy address 2 and 3. Page select is shifted only for
3187 * phy address 1.
3188 */
3189 if (hw->phy.addr == 1) {
3190 page_shift = IGP_PAGE_SHIFT;
3191 page_select = IGP01E1000_PHY_PAGE_SELECT;
3192 } else {
3193 page_shift = 0;
3194 page_select = BM_PHY_PAGE_SELECT;
3195 }
3196
3197 /* Page is shifted left, PHY expects (page x 32) */
3198 ret_val = e1000_write_phy_reg_mdic(hw, page_select,
3199 (page << page_shift));
3200 if (ret_val)
3201 goto release;
3202 }
3203
3204 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
3205 data);
3206
3207 release:
3208 hw->phy.ops.release(hw);
3209 return ret_val;
3210 }
3211
3212 /**
3213 * e1000_read_phy_reg_bm - Read BM PHY register
3214 * @hw: pointer to the HW structure
3215 * @offset: register offset to be read
3216 * @data: pointer to the read data
3217 *
3218 * Acquires semaphore, if necessary, then reads the PHY register at offset
3219 * and storing the retrieved information in data. Release any acquired
3220 * semaphores before exiting.
3221 **/
e1000_read_phy_reg_bm(struct e1000_hw * hw,u32 offset,u16 * data)3222 s32 e1000_read_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 *data)
3223 {
3224 s32 ret_val;
3225 u32 page = offset >> IGP_PAGE_SHIFT;
3226
3227 DEBUGFUNC("e1000_read_phy_reg_bm");
3228
3229 ret_val = hw->phy.ops.acquire(hw);
3230 if (ret_val)
3231 return ret_val;
3232
3233 /* Page 800 works differently than the rest so it has its own func */
3234 if (page == BM_WUC_PAGE) {
3235 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data,
3236 true, false);
3237 goto release;
3238 }
3239
3240 hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset);
3241
3242 if (offset > MAX_PHY_MULTI_PAGE_REG) {
3243 u32 page_shift, page_select;
3244
3245 /* Page select is register 31 for phy address 1 and 22 for
3246 * phy address 2 and 3. Page select is shifted only for
3247 * phy address 1.
3248 */
3249 if (hw->phy.addr == 1) {
3250 page_shift = IGP_PAGE_SHIFT;
3251 page_select = IGP01E1000_PHY_PAGE_SELECT;
3252 } else {
3253 page_shift = 0;
3254 page_select = BM_PHY_PAGE_SELECT;
3255 }
3256
3257 /* Page is shifted left, PHY expects (page x 32) */
3258 ret_val = e1000_write_phy_reg_mdic(hw, page_select,
3259 (page << page_shift));
3260 if (ret_val)
3261 goto release;
3262 }
3263
3264 ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
3265 data);
3266 release:
3267 hw->phy.ops.release(hw);
3268 return ret_val;
3269 }
3270
3271 /**
3272 * e1000_read_phy_reg_bm2 - Read BM PHY register
3273 * @hw: pointer to the HW structure
3274 * @offset: register offset to be read
3275 * @data: pointer to the read data
3276 *
3277 * Acquires semaphore, if necessary, then reads the PHY register at offset
3278 * and storing the retrieved information in data. Release any acquired
3279 * semaphores before exiting.
3280 **/
e1000_read_phy_reg_bm2(struct e1000_hw * hw,u32 offset,u16 * data)3281 s32 e1000_read_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 *data)
3282 {
3283 s32 ret_val;
3284 u16 page = (u16)(offset >> IGP_PAGE_SHIFT);
3285
3286 DEBUGFUNC("e1000_read_phy_reg_bm2");
3287
3288 ret_val = hw->phy.ops.acquire(hw);
3289 if (ret_val)
3290 return ret_val;
3291
3292 /* Page 800 works differently than the rest so it has its own func */
3293 if (page == BM_WUC_PAGE) {
3294 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data,
3295 true, false);
3296 goto release;
3297 }
3298
3299 hw->phy.addr = 1;
3300
3301 if (offset > MAX_PHY_MULTI_PAGE_REG) {
3302 /* Page is shifted left, PHY expects (page x 32) */
3303 ret_val = e1000_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT,
3304 page);
3305
3306 if (ret_val)
3307 goto release;
3308 }
3309
3310 ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
3311 data);
3312 release:
3313 hw->phy.ops.release(hw);
3314 return ret_val;
3315 }
3316
3317 /**
3318 * e1000_write_phy_reg_bm2 - Write BM PHY register
3319 * @hw: pointer to the HW structure
3320 * @offset: register offset to write to
3321 * @data: data to write at register offset
3322 *
3323 * Acquires semaphore, if necessary, then writes the data to PHY register
3324 * at the offset. Release any acquired semaphores before exiting.
3325 **/
e1000_write_phy_reg_bm2(struct e1000_hw * hw,u32 offset,u16 data)3326 s32 e1000_write_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 data)
3327 {
3328 s32 ret_val;
3329 u16 page = (u16)(offset >> IGP_PAGE_SHIFT);
3330
3331 DEBUGFUNC("e1000_write_phy_reg_bm2");
3332
3333 ret_val = hw->phy.ops.acquire(hw);
3334 if (ret_val)
3335 return ret_val;
3336
3337 /* Page 800 works differently than the rest so it has its own func */
3338 if (page == BM_WUC_PAGE) {
3339 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data,
3340 false, false);
3341 goto release;
3342 }
3343
3344 hw->phy.addr = 1;
3345
3346 if (offset > MAX_PHY_MULTI_PAGE_REG) {
3347 /* Page is shifted left, PHY expects (page x 32) */
3348 ret_val = e1000_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT,
3349 page);
3350
3351 if (ret_val)
3352 goto release;
3353 }
3354
3355 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
3356 data);
3357
3358 release:
3359 hw->phy.ops.release(hw);
3360 return ret_val;
3361 }
3362
3363 /**
3364 * e1000_enable_phy_wakeup_reg_access_bm - enable access to BM wakeup registers
3365 * @hw: pointer to the HW structure
3366 * @phy_reg: pointer to store original contents of BM_WUC_ENABLE_REG
3367 *
3368 * Assumes semaphore already acquired and phy_reg points to a valid memory
3369 * address to store contents of the BM_WUC_ENABLE_REG register.
3370 **/
e1000_enable_phy_wakeup_reg_access_bm(struct e1000_hw * hw,u16 * phy_reg)3371 s32 e1000_enable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg)
3372 {
3373 s32 ret_val;
3374 u16 temp;
3375
3376 DEBUGFUNC("e1000_enable_phy_wakeup_reg_access_bm");
3377
3378 if (!phy_reg)
3379 return -E1000_ERR_PARAM;
3380
3381 /* All page select, port ctrl and wakeup registers use phy address 1 */
3382 hw->phy.addr = 1;
3383
3384 /* Select Port Control Registers page */
3385 ret_val = e1000_set_page_igp(hw, (BM_PORT_CTRL_PAGE << IGP_PAGE_SHIFT));
3386 if (ret_val) {
3387 DEBUGOUT("Could not set Port Control page\n");
3388 return ret_val;
3389 }
3390
3391 ret_val = e1000_read_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, phy_reg);
3392 if (ret_val) {
3393 DEBUGOUT2("Could not read PHY register %d.%d\n",
3394 BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG);
3395 return ret_val;
3396 }
3397
3398 /* Enable both PHY wakeup mode and Wakeup register page writes.
3399 * Prevent a power state change by disabling ME and Host PHY wakeup.
3400 */
3401 temp = *phy_reg;
3402 temp |= BM_WUC_ENABLE_BIT;
3403 temp &= ~(BM_WUC_ME_WU_BIT | BM_WUC_HOST_WU_BIT);
3404
3405 ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, temp);
3406 if (ret_val) {
3407 DEBUGOUT2("Could not write PHY register %d.%d\n",
3408 BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG);
3409 return ret_val;
3410 }
3411
3412 /* Select Host Wakeup Registers page - caller now able to write
3413 * registers on the Wakeup registers page
3414 */
3415 return e1000_set_page_igp(hw, (BM_WUC_PAGE << IGP_PAGE_SHIFT));
3416 }
3417
3418 /**
3419 * e1000_disable_phy_wakeup_reg_access_bm - disable access to BM wakeup regs
3420 * @hw: pointer to the HW structure
3421 * @phy_reg: pointer to original contents of BM_WUC_ENABLE_REG
3422 *
3423 * Restore BM_WUC_ENABLE_REG to its original value.
3424 *
3425 * Assumes semaphore already acquired and *phy_reg is the contents of the
3426 * BM_WUC_ENABLE_REG before register(s) on BM_WUC_PAGE were accessed by
3427 * caller.
3428 **/
e1000_disable_phy_wakeup_reg_access_bm(struct e1000_hw * hw,u16 * phy_reg)3429 s32 e1000_disable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg)
3430 {
3431 s32 ret_val;
3432
3433 DEBUGFUNC("e1000_disable_phy_wakeup_reg_access_bm");
3434
3435 if (!phy_reg)
3436 return -E1000_ERR_PARAM;
3437
3438 /* Select Port Control Registers page */
3439 ret_val = e1000_set_page_igp(hw, (BM_PORT_CTRL_PAGE << IGP_PAGE_SHIFT));
3440 if (ret_val) {
3441 DEBUGOUT("Could not set Port Control page\n");
3442 return ret_val;
3443 }
3444
3445 /* Restore 769.17 to its original value */
3446 ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, *phy_reg);
3447 if (ret_val)
3448 DEBUGOUT2("Could not restore PHY register %d.%d\n",
3449 BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG);
3450
3451 return ret_val;
3452 }
3453
3454 /**
3455 * e1000_access_phy_wakeup_reg_bm - Read/write BM PHY wakeup register
3456 * @hw: pointer to the HW structure
3457 * @offset: register offset to be read or written
3458 * @data: pointer to the data to read or write
3459 * @read: determines if operation is read or write
3460 * @page_set: BM_WUC_PAGE already set and access enabled
3461 *
3462 * Read the PHY register at offset and store the retrieved information in
3463 * data, or write data to PHY register at offset. Note the procedure to
3464 * access the PHY wakeup registers is different than reading the other PHY
3465 * registers. It works as such:
3466 * 1) Set 769.17.2 (page 769, register 17, bit 2) = 1
3467 * 2) Set page to 800 for host (801 if we were manageability)
3468 * 3) Write the address using the address opcode (0x11)
3469 * 4) Read or write the data using the data opcode (0x12)
3470 * 5) Restore 769.17.2 to its original value
3471 *
3472 * Steps 1 and 2 are done by e1000_enable_phy_wakeup_reg_access_bm() and
3473 * step 5 is done by e1000_disable_phy_wakeup_reg_access_bm().
3474 *
3475 * Assumes semaphore is already acquired. When page_set==true, assumes
3476 * the PHY page is set to BM_WUC_PAGE (i.e. a function in the call stack
3477 * is responsible for calls to e1000_[enable|disable]_phy_wakeup_reg_bm()).
3478 **/
e1000_access_phy_wakeup_reg_bm(struct e1000_hw * hw,u32 offset,u16 * data,bool read,bool page_set)3479 static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset,
3480 u16 *data, bool read, bool page_set)
3481 {
3482 s32 ret_val;
3483 u16 reg = BM_PHY_REG_NUM(offset);
3484 u16 page = BM_PHY_REG_PAGE(offset);
3485 u16 phy_reg = 0;
3486
3487 DEBUGFUNC("e1000_access_phy_wakeup_reg_bm");
3488
3489 /* Gig must be disabled for MDIO accesses to Host Wakeup reg page */
3490 if ((hw->mac.type == e1000_pchlan) &&
3491 (!(E1000_READ_REG(hw, E1000_PHY_CTRL) & E1000_PHY_CTRL_GBE_DISABLE)))
3492 DEBUGOUT1("Attempting to access page %d while gig enabled.\n",
3493 page);
3494
3495 if (!page_set) {
3496 /* Enable access to PHY wakeup registers */
3497 ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);
3498 if (ret_val) {
3499 DEBUGOUT("Could not enable PHY wakeup reg access\n");
3500 return ret_val;
3501 }
3502 }
3503
3504 DEBUGOUT2("Accessing PHY page %d reg 0x%x\n", page, reg);
3505
3506 /* Write the Wakeup register page offset value using opcode 0x11 */
3507 ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_ADDRESS_OPCODE, reg);
3508 if (ret_val) {
3509 DEBUGOUT1("Could not write address opcode to page %d\n", page);
3510 return ret_val;
3511 }
3512
3513 if (read) {
3514 /* Read the Wakeup register page value using opcode 0x12 */
3515 ret_val = e1000_read_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE,
3516 data);
3517 } else {
3518 /* Write the Wakeup register page value using opcode 0x12 */
3519 ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE,
3520 *data);
3521 }
3522
3523 if (ret_val) {
3524 DEBUGOUT2("Could not access PHY reg %d.%d\n", page, reg);
3525 return ret_val;
3526 }
3527
3528 if (!page_set)
3529 ret_val = e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg);
3530
3531 return ret_val;
3532 }
3533
3534 /**
3535 * e1000_power_up_phy_copper - Restore copper link in case of PHY power down
3536 * @hw: pointer to the HW structure
3537 *
3538 * In the case of a PHY power down to save power, or to turn off link during a
3539 * driver unload, or wake on lan is not enabled, restore the link to previous
3540 * settings.
3541 **/
e1000_power_up_phy_copper(struct e1000_hw * hw)3542 void e1000_power_up_phy_copper(struct e1000_hw *hw)
3543 {
3544 s32 ret_val;
3545 u16 mii_reg = 0;
3546
3547 /* The PHY will retain its settings across a power down/up cycle */
3548 ret_val = hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg);
3549 if (ret_val) {
3550 DEBUGOUT("Error reading PHY control register\n");
3551 return;
3552 }
3553 mii_reg &= ~MII_CR_POWER_DOWN;
3554 hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg);
3555 }
3556
3557 /**
3558 * e1000_power_down_phy_copper - Restore copper link in case of PHY power down
3559 * @hw: pointer to the HW structure
3560 *
3561 * In the case of a PHY power down to save power, or to turn off link during a
3562 * driver unload, or wake on lan is not enabled, restore the link to previous
3563 * settings.
3564 **/
e1000_power_down_phy_copper(struct e1000_hw * hw)3565 void e1000_power_down_phy_copper(struct e1000_hw *hw)
3566 {
3567 s32 ret_val;
3568 u16 mii_reg = 0;
3569
3570 /* The PHY will retain its settings across a power down/up cycle */
3571 ret_val = hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg);
3572 if (ret_val) {
3573 DEBUGOUT("Error reading PHY control register\n");
3574 return;
3575 }
3576 mii_reg |= MII_CR_POWER_DOWN;
3577 hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg);
3578 msec_delay(1);
3579 }
3580
3581 /**
3582 * __e1000_read_phy_reg_hv - Read HV PHY register
3583 * @hw: pointer to the HW structure
3584 * @offset: register offset to be read
3585 * @data: pointer to the read data
3586 * @locked: semaphore has already been acquired or not
3587 * @page_set: BM_WUC_PAGE already set and access enabled
3588 *
3589 * Acquires semaphore, if necessary, then reads the PHY register at offset
3590 * and stores the retrieved information in data. Release any acquired
3591 * semaphore before exiting.
3592 **/
__e1000_read_phy_reg_hv(struct e1000_hw * hw,u32 offset,u16 * data,bool locked,bool page_set)3593 static s32 __e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data,
3594 bool locked, bool page_set)
3595 {
3596 s32 ret_val;
3597 u16 page = BM_PHY_REG_PAGE(offset);
3598 u16 reg = BM_PHY_REG_NUM(offset);
3599 u32 phy_addr = hw->phy.addr = e1000_get_phy_addr_for_hv_page(page);
3600
3601 DEBUGFUNC("__e1000_read_phy_reg_hv");
3602
3603 if (!locked) {
3604 ret_val = hw->phy.ops.acquire(hw);
3605 if (ret_val)
3606 return ret_val;
3607 }
3608 /* Page 800 works differently than the rest so it has its own func */
3609 if (page == BM_WUC_PAGE) {
3610 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data,
3611 true, page_set);
3612 goto out;
3613 }
3614
3615 if (page > 0 && page < HV_INTC_FC_PAGE_START) {
3616 ret_val = e1000_access_phy_debug_regs_hv(hw, offset,
3617 data, true);
3618 goto out;
3619 }
3620
3621 if (!page_set) {
3622 if (page == HV_INTC_FC_PAGE_START)
3623 page = 0;
3624
3625 if (reg > MAX_PHY_MULTI_PAGE_REG) {
3626 /* Page is shifted left, PHY expects (page x 32) */
3627 ret_val = e1000_set_page_igp(hw,
3628 (page << IGP_PAGE_SHIFT));
3629
3630 hw->phy.addr = phy_addr;
3631
3632 if (ret_val)
3633 goto out;
3634 }
3635 }
3636
3637 DEBUGOUT3("reading PHY page %d (or 0x%x shifted) reg 0x%x\n", page,
3638 page << IGP_PAGE_SHIFT, reg);
3639
3640 ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg,
3641 data);
3642 out:
3643 if (!locked)
3644 hw->phy.ops.release(hw);
3645
3646 return ret_val;
3647 }
3648
3649 /**
3650 * e1000_read_phy_reg_hv - Read HV PHY register
3651 * @hw: pointer to the HW structure
3652 * @offset: register offset to be read
3653 * @data: pointer to the read data
3654 *
3655 * Acquires semaphore then reads the PHY register at offset and stores
3656 * the retrieved information in data. Release the acquired semaphore
3657 * before exiting.
3658 **/
e1000_read_phy_reg_hv(struct e1000_hw * hw,u32 offset,u16 * data)3659 s32 e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data)
3660 {
3661 return __e1000_read_phy_reg_hv(hw, offset, data, false, false);
3662 }
3663
3664 /**
3665 * e1000_read_phy_reg_hv_locked - Read HV PHY register
3666 * @hw: pointer to the HW structure
3667 * @offset: register offset to be read
3668 * @data: pointer to the read data
3669 *
3670 * Reads the PHY register at offset and stores the retrieved information
3671 * in data. Assumes semaphore already acquired.
3672 **/
e1000_read_phy_reg_hv_locked(struct e1000_hw * hw,u32 offset,u16 * data)3673 s32 e1000_read_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 *data)
3674 {
3675 return __e1000_read_phy_reg_hv(hw, offset, data, true, false);
3676 }
3677
3678 /**
3679 * e1000_read_phy_reg_page_hv - Read HV PHY register
3680 * @hw: pointer to the HW structure
3681 * @offset: register offset to write to
3682 * @data: data to write at register offset
3683 *
3684 * Reads the PHY register at offset and stores the retrieved information
3685 * in data. Assumes semaphore already acquired and page already set.
3686 **/
e1000_read_phy_reg_page_hv(struct e1000_hw * hw,u32 offset,u16 * data)3687 s32 e1000_read_phy_reg_page_hv(struct e1000_hw *hw, u32 offset, u16 *data)
3688 {
3689 return __e1000_read_phy_reg_hv(hw, offset, data, true, true);
3690 }
3691
3692 /**
3693 * __e1000_write_phy_reg_hv - Write HV PHY register
3694 * @hw: pointer to the HW structure
3695 * @offset: register offset to write to
3696 * @data: data to write at register offset
3697 * @locked: semaphore has already been acquired or not
3698 * @page_set: BM_WUC_PAGE already set and access enabled
3699 *
3700 * Acquires semaphore, if necessary, then writes the data to PHY register
3701 * at the offset. Release any acquired semaphores before exiting.
3702 **/
__e1000_write_phy_reg_hv(struct e1000_hw * hw,u32 offset,u16 data,bool locked,bool page_set)3703 static s32 __e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data,
3704 bool locked, bool page_set)
3705 {
3706 s32 ret_val;
3707 u16 page = BM_PHY_REG_PAGE(offset);
3708 u16 reg = BM_PHY_REG_NUM(offset);
3709 u32 phy_addr = hw->phy.addr = e1000_get_phy_addr_for_hv_page(page);
3710
3711 DEBUGFUNC("__e1000_write_phy_reg_hv");
3712
3713 if (!locked) {
3714 ret_val = hw->phy.ops.acquire(hw);
3715 if (ret_val)
3716 return ret_val;
3717 }
3718 /* Page 800 works differently than the rest so it has its own func */
3719 if (page == BM_WUC_PAGE) {
3720 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data,
3721 false, page_set);
3722 goto out;
3723 }
3724
3725 if (page > 0 && page < HV_INTC_FC_PAGE_START) {
3726 ret_val = e1000_access_phy_debug_regs_hv(hw, offset,
3727 &data, false);
3728 goto out;
3729 }
3730
3731 if (!page_set) {
3732 if (page == HV_INTC_FC_PAGE_START)
3733 page = 0;
3734
3735 /* Workaround MDIO accesses being disabled after entering IEEE
3736 * Power Down (when bit 11 of the PHY Control register is set)
3737 */
3738 if ((hw->phy.type == e1000_phy_82578) &&
3739 (hw->phy.revision >= 1) &&
3740 (hw->phy.addr == 2) &&
3741 !(MAX_PHY_REG_ADDRESS & reg) &&
3742 (data & (1 << 11))) {
3743 u16 data2 = 0x7EFF;
3744 ret_val = e1000_access_phy_debug_regs_hv(hw,
3745 (1 << 6) | 0x3,
3746 &data2, false);
3747 if (ret_val)
3748 goto out;
3749 }
3750
3751 if (reg > MAX_PHY_MULTI_PAGE_REG) {
3752 /* Page is shifted left, PHY expects (page x 32) */
3753 ret_val = e1000_set_page_igp(hw,
3754 (page << IGP_PAGE_SHIFT));
3755
3756 hw->phy.addr = phy_addr;
3757
3758 if (ret_val)
3759 goto out;
3760 }
3761 }
3762
3763 DEBUGOUT3("writing PHY page %d (or 0x%x shifted) reg 0x%x\n", page,
3764 page << IGP_PAGE_SHIFT, reg);
3765
3766 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg,
3767 data);
3768
3769 out:
3770 if (!locked)
3771 hw->phy.ops.release(hw);
3772
3773 return ret_val;
3774 }
3775
3776 /**
3777 * e1000_write_phy_reg_hv - Write HV PHY register
3778 * @hw: pointer to the HW structure
3779 * @offset: register offset to write to
3780 * @data: data to write at register offset
3781 *
3782 * Acquires semaphore then writes the data to PHY register at the offset.
3783 * Release the acquired semaphores before exiting.
3784 **/
e1000_write_phy_reg_hv(struct e1000_hw * hw,u32 offset,u16 data)3785 s32 e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data)
3786 {
3787 return __e1000_write_phy_reg_hv(hw, offset, data, false, false);
3788 }
3789
3790 /**
3791 * e1000_write_phy_reg_hv_locked - Write HV PHY register
3792 * @hw: pointer to the HW structure
3793 * @offset: register offset to write to
3794 * @data: data to write at register offset
3795 *
3796 * Writes the data to PHY register at the offset. Assumes semaphore
3797 * already acquired.
3798 **/
e1000_write_phy_reg_hv_locked(struct e1000_hw * hw,u32 offset,u16 data)3799 s32 e1000_write_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 data)
3800 {
3801 return __e1000_write_phy_reg_hv(hw, offset, data, true, false);
3802 }
3803
3804 /**
3805 * e1000_write_phy_reg_page_hv - Write HV PHY register
3806 * @hw: pointer to the HW structure
3807 * @offset: register offset to write to
3808 * @data: data to write at register offset
3809 *
3810 * Writes the data to PHY register at the offset. Assumes semaphore
3811 * already acquired and page already set.
3812 **/
e1000_write_phy_reg_page_hv(struct e1000_hw * hw,u32 offset,u16 data)3813 s32 e1000_write_phy_reg_page_hv(struct e1000_hw *hw, u32 offset, u16 data)
3814 {
3815 return __e1000_write_phy_reg_hv(hw, offset, data, true, true);
3816 }
3817
3818 /**
3819 * e1000_get_phy_addr_for_hv_page - Get PHY adrress based on page
3820 * @page: page to be accessed
3821 **/
e1000_get_phy_addr_for_hv_page(u32 page)3822 static u32 e1000_get_phy_addr_for_hv_page(u32 page)
3823 {
3824 u32 phy_addr = 2;
3825
3826 if (page >= HV_INTC_FC_PAGE_START)
3827 phy_addr = 1;
3828
3829 return phy_addr;
3830 }
3831
3832 /**
3833 * e1000_access_phy_debug_regs_hv - Read HV PHY vendor specific high registers
3834 * @hw: pointer to the HW structure
3835 * @offset: register offset to be read or written
3836 * @data: pointer to the data to be read or written
3837 * @read: determines if operation is read or write
3838 *
3839 * Reads the PHY register at offset and stores the retreived information
3840 * in data. Assumes semaphore already acquired. Note that the procedure
3841 * to access these regs uses the address port and data port to read/write.
3842 * These accesses done with PHY address 2 and without using pages.
3843 **/
e1000_access_phy_debug_regs_hv(struct e1000_hw * hw,u32 offset,u16 * data,bool read)3844 static s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset,
3845 u16 *data, bool read)
3846 {
3847 s32 ret_val;
3848 u32 addr_reg;
3849 u32 data_reg;
3850
3851 DEBUGFUNC("e1000_access_phy_debug_regs_hv");
3852
3853 /* This takes care of the difference with desktop vs mobile phy */
3854 addr_reg = ((hw->phy.type == e1000_phy_82578) ?
3855 I82578_ADDR_REG : I82577_ADDR_REG);
3856 data_reg = addr_reg + 1;
3857
3858 /* All operations in this function are phy address 2 */
3859 hw->phy.addr = 2;
3860
3861 /* masking with 0x3F to remove the page from offset */
3862 ret_val = e1000_write_phy_reg_mdic(hw, addr_reg, (u16)offset & 0x3F);
3863 if (ret_val) {
3864 DEBUGOUT("Could not write the Address Offset port register\n");
3865 return ret_val;
3866 }
3867
3868 /* Read or write the data value next */
3869 if (read)
3870 ret_val = e1000_read_phy_reg_mdic(hw, data_reg, data);
3871 else
3872 ret_val = e1000_write_phy_reg_mdic(hw, data_reg, *data);
3873
3874 if (ret_val)
3875 DEBUGOUT("Could not access the Data port register\n");
3876
3877 return ret_val;
3878 }
3879
3880 /**
3881 * e1000_link_stall_workaround_hv - Si workaround
3882 * @hw: pointer to the HW structure
3883 *
3884 * This function works around a Si bug where the link partner can get
3885 * a link up indication before the PHY does. If small packets are sent
3886 * by the link partner they can be placed in the packet buffer without
3887 * being properly accounted for by the PHY and will stall preventing
3888 * further packets from being received. The workaround is to clear the
3889 * packet buffer after the PHY detects link up.
3890 **/
e1000_link_stall_workaround_hv(struct e1000_hw * hw)3891 s32 e1000_link_stall_workaround_hv(struct e1000_hw *hw)
3892 {
3893 s32 ret_val = E1000_SUCCESS;
3894 u16 data;
3895
3896 DEBUGFUNC("e1000_link_stall_workaround_hv");
3897
3898 if (hw->phy.type != e1000_phy_82578)
3899 return E1000_SUCCESS;
3900
3901 /* Do not apply workaround if in PHY loopback bit 14 set */
3902 ret_val = hw->phy.ops.read_reg(hw, PHY_CONTROL, &data);
3903 if (ret_val) {
3904 DEBUGOUT("Error reading PHY control register\n");
3905 return ret_val;
3906 }
3907 if (data & PHY_CONTROL_LB)
3908 return E1000_SUCCESS;
3909
3910 /* check if link is up and at 1Gbps */
3911 ret_val = hw->phy.ops.read_reg(hw, BM_CS_STATUS, &data);
3912 if (ret_val)
3913 return ret_val;
3914
3915 data &= (BM_CS_STATUS_LINK_UP | BM_CS_STATUS_RESOLVED |
3916 BM_CS_STATUS_SPEED_MASK);
3917
3918 if (data != (BM_CS_STATUS_LINK_UP | BM_CS_STATUS_RESOLVED |
3919 BM_CS_STATUS_SPEED_1000))
3920 return E1000_SUCCESS;
3921
3922 msec_delay(200);
3923
3924 /* flush the packets in the fifo buffer */
3925 ret_val = hw->phy.ops.write_reg(hw, HV_MUX_DATA_CTRL,
3926 (HV_MUX_DATA_CTRL_GEN_TO_MAC |
3927 HV_MUX_DATA_CTRL_FORCE_SPEED));
3928 if (ret_val)
3929 return ret_val;
3930
3931 return hw->phy.ops.write_reg(hw, HV_MUX_DATA_CTRL,
3932 HV_MUX_DATA_CTRL_GEN_TO_MAC);
3933 }
3934
3935 /**
3936 * e1000_check_polarity_82577 - Checks the polarity.
3937 * @hw: pointer to the HW structure
3938 *
3939 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
3940 *
3941 * Polarity is determined based on the PHY specific status register.
3942 **/
e1000_check_polarity_82577(struct e1000_hw * hw)3943 s32 e1000_check_polarity_82577(struct e1000_hw *hw)
3944 {
3945 struct e1000_phy_info *phy = &hw->phy;
3946 s32 ret_val;
3947 u16 data;
3948
3949 DEBUGFUNC("e1000_check_polarity_82577");
3950
3951 ret_val = phy->ops.read_reg(hw, I82577_PHY_STATUS_2, &data);
3952
3953 if (!ret_val)
3954 phy->cable_polarity = ((data & I82577_PHY_STATUS2_REV_POLARITY)
3955 ? e1000_rev_polarity_reversed
3956 : e1000_rev_polarity_normal);
3957
3958 return ret_val;
3959 }
3960
3961 /**
3962 * e1000_phy_force_speed_duplex_82577 - Force speed/duplex for I82577 PHY
3963 * @hw: pointer to the HW structure
3964 *
3965 * Calls the PHY setup function to force speed and duplex.
3966 **/
e1000_phy_force_speed_duplex_82577(struct e1000_hw * hw)3967 s32 e1000_phy_force_speed_duplex_82577(struct e1000_hw *hw)
3968 {
3969 struct e1000_phy_info *phy = &hw->phy;
3970 s32 ret_val;
3971 u16 phy_data;
3972 bool link;
3973
3974 DEBUGFUNC("e1000_phy_force_speed_duplex_82577");
3975
3976 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);
3977 if (ret_val)
3978 return ret_val;
3979
3980 e1000_phy_force_speed_duplex_setup(hw, &phy_data);
3981
3982 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);
3983 if (ret_val)
3984 return ret_val;
3985
3986 usec_delay(1);
3987
3988 if (phy->autoneg_wait_to_complete) {
3989 DEBUGOUT("Waiting for forced speed/duplex link on 82577 phy\n");
3990
3991 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
3992 100000, &link);
3993 if (ret_val)
3994 return ret_val;
3995
3996 if (!link)
3997 DEBUGOUT("Link taking longer than expected.\n");
3998
3999 /* Try once more */
4000 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
4001 100000, &link);
4002 }
4003
4004 return ret_val;
4005 }
4006
4007 /**
4008 * e1000_get_phy_info_82577 - Retrieve I82577 PHY information
4009 * @hw: pointer to the HW structure
4010 *
4011 * Read PHY status to determine if link is up. If link is up, then
4012 * set/determine 10base-T extended distance and polarity correction. Read
4013 * PHY port status to determine MDI/MDIx and speed. Based on the speed,
4014 * determine on the cable length, local and remote receiver.
4015 **/
e1000_get_phy_info_82577(struct e1000_hw * hw)4016 s32 e1000_get_phy_info_82577(struct e1000_hw *hw)
4017 {
4018 struct e1000_phy_info *phy = &hw->phy;
4019 s32 ret_val;
4020 u16 data;
4021 bool link;
4022
4023 DEBUGFUNC("e1000_get_phy_info_82577");
4024
4025 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
4026 if (ret_val)
4027 return ret_val;
4028
4029 if (!link) {
4030 DEBUGOUT("Phy info is only valid if link is up\n");
4031 return -E1000_ERR_CONFIG;
4032 }
4033
4034 phy->polarity_correction = true;
4035
4036 ret_val = e1000_check_polarity_82577(hw);
4037 if (ret_val)
4038 return ret_val;
4039
4040 ret_val = phy->ops.read_reg(hw, I82577_PHY_STATUS_2, &data);
4041 if (ret_val)
4042 return ret_val;
4043
4044 phy->is_mdix = !!(data & I82577_PHY_STATUS2_MDIX);
4045
4046 if ((data & I82577_PHY_STATUS2_SPEED_MASK) ==
4047 I82577_PHY_STATUS2_SPEED_1000MBPS) {
4048 ret_val = hw->phy.ops.get_cable_length(hw);
4049 if (ret_val)
4050 return ret_val;
4051
4052 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data);
4053 if (ret_val)
4054 return ret_val;
4055
4056 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS)
4057 ? e1000_1000t_rx_status_ok
4058 : e1000_1000t_rx_status_not_ok;
4059
4060 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS)
4061 ? e1000_1000t_rx_status_ok
4062 : e1000_1000t_rx_status_not_ok;
4063 } else {
4064 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
4065 phy->local_rx = e1000_1000t_rx_status_undefined;
4066 phy->remote_rx = e1000_1000t_rx_status_undefined;
4067 }
4068
4069 return E1000_SUCCESS;
4070 }
4071
4072 /**
4073 * e1000_get_cable_length_82577 - Determine cable length for 82577 PHY
4074 * @hw: pointer to the HW structure
4075 *
4076 * Reads the diagnostic status register and verifies result is valid before
4077 * placing it in the phy_cable_length field.
4078 **/
e1000_get_cable_length_82577(struct e1000_hw * hw)4079 s32 e1000_get_cable_length_82577(struct e1000_hw *hw)
4080 {
4081 struct e1000_phy_info *phy = &hw->phy;
4082 s32 ret_val;
4083 u16 phy_data, length;
4084
4085 DEBUGFUNC("e1000_get_cable_length_82577");
4086
4087 ret_val = phy->ops.read_reg(hw, I82577_PHY_DIAG_STATUS, &phy_data);
4088 if (ret_val)
4089 return ret_val;
4090
4091 length = ((phy_data & I82577_DSTATUS_CABLE_LENGTH) >>
4092 I82577_DSTATUS_CABLE_LENGTH_SHIFT);
4093
4094 if (length == E1000_CABLE_LENGTH_UNDEFINED)
4095 return -E1000_ERR_PHY;
4096
4097 phy->cable_length = length;
4098
4099 return E1000_SUCCESS;
4100 }
4101
4102 /**
4103 * e1000_write_phy_reg_gs40g - Write GS40G PHY register
4104 * @hw: pointer to the HW structure
4105 * @offset: register offset to write to
4106 * @data: data to write at register offset
4107 *
4108 * Acquires semaphore, if necessary, then writes the data to PHY register
4109 * at the offset. Release any acquired semaphores before exiting.
4110 **/
e1000_write_phy_reg_gs40g(struct e1000_hw * hw,u32 offset,u16 data)4111 s32 e1000_write_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 data)
4112 {
4113 s32 ret_val;
4114 u16 page = offset >> GS40G_PAGE_SHIFT;
4115
4116 DEBUGFUNC("e1000_write_phy_reg_gs40g");
4117
4118 offset = offset & GS40G_OFFSET_MASK;
4119 ret_val = hw->phy.ops.acquire(hw);
4120 if (ret_val)
4121 return ret_val;
4122
4123 ret_val = e1000_write_phy_reg_mdic(hw, GS40G_PAGE_SELECT, page);
4124 if (ret_val)
4125 goto release;
4126 ret_val = e1000_write_phy_reg_mdic(hw, offset, data);
4127
4128 release:
4129 hw->phy.ops.release(hw);
4130 return ret_val;
4131 }
4132
4133 /**
4134 * e1000_read_phy_reg_gs40g - Read GS40G PHY register
4135 * @hw: pointer to the HW structure
4136 * @offset: lower half is register offset to read to
4137 * upper half is page to use.
4138 * @data: data to read at register offset
4139 *
4140 * Acquires semaphore, if necessary, then reads the data in the PHY register
4141 * at the offset. Release any acquired semaphores before exiting.
4142 **/
e1000_read_phy_reg_gs40g(struct e1000_hw * hw,u32 offset,u16 * data)4143 s32 e1000_read_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 *data)
4144 {
4145 s32 ret_val;
4146 u16 page = offset >> GS40G_PAGE_SHIFT;
4147
4148 DEBUGFUNC("e1000_read_phy_reg_gs40g");
4149
4150 offset = offset & GS40G_OFFSET_MASK;
4151 ret_val = hw->phy.ops.acquire(hw);
4152 if (ret_val)
4153 return ret_val;
4154
4155 ret_val = e1000_write_phy_reg_mdic(hw, GS40G_PAGE_SELECT, page);
4156 if (ret_val)
4157 goto release;
4158 ret_val = e1000_read_phy_reg_mdic(hw, offset, data);
4159
4160 release:
4161 hw->phy.ops.release(hw);
4162 return ret_val;
4163 }
4164
4165 /**
4166 * e1000_read_phy_reg_mphy - Read mPHY control register
4167 * @hw: pointer to the HW structure
4168 * @address: address to be read
4169 * @data: pointer to the read data
4170 *
4171 * Reads the mPHY control register in the PHY at offset and stores the
4172 * information read to data.
4173 **/
e1000_read_phy_reg_mphy(struct e1000_hw * hw,u32 address,u32 * data)4174 s32 e1000_read_phy_reg_mphy(struct e1000_hw *hw, u32 address, u32 *data)
4175 {
4176 u32 mphy_ctrl = 0;
4177 bool locked = false;
4178 bool ready;
4179
4180 DEBUGFUNC("e1000_read_phy_reg_mphy");
4181
4182 /* Check if mPHY is ready to read/write operations */
4183 ready = e1000_is_mphy_ready(hw);
4184 if (!ready)
4185 return -E1000_ERR_PHY;
4186
4187 /* Check if mPHY access is disabled and enable it if so */
4188 mphy_ctrl = E1000_READ_REG(hw, E1000_MPHY_ADDR_CTRL);
4189 if (mphy_ctrl & E1000_MPHY_DIS_ACCESS) {
4190 locked = true;
4191 ready = e1000_is_mphy_ready(hw);
4192 if (!ready)
4193 return -E1000_ERR_PHY;
4194 mphy_ctrl |= E1000_MPHY_ENA_ACCESS;
4195 E1000_WRITE_REG(hw, E1000_MPHY_ADDR_CTRL, mphy_ctrl);
4196 }
4197
4198 /* Set the address that we want to read */
4199 ready = e1000_is_mphy_ready(hw);
4200 if (!ready)
4201 return -E1000_ERR_PHY;
4202
4203 /* We mask address, because we want to use only current lane */
4204 mphy_ctrl = (mphy_ctrl & ~E1000_MPHY_ADDRESS_MASK &
4205 ~E1000_MPHY_ADDRESS_FNC_OVERRIDE) |
4206 (address & E1000_MPHY_ADDRESS_MASK);
4207 E1000_WRITE_REG(hw, E1000_MPHY_ADDR_CTRL, mphy_ctrl);
4208
4209 /* Read data from the address */
4210 ready = e1000_is_mphy_ready(hw);
4211 if (!ready)
4212 return -E1000_ERR_PHY;
4213 *data = E1000_READ_REG(hw, E1000_MPHY_DATA);
4214
4215 /* Disable access to mPHY if it was originally disabled */
4216 if (locked)
4217 ready = e1000_is_mphy_ready(hw);
4218 if (!ready)
4219 return -E1000_ERR_PHY;
4220 E1000_WRITE_REG(hw, E1000_MPHY_ADDR_CTRL,
4221 E1000_MPHY_DIS_ACCESS);
4222
4223 return E1000_SUCCESS;
4224 }
4225
4226 /**
4227 * e1000_write_phy_reg_mphy - Write mPHY control register
4228 * @hw: pointer to the HW structure
4229 * @address: address to write to
4230 * @data: data to write to register at offset
4231 * @line_override: used when we want to use different line than default one
4232 *
4233 * Writes data to mPHY control register.
4234 **/
e1000_write_phy_reg_mphy(struct e1000_hw * hw,u32 address,u32 data,bool line_override)4235 s32 e1000_write_phy_reg_mphy(struct e1000_hw *hw, u32 address, u32 data,
4236 bool line_override)
4237 {
4238 u32 mphy_ctrl = 0;
4239 bool locked = false;
4240 bool ready;
4241
4242 DEBUGFUNC("e1000_write_phy_reg_mphy");
4243
4244 /* Check if mPHY is ready to read/write operations */
4245 ready = e1000_is_mphy_ready(hw);
4246 if (!ready)
4247 return -E1000_ERR_PHY;
4248
4249 /* Check if mPHY access is disabled and enable it if so */
4250 mphy_ctrl = E1000_READ_REG(hw, E1000_MPHY_ADDR_CTRL);
4251 if (mphy_ctrl & E1000_MPHY_DIS_ACCESS) {
4252 locked = true;
4253 ready = e1000_is_mphy_ready(hw);
4254 if (!ready)
4255 return -E1000_ERR_PHY;
4256 mphy_ctrl |= E1000_MPHY_ENA_ACCESS;
4257 E1000_WRITE_REG(hw, E1000_MPHY_ADDR_CTRL, mphy_ctrl);
4258 }
4259
4260 /* Set the address that we want to read */
4261 ready = e1000_is_mphy_ready(hw);
4262 if (!ready)
4263 return -E1000_ERR_PHY;
4264
4265 /* We mask address, because we want to use only current lane */
4266 if (line_override)
4267 mphy_ctrl |= E1000_MPHY_ADDRESS_FNC_OVERRIDE;
4268 else
4269 mphy_ctrl &= ~E1000_MPHY_ADDRESS_FNC_OVERRIDE;
4270 mphy_ctrl = (mphy_ctrl & ~E1000_MPHY_ADDRESS_MASK) |
4271 (address & E1000_MPHY_ADDRESS_MASK);
4272 E1000_WRITE_REG(hw, E1000_MPHY_ADDR_CTRL, mphy_ctrl);
4273
4274 /* Read data from the address */
4275 ready = e1000_is_mphy_ready(hw);
4276 if (!ready)
4277 return -E1000_ERR_PHY;
4278 E1000_WRITE_REG(hw, E1000_MPHY_DATA, data);
4279
4280 /* Disable access to mPHY if it was originally disabled */
4281 if (locked)
4282 ready = e1000_is_mphy_ready(hw);
4283 if (!ready)
4284 return -E1000_ERR_PHY;
4285 E1000_WRITE_REG(hw, E1000_MPHY_ADDR_CTRL,
4286 E1000_MPHY_DIS_ACCESS);
4287
4288 return E1000_SUCCESS;
4289 }
4290
4291 /**
4292 * e1000_is_mphy_ready - Check if mPHY control register is not busy
4293 * @hw: pointer to the HW structure
4294 *
4295 * Returns mPHY control register status.
4296 **/
e1000_is_mphy_ready(struct e1000_hw * hw)4297 bool e1000_is_mphy_ready(struct e1000_hw *hw)
4298 {
4299 u16 retry_count = 0;
4300 u32 mphy_ctrl = 0;
4301 bool ready = false;
4302
4303 while (retry_count < 2) {
4304 mphy_ctrl = E1000_READ_REG(hw, E1000_MPHY_ADDR_CTRL);
4305 if (mphy_ctrl & E1000_MPHY_BUSY) {
4306 usec_delay(20);
4307 retry_count++;
4308 continue;
4309 }
4310 ready = true;
4311 break;
4312 }
4313
4314 if (!ready)
4315 DEBUGOUT("ERROR READING mPHY control register, phy is busy.\n");
4316
4317 return ready;
4318 }
4319
4320 /**
4321 * __e1000_access_xmdio_reg - Read/write XMDIO register
4322 * @hw: pointer to the HW structure
4323 * @address: XMDIO address to program
4324 * @dev_addr: device address to program
4325 * @data: pointer to value to read/write from/to the XMDIO address
4326 * @read: boolean flag to indicate read or write
4327 **/
__e1000_access_xmdio_reg(struct e1000_hw * hw,u16 address,u8 dev_addr,u16 * data,bool read)4328 static s32 __e1000_access_xmdio_reg(struct e1000_hw *hw, u16 address,
4329 u8 dev_addr, u16 *data, bool read)
4330 {
4331 s32 ret_val;
4332
4333 DEBUGFUNC("__e1000_access_xmdio_reg");
4334
4335 ret_val = hw->phy.ops.write_reg(hw, E1000_MMDAC, dev_addr);
4336 if (ret_val)
4337 return ret_val;
4338
4339 ret_val = hw->phy.ops.write_reg(hw, E1000_MMDAAD, address);
4340 if (ret_val)
4341 return ret_val;
4342
4343 ret_val = hw->phy.ops.write_reg(hw, E1000_MMDAC, E1000_MMDAC_FUNC_DATA |
4344 dev_addr);
4345 if (ret_val)
4346 return ret_val;
4347
4348 if (read)
4349 ret_val = hw->phy.ops.read_reg(hw, E1000_MMDAAD, data);
4350 else
4351 ret_val = hw->phy.ops.write_reg(hw, E1000_MMDAAD, *data);
4352 if (ret_val)
4353 return ret_val;
4354
4355 /* Recalibrate the device back to 0 */
4356 ret_val = hw->phy.ops.write_reg(hw, E1000_MMDAC, 0);
4357 if (ret_val)
4358 return ret_val;
4359
4360 return ret_val;
4361 }
4362
4363 /**
4364 * e1000_read_xmdio_reg - Read XMDIO register
4365 * @hw: pointer to the HW structure
4366 * @addr: XMDIO address to program
4367 * @dev_addr: device address to program
4368 * @data: value to be read from the EMI address
4369 **/
e1000_read_xmdio_reg(struct e1000_hw * hw,u16 addr,u8 dev_addr,u16 * data)4370 s32 e1000_read_xmdio_reg(struct e1000_hw *hw, u16 addr, u8 dev_addr, u16 *data)
4371 {
4372 DEBUGFUNC("e1000_read_xmdio_reg");
4373
4374 return __e1000_access_xmdio_reg(hw, addr, dev_addr, data, true);
4375 }
4376
4377 /**
4378 * e1000_write_xmdio_reg - Write XMDIO register
4379 * @hw: pointer to the HW structure
4380 * @addr: XMDIO address to program
4381 * @dev_addr: device address to program
4382 * @data: value to be written to the XMDIO address
4383 **/
e1000_write_xmdio_reg(struct e1000_hw * hw,u16 addr,u8 dev_addr,u16 data)4384 s32 e1000_write_xmdio_reg(struct e1000_hw *hw, u16 addr, u8 dev_addr, u16 data)
4385 {
4386 DEBUGFUNC("e1000_write_xmdio_reg");
4387
4388 return __e1000_access_xmdio_reg(hw, addr, dev_addr, &data,
4389 false);
4390 }
4391