1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2020 - 2021 Alstom Group.
5 * Copyright (c) 2020 - 2021 Semihalf.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29 /* eSDHC controller driver for NXP QorIQ Layerscape SoCs. */
30
31 #include <sys/param.h>
32 #include <sys/endian.h>
33 #include <sys/kernel.h>
34 #include <sys/module.h>
35 #include <sys/rman.h>
36 #include <sys/sysctl.h>
37 #include <sys/taskqueue.h>
38
39 #include <machine/bus.h>
40 #include <machine/resource.h>
41
42 #include <dev/clk/clk.h>
43 #include <dev/syscon/syscon.h>
44 #include <dev/mmc/bridge.h>
45 #include <dev/mmc/mmcbrvar.h>
46 #include <dev/mmc/mmc_fdt_helpers.h>
47 #include <dev/ofw/ofw_bus.h>
48 #include <dev/ofw/ofw_bus_subr.h>
49 #include <dev/sdhci/sdhci.h>
50 #include <dev/sdhci/sdhci_fdt_gpio.h>
51
52 #include "mmcbr_if.h"
53 #include "sdhci_if.h"
54 #include "syscon_if.h"
55
56 #define RD4 (sc->read)
57 #define WR4 (sc->write)
58
59 #define SDHCI_FSL_PRES_STATE 0x24
60 #define SDHCI_FSL_PRES_SDSTB (1 << 3)
61 #define SDHCI_FSL_PRES_COMPAT_MASK 0x000f0f07
62
63 #define SDHCI_FSL_PROT_CTRL 0x28
64 #define SDHCI_FSL_PROT_CTRL_WIDTH_1BIT (0 << 1)
65 #define SDHCI_FSL_PROT_CTRL_WIDTH_4BIT (1 << 1)
66 #define SDHCI_FSL_PROT_CTRL_WIDTH_8BIT (2 << 1)
67 #define SDHCI_FSL_PROT_CTRL_WIDTH_MASK (3 << 1)
68 #define SDHCI_FSL_PROT_CTRL_BYTE_SWAP (0 << 4)
69 #define SDHCI_FSL_PROT_CTRL_BYTE_NATIVE (2 << 4)
70 #define SDHCI_FSL_PROT_CTRL_BYTE_MASK (3 << 4)
71 #define SDHCI_FSL_PROT_CTRL_DMA_MASK (3 << 8)
72 #define SDHCI_FSL_PROT_CTRL_VOLT_SEL (1 << 10)
73
74 #define SDHCI_FSL_IRQSTAT 0x30
75 #define SDHCI_FSL_IRQSTAT_BRR (1 << 5)
76 #define SDHCI_FSL_IRQSTAT_CINTSEN (1 << 8)
77 #define SDHCI_FSL_IRQSTAT_RTE (1 << 12)
78 #define SDHCI_FSL_IRQSTAT_TNE (1 << 26)
79
80 #define SDHCI_FSL_SYS_CTRL 0x2c
81 #define SDHCI_FSL_CLK_IPGEN (1 << 0)
82 #define SDHCI_FSL_CLK_SDCLKEN (1 << 3)
83 #define SDHCI_FSL_CLK_DIVIDER_MASK 0x000000f0
84 #define SDHCI_FSL_CLK_DIVIDER_SHIFT 4
85 #define SDHCI_FSL_CLK_PRESCALE_MASK 0x0000ff00
86 #define SDHCI_FSL_CLK_PRESCALE_SHIFT 8
87
88 #define SDHCI_FSL_WTMK_LVL 0x44
89 #define SDHCI_FSL_WTMK_RD_512B (0 << 0)
90 #define SDHCI_FSL_WTMK_WR_512B (0 << 15)
91
92 #define SDHCI_FSL_AUTOCERR 0x3C
93 #define SDHCI_FSL_AUTOCERR_UHMS_HS200 (3 << 16)
94 #define SDHCI_FSL_AUTOCERR_UHMS (7 << 16)
95 #define SDHCI_FSL_AUTOCERR_EXTN (1 << 22)
96 #define SDHCI_FSL_AUTOCERR_SMPCLKSEL (1 << 23)
97 #define SDHCI_FSL_AUTOCERR_UHMS_SHIFT 16
98
99 #define SDHCI_FSL_HOST_VERSION 0xfc
100 #define SDHCI_FSL_VENDOR_V23 0x13
101
102 #define SDHCI_FSL_CAPABILITIES2 0x114
103
104 #define SDHCI_FSL_TBCTL 0x120
105
106 #define SDHCI_FSL_TBSTAT 0x124
107 #define SDHCI_FSL_TBCTL_TBEN (1 << 2)
108 #define SDHCI_FSL_TBCTL_HS400_EN (1 << 4)
109 #define SDHCI_FSL_TBCTL_SAMP_CMD_DQS (1 << 5)
110 #define SDHCI_FSL_TBCTL_HS400_WND_ADJ (1 << 6)
111 #define SDHCI_FSL_TBCTL_TB_MODE_MASK 0x3
112 #define SDHCI_FSL_TBCTL_MODE_1 0
113 #define SDHCI_FSL_TBCTL_MODE_2 1
114 #define SDHCI_FSL_TBCTL_MODE_3 2
115 #define SDHCI_FSL_TBCTL_MODE_SW 3
116
117 #define SDHCI_FSL_TBPTR 0x128
118 #define SDHCI_FSL_TBPTR_WND_START_SHIFT 8
119 #define SDHCI_FSL_TBPTR_WND_MASK 0x7F
120
121 #define SDHCI_FSL_SDCLKCTL 0x144
122 #define SDHCI_FSL_SDCLKCTL_CMD_CLK_CTL (1 << 15)
123 #define SDHCI_FSL_SDCLKCTL_LPBK_CLK_SEL (1 << 31)
124
125 #define SDHCI_FSL_SDTIMINGCTL 0x148
126 #define SDHCI_FSL_SDTIMINGCTL_FLW_CTL (1 << 15)
127
128 #define SDHCI_FSL_DLLCFG0 0x160
129 #define SDHCI_FSL_DLLCFG0_FREQ_SEL (1 << 27)
130 #define SDHCI_FSL_DLLCFG0_RESET (1 << 30)
131 #define SDHCI_FSL_DLLCFG0_EN (1 << 31)
132
133 #define SDHCI_FSL_DLLCFG1 0x164
134 #define SDHCI_FSL_DLLCFG1_PULSE_STRETCH (1 << 31)
135
136 #define SDHCI_FSL_DLLSTAT0 0x170
137 #define SDHCI_FSL_DLLSTAT0_SLV_STS (1 << 27)
138
139 #define SDHCI_FSL_ESDHC_CTRL 0x40c
140 #define SDHCI_FSL_ESDHC_CTRL_SNOOP (1 << 6)
141 #define SDHCI_FSL_ESDHC_CTRL_FAF (1 << 18)
142 /*
143 * Bit 19 is misnamed: per the T2080 RM (16.3.32) this is PCS (Peripheral
144 * Clock Select). Set = peripheral clock / 2, clear = platform clock.
145 */
146 #define SDHCI_FSL_ESDHC_CTRL_CLK_DIV2 (1 << 19)
147
148 #define SCFG_SDHCIOVSELCR 0x408
149 #define SCFG_SDHCIOVSELCR_TGLEN (1 << 0)
150 #define SCFG_SDHCIOVSELCR_VS (1 << 31)
151 #define SCFG_SDHCIOVSELCR_VSELVAL_MASK (3 << 1)
152 #define SCFG_SDHCIOVSELCR_VSELVAL_1_8 0x0
153 #define SCFG_SDHCIOVSELCR_VSELVAL_3_3 0x2
154
155 #define SDHCI_FSL_CAN_VDD_MASK \
156 (SDHCI_CAN_VDD_180 | SDHCI_CAN_VDD_300 | SDHCI_CAN_VDD_330)
157
158 /* Some platforms do not detect pulse width correctly. */
159 #define SDHCI_FSL_UNRELIABLE_PULSE_DET (1 << 0)
160 /* On some platforms switching voltage to 1.8V is not supported */
161 #define SDHCI_FSL_UNSUPP_1_8V (1 << 1)
162 /* Hardware tuning can fail, fallback to SW tuning in that case. */
163 #define SDHCI_FSL_TUNING_ERRATUM_TYPE1 (1 << 2)
164 /*
165 * Pointer window might not be set properly on some platforms.
166 * Check window and perform SW tuning.
167 */
168 #define SDHCI_FSL_TUNING_ERRATUM_TYPE2 (1 << 3)
169 /*
170 * In HS400 mode only 4, 8, 12 clock dividers can be used.
171 * Use the smallest value, bigger than requested in that case.
172 */
173 #define SDHCI_FSL_HS400_LIMITED_CLK_DIV (1 << 4)
174
175 /*
176 * Some SoCs don't have a fixed regulator. Switching voltage
177 * requires special routine including syscon registers.
178 */
179 #define SDHCI_FSL_MISSING_VCCQ_REG (1 << 5)
180 /*
181 * Whether to route "peripheral clock / 2" into the eSDHC via ESDHCCTL[PCS].
182 * Layerscape parts and older SoCs feed the eSDHC through the peripheral clock
183 * and want the on-chip /2; some QorIQ parts (T-series) feed the eSDHC directly
184 * from the platform clock and must leave PCS clear.
185 */
186 #define SDHCI_FSL_NO_PCS_SEL (1 << 6)
187 /*
188 * Enable ESDHCCTL[SNOOP] so DMA transfers participate in cache coherence.
189 * QorIQ CoreNet hardware supports snooped DMA; set this on any SoC where we
190 * want DMA-coherent operation regardless of the DTS "dma-coherent" property.
191 */
192 #define SDHCI_FSL_DMA_SNOOP (1 << 7)
193
194 /*
195 * HS400 tuning is done in HS200 mode, but it has to be done using
196 * the target frequency. In order to apply the errata above we need to
197 * know the target mode during tuning procedure. Use this flag for just that.
198 */
199 #define SDHCI_FSL_HS400_FLAG (1 << 0)
200
201 #define SDHCI_FSL_MAX_RETRIES 20000 /* DELAY(10) * this = 200ms */
202
203 struct sdhci_fsl_fdt_softc {
204 device_t dev;
205 const struct sdhci_fsl_fdt_soc_data *soc_data;
206 struct resource *mem_res;
207 struct resource *irq_res;
208 void *irq_cookie;
209 uint32_t baseclk_hz;
210 uint32_t maxclk_hz;
211 struct sdhci_fdt_gpio *gpio;
212 struct sdhci_slot slot;
213 bool slot_init_done;
214 uint32_t cmd_and_mode;
215 uint16_t sdclk_bits;
216 struct mmc_helper fdt_helper;
217 uint32_t div_ratio;
218 uint8_t vendor_ver;
219 uint32_t flags;
220 uint32_t buf_order;
221
222 uint32_t (* read)(struct sdhci_fsl_fdt_softc *, bus_size_t);
223 void (* write)(struct sdhci_fsl_fdt_softc *, bus_size_t, uint32_t);
224 };
225
226 struct sdhci_fsl_fdt_soc_data {
227 int quirks;
228 int baseclk_div;
229 uint32_t errata;
230 uint32_t wml_value; /* SDHC_WTMK_LVL override; 0 = 512B/512B default. */
231 char *syscon_compat;
232 };
233
234 static const struct sdhci_fsl_fdt_soc_data sdhci_fsl_fdt_ls1012a_soc_data = {
235 .quirks = 0,
236 .baseclk_div = 1,
237 .errata = SDHCI_FSL_MISSING_VCCQ_REG | SDHCI_FSL_TUNING_ERRATUM_TYPE2,
238 .syscon_compat = "fsl,ls1012a-scfg",
239 };
240
241 static const struct sdhci_fsl_fdt_soc_data sdhci_fsl_fdt_ls1028a_soc_data = {
242 .quirks = SDHCI_QUIRK_DONT_SET_HISPD_BIT |
243 SDHCI_QUIRK_BROKEN_AUTO_STOP | SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK,
244 .baseclk_div = 2,
245 .errata = SDHCI_FSL_UNRELIABLE_PULSE_DET |
246 SDHCI_FSL_HS400_LIMITED_CLK_DIV,
247 };
248
249 static const struct sdhci_fsl_fdt_soc_data sdhci_fsl_fdt_ls1046a_soc_data = {
250 .quirks = SDHCI_QUIRK_DONT_SET_HISPD_BIT | SDHCI_QUIRK_BROKEN_AUTO_STOP,
251 .baseclk_div = 2,
252 .errata = SDHCI_FSL_MISSING_VCCQ_REG | SDHCI_FSL_TUNING_ERRATUM_TYPE2,
253 .syscon_compat = "fsl,ls1046a-scfg",
254 };
255
256 static const struct sdhci_fsl_fdt_soc_data sdhci_fsl_fdt_lx2160a_soc_data = {
257 .quirks = 0,
258 .baseclk_div = 2,
259 .errata = SDHCI_FSL_UNRELIABLE_PULSE_DET |
260 SDHCI_FSL_HS400_LIMITED_CLK_DIV,
261 };
262
263 /*
264 * P1022: BRST_LEN fields in the watermark register are reserved and read back
265 * as 0x10; write a WML that matches to avoid a false "changed" mismatch and
266 * keep behavior consistent with the fsl_sdhci(4) legacy driver's handling.
267 */
268 static const struct sdhci_fsl_fdt_soc_data sdhci_fsl_fdt_p1022_soc_data = {
269 .quirks = SDHCI_QUIRK_DONT_SET_HISPD_BIT |
270 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK,
271 .baseclk_div = 1,
272 .errata = SDHCI_FSL_NO_PCS_SEL | SDHCI_FSL_DMA_SNOOP,
273 .wml_value = 0x10801080,
274 };
275
276 /*
277 * Generic default targets PowerPC QorIQ eSDHC (T-series, P-series, MPC85xx),
278 * which is the common case for the "fsl,esdhc" compat fallback in-tree.
279 * - DONT_SET_HISPD_BIT: eSDHC has no HISPD bit at the SDHCI-standard offset.
280 * - DATA_TIMEOUT_USES_SDCLK: timeout counter runs off SDCLK, not TMCLK.
281 * - NO_PCS_SEL: eSDHC is fed directly from the platform clock; do not
282 * enable PCS. If a future Layerscape ARM SoC needs the /2 peripheral
283 * clock select, add a specific compat entry for it.
284 * R1B fix (SDHCI_QUIRK_NO_BUSY_IRQ) is applied at runtime from HOST_VERSION;
285 * no soc_data flag needed.
286 */
287 static const struct sdhci_fsl_fdt_soc_data sdhci_fsl_fdt_gen_data = {
288 .quirks = SDHCI_QUIRK_DONT_SET_HISPD_BIT |
289 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK,
290 .baseclk_div = 1,
291 .errata = SDHCI_FSL_NO_PCS_SEL | SDHCI_FSL_DMA_SNOOP,
292 };
293
294 static const struct ofw_compat_data sdhci_fsl_fdt_compat_data[] = {
295 {"fsl,ls1012a-esdhc", (uintptr_t)&sdhci_fsl_fdt_ls1012a_soc_data},
296 {"fsl,ls1028a-esdhc", (uintptr_t)&sdhci_fsl_fdt_ls1028a_soc_data},
297 {"fsl,ls1046a-esdhc", (uintptr_t)&sdhci_fsl_fdt_ls1046a_soc_data},
298 {"fsl,p1022-esdhc", (uintptr_t)&sdhci_fsl_fdt_p1022_soc_data},
299 {"fsl,esdhc", (uintptr_t)&sdhci_fsl_fdt_gen_data},
300 {NULL, 0}
301 };
302
303 static uint32_t
read_be(struct sdhci_fsl_fdt_softc * sc,bus_size_t off)304 read_be(struct sdhci_fsl_fdt_softc *sc, bus_size_t off)
305 {
306
307 return (be32toh(bus_read_4(sc->mem_res, off)));
308 }
309
310 static void
write_be(struct sdhci_fsl_fdt_softc * sc,bus_size_t off,uint32_t val)311 write_be(struct sdhci_fsl_fdt_softc *sc, bus_size_t off, uint32_t val)
312 {
313
314 bus_write_4(sc->mem_res, off, htobe32(val));
315 }
316
317 static uint32_t
read_le(struct sdhci_fsl_fdt_softc * sc,bus_size_t off)318 read_le(struct sdhci_fsl_fdt_softc *sc, bus_size_t off)
319 {
320
321 return (bus_read_4(sc->mem_res, off));
322 }
323
324 static void
write_le(struct sdhci_fsl_fdt_softc * sc,bus_size_t off,uint32_t val)325 write_le(struct sdhci_fsl_fdt_softc *sc, bus_size_t off, uint32_t val)
326 {
327
328 bus_write_4(sc->mem_res, off, val);
329 }
330
331
332 static uint16_t
sdhci_fsl_fdt_get_clock(struct sdhci_fsl_fdt_softc * sc)333 sdhci_fsl_fdt_get_clock(struct sdhci_fsl_fdt_softc *sc)
334 {
335 uint16_t val;
336
337 val = sc->sdclk_bits | SDHCI_CLOCK_INT_EN;
338 if (RD4(sc, SDHCI_FSL_PRES_STATE) & SDHCI_FSL_PRES_SDSTB)
339 val |= SDHCI_CLOCK_INT_STABLE;
340 if (RD4(sc, SDHCI_FSL_SYS_CTRL) & SDHCI_FSL_CLK_SDCLKEN)
341 val |= SDHCI_CLOCK_CARD_EN;
342
343 return (val);
344 }
345
346 /*
347 * Calculate clock prescaler and divisor values based on the following formula:
348 * `frequency = base clock / (prescaler * divisor)`.
349 */
350 #define SDHCI_FSL_FDT_CLK_DIV(sc, base, freq, pre, div) \
351 do { \
352 (pre) = (sc)->vendor_ver < SDHCI_FSL_VENDOR_V23 ? 2 : 1;\
353 while ((freq) < (base) / ((pre) * 16) && (pre) < 256) \
354 (pre) <<= 1; \
355 /* div/pre can't both be set to 1, according to PM. */ \
356 (div) = ((pre) == 1 ? 2 : 1); \
357 while ((freq) < (base) / ((pre) * (div)) && (div) < 16) \
358 ++(div); \
359 } while (0)
360
361 static void
fsl_sdhc_fdt_set_clock(struct sdhci_fsl_fdt_softc * sc,struct sdhci_slot * slot,uint16_t val)362 fsl_sdhc_fdt_set_clock(struct sdhci_fsl_fdt_softc *sc, struct sdhci_slot *slot,
363 uint16_t val)
364 {
365 uint32_t prescale, div, val32, div_ratio;
366
367 sc->sdclk_bits = val & SDHCI_DIVIDERS_MASK;
368 val32 = RD4(sc, SDHCI_CLOCK_CONTROL);
369
370 if ((val & SDHCI_CLOCK_CARD_EN) == 0) {
371 WR4(sc, SDHCI_CLOCK_CONTROL, val32 & ~SDHCI_FSL_CLK_SDCLKEN);
372 return;
373 }
374
375 /*
376 * Ignore dividers provided by core in `sdhci_set_clock` and calculate
377 * them anew with higher accuracy.
378 */
379 SDHCI_FSL_FDT_CLK_DIV(sc, sc->baseclk_hz, slot->clock, prescale, div);
380
381 div_ratio = prescale * div;
382
383 /*
384 * According to limited clock division erratum, clock dividers in hs400
385 * can be only 4, 8 or 12
386 */
387 if ((sc->soc_data->errata & SDHCI_FSL_HS400_LIMITED_CLK_DIV) &&
388 (sc->slot.host.ios.timing == bus_timing_mmc_hs400 ||
389 (sc->flags & SDHCI_FSL_HS400_FLAG))) {
390 if (div_ratio <= 4) {
391 prescale = 4;
392 div = 1;
393 } else if (div_ratio <= 8) {
394 prescale = 4;
395 div = 2;
396 } else if (div_ratio <= 12) {
397 prescale = 4;
398 div = 3;
399 } else {
400 device_printf(sc->dev, "Unsupported clock divider.\n");
401 }
402 }
403
404 sc->div_ratio = prescale * div;
405 if (bootverbose)
406 device_printf(sc->dev,
407 "Desired SD/MMC freq: %d, actual: %d; base %d prescale %d divisor %d\n",
408 slot->clock, sc->baseclk_hz / (prescale * div),
409 sc->baseclk_hz, prescale, div);
410
411 prescale >>= 1;
412 div -= 1;
413
414 val32 &= ~(SDHCI_FSL_CLK_DIVIDER_MASK | SDHCI_FSL_CLK_PRESCALE_MASK);
415 val32 |= div << SDHCI_FSL_CLK_DIVIDER_SHIFT;
416 val32 |= prescale << SDHCI_FSL_CLK_PRESCALE_SHIFT;
417 val32 |= SDHCI_FSL_CLK_IPGEN | SDHCI_FSL_CLK_SDCLKEN;
418 WR4(sc, SDHCI_CLOCK_CONTROL, val32);
419 }
420
421 static uint8_t
sdhci_fsl_fdt_read_1(device_t dev,struct sdhci_slot * slot,bus_size_t off)422 sdhci_fsl_fdt_read_1(device_t dev, struct sdhci_slot *slot, bus_size_t off)
423 {
424 struct sdhci_fsl_fdt_softc *sc;
425 uint32_t wrk32, val32;
426
427 sc = device_get_softc(dev);
428
429 switch (off) {
430 case SDHCI_HOST_CONTROL:
431 wrk32 = RD4(sc, SDHCI_FSL_PROT_CTRL);
432 val32 = wrk32 & (SDHCI_CTRL_LED | SDHCI_CTRL_CARD_DET |
433 SDHCI_CTRL_FORCE_CARD);
434 if (wrk32 & SDHCI_FSL_PROT_CTRL_WIDTH_4BIT)
435 val32 |= SDHCI_CTRL_4BITBUS;
436 else if (wrk32 & SDHCI_FSL_PROT_CTRL_WIDTH_8BIT)
437 val32 |= SDHCI_CTRL_8BITBUS;
438 return (val32);
439 case SDHCI_POWER_CONTROL:
440 return (SDHCI_POWER_ON | SDHCI_POWER_300);
441 default:
442 break;
443 }
444
445 return ((RD4(sc, off & ~3) >> (off & 3) * 8) & UINT8_MAX);
446 }
447
448 static uint16_t
sdhci_fsl_fdt_read_2(device_t dev,struct sdhci_slot * slot,bus_size_t off)449 sdhci_fsl_fdt_read_2(device_t dev, struct sdhci_slot *slot, bus_size_t off)
450 {
451 struct sdhci_fsl_fdt_softc *sc;
452 uint32_t val32;
453
454 sc = device_get_softc(dev);
455
456 switch (off) {
457 case SDHCI_CLOCK_CONTROL:
458 return (sdhci_fsl_fdt_get_clock(sc));
459 case SDHCI_HOST_VERSION:
460 return (RD4(sc, SDHCI_FSL_HOST_VERSION) & UINT16_MAX);
461 case SDHCI_TRANSFER_MODE:
462 return (sc->cmd_and_mode & UINT16_MAX);
463 case SDHCI_COMMAND_FLAGS:
464 return (sc->cmd_and_mode >> 16);
465 case SDHCI_SLOT_INT_STATUS:
466 /*
467 * eSDHC hardware manages only a single slot.
468 * Synthesize a slot interrupt status register for slot 1 below.
469 */
470 val32 = RD4(sc, SDHCI_INT_STATUS);
471 val32 &= RD4(sc, SDHCI_SIGNAL_ENABLE);
472 return (!!val32);
473 default:
474 return ((RD4(sc, off & ~3) >> (off & 3) * 8) & UINT16_MAX);
475 }
476 }
477
478 static uint32_t
sdhci_fsl_fdt_read_4(device_t dev,struct sdhci_slot * slot,bus_size_t off)479 sdhci_fsl_fdt_read_4(device_t dev, struct sdhci_slot *slot, bus_size_t off)
480 {
481 struct sdhci_fsl_fdt_softc *sc;
482 uint32_t wrk32, val32;
483
484 sc = device_get_softc(dev);
485
486 if (off == SDHCI_BUFFER)
487 return (bus_read_4(sc->mem_res, off));
488
489 val32 = RD4(sc, off);
490
491 if (off == SDHCI_PRESENT_STATE) {
492 wrk32 = val32;
493 val32 &= SDHCI_FSL_PRES_COMPAT_MASK;
494 val32 |= (wrk32 >> 4) & SDHCI_STATE_DAT_MASK;
495 val32 |= (wrk32 << 1) & SDHCI_STATE_CMD;
496 }
497
498 return (val32);
499 }
500
501 static void
sdhci_fsl_fdt_read_multi_4(device_t dev,struct sdhci_slot * slot,bus_size_t off,uint32_t * data,bus_size_t count)502 sdhci_fsl_fdt_read_multi_4(device_t dev, struct sdhci_slot *slot, bus_size_t off,
503 uint32_t *data, bus_size_t count)
504 {
505 struct sdhci_fsl_fdt_softc *sc;
506
507 sc = device_get_softc(dev);
508 bus_read_multi_4(sc->mem_res, off, data, count);
509 }
510
511 static void
sdhci_fsl_fdt_write_1(device_t dev,struct sdhci_slot * slot,bus_size_t off,uint8_t val)512 sdhci_fsl_fdt_write_1(device_t dev, struct sdhci_slot *slot, bus_size_t off,
513 uint8_t val)
514 {
515 struct sdhci_fsl_fdt_softc *sc;
516 uint32_t val32;
517
518 sc = device_get_softc(dev);
519
520 switch (off) {
521 case SDHCI_HOST_CONTROL:
522 val32 = RD4(sc, SDHCI_FSL_PROT_CTRL);
523 val32 &= ~SDHCI_FSL_PROT_CTRL_WIDTH_MASK;
524 val32 |= (val & SDHCI_CTRL_LED);
525
526 if (val & SDHCI_CTRL_8BITBUS)
527 val32 |= SDHCI_FSL_PROT_CTRL_WIDTH_8BIT;
528 else
529 /* Bus width is 1-bit when this flag is not set. */
530 val32 |= (val & SDHCI_CTRL_4BITBUS);
531 /* Enable SDMA by masking out this field. */
532 val32 &= ~SDHCI_FSL_PROT_CTRL_DMA_MASK;
533 val32 &= ~(SDHCI_CTRL_CARD_DET | SDHCI_CTRL_FORCE_CARD);
534 val32 |= (val & (SDHCI_CTRL_CARD_DET |
535 SDHCI_CTRL_FORCE_CARD));
536 WR4(sc, SDHCI_FSL_PROT_CTRL, val32);
537 return;
538 case SDHCI_POWER_CONTROL:
539 return;
540 default:
541 val32 = RD4(sc, off & ~3);
542 val32 &= ~(UINT8_MAX << (off & 3) * 8);
543 val32 |= (val << (off & 3) * 8);
544 WR4(sc, off & ~3, val32);
545 return;
546 }
547 }
548
549 static void
sdhci_fsl_fdt_write_2(device_t dev,struct sdhci_slot * slot,bus_size_t off,uint16_t val)550 sdhci_fsl_fdt_write_2(device_t dev, struct sdhci_slot *slot, bus_size_t off,
551 uint16_t val)
552 {
553 struct sdhci_fsl_fdt_softc *sc;
554 uint32_t val32;
555
556 sc = device_get_softc(dev);
557
558 switch (off) {
559 case SDHCI_CLOCK_CONTROL:
560 fsl_sdhc_fdt_set_clock(sc, slot, val);
561 return;
562 /*
563 * eSDHC hardware combines command and mode into a single
564 * register. Cache it here, so that command isn't written
565 * until after mode.
566 */
567 case SDHCI_TRANSFER_MODE:
568 sc->cmd_and_mode = val;
569 return;
570 case SDHCI_COMMAND_FLAGS:
571 sc->cmd_and_mode =
572 (sc->cmd_and_mode & UINT16_MAX) | (val << 16);
573 WR4(sc, SDHCI_TRANSFER_MODE, sc->cmd_and_mode);
574 sc->cmd_and_mode = 0;
575 return;
576 case SDHCI_HOST_CONTROL2:
577 /*
578 * Switching to HS400 requires a special procedure,
579 * which is done in sdhci_fsl_fdt_set_uhs_timing.
580 */
581 if ((val & SDHCI_CTRL2_UHS_MASK) == SDHCI_CTRL2_MMC_HS400)
582 val &= ~SDHCI_CTRL2_MMC_HS400;
583 default:
584 val32 = RD4(sc, off & ~3);
585 val32 &= ~(UINT16_MAX << (off & 3) * 8);
586 val32 |= ((val & UINT16_MAX) << (off & 3) * 8);
587 WR4(sc, off & ~3, val32);
588 return;
589 }
590 }
591
592 static void
sdhci_fsl_fdt_write_4(device_t dev,struct sdhci_slot * slot,bus_size_t off,uint32_t val)593 sdhci_fsl_fdt_write_4(device_t dev, struct sdhci_slot *slot, bus_size_t off,
594 uint32_t val)
595 {
596 struct sdhci_fsl_fdt_softc *sc;
597
598 sc = device_get_softc(dev);
599
600 switch (off) {
601 case SDHCI_BUFFER:
602 bus_write_4(sc->mem_res, off, val);
603 return;
604 /*
605 * eSDHC hardware lacks support for the SDMA buffer boundary
606 * feature and instead generates SDHCI_INT_DMA_END interrupts
607 * after each completed DMA data transfer.
608 * Since this duplicates the SDHCI_INT_DATA_END functionality,
609 * mask out the unneeded SDHCI_INT_DMA_END interrupt.
610 */
611 case SDHCI_INT_ENABLE:
612 case SDHCI_SIGNAL_ENABLE:
613 val &= ~SDHCI_INT_DMA_END;
614 /* FALLTHROUGH. */
615 default:
616 WR4(sc, off, val);
617 return;
618 }
619 }
620
621 static void
sdhci_fsl_fdt_write_multi_4(device_t dev,struct sdhci_slot * slot,bus_size_t off,uint32_t * data,bus_size_t count)622 sdhci_fsl_fdt_write_multi_4(device_t dev, struct sdhci_slot *slot,
623 bus_size_t off, uint32_t *data, bus_size_t count)
624 {
625 struct sdhci_fsl_fdt_softc *sc;
626
627 sc = device_get_softc(dev);
628 bus_write_multi_4(sc->mem_res, off, data, count);
629 }
630
631 static void
sdhci_fsl_fdt_irq(void * arg)632 sdhci_fsl_fdt_irq(void *arg)
633 {
634 struct sdhci_fsl_fdt_softc *sc;
635
636 sc = arg;
637 sdhci_generic_intr(&sc->slot);
638 return;
639 }
640
641 static int
sdhci_fsl_fdt_update_ios(device_t brdev,device_t reqdev)642 sdhci_fsl_fdt_update_ios(device_t brdev, device_t reqdev)
643 {
644 int err;
645 struct sdhci_fsl_fdt_softc *sc;
646 struct mmc_ios *ios;
647 struct sdhci_slot *slot;
648
649 err = sdhci_generic_update_ios(brdev, reqdev);
650 if (err != 0)
651 return (err);
652
653 sc = device_get_softc(brdev);
654 slot = device_get_ivars(reqdev);
655 ios = &slot->host.ios;
656
657 switch (ios->power_mode) {
658 case power_on:
659 break;
660 case power_off:
661 if (bootverbose)
662 device_printf(sc->dev, "Powering down sd/mmc\n");
663
664 if (sc->fdt_helper.vmmc_supply)
665 regulator_disable(sc->fdt_helper.vmmc_supply);
666 if (sc->fdt_helper.vqmmc_supply)
667 regulator_disable(sc->fdt_helper.vqmmc_supply);
668 break;
669 case power_up:
670 if (bootverbose)
671 device_printf(sc->dev, "Powering up sd/mmc\n");
672
673 if (sc->fdt_helper.vmmc_supply)
674 regulator_enable(sc->fdt_helper.vmmc_supply);
675 if (sc->fdt_helper.vqmmc_supply)
676 regulator_enable(sc->fdt_helper.vqmmc_supply);
677 break;
678 };
679
680 return (0);
681 }
682
683 static int
sdhci_fsl_fdt_switch_syscon_voltage(device_t dev,struct sdhci_fsl_fdt_softc * sc,enum mmc_vccq vccq)684 sdhci_fsl_fdt_switch_syscon_voltage(device_t dev,
685 struct sdhci_fsl_fdt_softc *sc, enum mmc_vccq vccq)
686 {
687 struct syscon *syscon;
688 phandle_t syscon_node;
689 uint32_t reg;
690
691 if (sc->soc_data->syscon_compat == NULL) {
692 device_printf(dev, "Empty syscon compat string.\n");
693 return (ENXIO);
694 }
695
696 syscon_node = ofw_bus_find_compatible(OF_finddevice("/"),
697 sc->soc_data->syscon_compat);
698
699 if (syscon_get_by_ofw_node(dev, syscon_node, &syscon) != 0) {
700 device_printf(dev, "Could not find syscon node.\n");
701 return (ENXIO);
702 }
703
704 reg = SYSCON_READ_4(syscon, SCFG_SDHCIOVSELCR);
705 reg &= ~SCFG_SDHCIOVSELCR_VSELVAL_MASK;
706 reg |= SCFG_SDHCIOVSELCR_TGLEN;
707
708 switch (vccq) {
709 case vccq_180:
710 reg |= SCFG_SDHCIOVSELCR_VSELVAL_1_8;
711 SYSCON_WRITE_4(syscon, SCFG_SDHCIOVSELCR, reg);
712
713 DELAY(5000);
714
715 reg = SYSCON_READ_4(syscon, SCFG_SDHCIOVSELCR);
716 reg |= SCFG_SDHCIOVSELCR_VS;
717 break;
718 case vccq_330:
719 reg |= SCFG_SDHCIOVSELCR_VSELVAL_3_3;
720 SYSCON_WRITE_4(syscon, SCFG_SDHCIOVSELCR, reg);
721
722 DELAY(5000);
723
724 reg = SYSCON_READ_4(syscon, SCFG_SDHCIOVSELCR);
725 reg &= ~SCFG_SDHCIOVSELCR_VS;
726 break;
727 default:
728 device_printf(dev, "Unsupported voltage requested.\n");
729 return (ENXIO);
730 }
731
732 SYSCON_WRITE_4(syscon, SCFG_SDHCIOVSELCR, reg);
733
734 return (0);
735 }
736
737 static int
sdhci_fsl_fdt_switch_vccq(device_t brdev,device_t reqdev)738 sdhci_fsl_fdt_switch_vccq(device_t brdev, device_t reqdev)
739 {
740 struct sdhci_fsl_fdt_softc *sc;
741 struct sdhci_slot *slot;
742 regulator_t vqmmc_supply;
743 uint32_t val_old, val;
744 int uvolt, err = 0;
745
746 sc = device_get_softc(brdev);
747 slot = device_get_ivars(reqdev);
748
749 val_old = val = RD4(sc, SDHCI_FSL_PROT_CTRL);
750
751 switch (slot->host.ios.vccq) {
752 case vccq_180:
753 if (sc->soc_data->errata & SDHCI_FSL_UNSUPP_1_8V)
754 return (EOPNOTSUPP);
755
756 val |= SDHCI_FSL_PROT_CTRL_VOLT_SEL;
757 uvolt = 1800000;
758 break;
759 case vccq_330:
760 val &= ~SDHCI_FSL_PROT_CTRL_VOLT_SEL;
761 uvolt = 3300000;
762 break;
763 default:
764 return (EOPNOTSUPP);
765 }
766
767 WR4(sc, SDHCI_FSL_PROT_CTRL, val);
768
769 if (sc->soc_data->errata & SDHCI_FSL_MISSING_VCCQ_REG) {
770 err = sdhci_fsl_fdt_switch_syscon_voltage(brdev, sc,
771 slot->host.ios.vccq);
772 if (err != 0)
773 goto vccq_fail;
774 }
775
776 vqmmc_supply = sc->fdt_helper.vqmmc_supply;
777 /*
778 * Even though we expect to find a fixed regulator in this controller
779 * family, let's play safe.
780 */
781 if (vqmmc_supply != NULL) {
782 err = regulator_set_voltage(vqmmc_supply, uvolt, uvolt);
783 if (err != 0)
784 goto vccq_fail;
785 }
786
787 return (0);
788
789 vccq_fail:
790 device_printf(sc->dev, "Cannot set vqmmc to %d<->%d\n", uvolt, uvolt);
791 WR4(sc, SDHCI_FSL_PROT_CTRL, val_old);
792
793 return (err);
794 }
795
796 static int
sdhci_fsl_fdt_get_ro(device_t bus,device_t child)797 sdhci_fsl_fdt_get_ro(device_t bus, device_t child)
798 {
799 struct sdhci_fsl_fdt_softc *sc;
800
801 sc = device_get_softc(bus);
802 return (sdhci_fdt_gpio_get_readonly(sc->gpio));
803 }
804
805 static bool
sdhci_fsl_fdt_get_card_present(device_t dev,struct sdhci_slot * slot)806 sdhci_fsl_fdt_get_card_present(device_t dev, struct sdhci_slot *slot)
807 {
808 struct sdhci_fsl_fdt_softc *sc;
809
810 sc = device_get_softc(dev);
811 return (sdhci_fdt_gpio_get_present(sc->gpio));
812 }
813
814 static uint32_t
sdhci_fsl_fdt_vddrange_to_mask(device_t dev,uint32_t * vdd_ranges,int len)815 sdhci_fsl_fdt_vddrange_to_mask(device_t dev, uint32_t *vdd_ranges, int len)
816 {
817 uint32_t vdd_min, vdd_max;
818 uint32_t vdd_mask = 0;
819 int i;
820
821 /* Ranges are organized as pairs of values. */
822 if ((len % 2) != 0) {
823 device_printf(dev, "Invalid voltage range\n");
824 return (0);
825 }
826 len = len / 2;
827
828 for (i = 0; i < len; i++) {
829 vdd_min = vdd_ranges[2 * i];
830 vdd_max = vdd_ranges[2 * i + 1];
831
832 if (vdd_min > vdd_max || vdd_min < 1650 || vdd_min > 3600 ||
833 vdd_max < 1650 || vdd_max > 3600) {
834 device_printf(dev, "Voltage range %d - %d is out of bounds\n",
835 vdd_min, vdd_max);
836 return (0);
837 }
838
839 if (vdd_min <= 1800 && vdd_max >= 1800)
840 vdd_mask |= SDHCI_CAN_VDD_180;
841 if (vdd_min <= 3000 && vdd_max >= 3000)
842 vdd_mask |= SDHCI_CAN_VDD_300;
843 if (vdd_min <= 3300 && vdd_max >= 3300)
844 vdd_mask |= SDHCI_CAN_VDD_330;
845 }
846
847 return (vdd_mask);
848 }
849
850 static void
sdhci_fsl_fdt_of_parse(device_t dev)851 sdhci_fsl_fdt_of_parse(device_t dev)
852 {
853 struct sdhci_fsl_fdt_softc *sc;
854 phandle_t node;
855 pcell_t *voltage_ranges;
856 uint32_t vdd_mask = 0;
857 ssize_t num_ranges;
858
859 sc = device_get_softc(dev);
860 node = ofw_bus_get_node(dev);
861
862 /* Call mmc_fdt_parse in order to get mmc related properties. */
863 mmc_fdt_parse(dev, node, &sc->fdt_helper, &sc->slot.host);
864
865 sc->slot.quirks |= SDHCI_QUIRK_MISSING_CAPS;
866 sc->slot.caps = sdhci_fsl_fdt_read_4(dev, &sc->slot,
867 SDHCI_CAPABILITIES) & ~(SDHCI_CAN_DO_SUSPEND);
868 sc->slot.caps2 = sdhci_fsl_fdt_read_4(dev, &sc->slot,
869 SDHCI_CAPABILITIES2);
870
871 /* Parse the "voltage-ranges" dts property. */
872 num_ranges = OF_getencprop_alloc(node, "voltage-ranges",
873 (void **) &voltage_ranges);
874 if (num_ranges <= 0)
875 return;
876 vdd_mask = sdhci_fsl_fdt_vddrange_to_mask(dev, voltage_ranges,
877 num_ranges / sizeof(uint32_t));
878 OF_prop_free(voltage_ranges);
879
880 /* Overwrite voltage caps only if we got something from dts. */
881 if (vdd_mask != 0 &&
882 (vdd_mask != (sc->slot.caps & SDHCI_FSL_CAN_VDD_MASK))) {
883 sc->slot.caps &= ~(SDHCI_FSL_CAN_VDD_MASK);
884 sc->slot.caps |= vdd_mask;
885 }
886 }
887
888 static int
sdhci_fsl_poll_register(struct sdhci_fsl_fdt_softc * sc,uint32_t reg,uint32_t mask,int value)889 sdhci_fsl_poll_register(struct sdhci_fsl_fdt_softc *sc,
890 uint32_t reg, uint32_t mask, int value)
891 {
892 int retries;
893
894 retries = SDHCI_FSL_MAX_RETRIES;
895
896 while ((RD4(sc, reg) & mask) != value) {
897 if (!retries--)
898 return (ENXIO);
899
900 DELAY(10);
901 }
902
903 return (0);
904 }
905
906 static int
sdhci_fsl_fdt_attach(device_t dev)907 sdhci_fsl_fdt_attach(device_t dev)
908 {
909 struct sdhci_fsl_fdt_softc *sc;
910 struct mmc_host *host;
911 uint32_t val;
912 uintptr_t ocd_data;
913 uint64_t clk_hz;
914 phandle_t node;
915 int rid, ret;
916 clk_t clk;
917
918 node = ofw_bus_get_node(dev);
919 sc = device_get_softc(dev);
920 ocd_data = ofw_bus_search_compatible(dev,
921 sdhci_fsl_fdt_compat_data)->ocd_data;
922 sc->dev = dev;
923 sc->flags = 0;
924 host = &sc->slot.host;
925 rid = 0;
926
927 /*
928 * LX2160A needs its own soc_data in order to apply SoC
929 * specific quriks. Since the controller is identified
930 * only with a generic compatible string we need to do this dance here.
931 */
932 if (ofw_bus_node_is_compatible(OF_finddevice("/"), "fsl,lx2160a"))
933 sc->soc_data = &sdhci_fsl_fdt_lx2160a_soc_data;
934 else
935 sc->soc_data = (struct sdhci_fsl_fdt_soc_data *)ocd_data;
936
937 sc->slot.quirks = sc->soc_data->quirks;
938 sc->slot.quirks &= ~sdhci_quirk_clear;
939 sc->slot.quirks |= sdhci_quirk_set;
940
941 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
942 RF_ACTIVE);
943 if (sc->mem_res == NULL) {
944 device_printf(dev,
945 "Could not allocate resources for controller\n");
946 return (ENOMEM);
947 }
948
949 rid = 0;
950 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
951 RF_ACTIVE);
952 if (sc->irq_res == NULL) {
953 device_printf(dev,
954 "Could not allocate irq resources for controller\n");
955 ret = ENOMEM;
956 goto err_free_mem;
957 }
958
959 ret = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_BIO | INTR_MPSAFE,
960 NULL, sdhci_fsl_fdt_irq, sc, &sc->irq_cookie);
961 if (ret != 0) {
962 device_printf(dev, "Could not setup IRQ handler\n");
963 goto err_free_irq_res;
964 }
965
966 ret = clk_get_by_ofw_index(dev, node, 0, &clk);
967 if (ret == 0) {
968 ret = clk_get_freq(clk, &clk_hz);
969 if (ret != 0) {
970 device_printf(dev,
971 "Could not get parent clock frequency\n");
972 goto err_free_irq;
973 }
974 } else {
975 pcell_t freq;
976
977 /*
978 * No clocks phandle; fall back to the "clock-frequency" DT
979 * property. Boards without a clock provider (e.g. PowerPC
980 * QorIQ) supply the eSDHC input clock this way.
981 */
982 if (OF_getencprop(node, "clock-frequency", &freq,
983 sizeof(freq)) <= 0) {
984 device_printf(dev, "no parent clock available\n");
985 ret = ENXIO;
986 goto err_free_irq;
987 }
988 clk_hz = freq;
989 }
990
991 sc->baseclk_hz = clk_hz / sc->soc_data->baseclk_div;
992
993 /* Figure out eSDHC block endianness before we touch any HW regs. */
994 if (OF_hasprop(node, "little-endian")) {
995 sc->read = read_le;
996 sc->write = write_le;
997 sc->buf_order = SDHCI_FSL_PROT_CTRL_BYTE_NATIVE;
998 } else {
999 sc->read = read_be;
1000 sc->write = write_be;
1001 sc->buf_order = SDHCI_FSL_PROT_CTRL_BYTE_SWAP;
1002 }
1003
1004 sc->vendor_ver = (RD4(sc, SDHCI_FSL_HOST_VERSION) &
1005 SDHCI_VENDOR_VER_MASK) >> SDHCI_VENDOR_VER_SHIFT;
1006
1007 sdhci_fsl_fdt_of_parse(dev);
1008 sc->maxclk_hz = host->f_max ? host->f_max : sc->baseclk_hz;
1009
1010 /*
1011 * Setting this register affects byte order in SDHCI_BUFFER only.
1012 * If the eSDHC block is connected over a big-endian bus, the data
1013 * read from/written to the buffer will be already byte swapped.
1014 * In such a case, setting SDHCI_FSL_PROT_CTRL_BYTE_SWAP will convert
1015 * the byte order again, resulting in a native byte order.
1016 * The read/write callbacks accommodate for this behavior.
1017 */
1018 val = RD4(sc, SDHCI_FSL_PROT_CTRL);
1019 val &= ~SDHCI_FSL_PROT_CTRL_BYTE_MASK;
1020 WR4(sc, SDHCI_FSL_PROT_CTRL, val | sc->buf_order);
1021
1022 /*
1023 * Gate the SD clock and set its source to
1024 * peripheral clock / baseclk_div. The frequency in baseclk_hz is set
1025 * to match this.
1026 */
1027 val = RD4(sc, SDHCI_CLOCK_CONTROL);
1028 WR4(sc, SDHCI_CLOCK_CONTROL, val & ~SDHCI_FSL_CLK_SDCLKEN);
1029 val = RD4(sc, SDHCI_FSL_ESDHC_CTRL);
1030 if (!(sc->soc_data->errata & SDHCI_FSL_NO_PCS_SEL))
1031 val |= SDHCI_FSL_ESDHC_CTRL_CLK_DIV2;
1032 /*
1033 * Enable DMA snooping when the SoC is known to be cache-coherent
1034 * (soc_data errata bit) or the DTS explicitly declares it. Without
1035 * snoop the CPU cache holds stale copies of DMA'd data and reads
1036 * return garbage even though bus_dmamap_sync completes cleanly.
1037 */
1038 if ((sc->soc_data->errata & SDHCI_FSL_DMA_SNOOP) ||
1039 OF_hasprop(node, "dma-coherent"))
1040 val |= SDHCI_FSL_ESDHC_CTRL_SNOOP;
1041 WR4(sc, SDHCI_FSL_ESDHC_CTRL, val);
1042 sc->slot.max_clk = sc->maxclk_hz;
1043 sc->gpio = sdhci_fdt_gpio_setup(dev, &sc->slot);
1044
1045 /*
1046 * Set the buffer watermark level to 128 words (512 bytes) for both
1047 * read and write. The hardware has a restriction that when the read or
1048 * write ready status is asserted, that means you can read exactly the
1049 * number of words set in the watermark register before you have to
1050 * re-check the status and potentially wait for more data. The main
1051 * sdhci driver provides no hook for doing status checking on less than
1052 * a full block boundary, so we set the watermark level to be a full
1053 * block. Reads and writes where the block size is less than the
1054 * watermark size will work correctly too, no need to change the
1055 * watermark for different size blocks. However, 128 is the maximum
1056 * allowed for the watermark, so PIO is limitted to 512 byte blocks.
1057 */
1058 WR4(sc, SDHCI_FSL_WTMK_LVL,
1059 sc->soc_data->wml_value != 0 ? sc->soc_data->wml_value :
1060 (SDHCI_FSL_WTMK_WR_512B | SDHCI_FSL_WTMK_RD_512B));
1061
1062 ret = sdhci_init_slot(dev, &sc->slot, 0);
1063 if (ret != 0)
1064 goto err_free_gpio;
1065 sc->slot_init_done = true;
1066 sdhci_start_slot(&sc->slot);
1067
1068 bus_attach_children(dev);
1069 return (0);
1070
1071 err_free_gpio:
1072 sdhci_fdt_gpio_teardown(sc->gpio);
1073 err_free_irq:
1074 bus_teardown_intr(dev, sc->irq_res, sc->irq_cookie);
1075 err_free_irq_res:
1076 bus_free_resource(dev, SYS_RES_IRQ, sc->irq_res);
1077 err_free_mem:
1078 bus_free_resource(dev, SYS_RES_MEMORY, sc->mem_res);
1079 return (ret);
1080 }
1081
1082 static int
sdhci_fsl_fdt_detach(device_t dev)1083 sdhci_fsl_fdt_detach(device_t dev)
1084 {
1085 struct sdhci_fsl_fdt_softc *sc;
1086
1087 sc = device_get_softc(dev);
1088 if (sc->slot_init_done)
1089 sdhci_cleanup_slot(&sc->slot);
1090 if (sc->gpio != NULL)
1091 sdhci_fdt_gpio_teardown(sc->gpio);
1092 if (sc->irq_cookie != NULL)
1093 bus_teardown_intr(dev, sc->irq_res, sc->irq_cookie);
1094 if (sc->irq_res != NULL)
1095 bus_free_resource(dev, SYS_RES_IRQ, sc->irq_res);
1096 if (sc->mem_res != NULL)
1097 bus_free_resource(dev, SYS_RES_MEMORY, sc->mem_res);
1098 return (0);
1099 }
1100
1101 static int
sdhci_fsl_fdt_probe(device_t dev)1102 sdhci_fsl_fdt_probe(device_t dev)
1103 {
1104 const struct ofw_compat_data *ocd;
1105
1106 if (!ofw_bus_status_okay(dev))
1107 return (ENXIO);
1108
1109 ocd = ofw_bus_search_compatible(dev, sdhci_fsl_fdt_compat_data);
1110 if (ocd->ocd_data == 0)
1111 return (ENXIO);
1112
1113 device_set_desc(dev, "NXP QorIQ Layerscape eSDHC controller");
1114
1115 return (BUS_PROBE_DEFAULT);
1116 }
1117
1118 static int
sdhci_fsl_fdt_read_ivar(device_t bus,device_t child,int which,uintptr_t * result)1119 sdhci_fsl_fdt_read_ivar(device_t bus, device_t child, int which,
1120 uintptr_t *result)
1121 {
1122 struct sdhci_slot *slot = device_get_ivars(child);
1123
1124 if (which == MMCBR_IVAR_MAX_DATA && (slot->opt & SDHCI_HAVE_DMA)) {
1125 /*
1126 * In the absence of SDMA buffer boundary functionality,
1127 * limit the maximum data length per read/write command
1128 * to bounce buffer size.
1129 */
1130 *result = howmany(slot->sdma_bbufsz, 512);
1131 return (0);
1132 }
1133 return (sdhci_generic_read_ivar(bus, child, which, result));
1134 }
1135
1136 static int
sdhci_fsl_fdt_write_ivar(device_t bus,device_t child,int which,uintptr_t value)1137 sdhci_fsl_fdt_write_ivar(device_t bus, device_t child, int which,
1138 uintptr_t value)
1139 {
1140 struct sdhci_fsl_fdt_softc *sc;
1141 struct sdhci_slot *slot = device_get_ivars(child);
1142 uint32_t prescale, div;
1143
1144 /* Don't depend on clock resolution limits from sdhci core. */
1145 if (which == MMCBR_IVAR_CLOCK) {
1146 if (value == 0) {
1147 slot->host.ios.clock = 0;
1148 return (0);
1149 }
1150
1151 sc = device_get_softc(bus);
1152
1153 SDHCI_FSL_FDT_CLK_DIV(sc, sc->baseclk_hz, value, prescale, div);
1154 slot->host.ios.clock = sc->baseclk_hz / (prescale * div);
1155
1156 return (0);
1157 }
1158
1159 return (sdhci_generic_write_ivar(bus, child, which, value));
1160 }
1161
1162 static void
sdhci_fsl_fdt_reset(device_t dev,struct sdhci_slot * slot,uint8_t mask)1163 sdhci_fsl_fdt_reset(device_t dev, struct sdhci_slot *slot, uint8_t mask)
1164 {
1165 struct sdhci_fsl_fdt_softc *sc;
1166 uint32_t val;
1167
1168 sdhci_generic_reset(dev, slot, mask);
1169
1170 if (!(mask & SDHCI_RESET_ALL))
1171 return;
1172
1173 sc = device_get_softc(dev);
1174
1175 /*
1176 * RESET_ALL clears PROT_CTRL and WML. Re-apply the byte-order
1177 * mode determined at attach and the block-size watermark so that
1178 * SDHCI_BUFFER accesses continue to match host bus endianness and
1179 * PIO reads/writes see BREN/BWEN asserted at 512-byte block
1180 * boundaries. Neither is restored by the generic reset path.
1181 */
1182 val = RD4(sc, SDHCI_FSL_PROT_CTRL);
1183 val &= ~SDHCI_FSL_PROT_CTRL_BYTE_MASK;
1184 WR4(sc, SDHCI_FSL_PROT_CTRL, val | sc->buf_order);
1185 WR4(sc, SDHCI_FSL_WTMK_LVL,
1186 sc->soc_data->wml_value != 0 ? sc->soc_data->wml_value :
1187 (SDHCI_FSL_WTMK_WR_512B | SDHCI_FSL_WTMK_RD_512B));
1188
1189 /*
1190 * ESDHCCTL[SNOOP] also does not survive RESET_ALL. Re-enable it if
1191 * the SoC needs cache-coherent DMA (see attach for the source of
1192 * truth).
1193 */
1194 if ((sc->soc_data->errata & SDHCI_FSL_DMA_SNOOP) ||
1195 OF_hasprop(ofw_bus_get_node(dev), "dma-coherent")) {
1196 val = RD4(sc, SDHCI_FSL_ESDHC_CTRL);
1197 val |= SDHCI_FSL_ESDHC_CTRL_SNOOP;
1198 WR4(sc, SDHCI_FSL_ESDHC_CTRL, val);
1199 }
1200
1201 /* Some registers have to be cleared by hand. */
1202 if (slot->version >= SDHCI_SPEC_300) {
1203 val = RD4(sc, SDHCI_FSL_TBCTL);
1204 val &= ~SDHCI_FSL_TBCTL_TBEN;
1205 WR4(sc, SDHCI_FSL_TBCTL, val);
1206 }
1207
1208 /*
1209 * Pulse width detection is not reliable on some boards. Perform
1210 * workaround by clearing register's bit according to errata.
1211 */
1212 if (sc->soc_data->errata & SDHCI_FSL_UNRELIABLE_PULSE_DET) {
1213 val = RD4(sc, SDHCI_FSL_DLLCFG1);
1214 val &= ~SDHCI_FSL_DLLCFG1_PULSE_STRETCH;
1215 WR4(sc, SDHCI_FSL_DLLCFG1, val);
1216 }
1217
1218 sc->flags = 0;
1219 }
1220
1221 static void
sdhci_fsl_switch_tuning_block(device_t dev,bool enable)1222 sdhci_fsl_switch_tuning_block(device_t dev, bool enable)
1223 {
1224 struct sdhci_fsl_fdt_softc *sc;
1225 uint32_t reg;
1226
1227 sc = device_get_softc(dev);
1228
1229 reg = RD4(sc, SDHCI_FSL_TBCTL);
1230
1231 if (enable)
1232 reg |= SDHCI_FSL_TBCTL_TBEN;
1233 else
1234 reg &= ~SDHCI_FSL_TBCTL_TBEN;
1235
1236 WR4(sc, SDHCI_FSL_TBCTL, reg);
1237 }
1238
1239 static int
sdhci_fsl_sw_tuning(struct sdhci_fsl_fdt_softc * sc,device_t bus,device_t child,bool hs400,uint32_t wnd_start,uint32_t wnd_end)1240 sdhci_fsl_sw_tuning(struct sdhci_fsl_fdt_softc *sc, device_t bus,
1241 device_t child, bool hs400, uint32_t wnd_start, uint32_t wnd_end)
1242 {
1243 uint32_t reg;
1244 int error;
1245
1246 if (sc->soc_data->errata & SDHCI_FSL_TUNING_ERRATUM_TYPE1 ||
1247 abs(wnd_start - wnd_end) <= (4 * sc->div_ratio + 2)) {
1248 wnd_start = 5 * sc->div_ratio;
1249 wnd_end = 3 * sc->div_ratio;
1250 } else {
1251 wnd_start = 8 * sc->div_ratio;
1252 wnd_end = 4 * sc->div_ratio;
1253 }
1254
1255 reg = RD4(sc, SDHCI_FSL_TBPTR);
1256 reg &= ~SDHCI_FSL_TBPTR_WND_MASK;
1257 reg &= ~(SDHCI_FSL_TBPTR_WND_MASK << SDHCI_FSL_TBPTR_WND_START_SHIFT);
1258 reg |= wnd_start << SDHCI_FSL_TBPTR_WND_START_SHIFT;
1259 reg |= wnd_end;
1260 WR4(sc, SDHCI_FSL_TBPTR, reg);
1261
1262 /*
1263 * Normally those are supposed to be set in sdhci_execute_tuning.
1264 * However in our case we need a small delay between setting the two.
1265 */
1266 reg = RD4(sc, SDHCI_FSL_AUTOCERR);
1267 reg |= SDHCI_FSL_AUTOCERR_EXTN;
1268 WR4(sc, SDHCI_FSL_AUTOCERR, reg);
1269 DELAY(10);
1270 reg |= SDHCI_FSL_AUTOCERR_SMPCLKSEL;
1271 WR4(sc, SDHCI_FSL_AUTOCERR, reg);
1272
1273 reg = RD4(sc, SDHCI_FSL_TBCTL);
1274 reg &= ~SDHCI_FSL_TBCTL_TB_MODE_MASK;
1275 reg |= SDHCI_FSL_TBCTL_MODE_SW;
1276 WR4(sc, SDHCI_FSL_TBCTL, reg);
1277
1278 error = sdhci_generic_tune(bus, child, hs400);
1279 if (error != 0) {
1280 device_printf(bus,
1281 "Failed to execute generic tune while performing software tuning.\n");
1282 }
1283
1284 return (error);
1285 }
1286
1287 static int
sdhci_fsl_fdt_tune(device_t bus,device_t child,bool hs400)1288 sdhci_fsl_fdt_tune(device_t bus, device_t child, bool hs400)
1289 {
1290 struct sdhci_fsl_fdt_softc *sc;
1291 uint32_t wnd_start, wnd_end;
1292 uint32_t clk_divider, reg;
1293 struct sdhci_slot *slot;
1294 int error;
1295
1296 sc = device_get_softc(bus);
1297 slot = device_get_ivars(child);
1298
1299 if (sc->slot.host.ios.timing == bus_timing_uhs_sdr50 &&
1300 !(slot->opt & SDHCI_SDR50_NEEDS_TUNING))
1301 return (0);
1302
1303 /*
1304 * For tuning mode SD clock divider must be within 3 to 16.
1305 * We also need to match the frequency to whatever mode is used.
1306 * For that reason we're just bailing if the dividers don't match
1307 * that requirement.
1308 */
1309 clk_divider = sc->baseclk_hz / slot->clock;
1310 if (clk_divider < 3 || clk_divider > 16)
1311 return (ENXIO);
1312
1313 if (hs400)
1314 sc->flags |= SDHCI_FSL_HS400_FLAG;
1315
1316 /* Disable clock. */
1317 fsl_sdhc_fdt_set_clock(sc, slot, sc->sdclk_bits);
1318
1319 /* Wait for PRSSTAT[SDSTB] to be set by hardware. */
1320 error = sdhci_fsl_poll_register(sc, SDHCI_FSL_PRES_STATE,
1321 SDHCI_FSL_PRES_SDSTB, SDHCI_FSL_PRES_SDSTB);
1322 if (error != 0)
1323 device_printf(bus,
1324 "Timeout while waiting for clock to stabilize.\n");
1325
1326 /* Flush async IO. */
1327 reg = RD4(sc, SDHCI_FSL_ESDHC_CTRL);
1328 reg |= SDHCI_FSL_ESDHC_CTRL_FAF;
1329 WR4(sc, SDHCI_FSL_ESDHC_CTRL, reg);
1330
1331 /* Wait for ESDHC[FAF] to be cleared by hardware. */
1332 error = sdhci_fsl_poll_register(sc, SDHCI_FSL_ESDHC_CTRL,
1333 SDHCI_FSL_ESDHC_CTRL_FAF, 0);
1334 if (error)
1335 device_printf(bus,
1336 "Timeout while waiting for hardware.\n");
1337
1338 /*
1339 * Set TBCTL[TB_EN] register and program valid tuning mode.
1340 * According to RM MODE_3 means that:
1341 * "eSDHC takes care of the re-tuning during data transfer
1342 * (auto re-tuning).".
1343 * Tuning mode can only be changed while the clock is disabled.
1344 */
1345 reg = RD4(sc, SDHCI_FSL_TBCTL);
1346 reg &= ~SDHCI_FSL_TBCTL_TB_MODE_MASK;
1347 reg |= SDHCI_FSL_TBCTL_TBEN | SDHCI_FSL_TBCTL_MODE_3;
1348 WR4(sc, SDHCI_FSL_TBCTL, reg);
1349
1350 /* Enable clock. */
1351 fsl_sdhc_fdt_set_clock(sc, slot, SDHCI_CLOCK_CARD_EN | sc->sdclk_bits);
1352
1353 /* Wait for clock to stabilize. */
1354 error = sdhci_fsl_poll_register(sc, SDHCI_FSL_PRES_STATE,
1355 SDHCI_FSL_PRES_SDSTB, SDHCI_FSL_PRES_SDSTB);
1356 if (error)
1357 device_printf(bus,
1358 "Timeout while waiting for clock to stabilize.\n");
1359
1360 /* Perform hardware tuning. */
1361 error = sdhci_generic_tune(bus, child, hs400);
1362
1363 reg = RD4(sc, SDHCI_FSL_TBPTR);
1364 wnd_start = reg >> SDHCI_FSL_TBPTR_WND_START_SHIFT;
1365 wnd_start &= SDHCI_FSL_TBPTR_WND_MASK;
1366 wnd_end = reg & SDHCI_FSL_TBPTR_WND_MASK;
1367
1368 /*
1369 * For erratum type2 affected platforms, the controller can erroneously
1370 * declare that the tuning was successful. Verify the tuning window to
1371 * make sure that we're fine.
1372 */
1373 if (error == 0 &&
1374 sc->soc_data->errata & SDHCI_FSL_TUNING_ERRATUM_TYPE2 &&
1375 abs(wnd_start - wnd_end) > (4 * sc->div_ratio + 2)) {
1376 error = EIO;
1377 }
1378
1379 /* If hardware tuning failed, try software tuning. */
1380 if (error != 0 &&
1381 (sc->soc_data->errata &
1382 (SDHCI_FSL_TUNING_ERRATUM_TYPE1 |
1383 SDHCI_FSL_TUNING_ERRATUM_TYPE2))) {
1384 error = sdhci_fsl_sw_tuning(sc, bus, child, hs400, wnd_start,
1385 wnd_end);
1386 if (error != 0)
1387 device_printf(bus, "Software tuning failed.\n");
1388 }
1389
1390 if (error != 0) {
1391 sdhci_fsl_switch_tuning_block(bus, false);
1392 return (error);
1393 }
1394 if (hs400) {
1395 reg = RD4(sc, SDHCI_FSL_SDTIMINGCTL);
1396 reg |= SDHCI_FSL_SDTIMINGCTL_FLW_CTL;
1397 WR4(sc, SDHCI_FSL_SDTIMINGCTL, reg);
1398 }
1399
1400 return (0);
1401 }
1402
1403 static int
sdhci_fsl_fdt_retune(device_t bus,device_t child,bool reset)1404 sdhci_fsl_fdt_retune(device_t bus, device_t child, bool reset)
1405 {
1406 struct sdhci_slot *slot;
1407 struct sdhci_fsl_fdt_softc *sc;
1408
1409 slot = device_get_ivars(child);
1410 sc = device_get_softc(bus);
1411
1412 if (!(slot->opt & SDHCI_TUNING_ENABLED))
1413 return (0);
1414
1415 /* HS400 must be tuned in HS200 mode. */
1416 if (slot->host.ios.timing == bus_timing_mmc_hs400)
1417 return (EINVAL);
1418
1419 /*
1420 * Only re-tuning with full reset is supported.
1421 * The controller is normally put in "mode 3", which means that
1422 * periodic re-tuning is done automatically. See comment in
1423 * sdhci_fsl_fdt_tune for details.
1424 * Because of that re-tuning should only be triggered as a result
1425 * of a CRC error.
1426 */
1427 if (!reset)
1428 return (ENOTSUP);
1429
1430 return (sdhci_fsl_fdt_tune(bus, child,
1431 sc->flags & SDHCI_FSL_HS400_FLAG));
1432 }
1433 static void
sdhci_fsl_disable_hs400_mode(device_t dev,struct sdhci_fsl_fdt_softc * sc)1434 sdhci_fsl_disable_hs400_mode(device_t dev, struct sdhci_fsl_fdt_softc *sc)
1435 {
1436 uint32_t reg;
1437 int error;
1438
1439 /* Check if HS400 is enabled right now. */
1440 reg = RD4(sc, SDHCI_FSL_TBCTL);
1441 if ((reg & SDHCI_FSL_TBCTL_HS400_EN) == 0)
1442 return;
1443
1444 reg = RD4(sc, SDHCI_FSL_SDTIMINGCTL);
1445 reg &= ~SDHCI_FSL_SDTIMINGCTL_FLW_CTL;
1446 WR4(sc, SDHCI_FSL_SDTIMINGCTL, reg);
1447
1448 reg = RD4(sc, SDHCI_FSL_SDCLKCTL);
1449 reg &= ~SDHCI_FSL_SDCLKCTL_CMD_CLK_CTL;
1450 WR4(sc, SDHCI_FSL_SDCLKCTL, reg);
1451
1452 fsl_sdhc_fdt_set_clock(sc, &sc->slot, sc->sdclk_bits);
1453 error = sdhci_fsl_poll_register(sc, SDHCI_FSL_PRES_STATE,
1454 SDHCI_FSL_PRES_SDSTB, SDHCI_FSL_PRES_SDSTB);
1455 if (error != 0)
1456 device_printf(dev,
1457 "Internal clock never stabilized.\n");
1458
1459 reg = RD4(sc, SDHCI_FSL_TBCTL);
1460 reg &= ~SDHCI_FSL_TBCTL_HS400_EN;
1461 WR4(sc, SDHCI_FSL_TBCTL, reg);
1462
1463 fsl_sdhc_fdt_set_clock(sc, &sc->slot, SDHCI_CLOCK_CARD_EN |
1464 sc->sdclk_bits);
1465
1466 error = sdhci_fsl_poll_register(sc, SDHCI_FSL_PRES_STATE,
1467 SDHCI_FSL_PRES_SDSTB, SDHCI_FSL_PRES_SDSTB);
1468 if (error != 0)
1469 device_printf(dev,
1470 "Internal clock never stabilized.\n");
1471
1472 reg = RD4(sc, SDHCI_FSL_DLLCFG0);
1473 reg &= ~(SDHCI_FSL_DLLCFG0_EN |
1474 SDHCI_FSL_DLLCFG0_FREQ_SEL);
1475 WR4(sc, SDHCI_FSL_DLLCFG0, reg);
1476
1477 reg = RD4(sc, SDHCI_FSL_TBCTL);
1478 reg &= ~SDHCI_FSL_TBCTL_HS400_WND_ADJ;
1479 WR4(sc, SDHCI_FSL_TBCTL, reg);
1480
1481 sdhci_fsl_switch_tuning_block(dev, false);
1482 }
1483
1484 static void
sdhci_fsl_enable_hs400_mode(device_t dev,struct sdhci_slot * slot,struct sdhci_fsl_fdt_softc * sc)1485 sdhci_fsl_enable_hs400_mode(device_t dev, struct sdhci_slot *slot,
1486 struct sdhci_fsl_fdt_softc *sc)
1487 {
1488 uint32_t reg;
1489 int error;
1490
1491 sdhci_fsl_switch_tuning_block(dev, true);
1492 fsl_sdhc_fdt_set_clock(sc, slot, sc->sdclk_bits);
1493
1494 error = sdhci_fsl_poll_register(sc, SDHCI_FSL_PRES_STATE,
1495 SDHCI_FSL_PRES_SDSTB, SDHCI_FSL_PRES_SDSTB);
1496 if (error != 0)
1497 device_printf(dev,
1498 "Timeout while waiting for clock to stabilize.\n");
1499
1500 reg = RD4(sc, SDHCI_FSL_TBCTL);
1501 reg |= SDHCI_FSL_TBCTL_HS400_EN;
1502 WR4(sc, SDHCI_FSL_TBCTL, reg);
1503 reg = RD4(sc, SDHCI_FSL_SDCLKCTL);
1504 reg |= SDHCI_FSL_SDCLKCTL_CMD_CLK_CTL;
1505 WR4(sc, SDHCI_FSL_SDCLKCTL, reg);
1506
1507 fsl_sdhc_fdt_set_clock(sc, slot, SDHCI_CLOCK_CARD_EN |
1508 sc->sdclk_bits);
1509 error = sdhci_fsl_poll_register(sc, SDHCI_FSL_PRES_STATE,
1510 SDHCI_FSL_PRES_SDSTB, SDHCI_FSL_PRES_SDSTB);
1511 if (error != 0)
1512 device_printf(dev,
1513 "Timeout while waiting for clock to stabilize.\n");
1514
1515 reg = RD4(sc, SDHCI_FSL_DLLCFG0);
1516 reg |= SDHCI_FSL_DLLCFG0_EN | SDHCI_FSL_DLLCFG0_RESET |
1517 SDHCI_FSL_DLLCFG0_FREQ_SEL;
1518 WR4(sc, SDHCI_FSL_DLLCFG0, reg);
1519
1520 /*
1521 * The reset bit is not a self clearing one.
1522 * Give it some time and clear it manually.
1523 */
1524 DELAY(100);
1525 reg &= ~SDHCI_FSL_DLLCFG0_RESET;
1526 WR4(sc, SDHCI_FSL_DLLCFG0, reg);
1527
1528 error = sdhci_fsl_poll_register(sc, SDHCI_FSL_DLLSTAT0,
1529 SDHCI_FSL_DLLSTAT0_SLV_STS, SDHCI_FSL_DLLSTAT0_SLV_STS);
1530 if (error != 0)
1531 device_printf(dev,
1532 "Timeout while waiting for DLL0.\n");
1533
1534 reg = RD4(sc, SDHCI_FSL_TBCTL);
1535 reg |= SDHCI_FSL_TBCTL_HS400_WND_ADJ;
1536 WR4(sc, SDHCI_FSL_TBCTL, reg);
1537
1538 fsl_sdhc_fdt_set_clock(sc, slot, sc->sdclk_bits);
1539
1540 error = sdhci_fsl_poll_register(sc, SDHCI_FSL_PRES_STATE,
1541 SDHCI_FSL_PRES_SDSTB, SDHCI_FSL_PRES_SDSTB);
1542 if (error != 0)
1543 device_printf(dev,
1544 "timeout while waiting for clock to stabilize.\n");
1545
1546 reg = RD4(sc, SDHCI_FSL_ESDHC_CTRL);
1547 reg |= SDHCI_FSL_ESDHC_CTRL_FAF;
1548 WR4(sc, SDHCI_FSL_ESDHC_CTRL, reg);
1549
1550 error = sdhci_fsl_poll_register(sc, SDHCI_FSL_ESDHC_CTRL,
1551 SDHCI_FSL_ESDHC_CTRL_FAF, 0);
1552 if (error != 0)
1553 device_printf(dev,
1554 "Timeout while waiting for hardware.\n");
1555
1556 fsl_sdhc_fdt_set_clock(sc, slot, SDHCI_CLOCK_CARD_EN |
1557 sc->sdclk_bits);
1558
1559 error = sdhci_fsl_poll_register(sc, SDHCI_FSL_PRES_STATE,
1560 SDHCI_FSL_PRES_SDSTB, SDHCI_FSL_PRES_SDSTB);
1561 if (error != 0)
1562 device_printf(dev,
1563 "Timeout while waiting for clock to stabilize.\n");
1564 }
1565
1566 static void
sdhci_fsl_fdt_set_uhs_timing(device_t dev,struct sdhci_slot * slot)1567 sdhci_fsl_fdt_set_uhs_timing(device_t dev, struct sdhci_slot *slot)
1568 {
1569 struct sdhci_fsl_fdt_softc *sc;
1570 const struct mmc_ios *ios;
1571 uint32_t mode, reg;
1572
1573 sc = device_get_softc(dev);
1574 ios = &slot->host.ios;
1575 mode = 0;
1576
1577 /*
1578 * When we switch to HS400 this function is called twice.
1579 * First after the timing is set, and then after the clock
1580 * is changed to the target frequency.
1581 * The controller can be switched to HS400 only after the latter
1582 * is done.
1583 */
1584 if (slot->host.ios.timing == bus_timing_mmc_hs400 &&
1585 ios->clock > SD_SDR50_MAX)
1586 sdhci_fsl_enable_hs400_mode(dev, slot, sc);
1587 else if (slot->host.ios.timing < bus_timing_mmc_hs400) {
1588 sdhci_fsl_disable_hs400_mode(dev, sc);
1589
1590 /*
1591 * Switching to HS400 requires a custom procedure executed in
1592 * sdhci_fsl_enable_hs400_mode in case above.
1593 * For all other modes we just need to set the corresponding flag.
1594 */
1595 reg = RD4(sc, SDHCI_FSL_AUTOCERR);
1596 reg &= ~SDHCI_FSL_AUTOCERR_UHMS;
1597 if (ios->clock > SD_SDR50_MAX)
1598 mode = SDHCI_CTRL2_UHS_SDR104;
1599 else if (ios->clock > SD_SDR25_MAX)
1600 mode = SDHCI_CTRL2_UHS_SDR50;
1601 else if (ios->clock > SD_SDR12_MAX) {
1602 if (ios->timing == bus_timing_uhs_ddr50 ||
1603 ios->timing == bus_timing_mmc_ddr52)
1604 mode = SDHCI_CTRL2_UHS_DDR50;
1605 else
1606 mode = SDHCI_CTRL2_UHS_SDR25;
1607 } else if (ios->clock > SD_MMC_CARD_ID_FREQUENCY)
1608 mode = SDHCI_CTRL2_UHS_SDR12;
1609
1610 reg |= mode << SDHCI_FSL_AUTOCERR_UHMS_SHIFT;
1611 WR4(sc, SDHCI_FSL_AUTOCERR, reg);
1612 }
1613 }
1614
1615 static const device_method_t sdhci_fsl_fdt_methods[] = {
1616 /* Device interface. */
1617 DEVMETHOD(device_probe, sdhci_fsl_fdt_probe),
1618 DEVMETHOD(device_attach, sdhci_fsl_fdt_attach),
1619 DEVMETHOD(device_detach, sdhci_fsl_fdt_detach),
1620
1621 /* Bus interface. */
1622 DEVMETHOD(bus_read_ivar, sdhci_fsl_fdt_read_ivar),
1623 DEVMETHOD(bus_write_ivar, sdhci_fsl_fdt_write_ivar),
1624
1625 /* MMC bridge interface. */
1626 DEVMETHOD(mmcbr_request, sdhci_generic_request),
1627 DEVMETHOD(mmcbr_get_ro, sdhci_fsl_fdt_get_ro),
1628 DEVMETHOD(mmcbr_acquire_host, sdhci_generic_acquire_host),
1629 DEVMETHOD(mmcbr_release_host, sdhci_generic_release_host),
1630 DEVMETHOD(mmcbr_switch_vccq, sdhci_fsl_fdt_switch_vccq),
1631 DEVMETHOD(mmcbr_update_ios, sdhci_fsl_fdt_update_ios),
1632 DEVMETHOD(mmcbr_tune, sdhci_fsl_fdt_tune),
1633 DEVMETHOD(mmcbr_retune, sdhci_fsl_fdt_retune),
1634
1635 /* SDHCI accessors. */
1636 DEVMETHOD(sdhci_read_1, sdhci_fsl_fdt_read_1),
1637 DEVMETHOD(sdhci_read_2, sdhci_fsl_fdt_read_2),
1638 DEVMETHOD(sdhci_read_4, sdhci_fsl_fdt_read_4),
1639 DEVMETHOD(sdhci_read_multi_4, sdhci_fsl_fdt_read_multi_4),
1640 DEVMETHOD(sdhci_write_1, sdhci_fsl_fdt_write_1),
1641 DEVMETHOD(sdhci_write_2, sdhci_fsl_fdt_write_2),
1642 DEVMETHOD(sdhci_write_4, sdhci_fsl_fdt_write_4),
1643 DEVMETHOD(sdhci_write_multi_4, sdhci_fsl_fdt_write_multi_4),
1644 DEVMETHOD(sdhci_get_card_present, sdhci_fsl_fdt_get_card_present),
1645 DEVMETHOD(sdhci_reset, sdhci_fsl_fdt_reset),
1646 DEVMETHOD(sdhci_set_uhs_timing, sdhci_fsl_fdt_set_uhs_timing),
1647 DEVMETHOD_END
1648 };
1649
1650 static driver_t sdhci_fsl_fdt_driver = {
1651 "sdhci_fsl_fdt",
1652 sdhci_fsl_fdt_methods,
1653 sizeof(struct sdhci_fsl_fdt_softc),
1654 };
1655
1656 DRIVER_MODULE(sdhci_fsl_fdt, simplebus, sdhci_fsl_fdt_driver, NULL, NULL);
1657 SDHCI_DEPEND(sdhci_fsl_fdt);
1658
1659 #ifndef MMCCAM
1660 MMC_DECLARE_BRIDGE(sdhci_fsl_fdt);
1661 #endif
1662