xref: /linux/drivers/net/ethernet/realtek/r8169_main.c (revision 2c1ed907520c50326b8f604907a8478b27881a2e)
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * r8169.c: RealTek 8169/8168/8101 ethernet driver.
4  *
5  * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
6  * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
7  * Copyright (c) a lot of people too. Please respect their work.
8  *
9  * See MAINTAINERS file for support contact information.
10  */
11 
12 #include <linux/module.h>
13 #include <linux/pci.h>
14 #include <linux/netdevice.h>
15 #include <linux/etherdevice.h>
16 #include <linux/clk.h>
17 #include <linux/delay.h>
18 #include <linux/ethtool.h>
19 #include <linux/phy.h>
20 #include <linux/if_vlan.h>
21 #include <linux/in.h>
22 #include <linux/io.h>
23 #include <linux/ip.h>
24 #include <linux/tcp.h>
25 #include <linux/interrupt.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/pm_runtime.h>
28 #include <linux/bitfield.h>
29 #include <linux/prefetch.h>
30 #include <linux/ipv6.h>
31 #include <linux/unaligned.h>
32 #include <net/ip6_checksum.h>
33 #include <net/netdev_queues.h>
34 
35 #include "r8169.h"
36 #include "r8169_firmware.h"
37 
38 #define FIRMWARE_8168D_1	"rtl_nic/rtl8168d-1.fw"
39 #define FIRMWARE_8168D_2	"rtl_nic/rtl8168d-2.fw"
40 #define FIRMWARE_8168E_1	"rtl_nic/rtl8168e-1.fw"
41 #define FIRMWARE_8168E_2	"rtl_nic/rtl8168e-2.fw"
42 #define FIRMWARE_8168E_3	"rtl_nic/rtl8168e-3.fw"
43 #define FIRMWARE_8168F_1	"rtl_nic/rtl8168f-1.fw"
44 #define FIRMWARE_8168F_2	"rtl_nic/rtl8168f-2.fw"
45 #define FIRMWARE_8105E_1	"rtl_nic/rtl8105e-1.fw"
46 #define FIRMWARE_8402_1		"rtl_nic/rtl8402-1.fw"
47 #define FIRMWARE_8411_1		"rtl_nic/rtl8411-1.fw"
48 #define FIRMWARE_8411_2		"rtl_nic/rtl8411-2.fw"
49 #define FIRMWARE_8106E_1	"rtl_nic/rtl8106e-1.fw"
50 #define FIRMWARE_8106E_2	"rtl_nic/rtl8106e-2.fw"
51 #define FIRMWARE_8168G_2	"rtl_nic/rtl8168g-2.fw"
52 #define FIRMWARE_8168G_3	"rtl_nic/rtl8168g-3.fw"
53 #define FIRMWARE_8168H_2	"rtl_nic/rtl8168h-2.fw"
54 #define FIRMWARE_8168FP_3	"rtl_nic/rtl8168fp-3.fw"
55 #define FIRMWARE_8107E_2	"rtl_nic/rtl8107e-2.fw"
56 #define FIRMWARE_8125A_3	"rtl_nic/rtl8125a-3.fw"
57 #define FIRMWARE_8125B_2	"rtl_nic/rtl8125b-2.fw"
58 #define FIRMWARE_8125D_1	"rtl_nic/rtl8125d-1.fw"
59 #define FIRMWARE_8125D_2	"rtl_nic/rtl8125d-2.fw"
60 #define FIRMWARE_8125BP_2	"rtl_nic/rtl8125bp-2.fw"
61 #define FIRMWARE_8126A_2	"rtl_nic/rtl8126a-2.fw"
62 #define FIRMWARE_8126A_3	"rtl_nic/rtl8126a-3.fw"
63 
64 #define TX_DMA_BURST	7	/* Maximum PCI burst, '7' is unlimited */
65 #define InterFrameGap	0x03	/* 3 means InterFrameGap = the shortest one */
66 
67 #define R8169_REGS_SIZE		256
68 #define R8169_RX_BUF_SIZE	(SZ_16K - 1)
69 #define NUM_TX_DESC	256	/* Number of Tx descriptor registers */
70 #define NUM_RX_DESC	256	/* Number of Rx descriptor registers */
71 #define R8169_TX_RING_BYTES	(NUM_TX_DESC * sizeof(struct TxDesc))
72 #define R8169_RX_RING_BYTES	(NUM_RX_DESC * sizeof(struct RxDesc))
73 #define R8169_TX_STOP_THRS	(MAX_SKB_FRAGS + 1)
74 #define R8169_TX_START_THRS	(2 * R8169_TX_STOP_THRS)
75 
76 #define OCP_STD_PHY_BASE	0xa400
77 
78 #define RTL_CFG_NO_GBIT	1
79 
80 /* write/read MMIO register */
81 #define RTL_W8(tp, reg, val8)	writeb((val8), tp->mmio_addr + (reg))
82 #define RTL_W16(tp, reg, val16)	writew((val16), tp->mmio_addr + (reg))
83 #define RTL_W32(tp, reg, val32)	writel((val32), tp->mmio_addr + (reg))
84 #define RTL_R8(tp, reg)		readb(tp->mmio_addr + (reg))
85 #define RTL_R16(tp, reg)		readw(tp->mmio_addr + (reg))
86 #define RTL_R32(tp, reg)		readl(tp->mmio_addr + (reg))
87 
88 #define JUMBO_4K	(4 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN)
89 #define JUMBO_6K	(6 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN)
90 #define JUMBO_7K	(7 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN)
91 #define JUMBO_9K	(9 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN)
92 
93 static const struct {
94 	const char *name;
95 	const char *fw_name;
96 } rtl_chip_infos[] = {
97 	/* PCI devices. */
98 	[RTL_GIGA_MAC_VER_02] = {"RTL8169s"				},
99 	[RTL_GIGA_MAC_VER_03] = {"RTL8110s"				},
100 	[RTL_GIGA_MAC_VER_04] = {"RTL8169sb/8110sb"			},
101 	[RTL_GIGA_MAC_VER_05] = {"RTL8169sc/8110sc"			},
102 	[RTL_GIGA_MAC_VER_06] = {"RTL8169sc/8110sc"			},
103 	/* PCI-E devices. */
104 	[RTL_GIGA_MAC_VER_07] = {"RTL8102e"				},
105 	[RTL_GIGA_MAC_VER_08] = {"RTL8102e"				},
106 	[RTL_GIGA_MAC_VER_09] = {"RTL8102e/RTL8103e"			},
107 	[RTL_GIGA_MAC_VER_10] = {"RTL8101e/RTL8100e"			},
108 	[RTL_GIGA_MAC_VER_14] = {"RTL8401"				},
109 	[RTL_GIGA_MAC_VER_17] = {"RTL8168b/8111b"			},
110 	[RTL_GIGA_MAC_VER_18] = {"RTL8168cp/8111cp"			},
111 	[RTL_GIGA_MAC_VER_19] = {"RTL8168c/8111c"			},
112 	[RTL_GIGA_MAC_VER_20] = {"RTL8168c/8111c"			},
113 	[RTL_GIGA_MAC_VER_21] = {"RTL8168c/8111c"			},
114 	[RTL_GIGA_MAC_VER_22] = {"RTL8168c/8111c"			},
115 	[RTL_GIGA_MAC_VER_23] = {"RTL8168cp/8111cp"			},
116 	[RTL_GIGA_MAC_VER_24] = {"RTL8168cp/8111cp"			},
117 	[RTL_GIGA_MAC_VER_25] = {"RTL8168d/8111d",	FIRMWARE_8168D_1},
118 	[RTL_GIGA_MAC_VER_26] = {"RTL8168d/8111d",	FIRMWARE_8168D_2},
119 	[RTL_GIGA_MAC_VER_28] = {"RTL8168dp/8111dp"			},
120 	[RTL_GIGA_MAC_VER_29] = {"RTL8105e",		FIRMWARE_8105E_1},
121 	[RTL_GIGA_MAC_VER_30] = {"RTL8105e",		FIRMWARE_8105E_1},
122 	[RTL_GIGA_MAC_VER_31] = {"RTL8168dp/8111dp"			},
123 	[RTL_GIGA_MAC_VER_32] = {"RTL8168e/8111e",	FIRMWARE_8168E_1},
124 	[RTL_GIGA_MAC_VER_33] = {"RTL8168e/8111e",	FIRMWARE_8168E_2},
125 	[RTL_GIGA_MAC_VER_34] = {"RTL8168evl/8111evl",	FIRMWARE_8168E_3},
126 	[RTL_GIGA_MAC_VER_35] = {"RTL8168f/8111f",	FIRMWARE_8168F_1},
127 	[RTL_GIGA_MAC_VER_36] = {"RTL8168f/8111f",	FIRMWARE_8168F_2},
128 	[RTL_GIGA_MAC_VER_37] = {"RTL8402",		FIRMWARE_8402_1 },
129 	[RTL_GIGA_MAC_VER_38] = {"RTL8411",		FIRMWARE_8411_1 },
130 	[RTL_GIGA_MAC_VER_39] = {"RTL8106e",		FIRMWARE_8106E_1},
131 	[RTL_GIGA_MAC_VER_40] = {"RTL8168g/8111g",	FIRMWARE_8168G_2},
132 	[RTL_GIGA_MAC_VER_42] = {"RTL8168gu/8111gu",	FIRMWARE_8168G_3},
133 	[RTL_GIGA_MAC_VER_43] = {"RTL8106eus",		FIRMWARE_8106E_2},
134 	[RTL_GIGA_MAC_VER_44] = {"RTL8411b",		FIRMWARE_8411_2 },
135 	[RTL_GIGA_MAC_VER_46] = {"RTL8168h/8111h",	FIRMWARE_8168H_2},
136 	[RTL_GIGA_MAC_VER_48] = {"RTL8107e",		FIRMWARE_8107E_2},
137 	[RTL_GIGA_MAC_VER_51] = {"RTL8168ep/8111ep"			},
138 	[RTL_GIGA_MAC_VER_52] = {"RTL8168fp/RTL8117",  FIRMWARE_8168FP_3},
139 	[RTL_GIGA_MAC_VER_53] = {"RTL8168fp/RTL8117",			},
140 	[RTL_GIGA_MAC_VER_61] = {"RTL8125A",		FIRMWARE_8125A_3},
141 	/* reserve 62 for CFG_METHOD_4 in the vendor driver */
142 	[RTL_GIGA_MAC_VER_63] = {"RTL8125B",		FIRMWARE_8125B_2},
143 	[RTL_GIGA_MAC_VER_64] = {"RTL8125D",		FIRMWARE_8125D_1},
144 	[RTL_GIGA_MAC_VER_65] = {"RTL8125D",		FIRMWARE_8125D_2},
145 	[RTL_GIGA_MAC_VER_66] = {"RTL8125BP",		FIRMWARE_8125BP_2},
146 	[RTL_GIGA_MAC_VER_70] = {"RTL8126A",		FIRMWARE_8126A_2},
147 	[RTL_GIGA_MAC_VER_71] = {"RTL8126A",		FIRMWARE_8126A_3},
148 };
149 
150 static const struct pci_device_id rtl8169_pci_tbl[] = {
151 	{ PCI_VDEVICE(REALTEK,	0x2502) },
152 	{ PCI_VDEVICE(REALTEK,	0x2600) },
153 	{ PCI_VDEVICE(REALTEK,	0x8129) },
154 	{ PCI_VDEVICE(REALTEK,	0x8136), RTL_CFG_NO_GBIT },
155 	{ PCI_VDEVICE(REALTEK,	0x8161) },
156 	{ PCI_VDEVICE(REALTEK,	0x8162) },
157 	{ PCI_VDEVICE(REALTEK,	0x8167) },
158 	{ PCI_VDEVICE(REALTEK,	0x8168) },
159 	{ PCI_VDEVICE(NCUBE,	0x8168) },
160 	{ PCI_VDEVICE(REALTEK,	0x8169) },
161 	{ PCI_VENDOR_ID_DLINK,	0x4300,
162 		PCI_VENDOR_ID_DLINK, 0x4b10, 0, 0 },
163 	{ PCI_VDEVICE(DLINK,	0x4300) },
164 	{ PCI_VDEVICE(DLINK,	0x4302) },
165 	{ PCI_VDEVICE(AT,	0xc107) },
166 	{ PCI_VDEVICE(USR,	0x0116) },
167 	{ PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0024 },
168 	{ 0x0001, 0x8168, PCI_ANY_ID, 0x2410 },
169 	{ PCI_VDEVICE(REALTEK,	0x8125) },
170 	{ PCI_VDEVICE(REALTEK,	0x8126) },
171 	{ PCI_VDEVICE(REALTEK,	0x3000) },
172 	{}
173 };
174 
175 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
176 
177 enum rtl_registers {
178 	MAC0		= 0,	/* Ethernet hardware address. */
179 	MAC4		= 4,
180 	MAR0		= 8,	/* Multicast filter. */
181 	CounterAddrLow		= 0x10,
182 	CounterAddrHigh		= 0x14,
183 	TxDescStartAddrLow	= 0x20,
184 	TxDescStartAddrHigh	= 0x24,
185 	TxHDescStartAddrLow	= 0x28,
186 	TxHDescStartAddrHigh	= 0x2c,
187 	FLASH		= 0x30,
188 	ERSR		= 0x36,
189 	ChipCmd		= 0x37,
190 	TxPoll		= 0x38,
191 	IntrMask	= 0x3c,
192 	IntrStatus	= 0x3e,
193 
194 	TxConfig	= 0x40,
195 #define	TXCFG_AUTO_FIFO			(1 << 7)	/* 8111e-vl */
196 #define	TXCFG_EMPTY			(1 << 11)	/* 8111e-vl */
197 
198 	RxConfig	= 0x44,
199 #define	RX128_INT_EN			(1 << 15)	/* 8111c and later */
200 #define	RX_MULTI_EN			(1 << 14)	/* 8111c only */
201 #define	RXCFG_FIFO_SHIFT		13
202 					/* No threshold before first PCI xfer */
203 #define	RX_FIFO_THRESH			(7 << RXCFG_FIFO_SHIFT)
204 #define	RX_EARLY_OFF			(1 << 11)
205 #define	RX_PAUSE_SLOT_ON		(1 << 11)	/* 8125b and later */
206 #define	RXCFG_DMA_SHIFT			8
207 					/* Unlimited maximum PCI burst. */
208 #define	RX_DMA_BURST			(7 << RXCFG_DMA_SHIFT)
209 
210 	Cfg9346		= 0x50,
211 	Config0		= 0x51,
212 	Config1		= 0x52,
213 	Config2		= 0x53,
214 #define PME_SIGNAL			(1 << 5)	/* 8168c and later */
215 
216 	Config3		= 0x54,
217 	Config4		= 0x55,
218 	Config5		= 0x56,
219 	PHYAR		= 0x60,
220 	PHYstatus	= 0x6c,
221 	RxMaxSize	= 0xda,
222 	CPlusCmd	= 0xe0,
223 	IntrMitigate	= 0xe2,
224 
225 #define RTL_COALESCE_TX_USECS	GENMASK(15, 12)
226 #define RTL_COALESCE_TX_FRAMES	GENMASK(11, 8)
227 #define RTL_COALESCE_RX_USECS	GENMASK(7, 4)
228 #define RTL_COALESCE_RX_FRAMES	GENMASK(3, 0)
229 
230 #define RTL_COALESCE_T_MAX	0x0fU
231 #define RTL_COALESCE_FRAME_MAX	(RTL_COALESCE_T_MAX * 4)
232 
233 	RxDescAddrLow	= 0xe4,
234 	RxDescAddrHigh	= 0xe8,
235 	EarlyTxThres	= 0xec,	/* 8169. Unit of 32 bytes. */
236 
237 #define NoEarlyTx	0x3f	/* Max value : no early transmit. */
238 
239 	MaxTxPacketSize	= 0xec,	/* 8101/8168. Unit of 128 bytes. */
240 
241 #define TxPacketMax	(8064 >> 7)
242 #define EarlySize	0x27
243 
244 	FuncEvent	= 0xf0,
245 	FuncEventMask	= 0xf4,
246 	FuncPresetState	= 0xf8,
247 	IBCR0           = 0xf8,
248 	IBCR2           = 0xf9,
249 	IBIMR0          = 0xfa,
250 	IBISR0          = 0xfb,
251 	FuncForceEvent	= 0xfc,
252 };
253 
254 enum rtl8168_8101_registers {
255 	CSIDR			= 0x64,
256 	CSIAR			= 0x68,
257 #define	CSIAR_FLAG			0x80000000
258 #define	CSIAR_WRITE_CMD			0x80000000
259 #define	CSIAR_BYTE_ENABLE		0x0000f000
260 #define	CSIAR_ADDR_MASK			0x00000fff
261 	PMCH			= 0x6f,
262 #define D3COLD_NO_PLL_DOWN		BIT(7)
263 #define D3HOT_NO_PLL_DOWN		BIT(6)
264 #define D3_NO_PLL_DOWN			(BIT(7) | BIT(6))
265 	EPHYAR			= 0x80,
266 #define	EPHYAR_FLAG			0x80000000
267 #define	EPHYAR_WRITE_CMD		0x80000000
268 #define	EPHYAR_REG_MASK			0x1f
269 #define	EPHYAR_REG_SHIFT		16
270 #define	EPHYAR_DATA_MASK		0xffff
271 	DLLPR			= 0xd0,
272 #define	PFM_EN				(1 << 6)
273 #define	TX_10M_PS_EN			(1 << 7)
274 	DBG_REG			= 0xd1,
275 #define	FIX_NAK_1			(1 << 4)
276 #define	FIX_NAK_2			(1 << 3)
277 	TWSI			= 0xd2,
278 	MCU			= 0xd3,
279 #define	NOW_IS_OOB			(1 << 7)
280 #define	TX_EMPTY			(1 << 5)
281 #define	RX_EMPTY			(1 << 4)
282 #define	RXTX_EMPTY			(TX_EMPTY | RX_EMPTY)
283 #define	EN_NDP				(1 << 3)
284 #define	EN_OOB_RESET			(1 << 2)
285 #define	LINK_LIST_RDY			(1 << 1)
286 	EFUSEAR			= 0xdc,
287 #define	EFUSEAR_FLAG			0x80000000
288 #define	EFUSEAR_WRITE_CMD		0x80000000
289 #define	EFUSEAR_READ_CMD		0x00000000
290 #define	EFUSEAR_REG_MASK		0x03ff
291 #define	EFUSEAR_REG_SHIFT		8
292 #define	EFUSEAR_DATA_MASK		0xff
293 	MISC_1			= 0xf2,
294 #define	PFM_D3COLD_EN			(1 << 6)
295 };
296 
297 enum rtl8168_registers {
298 	LED_CTRL		= 0x18,
299 	LED_FREQ		= 0x1a,
300 	EEE_LED			= 0x1b,
301 	ERIDR			= 0x70,
302 	ERIAR			= 0x74,
303 #define ERIAR_FLAG			0x80000000
304 #define ERIAR_WRITE_CMD			0x80000000
305 #define ERIAR_READ_CMD			0x00000000
306 #define ERIAR_ADDR_BYTE_ALIGN		4
307 #define ERIAR_TYPE_SHIFT		16
308 #define ERIAR_EXGMAC			(0x00 << ERIAR_TYPE_SHIFT)
309 #define ERIAR_MSIX			(0x01 << ERIAR_TYPE_SHIFT)
310 #define ERIAR_ASF			(0x02 << ERIAR_TYPE_SHIFT)
311 #define ERIAR_OOB			(0x02 << ERIAR_TYPE_SHIFT)
312 #define ERIAR_MASK_SHIFT		12
313 #define ERIAR_MASK_0001			(0x1 << ERIAR_MASK_SHIFT)
314 #define ERIAR_MASK_0011			(0x3 << ERIAR_MASK_SHIFT)
315 #define ERIAR_MASK_0100			(0x4 << ERIAR_MASK_SHIFT)
316 #define ERIAR_MASK_0101			(0x5 << ERIAR_MASK_SHIFT)
317 #define ERIAR_MASK_1111			(0xf << ERIAR_MASK_SHIFT)
318 	EPHY_RXER_NUM		= 0x7c,
319 	OCPDR			= 0xb0,	/* OCP GPHY access */
320 #define OCPDR_WRITE_CMD			0x80000000
321 #define OCPDR_READ_CMD			0x00000000
322 #define OCPDR_REG_MASK			0x7f
323 #define OCPDR_GPHY_REG_SHIFT		16
324 #define OCPDR_DATA_MASK			0xffff
325 	OCPAR			= 0xb4,
326 #define OCPAR_FLAG			0x80000000
327 #define OCPAR_GPHY_WRITE_CMD		0x8000f060
328 #define OCPAR_GPHY_READ_CMD		0x0000f060
329 	GPHY_OCP		= 0xb8,
330 	RDSAR1			= 0xd0,	/* 8168c only. Undocumented on 8168dp */
331 	MISC			= 0xf0,	/* 8168e only. */
332 #define TXPLA_RST			(1 << 29)
333 #define DISABLE_LAN_EN			(1 << 23) /* Enable GPIO pin */
334 #define PWM_EN				(1 << 22)
335 #define RXDV_GATED_EN			(1 << 19)
336 #define EARLY_TALLY_EN			(1 << 16)
337 };
338 
339 enum rtl8125_registers {
340 	LEDSEL0			= 0x18,
341 	INT_CFG0_8125		= 0x34,
342 #define INT_CFG0_ENABLE_8125		BIT(0)
343 #define INT_CFG0_CLKREQEN		BIT(3)
344 	IntrMask_8125		= 0x38,
345 	IntrStatus_8125		= 0x3c,
346 	INT_CFG1_8125		= 0x7a,
347 	LEDSEL2			= 0x84,
348 	LEDSEL1			= 0x86,
349 	TxPoll_8125		= 0x90,
350 	LEDSEL3			= 0x96,
351 	MAC0_BKP		= 0x19e0,
352 	RSS_CTRL_8125		= 0x4500,
353 	Q_NUM_CTRL_8125		= 0x4800,
354 	EEE_TXIDLE_TIMER_8125	= 0x6048,
355 };
356 
357 #define LEDSEL_MASK_8125	0x23f
358 
359 #define RX_VLAN_INNER_8125	BIT(22)
360 #define RX_VLAN_OUTER_8125	BIT(23)
361 #define RX_VLAN_8125		(RX_VLAN_INNER_8125 | RX_VLAN_OUTER_8125)
362 
363 #define RX_FETCH_DFLT_8125	(8 << 27)
364 
365 enum rtl_register_content {
366 	/* InterruptStatusBits */
367 	SYSErr		= 0x8000,
368 	PCSTimeout	= 0x4000,
369 	SWInt		= 0x0100,
370 	TxDescUnavail	= 0x0080,
371 	RxFIFOOver	= 0x0040,
372 	LinkChg		= 0x0020,
373 	RxOverflow	= 0x0010,
374 	TxErr		= 0x0008,
375 	TxOK		= 0x0004,
376 	RxErr		= 0x0002,
377 	RxOK		= 0x0001,
378 
379 	/* RxStatusDesc */
380 	RxRWT	= (1 << 22),
381 	RxRES	= (1 << 21),
382 	RxRUNT	= (1 << 20),
383 	RxCRC	= (1 << 19),
384 
385 	/* ChipCmdBits */
386 	StopReq		= 0x80,
387 	CmdReset	= 0x10,
388 	CmdRxEnb	= 0x08,
389 	CmdTxEnb	= 0x04,
390 	RxBufEmpty	= 0x01,
391 
392 	/* TXPoll register p.5 */
393 	HPQ		= 0x80,		/* Poll cmd on the high prio queue */
394 	NPQ		= 0x40,		/* Poll cmd on the low prio queue */
395 	FSWInt		= 0x01,		/* Forced software interrupt */
396 
397 	/* Cfg9346Bits */
398 	Cfg9346_Lock	= 0x00,
399 	Cfg9346_Unlock	= 0xc0,
400 
401 	/* rx_mode_bits */
402 	AcceptErr	= 0x20,
403 	AcceptRunt	= 0x10,
404 #define RX_CONFIG_ACCEPT_ERR_MASK	0x30
405 	AcceptBroadcast	= 0x08,
406 	AcceptMulticast	= 0x04,
407 	AcceptMyPhys	= 0x02,
408 	AcceptAllPhys	= 0x01,
409 #define RX_CONFIG_ACCEPT_OK_MASK	0x0f
410 #define RX_CONFIG_ACCEPT_MASK		0x3f
411 
412 	/* TxConfigBits */
413 	TxInterFrameGapShift = 24,
414 	TxDMAShift = 8,	/* DMA burst value (0-7) is shift this many bits */
415 
416 	/* Config1 register p.24 */
417 	LEDS1		= (1 << 7),
418 	LEDS0		= (1 << 6),
419 	Speed_down	= (1 << 4),
420 	MEMMAP		= (1 << 3),
421 	IOMAP		= (1 << 2),
422 	VPD		= (1 << 1),
423 	PMEnable	= (1 << 0),	/* Power Management Enable */
424 
425 	/* Config2 register p. 25 */
426 	ClkReqEn	= (1 << 7),	/* Clock Request Enable */
427 	MSIEnable	= (1 << 5),	/* 8169 only. Reserved in the 8168. */
428 	PCI_Clock_66MHz = 0x01,
429 	PCI_Clock_33MHz = 0x00,
430 
431 	/* Config3 register p.25 */
432 	MagicPacket	= (1 << 5),	/* Wake up when receives a Magic Packet */
433 	LinkUp		= (1 << 4),	/* Wake up when the cable connection is re-established */
434 	Jumbo_En0	= (1 << 2),	/* 8168 only. Reserved in the 8168b */
435 	Rdy_to_L23	= (1 << 1),	/* L23 Enable */
436 	Beacon_en	= (1 << 0),	/* 8168 only. Reserved in the 8168b */
437 
438 	/* Config4 register */
439 	Jumbo_En1	= (1 << 1),	/* 8168 only. Reserved in the 8168b */
440 
441 	/* Config5 register p.27 */
442 	BWF		= (1 << 6),	/* Accept Broadcast wakeup frame */
443 	MWF		= (1 << 5),	/* Accept Multicast wakeup frame */
444 	UWF		= (1 << 4),	/* Accept Unicast wakeup frame */
445 	Spi_en		= (1 << 3),
446 	LanWake		= (1 << 1),	/* LanWake enable/disable */
447 	PMEStatus	= (1 << 0),	/* PME status can be reset by PCI RST# */
448 	ASPM_en		= (1 << 0),	/* ASPM enable */
449 
450 	/* CPlusCmd p.31 */
451 	EnableBist	= (1 << 15),	// 8168 8101
452 	Mac_dbgo_oe	= (1 << 14),	// 8168 8101
453 	EnAnaPLL	= (1 << 14),	// 8169
454 	Normal_mode	= (1 << 13),	// unused
455 	Force_half_dup	= (1 << 12),	// 8168 8101
456 	Force_rxflow_en	= (1 << 11),	// 8168 8101
457 	Force_txflow_en	= (1 << 10),	// 8168 8101
458 	Cxpl_dbg_sel	= (1 << 9),	// 8168 8101
459 	ASF		= (1 << 8),	// 8168 8101
460 	PktCntrDisable	= (1 << 7),	// 8168 8101
461 	Mac_dbgo_sel	= 0x001c,	// 8168
462 	RxVlan		= (1 << 6),
463 	RxChkSum	= (1 << 5),
464 	PCIDAC		= (1 << 4),
465 	PCIMulRW	= (1 << 3),
466 #define INTT_MASK	GENMASK(1, 0)
467 #define CPCMD_MASK	(Normal_mode | RxVlan | RxChkSum | INTT_MASK)
468 
469 	/* rtl8169_PHYstatus */
470 	TBI_Enable	= 0x80,
471 	TxFlowCtrl	= 0x40,
472 	RxFlowCtrl	= 0x20,
473 	_1000bpsF	= 0x10,
474 	_100bps		= 0x08,
475 	_10bps		= 0x04,
476 	LinkStatus	= 0x02,
477 	FullDup		= 0x01,
478 
479 	/* ResetCounterCommand */
480 	CounterReset	= 0x1,
481 
482 	/* DumpCounterCommand */
483 	CounterDump	= 0x8,
484 
485 	/* magic enable v2 */
486 	MagicPacket_v2	= (1 << 16),	/* Wake up when receives a Magic Packet */
487 };
488 
489 enum rtl_desc_bit {
490 	/* First doubleword. */
491 	DescOwn		= (1 << 31), /* Descriptor is owned by NIC */
492 	RingEnd		= (1 << 30), /* End of descriptor ring */
493 	FirstFrag	= (1 << 29), /* First segment of a packet */
494 	LastFrag	= (1 << 28), /* Final segment of a packet */
495 };
496 
497 /* Generic case. */
498 enum rtl_tx_desc_bit {
499 	/* First doubleword. */
500 	TD_LSO		= (1 << 27),		/* Large Send Offload */
501 #define TD_MSS_MAX			0x07ffu	/* MSS value */
502 
503 	/* Second doubleword. */
504 	TxVlanTag	= (1 << 17),		/* Add VLAN tag */
505 };
506 
507 /* 8169, 8168b and 810x except 8102e. */
508 enum rtl_tx_desc_bit_0 {
509 	/* First doubleword. */
510 #define TD0_MSS_SHIFT			16	/* MSS position (11 bits) */
511 	TD0_TCP_CS	= (1 << 16),		/* Calculate TCP/IP checksum */
512 	TD0_UDP_CS	= (1 << 17),		/* Calculate UDP/IP checksum */
513 	TD0_IP_CS	= (1 << 18),		/* Calculate IP checksum */
514 };
515 
516 /* 8102e, 8168c and beyond. */
517 enum rtl_tx_desc_bit_1 {
518 	/* First doubleword. */
519 	TD1_GTSENV4	= (1 << 26),		/* Giant Send for IPv4 */
520 	TD1_GTSENV6	= (1 << 25),		/* Giant Send for IPv6 */
521 #define GTTCPHO_SHIFT			18
522 #define GTTCPHO_MAX			0x7f
523 
524 	/* Second doubleword. */
525 #define TCPHO_SHIFT			18
526 #define TCPHO_MAX			0x3ff
527 #define TD1_MSS_SHIFT			18	/* MSS position (11 bits) */
528 	TD1_IPv6_CS	= (1 << 28),		/* Calculate IPv6 checksum */
529 	TD1_IPv4_CS	= (1 << 29),		/* Calculate IPv4 checksum */
530 	TD1_TCP_CS	= (1 << 30),		/* Calculate TCP/IP checksum */
531 	TD1_UDP_CS	= (1 << 31),		/* Calculate UDP/IP checksum */
532 };
533 
534 enum rtl_rx_desc_bit {
535 	/* Rx private */
536 	PID1		= (1 << 18), /* Protocol ID bit 1/2 */
537 	PID0		= (1 << 17), /* Protocol ID bit 0/2 */
538 
539 #define RxProtoUDP	(PID1)
540 #define RxProtoTCP	(PID0)
541 #define RxProtoIP	(PID1 | PID0)
542 #define RxProtoMask	RxProtoIP
543 
544 	IPFail		= (1 << 16), /* IP checksum failed */
545 	UDPFail		= (1 << 15), /* UDP/IP checksum failed */
546 	TCPFail		= (1 << 14), /* TCP/IP checksum failed */
547 
548 #define RxCSFailMask	(IPFail | UDPFail | TCPFail)
549 
550 	RxVlanTag	= (1 << 16), /* VLAN tag available */
551 };
552 
553 #define RTL_GSO_MAX_SIZE_V1	32000
554 #define RTL_GSO_MAX_SEGS_V1	24
555 #define RTL_GSO_MAX_SIZE_V2	64000
556 #define RTL_GSO_MAX_SEGS_V2	64
557 
558 struct TxDesc {
559 	__le32 opts1;
560 	__le32 opts2;
561 	__le64 addr;
562 };
563 
564 struct RxDesc {
565 	__le32 opts1;
566 	__le32 opts2;
567 	__le64 addr;
568 };
569 
570 struct ring_info {
571 	struct sk_buff	*skb;
572 	u32		len;
573 };
574 
575 struct rtl8169_counters {
576 	__le64	tx_packets;
577 	__le64	rx_packets;
578 	__le64	tx_errors;
579 	__le32	rx_errors;
580 	__le16	rx_missed;
581 	__le16	align_errors;
582 	__le32	tx_one_collision;
583 	__le32	tx_multi_collision;
584 	__le64	rx_unicast;
585 	__le64	rx_broadcast;
586 	__le32	rx_multicast;
587 	__le16	tx_aborted;
588 	__le16	tx_underrun;
589 	/* new since RTL8125 */
590 	__le64 tx_octets;
591 	__le64 rx_octets;
592 	__le64 rx_multicast64;
593 	__le64 tx_unicast64;
594 	__le64 tx_broadcast64;
595 	__le64 tx_multicast64;
596 	__le32 tx_pause_on;
597 	__le32 tx_pause_off;
598 	__le32 tx_pause_all;
599 	__le32 tx_deferred;
600 	__le32 tx_late_collision;
601 	__le32 tx_all_collision;
602 	__le32 tx_aborted32;
603 	__le32 align_errors32;
604 	__le32 rx_frame_too_long;
605 	__le32 rx_runt;
606 	__le32 rx_pause_on;
607 	__le32 rx_pause_off;
608 	__le32 rx_pause_all;
609 	__le32 rx_unknown_opcode;
610 	__le32 rx_mac_error;
611 	__le32 tx_underrun32;
612 	__le32 rx_mac_missed;
613 	__le32 rx_tcam_dropped;
614 	__le32 tdu;
615 	__le32 rdu;
616 };
617 
618 struct rtl8169_tc_offsets {
619 	bool	inited;
620 	__le64	tx_errors;
621 	__le32	tx_multi_collision;
622 	__le16	tx_aborted;
623 	__le16	rx_missed;
624 };
625 
626 enum rtl_flag {
627 	RTL_FLAG_TASK_RESET_PENDING,
628 	RTL_FLAG_TASK_TX_TIMEOUT,
629 	RTL_FLAG_MAX
630 };
631 
632 enum rtl_dash_type {
633 	RTL_DASH_NONE,
634 	RTL_DASH_DP,
635 	RTL_DASH_EP,
636 	RTL_DASH_25_BP,
637 };
638 
639 struct rtl8169_private {
640 	void __iomem *mmio_addr;	/* memory map physical address */
641 	struct pci_dev *pci_dev;
642 	struct net_device *dev;
643 	struct phy_device *phydev;
644 	struct napi_struct napi;
645 	enum mac_version mac_version;
646 	enum rtl_dash_type dash_type;
647 	u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
648 	u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
649 	u32 dirty_tx;
650 	struct TxDesc *TxDescArray;	/* 256-aligned Tx descriptor ring */
651 	struct RxDesc *RxDescArray;	/* 256-aligned Rx descriptor ring */
652 	dma_addr_t TxPhyAddr;
653 	dma_addr_t RxPhyAddr;
654 	struct page *Rx_databuff[NUM_RX_DESC];	/* Rx data buffers */
655 	struct ring_info tx_skb[NUM_TX_DESC];	/* Tx data buffers */
656 	u16 cp_cmd;
657 	u16 tx_lpi_timer;
658 	u32 irq_mask;
659 	int irq;
660 	struct clk *clk;
661 
662 	struct {
663 		DECLARE_BITMAP(flags, RTL_FLAG_MAX);
664 		struct work_struct work;
665 	} wk;
666 
667 	raw_spinlock_t mac_ocp_lock;
668 	struct mutex led_lock;	/* serialize LED ctrl RMW access */
669 
670 	unsigned supports_gmii:1;
671 	unsigned aspm_manageable:1;
672 	unsigned dash_enabled:1;
673 	dma_addr_t counters_phys_addr;
674 	struct rtl8169_counters *counters;
675 	struct rtl8169_tc_offsets tc_offset;
676 	u32 saved_wolopts;
677 
678 	const char *fw_name;
679 	struct rtl_fw *rtl_fw;
680 
681 	struct r8169_led_classdev *leds;
682 
683 	u32 ocp_base;
684 };
685 
686 typedef void (*rtl_generic_fct)(struct rtl8169_private *tp);
687 
688 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
689 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
690 MODULE_SOFTDEP("pre: realtek");
691 MODULE_LICENSE("GPL");
692 MODULE_FIRMWARE(FIRMWARE_8168D_1);
693 MODULE_FIRMWARE(FIRMWARE_8168D_2);
694 MODULE_FIRMWARE(FIRMWARE_8168E_1);
695 MODULE_FIRMWARE(FIRMWARE_8168E_2);
696 MODULE_FIRMWARE(FIRMWARE_8168E_3);
697 MODULE_FIRMWARE(FIRMWARE_8105E_1);
698 MODULE_FIRMWARE(FIRMWARE_8168F_1);
699 MODULE_FIRMWARE(FIRMWARE_8168F_2);
700 MODULE_FIRMWARE(FIRMWARE_8402_1);
701 MODULE_FIRMWARE(FIRMWARE_8411_1);
702 MODULE_FIRMWARE(FIRMWARE_8411_2);
703 MODULE_FIRMWARE(FIRMWARE_8106E_1);
704 MODULE_FIRMWARE(FIRMWARE_8106E_2);
705 MODULE_FIRMWARE(FIRMWARE_8168G_2);
706 MODULE_FIRMWARE(FIRMWARE_8168G_3);
707 MODULE_FIRMWARE(FIRMWARE_8168H_2);
708 MODULE_FIRMWARE(FIRMWARE_8168FP_3);
709 MODULE_FIRMWARE(FIRMWARE_8107E_2);
710 MODULE_FIRMWARE(FIRMWARE_8125A_3);
711 MODULE_FIRMWARE(FIRMWARE_8125B_2);
712 MODULE_FIRMWARE(FIRMWARE_8125D_1);
713 MODULE_FIRMWARE(FIRMWARE_8125D_2);
714 MODULE_FIRMWARE(FIRMWARE_8125BP_2);
715 MODULE_FIRMWARE(FIRMWARE_8126A_2);
716 MODULE_FIRMWARE(FIRMWARE_8126A_3);
717 
tp_to_dev(struct rtl8169_private * tp)718 static inline struct device *tp_to_dev(struct rtl8169_private *tp)
719 {
720 	return &tp->pci_dev->dev;
721 }
722 
rtl_lock_config_regs(struct rtl8169_private * tp)723 static void rtl_lock_config_regs(struct rtl8169_private *tp)
724 {
725 	RTL_W8(tp, Cfg9346, Cfg9346_Lock);
726 }
727 
rtl_unlock_config_regs(struct rtl8169_private * tp)728 static void rtl_unlock_config_regs(struct rtl8169_private *tp)
729 {
730 	RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
731 }
732 
rtl_pci_commit(struct rtl8169_private * tp)733 static void rtl_pci_commit(struct rtl8169_private *tp)
734 {
735 	/* Read an arbitrary register to commit a preceding PCI write */
736 	RTL_R8(tp, ChipCmd);
737 }
738 
rtl_mod_config2(struct rtl8169_private * tp,u8 clear,u8 set)739 static void rtl_mod_config2(struct rtl8169_private *tp, u8 clear, u8 set)
740 {
741 	u8 val;
742 
743 	val = RTL_R8(tp, Config2);
744 	RTL_W8(tp, Config2, (val & ~clear) | set);
745 }
746 
rtl_mod_config5(struct rtl8169_private * tp,u8 clear,u8 set)747 static void rtl_mod_config5(struct rtl8169_private *tp, u8 clear, u8 set)
748 {
749 	u8 val;
750 
751 	val = RTL_R8(tp, Config5);
752 	RTL_W8(tp, Config5, (val & ~clear) | set);
753 }
754 
r8169_mod_reg8_cond(struct rtl8169_private * tp,int reg,u8 bits,bool cond)755 static void r8169_mod_reg8_cond(struct rtl8169_private *tp, int reg,
756 				u8 bits, bool cond)
757 {
758 	u8 val, old_val;
759 
760 	old_val = RTL_R8(tp, reg);
761 	if (cond)
762 		val = old_val | bits;
763 	else
764 		val = old_val & ~bits;
765 	if (val != old_val)
766 		RTL_W8(tp, reg, val);
767 }
768 
rtl_is_8125(struct rtl8169_private * tp)769 static bool rtl_is_8125(struct rtl8169_private *tp)
770 {
771 	return tp->mac_version >= RTL_GIGA_MAC_VER_61;
772 }
773 
rtl_is_8168evl_up(struct rtl8169_private * tp)774 static bool rtl_is_8168evl_up(struct rtl8169_private *tp)
775 {
776 	return tp->mac_version >= RTL_GIGA_MAC_VER_34 &&
777 	       tp->mac_version != RTL_GIGA_MAC_VER_39 &&
778 	       tp->mac_version <= RTL_GIGA_MAC_VER_53;
779 }
780 
rtl_supports_eee(struct rtl8169_private * tp)781 static bool rtl_supports_eee(struct rtl8169_private *tp)
782 {
783 	return tp->mac_version >= RTL_GIGA_MAC_VER_34 &&
784 	       tp->mac_version != RTL_GIGA_MAC_VER_37 &&
785 	       tp->mac_version != RTL_GIGA_MAC_VER_39;
786 }
787 
rtl_read_mac_from_reg(struct rtl8169_private * tp,u8 * mac,int reg)788 static void rtl_read_mac_from_reg(struct rtl8169_private *tp, u8 *mac, int reg)
789 {
790 	int i;
791 
792 	for (i = 0; i < ETH_ALEN; i++)
793 		mac[i] = RTL_R8(tp, reg + i);
794 }
795 
796 struct rtl_cond {
797 	bool (*check)(struct rtl8169_private *);
798 	const char *msg;
799 };
800 
rtl_loop_wait(struct rtl8169_private * tp,const struct rtl_cond * c,unsigned long usecs,int n,bool high)801 static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c,
802 			  unsigned long usecs, int n, bool high)
803 {
804 	int i;
805 
806 	for (i = 0; i < n; i++) {
807 		if (c->check(tp) == high)
808 			return true;
809 		fsleep(usecs);
810 	}
811 
812 	if (net_ratelimit())
813 		netdev_err(tp->dev, "%s == %d (loop: %d, delay: %lu).\n",
814 			   c->msg, !high, n, usecs);
815 	return false;
816 }
817 
rtl_loop_wait_high(struct rtl8169_private * tp,const struct rtl_cond * c,unsigned long d,int n)818 static bool rtl_loop_wait_high(struct rtl8169_private *tp,
819 			       const struct rtl_cond *c,
820 			       unsigned long d, int n)
821 {
822 	return rtl_loop_wait(tp, c, d, n, true);
823 }
824 
rtl_loop_wait_low(struct rtl8169_private * tp,const struct rtl_cond * c,unsigned long d,int n)825 static bool rtl_loop_wait_low(struct rtl8169_private *tp,
826 			      const struct rtl_cond *c,
827 			      unsigned long d, int n)
828 {
829 	return rtl_loop_wait(tp, c, d, n, false);
830 }
831 
832 #define DECLARE_RTL_COND(name)				\
833 static bool name ## _check(struct rtl8169_private *);	\
834 							\
835 static const struct rtl_cond name = {			\
836 	.check	= name ## _check,			\
837 	.msg	= #name					\
838 };							\
839 							\
840 static bool name ## _check(struct rtl8169_private *tp)
841 
rtl8168_led_mod_ctrl(struct rtl8169_private * tp,u16 mask,u16 val)842 int rtl8168_led_mod_ctrl(struct rtl8169_private *tp, u16 mask, u16 val)
843 {
844 	struct device *dev = tp_to_dev(tp);
845 	int ret;
846 
847 	ret = pm_runtime_resume_and_get(dev);
848 	if (ret < 0)
849 		return ret;
850 
851 	mutex_lock(&tp->led_lock);
852 	RTL_W16(tp, LED_CTRL, (RTL_R16(tp, LED_CTRL) & ~mask) | val);
853 	mutex_unlock(&tp->led_lock);
854 
855 	pm_runtime_put_sync(dev);
856 
857 	return 0;
858 }
859 
rtl8168_get_led_mode(struct rtl8169_private * tp)860 int rtl8168_get_led_mode(struct rtl8169_private *tp)
861 {
862 	struct device *dev = tp_to_dev(tp);
863 	int ret;
864 
865 	ret = pm_runtime_resume_and_get(dev);
866 	if (ret < 0)
867 		return ret;
868 
869 	ret = RTL_R16(tp, LED_CTRL);
870 
871 	pm_runtime_put_sync(dev);
872 
873 	return ret;
874 }
875 
rtl8125_get_led_reg(int index)876 static int rtl8125_get_led_reg(int index)
877 {
878 	static const int led_regs[] = { LEDSEL0, LEDSEL1, LEDSEL2, LEDSEL3 };
879 
880 	return led_regs[index];
881 }
882 
rtl8125_set_led_mode(struct rtl8169_private * tp,int index,u16 mode)883 int rtl8125_set_led_mode(struct rtl8169_private *tp, int index, u16 mode)
884 {
885 	int reg = rtl8125_get_led_reg(index);
886 	struct device *dev = tp_to_dev(tp);
887 	int ret;
888 	u16 val;
889 
890 	ret = pm_runtime_resume_and_get(dev);
891 	if (ret < 0)
892 		return ret;
893 
894 	mutex_lock(&tp->led_lock);
895 	val = RTL_R16(tp, reg) & ~LEDSEL_MASK_8125;
896 	RTL_W16(tp, reg, val | mode);
897 	mutex_unlock(&tp->led_lock);
898 
899 	pm_runtime_put_sync(dev);
900 
901 	return 0;
902 }
903 
rtl8125_get_led_mode(struct rtl8169_private * tp,int index)904 int rtl8125_get_led_mode(struct rtl8169_private *tp, int index)
905 {
906 	int reg = rtl8125_get_led_reg(index);
907 	struct device *dev = tp_to_dev(tp);
908 	int ret;
909 
910 	ret = pm_runtime_resume_and_get(dev);
911 	if (ret < 0)
912 		return ret;
913 
914 	ret = RTL_R16(tp, reg);
915 
916 	pm_runtime_put_sync(dev);
917 
918 	return ret;
919 }
920 
r8169_get_led_name(struct rtl8169_private * tp,int idx,char * buf,int buf_len)921 void r8169_get_led_name(struct rtl8169_private *tp, int idx,
922 			char *buf, int buf_len)
923 {
924 	struct pci_dev *pdev = tp->pci_dev;
925 	char pdom[8], pfun[8];
926 	int domain;
927 
928 	domain = pci_domain_nr(pdev->bus);
929 	if (domain)
930 		snprintf(pdom, sizeof(pdom), "P%d", domain);
931 	else
932 		pdom[0] = '\0';
933 
934 	if (pdev->multifunction)
935 		snprintf(pfun, sizeof(pfun), "f%d", PCI_FUNC(pdev->devfn));
936 	else
937 		pfun[0] = '\0';
938 
939 	snprintf(buf, buf_len, "en%sp%ds%d%s-%d::lan", pdom, pdev->bus->number,
940 		 PCI_SLOT(pdev->devfn), pfun, idx);
941 }
942 
r8168fp_adjust_ocp_cmd(struct rtl8169_private * tp,u32 * cmd,int type)943 static void r8168fp_adjust_ocp_cmd(struct rtl8169_private *tp, u32 *cmd, int type)
944 {
945 	/* based on RTL8168FP_OOBMAC_BASE in vendor driver */
946 	if (type == ERIAR_OOB &&
947 	    (tp->mac_version == RTL_GIGA_MAC_VER_52 ||
948 	     tp->mac_version == RTL_GIGA_MAC_VER_53))
949 		*cmd |= 0xf70 << 18;
950 }
951 
DECLARE_RTL_COND(rtl_eriar_cond)952 DECLARE_RTL_COND(rtl_eriar_cond)
953 {
954 	return RTL_R32(tp, ERIAR) & ERIAR_FLAG;
955 }
956 
_rtl_eri_write(struct rtl8169_private * tp,int addr,u32 mask,u32 val,int type)957 static void _rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
958 			   u32 val, int type)
959 {
960 	u32 cmd = ERIAR_WRITE_CMD | type | mask | addr;
961 
962 	if (WARN(addr & 3 || !mask, "addr: 0x%x, mask: 0x%08x\n", addr, mask))
963 		return;
964 
965 	RTL_W32(tp, ERIDR, val);
966 	r8168fp_adjust_ocp_cmd(tp, &cmd, type);
967 	RTL_W32(tp, ERIAR, cmd);
968 
969 	rtl_loop_wait_low(tp, &rtl_eriar_cond, 100, 100);
970 }
971 
rtl_eri_write(struct rtl8169_private * tp,int addr,u32 mask,u32 val)972 static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
973 			  u32 val)
974 {
975 	_rtl_eri_write(tp, addr, mask, val, ERIAR_EXGMAC);
976 }
977 
_rtl_eri_read(struct rtl8169_private * tp,int addr,int type)978 static u32 _rtl_eri_read(struct rtl8169_private *tp, int addr, int type)
979 {
980 	u32 cmd = ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr;
981 
982 	r8168fp_adjust_ocp_cmd(tp, &cmd, type);
983 	RTL_W32(tp, ERIAR, cmd);
984 
985 	return rtl_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ?
986 		RTL_R32(tp, ERIDR) : ~0;
987 }
988 
rtl_eri_read(struct rtl8169_private * tp,int addr)989 static u32 rtl_eri_read(struct rtl8169_private *tp, int addr)
990 {
991 	return _rtl_eri_read(tp, addr, ERIAR_EXGMAC);
992 }
993 
rtl_w0w1_eri(struct rtl8169_private * tp,int addr,u32 p,u32 m)994 static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 p, u32 m)
995 {
996 	u32 val = rtl_eri_read(tp, addr);
997 
998 	rtl_eri_write(tp, addr, ERIAR_MASK_1111, (val & ~m) | p);
999 }
1000 
rtl_eri_set_bits(struct rtl8169_private * tp,int addr,u32 p)1001 static void rtl_eri_set_bits(struct rtl8169_private *tp, int addr, u32 p)
1002 {
1003 	rtl_w0w1_eri(tp, addr, p, 0);
1004 }
1005 
rtl_eri_clear_bits(struct rtl8169_private * tp,int addr,u32 m)1006 static void rtl_eri_clear_bits(struct rtl8169_private *tp, int addr, u32 m)
1007 {
1008 	rtl_w0w1_eri(tp, addr, 0, m);
1009 }
1010 
rtl_ocp_reg_failure(u32 reg)1011 static bool rtl_ocp_reg_failure(u32 reg)
1012 {
1013 	return WARN_ONCE(reg & 0xffff0001, "Invalid ocp reg %x!\n", reg);
1014 }
1015 
DECLARE_RTL_COND(rtl_ocp_gphy_cond)1016 DECLARE_RTL_COND(rtl_ocp_gphy_cond)
1017 {
1018 	return RTL_R32(tp, GPHY_OCP) & OCPAR_FLAG;
1019 }
1020 
r8168_phy_ocp_write(struct rtl8169_private * tp,u32 reg,u32 data)1021 static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
1022 {
1023 	if (rtl_ocp_reg_failure(reg))
1024 		return;
1025 
1026 	RTL_W32(tp, GPHY_OCP, OCPAR_FLAG | (reg << 15) | data);
1027 
1028 	rtl_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10);
1029 }
1030 
r8168_phy_ocp_read(struct rtl8169_private * tp,u32 reg)1031 static int r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg)
1032 {
1033 	if (rtl_ocp_reg_failure(reg))
1034 		return 0;
1035 
1036 	RTL_W32(tp, GPHY_OCP, reg << 15);
1037 
1038 	return rtl_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ?
1039 		(RTL_R32(tp, GPHY_OCP) & 0xffff) : -ETIMEDOUT;
1040 }
1041 
__r8168_mac_ocp_write(struct rtl8169_private * tp,u32 reg,u32 data)1042 static void __r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
1043 {
1044 	if (rtl_ocp_reg_failure(reg))
1045 		return;
1046 
1047 	RTL_W32(tp, OCPDR, OCPAR_FLAG | (reg << 15) | data);
1048 }
1049 
r8168_mac_ocp_write(struct rtl8169_private * tp,u32 reg,u32 data)1050 static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
1051 {
1052 	unsigned long flags;
1053 
1054 	raw_spin_lock_irqsave(&tp->mac_ocp_lock, flags);
1055 	__r8168_mac_ocp_write(tp, reg, data);
1056 	raw_spin_unlock_irqrestore(&tp->mac_ocp_lock, flags);
1057 }
1058 
__r8168_mac_ocp_read(struct rtl8169_private * tp,u32 reg)1059 static u16 __r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg)
1060 {
1061 	if (rtl_ocp_reg_failure(reg))
1062 		return 0;
1063 
1064 	RTL_W32(tp, OCPDR, reg << 15);
1065 
1066 	return RTL_R32(tp, OCPDR);
1067 }
1068 
r8168_mac_ocp_read(struct rtl8169_private * tp,u32 reg)1069 static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg)
1070 {
1071 	unsigned long flags;
1072 	u16 val;
1073 
1074 	raw_spin_lock_irqsave(&tp->mac_ocp_lock, flags);
1075 	val = __r8168_mac_ocp_read(tp, reg);
1076 	raw_spin_unlock_irqrestore(&tp->mac_ocp_lock, flags);
1077 
1078 	return val;
1079 }
1080 
r8168_mac_ocp_modify(struct rtl8169_private * tp,u32 reg,u16 mask,u16 set)1081 static void r8168_mac_ocp_modify(struct rtl8169_private *tp, u32 reg, u16 mask,
1082 				 u16 set)
1083 {
1084 	unsigned long flags;
1085 	u16 data;
1086 
1087 	raw_spin_lock_irqsave(&tp->mac_ocp_lock, flags);
1088 	data = __r8168_mac_ocp_read(tp, reg);
1089 	__r8168_mac_ocp_write(tp, reg, (data & ~mask) | set);
1090 	raw_spin_unlock_irqrestore(&tp->mac_ocp_lock, flags);
1091 }
1092 
1093 /* Work around a hw issue with RTL8168g PHY, the quirk disables
1094  * PHY MCU interrupts before PHY power-down.
1095  */
rtl8168g_phy_suspend_quirk(struct rtl8169_private * tp,int value)1096 static void rtl8168g_phy_suspend_quirk(struct rtl8169_private *tp, int value)
1097 {
1098 	switch (tp->mac_version) {
1099 	case RTL_GIGA_MAC_VER_40:
1100 		if (value & BMCR_RESET || !(value & BMCR_PDOWN))
1101 			rtl_eri_set_bits(tp, 0x1a8, 0xfc000000);
1102 		else
1103 			rtl_eri_clear_bits(tp, 0x1a8, 0xfc000000);
1104 		break;
1105 	default:
1106 		break;
1107 	}
1108 };
1109 
r8168g_mdio_write(struct rtl8169_private * tp,int reg,int value)1110 static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value)
1111 {
1112 	if (reg == 0x1f) {
1113 		tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE;
1114 		return;
1115 	}
1116 
1117 	if (tp->ocp_base != OCP_STD_PHY_BASE)
1118 		reg -= 0x10;
1119 
1120 	if (tp->ocp_base == OCP_STD_PHY_BASE && reg == MII_BMCR)
1121 		rtl8168g_phy_suspend_quirk(tp, value);
1122 
1123 	r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value);
1124 }
1125 
r8168g_mdio_read(struct rtl8169_private * tp,int reg)1126 static int r8168g_mdio_read(struct rtl8169_private *tp, int reg)
1127 {
1128 	if (reg == 0x1f)
1129 		return tp->ocp_base == OCP_STD_PHY_BASE ? 0 : tp->ocp_base >> 4;
1130 
1131 	if (tp->ocp_base != OCP_STD_PHY_BASE)
1132 		reg -= 0x10;
1133 
1134 	return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2);
1135 }
1136 
mac_mcu_write(struct rtl8169_private * tp,int reg,int value)1137 static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value)
1138 {
1139 	if (reg == 0x1f) {
1140 		tp->ocp_base = value << 4;
1141 		return;
1142 	}
1143 
1144 	r8168_mac_ocp_write(tp, tp->ocp_base + reg, value);
1145 }
1146 
mac_mcu_read(struct rtl8169_private * tp,int reg)1147 static int mac_mcu_read(struct rtl8169_private *tp, int reg)
1148 {
1149 	return r8168_mac_ocp_read(tp, tp->ocp_base + reg);
1150 }
1151 
DECLARE_RTL_COND(rtl_phyar_cond)1152 DECLARE_RTL_COND(rtl_phyar_cond)
1153 {
1154 	return RTL_R32(tp, PHYAR) & 0x80000000;
1155 }
1156 
r8169_mdio_write(struct rtl8169_private * tp,int reg,int value)1157 static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value)
1158 {
1159 	RTL_W32(tp, PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff));
1160 
1161 	rtl_loop_wait_low(tp, &rtl_phyar_cond, 25, 20);
1162 	/*
1163 	 * According to hardware specs a 20us delay is required after write
1164 	 * complete indication, but before sending next command.
1165 	 */
1166 	udelay(20);
1167 }
1168 
r8169_mdio_read(struct rtl8169_private * tp,int reg)1169 static int r8169_mdio_read(struct rtl8169_private *tp, int reg)
1170 {
1171 	int value;
1172 
1173 	RTL_W32(tp, PHYAR, 0x0 | (reg & 0x1f) << 16);
1174 
1175 	value = rtl_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ?
1176 		RTL_R32(tp, PHYAR) & 0xffff : -ETIMEDOUT;
1177 
1178 	/*
1179 	 * According to hardware specs a 20us delay is required after read
1180 	 * complete indication, but before sending next command.
1181 	 */
1182 	udelay(20);
1183 
1184 	return value;
1185 }
1186 
DECLARE_RTL_COND(rtl_ocpar_cond)1187 DECLARE_RTL_COND(rtl_ocpar_cond)
1188 {
1189 	return RTL_R32(tp, OCPAR) & OCPAR_FLAG;
1190 }
1191 
1192 #define R8168DP_1_MDIO_ACCESS_BIT	0x00020000
1193 
r8168dp_2_mdio_start(struct rtl8169_private * tp)1194 static void r8168dp_2_mdio_start(struct rtl8169_private *tp)
1195 {
1196 	RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
1197 }
1198 
r8168dp_2_mdio_stop(struct rtl8169_private * tp)1199 static void r8168dp_2_mdio_stop(struct rtl8169_private *tp)
1200 {
1201 	RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
1202 }
1203 
r8168dp_2_mdio_write(struct rtl8169_private * tp,int reg,int value)1204 static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value)
1205 {
1206 	r8168dp_2_mdio_start(tp);
1207 
1208 	r8169_mdio_write(tp, reg, value);
1209 
1210 	r8168dp_2_mdio_stop(tp);
1211 }
1212 
r8168dp_2_mdio_read(struct rtl8169_private * tp,int reg)1213 static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg)
1214 {
1215 	int value;
1216 
1217 	/* Work around issue with chip reporting wrong PHY ID */
1218 	if (reg == MII_PHYSID2)
1219 		return 0xc912;
1220 
1221 	r8168dp_2_mdio_start(tp);
1222 
1223 	value = r8169_mdio_read(tp, reg);
1224 
1225 	r8168dp_2_mdio_stop(tp);
1226 
1227 	return value;
1228 }
1229 
rtl_writephy(struct rtl8169_private * tp,int location,int val)1230 static void rtl_writephy(struct rtl8169_private *tp, int location, int val)
1231 {
1232 	switch (tp->mac_version) {
1233 	case RTL_GIGA_MAC_VER_28:
1234 	case RTL_GIGA_MAC_VER_31:
1235 		r8168dp_2_mdio_write(tp, location, val);
1236 		break;
1237 	case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_71:
1238 		r8168g_mdio_write(tp, location, val);
1239 		break;
1240 	default:
1241 		r8169_mdio_write(tp, location, val);
1242 		break;
1243 	}
1244 }
1245 
rtl_readphy(struct rtl8169_private * tp,int location)1246 static int rtl_readphy(struct rtl8169_private *tp, int location)
1247 {
1248 	switch (tp->mac_version) {
1249 	case RTL_GIGA_MAC_VER_28:
1250 	case RTL_GIGA_MAC_VER_31:
1251 		return r8168dp_2_mdio_read(tp, location);
1252 	case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_71:
1253 		return r8168g_mdio_read(tp, location);
1254 	default:
1255 		return r8169_mdio_read(tp, location);
1256 	}
1257 }
1258 
DECLARE_RTL_COND(rtl_ephyar_cond)1259 DECLARE_RTL_COND(rtl_ephyar_cond)
1260 {
1261 	return RTL_R32(tp, EPHYAR) & EPHYAR_FLAG;
1262 }
1263 
rtl_ephy_write(struct rtl8169_private * tp,int reg_addr,int value)1264 static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value)
1265 {
1266 	RTL_W32(tp, EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
1267 		(reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1268 
1269 	rtl_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100);
1270 
1271 	udelay(10);
1272 }
1273 
rtl_ephy_read(struct rtl8169_private * tp,int reg_addr)1274 static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr)
1275 {
1276 	RTL_W32(tp, EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1277 
1278 	return rtl_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ?
1279 		RTL_R32(tp, EPHYAR) & EPHYAR_DATA_MASK : ~0;
1280 }
1281 
r8168dp_ocp_read(struct rtl8169_private * tp,u16 reg)1282 static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u16 reg)
1283 {
1284 	RTL_W32(tp, OCPAR, 0x0fu << 12 | (reg & 0x0fff));
1285 	return rtl_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ?
1286 		RTL_R32(tp, OCPDR) : ~0;
1287 }
1288 
r8168ep_ocp_read(struct rtl8169_private * tp,u16 reg)1289 static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u16 reg)
1290 {
1291 	return _rtl_eri_read(tp, reg, ERIAR_OOB);
1292 }
1293 
r8168dp_ocp_write(struct rtl8169_private * tp,u8 mask,u16 reg,u32 data)1294 static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1295 			      u32 data)
1296 {
1297 	RTL_W32(tp, OCPDR, data);
1298 	RTL_W32(tp, OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1299 	rtl_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20);
1300 }
1301 
r8168ep_ocp_write(struct rtl8169_private * tp,u8 mask,u16 reg,u32 data)1302 static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1303 			      u32 data)
1304 {
1305 	_rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT,
1306 		       data, ERIAR_OOB);
1307 }
1308 
r8168dp_oob_notify(struct rtl8169_private * tp,u8 cmd)1309 static void r8168dp_oob_notify(struct rtl8169_private *tp, u8 cmd)
1310 {
1311 	rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd);
1312 
1313 	r8168dp_ocp_write(tp, 0x1, 0x30, 0x00000001);
1314 }
1315 
1316 #define OOB_CMD_RESET		0x00
1317 #define OOB_CMD_DRIVER_START	0x05
1318 #define OOB_CMD_DRIVER_STOP	0x06
1319 
rtl8168_get_ocp_reg(struct rtl8169_private * tp)1320 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
1321 {
1322 	return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
1323 }
1324 
DECLARE_RTL_COND(rtl_dp_ocp_read_cond)1325 DECLARE_RTL_COND(rtl_dp_ocp_read_cond)
1326 {
1327 	u16 reg;
1328 
1329 	reg = rtl8168_get_ocp_reg(tp);
1330 
1331 	return r8168dp_ocp_read(tp, reg) & 0x00000800;
1332 }
1333 
DECLARE_RTL_COND(rtl_ep_ocp_read_cond)1334 DECLARE_RTL_COND(rtl_ep_ocp_read_cond)
1335 {
1336 	return r8168ep_ocp_read(tp, 0x124) & 0x00000001;
1337 }
1338 
DECLARE_RTL_COND(rtl_ocp_tx_cond)1339 DECLARE_RTL_COND(rtl_ocp_tx_cond)
1340 {
1341 	return RTL_R8(tp, IBISR0) & 0x20;
1342 }
1343 
rtl8168ep_stop_cmac(struct rtl8169_private * tp)1344 static void rtl8168ep_stop_cmac(struct rtl8169_private *tp)
1345 {
1346 	RTL_W8(tp, IBCR2, RTL_R8(tp, IBCR2) & ~0x01);
1347 	rtl_loop_wait_high(tp, &rtl_ocp_tx_cond, 50000, 2000);
1348 	RTL_W8(tp, IBISR0, RTL_R8(tp, IBISR0) | 0x20);
1349 	RTL_W8(tp, IBCR0, RTL_R8(tp, IBCR0) & ~0x01);
1350 }
1351 
rtl8168dp_driver_start(struct rtl8169_private * tp)1352 static void rtl8168dp_driver_start(struct rtl8169_private *tp)
1353 {
1354 	r8168dp_oob_notify(tp, OOB_CMD_DRIVER_START);
1355 	if (tp->dash_enabled)
1356 		rtl_loop_wait_high(tp, &rtl_dp_ocp_read_cond, 10000, 10);
1357 }
1358 
rtl8168ep_driver_start(struct rtl8169_private * tp)1359 static void rtl8168ep_driver_start(struct rtl8169_private *tp)
1360 {
1361 	r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START);
1362 	r8168ep_ocp_write(tp, 0x01, 0x30, r8168ep_ocp_read(tp, 0x30) | 0x01);
1363 	if (tp->dash_enabled)
1364 		rtl_loop_wait_high(tp, &rtl_ep_ocp_read_cond, 10000, 30);
1365 }
1366 
rtl8125bp_driver_start(struct rtl8169_private * tp)1367 static void rtl8125bp_driver_start(struct rtl8169_private *tp)
1368 {
1369 	r8168ep_ocp_write(tp, 0x01, 0x14, OOB_CMD_DRIVER_START);
1370 	r8168ep_ocp_write(tp, 0x01, 0x18, 0x00);
1371 	r8168ep_ocp_write(tp, 0x01, 0x10, 0x01);
1372 }
1373 
rtl8168_driver_start(struct rtl8169_private * tp)1374 static void rtl8168_driver_start(struct rtl8169_private *tp)
1375 {
1376 	if (tp->dash_type == RTL_DASH_DP)
1377 		rtl8168dp_driver_start(tp);
1378 	else if (tp->dash_type == RTL_DASH_25_BP)
1379 		rtl8125bp_driver_start(tp);
1380 	else
1381 		rtl8168ep_driver_start(tp);
1382 }
1383 
rtl8168dp_driver_stop(struct rtl8169_private * tp)1384 static void rtl8168dp_driver_stop(struct rtl8169_private *tp)
1385 {
1386 	r8168dp_oob_notify(tp, OOB_CMD_DRIVER_STOP);
1387 	if (tp->dash_enabled)
1388 		rtl_loop_wait_low(tp, &rtl_dp_ocp_read_cond, 10000, 10);
1389 }
1390 
rtl8168ep_driver_stop(struct rtl8169_private * tp)1391 static void rtl8168ep_driver_stop(struct rtl8169_private *tp)
1392 {
1393 	rtl8168ep_stop_cmac(tp);
1394 	r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP);
1395 	r8168ep_ocp_write(tp, 0x01, 0x30, r8168ep_ocp_read(tp, 0x30) | 0x01);
1396 	if (tp->dash_enabled)
1397 		rtl_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10000, 10);
1398 }
1399 
rtl8125bp_driver_stop(struct rtl8169_private * tp)1400 static void rtl8125bp_driver_stop(struct rtl8169_private *tp)
1401 {
1402 	r8168ep_ocp_write(tp, 0x01, 0x14, OOB_CMD_DRIVER_STOP);
1403 	r8168ep_ocp_write(tp, 0x01, 0x18, 0x00);
1404 	r8168ep_ocp_write(tp, 0x01, 0x10, 0x01);
1405 }
1406 
rtl8168_driver_stop(struct rtl8169_private * tp)1407 static void rtl8168_driver_stop(struct rtl8169_private *tp)
1408 {
1409 	if (tp->dash_type == RTL_DASH_DP)
1410 		rtl8168dp_driver_stop(tp);
1411 	else if (tp->dash_type == RTL_DASH_25_BP)
1412 		rtl8125bp_driver_stop(tp);
1413 	else
1414 		rtl8168ep_driver_stop(tp);
1415 }
1416 
r8168dp_check_dash(struct rtl8169_private * tp)1417 static bool r8168dp_check_dash(struct rtl8169_private *tp)
1418 {
1419 	u16 reg = rtl8168_get_ocp_reg(tp);
1420 
1421 	return r8168dp_ocp_read(tp, reg) & BIT(15);
1422 }
1423 
r8168ep_check_dash(struct rtl8169_private * tp)1424 static bool r8168ep_check_dash(struct rtl8169_private *tp)
1425 {
1426 	return r8168ep_ocp_read(tp, 0x128) & BIT(0);
1427 }
1428 
rtl_dash_is_enabled(struct rtl8169_private * tp)1429 static bool rtl_dash_is_enabled(struct rtl8169_private *tp)
1430 {
1431 	switch (tp->dash_type) {
1432 	case RTL_DASH_DP:
1433 		return r8168dp_check_dash(tp);
1434 	case RTL_DASH_EP:
1435 	case RTL_DASH_25_BP:
1436 		return r8168ep_check_dash(tp);
1437 	default:
1438 		return false;
1439 	}
1440 }
1441 
rtl_get_dash_type(struct rtl8169_private * tp)1442 static enum rtl_dash_type rtl_get_dash_type(struct rtl8169_private *tp)
1443 {
1444 	switch (tp->mac_version) {
1445 	case RTL_GIGA_MAC_VER_28:
1446 	case RTL_GIGA_MAC_VER_31:
1447 		return RTL_DASH_DP;
1448 	case RTL_GIGA_MAC_VER_51 ... RTL_GIGA_MAC_VER_53:
1449 		return RTL_DASH_EP;
1450 	case RTL_GIGA_MAC_VER_66:
1451 		return RTL_DASH_25_BP;
1452 	default:
1453 		return RTL_DASH_NONE;
1454 	}
1455 }
1456 
rtl_set_d3_pll_down(struct rtl8169_private * tp,bool enable)1457 static void rtl_set_d3_pll_down(struct rtl8169_private *tp, bool enable)
1458 {
1459 	if (tp->mac_version >= RTL_GIGA_MAC_VER_25 &&
1460 	    tp->mac_version != RTL_GIGA_MAC_VER_28 &&
1461 	    tp->mac_version != RTL_GIGA_MAC_VER_31 &&
1462 	    tp->mac_version != RTL_GIGA_MAC_VER_38)
1463 		r8169_mod_reg8_cond(tp, PMCH, D3_NO_PLL_DOWN, !enable);
1464 }
1465 
rtl_reset_packet_filter(struct rtl8169_private * tp)1466 static void rtl_reset_packet_filter(struct rtl8169_private *tp)
1467 {
1468 	rtl_eri_clear_bits(tp, 0xdc, BIT(0));
1469 	rtl_eri_set_bits(tp, 0xdc, BIT(0));
1470 }
1471 
DECLARE_RTL_COND(rtl_efusear_cond)1472 DECLARE_RTL_COND(rtl_efusear_cond)
1473 {
1474 	return RTL_R32(tp, EFUSEAR) & EFUSEAR_FLAG;
1475 }
1476 
rtl8168d_efuse_read(struct rtl8169_private * tp,int reg_addr)1477 u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr)
1478 {
1479 	RTL_W32(tp, EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1480 
1481 	return rtl_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ?
1482 		RTL_R32(tp, EFUSEAR) & EFUSEAR_DATA_MASK : ~0;
1483 }
1484 
rtl_get_events(struct rtl8169_private * tp)1485 static u32 rtl_get_events(struct rtl8169_private *tp)
1486 {
1487 	if (rtl_is_8125(tp))
1488 		return RTL_R32(tp, IntrStatus_8125);
1489 	else
1490 		return RTL_R16(tp, IntrStatus);
1491 }
1492 
rtl_ack_events(struct rtl8169_private * tp,u32 bits)1493 static void rtl_ack_events(struct rtl8169_private *tp, u32 bits)
1494 {
1495 	if (rtl_is_8125(tp))
1496 		RTL_W32(tp, IntrStatus_8125, bits);
1497 	else
1498 		RTL_W16(tp, IntrStatus, bits);
1499 }
1500 
rtl_irq_disable(struct rtl8169_private * tp)1501 static void rtl_irq_disable(struct rtl8169_private *tp)
1502 {
1503 	if (rtl_is_8125(tp))
1504 		RTL_W32(tp, IntrMask_8125, 0);
1505 	else
1506 		RTL_W16(tp, IntrMask, 0);
1507 }
1508 
rtl_irq_enable(struct rtl8169_private * tp)1509 static void rtl_irq_enable(struct rtl8169_private *tp)
1510 {
1511 	if (rtl_is_8125(tp))
1512 		RTL_W32(tp, IntrMask_8125, tp->irq_mask);
1513 	else
1514 		RTL_W16(tp, IntrMask, tp->irq_mask);
1515 }
1516 
rtl8169_irq_mask_and_ack(struct rtl8169_private * tp)1517 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1518 {
1519 	rtl_irq_disable(tp);
1520 	rtl_ack_events(tp, 0xffffffff);
1521 	rtl_pci_commit(tp);
1522 }
1523 
rtl_link_chg_patch(struct rtl8169_private * tp)1524 static void rtl_link_chg_patch(struct rtl8169_private *tp)
1525 {
1526 	struct phy_device *phydev = tp->phydev;
1527 
1528 	if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
1529 	    tp->mac_version == RTL_GIGA_MAC_VER_38) {
1530 		if (phydev->speed == SPEED_1000) {
1531 			rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011);
1532 			rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);
1533 		} else if (phydev->speed == SPEED_100) {
1534 			rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);
1535 			rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);
1536 		} else {
1537 			rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);
1538 			rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f);
1539 		}
1540 		rtl_reset_packet_filter(tp);
1541 	} else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1542 		   tp->mac_version == RTL_GIGA_MAC_VER_36) {
1543 		if (phydev->speed == SPEED_1000) {
1544 			rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011);
1545 			rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);
1546 		} else {
1547 			rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);
1548 			rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f);
1549 		}
1550 	} else if (tp->mac_version == RTL_GIGA_MAC_VER_37) {
1551 		if (phydev->speed == SPEED_10) {
1552 			rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02);
1553 			rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060a);
1554 		} else {
1555 			rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000);
1556 		}
1557 	}
1558 }
1559 
1560 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1561 
rtl8169_get_wol(struct net_device * dev,struct ethtool_wolinfo * wol)1562 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1563 {
1564 	struct rtl8169_private *tp = netdev_priv(dev);
1565 
1566 	wol->supported = WAKE_ANY;
1567 	wol->wolopts = tp->saved_wolopts;
1568 }
1569 
__rtl8169_set_wol(struct rtl8169_private * tp,u32 wolopts)1570 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1571 {
1572 	rtl_unlock_config_regs(tp);
1573 
1574 	if (rtl_is_8168evl_up(tp)) {
1575 		if (wolopts & WAKE_MAGIC)
1576 			rtl_eri_set_bits(tp, 0x0dc, MagicPacket_v2);
1577 		else
1578 			rtl_eri_clear_bits(tp, 0x0dc, MagicPacket_v2);
1579 	} else if (rtl_is_8125(tp)) {
1580 		if (wolopts & WAKE_MAGIC)
1581 			r8168_mac_ocp_modify(tp, 0xc0b6, 0, BIT(0));
1582 		else
1583 			r8168_mac_ocp_modify(tp, 0xc0b6, BIT(0), 0);
1584 	} else {
1585 		r8169_mod_reg8_cond(tp, Config3, MagicPacket,
1586 				    wolopts & WAKE_MAGIC);
1587 	}
1588 
1589 	r8169_mod_reg8_cond(tp, Config3, LinkUp, wolopts & WAKE_PHY);
1590 	if (rtl_is_8125(tp))
1591 		r8168_mac_ocp_modify(tp, 0xe0c6, 0x3f,
1592 				     wolopts & WAKE_PHY ? 0x13 : 0);
1593 	r8169_mod_reg8_cond(tp, Config5, UWF, wolopts & WAKE_UCAST);
1594 	r8169_mod_reg8_cond(tp, Config5, BWF, wolopts & WAKE_BCAST);
1595 	r8169_mod_reg8_cond(tp, Config5, MWF, wolopts & WAKE_MCAST);
1596 	r8169_mod_reg8_cond(tp, Config5, LanWake, wolopts);
1597 
1598 	switch (tp->mac_version) {
1599 	case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
1600 		r8169_mod_reg8_cond(tp, Config1, PMEnable, wolopts);
1601 		break;
1602 	case RTL_GIGA_MAC_VER_34:
1603 	case RTL_GIGA_MAC_VER_37:
1604 	case RTL_GIGA_MAC_VER_39 ... RTL_GIGA_MAC_VER_71:
1605 		r8169_mod_reg8_cond(tp, Config2, PME_SIGNAL, wolopts);
1606 		break;
1607 	default:
1608 		break;
1609 	}
1610 
1611 	rtl_lock_config_regs(tp);
1612 
1613 	device_set_wakeup_enable(tp_to_dev(tp), wolopts);
1614 
1615 	if (!tp->dash_enabled) {
1616 		rtl_set_d3_pll_down(tp, !wolopts);
1617 		tp->dev->ethtool->wol_enabled = wolopts ? 1 : 0;
1618 	}
1619 }
1620 
rtl8169_set_wol(struct net_device * dev,struct ethtool_wolinfo * wol)1621 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1622 {
1623 	struct rtl8169_private *tp = netdev_priv(dev);
1624 
1625 	if (wol->wolopts & ~WAKE_ANY)
1626 		return -EINVAL;
1627 
1628 	tp->saved_wolopts = wol->wolopts;
1629 	__rtl8169_set_wol(tp, tp->saved_wolopts);
1630 
1631 	return 0;
1632 }
1633 
rtl8169_get_drvinfo(struct net_device * dev,struct ethtool_drvinfo * info)1634 static void rtl8169_get_drvinfo(struct net_device *dev,
1635 				struct ethtool_drvinfo *info)
1636 {
1637 	struct rtl8169_private *tp = netdev_priv(dev);
1638 	struct rtl_fw *rtl_fw = tp->rtl_fw;
1639 
1640 	strscpy(info->driver, KBUILD_MODNAME, sizeof(info->driver));
1641 	strscpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
1642 	BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
1643 	if (rtl_fw)
1644 		strscpy(info->fw_version, rtl_fw->version,
1645 			sizeof(info->fw_version));
1646 }
1647 
rtl8169_get_regs_len(struct net_device * dev)1648 static int rtl8169_get_regs_len(struct net_device *dev)
1649 {
1650 	return R8169_REGS_SIZE;
1651 }
1652 
rtl8169_fix_features(struct net_device * dev,netdev_features_t features)1653 static netdev_features_t rtl8169_fix_features(struct net_device *dev,
1654 	netdev_features_t features)
1655 {
1656 	struct rtl8169_private *tp = netdev_priv(dev);
1657 
1658 	if (dev->mtu > TD_MSS_MAX)
1659 		features &= ~NETIF_F_ALL_TSO;
1660 
1661 	if (dev->mtu > ETH_DATA_LEN &&
1662 	    tp->mac_version > RTL_GIGA_MAC_VER_06)
1663 		features &= ~(NETIF_F_CSUM_MASK | NETIF_F_ALL_TSO);
1664 
1665 	return features;
1666 }
1667 
rtl_set_rx_config_features(struct rtl8169_private * tp,netdev_features_t features)1668 static void rtl_set_rx_config_features(struct rtl8169_private *tp,
1669 				       netdev_features_t features)
1670 {
1671 	u32 rx_config = RTL_R32(tp, RxConfig);
1672 
1673 	if (features & NETIF_F_RXALL)
1674 		rx_config |= RX_CONFIG_ACCEPT_ERR_MASK;
1675 	else
1676 		rx_config &= ~RX_CONFIG_ACCEPT_ERR_MASK;
1677 
1678 	if (rtl_is_8125(tp)) {
1679 		if (features & NETIF_F_HW_VLAN_CTAG_RX)
1680 			rx_config |= RX_VLAN_8125;
1681 		else
1682 			rx_config &= ~RX_VLAN_8125;
1683 	}
1684 
1685 	RTL_W32(tp, RxConfig, rx_config);
1686 }
1687 
rtl8169_set_features(struct net_device * dev,netdev_features_t features)1688 static int rtl8169_set_features(struct net_device *dev,
1689 				netdev_features_t features)
1690 {
1691 	struct rtl8169_private *tp = netdev_priv(dev);
1692 
1693 	rtl_set_rx_config_features(tp, features);
1694 
1695 	if (features & NETIF_F_RXCSUM)
1696 		tp->cp_cmd |= RxChkSum;
1697 	else
1698 		tp->cp_cmd &= ~RxChkSum;
1699 
1700 	if (!rtl_is_8125(tp)) {
1701 		if (features & NETIF_F_HW_VLAN_CTAG_RX)
1702 			tp->cp_cmd |= RxVlan;
1703 		else
1704 			tp->cp_cmd &= ~RxVlan;
1705 	}
1706 
1707 	RTL_W16(tp, CPlusCmd, tp->cp_cmd);
1708 	rtl_pci_commit(tp);
1709 
1710 	return 0;
1711 }
1712 
rtl8169_tx_vlan_tag(struct sk_buff * skb)1713 static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb)
1714 {
1715 	return (skb_vlan_tag_present(skb)) ?
1716 		TxVlanTag | swab16(skb_vlan_tag_get(skb)) : 0x00;
1717 }
1718 
rtl8169_rx_vlan_tag(struct RxDesc * desc,struct sk_buff * skb)1719 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1720 {
1721 	u32 opts2 = le32_to_cpu(desc->opts2);
1722 
1723 	if (opts2 & RxVlanTag)
1724 		__vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff));
1725 }
1726 
rtl8169_get_regs(struct net_device * dev,struct ethtool_regs * regs,void * p)1727 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1728 			     void *p)
1729 {
1730 	struct rtl8169_private *tp = netdev_priv(dev);
1731 	u32 __iomem *data = tp->mmio_addr;
1732 	u32 *dw = p;
1733 	int i;
1734 
1735 	for (i = 0; i < R8169_REGS_SIZE; i += 4)
1736 		memcpy_fromio(dw++, data++, 4);
1737 }
1738 
1739 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1740 	"tx_packets",
1741 	"rx_packets",
1742 	"tx_errors",
1743 	"rx_errors",
1744 	"rx_missed",
1745 	"align_errors",
1746 	"tx_single_collisions",
1747 	"tx_multi_collisions",
1748 	"unicast",
1749 	"broadcast",
1750 	"multicast",
1751 	"tx_aborted",
1752 	"tx_underrun",
1753 };
1754 
rtl8169_get_sset_count(struct net_device * dev,int sset)1755 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1756 {
1757 	switch (sset) {
1758 	case ETH_SS_STATS:
1759 		return ARRAY_SIZE(rtl8169_gstrings);
1760 	default:
1761 		return -EOPNOTSUPP;
1762 	}
1763 }
1764 
DECLARE_RTL_COND(rtl_counters_cond)1765 DECLARE_RTL_COND(rtl_counters_cond)
1766 {
1767 	return RTL_R32(tp, CounterAddrLow) & (CounterReset | CounterDump);
1768 }
1769 
rtl8169_do_counters(struct rtl8169_private * tp,u32 counter_cmd)1770 static void rtl8169_do_counters(struct rtl8169_private *tp, u32 counter_cmd)
1771 {
1772 	u32 cmd = lower_32_bits(tp->counters_phys_addr);
1773 
1774 	RTL_W32(tp, CounterAddrHigh, upper_32_bits(tp->counters_phys_addr));
1775 	rtl_pci_commit(tp);
1776 	RTL_W32(tp, CounterAddrLow, cmd);
1777 	RTL_W32(tp, CounterAddrLow, cmd | counter_cmd);
1778 
1779 	rtl_loop_wait_low(tp, &rtl_counters_cond, 10, 1000);
1780 }
1781 
rtl8169_update_counters(struct rtl8169_private * tp)1782 static void rtl8169_update_counters(struct rtl8169_private *tp)
1783 {
1784 	u8 val = RTL_R8(tp, ChipCmd);
1785 
1786 	/*
1787 	 * Some chips are unable to dump tally counters when the receiver
1788 	 * is disabled. If 0xff chip may be in a PCI power-save state.
1789 	 */
1790 	if (val & CmdRxEnb && val != 0xff)
1791 		rtl8169_do_counters(tp, CounterDump);
1792 }
1793 
rtl8169_init_counter_offsets(struct rtl8169_private * tp)1794 static void rtl8169_init_counter_offsets(struct rtl8169_private *tp)
1795 {
1796 	struct rtl8169_counters *counters = tp->counters;
1797 
1798 	/*
1799 	 * rtl8169_init_counter_offsets is called from rtl_open.  On chip
1800 	 * versions prior to RTL_GIGA_MAC_VER_19 the tally counters are only
1801 	 * reset by a power cycle, while the counter values collected by the
1802 	 * driver are reset at every driver unload/load cycle.
1803 	 *
1804 	 * To make sure the HW values returned by @get_stats64 match the SW
1805 	 * values, we collect the initial values at first open(*) and use them
1806 	 * as offsets to normalize the values returned by @get_stats64.
1807 	 *
1808 	 * (*) We can't call rtl8169_init_counter_offsets from rtl_init_one
1809 	 * for the reason stated in rtl8169_update_counters; CmdRxEnb is only
1810 	 * set at open time by rtl_hw_start.
1811 	 */
1812 
1813 	if (tp->tc_offset.inited)
1814 		return;
1815 
1816 	if (tp->mac_version >= RTL_GIGA_MAC_VER_19) {
1817 		rtl8169_do_counters(tp, CounterReset);
1818 	} else {
1819 		rtl8169_update_counters(tp);
1820 		tp->tc_offset.tx_errors = counters->tx_errors;
1821 		tp->tc_offset.tx_multi_collision = counters->tx_multi_collision;
1822 		tp->tc_offset.tx_aborted = counters->tx_aborted;
1823 		tp->tc_offset.rx_missed = counters->rx_missed;
1824 	}
1825 
1826 	tp->tc_offset.inited = true;
1827 }
1828 
rtl8169_get_ethtool_stats(struct net_device * dev,struct ethtool_stats * stats,u64 * data)1829 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1830 				      struct ethtool_stats *stats, u64 *data)
1831 {
1832 	struct rtl8169_private *tp = netdev_priv(dev);
1833 	struct rtl8169_counters *counters;
1834 
1835 	counters = tp->counters;
1836 	rtl8169_update_counters(tp);
1837 
1838 	data[0] = le64_to_cpu(counters->tx_packets);
1839 	data[1] = le64_to_cpu(counters->rx_packets);
1840 	data[2] = le64_to_cpu(counters->tx_errors);
1841 	data[3] = le32_to_cpu(counters->rx_errors);
1842 	data[4] = le16_to_cpu(counters->rx_missed);
1843 	data[5] = le16_to_cpu(counters->align_errors);
1844 	data[6] = le32_to_cpu(counters->tx_one_collision);
1845 	data[7] = le32_to_cpu(counters->tx_multi_collision);
1846 	data[8] = le64_to_cpu(counters->rx_unicast);
1847 	data[9] = le64_to_cpu(counters->rx_broadcast);
1848 	data[10] = le32_to_cpu(counters->rx_multicast);
1849 	data[11] = le16_to_cpu(counters->tx_aborted);
1850 	data[12] = le16_to_cpu(counters->tx_underrun);
1851 }
1852 
rtl8169_get_strings(struct net_device * dev,u32 stringset,u8 * data)1853 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1854 {
1855 	switch(stringset) {
1856 	case ETH_SS_STATS:
1857 		memcpy(data, rtl8169_gstrings, sizeof(rtl8169_gstrings));
1858 		break;
1859 	}
1860 }
1861 
1862 /*
1863  * Interrupt coalescing
1864  *
1865  * > 1 - the availability of the IntrMitigate (0xe2) register through the
1866  * >     8169, 8168 and 810x line of chipsets
1867  *
1868  * 8169, 8168, and 8136(810x) serial chipsets support it.
1869  *
1870  * > 2 - the Tx timer unit at gigabit speed
1871  *
1872  * The unit of the timer depends on both the speed and the setting of CPlusCmd
1873  * (0xe0) bit 1 and bit 0.
1874  *
1875  * For 8169
1876  * bit[1:0] \ speed        1000M           100M            10M
1877  * 0 0                     320ns           2.56us          40.96us
1878  * 0 1                     2.56us          20.48us         327.7us
1879  * 1 0                     5.12us          40.96us         655.4us
1880  * 1 1                     10.24us         81.92us         1.31ms
1881  *
1882  * For the other
1883  * bit[1:0] \ speed        1000M           100M            10M
1884  * 0 0                     5us             2.56us          40.96us
1885  * 0 1                     40us            20.48us         327.7us
1886  * 1 0                     80us            40.96us         655.4us
1887  * 1 1                     160us           81.92us         1.31ms
1888  */
1889 
1890 /* rx/tx scale factors for all CPlusCmd[0:1] cases */
1891 struct rtl_coalesce_info {
1892 	u32 speed;
1893 	u32 scale_nsecs[4];
1894 };
1895 
1896 /* produce array with base delay *1, *8, *8*2, *8*2*2 */
1897 #define COALESCE_DELAY(d) { (d), 8 * (d), 16 * (d), 32 * (d) }
1898 
1899 static const struct rtl_coalesce_info rtl_coalesce_info_8169[] = {
1900 	{ SPEED_1000,	COALESCE_DELAY(320) },
1901 	{ SPEED_100,	COALESCE_DELAY(2560) },
1902 	{ SPEED_10,	COALESCE_DELAY(40960) },
1903 	{ 0 },
1904 };
1905 
1906 static const struct rtl_coalesce_info rtl_coalesce_info_8168_8136[] = {
1907 	{ SPEED_1000,	COALESCE_DELAY(5000) },
1908 	{ SPEED_100,	COALESCE_DELAY(2560) },
1909 	{ SPEED_10,	COALESCE_DELAY(40960) },
1910 	{ 0 },
1911 };
1912 #undef COALESCE_DELAY
1913 
1914 /* get rx/tx scale vector corresponding to current speed */
1915 static const struct rtl_coalesce_info *
rtl_coalesce_info(struct rtl8169_private * tp)1916 rtl_coalesce_info(struct rtl8169_private *tp)
1917 {
1918 	const struct rtl_coalesce_info *ci;
1919 
1920 	if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
1921 		ci = rtl_coalesce_info_8169;
1922 	else
1923 		ci = rtl_coalesce_info_8168_8136;
1924 
1925 	/* if speed is unknown assume highest one */
1926 	if (tp->phydev->speed == SPEED_UNKNOWN)
1927 		return ci;
1928 
1929 	for (; ci->speed; ci++) {
1930 		if (tp->phydev->speed == ci->speed)
1931 			return ci;
1932 	}
1933 
1934 	return ERR_PTR(-ELNRNG);
1935 }
1936 
rtl_get_coalesce(struct net_device * dev,struct ethtool_coalesce * ec,struct kernel_ethtool_coalesce * kernel_coal,struct netlink_ext_ack * extack)1937 static int rtl_get_coalesce(struct net_device *dev,
1938 			    struct ethtool_coalesce *ec,
1939 			    struct kernel_ethtool_coalesce *kernel_coal,
1940 			    struct netlink_ext_ack *extack)
1941 {
1942 	struct rtl8169_private *tp = netdev_priv(dev);
1943 	const struct rtl_coalesce_info *ci;
1944 	u32 scale, c_us, c_fr;
1945 	u16 intrmit;
1946 
1947 	if (rtl_is_8125(tp))
1948 		return -EOPNOTSUPP;
1949 
1950 	memset(ec, 0, sizeof(*ec));
1951 
1952 	/* get rx/tx scale corresponding to current speed and CPlusCmd[0:1] */
1953 	ci = rtl_coalesce_info(tp);
1954 	if (IS_ERR(ci))
1955 		return PTR_ERR(ci);
1956 
1957 	scale = ci->scale_nsecs[tp->cp_cmd & INTT_MASK];
1958 
1959 	intrmit = RTL_R16(tp, IntrMitigate);
1960 
1961 	c_us = FIELD_GET(RTL_COALESCE_TX_USECS, intrmit);
1962 	ec->tx_coalesce_usecs = DIV_ROUND_UP(c_us * scale, 1000);
1963 
1964 	c_fr = FIELD_GET(RTL_COALESCE_TX_FRAMES, intrmit);
1965 	/* ethtool_coalesce states usecs and max_frames must not both be 0 */
1966 	ec->tx_max_coalesced_frames = (c_us || c_fr) ? c_fr * 4 : 1;
1967 
1968 	c_us = FIELD_GET(RTL_COALESCE_RX_USECS, intrmit);
1969 	ec->rx_coalesce_usecs = DIV_ROUND_UP(c_us * scale, 1000);
1970 
1971 	c_fr = FIELD_GET(RTL_COALESCE_RX_FRAMES, intrmit);
1972 	ec->rx_max_coalesced_frames = (c_us || c_fr) ? c_fr * 4 : 1;
1973 
1974 	return 0;
1975 }
1976 
1977 /* choose appropriate scale factor and CPlusCmd[0:1] for (speed, usec) */
rtl_coalesce_choose_scale(struct rtl8169_private * tp,u32 usec,u16 * cp01)1978 static int rtl_coalesce_choose_scale(struct rtl8169_private *tp, u32 usec,
1979 				     u16 *cp01)
1980 {
1981 	const struct rtl_coalesce_info *ci;
1982 	u16 i;
1983 
1984 	ci = rtl_coalesce_info(tp);
1985 	if (IS_ERR(ci))
1986 		return PTR_ERR(ci);
1987 
1988 	for (i = 0; i < 4; i++) {
1989 		if (usec <= ci->scale_nsecs[i] * RTL_COALESCE_T_MAX / 1000U) {
1990 			*cp01 = i;
1991 			return ci->scale_nsecs[i];
1992 		}
1993 	}
1994 
1995 	return -ERANGE;
1996 }
1997 
rtl_set_coalesce(struct net_device * dev,struct ethtool_coalesce * ec,struct kernel_ethtool_coalesce * kernel_coal,struct netlink_ext_ack * extack)1998 static int rtl_set_coalesce(struct net_device *dev,
1999 			    struct ethtool_coalesce *ec,
2000 			    struct kernel_ethtool_coalesce *kernel_coal,
2001 			    struct netlink_ext_ack *extack)
2002 {
2003 	struct rtl8169_private *tp = netdev_priv(dev);
2004 	u32 tx_fr = ec->tx_max_coalesced_frames;
2005 	u32 rx_fr = ec->rx_max_coalesced_frames;
2006 	u32 coal_usec_max, units;
2007 	u16 w = 0, cp01 = 0;
2008 	int scale;
2009 
2010 	if (rtl_is_8125(tp))
2011 		return -EOPNOTSUPP;
2012 
2013 	if (rx_fr > RTL_COALESCE_FRAME_MAX || tx_fr > RTL_COALESCE_FRAME_MAX)
2014 		return -ERANGE;
2015 
2016 	coal_usec_max = max(ec->rx_coalesce_usecs, ec->tx_coalesce_usecs);
2017 	scale = rtl_coalesce_choose_scale(tp, coal_usec_max, &cp01);
2018 	if (scale < 0)
2019 		return scale;
2020 
2021 	/* Accept max_frames=1 we returned in rtl_get_coalesce. Accept it
2022 	 * not only when usecs=0 because of e.g. the following scenario:
2023 	 *
2024 	 * - both rx_usecs=0 & rx_frames=0 in hardware (no delay on RX)
2025 	 * - rtl_get_coalesce returns rx_usecs=0, rx_frames=1
2026 	 * - then user does `ethtool -C eth0 rx-usecs 100`
2027 	 *
2028 	 * Since ethtool sends to kernel whole ethtool_coalesce settings,
2029 	 * if we want to ignore rx_frames then it has to be set to 0.
2030 	 */
2031 	if (rx_fr == 1)
2032 		rx_fr = 0;
2033 	if (tx_fr == 1)
2034 		tx_fr = 0;
2035 
2036 	/* HW requires time limit to be set if frame limit is set */
2037 	if ((tx_fr && !ec->tx_coalesce_usecs) ||
2038 	    (rx_fr && !ec->rx_coalesce_usecs))
2039 		return -EINVAL;
2040 
2041 	w |= FIELD_PREP(RTL_COALESCE_TX_FRAMES, DIV_ROUND_UP(tx_fr, 4));
2042 	w |= FIELD_PREP(RTL_COALESCE_RX_FRAMES, DIV_ROUND_UP(rx_fr, 4));
2043 
2044 	units = DIV_ROUND_UP(ec->tx_coalesce_usecs * 1000U, scale);
2045 	w |= FIELD_PREP(RTL_COALESCE_TX_USECS, units);
2046 	units = DIV_ROUND_UP(ec->rx_coalesce_usecs * 1000U, scale);
2047 	w |= FIELD_PREP(RTL_COALESCE_RX_USECS, units);
2048 
2049 	RTL_W16(tp, IntrMitigate, w);
2050 
2051 	/* Meaning of PktCntrDisable bit changed from RTL8168e-vl */
2052 	if (rtl_is_8168evl_up(tp)) {
2053 		if (!rx_fr && !tx_fr)
2054 			/* disable packet counter */
2055 			tp->cp_cmd |= PktCntrDisable;
2056 		else
2057 			tp->cp_cmd &= ~PktCntrDisable;
2058 	}
2059 
2060 	tp->cp_cmd = (tp->cp_cmd & ~INTT_MASK) | cp01;
2061 	RTL_W16(tp, CPlusCmd, tp->cp_cmd);
2062 	rtl_pci_commit(tp);
2063 
2064 	return 0;
2065 }
2066 
rtl_set_eee_txidle_timer(struct rtl8169_private * tp)2067 static void rtl_set_eee_txidle_timer(struct rtl8169_private *tp)
2068 {
2069 	unsigned int timer_val = READ_ONCE(tp->dev->mtu) + ETH_HLEN + 0x20;
2070 
2071 	switch (tp->mac_version) {
2072 	case RTL_GIGA_MAC_VER_46:
2073 	case RTL_GIGA_MAC_VER_48:
2074 		tp->tx_lpi_timer = timer_val;
2075 		r8168_mac_ocp_write(tp, 0xe048, timer_val);
2076 		break;
2077 	case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_71:
2078 		tp->tx_lpi_timer = timer_val;
2079 		RTL_W16(tp, EEE_TXIDLE_TIMER_8125, timer_val);
2080 		break;
2081 	default:
2082 		break;
2083 	}
2084 }
2085 
r8169_get_tx_lpi_timer_us(struct rtl8169_private * tp)2086 static unsigned int r8169_get_tx_lpi_timer_us(struct rtl8169_private *tp)
2087 {
2088 	unsigned int speed = tp->phydev->speed;
2089 	unsigned int timer = tp->tx_lpi_timer;
2090 
2091 	if (!timer || speed == SPEED_UNKNOWN)
2092 		return 0;
2093 
2094 	/* tx_lpi_timer value is in bytes */
2095 	return DIV_ROUND_CLOSEST(timer * BITS_PER_BYTE, speed);
2096 }
2097 
rtl8169_get_eee(struct net_device * dev,struct ethtool_keee * data)2098 static int rtl8169_get_eee(struct net_device *dev, struct ethtool_keee *data)
2099 {
2100 	struct rtl8169_private *tp = netdev_priv(dev);
2101 	int ret;
2102 
2103 	if (!rtl_supports_eee(tp))
2104 		return -EOPNOTSUPP;
2105 
2106 	ret = phy_ethtool_get_eee(tp->phydev, data);
2107 	if (ret)
2108 		return ret;
2109 
2110 	data->tx_lpi_timer = r8169_get_tx_lpi_timer_us(tp);
2111 
2112 	return 0;
2113 }
2114 
rtl8169_set_eee(struct net_device * dev,struct ethtool_keee * data)2115 static int rtl8169_set_eee(struct net_device *dev, struct ethtool_keee *data)
2116 {
2117 	struct rtl8169_private *tp = netdev_priv(dev);
2118 
2119 	if (!rtl_supports_eee(tp))
2120 		return -EOPNOTSUPP;
2121 
2122 	return phy_ethtool_set_eee(tp->phydev, data);
2123 }
2124 
rtl8169_get_ringparam(struct net_device * dev,struct ethtool_ringparam * data,struct kernel_ethtool_ringparam * kernel_data,struct netlink_ext_ack * extack)2125 static void rtl8169_get_ringparam(struct net_device *dev,
2126 				  struct ethtool_ringparam *data,
2127 				  struct kernel_ethtool_ringparam *kernel_data,
2128 				  struct netlink_ext_ack *extack)
2129 {
2130 	data->rx_max_pending = NUM_RX_DESC;
2131 	data->rx_pending = NUM_RX_DESC;
2132 	data->tx_max_pending = NUM_TX_DESC;
2133 	data->tx_pending = NUM_TX_DESC;
2134 }
2135 
rtl8169_get_pause_stats(struct net_device * dev,struct ethtool_pause_stats * pause_stats)2136 static void rtl8169_get_pause_stats(struct net_device *dev,
2137 				    struct ethtool_pause_stats *pause_stats)
2138 {
2139 	struct rtl8169_private *tp = netdev_priv(dev);
2140 
2141 	if (!rtl_is_8125(tp))
2142 		return;
2143 
2144 	rtl8169_update_counters(tp);
2145 	pause_stats->tx_pause_frames = le32_to_cpu(tp->counters->tx_pause_on);
2146 	pause_stats->rx_pause_frames = le32_to_cpu(tp->counters->rx_pause_on);
2147 }
2148 
rtl8169_get_pauseparam(struct net_device * dev,struct ethtool_pauseparam * data)2149 static void rtl8169_get_pauseparam(struct net_device *dev,
2150 				   struct ethtool_pauseparam *data)
2151 {
2152 	struct rtl8169_private *tp = netdev_priv(dev);
2153 	bool tx_pause, rx_pause;
2154 
2155 	phy_get_pause(tp->phydev, &tx_pause, &rx_pause);
2156 
2157 	data->autoneg = tp->phydev->autoneg;
2158 	data->tx_pause = tx_pause ? 1 : 0;
2159 	data->rx_pause = rx_pause ? 1 : 0;
2160 }
2161 
rtl8169_set_pauseparam(struct net_device * dev,struct ethtool_pauseparam * data)2162 static int rtl8169_set_pauseparam(struct net_device *dev,
2163 				  struct ethtool_pauseparam *data)
2164 {
2165 	struct rtl8169_private *tp = netdev_priv(dev);
2166 
2167 	if (dev->mtu > ETH_DATA_LEN)
2168 		return -EOPNOTSUPP;
2169 
2170 	phy_set_asym_pause(tp->phydev, data->rx_pause, data->tx_pause);
2171 
2172 	return 0;
2173 }
2174 
rtl8169_get_eth_mac_stats(struct net_device * dev,struct ethtool_eth_mac_stats * mac_stats)2175 static void rtl8169_get_eth_mac_stats(struct net_device *dev,
2176 				      struct ethtool_eth_mac_stats *mac_stats)
2177 {
2178 	struct rtl8169_private *tp = netdev_priv(dev);
2179 
2180 	rtl8169_update_counters(tp);
2181 
2182 	mac_stats->FramesTransmittedOK =
2183 		le64_to_cpu(tp->counters->tx_packets);
2184 	mac_stats->SingleCollisionFrames =
2185 		le32_to_cpu(tp->counters->tx_one_collision);
2186 	mac_stats->MultipleCollisionFrames =
2187 		le32_to_cpu(tp->counters->tx_multi_collision);
2188 	mac_stats->FramesReceivedOK =
2189 		le64_to_cpu(tp->counters->rx_packets);
2190 	mac_stats->AlignmentErrors =
2191 		le16_to_cpu(tp->counters->align_errors);
2192 	mac_stats->FramesLostDueToIntMACXmitError =
2193 		le64_to_cpu(tp->counters->tx_errors);
2194 	mac_stats->BroadcastFramesReceivedOK =
2195 		le64_to_cpu(tp->counters->rx_broadcast);
2196 	mac_stats->MulticastFramesReceivedOK =
2197 		le32_to_cpu(tp->counters->rx_multicast);
2198 
2199 	if (!rtl_is_8125(tp))
2200 		return;
2201 
2202 	mac_stats->AlignmentErrors =
2203 		le32_to_cpu(tp->counters->align_errors32);
2204 	mac_stats->OctetsTransmittedOK =
2205 		le64_to_cpu(tp->counters->tx_octets);
2206 	mac_stats->LateCollisions =
2207 		le32_to_cpu(tp->counters->tx_late_collision);
2208 	mac_stats->FramesAbortedDueToXSColls =
2209 		le32_to_cpu(tp->counters->tx_aborted32);
2210 	mac_stats->OctetsReceivedOK =
2211 		le64_to_cpu(tp->counters->rx_octets);
2212 	mac_stats->FramesLostDueToIntMACRcvError =
2213 		le32_to_cpu(tp->counters->rx_mac_error);
2214 	mac_stats->MulticastFramesXmittedOK =
2215 		le64_to_cpu(tp->counters->tx_multicast64);
2216 	mac_stats->BroadcastFramesXmittedOK =
2217 		le64_to_cpu(tp->counters->tx_broadcast64);
2218 	mac_stats->MulticastFramesReceivedOK =
2219 		le64_to_cpu(tp->counters->rx_multicast64);
2220 	mac_stats->FrameTooLongErrors =
2221 		le32_to_cpu(tp->counters->rx_frame_too_long);
2222 }
2223 
rtl8169_get_eth_ctrl_stats(struct net_device * dev,struct ethtool_eth_ctrl_stats * ctrl_stats)2224 static void rtl8169_get_eth_ctrl_stats(struct net_device *dev,
2225 				       struct ethtool_eth_ctrl_stats *ctrl_stats)
2226 {
2227 	struct rtl8169_private *tp = netdev_priv(dev);
2228 
2229 	if (!rtl_is_8125(tp))
2230 		return;
2231 
2232 	rtl8169_update_counters(tp);
2233 
2234 	ctrl_stats->UnsupportedOpcodesReceived =
2235 		le32_to_cpu(tp->counters->rx_unknown_opcode);
2236 }
2237 
2238 static const struct ethtool_ops rtl8169_ethtool_ops = {
2239 	.supported_coalesce_params = ETHTOOL_COALESCE_USECS |
2240 				     ETHTOOL_COALESCE_MAX_FRAMES,
2241 	.get_drvinfo		= rtl8169_get_drvinfo,
2242 	.get_regs_len		= rtl8169_get_regs_len,
2243 	.get_link		= ethtool_op_get_link,
2244 	.get_coalesce		= rtl_get_coalesce,
2245 	.set_coalesce		= rtl_set_coalesce,
2246 	.get_regs		= rtl8169_get_regs,
2247 	.get_wol		= rtl8169_get_wol,
2248 	.set_wol		= rtl8169_set_wol,
2249 	.get_strings		= rtl8169_get_strings,
2250 	.get_sset_count		= rtl8169_get_sset_count,
2251 	.get_ethtool_stats	= rtl8169_get_ethtool_stats,
2252 	.get_ts_info		= ethtool_op_get_ts_info,
2253 	.nway_reset		= phy_ethtool_nway_reset,
2254 	.get_eee		= rtl8169_get_eee,
2255 	.set_eee		= rtl8169_set_eee,
2256 	.get_link_ksettings	= phy_ethtool_get_link_ksettings,
2257 	.set_link_ksettings	= phy_ethtool_set_link_ksettings,
2258 	.get_ringparam		= rtl8169_get_ringparam,
2259 	.get_pause_stats	= rtl8169_get_pause_stats,
2260 	.get_pauseparam		= rtl8169_get_pauseparam,
2261 	.set_pauseparam		= rtl8169_set_pauseparam,
2262 	.get_eth_mac_stats	= rtl8169_get_eth_mac_stats,
2263 	.get_eth_ctrl_stats	= rtl8169_get_eth_ctrl_stats,
2264 };
2265 
rtl8169_get_mac_version(u16 xid,bool gmii)2266 static enum mac_version rtl8169_get_mac_version(u16 xid, bool gmii)
2267 {
2268 	/*
2269 	 * The driver currently handles the 8168Bf and the 8168Be identically
2270 	 * but they can be identified more specifically through the test below
2271 	 * if needed:
2272 	 *
2273 	 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
2274 	 *
2275 	 * Same thing for the 8101Eb and the 8101Ec:
2276 	 *
2277 	 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
2278 	 */
2279 	static const struct rtl_mac_info {
2280 		u16 mask;
2281 		u16 val;
2282 		enum mac_version ver;
2283 	} mac_info[] = {
2284 		/* 8126A family. */
2285 		{ 0x7cf, 0x64a,	RTL_GIGA_MAC_VER_71 },
2286 		{ 0x7cf, 0x649,	RTL_GIGA_MAC_VER_70 },
2287 
2288 		/* 8125BP family. */
2289 		{ 0x7cf, 0x681,	RTL_GIGA_MAC_VER_66 },
2290 
2291 		/* 8125D family. */
2292 		{ 0x7cf, 0x689,	RTL_GIGA_MAC_VER_65 },
2293 		{ 0x7cf, 0x688,	RTL_GIGA_MAC_VER_64 },
2294 
2295 		/* 8125B family. */
2296 		{ 0x7cf, 0x641,	RTL_GIGA_MAC_VER_63 },
2297 
2298 		/* 8125A family. */
2299 		{ 0x7cf, 0x609,	RTL_GIGA_MAC_VER_61 },
2300 		/* It seems only XID 609 made it to the mass market.
2301 		 * { 0x7cf, 0x608,	RTL_GIGA_MAC_VER_60 },
2302 		 * { 0x7c8, 0x608,	RTL_GIGA_MAC_VER_61 },
2303 		 */
2304 
2305 		/* RTL8117 */
2306 		{ 0x7cf, 0x54b,	RTL_GIGA_MAC_VER_53 },
2307 		{ 0x7cf, 0x54a,	RTL_GIGA_MAC_VER_52 },
2308 
2309 		/* 8168EP family. */
2310 		{ 0x7cf, 0x502,	RTL_GIGA_MAC_VER_51 },
2311 		/* It seems this chip version never made it to
2312 		 * the wild. Let's disable detection.
2313 		 * { 0x7cf, 0x501,      RTL_GIGA_MAC_VER_50 },
2314 		 * { 0x7cf, 0x500,      RTL_GIGA_MAC_VER_49 },
2315 		 */
2316 
2317 		/* 8168H family. */
2318 		{ 0x7cf, 0x541,	RTL_GIGA_MAC_VER_46 },
2319 		/* It seems this chip version never made it to
2320 		 * the wild. Let's disable detection.
2321 		 * { 0x7cf, 0x540,	RTL_GIGA_MAC_VER_45 },
2322 		 */
2323 		/* Realtek calls it RTL8168M, but it's handled like RTL8168H */
2324 		{ 0x7cf, 0x6c0,	RTL_GIGA_MAC_VER_46 },
2325 
2326 		/* 8168G family. */
2327 		{ 0x7cf, 0x5c8,	RTL_GIGA_MAC_VER_44 },
2328 		{ 0x7cf, 0x509,	RTL_GIGA_MAC_VER_42 },
2329 		/* It seems this chip version never made it to
2330 		 * the wild. Let's disable detection.
2331 		 * { 0x7cf, 0x4c1,	RTL_GIGA_MAC_VER_41 },
2332 		 */
2333 		{ 0x7cf, 0x4c0,	RTL_GIGA_MAC_VER_40 },
2334 
2335 		/* 8168F family. */
2336 		{ 0x7c8, 0x488,	RTL_GIGA_MAC_VER_38 },
2337 		{ 0x7cf, 0x481,	RTL_GIGA_MAC_VER_36 },
2338 		{ 0x7cf, 0x480,	RTL_GIGA_MAC_VER_35 },
2339 
2340 		/* 8168E family. */
2341 		{ 0x7c8, 0x2c8,	RTL_GIGA_MAC_VER_34 },
2342 		{ 0x7cf, 0x2c1,	RTL_GIGA_MAC_VER_32 },
2343 		{ 0x7c8, 0x2c0,	RTL_GIGA_MAC_VER_33 },
2344 
2345 		/* 8168D family. */
2346 		{ 0x7cf, 0x281,	RTL_GIGA_MAC_VER_25 },
2347 		{ 0x7c8, 0x280,	RTL_GIGA_MAC_VER_26 },
2348 
2349 		/* 8168DP family. */
2350 		/* It seems this early RTL8168dp version never made it to
2351 		 * the wild. Support has been removed.
2352 		 * { 0x7cf, 0x288,      RTL_GIGA_MAC_VER_27 },
2353 		 */
2354 		{ 0x7cf, 0x28a,	RTL_GIGA_MAC_VER_28 },
2355 		{ 0x7cf, 0x28b,	RTL_GIGA_MAC_VER_31 },
2356 
2357 		/* 8168C family. */
2358 		{ 0x7cf, 0x3c9,	RTL_GIGA_MAC_VER_23 },
2359 		{ 0x7cf, 0x3c8,	RTL_GIGA_MAC_VER_18 },
2360 		{ 0x7c8, 0x3c8,	RTL_GIGA_MAC_VER_24 },
2361 		{ 0x7cf, 0x3c0,	RTL_GIGA_MAC_VER_19 },
2362 		{ 0x7cf, 0x3c2,	RTL_GIGA_MAC_VER_20 },
2363 		{ 0x7cf, 0x3c3,	RTL_GIGA_MAC_VER_21 },
2364 		{ 0x7c8, 0x3c0,	RTL_GIGA_MAC_VER_22 },
2365 
2366 		/* 8168B family. */
2367 		{ 0x7c8, 0x380,	RTL_GIGA_MAC_VER_17 },
2368 		/* This one is very old and rare, support has been removed.
2369 		 * { 0x7c8, 0x300,	RTL_GIGA_MAC_VER_11 },
2370 		 */
2371 
2372 		/* 8101 family. */
2373 		{ 0x7c8, 0x448,	RTL_GIGA_MAC_VER_39 },
2374 		{ 0x7c8, 0x440,	RTL_GIGA_MAC_VER_37 },
2375 		{ 0x7cf, 0x409,	RTL_GIGA_MAC_VER_29 },
2376 		{ 0x7c8, 0x408,	RTL_GIGA_MAC_VER_30 },
2377 		{ 0x7cf, 0x349,	RTL_GIGA_MAC_VER_08 },
2378 		{ 0x7cf, 0x249,	RTL_GIGA_MAC_VER_08 },
2379 		{ 0x7cf, 0x348,	RTL_GIGA_MAC_VER_07 },
2380 		{ 0x7cf, 0x248,	RTL_GIGA_MAC_VER_07 },
2381 		{ 0x7cf, 0x240,	RTL_GIGA_MAC_VER_14 },
2382 		{ 0x7c8, 0x348,	RTL_GIGA_MAC_VER_09 },
2383 		{ 0x7c8, 0x248,	RTL_GIGA_MAC_VER_09 },
2384 		{ 0x7c8, 0x340,	RTL_GIGA_MAC_VER_10 },
2385 
2386 		/* 8110 family. */
2387 		{ 0xfc8, 0x980,	RTL_GIGA_MAC_VER_06 },
2388 		{ 0xfc8, 0x180,	RTL_GIGA_MAC_VER_05 },
2389 		{ 0xfc8, 0x100,	RTL_GIGA_MAC_VER_04 },
2390 		{ 0xfc8, 0x040,	RTL_GIGA_MAC_VER_03 },
2391 		{ 0xfc8, 0x008,	RTL_GIGA_MAC_VER_02 },
2392 
2393 		/* Catch-all */
2394 		{ 0x000, 0x000,	RTL_GIGA_MAC_NONE   }
2395 	};
2396 	const struct rtl_mac_info *p = mac_info;
2397 	enum mac_version ver;
2398 
2399 	while ((xid & p->mask) != p->val)
2400 		p++;
2401 	ver = p->ver;
2402 
2403 	if (ver != RTL_GIGA_MAC_NONE && !gmii) {
2404 		if (ver == RTL_GIGA_MAC_VER_42)
2405 			ver = RTL_GIGA_MAC_VER_43;
2406 		else if (ver == RTL_GIGA_MAC_VER_46)
2407 			ver = RTL_GIGA_MAC_VER_48;
2408 	}
2409 
2410 	return ver;
2411 }
2412 
rtl_release_firmware(struct rtl8169_private * tp)2413 static void rtl_release_firmware(struct rtl8169_private *tp)
2414 {
2415 	if (tp->rtl_fw) {
2416 		rtl_fw_release_firmware(tp->rtl_fw);
2417 		kfree(tp->rtl_fw);
2418 		tp->rtl_fw = NULL;
2419 	}
2420 }
2421 
r8169_apply_firmware(struct rtl8169_private * tp)2422 void r8169_apply_firmware(struct rtl8169_private *tp)
2423 {
2424 	int val;
2425 
2426 	/* TODO: release firmware if rtl_fw_write_firmware signals failure. */
2427 	if (tp->rtl_fw) {
2428 		rtl_fw_write_firmware(tp, tp->rtl_fw);
2429 		/* At least one firmware doesn't reset tp->ocp_base. */
2430 		tp->ocp_base = OCP_STD_PHY_BASE;
2431 
2432 		/* PHY soft reset may still be in progress */
2433 		phy_read_poll_timeout(tp->phydev, MII_BMCR, val,
2434 				      !(val & BMCR_RESET),
2435 				      50000, 600000, true);
2436 	}
2437 }
2438 
rtl8168_config_eee_mac(struct rtl8169_private * tp)2439 static void rtl8168_config_eee_mac(struct rtl8169_private *tp)
2440 {
2441 	/* Adjust EEE LED frequency */
2442 	if (tp->mac_version != RTL_GIGA_MAC_VER_38)
2443 		RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
2444 
2445 	rtl_eri_set_bits(tp, 0x1b0, 0x0003);
2446 }
2447 
rtl8125a_config_eee_mac(struct rtl8169_private * tp)2448 static void rtl8125a_config_eee_mac(struct rtl8169_private *tp)
2449 {
2450 	r8168_mac_ocp_modify(tp, 0xe040, 0, BIT(1) | BIT(0));
2451 	r8168_mac_ocp_modify(tp, 0xeb62, 0, BIT(2) | BIT(1));
2452 }
2453 
rtl8125b_config_eee_mac(struct rtl8169_private * tp)2454 static void rtl8125b_config_eee_mac(struct rtl8169_private *tp)
2455 {
2456 	r8168_mac_ocp_modify(tp, 0xe040, 0, BIT(1) | BIT(0));
2457 }
2458 
rtl_rar_exgmac_set(struct rtl8169_private * tp,const u8 * addr)2459 static void rtl_rar_exgmac_set(struct rtl8169_private *tp, const u8 *addr)
2460 {
2461 	rtl_eri_write(tp, 0xe0, ERIAR_MASK_1111, get_unaligned_le32(addr));
2462 	rtl_eri_write(tp, 0xe4, ERIAR_MASK_1111, get_unaligned_le16(addr + 4));
2463 	rtl_eri_write(tp, 0xf0, ERIAR_MASK_1111, get_unaligned_le16(addr) << 16);
2464 	rtl_eri_write(tp, 0xf4, ERIAR_MASK_1111, get_unaligned_le32(addr + 2));
2465 }
2466 
rtl8168h_2_get_adc_bias_ioffset(struct rtl8169_private * tp)2467 u16 rtl8168h_2_get_adc_bias_ioffset(struct rtl8169_private *tp)
2468 {
2469 	u16 data1, data2, ioffset;
2470 
2471 	r8168_mac_ocp_write(tp, 0xdd02, 0x807d);
2472 	data1 = r8168_mac_ocp_read(tp, 0xdd02);
2473 	data2 = r8168_mac_ocp_read(tp, 0xdd00);
2474 
2475 	ioffset = (data2 >> 1) & 0x7ff8;
2476 	ioffset |= data2 & 0x0007;
2477 	if (data1 & BIT(7))
2478 		ioffset |= BIT(15);
2479 
2480 	return ioffset;
2481 }
2482 
rtl_schedule_task(struct rtl8169_private * tp,enum rtl_flag flag)2483 static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)
2484 {
2485 	set_bit(flag, tp->wk.flags);
2486 	if (!schedule_work(&tp->wk.work))
2487 		clear_bit(flag, tp->wk.flags);
2488 }
2489 
rtl8169_init_phy(struct rtl8169_private * tp)2490 static void rtl8169_init_phy(struct rtl8169_private *tp)
2491 {
2492 	r8169_hw_phy_config(tp, tp->phydev, tp->mac_version);
2493 
2494 	if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
2495 		pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
2496 		pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
2497 		/* set undocumented MAC Reg C+CR Offset 0x82h */
2498 		RTL_W8(tp, 0x82, 0x01);
2499 	}
2500 
2501 	if (tp->mac_version == RTL_GIGA_MAC_VER_05 &&
2502 	    tp->pci_dev->subsystem_vendor == PCI_VENDOR_ID_GIGABYTE &&
2503 	    tp->pci_dev->subsystem_device == 0xe000)
2504 		phy_write_paged(tp->phydev, 0x0001, 0x10, 0xf01b);
2505 
2506 	/* We may have called phy_speed_down before */
2507 	phy_speed_up(tp->phydev);
2508 
2509 	genphy_soft_reset(tp->phydev);
2510 }
2511 
rtl_rar_set(struct rtl8169_private * tp,const u8 * addr)2512 static void rtl_rar_set(struct rtl8169_private *tp, const u8 *addr)
2513 {
2514 	rtl_unlock_config_regs(tp);
2515 
2516 	RTL_W32(tp, MAC4, get_unaligned_le16(addr + 4));
2517 	rtl_pci_commit(tp);
2518 
2519 	RTL_W32(tp, MAC0, get_unaligned_le32(addr));
2520 	rtl_pci_commit(tp);
2521 
2522 	if (tp->mac_version == RTL_GIGA_MAC_VER_34)
2523 		rtl_rar_exgmac_set(tp, addr);
2524 
2525 	rtl_lock_config_regs(tp);
2526 }
2527 
rtl_set_mac_address(struct net_device * dev,void * p)2528 static int rtl_set_mac_address(struct net_device *dev, void *p)
2529 {
2530 	struct rtl8169_private *tp = netdev_priv(dev);
2531 	int ret;
2532 
2533 	ret = eth_mac_addr(dev, p);
2534 	if (ret)
2535 		return ret;
2536 
2537 	rtl_rar_set(tp, dev->dev_addr);
2538 
2539 	return 0;
2540 }
2541 
rtl_init_rxcfg(struct rtl8169_private * tp)2542 static void rtl_init_rxcfg(struct rtl8169_private *tp)
2543 {
2544 	switch (tp->mac_version) {
2545 	case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
2546 	case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17:
2547 		RTL_W32(tp, RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
2548 		break;
2549 	case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24:
2550 	case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_36:
2551 	case RTL_GIGA_MAC_VER_38:
2552 		RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
2553 		break;
2554 	case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_53:
2555 		RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF);
2556 		break;
2557 	case RTL_GIGA_MAC_VER_61:
2558 		RTL_W32(tp, RxConfig, RX_FETCH_DFLT_8125 | RX_DMA_BURST);
2559 		break;
2560 	case RTL_GIGA_MAC_VER_63 ... RTL_GIGA_MAC_VER_71:
2561 		RTL_W32(tp, RxConfig, RX_FETCH_DFLT_8125 | RX_DMA_BURST |
2562 			RX_PAUSE_SLOT_ON);
2563 		break;
2564 	default:
2565 		RTL_W32(tp, RxConfig, RX128_INT_EN | RX_DMA_BURST);
2566 		break;
2567 	}
2568 }
2569 
rtl8169_init_ring_indexes(struct rtl8169_private * tp)2570 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
2571 {
2572 	tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0;
2573 }
2574 
rtl_jumbo_config(struct rtl8169_private * tp)2575 static void rtl_jumbo_config(struct rtl8169_private *tp)
2576 {
2577 	bool jumbo = tp->dev->mtu > ETH_DATA_LEN;
2578 	int readrq = 4096;
2579 
2580 	if (jumbo && tp->mac_version >= RTL_GIGA_MAC_VER_17 &&
2581 	    tp->mac_version <= RTL_GIGA_MAC_VER_26)
2582 		readrq = 512;
2583 
2584 	rtl_unlock_config_regs(tp);
2585 	switch (tp->mac_version) {
2586 	case RTL_GIGA_MAC_VER_17:
2587 		r8169_mod_reg8_cond(tp, Config4, BIT(0), jumbo);
2588 		break;
2589 	case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_26:
2590 		r8169_mod_reg8_cond(tp, Config3, Jumbo_En0, jumbo);
2591 		r8169_mod_reg8_cond(tp, Config4, Jumbo_En1, jumbo);
2592 		break;
2593 	case RTL_GIGA_MAC_VER_28:
2594 		r8169_mod_reg8_cond(tp, Config3, Jumbo_En0, jumbo);
2595 		break;
2596 	case RTL_GIGA_MAC_VER_31 ... RTL_GIGA_MAC_VER_33:
2597 		RTL_W8(tp, MaxTxPacketSize, jumbo ? 0x24 : 0x3f);
2598 		r8169_mod_reg8_cond(tp, Config3, Jumbo_En0, jumbo);
2599 		r8169_mod_reg8_cond(tp, Config4, BIT(0), jumbo);
2600 		break;
2601 	default:
2602 		break;
2603 	}
2604 	rtl_lock_config_regs(tp);
2605 
2606 	if (pci_is_pcie(tp->pci_dev) && tp->supports_gmii)
2607 		pcie_set_readrq(tp->pci_dev, readrq);
2608 
2609 	/* Chip doesn't support pause in jumbo mode */
2610 	if (jumbo) {
2611 		linkmode_clear_bit(ETHTOOL_LINK_MODE_Pause_BIT,
2612 				   tp->phydev->advertising);
2613 		linkmode_clear_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT,
2614 				   tp->phydev->advertising);
2615 		phy_start_aneg(tp->phydev);
2616 	}
2617 }
2618 
DECLARE_RTL_COND(rtl_chipcmd_cond)2619 DECLARE_RTL_COND(rtl_chipcmd_cond)
2620 {
2621 	return RTL_R8(tp, ChipCmd) & CmdReset;
2622 }
2623 
rtl_hw_reset(struct rtl8169_private * tp)2624 static void rtl_hw_reset(struct rtl8169_private *tp)
2625 {
2626 	RTL_W8(tp, ChipCmd, CmdReset);
2627 
2628 	rtl_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100);
2629 }
2630 
rtl_request_firmware(struct rtl8169_private * tp)2631 static void rtl_request_firmware(struct rtl8169_private *tp)
2632 {
2633 	struct rtl_fw *rtl_fw;
2634 
2635 	/* firmware loaded already or no firmware available */
2636 	if (tp->rtl_fw || !tp->fw_name)
2637 		return;
2638 
2639 	rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
2640 	if (!rtl_fw)
2641 		return;
2642 
2643 	rtl_fw->phy_write = rtl_writephy;
2644 	rtl_fw->phy_read = rtl_readphy;
2645 	rtl_fw->mac_mcu_write = mac_mcu_write;
2646 	rtl_fw->mac_mcu_read = mac_mcu_read;
2647 	rtl_fw->fw_name = tp->fw_name;
2648 	rtl_fw->dev = tp_to_dev(tp);
2649 
2650 	if (rtl_fw_request_firmware(rtl_fw))
2651 		kfree(rtl_fw);
2652 	else
2653 		tp->rtl_fw = rtl_fw;
2654 }
2655 
rtl_rx_close(struct rtl8169_private * tp)2656 static void rtl_rx_close(struct rtl8169_private *tp)
2657 {
2658 	RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
2659 }
2660 
DECLARE_RTL_COND(rtl_npq_cond)2661 DECLARE_RTL_COND(rtl_npq_cond)
2662 {
2663 	return RTL_R8(tp, TxPoll) & NPQ;
2664 }
2665 
DECLARE_RTL_COND(rtl_txcfg_empty_cond)2666 DECLARE_RTL_COND(rtl_txcfg_empty_cond)
2667 {
2668 	return RTL_R32(tp, TxConfig) & TXCFG_EMPTY;
2669 }
2670 
DECLARE_RTL_COND(rtl_rxtx_empty_cond)2671 DECLARE_RTL_COND(rtl_rxtx_empty_cond)
2672 {
2673 	return (RTL_R8(tp, MCU) & RXTX_EMPTY) == RXTX_EMPTY;
2674 }
2675 
DECLARE_RTL_COND(rtl_rxtx_empty_cond_2)2676 DECLARE_RTL_COND(rtl_rxtx_empty_cond_2)
2677 {
2678 	/* IntrMitigate has new functionality on RTL8125 */
2679 	return (RTL_R16(tp, IntrMitigate) & 0x0103) == 0x0103;
2680 }
2681 
rtl_wait_txrx_fifo_empty(struct rtl8169_private * tp)2682 static void rtl_wait_txrx_fifo_empty(struct rtl8169_private *tp)
2683 {
2684 	switch (tp->mac_version) {
2685 	case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_53:
2686 		rtl_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42);
2687 		rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42);
2688 		break;
2689 	case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_61:
2690 		rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42);
2691 		break;
2692 	case RTL_GIGA_MAC_VER_63 ... RTL_GIGA_MAC_VER_71:
2693 		RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
2694 		rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42);
2695 		rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond_2, 100, 42);
2696 		break;
2697 	default:
2698 		break;
2699 	}
2700 }
2701 
rtl_disable_rxdvgate(struct rtl8169_private * tp)2702 static void rtl_disable_rxdvgate(struct rtl8169_private *tp)
2703 {
2704 	RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
2705 }
2706 
rtl_enable_rxdvgate(struct rtl8169_private * tp)2707 static void rtl_enable_rxdvgate(struct rtl8169_private *tp)
2708 {
2709 	RTL_W32(tp, MISC, RTL_R32(tp, MISC) | RXDV_GATED_EN);
2710 	fsleep(2000);
2711 	rtl_wait_txrx_fifo_empty(tp);
2712 }
2713 
rtl_wol_enable_rx(struct rtl8169_private * tp)2714 static void rtl_wol_enable_rx(struct rtl8169_private *tp)
2715 {
2716 	if (tp->mac_version >= RTL_GIGA_MAC_VER_25)
2717 		RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) |
2718 			AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
2719 
2720 	if (tp->mac_version >= RTL_GIGA_MAC_VER_40)
2721 		rtl_disable_rxdvgate(tp);
2722 }
2723 
rtl_prepare_power_down(struct rtl8169_private * tp)2724 static void rtl_prepare_power_down(struct rtl8169_private *tp)
2725 {
2726 	if (tp->dash_enabled)
2727 		return;
2728 
2729 	if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
2730 	    tp->mac_version == RTL_GIGA_MAC_VER_33)
2731 		rtl_ephy_write(tp, 0x19, 0xff64);
2732 
2733 	if (device_may_wakeup(tp_to_dev(tp))) {
2734 		phy_speed_down(tp->phydev, false);
2735 		rtl_wol_enable_rx(tp);
2736 	}
2737 }
2738 
rtl_set_tx_config_registers(struct rtl8169_private * tp)2739 static void rtl_set_tx_config_registers(struct rtl8169_private *tp)
2740 {
2741 	u32 val = TX_DMA_BURST << TxDMAShift |
2742 		  InterFrameGap << TxInterFrameGapShift;
2743 
2744 	if (rtl_is_8168evl_up(tp))
2745 		val |= TXCFG_AUTO_FIFO;
2746 
2747 	RTL_W32(tp, TxConfig, val);
2748 }
2749 
rtl_set_rx_max_size(struct rtl8169_private * tp)2750 static void rtl_set_rx_max_size(struct rtl8169_private *tp)
2751 {
2752 	/* Low hurts. Let's disable the filtering. */
2753 	RTL_W16(tp, RxMaxSize, R8169_RX_BUF_SIZE + 1);
2754 }
2755 
rtl_set_rx_tx_desc_registers(struct rtl8169_private * tp)2756 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp)
2757 {
2758 	/*
2759 	 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
2760 	 * register to be written before TxDescAddrLow to work.
2761 	 * Switching from MMIO to I/O access fixes the issue as well.
2762 	 */
2763 	RTL_W32(tp, TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
2764 	RTL_W32(tp, TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
2765 	RTL_W32(tp, RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
2766 	RTL_W32(tp, RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
2767 }
2768 
rtl8169_set_magic_reg(struct rtl8169_private * tp)2769 static void rtl8169_set_magic_reg(struct rtl8169_private *tp)
2770 {
2771 	u32 val;
2772 
2773 	if (tp->mac_version == RTL_GIGA_MAC_VER_05)
2774 		val = 0x000fff00;
2775 	else if (tp->mac_version == RTL_GIGA_MAC_VER_06)
2776 		val = 0x00ffff00;
2777 	else
2778 		return;
2779 
2780 	if (RTL_R8(tp, Config2) & PCI_Clock_66MHz)
2781 		val |= 0xff;
2782 
2783 	RTL_W32(tp, 0x7c, val);
2784 }
2785 
rtl_set_rx_mode(struct net_device * dev)2786 static void rtl_set_rx_mode(struct net_device *dev)
2787 {
2788 	u32 rx_mode = AcceptBroadcast | AcceptMyPhys | AcceptMulticast;
2789 	/* Multicast hash filter */
2790 	u32 mc_filter[2] = { 0xffffffff, 0xffffffff };
2791 	struct rtl8169_private *tp = netdev_priv(dev);
2792 	u32 tmp;
2793 
2794 	if (dev->flags & IFF_PROMISC) {
2795 		rx_mode |= AcceptAllPhys;
2796 	} else if (!(dev->flags & IFF_MULTICAST)) {
2797 		rx_mode &= ~AcceptMulticast;
2798 	} else if (dev->flags & IFF_ALLMULTI ||
2799 		   tp->mac_version == RTL_GIGA_MAC_VER_35) {
2800 		/* accept all multicasts */
2801 	} else if (netdev_mc_empty(dev)) {
2802 		rx_mode &= ~AcceptMulticast;
2803 	} else {
2804 		struct netdev_hw_addr *ha;
2805 
2806 		mc_filter[1] = mc_filter[0] = 0;
2807 		netdev_for_each_mc_addr(ha, dev) {
2808 			u32 bit_nr = eth_hw_addr_crc(ha) >> 26;
2809 			mc_filter[bit_nr >> 5] |= BIT(bit_nr & 31);
2810 		}
2811 
2812 		if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
2813 			tmp = mc_filter[0];
2814 			mc_filter[0] = swab32(mc_filter[1]);
2815 			mc_filter[1] = swab32(tmp);
2816 		}
2817 	}
2818 
2819 	RTL_W32(tp, MAR0 + 4, mc_filter[1]);
2820 	RTL_W32(tp, MAR0 + 0, mc_filter[0]);
2821 
2822 	tmp = RTL_R32(tp, RxConfig);
2823 	RTL_W32(tp, RxConfig, (tmp & ~RX_CONFIG_ACCEPT_OK_MASK) | rx_mode);
2824 }
2825 
DECLARE_RTL_COND(rtl_csiar_cond)2826 DECLARE_RTL_COND(rtl_csiar_cond)
2827 {
2828 	return RTL_R32(tp, CSIAR) & CSIAR_FLAG;
2829 }
2830 
rtl_csi_write(struct rtl8169_private * tp,int addr,int value)2831 static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value)
2832 {
2833 	u32 func = PCI_FUNC(tp->pci_dev->devfn);
2834 
2835 	RTL_W32(tp, CSIDR, value);
2836 	RTL_W32(tp, CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
2837 		CSIAR_BYTE_ENABLE | func << 16);
2838 
2839 	rtl_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
2840 }
2841 
rtl_csi_read(struct rtl8169_private * tp,int addr)2842 static u32 rtl_csi_read(struct rtl8169_private *tp, int addr)
2843 {
2844 	u32 func = PCI_FUNC(tp->pci_dev->devfn);
2845 
2846 	RTL_W32(tp, CSIAR, (addr & CSIAR_ADDR_MASK) | func << 16 |
2847 		CSIAR_BYTE_ENABLE);
2848 
2849 	return rtl_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
2850 		RTL_R32(tp, CSIDR) : ~0;
2851 }
2852 
rtl_set_aspm_entry_latency(struct rtl8169_private * tp,u8 val)2853 static void rtl_set_aspm_entry_latency(struct rtl8169_private *tp, u8 val)
2854 {
2855 	struct pci_dev *pdev = tp->pci_dev;
2856 	u32 csi;
2857 
2858 	/* According to Realtek the value at config space address 0x070f
2859 	 * controls the L0s/L1 entrance latency. We try standard ECAM access
2860 	 * first and if it fails fall back to CSI.
2861 	 * bit 0..2: L0: 0 = 1us, 1 = 2us .. 6 = 7us, 7 = 7us (no typo)
2862 	 * bit 3..5: L1: 0 = 1us, 1 = 2us .. 6 = 64us, 7 = 64us
2863 	 */
2864 	if (pdev->cfg_size > 0x070f &&
2865 	    pci_write_config_byte(pdev, 0x070f, val) == PCIBIOS_SUCCESSFUL)
2866 		return;
2867 
2868 	netdev_notice_once(tp->dev,
2869 		"No native access to PCI extended config space, falling back to CSI\n");
2870 	csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff;
2871 	rtl_csi_write(tp, 0x070c, csi | val << 24);
2872 }
2873 
rtl_set_def_aspm_entry_latency(struct rtl8169_private * tp)2874 static void rtl_set_def_aspm_entry_latency(struct rtl8169_private *tp)
2875 {
2876 	/* L0 7us, L1 16us */
2877 	rtl_set_aspm_entry_latency(tp, 0x27);
2878 }
2879 
2880 struct ephy_info {
2881 	unsigned int offset;
2882 	u16 mask;
2883 	u16 bits;
2884 };
2885 
__rtl_ephy_init(struct rtl8169_private * tp,const struct ephy_info * e,int len)2886 static void __rtl_ephy_init(struct rtl8169_private *tp,
2887 			    const struct ephy_info *e, int len)
2888 {
2889 	u16 w;
2890 
2891 	while (len-- > 0) {
2892 		w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits;
2893 		rtl_ephy_write(tp, e->offset, w);
2894 		e++;
2895 	}
2896 }
2897 
2898 #define rtl_ephy_init(tp, a) __rtl_ephy_init(tp, a, ARRAY_SIZE(a))
2899 
rtl_disable_clock_request(struct rtl8169_private * tp)2900 static void rtl_disable_clock_request(struct rtl8169_private *tp)
2901 {
2902 	pcie_capability_clear_word(tp->pci_dev, PCI_EXP_LNKCTL,
2903 				   PCI_EXP_LNKCTL_CLKREQ_EN);
2904 }
2905 
rtl_enable_clock_request(struct rtl8169_private * tp)2906 static void rtl_enable_clock_request(struct rtl8169_private *tp)
2907 {
2908 	pcie_capability_set_word(tp->pci_dev, PCI_EXP_LNKCTL,
2909 				 PCI_EXP_LNKCTL_CLKREQ_EN);
2910 }
2911 
rtl_pcie_state_l2l3_disable(struct rtl8169_private * tp)2912 static void rtl_pcie_state_l2l3_disable(struct rtl8169_private *tp)
2913 {
2914 	/* work around an issue when PCI reset occurs during L2/L3 state */
2915 	RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Rdy_to_L23);
2916 }
2917 
rtl_enable_exit_l1(struct rtl8169_private * tp)2918 static void rtl_enable_exit_l1(struct rtl8169_private *tp)
2919 {
2920 	/* Bits control which events trigger ASPM L1 exit:
2921 	 * Bit 12: rxdv
2922 	 * Bit 11: ltr_msg
2923 	 * Bit 10: txdma_poll
2924 	 * Bit  9: xadm
2925 	 * Bit  8: pktavi
2926 	 * Bit  7: txpla
2927 	 */
2928 	switch (tp->mac_version) {
2929 	case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_36:
2930 		rtl_eri_set_bits(tp, 0xd4, 0x1f00);
2931 		break;
2932 	case RTL_GIGA_MAC_VER_37 ... RTL_GIGA_MAC_VER_38:
2933 		rtl_eri_set_bits(tp, 0xd4, 0x0c00);
2934 		break;
2935 	case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_71:
2936 		r8168_mac_ocp_modify(tp, 0xc0ac, 0, 0x1f80);
2937 		break;
2938 	default:
2939 		break;
2940 	}
2941 }
2942 
rtl_disable_exit_l1(struct rtl8169_private * tp)2943 static void rtl_disable_exit_l1(struct rtl8169_private *tp)
2944 {
2945 	switch (tp->mac_version) {
2946 	case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:
2947 		rtl_eri_clear_bits(tp, 0xd4, 0x1f00);
2948 		break;
2949 	case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_71:
2950 		r8168_mac_ocp_modify(tp, 0xc0ac, 0x1f80, 0);
2951 		break;
2952 	default:
2953 		break;
2954 	}
2955 }
2956 
rtl_hw_aspm_clkreq_enable(struct rtl8169_private * tp,bool enable)2957 static void rtl_hw_aspm_clkreq_enable(struct rtl8169_private *tp, bool enable)
2958 {
2959 	u8 val8;
2960 
2961 	if (tp->mac_version < RTL_GIGA_MAC_VER_32)
2962 		return;
2963 
2964 	/* Don't enable ASPM in the chip if OS can't control ASPM */
2965 	if (enable && tp->aspm_manageable) {
2966 		/* On these chip versions ASPM can even harm
2967 		 * bus communication of other PCI devices.
2968 		 */
2969 		if (tp->mac_version == RTL_GIGA_MAC_VER_42 ||
2970 		    tp->mac_version == RTL_GIGA_MAC_VER_43)
2971 			return;
2972 
2973 		rtl_mod_config5(tp, 0, ASPM_en);
2974 		switch (tp->mac_version) {
2975 		case RTL_GIGA_MAC_VER_70:
2976 		case RTL_GIGA_MAC_VER_71:
2977 			val8 = RTL_R8(tp, INT_CFG0_8125) | INT_CFG0_CLKREQEN;
2978 			RTL_W8(tp, INT_CFG0_8125, val8);
2979 			break;
2980 		default:
2981 			rtl_mod_config2(tp, 0, ClkReqEn);
2982 			break;
2983 		}
2984 
2985 		switch (tp->mac_version) {
2986 		case RTL_GIGA_MAC_VER_46 ... RTL_GIGA_MAC_VER_48:
2987 		case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_71:
2988 			/* reset ephy tx/rx disable timer */
2989 			r8168_mac_ocp_modify(tp, 0xe094, 0xff00, 0);
2990 			/* chip can trigger L1.2 */
2991 			r8168_mac_ocp_modify(tp, 0xe092, 0x00ff, BIT(2));
2992 			break;
2993 		default:
2994 			break;
2995 		}
2996 	} else {
2997 		switch (tp->mac_version) {
2998 		case RTL_GIGA_MAC_VER_46 ... RTL_GIGA_MAC_VER_48:
2999 		case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_71:
3000 			r8168_mac_ocp_modify(tp, 0xe092, 0x00ff, 0);
3001 			break;
3002 		default:
3003 			break;
3004 		}
3005 
3006 		switch (tp->mac_version) {
3007 		case RTL_GIGA_MAC_VER_70:
3008 		case RTL_GIGA_MAC_VER_71:
3009 			val8 = RTL_R8(tp, INT_CFG0_8125) & ~INT_CFG0_CLKREQEN;
3010 			RTL_W8(tp, INT_CFG0_8125, val8);
3011 			break;
3012 		default:
3013 			rtl_mod_config2(tp, ClkReqEn, 0);
3014 			break;
3015 		}
3016 		rtl_mod_config5(tp, ASPM_en, 0);
3017 	}
3018 }
3019 
rtl_set_fifo_size(struct rtl8169_private * tp,u16 rx_stat,u16 tx_stat,u16 rx_dyn,u16 tx_dyn)3020 static void rtl_set_fifo_size(struct rtl8169_private *tp, u16 rx_stat,
3021 			      u16 tx_stat, u16 rx_dyn, u16 tx_dyn)
3022 {
3023 	/* Usage of dynamic vs. static FIFO is controlled by bit
3024 	 * TXCFG_AUTO_FIFO. Exact meaning of FIFO values isn't known.
3025 	 */
3026 	rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, (rx_stat << 16) | rx_dyn);
3027 	rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, (tx_stat << 16) | tx_dyn);
3028 }
3029 
rtl8168g_set_pause_thresholds(struct rtl8169_private * tp,u8 low,u8 high)3030 static void rtl8168g_set_pause_thresholds(struct rtl8169_private *tp,
3031 					  u8 low, u8 high)
3032 {
3033 	/* FIFO thresholds for pause flow control */
3034 	rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, low);
3035 	rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, high);
3036 }
3037 
rtl_hw_start_8168b(struct rtl8169_private * tp)3038 static void rtl_hw_start_8168b(struct rtl8169_private *tp)
3039 {
3040 	RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
3041 }
3042 
__rtl_hw_start_8168cp(struct rtl8169_private * tp)3043 static void __rtl_hw_start_8168cp(struct rtl8169_private *tp)
3044 {
3045 	RTL_W8(tp, Config1, RTL_R8(tp, Config1) | Speed_down);
3046 
3047 	RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
3048 
3049 	rtl_disable_clock_request(tp);
3050 }
3051 
rtl_hw_start_8168cp_1(struct rtl8169_private * tp)3052 static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp)
3053 {
3054 	static const struct ephy_info e_info_8168cp[] = {
3055 		{ 0x01, 0,	0x0001 },
3056 		{ 0x02, 0x0800,	0x1000 },
3057 		{ 0x03, 0,	0x0042 },
3058 		{ 0x06, 0x0080,	0x0000 },
3059 		{ 0x07, 0,	0x2000 }
3060 	};
3061 
3062 	rtl_set_def_aspm_entry_latency(tp);
3063 
3064 	rtl_ephy_init(tp, e_info_8168cp);
3065 
3066 	__rtl_hw_start_8168cp(tp);
3067 }
3068 
rtl_hw_start_8168cp_2(struct rtl8169_private * tp)3069 static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp)
3070 {
3071 	rtl_set_def_aspm_entry_latency(tp);
3072 
3073 	RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
3074 }
3075 
rtl_hw_start_8168cp_3(struct rtl8169_private * tp)3076 static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp)
3077 {
3078 	rtl_set_def_aspm_entry_latency(tp);
3079 
3080 	RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
3081 
3082 	/* Magic. */
3083 	RTL_W8(tp, DBG_REG, 0x20);
3084 }
3085 
rtl_hw_start_8168c_1(struct rtl8169_private * tp)3086 static void rtl_hw_start_8168c_1(struct rtl8169_private *tp)
3087 {
3088 	static const struct ephy_info e_info_8168c_1[] = {
3089 		{ 0x02, 0x0800,	0x1000 },
3090 		{ 0x03, 0,	0x0002 },
3091 		{ 0x06, 0x0080,	0x0000 }
3092 	};
3093 
3094 	rtl_set_def_aspm_entry_latency(tp);
3095 
3096 	RTL_W8(tp, DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
3097 
3098 	rtl_ephy_init(tp, e_info_8168c_1);
3099 
3100 	__rtl_hw_start_8168cp(tp);
3101 }
3102 
rtl_hw_start_8168c_2(struct rtl8169_private * tp)3103 static void rtl_hw_start_8168c_2(struct rtl8169_private *tp)
3104 {
3105 	static const struct ephy_info e_info_8168c_2[] = {
3106 		{ 0x01, 0,	0x0001 },
3107 		{ 0x03, 0x0400,	0x0020 }
3108 	};
3109 
3110 	rtl_set_def_aspm_entry_latency(tp);
3111 
3112 	rtl_ephy_init(tp, e_info_8168c_2);
3113 
3114 	__rtl_hw_start_8168cp(tp);
3115 }
3116 
rtl_hw_start_8168c_4(struct rtl8169_private * tp)3117 static void rtl_hw_start_8168c_4(struct rtl8169_private *tp)
3118 {
3119 	rtl_set_def_aspm_entry_latency(tp);
3120 
3121 	__rtl_hw_start_8168cp(tp);
3122 }
3123 
rtl_hw_start_8168d(struct rtl8169_private * tp)3124 static void rtl_hw_start_8168d(struct rtl8169_private *tp)
3125 {
3126 	rtl_set_def_aspm_entry_latency(tp);
3127 
3128 	rtl_disable_clock_request(tp);
3129 }
3130 
rtl_hw_start_8168d_4(struct rtl8169_private * tp)3131 static void rtl_hw_start_8168d_4(struct rtl8169_private *tp)
3132 {
3133 	static const struct ephy_info e_info_8168d_4[] = {
3134 		{ 0x0b, 0x0000,	0x0048 },
3135 		{ 0x19, 0x0020,	0x0050 },
3136 		{ 0x0c, 0x0100,	0x0020 },
3137 		{ 0x10, 0x0004,	0x0000 },
3138 	};
3139 
3140 	rtl_set_def_aspm_entry_latency(tp);
3141 
3142 	rtl_ephy_init(tp, e_info_8168d_4);
3143 
3144 	rtl_enable_clock_request(tp);
3145 }
3146 
rtl_hw_start_8168e_1(struct rtl8169_private * tp)3147 static void rtl_hw_start_8168e_1(struct rtl8169_private *tp)
3148 {
3149 	static const struct ephy_info e_info_8168e_1[] = {
3150 		{ 0x00, 0x0200,	0x0100 },
3151 		{ 0x00, 0x0000,	0x0004 },
3152 		{ 0x06, 0x0002,	0x0001 },
3153 		{ 0x06, 0x0000,	0x0030 },
3154 		{ 0x07, 0x0000,	0x2000 },
3155 		{ 0x00, 0x0000,	0x0020 },
3156 		{ 0x03, 0x5800,	0x2000 },
3157 		{ 0x03, 0x0000,	0x0001 },
3158 		{ 0x01, 0x0800,	0x1000 },
3159 		{ 0x07, 0x0000,	0x4000 },
3160 		{ 0x1e, 0x0000,	0x2000 },
3161 		{ 0x19, 0xffff,	0xfe6c },
3162 		{ 0x0a, 0x0000,	0x0040 }
3163 	};
3164 
3165 	rtl_set_def_aspm_entry_latency(tp);
3166 
3167 	rtl_ephy_init(tp, e_info_8168e_1);
3168 
3169 	rtl_disable_clock_request(tp);
3170 
3171 	/* Reset tx FIFO pointer */
3172 	RTL_W32(tp, MISC, RTL_R32(tp, MISC) | TXPLA_RST);
3173 	RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~TXPLA_RST);
3174 
3175 	rtl_mod_config5(tp, Spi_en, 0);
3176 }
3177 
rtl_hw_start_8168e_2(struct rtl8169_private * tp)3178 static void rtl_hw_start_8168e_2(struct rtl8169_private *tp)
3179 {
3180 	static const struct ephy_info e_info_8168e_2[] = {
3181 		{ 0x09, 0x0000,	0x0080 },
3182 		{ 0x19, 0x0000,	0x0224 },
3183 		{ 0x00, 0x0000,	0x0004 },
3184 		{ 0x0c, 0x3df0,	0x0200 },
3185 	};
3186 
3187 	rtl_set_def_aspm_entry_latency(tp);
3188 
3189 	rtl_ephy_init(tp, e_info_8168e_2);
3190 
3191 	rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
3192 	rtl_eri_write(tp, 0xb8, ERIAR_MASK_1111, 0x0000);
3193 	rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06);
3194 	rtl_eri_set_bits(tp, 0x1d0, BIT(1));
3195 	rtl_reset_packet_filter(tp);
3196 	rtl_eri_set_bits(tp, 0x1b0, BIT(4));
3197 	rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050);
3198 	rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060);
3199 
3200 	rtl_disable_clock_request(tp);
3201 
3202 	RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
3203 
3204 	rtl8168_config_eee_mac(tp);
3205 
3206 	RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
3207 	RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
3208 	rtl_mod_config5(tp, Spi_en, 0);
3209 }
3210 
rtl_hw_start_8168f(struct rtl8169_private * tp)3211 static void rtl_hw_start_8168f(struct rtl8169_private *tp)
3212 {
3213 	rtl_set_def_aspm_entry_latency(tp);
3214 
3215 	rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
3216 	rtl_eri_write(tp, 0xb8, ERIAR_MASK_1111, 0x0000);
3217 	rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06);
3218 	rtl_reset_packet_filter(tp);
3219 	rtl_eri_set_bits(tp, 0x1b0, BIT(4));
3220 	rtl_eri_set_bits(tp, 0x1d0, BIT(4) | BIT(1));
3221 	rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050);
3222 	rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060);
3223 
3224 	rtl_disable_clock_request(tp);
3225 
3226 	RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
3227 	RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
3228 	RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
3229 	rtl_mod_config5(tp, Spi_en, 0);
3230 
3231 	rtl8168_config_eee_mac(tp);
3232 }
3233 
rtl_hw_start_8168f_1(struct rtl8169_private * tp)3234 static void rtl_hw_start_8168f_1(struct rtl8169_private *tp)
3235 {
3236 	static const struct ephy_info e_info_8168f_1[] = {
3237 		{ 0x06, 0x00c0,	0x0020 },
3238 		{ 0x08, 0x0001,	0x0002 },
3239 		{ 0x09, 0x0000,	0x0080 },
3240 		{ 0x19, 0x0000,	0x0224 },
3241 		{ 0x00, 0x0000,	0x0008 },
3242 		{ 0x0c, 0x3df0,	0x0200 },
3243 	};
3244 
3245 	rtl_hw_start_8168f(tp);
3246 
3247 	rtl_ephy_init(tp, e_info_8168f_1);
3248 }
3249 
rtl_hw_start_8411(struct rtl8169_private * tp)3250 static void rtl_hw_start_8411(struct rtl8169_private *tp)
3251 {
3252 	static const struct ephy_info e_info_8168f_1[] = {
3253 		{ 0x06, 0x00c0,	0x0020 },
3254 		{ 0x0f, 0xffff,	0x5200 },
3255 		{ 0x19, 0x0000,	0x0224 },
3256 		{ 0x00, 0x0000,	0x0008 },
3257 		{ 0x0c, 0x3df0,	0x0200 },
3258 	};
3259 
3260 	rtl_hw_start_8168f(tp);
3261 	rtl_pcie_state_l2l3_disable(tp);
3262 
3263 	rtl_ephy_init(tp, e_info_8168f_1);
3264 }
3265 
rtl_hw_start_8168g(struct rtl8169_private * tp)3266 static void rtl_hw_start_8168g(struct rtl8169_private *tp)
3267 {
3268 	rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
3269 	rtl8168g_set_pause_thresholds(tp, 0x38, 0x48);
3270 
3271 	rtl_set_def_aspm_entry_latency(tp);
3272 
3273 	rtl_reset_packet_filter(tp);
3274 	rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f);
3275 
3276 	rtl_disable_rxdvgate(tp);
3277 
3278 	rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
3279 	rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
3280 
3281 	rtl8168_config_eee_mac(tp);
3282 
3283 	rtl_w0w1_eri(tp, 0x2fc, 0x01, 0x06);
3284 	rtl_eri_clear_bits(tp, 0x1b0, BIT(12));
3285 
3286 	rtl_pcie_state_l2l3_disable(tp);
3287 }
3288 
rtl_hw_start_8168g_1(struct rtl8169_private * tp)3289 static void rtl_hw_start_8168g_1(struct rtl8169_private *tp)
3290 {
3291 	static const struct ephy_info e_info_8168g_1[] = {
3292 		{ 0x00, 0x0008,	0x0000 },
3293 		{ 0x0c, 0x3ff0,	0x0820 },
3294 		{ 0x1e, 0x0000,	0x0001 },
3295 		{ 0x19, 0x8000,	0x0000 }
3296 	};
3297 
3298 	rtl_hw_start_8168g(tp);
3299 	rtl_ephy_init(tp, e_info_8168g_1);
3300 }
3301 
rtl_hw_start_8168g_2(struct rtl8169_private * tp)3302 static void rtl_hw_start_8168g_2(struct rtl8169_private *tp)
3303 {
3304 	static const struct ephy_info e_info_8168g_2[] = {
3305 		{ 0x00, 0x0008,	0x0000 },
3306 		{ 0x0c, 0x3ff0,	0x0820 },
3307 		{ 0x19, 0xffff,	0x7c00 },
3308 		{ 0x1e, 0xffff,	0x20eb },
3309 		{ 0x0d, 0xffff,	0x1666 },
3310 		{ 0x00, 0xffff,	0x10a3 },
3311 		{ 0x06, 0xffff,	0xf050 },
3312 		{ 0x04, 0x0000,	0x0010 },
3313 		{ 0x1d, 0x4000,	0x0000 },
3314 	};
3315 
3316 	rtl_hw_start_8168g(tp);
3317 	rtl_ephy_init(tp, e_info_8168g_2);
3318 }
3319 
rtl8411b_fix_phy_down(struct rtl8169_private * tp)3320 static void rtl8411b_fix_phy_down(struct rtl8169_private *tp)
3321 {
3322 	static const u16 fix_data[] = {
3323 /* 0xf800 */ 0xe008, 0xe00a, 0xe00c, 0xe00e, 0xe027, 0xe04f, 0xe05e, 0xe065,
3324 /* 0xf810 */ 0xc602, 0xbe00, 0x0000, 0xc502, 0xbd00, 0x074c, 0xc302, 0xbb00,
3325 /* 0xf820 */ 0x080a, 0x6420, 0x48c2, 0x8c20, 0xc516, 0x64a4, 0x49c0, 0xf009,
3326 /* 0xf830 */ 0x74a2, 0x8ca5, 0x74a0, 0xc50e, 0x9ca2, 0x1c11, 0x9ca0, 0xe006,
3327 /* 0xf840 */ 0x74f8, 0x48c4, 0x8cf8, 0xc404, 0xbc00, 0xc403, 0xbc00, 0x0bf2,
3328 /* 0xf850 */ 0x0c0a, 0xe434, 0xd3c0, 0x49d9, 0xf01f, 0xc526, 0x64a5, 0x1400,
3329 /* 0xf860 */ 0xf007, 0x0c01, 0x8ca5, 0x1c15, 0xc51b, 0x9ca0, 0xe013, 0xc519,
3330 /* 0xf870 */ 0x74a0, 0x48c4, 0x8ca0, 0xc516, 0x74a4, 0x48c8, 0x48ca, 0x9ca4,
3331 /* 0xf880 */ 0xc512, 0x1b00, 0x9ba0, 0x1b1c, 0x483f, 0x9ba2, 0x1b04, 0xc508,
3332 /* 0xf890 */ 0x9ba0, 0xc505, 0xbd00, 0xc502, 0xbd00, 0x0300, 0x051e, 0xe434,
3333 /* 0xf8a0 */ 0xe018, 0xe092, 0xde20, 0xd3c0, 0xc50f, 0x76a4, 0x49e3, 0xf007,
3334 /* 0xf8b0 */ 0x49c0, 0xf103, 0xc607, 0xbe00, 0xc606, 0xbe00, 0xc602, 0xbe00,
3335 /* 0xf8c0 */ 0x0c4c, 0x0c28, 0x0c2c, 0xdc00, 0xc707, 0x1d00, 0x8de2, 0x48c1,
3336 /* 0xf8d0 */ 0xc502, 0xbd00, 0x00aa, 0xe0c0, 0xc502, 0xbd00, 0x0132
3337 	};
3338 	unsigned long flags;
3339 	int i;
3340 
3341 	raw_spin_lock_irqsave(&tp->mac_ocp_lock, flags);
3342 	for (i = 0; i < ARRAY_SIZE(fix_data); i++)
3343 		__r8168_mac_ocp_write(tp, 0xf800 + 2 * i, fix_data[i]);
3344 	raw_spin_unlock_irqrestore(&tp->mac_ocp_lock, flags);
3345 }
3346 
rtl_hw_start_8411_2(struct rtl8169_private * tp)3347 static void rtl_hw_start_8411_2(struct rtl8169_private *tp)
3348 {
3349 	static const struct ephy_info e_info_8411_2[] = {
3350 		{ 0x00, 0x0008,	0x0000 },
3351 		{ 0x0c, 0x37d0,	0x0820 },
3352 		{ 0x1e, 0x0000,	0x0001 },
3353 		{ 0x19, 0x8021,	0x0000 },
3354 		{ 0x1e, 0x0000,	0x2000 },
3355 		{ 0x0d, 0x0100,	0x0200 },
3356 		{ 0x00, 0x0000,	0x0080 },
3357 		{ 0x06, 0x0000,	0x0010 },
3358 		{ 0x04, 0x0000,	0x0010 },
3359 		{ 0x1d, 0x0000,	0x4000 },
3360 	};
3361 
3362 	rtl_hw_start_8168g(tp);
3363 
3364 	rtl_ephy_init(tp, e_info_8411_2);
3365 
3366 	/* The following Realtek-provided magic fixes an issue with the RX unit
3367 	 * getting confused after the PHY having been powered-down.
3368 	 */
3369 	r8168_mac_ocp_write(tp, 0xFC28, 0x0000);
3370 	r8168_mac_ocp_write(tp, 0xFC2A, 0x0000);
3371 	r8168_mac_ocp_write(tp, 0xFC2C, 0x0000);
3372 	r8168_mac_ocp_write(tp, 0xFC2E, 0x0000);
3373 	r8168_mac_ocp_write(tp, 0xFC30, 0x0000);
3374 	r8168_mac_ocp_write(tp, 0xFC32, 0x0000);
3375 	r8168_mac_ocp_write(tp, 0xFC34, 0x0000);
3376 	r8168_mac_ocp_write(tp, 0xFC36, 0x0000);
3377 	mdelay(3);
3378 	r8168_mac_ocp_write(tp, 0xFC26, 0x0000);
3379 
3380 	rtl8411b_fix_phy_down(tp);
3381 
3382 	r8168_mac_ocp_write(tp, 0xFC26, 0x8000);
3383 
3384 	r8168_mac_ocp_write(tp, 0xFC2A, 0x0743);
3385 	r8168_mac_ocp_write(tp, 0xFC2C, 0x0801);
3386 	r8168_mac_ocp_write(tp, 0xFC2E, 0x0BE9);
3387 	r8168_mac_ocp_write(tp, 0xFC30, 0x02FD);
3388 	r8168_mac_ocp_write(tp, 0xFC32, 0x0C25);
3389 	r8168_mac_ocp_write(tp, 0xFC34, 0x00A9);
3390 	r8168_mac_ocp_write(tp, 0xFC36, 0x012D);
3391 }
3392 
rtl_hw_start_8168h_1(struct rtl8169_private * tp)3393 static void rtl_hw_start_8168h_1(struct rtl8169_private *tp)
3394 {
3395 	static const struct ephy_info e_info_8168h_1[] = {
3396 		{ 0x1e, 0x0800,	0x0001 },
3397 		{ 0x1d, 0x0000,	0x0800 },
3398 		{ 0x05, 0xffff,	0x2089 },
3399 		{ 0x06, 0xffff,	0x5881 },
3400 		{ 0x04, 0xffff,	0x854a },
3401 		{ 0x01, 0xffff,	0x068b }
3402 	};
3403 	int rg_saw_cnt;
3404 
3405 	rtl_ephy_init(tp, e_info_8168h_1);
3406 
3407 	rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
3408 	rtl8168g_set_pause_thresholds(tp, 0x38, 0x48);
3409 
3410 	rtl_set_def_aspm_entry_latency(tp);
3411 
3412 	rtl_reset_packet_filter(tp);
3413 
3414 	rtl_eri_set_bits(tp, 0xdc, 0x001c);
3415 
3416 	rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87);
3417 
3418 	rtl_disable_rxdvgate(tp);
3419 
3420 	rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
3421 	rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
3422 
3423 	rtl8168_config_eee_mac(tp);
3424 
3425 	RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
3426 	RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
3427 
3428 	RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
3429 
3430 	rtl_eri_clear_bits(tp, 0x1b0, BIT(12));
3431 
3432 	rtl_pcie_state_l2l3_disable(tp);
3433 
3434 	rg_saw_cnt = phy_read_paged(tp->phydev, 0x0c42, 0x13) & 0x3fff;
3435 	if (rg_saw_cnt > 0) {
3436 		u16 sw_cnt_1ms_ini;
3437 
3438 		sw_cnt_1ms_ini = 16000000/rg_saw_cnt;
3439 		sw_cnt_1ms_ini &= 0x0fff;
3440 		r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini);
3441 	}
3442 
3443 	r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070);
3444 	r8168_mac_ocp_modify(tp, 0xe052, 0x6000, 0x8008);
3445 	r8168_mac_ocp_modify(tp, 0xe0d6, 0x01ff, 0x017f);
3446 	r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f);
3447 
3448 	r8168_mac_ocp_write(tp, 0xe63e, 0x0001);
3449 	r8168_mac_ocp_write(tp, 0xe63e, 0x0000);
3450 	r8168_mac_ocp_write(tp, 0xc094, 0x0000);
3451 	r8168_mac_ocp_write(tp, 0xc09e, 0x0000);
3452 }
3453 
rtl_hw_start_8168ep(struct rtl8169_private * tp)3454 static void rtl_hw_start_8168ep(struct rtl8169_private *tp)
3455 {
3456 	rtl8168ep_stop_cmac(tp);
3457 
3458 	rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
3459 	rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f);
3460 
3461 	rtl_set_def_aspm_entry_latency(tp);
3462 
3463 	rtl_reset_packet_filter(tp);
3464 
3465 	rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87);
3466 
3467 	rtl_disable_rxdvgate(tp);
3468 
3469 	rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
3470 	rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
3471 
3472 	rtl8168_config_eee_mac(tp);
3473 
3474 	rtl_w0w1_eri(tp, 0x2fc, 0x01, 0x06);
3475 
3476 	RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
3477 
3478 	rtl_pcie_state_l2l3_disable(tp);
3479 }
3480 
rtl_hw_start_8168ep_3(struct rtl8169_private * tp)3481 static void rtl_hw_start_8168ep_3(struct rtl8169_private *tp)
3482 {
3483 	static const struct ephy_info e_info_8168ep_3[] = {
3484 		{ 0x00, 0x0000,	0x0080 },
3485 		{ 0x0d, 0x0100,	0x0200 },
3486 		{ 0x19, 0x8021,	0x0000 },
3487 		{ 0x1e, 0x0000,	0x2000 },
3488 	};
3489 
3490 	rtl_ephy_init(tp, e_info_8168ep_3);
3491 
3492 	rtl_hw_start_8168ep(tp);
3493 
3494 	RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
3495 	RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
3496 
3497 	r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x0271);
3498 	r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000);
3499 	r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080);
3500 }
3501 
rtl_hw_start_8117(struct rtl8169_private * tp)3502 static void rtl_hw_start_8117(struct rtl8169_private *tp)
3503 {
3504 	static const struct ephy_info e_info_8117[] = {
3505 		{ 0x19, 0x0040,	0x1100 },
3506 		{ 0x59, 0x0040,	0x1100 },
3507 	};
3508 	int rg_saw_cnt;
3509 
3510 	rtl8168ep_stop_cmac(tp);
3511 	rtl_ephy_init(tp, e_info_8117);
3512 
3513 	rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
3514 	rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f);
3515 
3516 	rtl_set_def_aspm_entry_latency(tp);
3517 
3518 	rtl_reset_packet_filter(tp);
3519 
3520 	rtl_eri_set_bits(tp, 0xd4, 0x0010);
3521 
3522 	rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87);
3523 
3524 	rtl_disable_rxdvgate(tp);
3525 
3526 	rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
3527 	rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
3528 
3529 	rtl8168_config_eee_mac(tp);
3530 
3531 	RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
3532 	RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
3533 
3534 	RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
3535 
3536 	rtl_eri_clear_bits(tp, 0x1b0, BIT(12));
3537 
3538 	rtl_pcie_state_l2l3_disable(tp);
3539 
3540 	rg_saw_cnt = phy_read_paged(tp->phydev, 0x0c42, 0x13) & 0x3fff;
3541 	if (rg_saw_cnt > 0) {
3542 		u16 sw_cnt_1ms_ini;
3543 
3544 		sw_cnt_1ms_ini = (16000000 / rg_saw_cnt) & 0x0fff;
3545 		r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini);
3546 	}
3547 
3548 	r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070);
3549 	r8168_mac_ocp_write(tp, 0xea80, 0x0003);
3550 	r8168_mac_ocp_modify(tp, 0xe052, 0x0000, 0x0009);
3551 	r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f);
3552 
3553 	r8168_mac_ocp_write(tp, 0xe63e, 0x0001);
3554 	r8168_mac_ocp_write(tp, 0xe63e, 0x0000);
3555 	r8168_mac_ocp_write(tp, 0xc094, 0x0000);
3556 	r8168_mac_ocp_write(tp, 0xc09e, 0x0000);
3557 
3558 	/* firmware is for MAC only */
3559 	r8169_apply_firmware(tp);
3560 }
3561 
rtl_hw_start_8102e_1(struct rtl8169_private * tp)3562 static void rtl_hw_start_8102e_1(struct rtl8169_private *tp)
3563 {
3564 	static const struct ephy_info e_info_8102e_1[] = {
3565 		{ 0x01,	0, 0x6e65 },
3566 		{ 0x02,	0, 0x091f },
3567 		{ 0x03,	0, 0xc2f9 },
3568 		{ 0x06,	0, 0xafb5 },
3569 		{ 0x07,	0, 0x0e00 },
3570 		{ 0x19,	0, 0xec80 },
3571 		{ 0x01,	0, 0x2e65 },
3572 		{ 0x01,	0, 0x6e65 }
3573 	};
3574 	u8 cfg1;
3575 
3576 	rtl_set_def_aspm_entry_latency(tp);
3577 
3578 	RTL_W8(tp, DBG_REG, FIX_NAK_1);
3579 
3580 	RTL_W8(tp, Config1,
3581 	       LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
3582 	RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
3583 
3584 	cfg1 = RTL_R8(tp, Config1);
3585 	if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
3586 		RTL_W8(tp, Config1, cfg1 & ~LEDS0);
3587 
3588 	rtl_ephy_init(tp, e_info_8102e_1);
3589 }
3590 
rtl_hw_start_8102e_2(struct rtl8169_private * tp)3591 static void rtl_hw_start_8102e_2(struct rtl8169_private *tp)
3592 {
3593 	rtl_set_def_aspm_entry_latency(tp);
3594 
3595 	RTL_W8(tp, Config1, MEMMAP | IOMAP | VPD | PMEnable);
3596 	RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
3597 }
3598 
rtl_hw_start_8102e_3(struct rtl8169_private * tp)3599 static void rtl_hw_start_8102e_3(struct rtl8169_private *tp)
3600 {
3601 	rtl_hw_start_8102e_2(tp);
3602 
3603 	rtl_ephy_write(tp, 0x03, 0xc2f9);
3604 }
3605 
rtl_hw_start_8401(struct rtl8169_private * tp)3606 static void rtl_hw_start_8401(struct rtl8169_private *tp)
3607 {
3608 	static const struct ephy_info e_info_8401[] = {
3609 		{ 0x01,	0xffff, 0x6fe5 },
3610 		{ 0x03,	0xffff, 0x0599 },
3611 		{ 0x06,	0xffff, 0xaf25 },
3612 		{ 0x07,	0xffff, 0x8e68 },
3613 	};
3614 
3615 	rtl_ephy_init(tp, e_info_8401);
3616 	RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
3617 }
3618 
rtl_hw_start_8105e_1(struct rtl8169_private * tp)3619 static void rtl_hw_start_8105e_1(struct rtl8169_private *tp)
3620 {
3621 	static const struct ephy_info e_info_8105e_1[] = {
3622 		{ 0x07,	0, 0x4000 },
3623 		{ 0x19,	0, 0x0200 },
3624 		{ 0x19,	0, 0x0020 },
3625 		{ 0x1e,	0, 0x2000 },
3626 		{ 0x03,	0, 0x0001 },
3627 		{ 0x19,	0, 0x0100 },
3628 		{ 0x19,	0, 0x0004 },
3629 		{ 0x0a,	0, 0x0020 }
3630 	};
3631 
3632 	/* Force LAN exit from ASPM if Rx/Tx are not idle */
3633 	RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
3634 
3635 	/* Disable Early Tally Counter */
3636 	RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) & ~0x010000);
3637 
3638 	RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
3639 	RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
3640 
3641 	rtl_ephy_init(tp, e_info_8105e_1);
3642 
3643 	rtl_pcie_state_l2l3_disable(tp);
3644 }
3645 
rtl_hw_start_8105e_2(struct rtl8169_private * tp)3646 static void rtl_hw_start_8105e_2(struct rtl8169_private *tp)
3647 {
3648 	rtl_hw_start_8105e_1(tp);
3649 	rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000);
3650 }
3651 
rtl_hw_start_8402(struct rtl8169_private * tp)3652 static void rtl_hw_start_8402(struct rtl8169_private *tp)
3653 {
3654 	static const struct ephy_info e_info_8402[] = {
3655 		{ 0x19,	0xffff, 0xff64 },
3656 		{ 0x1e,	0, 0x4000 }
3657 	};
3658 
3659 	rtl_set_def_aspm_entry_latency(tp);
3660 
3661 	/* Force LAN exit from ASPM if Rx/Tx are not idle */
3662 	RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
3663 
3664 	RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
3665 
3666 	rtl_ephy_init(tp, e_info_8402);
3667 
3668 	rtl_set_fifo_size(tp, 0x00, 0x00, 0x02, 0x06);
3669 	rtl_reset_packet_filter(tp);
3670 	rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
3671 	rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
3672 	rtl_w0w1_eri(tp, 0x0d4, 0x0e00, 0xff00);
3673 
3674 	/* disable EEE */
3675 	rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000);
3676 
3677 	rtl_pcie_state_l2l3_disable(tp);
3678 }
3679 
rtl_hw_start_8106(struct rtl8169_private * tp)3680 static void rtl_hw_start_8106(struct rtl8169_private *tp)
3681 {
3682 	/* Force LAN exit from ASPM if Rx/Tx are not idle */
3683 	RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
3684 
3685 	RTL_W32(tp, MISC, (RTL_R32(tp, MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN);
3686 	RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
3687 	RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
3688 
3689 	/* L0 7us, L1 32us - needed to avoid issues with link-up detection */
3690 	rtl_set_aspm_entry_latency(tp, 0x2f);
3691 
3692 	rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000);
3693 
3694 	/* disable EEE */
3695 	rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000);
3696 
3697 	rtl_pcie_state_l2l3_disable(tp);
3698 }
3699 
DECLARE_RTL_COND(rtl_mac_ocp_e00e_cond)3700 DECLARE_RTL_COND(rtl_mac_ocp_e00e_cond)
3701 {
3702 	return r8168_mac_ocp_read(tp, 0xe00e) & BIT(13);
3703 }
3704 
rtl_hw_start_8125_common(struct rtl8169_private * tp)3705 static void rtl_hw_start_8125_common(struct rtl8169_private *tp)
3706 {
3707 	rtl_pcie_state_l2l3_disable(tp);
3708 
3709 	RTL_W16(tp, 0x382, 0x221b);
3710 	RTL_W32(tp, RSS_CTRL_8125, 0);
3711 	RTL_W16(tp, Q_NUM_CTRL_8125, 0);
3712 
3713 	/* disable UPS */
3714 	r8168_mac_ocp_modify(tp, 0xd40a, 0x0010, 0x0000);
3715 
3716 	RTL_W8(tp, Config1, RTL_R8(tp, Config1) & ~0x10);
3717 
3718 	r8168_mac_ocp_write(tp, 0xc140, 0xffff);
3719 	r8168_mac_ocp_write(tp, 0xc142, 0xffff);
3720 
3721 	r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x03a9);
3722 	r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000);
3723 	r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080);
3724 
3725 	/* disable new tx descriptor format */
3726 	r8168_mac_ocp_modify(tp, 0xeb58, 0x0001, 0x0000);
3727 
3728 	if (tp->mac_version == RTL_GIGA_MAC_VER_70 ||
3729 	    tp->mac_version == RTL_GIGA_MAC_VER_71)
3730 		RTL_W8(tp, 0xD8, RTL_R8(tp, 0xD8) & ~0x02);
3731 
3732 	if (tp->mac_version == RTL_GIGA_MAC_VER_70 ||
3733 	    tp->mac_version == RTL_GIGA_MAC_VER_71)
3734 		r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0400);
3735 	else if (tp->mac_version == RTL_GIGA_MAC_VER_63)
3736 		r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0200);
3737 	else
3738 		r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0300);
3739 
3740 	if (tp->mac_version == RTL_GIGA_MAC_VER_63)
3741 		r8168_mac_ocp_modify(tp, 0xe63e, 0x0c30, 0x0000);
3742 	else
3743 		r8168_mac_ocp_modify(tp, 0xe63e, 0x0c30, 0x0020);
3744 
3745 	r8168_mac_ocp_modify(tp, 0xc0b4, 0x0000, 0x000c);
3746 	r8168_mac_ocp_modify(tp, 0xeb6a, 0x00ff, 0x0033);
3747 	r8168_mac_ocp_modify(tp, 0xeb50, 0x03e0, 0x0040);
3748 	r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0030);
3749 	r8168_mac_ocp_modify(tp, 0xe040, 0x1000, 0x0000);
3750 	r8168_mac_ocp_modify(tp, 0xea1c, 0x0003, 0x0001);
3751 	if (tp->mac_version == RTL_GIGA_MAC_VER_70 ||
3752 	    tp->mac_version == RTL_GIGA_MAC_VER_71)
3753 		r8168_mac_ocp_modify(tp, 0xea1c, 0x0300, 0x0000);
3754 	else
3755 		r8168_mac_ocp_modify(tp, 0xea1c, 0x0004, 0x0000);
3756 	r8168_mac_ocp_modify(tp, 0xe0c0, 0x4f0f, 0x4403);
3757 	r8168_mac_ocp_modify(tp, 0xe052, 0x0080, 0x0068);
3758 	r8168_mac_ocp_modify(tp, 0xd430, 0x0fff, 0x047f);
3759 
3760 	r8168_mac_ocp_modify(tp, 0xea1c, 0x0004, 0x0000);
3761 	r8168_mac_ocp_modify(tp, 0xeb54, 0x0000, 0x0001);
3762 	udelay(1);
3763 	r8168_mac_ocp_modify(tp, 0xeb54, 0x0001, 0x0000);
3764 	RTL_W16(tp, 0x1880, RTL_R16(tp, 0x1880) & ~0x0030);
3765 
3766 	r8168_mac_ocp_write(tp, 0xe098, 0xc302);
3767 
3768 	rtl_loop_wait_low(tp, &rtl_mac_ocp_e00e_cond, 1000, 10);
3769 
3770 	if (tp->mac_version == RTL_GIGA_MAC_VER_61)
3771 		rtl8125a_config_eee_mac(tp);
3772 	else
3773 		rtl8125b_config_eee_mac(tp);
3774 
3775 	rtl_disable_rxdvgate(tp);
3776 }
3777 
rtl_hw_start_8125a_2(struct rtl8169_private * tp)3778 static void rtl_hw_start_8125a_2(struct rtl8169_private *tp)
3779 {
3780 	static const struct ephy_info e_info_8125a_2[] = {
3781 		{ 0x04, 0xffff, 0xd000 },
3782 		{ 0x0a, 0xffff, 0x8653 },
3783 		{ 0x23, 0xffff, 0xab66 },
3784 		{ 0x20, 0xffff, 0x9455 },
3785 		{ 0x21, 0xffff, 0x99ff },
3786 		{ 0x29, 0xffff, 0xfe04 },
3787 
3788 		{ 0x44, 0xffff, 0xd000 },
3789 		{ 0x4a, 0xffff, 0x8653 },
3790 		{ 0x63, 0xffff, 0xab66 },
3791 		{ 0x60, 0xffff, 0x9455 },
3792 		{ 0x61, 0xffff, 0x99ff },
3793 		{ 0x69, 0xffff, 0xfe04 },
3794 	};
3795 
3796 	rtl_set_def_aspm_entry_latency(tp);
3797 	rtl_ephy_init(tp, e_info_8125a_2);
3798 	rtl_hw_start_8125_common(tp);
3799 }
3800 
rtl_hw_start_8125b(struct rtl8169_private * tp)3801 static void rtl_hw_start_8125b(struct rtl8169_private *tp)
3802 {
3803 	static const struct ephy_info e_info_8125b[] = {
3804 		{ 0x0b, 0xffff, 0xa908 },
3805 		{ 0x1e, 0xffff, 0x20eb },
3806 		{ 0x4b, 0xffff, 0xa908 },
3807 		{ 0x5e, 0xffff, 0x20eb },
3808 		{ 0x22, 0x0030, 0x0020 },
3809 		{ 0x62, 0x0030, 0x0020 },
3810 	};
3811 
3812 	rtl_set_def_aspm_entry_latency(tp);
3813 	rtl_ephy_init(tp, e_info_8125b);
3814 	rtl_hw_start_8125_common(tp);
3815 }
3816 
rtl_hw_start_8125d(struct rtl8169_private * tp)3817 static void rtl_hw_start_8125d(struct rtl8169_private *tp)
3818 {
3819 	rtl_set_def_aspm_entry_latency(tp);
3820 	rtl_hw_start_8125_common(tp);
3821 }
3822 
rtl_hw_start_8126a(struct rtl8169_private * tp)3823 static void rtl_hw_start_8126a(struct rtl8169_private *tp)
3824 {
3825 	rtl_set_def_aspm_entry_latency(tp);
3826 	rtl_hw_start_8125_common(tp);
3827 }
3828 
rtl_hw_config(struct rtl8169_private * tp)3829 static void rtl_hw_config(struct rtl8169_private *tp)
3830 {
3831 	static const rtl_generic_fct hw_configs[] = {
3832 		[RTL_GIGA_MAC_VER_07] = rtl_hw_start_8102e_1,
3833 		[RTL_GIGA_MAC_VER_08] = rtl_hw_start_8102e_3,
3834 		[RTL_GIGA_MAC_VER_09] = rtl_hw_start_8102e_2,
3835 		[RTL_GIGA_MAC_VER_10] = NULL,
3836 		[RTL_GIGA_MAC_VER_14] = rtl_hw_start_8401,
3837 		[RTL_GIGA_MAC_VER_17] = rtl_hw_start_8168b,
3838 		[RTL_GIGA_MAC_VER_18] = rtl_hw_start_8168cp_1,
3839 		[RTL_GIGA_MAC_VER_19] = rtl_hw_start_8168c_1,
3840 		[RTL_GIGA_MAC_VER_20] = rtl_hw_start_8168c_2,
3841 		[RTL_GIGA_MAC_VER_21] = rtl_hw_start_8168c_2,
3842 		[RTL_GIGA_MAC_VER_22] = rtl_hw_start_8168c_4,
3843 		[RTL_GIGA_MAC_VER_23] = rtl_hw_start_8168cp_2,
3844 		[RTL_GIGA_MAC_VER_24] = rtl_hw_start_8168cp_3,
3845 		[RTL_GIGA_MAC_VER_25] = rtl_hw_start_8168d,
3846 		[RTL_GIGA_MAC_VER_26] = rtl_hw_start_8168d,
3847 		[RTL_GIGA_MAC_VER_28] = rtl_hw_start_8168d_4,
3848 		[RTL_GIGA_MAC_VER_29] = rtl_hw_start_8105e_1,
3849 		[RTL_GIGA_MAC_VER_30] = rtl_hw_start_8105e_2,
3850 		[RTL_GIGA_MAC_VER_31] = rtl_hw_start_8168d,
3851 		[RTL_GIGA_MAC_VER_32] = rtl_hw_start_8168e_1,
3852 		[RTL_GIGA_MAC_VER_33] = rtl_hw_start_8168e_1,
3853 		[RTL_GIGA_MAC_VER_34] = rtl_hw_start_8168e_2,
3854 		[RTL_GIGA_MAC_VER_35] = rtl_hw_start_8168f_1,
3855 		[RTL_GIGA_MAC_VER_36] = rtl_hw_start_8168f_1,
3856 		[RTL_GIGA_MAC_VER_37] = rtl_hw_start_8402,
3857 		[RTL_GIGA_MAC_VER_38] = rtl_hw_start_8411,
3858 		[RTL_GIGA_MAC_VER_39] = rtl_hw_start_8106,
3859 		[RTL_GIGA_MAC_VER_40] = rtl_hw_start_8168g_1,
3860 		[RTL_GIGA_MAC_VER_42] = rtl_hw_start_8168g_2,
3861 		[RTL_GIGA_MAC_VER_43] = rtl_hw_start_8168g_2,
3862 		[RTL_GIGA_MAC_VER_44] = rtl_hw_start_8411_2,
3863 		[RTL_GIGA_MAC_VER_46] = rtl_hw_start_8168h_1,
3864 		[RTL_GIGA_MAC_VER_48] = rtl_hw_start_8168h_1,
3865 		[RTL_GIGA_MAC_VER_51] = rtl_hw_start_8168ep_3,
3866 		[RTL_GIGA_MAC_VER_52] = rtl_hw_start_8117,
3867 		[RTL_GIGA_MAC_VER_53] = rtl_hw_start_8117,
3868 		[RTL_GIGA_MAC_VER_61] = rtl_hw_start_8125a_2,
3869 		[RTL_GIGA_MAC_VER_63] = rtl_hw_start_8125b,
3870 		[RTL_GIGA_MAC_VER_64] = rtl_hw_start_8125d,
3871 		[RTL_GIGA_MAC_VER_65] = rtl_hw_start_8125d,
3872 		[RTL_GIGA_MAC_VER_66] = rtl_hw_start_8125d,
3873 		[RTL_GIGA_MAC_VER_70] = rtl_hw_start_8126a,
3874 		[RTL_GIGA_MAC_VER_71] = rtl_hw_start_8126a,
3875 	};
3876 
3877 	if (hw_configs[tp->mac_version])
3878 		hw_configs[tp->mac_version](tp);
3879 }
3880 
rtl_hw_start_8125(struct rtl8169_private * tp)3881 static void rtl_hw_start_8125(struct rtl8169_private *tp)
3882 {
3883 	int i;
3884 
3885 	RTL_W8(tp, INT_CFG0_8125, 0x00);
3886 
3887 	/* disable interrupt coalescing */
3888 	switch (tp->mac_version) {
3889 	case RTL_GIGA_MAC_VER_61:
3890 	case RTL_GIGA_MAC_VER_64:
3891 	case RTL_GIGA_MAC_VER_65:
3892 	case RTL_GIGA_MAC_VER_66:
3893 		for (i = 0xa00; i < 0xb00; i += 4)
3894 			RTL_W32(tp, i, 0);
3895 		break;
3896 	case RTL_GIGA_MAC_VER_63:
3897 	case RTL_GIGA_MAC_VER_70:
3898 	case RTL_GIGA_MAC_VER_71:
3899 		for (i = 0xa00; i < 0xa80; i += 4)
3900 			RTL_W32(tp, i, 0);
3901 		RTL_W16(tp, INT_CFG1_8125, 0x0000);
3902 		break;
3903 	default:
3904 		break;
3905 	}
3906 
3907 	/* enable extended tally counter */
3908 	r8168_mac_ocp_modify(tp, 0xea84, 0, BIT(1) | BIT(0));
3909 
3910 	rtl_hw_config(tp);
3911 }
3912 
rtl_hw_start_8168(struct rtl8169_private * tp)3913 static void rtl_hw_start_8168(struct rtl8169_private *tp)
3914 {
3915 	if (rtl_is_8168evl_up(tp))
3916 		RTL_W8(tp, MaxTxPacketSize, EarlySize);
3917 	else
3918 		RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
3919 
3920 	rtl_hw_config(tp);
3921 
3922 	/* disable interrupt coalescing */
3923 	RTL_W16(tp, IntrMitigate, 0x0000);
3924 }
3925 
rtl_hw_start_8169(struct rtl8169_private * tp)3926 static void rtl_hw_start_8169(struct rtl8169_private *tp)
3927 {
3928 	RTL_W8(tp, EarlyTxThres, NoEarlyTx);
3929 
3930 	tp->cp_cmd |= PCIMulRW;
3931 
3932 	if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
3933 	    tp->mac_version == RTL_GIGA_MAC_VER_03)
3934 		tp->cp_cmd |= EnAnaPLL;
3935 
3936 	RTL_W16(tp, CPlusCmd, tp->cp_cmd);
3937 
3938 	rtl8169_set_magic_reg(tp);
3939 
3940 	/* disable interrupt coalescing */
3941 	RTL_W16(tp, IntrMitigate, 0x0000);
3942 }
3943 
rtl_hw_start(struct rtl8169_private * tp)3944 static void rtl_hw_start(struct  rtl8169_private *tp)
3945 {
3946 	rtl_unlock_config_regs(tp);
3947 	/* disable aspm and clock request before ephy access */
3948 	rtl_hw_aspm_clkreq_enable(tp, false);
3949 	RTL_W16(tp, CPlusCmd, tp->cp_cmd);
3950 
3951 	rtl_set_eee_txidle_timer(tp);
3952 
3953 	if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
3954 		rtl_hw_start_8169(tp);
3955 	else if (rtl_is_8125(tp))
3956 		rtl_hw_start_8125(tp);
3957 	else
3958 		rtl_hw_start_8168(tp);
3959 
3960 	rtl_enable_exit_l1(tp);
3961 	rtl_hw_aspm_clkreq_enable(tp, true);
3962 	rtl_set_rx_max_size(tp);
3963 	rtl_set_rx_tx_desc_registers(tp);
3964 	rtl_lock_config_regs(tp);
3965 
3966 	rtl_jumbo_config(tp);
3967 
3968 	/* Initially a 10 us delay. Turned it into a PCI commit. - FR */
3969 	rtl_pci_commit(tp);
3970 
3971 	RTL_W8(tp, ChipCmd, CmdTxEnb | CmdRxEnb);
3972 	rtl_init_rxcfg(tp);
3973 	rtl_set_tx_config_registers(tp);
3974 	rtl_set_rx_config_features(tp, tp->dev->features);
3975 	rtl_set_rx_mode(tp->dev);
3976 	rtl_irq_enable(tp);
3977 }
3978 
rtl8169_change_mtu(struct net_device * dev,int new_mtu)3979 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
3980 {
3981 	struct rtl8169_private *tp = netdev_priv(dev);
3982 
3983 	WRITE_ONCE(dev->mtu, new_mtu);
3984 	netdev_update_features(dev);
3985 	rtl_jumbo_config(tp);
3986 	rtl_set_eee_txidle_timer(tp);
3987 
3988 	return 0;
3989 }
3990 
rtl8169_mark_to_asic(struct RxDesc * desc)3991 static void rtl8169_mark_to_asic(struct RxDesc *desc)
3992 {
3993 	u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
3994 
3995 	desc->opts2 = 0;
3996 	/* Force memory writes to complete before releasing descriptor */
3997 	dma_wmb();
3998 	WRITE_ONCE(desc->opts1, cpu_to_le32(DescOwn | eor | R8169_RX_BUF_SIZE));
3999 }
4000 
rtl8169_alloc_rx_data(struct rtl8169_private * tp,struct RxDesc * desc)4001 static struct page *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
4002 					  struct RxDesc *desc)
4003 {
4004 	struct device *d = tp_to_dev(tp);
4005 	int node = dev_to_node(d);
4006 	dma_addr_t mapping;
4007 	struct page *data;
4008 
4009 	data = alloc_pages_node(node, GFP_KERNEL, get_order(R8169_RX_BUF_SIZE));
4010 	if (!data)
4011 		return NULL;
4012 
4013 	mapping = dma_map_page(d, data, 0, R8169_RX_BUF_SIZE, DMA_FROM_DEVICE);
4014 	if (unlikely(dma_mapping_error(d, mapping))) {
4015 		netdev_err(tp->dev, "Failed to map RX DMA!\n");
4016 		__free_pages(data, get_order(R8169_RX_BUF_SIZE));
4017 		return NULL;
4018 	}
4019 
4020 	desc->addr = cpu_to_le64(mapping);
4021 	rtl8169_mark_to_asic(desc);
4022 
4023 	return data;
4024 }
4025 
rtl8169_rx_clear(struct rtl8169_private * tp)4026 static void rtl8169_rx_clear(struct rtl8169_private *tp)
4027 {
4028 	int i;
4029 
4030 	for (i = 0; i < NUM_RX_DESC && tp->Rx_databuff[i]; i++) {
4031 		dma_unmap_page(tp_to_dev(tp),
4032 			       le64_to_cpu(tp->RxDescArray[i].addr),
4033 			       R8169_RX_BUF_SIZE, DMA_FROM_DEVICE);
4034 		__free_pages(tp->Rx_databuff[i], get_order(R8169_RX_BUF_SIZE));
4035 		tp->Rx_databuff[i] = NULL;
4036 		tp->RxDescArray[i].addr = 0;
4037 		tp->RxDescArray[i].opts1 = 0;
4038 	}
4039 }
4040 
rtl8169_rx_fill(struct rtl8169_private * tp)4041 static int rtl8169_rx_fill(struct rtl8169_private *tp)
4042 {
4043 	int i;
4044 
4045 	for (i = 0; i < NUM_RX_DESC; i++) {
4046 		struct page *data;
4047 
4048 		data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
4049 		if (!data) {
4050 			rtl8169_rx_clear(tp);
4051 			return -ENOMEM;
4052 		}
4053 		tp->Rx_databuff[i] = data;
4054 	}
4055 
4056 	/* mark as last descriptor in the ring */
4057 	tp->RxDescArray[NUM_RX_DESC - 1].opts1 |= cpu_to_le32(RingEnd);
4058 
4059 	return 0;
4060 }
4061 
rtl8169_init_ring(struct rtl8169_private * tp)4062 static int rtl8169_init_ring(struct rtl8169_private *tp)
4063 {
4064 	rtl8169_init_ring_indexes(tp);
4065 
4066 	memset(tp->tx_skb, 0, sizeof(tp->tx_skb));
4067 	memset(tp->Rx_databuff, 0, sizeof(tp->Rx_databuff));
4068 
4069 	return rtl8169_rx_fill(tp);
4070 }
4071 
rtl8169_unmap_tx_skb(struct rtl8169_private * tp,unsigned int entry)4072 static void rtl8169_unmap_tx_skb(struct rtl8169_private *tp, unsigned int entry)
4073 {
4074 	struct ring_info *tx_skb = tp->tx_skb + entry;
4075 	struct TxDesc *desc = tp->TxDescArray + entry;
4076 
4077 	dma_unmap_single(tp_to_dev(tp), le64_to_cpu(desc->addr), tx_skb->len,
4078 			 DMA_TO_DEVICE);
4079 	memset(desc, 0, sizeof(*desc));
4080 	memset(tx_skb, 0, sizeof(*tx_skb));
4081 }
4082 
rtl8169_tx_clear_range(struct rtl8169_private * tp,u32 start,unsigned int n)4083 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
4084 				   unsigned int n)
4085 {
4086 	unsigned int i;
4087 
4088 	for (i = 0; i < n; i++) {
4089 		unsigned int entry = (start + i) % NUM_TX_DESC;
4090 		struct ring_info *tx_skb = tp->tx_skb + entry;
4091 		unsigned int len = tx_skb->len;
4092 
4093 		if (len) {
4094 			struct sk_buff *skb = tx_skb->skb;
4095 
4096 			rtl8169_unmap_tx_skb(tp, entry);
4097 			if (skb)
4098 				dev_consume_skb_any(skb);
4099 		}
4100 	}
4101 }
4102 
rtl8169_tx_clear(struct rtl8169_private * tp)4103 static void rtl8169_tx_clear(struct rtl8169_private *tp)
4104 {
4105 	rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
4106 	netdev_reset_queue(tp->dev);
4107 }
4108 
rtl8169_cleanup(struct rtl8169_private * tp)4109 static void rtl8169_cleanup(struct rtl8169_private *tp)
4110 {
4111 	napi_disable(&tp->napi);
4112 
4113 	/* Give a racing hard_start_xmit a few cycles to complete. */
4114 	synchronize_net();
4115 
4116 	/* Disable interrupts */
4117 	rtl8169_irq_mask_and_ack(tp);
4118 
4119 	rtl_rx_close(tp);
4120 
4121 	switch (tp->mac_version) {
4122 	case RTL_GIGA_MAC_VER_28:
4123 	case RTL_GIGA_MAC_VER_31:
4124 		rtl_loop_wait_low(tp, &rtl_npq_cond, 20, 2000);
4125 		break;
4126 	case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:
4127 		RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
4128 		rtl_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666);
4129 		break;
4130 	case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_71:
4131 		rtl_enable_rxdvgate(tp);
4132 		fsleep(2000);
4133 		break;
4134 	default:
4135 		RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
4136 		fsleep(100);
4137 		break;
4138 	}
4139 
4140 	rtl_hw_reset(tp);
4141 
4142 	rtl8169_tx_clear(tp);
4143 	rtl8169_init_ring_indexes(tp);
4144 }
4145 
rtl_reset_work(struct rtl8169_private * tp)4146 static void rtl_reset_work(struct rtl8169_private *tp)
4147 {
4148 	int i;
4149 
4150 	netif_stop_queue(tp->dev);
4151 
4152 	rtl8169_cleanup(tp);
4153 
4154 	for (i = 0; i < NUM_RX_DESC; i++)
4155 		rtl8169_mark_to_asic(tp->RxDescArray + i);
4156 
4157 	napi_enable(&tp->napi);
4158 	rtl_hw_start(tp);
4159 }
4160 
rtl8169_tx_timeout(struct net_device * dev,unsigned int txqueue)4161 static void rtl8169_tx_timeout(struct net_device *dev, unsigned int txqueue)
4162 {
4163 	struct rtl8169_private *tp = netdev_priv(dev);
4164 
4165 	rtl_schedule_task(tp, RTL_FLAG_TASK_TX_TIMEOUT);
4166 }
4167 
rtl8169_tx_map(struct rtl8169_private * tp,const u32 * opts,u32 len,void * addr,unsigned int entry,bool desc_own)4168 static int rtl8169_tx_map(struct rtl8169_private *tp, const u32 *opts, u32 len,
4169 			  void *addr, unsigned int entry, bool desc_own)
4170 {
4171 	struct TxDesc *txd = tp->TxDescArray + entry;
4172 	struct device *d = tp_to_dev(tp);
4173 	dma_addr_t mapping;
4174 	u32 opts1;
4175 	int ret;
4176 
4177 	mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
4178 	ret = dma_mapping_error(d, mapping);
4179 	if (unlikely(ret)) {
4180 		if (net_ratelimit())
4181 			netdev_err(tp->dev, "Failed to map TX data!\n");
4182 		return ret;
4183 	}
4184 
4185 	txd->addr = cpu_to_le64(mapping);
4186 	txd->opts2 = cpu_to_le32(opts[1]);
4187 
4188 	opts1 = opts[0] | len;
4189 	if (entry == NUM_TX_DESC - 1)
4190 		opts1 |= RingEnd;
4191 	if (desc_own)
4192 		opts1 |= DescOwn;
4193 	txd->opts1 = cpu_to_le32(opts1);
4194 
4195 	tp->tx_skb[entry].len = len;
4196 
4197 	return 0;
4198 }
4199 
rtl8169_xmit_frags(struct rtl8169_private * tp,struct sk_buff * skb,const u32 * opts,unsigned int entry)4200 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
4201 			      const u32 *opts, unsigned int entry)
4202 {
4203 	struct skb_shared_info *info = skb_shinfo(skb);
4204 	unsigned int cur_frag;
4205 
4206 	for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
4207 		const skb_frag_t *frag = info->frags + cur_frag;
4208 		void *addr = skb_frag_address(frag);
4209 		u32 len = skb_frag_size(frag);
4210 
4211 		entry = (entry + 1) % NUM_TX_DESC;
4212 
4213 		if (unlikely(rtl8169_tx_map(tp, opts, len, addr, entry, true)))
4214 			goto err_out;
4215 	}
4216 
4217 	return 0;
4218 
4219 err_out:
4220 	rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
4221 	return -EIO;
4222 }
4223 
rtl_skb_is_udp(struct sk_buff * skb)4224 static bool rtl_skb_is_udp(struct sk_buff *skb)
4225 {
4226 	int no = skb_network_offset(skb);
4227 	struct ipv6hdr *i6h, _i6h;
4228 	struct iphdr *ih, _ih;
4229 
4230 	switch (vlan_get_protocol(skb)) {
4231 	case htons(ETH_P_IP):
4232 		ih = skb_header_pointer(skb, no, sizeof(_ih), &_ih);
4233 		return ih && ih->protocol == IPPROTO_UDP;
4234 	case htons(ETH_P_IPV6):
4235 		i6h = skb_header_pointer(skb, no, sizeof(_i6h), &_i6h);
4236 		return i6h && i6h->nexthdr == IPPROTO_UDP;
4237 	default:
4238 		return false;
4239 	}
4240 }
4241 
4242 #define RTL_MIN_PATCH_LEN	47
4243 
4244 /* see rtl8125_get_patch_pad_len() in r8125 vendor driver */
rtl8125_quirk_udp_padto(struct rtl8169_private * tp,struct sk_buff * skb)4245 static unsigned int rtl8125_quirk_udp_padto(struct rtl8169_private *tp,
4246 					    struct sk_buff *skb)
4247 {
4248 	unsigned int padto = 0, len = skb->len;
4249 
4250 	if (len < 128 + RTL_MIN_PATCH_LEN && rtl_skb_is_udp(skb) &&
4251 	    skb_transport_header_was_set(skb)) {
4252 		unsigned int trans_data_len = skb_tail_pointer(skb) -
4253 					      skb_transport_header(skb);
4254 
4255 		if (trans_data_len >= offsetof(struct udphdr, len) &&
4256 		    trans_data_len < RTL_MIN_PATCH_LEN) {
4257 			u16 dest = ntohs(udp_hdr(skb)->dest);
4258 
4259 			/* dest is a standard PTP port */
4260 			if (dest == 319 || dest == 320)
4261 				padto = len + RTL_MIN_PATCH_LEN - trans_data_len;
4262 		}
4263 
4264 		if (trans_data_len < sizeof(struct udphdr))
4265 			padto = max_t(unsigned int, padto,
4266 				      len + sizeof(struct udphdr) - trans_data_len);
4267 	}
4268 
4269 	return padto;
4270 }
4271 
rtl_quirk_packet_padto(struct rtl8169_private * tp,struct sk_buff * skb)4272 static unsigned int rtl_quirk_packet_padto(struct rtl8169_private *tp,
4273 					   struct sk_buff *skb)
4274 {
4275 	unsigned int padto = 0;
4276 
4277 	switch (tp->mac_version) {
4278 	case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_63:
4279 		padto = rtl8125_quirk_udp_padto(tp, skb);
4280 		break;
4281 	default:
4282 		break;
4283 	}
4284 
4285 	switch (tp->mac_version) {
4286 	case RTL_GIGA_MAC_VER_34:
4287 	case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_71:
4288 		padto = max_t(unsigned int, padto, ETH_ZLEN);
4289 		break;
4290 	default:
4291 		break;
4292 	}
4293 
4294 	return padto;
4295 }
4296 
rtl8169_tso_csum_v1(struct sk_buff * skb,u32 * opts)4297 static void rtl8169_tso_csum_v1(struct sk_buff *skb, u32 *opts)
4298 {
4299 	u32 mss = skb_shinfo(skb)->gso_size;
4300 
4301 	if (mss) {
4302 		opts[0] |= TD_LSO;
4303 		opts[0] |= mss << TD0_MSS_SHIFT;
4304 	} else if (skb->ip_summed == CHECKSUM_PARTIAL) {
4305 		const struct iphdr *ip = ip_hdr(skb);
4306 
4307 		if (ip->protocol == IPPROTO_TCP)
4308 			opts[0] |= TD0_IP_CS | TD0_TCP_CS;
4309 		else if (ip->protocol == IPPROTO_UDP)
4310 			opts[0] |= TD0_IP_CS | TD0_UDP_CS;
4311 		else
4312 			WARN_ON_ONCE(1);
4313 	}
4314 }
4315 
rtl8169_tso_csum_v2(struct rtl8169_private * tp,struct sk_buff * skb,u32 * opts)4316 static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp,
4317 				struct sk_buff *skb, u32 *opts)
4318 {
4319 	struct skb_shared_info *shinfo = skb_shinfo(skb);
4320 	u32 mss = shinfo->gso_size;
4321 
4322 	if (mss) {
4323 		if (shinfo->gso_type & SKB_GSO_TCPV4) {
4324 			opts[0] |= TD1_GTSENV4;
4325 		} else if (shinfo->gso_type & SKB_GSO_TCPV6) {
4326 			if (skb_cow_head(skb, 0))
4327 				return false;
4328 
4329 			tcp_v6_gso_csum_prep(skb);
4330 			opts[0] |= TD1_GTSENV6;
4331 		} else {
4332 			WARN_ON_ONCE(1);
4333 		}
4334 
4335 		opts[0] |= skb_transport_offset(skb) << GTTCPHO_SHIFT;
4336 		opts[1] |= mss << TD1_MSS_SHIFT;
4337 	} else if (skb->ip_summed == CHECKSUM_PARTIAL) {
4338 		u8 ip_protocol;
4339 
4340 		switch (vlan_get_protocol(skb)) {
4341 		case htons(ETH_P_IP):
4342 			opts[1] |= TD1_IPv4_CS;
4343 			ip_protocol = ip_hdr(skb)->protocol;
4344 			break;
4345 
4346 		case htons(ETH_P_IPV6):
4347 			opts[1] |= TD1_IPv6_CS;
4348 			ip_protocol = ipv6_hdr(skb)->nexthdr;
4349 			break;
4350 
4351 		default:
4352 			ip_protocol = IPPROTO_RAW;
4353 			break;
4354 		}
4355 
4356 		if (ip_protocol == IPPROTO_TCP)
4357 			opts[1] |= TD1_TCP_CS;
4358 		else if (ip_protocol == IPPROTO_UDP)
4359 			opts[1] |= TD1_UDP_CS;
4360 		else
4361 			WARN_ON_ONCE(1);
4362 
4363 		opts[1] |= skb_transport_offset(skb) << TCPHO_SHIFT;
4364 	} else {
4365 		unsigned int padto = rtl_quirk_packet_padto(tp, skb);
4366 
4367 		/* skb_padto would free the skb on error */
4368 		return !__skb_put_padto(skb, padto, false);
4369 	}
4370 
4371 	return true;
4372 }
4373 
rtl_tx_slots_avail(struct rtl8169_private * tp)4374 static unsigned int rtl_tx_slots_avail(struct rtl8169_private *tp)
4375 {
4376 	return READ_ONCE(tp->dirty_tx) + NUM_TX_DESC - READ_ONCE(tp->cur_tx);
4377 }
4378 
4379 /* Versions RTL8102e and from RTL8168c onwards support csum_v2 */
rtl_chip_supports_csum_v2(struct rtl8169_private * tp)4380 static bool rtl_chip_supports_csum_v2(struct rtl8169_private *tp)
4381 {
4382 	switch (tp->mac_version) {
4383 	case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
4384 	case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17:
4385 		return false;
4386 	default:
4387 		return true;
4388 	}
4389 }
4390 
rtl8169_doorbell(struct rtl8169_private * tp)4391 static void rtl8169_doorbell(struct rtl8169_private *tp)
4392 {
4393 	if (rtl_is_8125(tp))
4394 		RTL_W16(tp, TxPoll_8125, BIT(0));
4395 	else
4396 		RTL_W8(tp, TxPoll, NPQ);
4397 }
4398 
rtl8169_start_xmit(struct sk_buff * skb,struct net_device * dev)4399 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
4400 				      struct net_device *dev)
4401 {
4402 	struct rtl8169_private *tp = netdev_priv(dev);
4403 	unsigned int entry = tp->cur_tx % NUM_TX_DESC;
4404 	struct TxDesc *txd_first, *txd_last;
4405 	bool stop_queue, door_bell;
4406 	unsigned int frags;
4407 	u32 opts[2];
4408 
4409 	if (unlikely(!rtl_tx_slots_avail(tp))) {
4410 		if (net_ratelimit())
4411 			netdev_err(dev, "BUG! Tx Ring full when queue awake!\n");
4412 		netif_stop_queue(dev);
4413 		return NETDEV_TX_BUSY;
4414 	}
4415 
4416 	opts[1] = rtl8169_tx_vlan_tag(skb);
4417 	opts[0] = 0;
4418 
4419 	if (!rtl_chip_supports_csum_v2(tp))
4420 		rtl8169_tso_csum_v1(skb, opts);
4421 	else if (!rtl8169_tso_csum_v2(tp, skb, opts))
4422 		goto err_dma_0;
4423 
4424 	if (unlikely(rtl8169_tx_map(tp, opts, skb_headlen(skb), skb->data,
4425 				    entry, false)))
4426 		goto err_dma_0;
4427 
4428 	txd_first = tp->TxDescArray + entry;
4429 
4430 	frags = skb_shinfo(skb)->nr_frags;
4431 	if (frags) {
4432 		if (rtl8169_xmit_frags(tp, skb, opts, entry))
4433 			goto err_dma_1;
4434 		entry = (entry + frags) % NUM_TX_DESC;
4435 	}
4436 
4437 	txd_last = tp->TxDescArray + entry;
4438 	txd_last->opts1 |= cpu_to_le32(LastFrag);
4439 	tp->tx_skb[entry].skb = skb;
4440 
4441 	skb_tx_timestamp(skb);
4442 
4443 	/* Force memory writes to complete before releasing descriptor */
4444 	dma_wmb();
4445 
4446 	door_bell = __netdev_sent_queue(dev, skb->len, netdev_xmit_more());
4447 
4448 	txd_first->opts1 |= cpu_to_le32(DescOwn | FirstFrag);
4449 
4450 	/* rtl_tx needs to see descriptor changes before updated tp->cur_tx */
4451 	smp_wmb();
4452 
4453 	WRITE_ONCE(tp->cur_tx, tp->cur_tx + frags + 1);
4454 
4455 	stop_queue = !netif_subqueue_maybe_stop(dev, 0, rtl_tx_slots_avail(tp),
4456 						R8169_TX_STOP_THRS,
4457 						R8169_TX_START_THRS);
4458 	if (door_bell || stop_queue)
4459 		rtl8169_doorbell(tp);
4460 
4461 	return NETDEV_TX_OK;
4462 
4463 err_dma_1:
4464 	rtl8169_unmap_tx_skb(tp, entry);
4465 err_dma_0:
4466 	dev_kfree_skb_any(skb);
4467 	dev->stats.tx_dropped++;
4468 	return NETDEV_TX_OK;
4469 }
4470 
rtl_last_frag_len(struct sk_buff * skb)4471 static unsigned int rtl_last_frag_len(struct sk_buff *skb)
4472 {
4473 	struct skb_shared_info *info = skb_shinfo(skb);
4474 	unsigned int nr_frags = info->nr_frags;
4475 
4476 	if (!nr_frags)
4477 		return UINT_MAX;
4478 
4479 	return skb_frag_size(info->frags + nr_frags - 1);
4480 }
4481 
4482 /* Workaround for hw issues with TSO on RTL8168evl */
rtl8168evl_fix_tso(struct sk_buff * skb,netdev_features_t features)4483 static netdev_features_t rtl8168evl_fix_tso(struct sk_buff *skb,
4484 					    netdev_features_t features)
4485 {
4486 	/* IPv4 header has options field */
4487 	if (vlan_get_protocol(skb) == htons(ETH_P_IP) &&
4488 	    ip_hdrlen(skb) > sizeof(struct iphdr))
4489 		features &= ~NETIF_F_ALL_TSO;
4490 
4491 	/* IPv4 TCP header has options field */
4492 	else if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV4 &&
4493 		 tcp_hdrlen(skb) > sizeof(struct tcphdr))
4494 		features &= ~NETIF_F_ALL_TSO;
4495 
4496 	else if (rtl_last_frag_len(skb) <= 6)
4497 		features &= ~NETIF_F_ALL_TSO;
4498 
4499 	return features;
4500 }
4501 
rtl8169_features_check(struct sk_buff * skb,struct net_device * dev,netdev_features_t features)4502 static netdev_features_t rtl8169_features_check(struct sk_buff *skb,
4503 						struct net_device *dev,
4504 						netdev_features_t features)
4505 {
4506 	struct rtl8169_private *tp = netdev_priv(dev);
4507 
4508 	if (skb_is_gso(skb)) {
4509 		if (tp->mac_version == RTL_GIGA_MAC_VER_34)
4510 			features = rtl8168evl_fix_tso(skb, features);
4511 
4512 		if (skb_transport_offset(skb) > GTTCPHO_MAX &&
4513 		    rtl_chip_supports_csum_v2(tp))
4514 			features &= ~NETIF_F_ALL_TSO;
4515 	} else if (skb->ip_summed == CHECKSUM_PARTIAL) {
4516 		/* work around hw bug on some chip versions */
4517 		if (skb->len < ETH_ZLEN)
4518 			features &= ~NETIF_F_CSUM_MASK;
4519 
4520 		if (rtl_quirk_packet_padto(tp, skb))
4521 			features &= ~NETIF_F_CSUM_MASK;
4522 
4523 		if (skb_transport_offset(skb) > TCPHO_MAX &&
4524 		    rtl_chip_supports_csum_v2(tp))
4525 			features &= ~NETIF_F_CSUM_MASK;
4526 	}
4527 
4528 	return vlan_features_check(skb, features);
4529 }
4530 
rtl8169_pcierr_interrupt(struct net_device * dev)4531 static void rtl8169_pcierr_interrupt(struct net_device *dev)
4532 {
4533 	struct rtl8169_private *tp = netdev_priv(dev);
4534 	struct pci_dev *pdev = tp->pci_dev;
4535 	int pci_status_errs;
4536 	u16 pci_cmd;
4537 
4538 	pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
4539 
4540 	pci_status_errs = pci_status_get_and_clear_errors(pdev);
4541 
4542 	if (net_ratelimit())
4543 		netdev_err(dev, "PCI error (cmd = 0x%04x, status_errs = 0x%04x)\n",
4544 			   pci_cmd, pci_status_errs);
4545 
4546 	rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
4547 }
4548 
rtl_tx(struct net_device * dev,struct rtl8169_private * tp,int budget)4549 static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp,
4550 		   int budget)
4551 {
4552 	unsigned int dirty_tx, bytes_compl = 0, pkts_compl = 0;
4553 	struct sk_buff *skb;
4554 
4555 	dirty_tx = tp->dirty_tx;
4556 
4557 	while (READ_ONCE(tp->cur_tx) != dirty_tx) {
4558 		unsigned int entry = dirty_tx % NUM_TX_DESC;
4559 		u32 status;
4560 
4561 		status = le32_to_cpu(READ_ONCE(tp->TxDescArray[entry].opts1));
4562 		if (status & DescOwn)
4563 			break;
4564 
4565 		skb = tp->tx_skb[entry].skb;
4566 		rtl8169_unmap_tx_skb(tp, entry);
4567 
4568 		if (skb) {
4569 			pkts_compl++;
4570 			bytes_compl += skb->len;
4571 			napi_consume_skb(skb, budget);
4572 		}
4573 		dirty_tx++;
4574 	}
4575 
4576 	if (tp->dirty_tx != dirty_tx) {
4577 		dev_sw_netstats_tx_add(dev, pkts_compl, bytes_compl);
4578 		WRITE_ONCE(tp->dirty_tx, dirty_tx);
4579 
4580 		netif_subqueue_completed_wake(dev, 0, pkts_compl, bytes_compl,
4581 					      rtl_tx_slots_avail(tp),
4582 					      R8169_TX_START_THRS);
4583 		/*
4584 		 * 8168 hack: TxPoll requests are lost when the Tx packets are
4585 		 * too close. Let's kick an extra TxPoll request when a burst
4586 		 * of start_xmit activity is detected (if it is not detected,
4587 		 * it is slow enough). -- FR
4588 		 * If skb is NULL then we come here again once a tx irq is
4589 		 * triggered after the last fragment is marked transmitted.
4590 		 */
4591 		if (READ_ONCE(tp->cur_tx) != dirty_tx && skb)
4592 			rtl8169_doorbell(tp);
4593 	}
4594 }
4595 
rtl8169_fragmented_frame(u32 status)4596 static inline int rtl8169_fragmented_frame(u32 status)
4597 {
4598 	return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
4599 }
4600 
rtl8169_rx_csum(struct sk_buff * skb,u32 opts1)4601 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
4602 {
4603 	u32 status = opts1 & (RxProtoMask | RxCSFailMask);
4604 
4605 	if (status == RxProtoTCP || status == RxProtoUDP)
4606 		skb->ip_summed = CHECKSUM_UNNECESSARY;
4607 	else
4608 		skb_checksum_none_assert(skb);
4609 }
4610 
rtl_rx(struct net_device * dev,struct rtl8169_private * tp,int budget)4611 static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, int budget)
4612 {
4613 	struct device *d = tp_to_dev(tp);
4614 	int count;
4615 
4616 	for (count = 0; count < budget; count++, tp->cur_rx++) {
4617 		unsigned int pkt_size, entry = tp->cur_rx % NUM_RX_DESC;
4618 		struct RxDesc *desc = tp->RxDescArray + entry;
4619 		struct sk_buff *skb;
4620 		const void *rx_buf;
4621 		dma_addr_t addr;
4622 		u32 status;
4623 
4624 		status = le32_to_cpu(READ_ONCE(desc->opts1));
4625 		if (status & DescOwn)
4626 			break;
4627 
4628 		/* This barrier is needed to keep us from reading
4629 		 * any other fields out of the Rx descriptor until
4630 		 * we know the status of DescOwn
4631 		 */
4632 		dma_rmb();
4633 
4634 		if (unlikely(status & RxRES)) {
4635 			if (net_ratelimit())
4636 				netdev_warn(dev, "Rx ERROR. status = %08x\n",
4637 					    status);
4638 			dev->stats.rx_errors++;
4639 			if (status & (RxRWT | RxRUNT))
4640 				dev->stats.rx_length_errors++;
4641 			if (status & RxCRC)
4642 				dev->stats.rx_crc_errors++;
4643 
4644 			if (!(dev->features & NETIF_F_RXALL))
4645 				goto release_descriptor;
4646 			else if (status & RxRWT || !(status & (RxRUNT | RxCRC)))
4647 				goto release_descriptor;
4648 		}
4649 
4650 		pkt_size = status & GENMASK(13, 0);
4651 		if (likely(!(dev->features & NETIF_F_RXFCS)))
4652 			pkt_size -= ETH_FCS_LEN;
4653 
4654 		/* The driver does not support incoming fragmented frames.
4655 		 * They are seen as a symptom of over-mtu sized frames.
4656 		 */
4657 		if (unlikely(rtl8169_fragmented_frame(status))) {
4658 			dev->stats.rx_dropped++;
4659 			dev->stats.rx_length_errors++;
4660 			goto release_descriptor;
4661 		}
4662 
4663 		skb = napi_alloc_skb(&tp->napi, pkt_size);
4664 		if (unlikely(!skb)) {
4665 			dev->stats.rx_dropped++;
4666 			goto release_descriptor;
4667 		}
4668 
4669 		addr = le64_to_cpu(desc->addr);
4670 		rx_buf = page_address(tp->Rx_databuff[entry]);
4671 
4672 		dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
4673 		prefetch(rx_buf);
4674 		skb_copy_to_linear_data(skb, rx_buf, pkt_size);
4675 		skb->tail += pkt_size;
4676 		skb->len = pkt_size;
4677 		dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
4678 
4679 		rtl8169_rx_csum(skb, status);
4680 		skb->protocol = eth_type_trans(skb, dev);
4681 
4682 		rtl8169_rx_vlan_tag(desc, skb);
4683 
4684 		if (skb->pkt_type == PACKET_MULTICAST)
4685 			dev->stats.multicast++;
4686 
4687 		napi_gro_receive(&tp->napi, skb);
4688 
4689 		dev_sw_netstats_rx_add(dev, pkt_size);
4690 release_descriptor:
4691 		rtl8169_mark_to_asic(desc);
4692 	}
4693 
4694 	return count;
4695 }
4696 
rtl8169_interrupt(int irq,void * dev_instance)4697 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
4698 {
4699 	struct rtl8169_private *tp = dev_instance;
4700 	u32 status = rtl_get_events(tp);
4701 
4702 	if ((status & 0xffff) == 0xffff || !(status & tp->irq_mask))
4703 		return IRQ_NONE;
4704 
4705 	/* At least RTL8168fp may unexpectedly set the SYSErr bit */
4706 	if (unlikely(status & SYSErr &&
4707 	    tp->mac_version <= RTL_GIGA_MAC_VER_06)) {
4708 		rtl8169_pcierr_interrupt(tp->dev);
4709 		goto out;
4710 	}
4711 
4712 	if (status & LinkChg)
4713 		phy_mac_interrupt(tp->phydev);
4714 
4715 	rtl_irq_disable(tp);
4716 	napi_schedule(&tp->napi);
4717 out:
4718 	rtl_ack_events(tp, status);
4719 
4720 	return IRQ_HANDLED;
4721 }
4722 
rtl_task(struct work_struct * work)4723 static void rtl_task(struct work_struct *work)
4724 {
4725 	struct rtl8169_private *tp =
4726 		container_of(work, struct rtl8169_private, wk.work);
4727 	int ret;
4728 
4729 	if (test_and_clear_bit(RTL_FLAG_TASK_TX_TIMEOUT, tp->wk.flags)) {
4730 		/* if chip isn't accessible, reset bus to revive it */
4731 		if (RTL_R32(tp, TxConfig) == ~0) {
4732 			ret = pci_reset_bus(tp->pci_dev);
4733 			if (ret < 0) {
4734 				netdev_err(tp->dev, "Can't reset secondary PCI bus, detach NIC\n");
4735 				netif_device_detach(tp->dev);
4736 				return;
4737 			}
4738 		}
4739 
4740 		/* ASPM compatibility issues are a typical reason for tx timeouts */
4741 		ret = pci_disable_link_state(tp->pci_dev, PCIE_LINK_STATE_L1 |
4742 							  PCIE_LINK_STATE_L0S);
4743 		if (!ret)
4744 			netdev_warn_once(tp->dev, "ASPM disabled on Tx timeout\n");
4745 		goto reset;
4746 	}
4747 
4748 	if (test_and_clear_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags)) {
4749 reset:
4750 		rtl_reset_work(tp);
4751 		netif_wake_queue(tp->dev);
4752 	}
4753 }
4754 
rtl8169_poll(struct napi_struct * napi,int budget)4755 static int rtl8169_poll(struct napi_struct *napi, int budget)
4756 {
4757 	struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
4758 	struct net_device *dev = tp->dev;
4759 	int work_done;
4760 
4761 	rtl_tx(dev, tp, budget);
4762 
4763 	work_done = rtl_rx(dev, tp, budget);
4764 
4765 	if (work_done < budget && napi_complete_done(napi, work_done))
4766 		rtl_irq_enable(tp);
4767 
4768 	return work_done;
4769 }
4770 
r8169_phylink_handler(struct net_device * ndev)4771 static void r8169_phylink_handler(struct net_device *ndev)
4772 {
4773 	struct rtl8169_private *tp = netdev_priv(ndev);
4774 	struct device *d = tp_to_dev(tp);
4775 
4776 	if (netif_carrier_ok(ndev)) {
4777 		rtl_link_chg_patch(tp);
4778 		pm_request_resume(d);
4779 	} else {
4780 		pm_runtime_idle(d);
4781 	}
4782 
4783 	phy_print_status(tp->phydev);
4784 }
4785 
r8169_phy_connect(struct rtl8169_private * tp)4786 static int r8169_phy_connect(struct rtl8169_private *tp)
4787 {
4788 	struct phy_device *phydev = tp->phydev;
4789 	phy_interface_t phy_mode;
4790 	int ret;
4791 
4792 	phy_mode = tp->supports_gmii ? PHY_INTERFACE_MODE_GMII :
4793 		   PHY_INTERFACE_MODE_MII;
4794 
4795 	ret = phy_connect_direct(tp->dev, phydev, r8169_phylink_handler,
4796 				 phy_mode);
4797 	if (ret)
4798 		return ret;
4799 
4800 	if (!tp->supports_gmii)
4801 		phy_set_max_speed(phydev, SPEED_100);
4802 
4803 	phy_attached_info(phydev);
4804 
4805 	return 0;
4806 }
4807 
rtl8169_down(struct rtl8169_private * tp)4808 static void rtl8169_down(struct rtl8169_private *tp)
4809 {
4810 	disable_work_sync(&tp->wk.work);
4811 	/* Clear all task flags */
4812 	bitmap_zero(tp->wk.flags, RTL_FLAG_MAX);
4813 
4814 	phy_stop(tp->phydev);
4815 
4816 	rtl8169_update_counters(tp);
4817 
4818 	pci_clear_master(tp->pci_dev);
4819 	rtl_pci_commit(tp);
4820 
4821 	rtl8169_cleanup(tp);
4822 	rtl_disable_exit_l1(tp);
4823 	rtl_prepare_power_down(tp);
4824 
4825 	if (tp->dash_type != RTL_DASH_NONE)
4826 		rtl8168_driver_stop(tp);
4827 }
4828 
rtl8169_up(struct rtl8169_private * tp)4829 static void rtl8169_up(struct rtl8169_private *tp)
4830 {
4831 	if (tp->dash_type != RTL_DASH_NONE)
4832 		rtl8168_driver_start(tp);
4833 
4834 	pci_set_master(tp->pci_dev);
4835 	phy_init_hw(tp->phydev);
4836 	phy_resume(tp->phydev);
4837 	rtl8169_init_phy(tp);
4838 	napi_enable(&tp->napi);
4839 	enable_work(&tp->wk.work);
4840 	rtl_reset_work(tp);
4841 
4842 	phy_start(tp->phydev);
4843 }
4844 
rtl8169_close(struct net_device * dev)4845 static int rtl8169_close(struct net_device *dev)
4846 {
4847 	struct rtl8169_private *tp = netdev_priv(dev);
4848 	struct pci_dev *pdev = tp->pci_dev;
4849 
4850 	pm_runtime_get_sync(&pdev->dev);
4851 
4852 	netif_stop_queue(dev);
4853 	rtl8169_down(tp);
4854 	rtl8169_rx_clear(tp);
4855 
4856 	free_irq(tp->irq, tp);
4857 
4858 	phy_disconnect(tp->phydev);
4859 
4860 	dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
4861 			  tp->RxPhyAddr);
4862 	dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
4863 			  tp->TxPhyAddr);
4864 	tp->TxDescArray = NULL;
4865 	tp->RxDescArray = NULL;
4866 
4867 	pm_runtime_put_sync(&pdev->dev);
4868 
4869 	return 0;
4870 }
4871 
4872 #ifdef CONFIG_NET_POLL_CONTROLLER
rtl8169_netpoll(struct net_device * dev)4873 static void rtl8169_netpoll(struct net_device *dev)
4874 {
4875 	struct rtl8169_private *tp = netdev_priv(dev);
4876 
4877 	rtl8169_interrupt(tp->irq, tp);
4878 }
4879 #endif
4880 
rtl_open(struct net_device * dev)4881 static int rtl_open(struct net_device *dev)
4882 {
4883 	struct rtl8169_private *tp = netdev_priv(dev);
4884 	struct pci_dev *pdev = tp->pci_dev;
4885 	unsigned long irqflags;
4886 	int retval = -ENOMEM;
4887 
4888 	pm_runtime_get_sync(&pdev->dev);
4889 
4890 	/*
4891 	 * Rx and Tx descriptors needs 256 bytes alignment.
4892 	 * dma_alloc_coherent provides more.
4893 	 */
4894 	tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
4895 					     &tp->TxPhyAddr, GFP_KERNEL);
4896 	if (!tp->TxDescArray)
4897 		goto out;
4898 
4899 	tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
4900 					     &tp->RxPhyAddr, GFP_KERNEL);
4901 	if (!tp->RxDescArray)
4902 		goto err_free_tx_0;
4903 
4904 	retval = rtl8169_init_ring(tp);
4905 	if (retval < 0)
4906 		goto err_free_rx_1;
4907 
4908 	rtl_request_firmware(tp);
4909 
4910 	irqflags = pci_dev_msi_enabled(pdev) ? IRQF_NO_THREAD : IRQF_SHARED;
4911 	retval = request_irq(tp->irq, rtl8169_interrupt, irqflags, dev->name, tp);
4912 	if (retval < 0)
4913 		goto err_release_fw_2;
4914 
4915 	retval = r8169_phy_connect(tp);
4916 	if (retval)
4917 		goto err_free_irq;
4918 
4919 	rtl8169_up(tp);
4920 	rtl8169_init_counter_offsets(tp);
4921 	netif_start_queue(dev);
4922 out:
4923 	pm_runtime_put_sync(&pdev->dev);
4924 
4925 	return retval;
4926 
4927 err_free_irq:
4928 	free_irq(tp->irq, tp);
4929 err_release_fw_2:
4930 	rtl_release_firmware(tp);
4931 	rtl8169_rx_clear(tp);
4932 err_free_rx_1:
4933 	dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
4934 			  tp->RxPhyAddr);
4935 	tp->RxDescArray = NULL;
4936 err_free_tx_0:
4937 	dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
4938 			  tp->TxPhyAddr);
4939 	tp->TxDescArray = NULL;
4940 	goto out;
4941 }
4942 
4943 static void
rtl8169_get_stats64(struct net_device * dev,struct rtnl_link_stats64 * stats)4944 rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
4945 {
4946 	struct rtl8169_private *tp = netdev_priv(dev);
4947 	struct pci_dev *pdev = tp->pci_dev;
4948 	struct rtl8169_counters *counters = tp->counters;
4949 
4950 	pm_runtime_get_noresume(&pdev->dev);
4951 
4952 	netdev_stats_to_stats64(stats, &dev->stats);
4953 	dev_fetch_sw_netstats(stats, dev->tstats);
4954 
4955 	/*
4956 	 * Fetch additional counter values missing in stats collected by driver
4957 	 * from tally counters.
4958 	 */
4959 	if (pm_runtime_active(&pdev->dev))
4960 		rtl8169_update_counters(tp);
4961 
4962 	/*
4963 	 * Subtract values fetched during initalization.
4964 	 * See rtl8169_init_counter_offsets for a description why we do that.
4965 	 */
4966 	stats->tx_errors = le64_to_cpu(counters->tx_errors) -
4967 		le64_to_cpu(tp->tc_offset.tx_errors);
4968 	stats->collisions = le32_to_cpu(counters->tx_multi_collision) -
4969 		le32_to_cpu(tp->tc_offset.tx_multi_collision);
4970 	stats->tx_aborted_errors = le16_to_cpu(counters->tx_aborted) -
4971 		le16_to_cpu(tp->tc_offset.tx_aborted);
4972 	stats->rx_missed_errors = le16_to_cpu(counters->rx_missed) -
4973 		le16_to_cpu(tp->tc_offset.rx_missed);
4974 
4975 	pm_runtime_put_noidle(&pdev->dev);
4976 }
4977 
rtl8169_net_suspend(struct rtl8169_private * tp)4978 static void rtl8169_net_suspend(struct rtl8169_private *tp)
4979 {
4980 	netif_device_detach(tp->dev);
4981 
4982 	if (netif_running(tp->dev))
4983 		rtl8169_down(tp);
4984 }
4985 
rtl8169_runtime_resume(struct device * dev)4986 static int rtl8169_runtime_resume(struct device *dev)
4987 {
4988 	struct rtl8169_private *tp = dev_get_drvdata(dev);
4989 
4990 	rtl_rar_set(tp, tp->dev->dev_addr);
4991 	__rtl8169_set_wol(tp, tp->saved_wolopts);
4992 
4993 	if (tp->TxDescArray)
4994 		rtl8169_up(tp);
4995 
4996 	netif_device_attach(tp->dev);
4997 
4998 	return 0;
4999 }
5000 
rtl8169_suspend(struct device * device)5001 static int rtl8169_suspend(struct device *device)
5002 {
5003 	struct rtl8169_private *tp = dev_get_drvdata(device);
5004 
5005 	rtnl_lock();
5006 	rtl8169_net_suspend(tp);
5007 	if (!device_may_wakeup(tp_to_dev(tp)))
5008 		clk_disable_unprepare(tp->clk);
5009 	rtnl_unlock();
5010 
5011 	return 0;
5012 }
5013 
rtl8169_resume(struct device * device)5014 static int rtl8169_resume(struct device *device)
5015 {
5016 	struct rtl8169_private *tp = dev_get_drvdata(device);
5017 
5018 	if (!device_may_wakeup(tp_to_dev(tp)))
5019 		clk_prepare_enable(tp->clk);
5020 
5021 	/* Reportedly at least Asus X453MA truncates packets otherwise */
5022 	if (tp->mac_version == RTL_GIGA_MAC_VER_37)
5023 		rtl_init_rxcfg(tp);
5024 
5025 	return rtl8169_runtime_resume(device);
5026 }
5027 
rtl8169_runtime_suspend(struct device * device)5028 static int rtl8169_runtime_suspend(struct device *device)
5029 {
5030 	struct rtl8169_private *tp = dev_get_drvdata(device);
5031 
5032 	if (!tp->TxDescArray) {
5033 		netif_device_detach(tp->dev);
5034 		return 0;
5035 	}
5036 
5037 	rtnl_lock();
5038 	__rtl8169_set_wol(tp, WAKE_PHY);
5039 	rtl8169_net_suspend(tp);
5040 	rtnl_unlock();
5041 
5042 	return 0;
5043 }
5044 
rtl8169_runtime_idle(struct device * device)5045 static int rtl8169_runtime_idle(struct device *device)
5046 {
5047 	struct rtl8169_private *tp = dev_get_drvdata(device);
5048 
5049 	if (tp->dash_enabled)
5050 		return -EBUSY;
5051 
5052 	if (!netif_running(tp->dev) || !netif_carrier_ok(tp->dev))
5053 		pm_schedule_suspend(device, 10000);
5054 
5055 	return -EBUSY;
5056 }
5057 
5058 static const struct dev_pm_ops rtl8169_pm_ops = {
5059 	SYSTEM_SLEEP_PM_OPS(rtl8169_suspend, rtl8169_resume)
5060 	RUNTIME_PM_OPS(rtl8169_runtime_suspend, rtl8169_runtime_resume,
5061 		       rtl8169_runtime_idle)
5062 };
5063 
rtl_shutdown(struct pci_dev * pdev)5064 static void rtl_shutdown(struct pci_dev *pdev)
5065 {
5066 	struct rtl8169_private *tp = pci_get_drvdata(pdev);
5067 
5068 	rtnl_lock();
5069 	rtl8169_net_suspend(tp);
5070 	rtnl_unlock();
5071 
5072 	/* Restore original MAC address */
5073 	rtl_rar_set(tp, tp->dev->perm_addr);
5074 
5075 	if (system_state == SYSTEM_POWER_OFF && !tp->dash_enabled) {
5076 		pci_wake_from_d3(pdev, tp->saved_wolopts);
5077 		pci_set_power_state(pdev, PCI_D3hot);
5078 	}
5079 }
5080 
rtl_remove_one(struct pci_dev * pdev)5081 static void rtl_remove_one(struct pci_dev *pdev)
5082 {
5083 	struct rtl8169_private *tp = pci_get_drvdata(pdev);
5084 
5085 	if (pci_dev_run_wake(pdev))
5086 		pm_runtime_get_noresume(&pdev->dev);
5087 
5088 	disable_work_sync(&tp->wk.work);
5089 
5090 	if (IS_ENABLED(CONFIG_R8169_LEDS))
5091 		r8169_remove_leds(tp->leds);
5092 
5093 	unregister_netdev(tp->dev);
5094 
5095 	if (tp->dash_type != RTL_DASH_NONE)
5096 		rtl8168_driver_stop(tp);
5097 
5098 	rtl_release_firmware(tp);
5099 
5100 	/* restore original MAC address */
5101 	rtl_rar_set(tp, tp->dev->perm_addr);
5102 }
5103 
5104 static const struct net_device_ops rtl_netdev_ops = {
5105 	.ndo_open		= rtl_open,
5106 	.ndo_stop		= rtl8169_close,
5107 	.ndo_get_stats64	= rtl8169_get_stats64,
5108 	.ndo_start_xmit		= rtl8169_start_xmit,
5109 	.ndo_features_check	= rtl8169_features_check,
5110 	.ndo_tx_timeout		= rtl8169_tx_timeout,
5111 	.ndo_validate_addr	= eth_validate_addr,
5112 	.ndo_change_mtu		= rtl8169_change_mtu,
5113 	.ndo_fix_features	= rtl8169_fix_features,
5114 	.ndo_set_features	= rtl8169_set_features,
5115 	.ndo_set_mac_address	= rtl_set_mac_address,
5116 	.ndo_eth_ioctl		= phy_do_ioctl_running,
5117 	.ndo_set_rx_mode	= rtl_set_rx_mode,
5118 #ifdef CONFIG_NET_POLL_CONTROLLER
5119 	.ndo_poll_controller	= rtl8169_netpoll,
5120 #endif
5121 
5122 };
5123 
rtl_set_irq_mask(struct rtl8169_private * tp)5124 static void rtl_set_irq_mask(struct rtl8169_private *tp)
5125 {
5126 	tp->irq_mask = RxOK | RxErr | TxOK | TxErr | LinkChg;
5127 
5128 	if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
5129 		tp->irq_mask |= SYSErr | RxFIFOOver;
5130 }
5131 
rtl_alloc_irq(struct rtl8169_private * tp)5132 static int rtl_alloc_irq(struct rtl8169_private *tp)
5133 {
5134 	unsigned int flags;
5135 
5136 	switch (tp->mac_version) {
5137 	case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
5138 		rtl_unlock_config_regs(tp);
5139 		RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~MSIEnable);
5140 		rtl_lock_config_regs(tp);
5141 		fallthrough;
5142 	case RTL_GIGA_MAC_VER_07 ... RTL_GIGA_MAC_VER_17:
5143 		flags = PCI_IRQ_INTX;
5144 		break;
5145 	default:
5146 		flags = PCI_IRQ_ALL_TYPES;
5147 		break;
5148 	}
5149 
5150 	return pci_alloc_irq_vectors(tp->pci_dev, 1, 1, flags);
5151 }
5152 
rtl_read_mac_address(struct rtl8169_private * tp,u8 mac_addr[ETH_ALEN])5153 static void rtl_read_mac_address(struct rtl8169_private *tp,
5154 				 u8 mac_addr[ETH_ALEN])
5155 {
5156 	/* Get MAC address */
5157 	if (rtl_is_8168evl_up(tp) && tp->mac_version != RTL_GIGA_MAC_VER_34) {
5158 		u32 value;
5159 
5160 		value = rtl_eri_read(tp, 0xe0);
5161 		put_unaligned_le32(value, mac_addr);
5162 		value = rtl_eri_read(tp, 0xe4);
5163 		put_unaligned_le16(value, mac_addr + 4);
5164 	} else if (rtl_is_8125(tp)) {
5165 		rtl_read_mac_from_reg(tp, mac_addr, MAC0_BKP);
5166 	}
5167 }
5168 
DECLARE_RTL_COND(rtl_link_list_ready_cond)5169 DECLARE_RTL_COND(rtl_link_list_ready_cond)
5170 {
5171 	return RTL_R8(tp, MCU) & LINK_LIST_RDY;
5172 }
5173 
r8168g_wait_ll_share_fifo_ready(struct rtl8169_private * tp)5174 static void r8168g_wait_ll_share_fifo_ready(struct rtl8169_private *tp)
5175 {
5176 	rtl_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42);
5177 }
5178 
r8169_mdio_read_reg(struct mii_bus * mii_bus,int phyaddr,int phyreg)5179 static int r8169_mdio_read_reg(struct mii_bus *mii_bus, int phyaddr, int phyreg)
5180 {
5181 	struct rtl8169_private *tp = mii_bus->priv;
5182 
5183 	if (phyaddr > 0)
5184 		return -ENODEV;
5185 
5186 	return rtl_readphy(tp, phyreg);
5187 }
5188 
r8169_mdio_write_reg(struct mii_bus * mii_bus,int phyaddr,int phyreg,u16 val)5189 static int r8169_mdio_write_reg(struct mii_bus *mii_bus, int phyaddr,
5190 				int phyreg, u16 val)
5191 {
5192 	struct rtl8169_private *tp = mii_bus->priv;
5193 
5194 	if (phyaddr > 0)
5195 		return -ENODEV;
5196 
5197 	rtl_writephy(tp, phyreg, val);
5198 
5199 	return 0;
5200 }
5201 
r8169_mdio_register(struct rtl8169_private * tp)5202 static int r8169_mdio_register(struct rtl8169_private *tp)
5203 {
5204 	struct pci_dev *pdev = tp->pci_dev;
5205 	struct mii_bus *new_bus;
5206 	int ret;
5207 
5208 	/* On some boards with this chip version the BIOS is buggy and misses
5209 	 * to reset the PHY page selector. This results in the PHY ID read
5210 	 * accessing registers on a different page, returning a more or
5211 	 * less random value. Fix this by resetting the page selector first.
5212 	 */
5213 	if (tp->mac_version == RTL_GIGA_MAC_VER_25 ||
5214 	    tp->mac_version == RTL_GIGA_MAC_VER_26)
5215 		r8169_mdio_write(tp, 0x1f, 0);
5216 
5217 	new_bus = devm_mdiobus_alloc(&pdev->dev);
5218 	if (!new_bus)
5219 		return -ENOMEM;
5220 
5221 	new_bus->name = "r8169";
5222 	new_bus->priv = tp;
5223 	new_bus->parent = &pdev->dev;
5224 	new_bus->irq[0] = PHY_MAC_INTERRUPT;
5225 	snprintf(new_bus->id, MII_BUS_ID_SIZE, "r8169-%x-%x",
5226 		 pci_domain_nr(pdev->bus), pci_dev_id(pdev));
5227 
5228 	new_bus->read = r8169_mdio_read_reg;
5229 	new_bus->write = r8169_mdio_write_reg;
5230 
5231 	ret = devm_mdiobus_register(&pdev->dev, new_bus);
5232 	if (ret)
5233 		return ret;
5234 
5235 	tp->phydev = mdiobus_get_phy(new_bus, 0);
5236 	if (!tp->phydev) {
5237 		return -ENODEV;
5238 	} else if (!tp->phydev->drv) {
5239 		/* Most chip versions fail with the genphy driver.
5240 		 * Therefore ensure that the dedicated PHY driver is loaded.
5241 		 */
5242 		dev_err(&pdev->dev, "no dedicated PHY driver found for PHY ID 0x%08x, maybe realtek.ko needs to be added to initramfs?\n",
5243 			tp->phydev->phy_id);
5244 		return -EUNATCH;
5245 	}
5246 
5247 	tp->phydev->mac_managed_pm = true;
5248 	if (rtl_supports_eee(tp))
5249 		phy_support_eee(tp->phydev);
5250 	phy_support_asym_pause(tp->phydev);
5251 
5252 	/* mimic behavior of r8125/r8126 vendor drivers */
5253 	if (tp->mac_version == RTL_GIGA_MAC_VER_61)
5254 		phy_set_eee_broken(tp->phydev,
5255 				   ETHTOOL_LINK_MODE_2500baseT_Full_BIT);
5256 	phy_set_eee_broken(tp->phydev, ETHTOOL_LINK_MODE_5000baseT_Full_BIT);
5257 
5258 	/* PHY will be woken up in rtl_open() */
5259 	phy_suspend(tp->phydev);
5260 
5261 	return 0;
5262 }
5263 
rtl_hw_init_8168g(struct rtl8169_private * tp)5264 static void rtl_hw_init_8168g(struct rtl8169_private *tp)
5265 {
5266 	rtl_enable_rxdvgate(tp);
5267 
5268 	RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
5269 	msleep(1);
5270 	RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
5271 
5272 	r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0);
5273 	r8168g_wait_ll_share_fifo_ready(tp);
5274 
5275 	r8168_mac_ocp_modify(tp, 0xe8de, 0, BIT(15));
5276 	r8168g_wait_ll_share_fifo_ready(tp);
5277 }
5278 
rtl_hw_init_8125(struct rtl8169_private * tp)5279 static void rtl_hw_init_8125(struct rtl8169_private *tp)
5280 {
5281 	rtl_enable_rxdvgate(tp);
5282 
5283 	RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
5284 	msleep(1);
5285 	RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
5286 
5287 	r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0);
5288 	r8168g_wait_ll_share_fifo_ready(tp);
5289 
5290 	r8168_mac_ocp_write(tp, 0xc0aa, 0x07d0);
5291 	r8168_mac_ocp_write(tp, 0xc0a6, 0x0150);
5292 	r8168_mac_ocp_write(tp, 0xc01e, 0x5555);
5293 	r8168g_wait_ll_share_fifo_ready(tp);
5294 }
5295 
rtl_hw_initialize(struct rtl8169_private * tp)5296 static void rtl_hw_initialize(struct rtl8169_private *tp)
5297 {
5298 	switch (tp->mac_version) {
5299 	case RTL_GIGA_MAC_VER_51 ... RTL_GIGA_MAC_VER_53:
5300 		rtl8168ep_stop_cmac(tp);
5301 		fallthrough;
5302 	case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_48:
5303 		rtl_hw_init_8168g(tp);
5304 		break;
5305 	case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_71:
5306 		rtl_hw_init_8125(tp);
5307 		break;
5308 	default:
5309 		break;
5310 	}
5311 }
5312 
rtl_jumbo_max(struct rtl8169_private * tp)5313 static int rtl_jumbo_max(struct rtl8169_private *tp)
5314 {
5315 	/* Non-GBit versions don't support jumbo frames */
5316 	if (!tp->supports_gmii)
5317 		return 0;
5318 
5319 	switch (tp->mac_version) {
5320 	/* RTL8169 */
5321 	case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
5322 		return JUMBO_7K;
5323 	/* RTL8168b */
5324 	case RTL_GIGA_MAC_VER_17:
5325 		return JUMBO_4K;
5326 	/* RTL8168c */
5327 	case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24:
5328 		return JUMBO_6K;
5329 	default:
5330 		return JUMBO_9K;
5331 	}
5332 }
5333 
rtl_init_mac_address(struct rtl8169_private * tp)5334 static void rtl_init_mac_address(struct rtl8169_private *tp)
5335 {
5336 	u8 mac_addr[ETH_ALEN] __aligned(2) = {};
5337 	struct net_device *dev = tp->dev;
5338 	int rc;
5339 
5340 	rc = eth_platform_get_mac_address(tp_to_dev(tp), mac_addr);
5341 	if (!rc)
5342 		goto done;
5343 
5344 	rtl_read_mac_address(tp, mac_addr);
5345 	if (is_valid_ether_addr(mac_addr))
5346 		goto done;
5347 
5348 	rtl_read_mac_from_reg(tp, mac_addr, MAC0);
5349 	if (is_valid_ether_addr(mac_addr))
5350 		goto done;
5351 
5352 	eth_random_addr(mac_addr);
5353 	dev->addr_assign_type = NET_ADDR_RANDOM;
5354 	dev_warn(tp_to_dev(tp), "can't read MAC address, setting random one\n");
5355 done:
5356 	eth_hw_addr_set(dev, mac_addr);
5357 	rtl_rar_set(tp, mac_addr);
5358 }
5359 
5360 /* register is set if system vendor successfully tested ASPM 1.2 */
rtl_aspm_is_safe(struct rtl8169_private * tp)5361 static bool rtl_aspm_is_safe(struct rtl8169_private *tp)
5362 {
5363 	if (tp->mac_version >= RTL_GIGA_MAC_VER_61 &&
5364 	    r8168_mac_ocp_read(tp, 0xc0b2) & 0xf)
5365 		return true;
5366 
5367 	return false;
5368 }
5369 
rtl_init_one(struct pci_dev * pdev,const struct pci_device_id * ent)5370 static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
5371 {
5372 	struct rtl8169_private *tp;
5373 	int jumbo_max, region, rc;
5374 	enum mac_version chipset;
5375 	struct net_device *dev;
5376 	u32 txconfig;
5377 	u16 xid;
5378 
5379 	dev = devm_alloc_etherdev(&pdev->dev, sizeof (*tp));
5380 	if (!dev)
5381 		return -ENOMEM;
5382 
5383 	SET_NETDEV_DEV(dev, &pdev->dev);
5384 	dev->netdev_ops = &rtl_netdev_ops;
5385 	tp = netdev_priv(dev);
5386 	tp->dev = dev;
5387 	tp->pci_dev = pdev;
5388 	tp->supports_gmii = ent->driver_data == RTL_CFG_NO_GBIT ? 0 : 1;
5389 	tp->ocp_base = OCP_STD_PHY_BASE;
5390 
5391 	raw_spin_lock_init(&tp->mac_ocp_lock);
5392 	mutex_init(&tp->led_lock);
5393 
5394 	/* Get the *optional* external "ether_clk" used on some boards */
5395 	tp->clk = devm_clk_get_optional_enabled(&pdev->dev, "ether_clk");
5396 	if (IS_ERR(tp->clk))
5397 		return dev_err_probe(&pdev->dev, PTR_ERR(tp->clk), "failed to get ether_clk\n");
5398 
5399 	/* enable device (incl. PCI PM wakeup and hotplug setup) */
5400 	rc = pcim_enable_device(pdev);
5401 	if (rc < 0)
5402 		return dev_err_probe(&pdev->dev, rc, "enable failure\n");
5403 
5404 	if (pcim_set_mwi(pdev) < 0)
5405 		dev_info(&pdev->dev, "Mem-Wr-Inval unavailable\n");
5406 
5407 	/* use first MMIO region */
5408 	region = ffs(pci_select_bars(pdev, IORESOURCE_MEM)) - 1;
5409 	if (region < 0)
5410 		return dev_err_probe(&pdev->dev, -ENODEV, "no MMIO resource found\n");
5411 
5412 	rc = pcim_iomap_regions(pdev, BIT(region), KBUILD_MODNAME);
5413 	if (rc < 0)
5414 		return dev_err_probe(&pdev->dev, rc, "cannot remap MMIO, aborting\n");
5415 
5416 	tp->mmio_addr = pcim_iomap_table(pdev)[region];
5417 
5418 	txconfig = RTL_R32(tp, TxConfig);
5419 	if (txconfig == ~0U)
5420 		return dev_err_probe(&pdev->dev, -EIO, "PCI read failed\n");
5421 
5422 	xid = (txconfig >> 20) & 0xfcf;
5423 
5424 	/* Identify chip attached to board */
5425 	chipset = rtl8169_get_mac_version(xid, tp->supports_gmii);
5426 	if (chipset == RTL_GIGA_MAC_NONE)
5427 		return dev_err_probe(&pdev->dev, -ENODEV,
5428 				     "unknown chip XID %03x, contact r8169 maintainers (see MAINTAINERS file)\n",
5429 				     xid);
5430 	tp->mac_version = chipset;
5431 
5432 	/* Disable ASPM L1 as that cause random device stop working
5433 	 * problems as well as full system hangs for some PCIe devices users.
5434 	 */
5435 	if (rtl_aspm_is_safe(tp))
5436 		rc = 0;
5437 	else
5438 		rc = pci_disable_link_state(pdev, PCIE_LINK_STATE_L1);
5439 	tp->aspm_manageable = !rc;
5440 
5441 	tp->dash_type = rtl_get_dash_type(tp);
5442 	tp->dash_enabled = rtl_dash_is_enabled(tp);
5443 
5444 	tp->cp_cmd = RTL_R16(tp, CPlusCmd) & CPCMD_MASK;
5445 
5446 	if (sizeof(dma_addr_t) > 4 && tp->mac_version >= RTL_GIGA_MAC_VER_18 &&
5447 	    !dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)))
5448 		dev->features |= NETIF_F_HIGHDMA;
5449 
5450 	rtl_init_rxcfg(tp);
5451 
5452 	rtl8169_irq_mask_and_ack(tp);
5453 
5454 	rtl_hw_initialize(tp);
5455 
5456 	rtl_hw_reset(tp);
5457 
5458 	rc = rtl_alloc_irq(tp);
5459 	if (rc < 0)
5460 		return dev_err_probe(&pdev->dev, rc, "Can't allocate interrupt\n");
5461 
5462 	tp->irq = pci_irq_vector(pdev, 0);
5463 
5464 	INIT_WORK(&tp->wk.work, rtl_task);
5465 	disable_work(&tp->wk.work);
5466 
5467 	rtl_init_mac_address(tp);
5468 
5469 	dev->ethtool_ops = &rtl8169_ethtool_ops;
5470 
5471 	netif_napi_add(dev, &tp->napi, rtl8169_poll);
5472 
5473 	dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_RXCSUM |
5474 			   NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
5475 	dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO;
5476 	dev->priv_flags |= IFF_LIVE_ADDR_CHANGE;
5477 
5478 	/*
5479 	 * Pretend we are using VLANs; This bypasses a nasty bug where
5480 	 * Interrupts stop flowing on high load on 8110SCd controllers.
5481 	 */
5482 	if (tp->mac_version == RTL_GIGA_MAC_VER_05)
5483 		/* Disallow toggling */
5484 		dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX;
5485 
5486 	if (rtl_chip_supports_csum_v2(tp))
5487 		dev->hw_features |= NETIF_F_IPV6_CSUM;
5488 
5489 	dev->features |= dev->hw_features;
5490 
5491 	if (rtl_chip_supports_csum_v2(tp)) {
5492 		dev->hw_features |= NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO6;
5493 		netif_set_tso_max_size(dev, RTL_GSO_MAX_SIZE_V2);
5494 		netif_set_tso_max_segs(dev, RTL_GSO_MAX_SEGS_V2);
5495 	} else {
5496 		dev->hw_features |= NETIF_F_SG | NETIF_F_TSO;
5497 		netif_set_tso_max_size(dev, RTL_GSO_MAX_SIZE_V1);
5498 		netif_set_tso_max_segs(dev, RTL_GSO_MAX_SEGS_V1);
5499 	}
5500 
5501 	/* There has been a number of reports that using SG/TSO results in
5502 	 * tx timeouts. However for a lot of people SG/TSO works fine.
5503 	 * It's not fully clear which chip versions are affected. Vendor
5504 	 * drivers enable SG/TSO for certain chip versions per default,
5505 	 * let's mimic this here. On other chip versions users can
5506 	 * use ethtool to enable SG/TSO, use at own risk!
5507 	 */
5508 	if (tp->mac_version >= RTL_GIGA_MAC_VER_46 &&
5509 	    tp->mac_version != RTL_GIGA_MAC_VER_61)
5510 		dev->features |= dev->hw_features;
5511 
5512 	dev->hw_features |= NETIF_F_RXALL;
5513 	dev->hw_features |= NETIF_F_RXFCS;
5514 
5515 	dev->pcpu_stat_type = NETDEV_PCPU_STAT_TSTATS;
5516 
5517 	netdev_sw_irq_coalesce_default_on(dev);
5518 
5519 	/* configure chip for default features */
5520 	rtl8169_set_features(dev, dev->features);
5521 
5522 	if (!tp->dash_enabled) {
5523 		rtl_set_d3_pll_down(tp, true);
5524 	} else {
5525 		rtl_set_d3_pll_down(tp, false);
5526 		dev->ethtool->wol_enabled = 1;
5527 	}
5528 
5529 	jumbo_max = rtl_jumbo_max(tp);
5530 	if (jumbo_max)
5531 		dev->max_mtu = jumbo_max;
5532 
5533 	rtl_set_irq_mask(tp);
5534 
5535 	tp->fw_name = rtl_chip_infos[chipset].fw_name;
5536 
5537 	tp->counters = dmam_alloc_coherent (&pdev->dev, sizeof(*tp->counters),
5538 					    &tp->counters_phys_addr,
5539 					    GFP_KERNEL);
5540 	if (!tp->counters)
5541 		return -ENOMEM;
5542 
5543 	pci_set_drvdata(pdev, tp);
5544 
5545 	rc = r8169_mdio_register(tp);
5546 	if (rc)
5547 		return rc;
5548 
5549 	rc = register_netdev(dev);
5550 	if (rc)
5551 		return rc;
5552 
5553 	if (IS_ENABLED(CONFIG_R8169_LEDS)) {
5554 		if (rtl_is_8125(tp))
5555 			tp->leds = rtl8125_init_leds(dev);
5556 		else if (tp->mac_version > RTL_GIGA_MAC_VER_06)
5557 			tp->leds = rtl8168_init_leds(dev);
5558 	}
5559 
5560 	netdev_info(dev, "%s, %pM, XID %03x, IRQ %d\n",
5561 		    rtl_chip_infos[chipset].name, dev->dev_addr, xid, tp->irq);
5562 
5563 	if (jumbo_max)
5564 		netdev_info(dev, "jumbo features [frames: %d bytes, tx checksumming: %s]\n",
5565 			    jumbo_max, tp->mac_version <= RTL_GIGA_MAC_VER_06 ?
5566 			    "ok" : "ko");
5567 
5568 	if (tp->dash_type != RTL_DASH_NONE) {
5569 		netdev_info(dev, "DASH %s\n",
5570 			    tp->dash_enabled ? "enabled" : "disabled");
5571 		rtl8168_driver_start(tp);
5572 	}
5573 
5574 	if (pci_dev_run_wake(pdev))
5575 		pm_runtime_put_sync(&pdev->dev);
5576 
5577 	return 0;
5578 }
5579 
5580 static struct pci_driver rtl8169_pci_driver = {
5581 	.name		= KBUILD_MODNAME,
5582 	.id_table	= rtl8169_pci_tbl,
5583 	.probe		= rtl_init_one,
5584 	.remove		= rtl_remove_one,
5585 	.shutdown	= rtl_shutdown,
5586 	.driver.pm	= pm_ptr(&rtl8169_pm_ops),
5587 };
5588 
5589 module_pci_driver(rtl8169_pci_driver);
5590