1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (c) 2018, The Linux Foundation. All rights reserved.
4 * datasheet: https://www.ti.com/lit/ds/symlink/sn65dsi86.pdf
5 */
6
7 #include <linux/atomic.h>
8 #include <linux/auxiliary_bus.h>
9 #include <linux/bitfield.h>
10 #include <linux/bits.h>
11 #include <linux/clk.h>
12 #include <linux/debugfs.h>
13 #include <linux/gpio/consumer.h>
14 #include <linux/gpio/driver.h>
15 #include <linux/i2c.h>
16 #include <linux/iopoll.h>
17 #include <linux/module.h>
18 #include <linux/of_graph.h>
19 #include <linux/pm_runtime.h>
20 #include <linux/pwm.h>
21 #include <linux/regmap.h>
22 #include <linux/regulator/consumer.h>
23
24 #include <linux/unaligned.h>
25
26 #include <drm/display/drm_dp_aux_bus.h>
27 #include <drm/display/drm_dp_helper.h>
28 #include <drm/drm_atomic.h>
29 #include <drm/drm_atomic_helper.h>
30 #include <drm/drm_bridge.h>
31 #include <drm/drm_bridge_connector.h>
32 #include <drm/drm_edid.h>
33 #include <drm/drm_mipi_dsi.h>
34 #include <drm/drm_of.h>
35 #include <drm/drm_print.h>
36 #include <drm/drm_probe_helper.h>
37
38 #define SN_DEVICE_ID_REGS 0x00 /* up to 0x07 */
39 #define SN_DEVICE_REV_REG 0x08
40 #define SN_DPPLL_SRC_REG 0x0A
41 #define DPPLL_CLK_SRC_DSICLK BIT(0)
42 #define REFCLK_FREQ_MASK GENMASK(3, 1)
43 #define REFCLK_FREQ(x) ((x) << 1)
44 #define DPPLL_SRC_DP_PLL_LOCK BIT(7)
45 #define SN_PLL_ENABLE_REG 0x0D
46 #define SN_DSI_LANES_REG 0x10
47 #define CHA_DSI_LANES_MASK GENMASK(4, 3)
48 #define CHA_DSI_LANES(x) ((x) << 3)
49 #define SN_DSIA_CLK_FREQ_REG 0x12
50 #define SN_CHA_ACTIVE_LINE_LENGTH_LOW_REG 0x20
51 #define SN_CHA_VERTICAL_DISPLAY_SIZE_LOW_REG 0x24
52 #define SN_CHA_HSYNC_PULSE_WIDTH_LOW_REG 0x2C
53 #define SN_CHA_HSYNC_PULSE_WIDTH_HIGH_REG 0x2D
54 #define CHA_HSYNC_POLARITY BIT(7)
55 #define SN_CHA_VSYNC_PULSE_WIDTH_LOW_REG 0x30
56 #define SN_CHA_VSYNC_PULSE_WIDTH_HIGH_REG 0x31
57 #define CHA_VSYNC_POLARITY BIT(7)
58 #define SN_CHA_HORIZONTAL_BACK_PORCH_REG 0x34
59 #define SN_CHA_VERTICAL_BACK_PORCH_REG 0x36
60 #define SN_CHA_HORIZONTAL_FRONT_PORCH_REG 0x38
61 #define SN_CHA_VERTICAL_FRONT_PORCH_REG 0x3A
62 #define SN_LN_ASSIGN_REG 0x59
63 #define LN_ASSIGN_WIDTH 2
64 #define SN_ENH_FRAME_REG 0x5A
65 #define VSTREAM_ENABLE BIT(3)
66 #define LN_POLRS_OFFSET 4
67 #define LN_POLRS_MASK 0xf0
68 #define SN_DATA_FORMAT_REG 0x5B
69 #define BPP_18_RGB BIT(0)
70 #define SN_HPD_DISABLE_REG 0x5C
71 #define HPD_DISABLE BIT(0)
72 #define HPD_DEBOUNCED_STATE BIT(4)
73 #define SN_GPIO_IO_REG 0x5E
74 #define SN_GPIO_INPUT_SHIFT 4
75 #define SN_GPIO_OUTPUT_SHIFT 0
76 #define SN_GPIO_CTRL_REG 0x5F
77 #define SN_GPIO_MUX_INPUT 0
78 #define SN_GPIO_MUX_OUTPUT 1
79 #define SN_GPIO_MUX_SPECIAL 2
80 #define SN_GPIO_MUX_MASK 0x3
81 #define SN_AUX_WDATA_REG(x) (0x64 + (x))
82 #define SN_AUX_ADDR_19_16_REG 0x74
83 #define SN_AUX_ADDR_15_8_REG 0x75
84 #define SN_AUX_ADDR_7_0_REG 0x76
85 #define SN_AUX_ADDR_MASK GENMASK(19, 0)
86 #define SN_AUX_LENGTH_REG 0x77
87 #define SN_AUX_CMD_REG 0x78
88 #define AUX_CMD_SEND BIT(0)
89 #define AUX_CMD_REQ(x) ((x) << 4)
90 #define SN_AUX_RDATA_REG(x) (0x79 + (x))
91 #define SN_SSC_CONFIG_REG 0x93
92 #define DP_NUM_LANES_MASK GENMASK(5, 4)
93 #define DP_NUM_LANES(x) ((x) << 4)
94 #define SN_DATARATE_CONFIG_REG 0x94
95 #define DP_DATARATE_MASK GENMASK(7, 5)
96 #define DP_DATARATE(x) ((x) << 5)
97 #define SN_TRAINING_SETTING_REG 0x95
98 #define SCRAMBLE_DISABLE BIT(4)
99 #define SN_ML_TX_MODE_REG 0x96
100 #define ML_TX_MAIN_LINK_OFF 0
101 #define ML_TX_NORMAL_MODE BIT(0)
102 #define SN_PWM_PRE_DIV_REG 0xA0
103 #define SN_BACKLIGHT_SCALE_REG 0xA1
104 #define BACKLIGHT_SCALE_MAX 0xFFFF
105 #define SN_BACKLIGHT_REG 0xA3
106 #define SN_PWM_EN_INV_REG 0xA5
107 #define SN_PWM_INV_MASK BIT(0)
108 #define SN_PWM_EN_MASK BIT(1)
109 #define SN_AUX_CMD_STATUS_REG 0xF4
110 #define AUX_IRQ_STATUS_AUX_RPLY_TOUT BIT(3)
111 #define AUX_IRQ_STATUS_AUX_SHORT BIT(5)
112 #define AUX_IRQ_STATUS_NAT_I2C_FAIL BIT(6)
113
114 #define MIN_DSI_CLK_FREQ_MHZ 40
115
116 /* fudge factor required to account for 8b/10b encoding */
117 #define DP_CLK_FUDGE_NUM 10
118 #define DP_CLK_FUDGE_DEN 8
119
120 /* Matches DP_AUX_MAX_PAYLOAD_BYTES (for now) */
121 #define SN_AUX_MAX_PAYLOAD_BYTES 16
122
123 #define SN_REGULATOR_SUPPLY_NUM 4
124
125 #define SN_MAX_DP_LANES 4
126 #define SN_NUM_GPIOS 4
127 #define SN_GPIO_PHYSICAL_OFFSET 1
128
129 #define SN_LINK_TRAINING_TRIES 10
130
131 #define SN_PWM_GPIO_IDX 3 /* 4th GPIO */
132
133 /**
134 * struct ti_sn65dsi86 - Platform data for ti-sn65dsi86 driver.
135 * @bridge_aux: AUX-bus sub device for MIPI-to-eDP bridge functionality.
136 * @gpio_aux: AUX-bus sub device for GPIO controller functionality.
137 * @aux_aux: AUX-bus sub device for eDP AUX channel functionality.
138 * @pwm_aux: AUX-bus sub device for PWM controller functionality.
139 *
140 * @dev: Pointer to the top level (i2c) device.
141 * @regmap: Regmap for accessing i2c.
142 * @aux: Our aux channel.
143 * @bridge: Our bridge.
144 * @connector: Our connector.
145 * @host_node: Remote DSI node.
146 * @dsi: Our MIPI DSI source.
147 * @refclk: Our reference clock.
148 * @next_bridge: The bridge on the eDP side.
149 * @enable_gpio: The GPIO we toggle to enable the bridge.
150 * @supplies: Data for bulk enabling/disabling our regulators.
151 * @dp_lanes: Count of dp_lanes we're using.
152 * @ln_assign: Value to program to the LN_ASSIGN register.
153 * @ln_polrs: Value for the 4-bit LN_POLRS field of SN_ENH_FRAME_REG.
154 * @comms_enabled: If true then communication over the aux channel is enabled.
155 * @comms_mutex: Protects modification of comms_enabled.
156 *
157 * @gchip: If we expose our GPIOs, this is used.
158 * @gchip_output: A cache of whether we've set GPIOs to output. This
159 * serves double-duty of keeping track of the direction and
160 * also keeping track of whether we've incremented the
161 * pm_runtime reference count for this pin, which we do
162 * whenever a pin is configured as an output. This is a
163 * bitmap so we can do atomic ops on it without an extra
164 * lock so concurrent users of our 4 GPIOs don't stomp on
165 * each other's read-modify-write.
166 *
167 * @pchip: pwm_chip if the PWM is exposed.
168 * @pwm_enabled: Used to track if the PWM signal is currently enabled.
169 * @pwm_pin_busy: Track if GPIO4 is currently requested for GPIO or PWM.
170 * @pwm_refclk_freq: Cache for the reference clock input to the PWM.
171 */
172 struct ti_sn65dsi86 {
173 struct auxiliary_device *bridge_aux;
174 struct auxiliary_device *gpio_aux;
175 struct auxiliary_device *aux_aux;
176 struct auxiliary_device *pwm_aux;
177
178 struct device *dev;
179 struct regmap *regmap;
180 struct drm_dp_aux aux;
181 struct drm_bridge bridge;
182 struct drm_connector *connector;
183 struct device_node *host_node;
184 struct mipi_dsi_device *dsi;
185 struct clk *refclk;
186 struct drm_bridge *next_bridge;
187 struct gpio_desc *enable_gpio;
188 struct regulator_bulk_data supplies[SN_REGULATOR_SUPPLY_NUM];
189 int dp_lanes;
190 u8 ln_assign;
191 u8 ln_polrs;
192 bool comms_enabled;
193 struct mutex comms_mutex;
194
195 #if defined(CONFIG_OF_GPIO)
196 struct gpio_chip gchip;
197 DECLARE_BITMAP(gchip_output, SN_NUM_GPIOS);
198 #endif
199 #if IS_REACHABLE(CONFIG_PWM)
200 struct pwm_chip *pchip;
201 bool pwm_enabled;
202 atomic_t pwm_pin_busy;
203 #endif
204 unsigned int pwm_refclk_freq;
205 };
206
207 static const struct regmap_range ti_sn65dsi86_volatile_ranges[] = {
208 { .range_min = 0, .range_max = 0xFF },
209 };
210
211 static const struct regmap_access_table ti_sn_bridge_volatile_table = {
212 .yes_ranges = ti_sn65dsi86_volatile_ranges,
213 .n_yes_ranges = ARRAY_SIZE(ti_sn65dsi86_volatile_ranges),
214 };
215
216 static const struct regmap_config ti_sn65dsi86_regmap_config = {
217 .reg_bits = 8,
218 .val_bits = 8,
219 .volatile_table = &ti_sn_bridge_volatile_table,
220 .cache_type = REGCACHE_NONE,
221 .max_register = 0xFF,
222 };
223
ti_sn65dsi86_read_u16(struct ti_sn65dsi86 * pdata,unsigned int reg,u16 * val)224 static int __maybe_unused ti_sn65dsi86_read_u16(struct ti_sn65dsi86 *pdata,
225 unsigned int reg, u16 *val)
226 {
227 u8 buf[2];
228 int ret;
229
230 ret = regmap_bulk_read(pdata->regmap, reg, buf, ARRAY_SIZE(buf));
231 if (ret)
232 return ret;
233
234 *val = buf[0] | (buf[1] << 8);
235
236 return 0;
237 }
238
ti_sn65dsi86_write_u16(struct ti_sn65dsi86 * pdata,unsigned int reg,u16 val)239 static void ti_sn65dsi86_write_u16(struct ti_sn65dsi86 *pdata,
240 unsigned int reg, u16 val)
241 {
242 u8 buf[2] = { val & 0xff, val >> 8 };
243
244 regmap_bulk_write(pdata->regmap, reg, buf, ARRAY_SIZE(buf));
245 }
246
247 static struct drm_display_mode *
get_new_adjusted_display_mode(struct drm_bridge * bridge,struct drm_atomic_state * state)248 get_new_adjusted_display_mode(struct drm_bridge *bridge,
249 struct drm_atomic_state *state)
250 {
251 struct drm_connector *connector =
252 drm_atomic_get_new_connector_for_encoder(state, bridge->encoder);
253 struct drm_connector_state *conn_state =
254 drm_atomic_get_new_connector_state(state, connector);
255 struct drm_crtc_state *crtc_state =
256 drm_atomic_get_new_crtc_state(state, conn_state->crtc);
257
258 return &crtc_state->adjusted_mode;
259 }
260
ti_sn_bridge_get_dsi_freq(struct ti_sn65dsi86 * pdata,struct drm_atomic_state * state)261 static u32 ti_sn_bridge_get_dsi_freq(struct ti_sn65dsi86 *pdata,
262 struct drm_atomic_state *state)
263 {
264 u32 bit_rate_khz, clk_freq_khz;
265 struct drm_display_mode *mode =
266 get_new_adjusted_display_mode(&pdata->bridge, state);
267
268 bit_rate_khz = mode->clock *
269 mipi_dsi_pixel_format_to_bpp(pdata->dsi->format);
270 clk_freq_khz = bit_rate_khz / (pdata->dsi->lanes * 2);
271
272 return clk_freq_khz;
273 }
274
275 /* clk frequencies supported by bridge in Hz in case derived from REFCLK pin */
276 static const u32 ti_sn_bridge_refclk_lut[] = {
277 12000000,
278 19200000,
279 26000000,
280 27000000,
281 38400000,
282 };
283
284 /* clk frequencies supported by bridge in Hz in case derived from DACP/N pin */
285 static const u32 ti_sn_bridge_dsiclk_lut[] = {
286 468000000,
287 384000000,
288 416000000,
289 486000000,
290 460800000,
291 };
292
ti_sn_bridge_set_refclk_freq(struct ti_sn65dsi86 * pdata,struct drm_atomic_state * state)293 static void ti_sn_bridge_set_refclk_freq(struct ti_sn65dsi86 *pdata,
294 struct drm_atomic_state *state)
295 {
296 int i;
297 u32 refclk_rate;
298 const u32 *refclk_lut;
299 size_t refclk_lut_size;
300
301 if (pdata->refclk) {
302 refclk_rate = clk_get_rate(pdata->refclk);
303 refclk_lut = ti_sn_bridge_refclk_lut;
304 refclk_lut_size = ARRAY_SIZE(ti_sn_bridge_refclk_lut);
305 clk_prepare_enable(pdata->refclk);
306 } else {
307 refclk_rate = ti_sn_bridge_get_dsi_freq(pdata, state) * 1000;
308 refclk_lut = ti_sn_bridge_dsiclk_lut;
309 refclk_lut_size = ARRAY_SIZE(ti_sn_bridge_dsiclk_lut);
310 }
311
312 /* for i equals to refclk_lut_size means default frequency */
313 for (i = 0; i < refclk_lut_size; i++)
314 if (refclk_lut[i] == refclk_rate)
315 break;
316
317 /* avoid buffer overflow and "1" is the default rate in the datasheet. */
318 if (i >= refclk_lut_size)
319 i = 1;
320
321 regmap_update_bits(pdata->regmap, SN_DPPLL_SRC_REG, REFCLK_FREQ_MASK,
322 REFCLK_FREQ(i));
323
324 /*
325 * The PWM refclk is based on the value written to SN_DPPLL_SRC_REG,
326 * regardless of its actual sourcing.
327 */
328 pdata->pwm_refclk_freq = ti_sn_bridge_refclk_lut[i];
329 }
330
ti_sn65dsi86_enable_comms(struct ti_sn65dsi86 * pdata,struct drm_atomic_state * state)331 static void ti_sn65dsi86_enable_comms(struct ti_sn65dsi86 *pdata,
332 struct drm_atomic_state *state)
333 {
334 mutex_lock(&pdata->comms_mutex);
335
336 /* configure bridge ref_clk */
337 ti_sn_bridge_set_refclk_freq(pdata, state);
338
339 /*
340 * HPD on this bridge chip is a bit useless. This is an eDP bridge
341 * so the HPD is an internal signal that's only there to signal that
342 * the panel is done powering up. ...but the bridge chip debounces
343 * this signal by between 100 ms and 400 ms (depending on process,
344 * voltage, and temperate--I measured it at about 200 ms). One
345 * particular panel asserted HPD 84 ms after it was powered on meaning
346 * that we saw HPD 284 ms after power on. ...but the same panel said
347 * that instead of looking at HPD you could just hardcode a delay of
348 * 200 ms. We'll assume that the panel driver will have the hardcoded
349 * delay in its prepare and always disable HPD.
350 *
351 * For DisplayPort bridge type, we need HPD. So we use the bridge type
352 * to conditionally disable HPD.
353 * NOTE: The bridge type is set in ti_sn_bridge_probe() but enable_comms()
354 * can be called before. So for DisplayPort, HPD will be enabled once
355 * bridge type is set. We are using bridge type instead of "no-hpd"
356 * property because it is not used properly in devicetree description
357 * and hence is unreliable.
358 */
359
360 if (pdata->bridge.type != DRM_MODE_CONNECTOR_DisplayPort)
361 regmap_update_bits(pdata->regmap, SN_HPD_DISABLE_REG, HPD_DISABLE,
362 HPD_DISABLE);
363
364 pdata->comms_enabled = true;
365
366 mutex_unlock(&pdata->comms_mutex);
367 }
368
ti_sn65dsi86_disable_comms(struct ti_sn65dsi86 * pdata)369 static void ti_sn65dsi86_disable_comms(struct ti_sn65dsi86 *pdata)
370 {
371 mutex_lock(&pdata->comms_mutex);
372
373 pdata->comms_enabled = false;
374 clk_disable_unprepare(pdata->refclk);
375
376 mutex_unlock(&pdata->comms_mutex);
377 }
378
ti_sn65dsi86_resume(struct device * dev)379 static int __maybe_unused ti_sn65dsi86_resume(struct device *dev)
380 {
381 struct ti_sn65dsi86 *pdata = dev_get_drvdata(dev);
382 int ret;
383
384 ret = regulator_bulk_enable(SN_REGULATOR_SUPPLY_NUM, pdata->supplies);
385 if (ret) {
386 DRM_ERROR("failed to enable supplies %d\n", ret);
387 return ret;
388 }
389
390 /* td2: min 100 us after regulators before enabling the GPIO */
391 usleep_range(100, 110);
392
393 gpiod_set_value_cansleep(pdata->enable_gpio, 1);
394
395 /*
396 * If we have a reference clock we can enable communication w/ the
397 * panel (including the aux channel) w/out any need for an input clock
398 * so we can do it in resume which lets us read the EDID before
399 * pre_enable(). Without a reference clock we need the MIPI reference
400 * clock so reading early doesn't work.
401 */
402 if (pdata->refclk)
403 ti_sn65dsi86_enable_comms(pdata, NULL);
404
405 return ret;
406 }
407
ti_sn65dsi86_suspend(struct device * dev)408 static int __maybe_unused ti_sn65dsi86_suspend(struct device *dev)
409 {
410 struct ti_sn65dsi86 *pdata = dev_get_drvdata(dev);
411 int ret;
412
413 if (pdata->refclk)
414 ti_sn65dsi86_disable_comms(pdata);
415
416 gpiod_set_value_cansleep(pdata->enable_gpio, 0);
417
418 ret = regulator_bulk_disable(SN_REGULATOR_SUPPLY_NUM, pdata->supplies);
419 if (ret)
420 DRM_ERROR("failed to disable supplies %d\n", ret);
421
422 return ret;
423 }
424
425 static const struct dev_pm_ops ti_sn65dsi86_pm_ops = {
426 SET_RUNTIME_PM_OPS(ti_sn65dsi86_suspend, ti_sn65dsi86_resume, NULL)
427 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
428 pm_runtime_force_resume)
429 };
430
status_show(struct seq_file * s,void * data)431 static int status_show(struct seq_file *s, void *data)
432 {
433 struct ti_sn65dsi86 *pdata = s->private;
434 unsigned int reg, val;
435
436 seq_puts(s, "STATUS REGISTERS:\n");
437
438 pm_runtime_get_sync(pdata->dev);
439
440 /* IRQ Status Registers, see Table 31 in datasheet */
441 for (reg = 0xf0; reg <= 0xf8; reg++) {
442 regmap_read(pdata->regmap, reg, &val);
443 seq_printf(s, "[0x%02x] = 0x%08x\n", reg, val);
444 }
445
446 pm_runtime_put_autosuspend(pdata->dev);
447
448 return 0;
449 }
450 DEFINE_SHOW_ATTRIBUTE(status);
451
452 /* -----------------------------------------------------------------------------
453 * Auxiliary Devices (*not* AUX)
454 */
455
ti_sn65dsi86_uninit_aux(void * data)456 static void ti_sn65dsi86_uninit_aux(void *data)
457 {
458 auxiliary_device_uninit(data);
459 }
460
ti_sn65dsi86_delete_aux(void * data)461 static void ti_sn65dsi86_delete_aux(void *data)
462 {
463 auxiliary_device_delete(data);
464 }
465
ti_sn65dsi86_aux_device_release(struct device * dev)466 static void ti_sn65dsi86_aux_device_release(struct device *dev)
467 {
468 struct auxiliary_device *aux = container_of(dev, struct auxiliary_device, dev);
469
470 kfree(aux);
471 }
472
ti_sn65dsi86_add_aux_device(struct ti_sn65dsi86 * pdata,struct auxiliary_device ** aux_out,const char * name)473 static int ti_sn65dsi86_add_aux_device(struct ti_sn65dsi86 *pdata,
474 struct auxiliary_device **aux_out,
475 const char *name)
476 {
477 struct device *dev = pdata->dev;
478 const struct i2c_client *client = to_i2c_client(dev);
479 struct auxiliary_device *aux;
480 int ret;
481
482 aux = kzalloc(sizeof(*aux), GFP_KERNEL);
483 if (!aux)
484 return -ENOMEM;
485
486 aux->name = name;
487 aux->id = (client->adapter->nr << 10) | client->addr;
488 aux->dev.parent = dev;
489 aux->dev.release = ti_sn65dsi86_aux_device_release;
490 device_set_of_node_from_dev(&aux->dev, dev);
491 ret = auxiliary_device_init(aux);
492 if (ret) {
493 kfree(aux);
494 return ret;
495 }
496 ret = devm_add_action_or_reset(dev, ti_sn65dsi86_uninit_aux, aux);
497 if (ret)
498 return ret;
499
500 ret = auxiliary_device_add(aux);
501 if (ret)
502 return ret;
503 ret = devm_add_action_or_reset(dev, ti_sn65dsi86_delete_aux, aux);
504 if (!ret)
505 *aux_out = aux;
506
507 return ret;
508 }
509
510 /* -----------------------------------------------------------------------------
511 * AUX Adapter
512 */
513
aux_to_ti_sn65dsi86(struct drm_dp_aux * aux)514 static struct ti_sn65dsi86 *aux_to_ti_sn65dsi86(struct drm_dp_aux *aux)
515 {
516 return container_of(aux, struct ti_sn65dsi86, aux);
517 }
518
ti_sn_aux_transfer(struct drm_dp_aux * aux,struct drm_dp_aux_msg * msg)519 static ssize_t ti_sn_aux_transfer(struct drm_dp_aux *aux,
520 struct drm_dp_aux_msg *msg)
521 {
522 struct ti_sn65dsi86 *pdata = aux_to_ti_sn65dsi86(aux);
523 u32 request = msg->request & ~(DP_AUX_I2C_MOT | DP_AUX_I2C_WRITE_STATUS_UPDATE);
524 u32 request_val = AUX_CMD_REQ(msg->request);
525 u8 *buf = msg->buffer;
526 unsigned int len = msg->size;
527 unsigned int short_len;
528 unsigned int val;
529 int ret;
530 u8 addr_len[SN_AUX_LENGTH_REG + 1 - SN_AUX_ADDR_19_16_REG];
531
532 if (len > SN_AUX_MAX_PAYLOAD_BYTES)
533 return -EINVAL;
534
535 pm_runtime_get_sync(pdata->dev);
536 mutex_lock(&pdata->comms_mutex);
537
538 /*
539 * If someone tries to do a DDC over AUX transaction before pre_enable()
540 * on a device without a dedicated reference clock then we just can't
541 * do it. Fail right away. This prevents non-refclk users from reading
542 * the EDID before enabling the panel but such is life.
543 */
544 if (!pdata->comms_enabled) {
545 ret = -EIO;
546 goto exit;
547 }
548
549 switch (request) {
550 case DP_AUX_NATIVE_WRITE:
551 case DP_AUX_I2C_WRITE:
552 case DP_AUX_NATIVE_READ:
553 case DP_AUX_I2C_READ:
554 regmap_write(pdata->regmap, SN_AUX_CMD_REG, request_val);
555 /* Assume it's good */
556 msg->reply = 0;
557 break;
558 default:
559 ret = -EINVAL;
560 goto exit;
561 }
562
563 BUILD_BUG_ON(sizeof(addr_len) != sizeof(__be32));
564 put_unaligned_be32((msg->address & SN_AUX_ADDR_MASK) << 8 | len,
565 addr_len);
566 regmap_bulk_write(pdata->regmap, SN_AUX_ADDR_19_16_REG, addr_len,
567 ARRAY_SIZE(addr_len));
568
569 if (request == DP_AUX_NATIVE_WRITE || request == DP_AUX_I2C_WRITE)
570 regmap_bulk_write(pdata->regmap, SN_AUX_WDATA_REG(0), buf, len);
571
572 /* Clear old status bits before start so we don't get confused */
573 regmap_write(pdata->regmap, SN_AUX_CMD_STATUS_REG,
574 AUX_IRQ_STATUS_NAT_I2C_FAIL |
575 AUX_IRQ_STATUS_AUX_RPLY_TOUT |
576 AUX_IRQ_STATUS_AUX_SHORT);
577
578 regmap_write(pdata->regmap, SN_AUX_CMD_REG, request_val | AUX_CMD_SEND);
579
580 /* Zero delay loop because i2c transactions are slow already */
581 ret = regmap_read_poll_timeout(pdata->regmap, SN_AUX_CMD_REG, val,
582 !(val & AUX_CMD_SEND), 0, 50 * 1000);
583 if (ret)
584 goto exit;
585
586 ret = regmap_read(pdata->regmap, SN_AUX_CMD_STATUS_REG, &val);
587 if (ret)
588 goto exit;
589
590 if (val & AUX_IRQ_STATUS_AUX_RPLY_TOUT) {
591 /*
592 * The hardware tried the message seven times per the DP spec
593 * but it hit a timeout. We ignore defers here because they're
594 * handled in hardware.
595 */
596 ret = -ETIMEDOUT;
597 goto exit;
598 }
599
600 if (val & AUX_IRQ_STATUS_AUX_SHORT) {
601 ret = regmap_read(pdata->regmap, SN_AUX_LENGTH_REG, &short_len);
602 len = min(len, short_len);
603 if (ret)
604 goto exit;
605 } else if (val & AUX_IRQ_STATUS_NAT_I2C_FAIL) {
606 switch (request) {
607 case DP_AUX_I2C_WRITE:
608 case DP_AUX_I2C_READ:
609 msg->reply |= DP_AUX_I2C_REPLY_NACK;
610 break;
611 case DP_AUX_NATIVE_READ:
612 case DP_AUX_NATIVE_WRITE:
613 msg->reply |= DP_AUX_NATIVE_REPLY_NACK;
614 break;
615 }
616 len = 0;
617 goto exit;
618 }
619
620 if (request != DP_AUX_NATIVE_WRITE && request != DP_AUX_I2C_WRITE && len != 0)
621 ret = regmap_bulk_read(pdata->regmap, SN_AUX_RDATA_REG(0), buf, len);
622
623 exit:
624 mutex_unlock(&pdata->comms_mutex);
625 pm_runtime_mark_last_busy(pdata->dev);
626 pm_runtime_put_autosuspend(pdata->dev);
627
628 if (ret)
629 return ret;
630 return len;
631 }
632
ti_sn_aux_wait_hpd_asserted(struct drm_dp_aux * aux,unsigned long wait_us)633 static int ti_sn_aux_wait_hpd_asserted(struct drm_dp_aux *aux, unsigned long wait_us)
634 {
635 /*
636 * The HPD in this chip is a bit useless (See comment in
637 * ti_sn65dsi86_enable_comms) so if our driver is expected to wait
638 * for HPD, we just assume it's asserted after the wait_us delay.
639 *
640 * In case we are asked to wait forever (wait_us=0) take conservative
641 * 500ms delay.
642 */
643 if (wait_us == 0)
644 wait_us = 500000;
645
646 usleep_range(wait_us, wait_us + 1000);
647
648 return 0;
649 }
650
ti_sn_aux_probe(struct auxiliary_device * adev,const struct auxiliary_device_id * id)651 static int ti_sn_aux_probe(struct auxiliary_device *adev,
652 const struct auxiliary_device_id *id)
653 {
654 struct ti_sn65dsi86 *pdata = dev_get_drvdata(adev->dev.parent);
655 int ret;
656
657 pdata->aux.name = "ti-sn65dsi86-aux";
658 pdata->aux.dev = &adev->dev;
659 pdata->aux.transfer = ti_sn_aux_transfer;
660 pdata->aux.wait_hpd_asserted = ti_sn_aux_wait_hpd_asserted;
661 drm_dp_aux_init(&pdata->aux);
662
663 ret = devm_of_dp_aux_populate_ep_devices(&pdata->aux);
664 if (ret)
665 return ret;
666
667 /*
668 * The eDP to MIPI bridge parts don't work until the AUX channel is
669 * setup so we don't add it in the main driver probe, we add it now.
670 */
671 return ti_sn65dsi86_add_aux_device(pdata, &pdata->bridge_aux, "bridge");
672 }
673
674 static const struct auxiliary_device_id ti_sn_aux_id_table[] = {
675 { .name = "ti_sn65dsi86.aux", },
676 {},
677 };
678
679 static struct auxiliary_driver ti_sn_aux_driver = {
680 .name = "aux",
681 .probe = ti_sn_aux_probe,
682 .id_table = ti_sn_aux_id_table,
683 };
684
685 /*------------------------------------------------------------------------------
686 * DRM Bridge
687 */
688
bridge_to_ti_sn65dsi86(struct drm_bridge * bridge)689 static struct ti_sn65dsi86 *bridge_to_ti_sn65dsi86(struct drm_bridge *bridge)
690 {
691 return container_of(bridge, struct ti_sn65dsi86, bridge);
692 }
693
ti_sn_attach_host(struct auxiliary_device * adev,struct ti_sn65dsi86 * pdata)694 static int ti_sn_attach_host(struct auxiliary_device *adev, struct ti_sn65dsi86 *pdata)
695 {
696 int val;
697 struct mipi_dsi_host *host;
698 struct mipi_dsi_device *dsi;
699 struct device *dev = pdata->dev;
700 const struct mipi_dsi_device_info info = { .type = "ti_sn_bridge",
701 .channel = 0,
702 .node = NULL,
703 };
704
705 host = of_find_mipi_dsi_host_by_node(pdata->host_node);
706 if (!host)
707 return -EPROBE_DEFER;
708
709 dsi = devm_mipi_dsi_device_register_full(&adev->dev, host, &info);
710 if (IS_ERR(dsi))
711 return PTR_ERR(dsi);
712
713 /* TODO: setting to 4 MIPI lanes always for now */
714 dsi->lanes = 4;
715 dsi->format = MIPI_DSI_FMT_RGB888;
716 dsi->mode_flags = MIPI_DSI_MODE_VIDEO;
717
718 /* check if continuous dsi clock is required or not */
719 pm_runtime_get_sync(dev);
720 regmap_read(pdata->regmap, SN_DPPLL_SRC_REG, &val);
721 pm_runtime_put_autosuspend(dev);
722 if (!(val & DPPLL_CLK_SRC_DSICLK))
723 dsi->mode_flags |= MIPI_DSI_CLOCK_NON_CONTINUOUS;
724
725 pdata->dsi = dsi;
726
727 return devm_mipi_dsi_attach(&adev->dev, dsi);
728 }
729
ti_sn_bridge_attach(struct drm_bridge * bridge,struct drm_encoder * encoder,enum drm_bridge_attach_flags flags)730 static int ti_sn_bridge_attach(struct drm_bridge *bridge,
731 struct drm_encoder *encoder,
732 enum drm_bridge_attach_flags flags)
733 {
734 struct ti_sn65dsi86 *pdata = bridge_to_ti_sn65dsi86(bridge);
735 int ret;
736
737 pdata->aux.drm_dev = bridge->dev;
738 ret = drm_dp_aux_register(&pdata->aux);
739 if (ret < 0) {
740 drm_err(bridge->dev, "Failed to register DP AUX channel: %d\n", ret);
741 return ret;
742 }
743
744 /*
745 * Attach the next bridge.
746 * We never want the next bridge to *also* create a connector.
747 */
748 ret = drm_bridge_attach(encoder, pdata->next_bridge,
749 &pdata->bridge, flags | DRM_BRIDGE_ATTACH_NO_CONNECTOR);
750 if (ret < 0)
751 goto err_initted_aux;
752
753 if (flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)
754 return 0;
755
756 pdata->connector = drm_bridge_connector_init(pdata->bridge.dev,
757 pdata->bridge.encoder);
758 if (IS_ERR(pdata->connector)) {
759 ret = PTR_ERR(pdata->connector);
760 goto err_initted_aux;
761 }
762
763 drm_connector_attach_encoder(pdata->connector, pdata->bridge.encoder);
764
765 return 0;
766
767 err_initted_aux:
768 drm_dp_aux_unregister(&pdata->aux);
769 return ret;
770 }
771
ti_sn_bridge_detach(struct drm_bridge * bridge)772 static void ti_sn_bridge_detach(struct drm_bridge *bridge)
773 {
774 drm_dp_aux_unregister(&bridge_to_ti_sn65dsi86(bridge)->aux);
775 }
776
777 static enum drm_mode_status
ti_sn_bridge_mode_valid(struct drm_bridge * bridge,const struct drm_display_info * info,const struct drm_display_mode * mode)778 ti_sn_bridge_mode_valid(struct drm_bridge *bridge,
779 const struct drm_display_info *info,
780 const struct drm_display_mode *mode)
781 {
782 /* maximum supported resolution is 4K at 60 fps */
783 if (mode->clock > 594000)
784 return MODE_CLOCK_HIGH;
785
786 /*
787 * The front and back porch registers are 8 bits, and pulse width
788 * registers are 15 bits, so reject any modes with larger periods.
789 */
790
791 if ((mode->hsync_start - mode->hdisplay) > 0xff)
792 return MODE_HBLANK_WIDE;
793
794 if ((mode->vsync_start - mode->vdisplay) > 0xff)
795 return MODE_VBLANK_WIDE;
796
797 if ((mode->hsync_end - mode->hsync_start) > 0x7fff)
798 return MODE_HSYNC_WIDE;
799
800 if ((mode->vsync_end - mode->vsync_start) > 0x7fff)
801 return MODE_VSYNC_WIDE;
802
803 if ((mode->htotal - mode->hsync_end) > 0xff)
804 return MODE_HBLANK_WIDE;
805
806 if ((mode->vtotal - mode->vsync_end) > 0xff)
807 return MODE_VBLANK_WIDE;
808
809 return MODE_OK;
810 }
811
ti_sn_bridge_atomic_disable(struct drm_bridge * bridge,struct drm_atomic_state * state)812 static void ti_sn_bridge_atomic_disable(struct drm_bridge *bridge,
813 struct drm_atomic_state *state)
814 {
815 struct ti_sn65dsi86 *pdata = bridge_to_ti_sn65dsi86(bridge);
816
817 /* disable video stream */
818 regmap_update_bits(pdata->regmap, SN_ENH_FRAME_REG, VSTREAM_ENABLE, 0);
819 }
820
ti_sn_bridge_set_dsi_rate(struct ti_sn65dsi86 * pdata,struct drm_atomic_state * state)821 static void ti_sn_bridge_set_dsi_rate(struct ti_sn65dsi86 *pdata,
822 struct drm_atomic_state *state)
823 {
824 unsigned int bit_rate_mhz, clk_freq_mhz;
825 unsigned int val;
826 struct drm_display_mode *mode =
827 get_new_adjusted_display_mode(&pdata->bridge, state);
828
829 /* set DSIA clk frequency */
830 bit_rate_mhz = (mode->clock / 1000) *
831 mipi_dsi_pixel_format_to_bpp(pdata->dsi->format);
832 clk_freq_mhz = bit_rate_mhz / (pdata->dsi->lanes * 2);
833
834 /* for each increment in val, frequency increases by 5MHz */
835 val = (MIN_DSI_CLK_FREQ_MHZ / 5) +
836 (((clk_freq_mhz - MIN_DSI_CLK_FREQ_MHZ) / 5) & 0xFF);
837 regmap_write(pdata->regmap, SN_DSIA_CLK_FREQ_REG, val);
838 }
839
ti_sn_bridge_get_bpp(struct drm_connector * connector)840 static unsigned int ti_sn_bridge_get_bpp(struct drm_connector *connector)
841 {
842 if (connector->display_info.bpc <= 6)
843 return 18;
844 else
845 return 24;
846 }
847
848 /*
849 * LUT index corresponds to register value and
850 * LUT values corresponds to dp data rate supported
851 * by the bridge in Mbps unit.
852 */
853 static const unsigned int ti_sn_bridge_dp_rate_lut[] = {
854 0, 1620, 2160, 2430, 2700, 3240, 4320, 5400
855 };
856
ti_sn_bridge_calc_min_dp_rate_idx(struct ti_sn65dsi86 * pdata,struct drm_atomic_state * state,unsigned int bpp)857 static int ti_sn_bridge_calc_min_dp_rate_idx(struct ti_sn65dsi86 *pdata,
858 struct drm_atomic_state *state,
859 unsigned int bpp)
860 {
861 unsigned int bit_rate_khz, dp_rate_mhz;
862 unsigned int i;
863 struct drm_display_mode *mode =
864 get_new_adjusted_display_mode(&pdata->bridge, state);
865
866 /* Calculate minimum bit rate based on our pixel clock. */
867 bit_rate_khz = mode->clock * bpp;
868
869 /* Calculate minimum DP data rate, taking 80% as per DP spec */
870 dp_rate_mhz = DIV_ROUND_UP(bit_rate_khz * DP_CLK_FUDGE_NUM,
871 1000 * pdata->dp_lanes * DP_CLK_FUDGE_DEN);
872
873 for (i = 1; i < ARRAY_SIZE(ti_sn_bridge_dp_rate_lut) - 1; i++)
874 if (ti_sn_bridge_dp_rate_lut[i] >= dp_rate_mhz)
875 break;
876
877 return i;
878 }
879
ti_sn_bridge_read_valid_rates(struct ti_sn65dsi86 * pdata)880 static unsigned int ti_sn_bridge_read_valid_rates(struct ti_sn65dsi86 *pdata)
881 {
882 unsigned int valid_rates = 0;
883 unsigned int rate_per_200khz;
884 unsigned int rate_mhz;
885 u8 dpcd_val;
886 int ret;
887 int i, j;
888
889 ret = drm_dp_dpcd_readb(&pdata->aux, DP_EDP_DPCD_REV, &dpcd_val);
890 if (ret != 1) {
891 DRM_DEV_ERROR(pdata->dev,
892 "Can't read eDP rev (%d), assuming 1.1\n", ret);
893 dpcd_val = DP_EDP_11;
894 }
895
896 if (dpcd_val >= DP_EDP_14) {
897 /* eDP 1.4 devices must provide a custom table */
898 __le16 sink_rates[DP_MAX_SUPPORTED_RATES];
899
900 ret = drm_dp_dpcd_read(&pdata->aux, DP_SUPPORTED_LINK_RATES,
901 sink_rates, sizeof(sink_rates));
902
903 if (ret != sizeof(sink_rates)) {
904 DRM_DEV_ERROR(pdata->dev,
905 "Can't read supported rate table (%d)\n", ret);
906
907 /* By zeroing we'll fall back to DP_MAX_LINK_RATE. */
908 memset(sink_rates, 0, sizeof(sink_rates));
909 }
910
911 for (i = 0; i < ARRAY_SIZE(sink_rates); i++) {
912 rate_per_200khz = le16_to_cpu(sink_rates[i]);
913
914 if (!rate_per_200khz)
915 break;
916
917 rate_mhz = rate_per_200khz * 200 / 1000;
918 for (j = 0;
919 j < ARRAY_SIZE(ti_sn_bridge_dp_rate_lut);
920 j++) {
921 if (ti_sn_bridge_dp_rate_lut[j] == rate_mhz)
922 valid_rates |= BIT(j);
923 }
924 }
925
926 for (i = 0; i < ARRAY_SIZE(ti_sn_bridge_dp_rate_lut); i++) {
927 if (valid_rates & BIT(i))
928 return valid_rates;
929 }
930 DRM_DEV_ERROR(pdata->dev,
931 "No matching eDP rates in table; falling back\n");
932 }
933
934 /* On older versions best we can do is use DP_MAX_LINK_RATE */
935 ret = drm_dp_dpcd_readb(&pdata->aux, DP_MAX_LINK_RATE, &dpcd_val);
936 if (ret != 1) {
937 DRM_DEV_ERROR(pdata->dev,
938 "Can't read max rate (%d); assuming 5.4 GHz\n",
939 ret);
940 dpcd_val = DP_LINK_BW_5_4;
941 }
942
943 switch (dpcd_val) {
944 default:
945 DRM_DEV_ERROR(pdata->dev,
946 "Unexpected max rate (%#x); assuming 5.4 GHz\n",
947 (int)dpcd_val);
948 fallthrough;
949 case DP_LINK_BW_5_4:
950 valid_rates |= BIT(7);
951 fallthrough;
952 case DP_LINK_BW_2_7:
953 valid_rates |= BIT(4);
954 fallthrough;
955 case DP_LINK_BW_1_62:
956 valid_rates |= BIT(1);
957 break;
958 }
959
960 return valid_rates;
961 }
962
ti_sn_bridge_set_video_timings(struct ti_sn65dsi86 * pdata,struct drm_atomic_state * state)963 static void ti_sn_bridge_set_video_timings(struct ti_sn65dsi86 *pdata,
964 struct drm_atomic_state *state)
965 {
966 struct drm_display_mode *mode =
967 get_new_adjusted_display_mode(&pdata->bridge, state);
968 u8 hsync_polarity = 0, vsync_polarity = 0;
969
970 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
971 hsync_polarity = CHA_HSYNC_POLARITY;
972 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
973 vsync_polarity = CHA_VSYNC_POLARITY;
974
975 ti_sn65dsi86_write_u16(pdata, SN_CHA_ACTIVE_LINE_LENGTH_LOW_REG,
976 mode->hdisplay);
977 ti_sn65dsi86_write_u16(pdata, SN_CHA_VERTICAL_DISPLAY_SIZE_LOW_REG,
978 mode->vdisplay);
979 regmap_write(pdata->regmap, SN_CHA_HSYNC_PULSE_WIDTH_LOW_REG,
980 (mode->hsync_end - mode->hsync_start) & 0xFF);
981 regmap_write(pdata->regmap, SN_CHA_HSYNC_PULSE_WIDTH_HIGH_REG,
982 (((mode->hsync_end - mode->hsync_start) >> 8) & 0x7F) |
983 hsync_polarity);
984 regmap_write(pdata->regmap, SN_CHA_VSYNC_PULSE_WIDTH_LOW_REG,
985 (mode->vsync_end - mode->vsync_start) & 0xFF);
986 regmap_write(pdata->regmap, SN_CHA_VSYNC_PULSE_WIDTH_HIGH_REG,
987 (((mode->vsync_end - mode->vsync_start) >> 8) & 0x7F) |
988 vsync_polarity);
989
990 regmap_write(pdata->regmap, SN_CHA_HORIZONTAL_BACK_PORCH_REG,
991 (mode->htotal - mode->hsync_end) & 0xFF);
992 regmap_write(pdata->regmap, SN_CHA_VERTICAL_BACK_PORCH_REG,
993 (mode->vtotal - mode->vsync_end) & 0xFF);
994
995 regmap_write(pdata->regmap, SN_CHA_HORIZONTAL_FRONT_PORCH_REG,
996 (mode->hsync_start - mode->hdisplay) & 0xFF);
997 regmap_write(pdata->regmap, SN_CHA_VERTICAL_FRONT_PORCH_REG,
998 (mode->vsync_start - mode->vdisplay) & 0xFF);
999
1000 usleep_range(10000, 10500); /* 10ms delay recommended by spec */
1001 }
1002
ti_sn_get_max_lanes(struct ti_sn65dsi86 * pdata)1003 static unsigned int ti_sn_get_max_lanes(struct ti_sn65dsi86 *pdata)
1004 {
1005 u8 data;
1006 int ret;
1007
1008 ret = drm_dp_dpcd_readb(&pdata->aux, DP_MAX_LANE_COUNT, &data);
1009 if (ret != 1) {
1010 DRM_DEV_ERROR(pdata->dev,
1011 "Can't read lane count (%d); assuming 4\n", ret);
1012 return 4;
1013 }
1014
1015 return data & DP_LANE_COUNT_MASK;
1016 }
1017
ti_sn_link_training(struct ti_sn65dsi86 * pdata,int dp_rate_idx,const char ** last_err_str)1018 static int ti_sn_link_training(struct ti_sn65dsi86 *pdata, int dp_rate_idx,
1019 const char **last_err_str)
1020 {
1021 unsigned int val;
1022 int ret;
1023 int i;
1024
1025 /* set dp clk frequency value */
1026 regmap_update_bits(pdata->regmap, SN_DATARATE_CONFIG_REG,
1027 DP_DATARATE_MASK, DP_DATARATE(dp_rate_idx));
1028
1029 /* enable DP PLL */
1030 regmap_write(pdata->regmap, SN_PLL_ENABLE_REG, 1);
1031
1032 ret = regmap_read_poll_timeout(pdata->regmap, SN_DPPLL_SRC_REG, val,
1033 val & DPPLL_SRC_DP_PLL_LOCK, 1000,
1034 50 * 1000);
1035 if (ret) {
1036 *last_err_str = "DP_PLL_LOCK polling failed";
1037 goto exit;
1038 }
1039
1040 /*
1041 * We'll try to link train several times. As part of link training
1042 * the bridge chip will write DP_SET_POWER_D0 to DP_SET_POWER. If
1043 * the panel isn't ready quite it might respond NAK here which means
1044 * we need to try again.
1045 */
1046 for (i = 0; i < SN_LINK_TRAINING_TRIES; i++) {
1047 /* Semi auto link training mode */
1048 regmap_write(pdata->regmap, SN_ML_TX_MODE_REG, 0x0A);
1049 ret = regmap_read_poll_timeout(pdata->regmap, SN_ML_TX_MODE_REG, val,
1050 val == ML_TX_MAIN_LINK_OFF ||
1051 val == ML_TX_NORMAL_MODE, 1000,
1052 500 * 1000);
1053 if (ret) {
1054 *last_err_str = "Training complete polling failed";
1055 } else if (val == ML_TX_MAIN_LINK_OFF) {
1056 *last_err_str = "Link training failed, link is off";
1057 ret = -EIO;
1058 continue;
1059 }
1060
1061 break;
1062 }
1063
1064 /* If we saw quite a few retries, add a note about it */
1065 if (!ret && i > SN_LINK_TRAINING_TRIES / 2)
1066 DRM_DEV_INFO(pdata->dev, "Link training needed %d retries\n", i);
1067
1068 exit:
1069 /* Disable the PLL if we failed */
1070 if (ret)
1071 regmap_write(pdata->regmap, SN_PLL_ENABLE_REG, 0);
1072
1073 return ret;
1074 }
1075
ti_sn_bridge_atomic_enable(struct drm_bridge * bridge,struct drm_atomic_state * state)1076 static void ti_sn_bridge_atomic_enable(struct drm_bridge *bridge,
1077 struct drm_atomic_state *state)
1078 {
1079 struct ti_sn65dsi86 *pdata = bridge_to_ti_sn65dsi86(bridge);
1080 struct drm_connector *connector;
1081 const char *last_err_str = "No supported DP rate";
1082 unsigned int valid_rates;
1083 int dp_rate_idx;
1084 unsigned int val;
1085 int ret = -EINVAL;
1086 int max_dp_lanes;
1087 unsigned int bpp;
1088
1089 connector = drm_atomic_get_new_connector_for_encoder(state,
1090 bridge->encoder);
1091 if (!connector) {
1092 dev_err_ratelimited(pdata->dev, "Could not get the connector\n");
1093 return;
1094 }
1095
1096 max_dp_lanes = ti_sn_get_max_lanes(pdata);
1097 pdata->dp_lanes = min(pdata->dp_lanes, max_dp_lanes);
1098
1099 /* DSI_A lane config */
1100 val = CHA_DSI_LANES(SN_MAX_DP_LANES - pdata->dsi->lanes);
1101 regmap_update_bits(pdata->regmap, SN_DSI_LANES_REG,
1102 CHA_DSI_LANES_MASK, val);
1103
1104 regmap_write(pdata->regmap, SN_LN_ASSIGN_REG, pdata->ln_assign);
1105 regmap_update_bits(pdata->regmap, SN_ENH_FRAME_REG, LN_POLRS_MASK,
1106 pdata->ln_polrs << LN_POLRS_OFFSET);
1107
1108 /* set dsi clk frequency value */
1109 ti_sn_bridge_set_dsi_rate(pdata, state);
1110
1111 /*
1112 * The SN65DSI86 only supports ASSR Display Authentication method and
1113 * this method is enabled for eDP panels. An eDP panel must support this
1114 * authentication method. We need to enable this method in the eDP panel
1115 * at DisplayPort address 0x0010A prior to link training.
1116 *
1117 * As only ASSR is supported by SN65DSI86, for full DisplayPort displays
1118 * we need to disable the scrambler.
1119 */
1120 if (pdata->bridge.type == DRM_MODE_CONNECTOR_eDP) {
1121 drm_dp_dpcd_writeb(&pdata->aux, DP_EDP_CONFIGURATION_SET,
1122 DP_ALTERNATE_SCRAMBLER_RESET_ENABLE);
1123
1124 regmap_update_bits(pdata->regmap, SN_TRAINING_SETTING_REG,
1125 SCRAMBLE_DISABLE, 0);
1126 } else {
1127 regmap_update_bits(pdata->regmap, SN_TRAINING_SETTING_REG,
1128 SCRAMBLE_DISABLE, SCRAMBLE_DISABLE);
1129 }
1130
1131 bpp = ti_sn_bridge_get_bpp(connector);
1132 /* Set the DP output format (18 bpp or 24 bpp) */
1133 val = bpp == 18 ? BPP_18_RGB : 0;
1134 regmap_update_bits(pdata->regmap, SN_DATA_FORMAT_REG, BPP_18_RGB, val);
1135
1136 /* DP lane config */
1137 val = DP_NUM_LANES(min(pdata->dp_lanes, 3));
1138 regmap_update_bits(pdata->regmap, SN_SSC_CONFIG_REG, DP_NUM_LANES_MASK,
1139 val);
1140
1141 valid_rates = ti_sn_bridge_read_valid_rates(pdata);
1142
1143 /* Train until we run out of rates */
1144 for (dp_rate_idx = ti_sn_bridge_calc_min_dp_rate_idx(pdata, state, bpp);
1145 dp_rate_idx < ARRAY_SIZE(ti_sn_bridge_dp_rate_lut);
1146 dp_rate_idx++) {
1147 if (!(valid_rates & BIT(dp_rate_idx)))
1148 continue;
1149
1150 ret = ti_sn_link_training(pdata, dp_rate_idx, &last_err_str);
1151 if (!ret)
1152 break;
1153 }
1154 if (ret) {
1155 DRM_DEV_ERROR(pdata->dev, "%s (%d)\n", last_err_str, ret);
1156 return;
1157 }
1158
1159 /* config video parameters */
1160 ti_sn_bridge_set_video_timings(pdata, state);
1161
1162 /* enable video stream */
1163 regmap_update_bits(pdata->regmap, SN_ENH_FRAME_REG, VSTREAM_ENABLE,
1164 VSTREAM_ENABLE);
1165 }
1166
ti_sn_bridge_atomic_pre_enable(struct drm_bridge * bridge,struct drm_atomic_state * state)1167 static void ti_sn_bridge_atomic_pre_enable(struct drm_bridge *bridge,
1168 struct drm_atomic_state *state)
1169 {
1170 struct ti_sn65dsi86 *pdata = bridge_to_ti_sn65dsi86(bridge);
1171
1172 pm_runtime_get_sync(pdata->dev);
1173
1174 if (!pdata->refclk)
1175 ti_sn65dsi86_enable_comms(pdata, state);
1176
1177 /* td7: min 100 us after enable before DSI data */
1178 usleep_range(100, 110);
1179 }
1180
ti_sn_bridge_atomic_post_disable(struct drm_bridge * bridge,struct drm_atomic_state * state)1181 static void ti_sn_bridge_atomic_post_disable(struct drm_bridge *bridge,
1182 struct drm_atomic_state *state)
1183 {
1184 struct ti_sn65dsi86 *pdata = bridge_to_ti_sn65dsi86(bridge);
1185
1186 /* semi auto link training mode OFF */
1187 regmap_write(pdata->regmap, SN_ML_TX_MODE_REG, 0);
1188 /* Num lanes to 0 as per power sequencing in data sheet */
1189 regmap_update_bits(pdata->regmap, SN_SSC_CONFIG_REG, DP_NUM_LANES_MASK, 0);
1190 /* disable DP PLL */
1191 regmap_write(pdata->regmap, SN_PLL_ENABLE_REG, 0);
1192
1193 if (!pdata->refclk)
1194 ti_sn65dsi86_disable_comms(pdata);
1195
1196 pm_runtime_put_sync(pdata->dev);
1197 }
1198
ti_sn_bridge_detect(struct drm_bridge * bridge)1199 static enum drm_connector_status ti_sn_bridge_detect(struct drm_bridge *bridge)
1200 {
1201 struct ti_sn65dsi86 *pdata = bridge_to_ti_sn65dsi86(bridge);
1202 int val = 0;
1203
1204 /*
1205 * Runtime reference is grabbed in ti_sn_bridge_hpd_enable()
1206 * as the chip won't report HPD just after being powered on.
1207 * HPD_DEBOUNCED_STATE reflects correct state only after the
1208 * debounce time (~100-400 ms).
1209 */
1210
1211 regmap_read(pdata->regmap, SN_HPD_DISABLE_REG, &val);
1212
1213 return val & HPD_DEBOUNCED_STATE ? connector_status_connected
1214 : connector_status_disconnected;
1215 }
1216
ti_sn_bridge_edid_read(struct drm_bridge * bridge,struct drm_connector * connector)1217 static const struct drm_edid *ti_sn_bridge_edid_read(struct drm_bridge *bridge,
1218 struct drm_connector *connector)
1219 {
1220 struct ti_sn65dsi86 *pdata = bridge_to_ti_sn65dsi86(bridge);
1221
1222 return drm_edid_read_ddc(connector, &pdata->aux.ddc);
1223 }
1224
ti_sn65dsi86_debugfs_init(struct drm_bridge * bridge,struct dentry * root)1225 static void ti_sn65dsi86_debugfs_init(struct drm_bridge *bridge, struct dentry *root)
1226 {
1227 struct ti_sn65dsi86 *pdata = bridge_to_ti_sn65dsi86(bridge);
1228 struct dentry *debugfs;
1229
1230 debugfs = debugfs_create_dir(dev_name(pdata->dev), root);
1231 debugfs_create_file("status", 0600, debugfs, pdata, &status_fops);
1232 }
1233
ti_sn_bridge_hpd_enable(struct drm_bridge * bridge)1234 static void ti_sn_bridge_hpd_enable(struct drm_bridge *bridge)
1235 {
1236 struct ti_sn65dsi86 *pdata = bridge_to_ti_sn65dsi86(bridge);
1237
1238 /*
1239 * Device needs to be powered on before reading the HPD state
1240 * for reliable hpd detection in ti_sn_bridge_detect() due to
1241 * the high debounce time.
1242 */
1243
1244 pm_runtime_get_sync(pdata->dev);
1245 }
1246
ti_sn_bridge_hpd_disable(struct drm_bridge * bridge)1247 static void ti_sn_bridge_hpd_disable(struct drm_bridge *bridge)
1248 {
1249 struct ti_sn65dsi86 *pdata = bridge_to_ti_sn65dsi86(bridge);
1250
1251 pm_runtime_put_autosuspend(pdata->dev);
1252 }
1253
1254 static const struct drm_bridge_funcs ti_sn_bridge_funcs = {
1255 .attach = ti_sn_bridge_attach,
1256 .detach = ti_sn_bridge_detach,
1257 .mode_valid = ti_sn_bridge_mode_valid,
1258 .edid_read = ti_sn_bridge_edid_read,
1259 .detect = ti_sn_bridge_detect,
1260 .atomic_pre_enable = ti_sn_bridge_atomic_pre_enable,
1261 .atomic_enable = ti_sn_bridge_atomic_enable,
1262 .atomic_disable = ti_sn_bridge_atomic_disable,
1263 .atomic_post_disable = ti_sn_bridge_atomic_post_disable,
1264 .atomic_reset = drm_atomic_helper_bridge_reset,
1265 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
1266 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
1267 .debugfs_init = ti_sn65dsi86_debugfs_init,
1268 .hpd_enable = ti_sn_bridge_hpd_enable,
1269 .hpd_disable = ti_sn_bridge_hpd_disable,
1270 };
1271
ti_sn_bridge_parse_lanes(struct ti_sn65dsi86 * pdata,struct device_node * np)1272 static void ti_sn_bridge_parse_lanes(struct ti_sn65dsi86 *pdata,
1273 struct device_node *np)
1274 {
1275 u32 lane_assignments[SN_MAX_DP_LANES] = { 0, 1, 2, 3 };
1276 u32 lane_polarities[SN_MAX_DP_LANES] = { };
1277 struct device_node *endpoint;
1278 u8 ln_assign = 0;
1279 u8 ln_polrs = 0;
1280 int dp_lanes;
1281 int i;
1282
1283 /*
1284 * Read config from the device tree about lane remapping and lane
1285 * polarities. These are optional and we assume identity map and
1286 * normal polarity if nothing is specified. It's OK to specify just
1287 * data-lanes but not lane-polarities but not vice versa.
1288 *
1289 * Error checking is light (we just make sure we don't crash or
1290 * buffer overrun) and we assume dts is well formed and specifying
1291 * mappings that the hardware supports.
1292 */
1293 endpoint = of_graph_get_endpoint_by_regs(np, 1, -1);
1294 dp_lanes = drm_of_get_data_lanes_count(endpoint, 1, SN_MAX_DP_LANES);
1295 if (dp_lanes > 0) {
1296 of_property_read_u32_array(endpoint, "data-lanes",
1297 lane_assignments, dp_lanes);
1298 of_property_read_u32_array(endpoint, "lane-polarities",
1299 lane_polarities, dp_lanes);
1300 } else {
1301 dp_lanes = SN_MAX_DP_LANES;
1302 }
1303 of_node_put(endpoint);
1304
1305 /*
1306 * Convert into register format. Loop over all lanes even if
1307 * data-lanes had fewer elements so that we nicely initialize
1308 * the LN_ASSIGN register.
1309 */
1310 for (i = SN_MAX_DP_LANES - 1; i >= 0; i--) {
1311 ln_assign = ln_assign << LN_ASSIGN_WIDTH | lane_assignments[i];
1312 ln_polrs = ln_polrs << 1 | lane_polarities[i];
1313 }
1314
1315 /* Stash in our struct for when we power on */
1316 pdata->dp_lanes = dp_lanes;
1317 pdata->ln_assign = ln_assign;
1318 pdata->ln_polrs = ln_polrs;
1319 }
1320
ti_sn_bridge_parse_dsi_host(struct ti_sn65dsi86 * pdata)1321 static int ti_sn_bridge_parse_dsi_host(struct ti_sn65dsi86 *pdata)
1322 {
1323 struct device_node *np = pdata->dev->of_node;
1324
1325 pdata->host_node = of_graph_get_remote_node(np, 0, 0);
1326
1327 if (!pdata->host_node) {
1328 DRM_ERROR("remote dsi host node not found\n");
1329 return -ENODEV;
1330 }
1331
1332 return 0;
1333 }
1334
ti_sn_bridge_probe(struct auxiliary_device * adev,const struct auxiliary_device_id * id)1335 static int ti_sn_bridge_probe(struct auxiliary_device *adev,
1336 const struct auxiliary_device_id *id)
1337 {
1338 struct ti_sn65dsi86 *pdata = dev_get_drvdata(adev->dev.parent);
1339 struct device_node *np = pdata->dev->of_node;
1340 int ret;
1341
1342 pdata->next_bridge = devm_drm_of_get_bridge(&adev->dev, np, 1, 0);
1343 if (IS_ERR(pdata->next_bridge))
1344 return dev_err_probe(&adev->dev, PTR_ERR(pdata->next_bridge),
1345 "failed to create panel bridge\n");
1346
1347 ti_sn_bridge_parse_lanes(pdata, np);
1348
1349 ret = ti_sn_bridge_parse_dsi_host(pdata);
1350 if (ret)
1351 return ret;
1352
1353 pdata->bridge.of_node = np;
1354 pdata->bridge.type = pdata->next_bridge->type == DRM_MODE_CONNECTOR_DisplayPort
1355 ? DRM_MODE_CONNECTOR_DisplayPort : DRM_MODE_CONNECTOR_eDP;
1356
1357 if (pdata->bridge.type == DRM_MODE_CONNECTOR_DisplayPort) {
1358 pdata->bridge.ops = DRM_BRIDGE_OP_EDID | DRM_BRIDGE_OP_DETECT |
1359 DRM_BRIDGE_OP_HPD;
1360 /*
1361 * If comms were already enabled they would have been enabled
1362 * with the wrong value of HPD_DISABLE. Update it now. Comms
1363 * could be enabled if anyone is holding a pm_runtime reference
1364 * (like if a GPIO is in use). Note that in most cases nobody
1365 * is doing AUX channel xfers before the bridge is added so
1366 * HPD doesn't _really_ matter then. The only exception is in
1367 * the eDP case where the panel wants to read the EDID before
1368 * the bridge is added. We always consistently have HPD disabled
1369 * for eDP.
1370 */
1371 mutex_lock(&pdata->comms_mutex);
1372 if (pdata->comms_enabled)
1373 regmap_update_bits(pdata->regmap, SN_HPD_DISABLE_REG,
1374 HPD_DISABLE, 0);
1375 mutex_unlock(&pdata->comms_mutex);
1376 };
1377
1378 drm_bridge_add(&pdata->bridge);
1379
1380 ret = ti_sn_attach_host(adev, pdata);
1381 if (ret) {
1382 dev_err_probe(&adev->dev, ret, "failed to attach dsi host\n");
1383 goto err_remove_bridge;
1384 }
1385
1386 return 0;
1387
1388 err_remove_bridge:
1389 drm_bridge_remove(&pdata->bridge);
1390 return ret;
1391 }
1392
ti_sn_bridge_remove(struct auxiliary_device * adev)1393 static void ti_sn_bridge_remove(struct auxiliary_device *adev)
1394 {
1395 struct ti_sn65dsi86 *pdata = dev_get_drvdata(adev->dev.parent);
1396
1397 if (!pdata)
1398 return;
1399
1400 drm_bridge_remove(&pdata->bridge);
1401
1402 of_node_put(pdata->host_node);
1403 }
1404
1405 static const struct auxiliary_device_id ti_sn_bridge_id_table[] = {
1406 { .name = "ti_sn65dsi86.bridge", },
1407 {},
1408 };
1409
1410 static struct auxiliary_driver ti_sn_bridge_driver = {
1411 .name = "bridge",
1412 .probe = ti_sn_bridge_probe,
1413 .remove = ti_sn_bridge_remove,
1414 .id_table = ti_sn_bridge_id_table,
1415 };
1416
1417 /* -----------------------------------------------------------------------------
1418 * PWM Controller
1419 */
1420 #if IS_REACHABLE(CONFIG_PWM)
ti_sn_pwm_pin_request(struct ti_sn65dsi86 * pdata)1421 static int ti_sn_pwm_pin_request(struct ti_sn65dsi86 *pdata)
1422 {
1423 return atomic_xchg(&pdata->pwm_pin_busy, 1) ? -EBUSY : 0;
1424 }
1425
ti_sn_pwm_pin_release(struct ti_sn65dsi86 * pdata)1426 static void ti_sn_pwm_pin_release(struct ti_sn65dsi86 *pdata)
1427 {
1428 atomic_set(&pdata->pwm_pin_busy, 0);
1429 }
1430
pwm_chip_to_ti_sn_bridge(struct pwm_chip * chip)1431 static struct ti_sn65dsi86 *pwm_chip_to_ti_sn_bridge(struct pwm_chip *chip)
1432 {
1433 return pwmchip_get_drvdata(chip);
1434 }
1435
ti_sn_pwm_request(struct pwm_chip * chip,struct pwm_device * pwm)1436 static int ti_sn_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm)
1437 {
1438 struct ti_sn65dsi86 *pdata = pwm_chip_to_ti_sn_bridge(chip);
1439
1440 return ti_sn_pwm_pin_request(pdata);
1441 }
1442
ti_sn_pwm_free(struct pwm_chip * chip,struct pwm_device * pwm)1443 static void ti_sn_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
1444 {
1445 struct ti_sn65dsi86 *pdata = pwm_chip_to_ti_sn_bridge(chip);
1446
1447 ti_sn_pwm_pin_release(pdata);
1448 }
1449
1450 /*
1451 * Limitations:
1452 * - The PWM signal is not driven when the chip is powered down, or in its
1453 * reset state and the driver does not implement the "suspend state"
1454 * described in the documentation. In order to save power, state->enabled is
1455 * interpreted as denoting if the signal is expected to be valid, and is used
1456 * to determine if the chip needs to be kept powered.
1457 * - Changing both period and duty_cycle is not done atomically, neither is the
1458 * multi-byte register updates, so the output might briefly be undefined
1459 * during update.
1460 */
ti_sn_pwm_apply(struct pwm_chip * chip,struct pwm_device * pwm,const struct pwm_state * state)1461 static int ti_sn_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
1462 const struct pwm_state *state)
1463 {
1464 struct ti_sn65dsi86 *pdata = pwm_chip_to_ti_sn_bridge(chip);
1465 unsigned int pwm_en_inv;
1466 unsigned int backlight;
1467 unsigned int pre_div;
1468 unsigned int scale;
1469 u64 period_max;
1470 u64 period;
1471 int ret;
1472
1473 if (!pdata->pwm_enabled) {
1474 ret = pm_runtime_resume_and_get(pwmchip_parent(chip));
1475 if (ret < 0)
1476 return ret;
1477 }
1478
1479 if (state->enabled) {
1480 if (!pdata->pwm_enabled) {
1481 /*
1482 * The chip might have been powered down while we
1483 * didn't hold a PM runtime reference, so mux in the
1484 * PWM function on the GPIO pin again.
1485 */
1486 ret = regmap_update_bits(pdata->regmap, SN_GPIO_CTRL_REG,
1487 SN_GPIO_MUX_MASK << (2 * SN_PWM_GPIO_IDX),
1488 SN_GPIO_MUX_SPECIAL << (2 * SN_PWM_GPIO_IDX));
1489 if (ret) {
1490 dev_err(pwmchip_parent(chip), "failed to mux in PWM function\n");
1491 goto out;
1492 }
1493 }
1494
1495 /*
1496 * Per the datasheet the PWM frequency is given by:
1497 *
1498 * REFCLK_FREQ
1499 * PWM_FREQ = -----------------------------------
1500 * PWM_PRE_DIV * BACKLIGHT_SCALE + 1
1501 *
1502 * However, after careful review the author is convinced that
1503 * the documentation has lost some parenthesis around
1504 * "BACKLIGHT_SCALE + 1".
1505 *
1506 * With the period T_pwm = 1/PWM_FREQ this can be written:
1507 *
1508 * T_pwm * REFCLK_FREQ = PWM_PRE_DIV * (BACKLIGHT_SCALE + 1)
1509 *
1510 * In order to keep BACKLIGHT_SCALE within its 16 bits,
1511 * PWM_PRE_DIV must be:
1512 *
1513 * T_pwm * REFCLK_FREQ
1514 * PWM_PRE_DIV >= -------------------------
1515 * BACKLIGHT_SCALE_MAX + 1
1516 *
1517 * To simplify the search and to favour higher resolution of
1518 * the duty cycle over accuracy of the period, the lowest
1519 * possible PWM_PRE_DIV is used. Finally the scale is
1520 * calculated as:
1521 *
1522 * T_pwm * REFCLK_FREQ
1523 * BACKLIGHT_SCALE = ---------------------- - 1
1524 * PWM_PRE_DIV
1525 *
1526 * Here T_pwm is represented in seconds, so appropriate scaling
1527 * to nanoseconds is necessary.
1528 */
1529
1530 /* Minimum T_pwm is 1 / REFCLK_FREQ */
1531 if (state->period <= NSEC_PER_SEC / pdata->pwm_refclk_freq) {
1532 ret = -EINVAL;
1533 goto out;
1534 }
1535
1536 /*
1537 * Maximum T_pwm is 255 * (65535 + 1) / REFCLK_FREQ
1538 * Limit period to this to avoid overflows
1539 */
1540 period_max = div_u64((u64)NSEC_PER_SEC * 255 * (65535 + 1),
1541 pdata->pwm_refclk_freq);
1542 period = min(state->period, period_max);
1543
1544 pre_div = DIV64_U64_ROUND_UP(period * pdata->pwm_refclk_freq,
1545 (u64)NSEC_PER_SEC * (BACKLIGHT_SCALE_MAX + 1));
1546 scale = div64_u64(period * pdata->pwm_refclk_freq, (u64)NSEC_PER_SEC * pre_div) - 1;
1547
1548 /*
1549 * The documentation has the duty ratio given as:
1550 *
1551 * duty BACKLIGHT
1552 * ------- = ---------------------
1553 * period BACKLIGHT_SCALE + 1
1554 *
1555 * Solve for BACKLIGHT, substituting BACKLIGHT_SCALE according
1556 * to definition above and adjusting for nanosecond
1557 * representation of duty cycle gives us:
1558 */
1559 backlight = div64_u64(state->duty_cycle * pdata->pwm_refclk_freq,
1560 (u64)NSEC_PER_SEC * pre_div);
1561 if (backlight > scale)
1562 backlight = scale;
1563
1564 ret = regmap_write(pdata->regmap, SN_PWM_PRE_DIV_REG, pre_div);
1565 if (ret) {
1566 dev_err(pwmchip_parent(chip), "failed to update PWM_PRE_DIV\n");
1567 goto out;
1568 }
1569
1570 ti_sn65dsi86_write_u16(pdata, SN_BACKLIGHT_SCALE_REG, scale);
1571 ti_sn65dsi86_write_u16(pdata, SN_BACKLIGHT_REG, backlight);
1572 }
1573
1574 pwm_en_inv = FIELD_PREP(SN_PWM_EN_MASK, state->enabled) |
1575 FIELD_PREP(SN_PWM_INV_MASK, state->polarity == PWM_POLARITY_INVERSED);
1576 ret = regmap_write(pdata->regmap, SN_PWM_EN_INV_REG, pwm_en_inv);
1577 if (ret) {
1578 dev_err(pwmchip_parent(chip), "failed to update PWM_EN/PWM_INV\n");
1579 goto out;
1580 }
1581
1582 pdata->pwm_enabled = state->enabled;
1583 out:
1584
1585 if (!pdata->pwm_enabled)
1586 pm_runtime_put_sync(pwmchip_parent(chip));
1587
1588 return ret;
1589 }
1590
ti_sn_pwm_get_state(struct pwm_chip * chip,struct pwm_device * pwm,struct pwm_state * state)1591 static int ti_sn_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
1592 struct pwm_state *state)
1593 {
1594 struct ti_sn65dsi86 *pdata = pwm_chip_to_ti_sn_bridge(chip);
1595 unsigned int pwm_en_inv;
1596 unsigned int pre_div;
1597 u16 backlight;
1598 u16 scale;
1599 int ret;
1600
1601 ret = regmap_read(pdata->regmap, SN_PWM_EN_INV_REG, &pwm_en_inv);
1602 if (ret)
1603 return ret;
1604
1605 ret = ti_sn65dsi86_read_u16(pdata, SN_BACKLIGHT_SCALE_REG, &scale);
1606 if (ret)
1607 return ret;
1608
1609 ret = ti_sn65dsi86_read_u16(pdata, SN_BACKLIGHT_REG, &backlight);
1610 if (ret)
1611 return ret;
1612
1613 ret = regmap_read(pdata->regmap, SN_PWM_PRE_DIV_REG, &pre_div);
1614 if (ret)
1615 return ret;
1616
1617 state->enabled = FIELD_GET(SN_PWM_EN_MASK, pwm_en_inv);
1618 if (FIELD_GET(SN_PWM_INV_MASK, pwm_en_inv))
1619 state->polarity = PWM_POLARITY_INVERSED;
1620 else
1621 state->polarity = PWM_POLARITY_NORMAL;
1622
1623 state->period = DIV_ROUND_UP_ULL((u64)NSEC_PER_SEC * pre_div * (scale + 1),
1624 pdata->pwm_refclk_freq);
1625 state->duty_cycle = DIV_ROUND_UP_ULL((u64)NSEC_PER_SEC * pre_div * backlight,
1626 pdata->pwm_refclk_freq);
1627
1628 if (state->duty_cycle > state->period)
1629 state->duty_cycle = state->period;
1630
1631 return 0;
1632 }
1633
1634 static const struct pwm_ops ti_sn_pwm_ops = {
1635 .request = ti_sn_pwm_request,
1636 .free = ti_sn_pwm_free,
1637 .apply = ti_sn_pwm_apply,
1638 .get_state = ti_sn_pwm_get_state,
1639 };
1640
ti_sn_pwm_probe(struct auxiliary_device * adev,const struct auxiliary_device_id * id)1641 static int ti_sn_pwm_probe(struct auxiliary_device *adev,
1642 const struct auxiliary_device_id *id)
1643 {
1644 struct pwm_chip *chip;
1645 struct ti_sn65dsi86 *pdata = dev_get_drvdata(adev->dev.parent);
1646
1647 pdata->pchip = chip = devm_pwmchip_alloc(&adev->dev, 1, 0);
1648 if (IS_ERR(chip))
1649 return PTR_ERR(chip);
1650
1651 pwmchip_set_drvdata(chip, pdata);
1652
1653 chip->ops = &ti_sn_pwm_ops;
1654 chip->of_xlate = of_pwm_single_xlate;
1655
1656 devm_pm_runtime_enable(&adev->dev);
1657
1658 return pwmchip_add(chip);
1659 }
1660
ti_sn_pwm_remove(struct auxiliary_device * adev)1661 static void ti_sn_pwm_remove(struct auxiliary_device *adev)
1662 {
1663 struct ti_sn65dsi86 *pdata = dev_get_drvdata(adev->dev.parent);
1664
1665 pwmchip_remove(pdata->pchip);
1666
1667 if (pdata->pwm_enabled)
1668 pm_runtime_put_sync(&adev->dev);
1669 }
1670
1671 static const struct auxiliary_device_id ti_sn_pwm_id_table[] = {
1672 { .name = "ti_sn65dsi86.pwm", },
1673 {},
1674 };
1675
1676 static struct auxiliary_driver ti_sn_pwm_driver = {
1677 .name = "pwm",
1678 .probe = ti_sn_pwm_probe,
1679 .remove = ti_sn_pwm_remove,
1680 .id_table = ti_sn_pwm_id_table,
1681 };
1682
ti_sn_pwm_register(void)1683 static int __init ti_sn_pwm_register(void)
1684 {
1685 return auxiliary_driver_register(&ti_sn_pwm_driver);
1686 }
1687
ti_sn_pwm_unregister(void)1688 static void ti_sn_pwm_unregister(void)
1689 {
1690 auxiliary_driver_unregister(&ti_sn_pwm_driver);
1691 }
1692
1693 #else
ti_sn_pwm_pin_request(struct ti_sn65dsi86 * pdata)1694 static inline int __maybe_unused ti_sn_pwm_pin_request(struct ti_sn65dsi86 *pdata) { return 0; }
ti_sn_pwm_pin_release(struct ti_sn65dsi86 * pdata)1695 static inline void __maybe_unused ti_sn_pwm_pin_release(struct ti_sn65dsi86 *pdata) {}
1696
ti_sn_pwm_register(void)1697 static inline int ti_sn_pwm_register(void) { return 0; }
ti_sn_pwm_unregister(void)1698 static inline void ti_sn_pwm_unregister(void) {}
1699 #endif
1700
1701 /* -----------------------------------------------------------------------------
1702 * GPIO Controller
1703 */
1704 #if defined(CONFIG_OF_GPIO)
1705
tn_sn_bridge_of_xlate(struct gpio_chip * chip,const struct of_phandle_args * gpiospec,u32 * flags)1706 static int tn_sn_bridge_of_xlate(struct gpio_chip *chip,
1707 const struct of_phandle_args *gpiospec,
1708 u32 *flags)
1709 {
1710 if (WARN_ON(gpiospec->args_count < chip->of_gpio_n_cells))
1711 return -EINVAL;
1712
1713 if (gpiospec->args[0] > chip->ngpio || gpiospec->args[0] < 1)
1714 return -EINVAL;
1715
1716 if (flags)
1717 *flags = gpiospec->args[1];
1718
1719 return gpiospec->args[0] - SN_GPIO_PHYSICAL_OFFSET;
1720 }
1721
ti_sn_bridge_gpio_get_direction(struct gpio_chip * chip,unsigned int offset)1722 static int ti_sn_bridge_gpio_get_direction(struct gpio_chip *chip,
1723 unsigned int offset)
1724 {
1725 struct ti_sn65dsi86 *pdata = gpiochip_get_data(chip);
1726
1727 /*
1728 * We already have to keep track of the direction because we use
1729 * that to figure out whether we've powered the device. We can
1730 * just return that rather than (maybe) powering up the device
1731 * to ask its direction.
1732 */
1733 return test_bit(offset, pdata->gchip_output) ?
1734 GPIO_LINE_DIRECTION_OUT : GPIO_LINE_DIRECTION_IN;
1735 }
1736
ti_sn_bridge_gpio_get(struct gpio_chip * chip,unsigned int offset)1737 static int ti_sn_bridge_gpio_get(struct gpio_chip *chip, unsigned int offset)
1738 {
1739 struct ti_sn65dsi86 *pdata = gpiochip_get_data(chip);
1740 unsigned int val;
1741 int ret;
1742
1743 /*
1744 * When the pin is an input we don't forcibly keep the bridge
1745 * powered--we just power it on to read the pin. NOTE: part of
1746 * the reason this works is that the bridge defaults (when
1747 * powered back on) to all 4 GPIOs being configured as GPIO input.
1748 * Also note that if something else is keeping the chip powered the
1749 * pm_runtime functions are lightweight increments of a refcount.
1750 */
1751 pm_runtime_get_sync(pdata->dev);
1752 ret = regmap_read(pdata->regmap, SN_GPIO_IO_REG, &val);
1753 pm_runtime_put_autosuspend(pdata->dev);
1754
1755 if (ret)
1756 return ret;
1757
1758 return !!(val & BIT(SN_GPIO_INPUT_SHIFT + offset));
1759 }
1760
ti_sn_bridge_gpio_set(struct gpio_chip * chip,unsigned int offset,int val)1761 static void ti_sn_bridge_gpio_set(struct gpio_chip *chip, unsigned int offset,
1762 int val)
1763 {
1764 struct ti_sn65dsi86 *pdata = gpiochip_get_data(chip);
1765 int ret;
1766
1767 if (!test_bit(offset, pdata->gchip_output)) {
1768 dev_err(pdata->dev, "Ignoring GPIO set while input\n");
1769 return;
1770 }
1771
1772 val &= 1;
1773 ret = regmap_update_bits(pdata->regmap, SN_GPIO_IO_REG,
1774 BIT(SN_GPIO_OUTPUT_SHIFT + offset),
1775 val << (SN_GPIO_OUTPUT_SHIFT + offset));
1776 if (ret)
1777 dev_warn(pdata->dev,
1778 "Failed to set bridge GPIO %u: %d\n", offset, ret);
1779 }
1780
ti_sn_bridge_gpio_direction_input(struct gpio_chip * chip,unsigned int offset)1781 static int ti_sn_bridge_gpio_direction_input(struct gpio_chip *chip,
1782 unsigned int offset)
1783 {
1784 struct ti_sn65dsi86 *pdata = gpiochip_get_data(chip);
1785 int shift = offset * 2;
1786 int ret;
1787
1788 if (!test_and_clear_bit(offset, pdata->gchip_output))
1789 return 0;
1790
1791 ret = regmap_update_bits(pdata->regmap, SN_GPIO_CTRL_REG,
1792 SN_GPIO_MUX_MASK << shift,
1793 SN_GPIO_MUX_INPUT << shift);
1794 if (ret) {
1795 set_bit(offset, pdata->gchip_output);
1796 return ret;
1797 }
1798
1799 /*
1800 * NOTE: if nobody else is powering the device this may fully power
1801 * it off and when it comes back it will have lost all state, but
1802 * that's OK because the default is input and we're now an input.
1803 */
1804 pm_runtime_put_autosuspend(pdata->dev);
1805
1806 return 0;
1807 }
1808
ti_sn_bridge_gpio_direction_output(struct gpio_chip * chip,unsigned int offset,int val)1809 static int ti_sn_bridge_gpio_direction_output(struct gpio_chip *chip,
1810 unsigned int offset, int val)
1811 {
1812 struct ti_sn65dsi86 *pdata = gpiochip_get_data(chip);
1813 int shift = offset * 2;
1814 int ret;
1815
1816 if (test_and_set_bit(offset, pdata->gchip_output))
1817 return 0;
1818
1819 pm_runtime_get_sync(pdata->dev);
1820
1821 /* Set value first to avoid glitching */
1822 ti_sn_bridge_gpio_set(chip, offset, val);
1823
1824 /* Set direction */
1825 ret = regmap_update_bits(pdata->regmap, SN_GPIO_CTRL_REG,
1826 SN_GPIO_MUX_MASK << shift,
1827 SN_GPIO_MUX_OUTPUT << shift);
1828 if (ret) {
1829 clear_bit(offset, pdata->gchip_output);
1830 pm_runtime_put_autosuspend(pdata->dev);
1831 }
1832
1833 return ret;
1834 }
1835
ti_sn_bridge_gpio_request(struct gpio_chip * chip,unsigned int offset)1836 static int ti_sn_bridge_gpio_request(struct gpio_chip *chip, unsigned int offset)
1837 {
1838 struct ti_sn65dsi86 *pdata = gpiochip_get_data(chip);
1839
1840 if (offset == SN_PWM_GPIO_IDX)
1841 return ti_sn_pwm_pin_request(pdata);
1842
1843 return 0;
1844 }
1845
ti_sn_bridge_gpio_free(struct gpio_chip * chip,unsigned int offset)1846 static void ti_sn_bridge_gpio_free(struct gpio_chip *chip, unsigned int offset)
1847 {
1848 struct ti_sn65dsi86 *pdata = gpiochip_get_data(chip);
1849
1850 /* We won't keep pm_runtime if we're input, so switch there on free */
1851 ti_sn_bridge_gpio_direction_input(chip, offset);
1852
1853 if (offset == SN_PWM_GPIO_IDX)
1854 ti_sn_pwm_pin_release(pdata);
1855 }
1856
1857 static const char * const ti_sn_bridge_gpio_names[SN_NUM_GPIOS] = {
1858 "GPIO1", "GPIO2", "GPIO3", "GPIO4"
1859 };
1860
ti_sn_gpio_probe(struct auxiliary_device * adev,const struct auxiliary_device_id * id)1861 static int ti_sn_gpio_probe(struct auxiliary_device *adev,
1862 const struct auxiliary_device_id *id)
1863 {
1864 struct ti_sn65dsi86 *pdata = dev_get_drvdata(adev->dev.parent);
1865 int ret;
1866
1867 /* Only init if someone is going to use us as a GPIO controller */
1868 if (!of_property_read_bool(pdata->dev->of_node, "gpio-controller"))
1869 return 0;
1870
1871 pdata->gchip.label = dev_name(pdata->dev);
1872 pdata->gchip.parent = pdata->dev;
1873 pdata->gchip.owner = THIS_MODULE;
1874 pdata->gchip.of_xlate = tn_sn_bridge_of_xlate;
1875 pdata->gchip.of_gpio_n_cells = 2;
1876 pdata->gchip.request = ti_sn_bridge_gpio_request;
1877 pdata->gchip.free = ti_sn_bridge_gpio_free;
1878 pdata->gchip.get_direction = ti_sn_bridge_gpio_get_direction;
1879 pdata->gchip.direction_input = ti_sn_bridge_gpio_direction_input;
1880 pdata->gchip.direction_output = ti_sn_bridge_gpio_direction_output;
1881 pdata->gchip.get = ti_sn_bridge_gpio_get;
1882 pdata->gchip.set = ti_sn_bridge_gpio_set;
1883 pdata->gchip.can_sleep = true;
1884 pdata->gchip.names = ti_sn_bridge_gpio_names;
1885 pdata->gchip.ngpio = SN_NUM_GPIOS;
1886 pdata->gchip.base = -1;
1887 ret = devm_gpiochip_add_data(&adev->dev, &pdata->gchip, pdata);
1888 if (ret)
1889 dev_err(pdata->dev, "can't add gpio chip\n");
1890
1891 return ret;
1892 }
1893
1894 static const struct auxiliary_device_id ti_sn_gpio_id_table[] = {
1895 { .name = "ti_sn65dsi86.gpio", },
1896 {},
1897 };
1898
1899 MODULE_DEVICE_TABLE(auxiliary, ti_sn_gpio_id_table);
1900
1901 static struct auxiliary_driver ti_sn_gpio_driver = {
1902 .name = "gpio",
1903 .probe = ti_sn_gpio_probe,
1904 .id_table = ti_sn_gpio_id_table,
1905 };
1906
ti_sn_gpio_register(void)1907 static int __init ti_sn_gpio_register(void)
1908 {
1909 return auxiliary_driver_register(&ti_sn_gpio_driver);
1910 }
1911
ti_sn_gpio_unregister(void)1912 static void ti_sn_gpio_unregister(void)
1913 {
1914 auxiliary_driver_unregister(&ti_sn_gpio_driver);
1915 }
1916
1917 #else
1918
ti_sn_gpio_register(void)1919 static inline int ti_sn_gpio_register(void) { return 0; }
ti_sn_gpio_unregister(void)1920 static inline void ti_sn_gpio_unregister(void) {}
1921
1922 #endif
1923
1924 /* -----------------------------------------------------------------------------
1925 * Probe & Remove
1926 */
1927
ti_sn65dsi86_runtime_disable(void * data)1928 static void ti_sn65dsi86_runtime_disable(void *data)
1929 {
1930 pm_runtime_dont_use_autosuspend(data);
1931 pm_runtime_disable(data);
1932 }
1933
ti_sn65dsi86_parse_regulators(struct ti_sn65dsi86 * pdata)1934 static int ti_sn65dsi86_parse_regulators(struct ti_sn65dsi86 *pdata)
1935 {
1936 unsigned int i;
1937 const char * const ti_sn_bridge_supply_names[] = {
1938 "vcca", "vcc", "vccio", "vpll",
1939 };
1940
1941 for (i = 0; i < SN_REGULATOR_SUPPLY_NUM; i++)
1942 pdata->supplies[i].supply = ti_sn_bridge_supply_names[i];
1943
1944 return devm_regulator_bulk_get(pdata->dev, SN_REGULATOR_SUPPLY_NUM,
1945 pdata->supplies);
1946 }
1947
ti_sn65dsi86_probe(struct i2c_client * client)1948 static int ti_sn65dsi86_probe(struct i2c_client *client)
1949 {
1950 struct device *dev = &client->dev;
1951 struct ti_sn65dsi86 *pdata;
1952 u8 id_buf[8];
1953 int ret;
1954
1955 if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) {
1956 DRM_ERROR("device doesn't support I2C\n");
1957 return -ENODEV;
1958 }
1959
1960 pdata = devm_drm_bridge_alloc(dev, struct ti_sn65dsi86, bridge, &ti_sn_bridge_funcs);
1961 if (IS_ERR(pdata))
1962 return PTR_ERR(pdata);
1963 dev_set_drvdata(dev, pdata);
1964 pdata->dev = dev;
1965
1966 mutex_init(&pdata->comms_mutex);
1967
1968 pdata->regmap = devm_regmap_init_i2c(client,
1969 &ti_sn65dsi86_regmap_config);
1970 if (IS_ERR(pdata->regmap))
1971 return dev_err_probe(dev, PTR_ERR(pdata->regmap),
1972 "regmap i2c init failed\n");
1973
1974 pdata->enable_gpio = devm_gpiod_get_optional(dev, "enable",
1975 GPIOD_OUT_LOW);
1976 if (IS_ERR(pdata->enable_gpio))
1977 return dev_err_probe(dev, PTR_ERR(pdata->enable_gpio),
1978 "failed to get enable gpio from DT\n");
1979
1980 ret = ti_sn65dsi86_parse_regulators(pdata);
1981 if (ret)
1982 return dev_err_probe(dev, ret, "failed to parse regulators\n");
1983
1984 pdata->refclk = devm_clk_get_optional(dev, "refclk");
1985 if (IS_ERR(pdata->refclk))
1986 return dev_err_probe(dev, PTR_ERR(pdata->refclk),
1987 "failed to get reference clock\n");
1988
1989 pm_runtime_enable(dev);
1990 pm_runtime_set_autosuspend_delay(pdata->dev, 500);
1991 pm_runtime_use_autosuspend(pdata->dev);
1992 ret = devm_add_action_or_reset(dev, ti_sn65dsi86_runtime_disable, dev);
1993 if (ret)
1994 return ret;
1995
1996 pm_runtime_get_sync(dev);
1997 ret = regmap_bulk_read(pdata->regmap, SN_DEVICE_ID_REGS, id_buf, ARRAY_SIZE(id_buf));
1998 pm_runtime_put_autosuspend(dev);
1999 if (ret)
2000 return dev_err_probe(dev, ret, "failed to read device id\n");
2001
2002 /* The ID string is stored backwards */
2003 if (strncmp(id_buf, "68ISD ", ARRAY_SIZE(id_buf)))
2004 return dev_err_probe(dev, -EOPNOTSUPP, "unsupported device id\n");
2005
2006 /*
2007 * Break ourselves up into a collection of aux devices. The only real
2008 * motiviation here is to solve the chicken-and-egg problem of probe
2009 * ordering. The bridge wants the panel to be there when it probes.
2010 * The panel wants its HPD GPIO (provided by sn65dsi86 on some boards)
2011 * when it probes. The panel and maybe backlight might want the DDC
2012 * bus or the pwm_chip. Having sub-devices allows the some sub devices
2013 * to finish probing even if others return -EPROBE_DEFER and gets us
2014 * around the problems.
2015 */
2016
2017 if (IS_ENABLED(CONFIG_OF_GPIO)) {
2018 ret = ti_sn65dsi86_add_aux_device(pdata, &pdata->gpio_aux, "gpio");
2019 if (ret)
2020 return ret;
2021 }
2022
2023 if (IS_REACHABLE(CONFIG_PWM)) {
2024 ret = ti_sn65dsi86_add_aux_device(pdata, &pdata->pwm_aux, "pwm");
2025 if (ret)
2026 return ret;
2027 }
2028
2029 /*
2030 * NOTE: At the end of the AUX channel probe we'll add the aux device
2031 * for the bridge. This is because the bridge can't be used until the
2032 * AUX channel is there and this is a very simple solution to the
2033 * dependency problem.
2034 */
2035 return ti_sn65dsi86_add_aux_device(pdata, &pdata->aux_aux, "aux");
2036 }
2037
2038 static const struct i2c_device_id ti_sn65dsi86_id[] = {
2039 { "ti,sn65dsi86" },
2040 {}
2041 };
2042 MODULE_DEVICE_TABLE(i2c, ti_sn65dsi86_id);
2043
2044 static const struct of_device_id ti_sn65dsi86_match_table[] = {
2045 {.compatible = "ti,sn65dsi86"},
2046 {},
2047 };
2048 MODULE_DEVICE_TABLE(of, ti_sn65dsi86_match_table);
2049
2050 static struct i2c_driver ti_sn65dsi86_driver = {
2051 .driver = {
2052 .name = "ti_sn65dsi86",
2053 .of_match_table = ti_sn65dsi86_match_table,
2054 .pm = &ti_sn65dsi86_pm_ops,
2055 },
2056 .probe = ti_sn65dsi86_probe,
2057 .id_table = ti_sn65dsi86_id,
2058 };
2059
ti_sn65dsi86_init(void)2060 static int __init ti_sn65dsi86_init(void)
2061 {
2062 int ret;
2063
2064 ret = i2c_add_driver(&ti_sn65dsi86_driver);
2065 if (ret)
2066 return ret;
2067
2068 ret = ti_sn_gpio_register();
2069 if (ret)
2070 goto err_main_was_registered;
2071
2072 ret = ti_sn_pwm_register();
2073 if (ret)
2074 goto err_gpio_was_registered;
2075
2076 ret = auxiliary_driver_register(&ti_sn_aux_driver);
2077 if (ret)
2078 goto err_pwm_was_registered;
2079
2080 ret = auxiliary_driver_register(&ti_sn_bridge_driver);
2081 if (ret)
2082 goto err_aux_was_registered;
2083
2084 return 0;
2085
2086 err_aux_was_registered:
2087 auxiliary_driver_unregister(&ti_sn_aux_driver);
2088 err_pwm_was_registered:
2089 ti_sn_pwm_unregister();
2090 err_gpio_was_registered:
2091 ti_sn_gpio_unregister();
2092 err_main_was_registered:
2093 i2c_del_driver(&ti_sn65dsi86_driver);
2094
2095 return ret;
2096 }
2097 module_init(ti_sn65dsi86_init);
2098
ti_sn65dsi86_exit(void)2099 static void __exit ti_sn65dsi86_exit(void)
2100 {
2101 auxiliary_driver_unregister(&ti_sn_bridge_driver);
2102 auxiliary_driver_unregister(&ti_sn_aux_driver);
2103 ti_sn_pwm_unregister();
2104 ti_sn_gpio_unregister();
2105 i2c_del_driver(&ti_sn65dsi86_driver);
2106 }
2107 module_exit(ti_sn65dsi86_exit);
2108
2109 MODULE_AUTHOR("Sandeep Panda <spanda@codeaurora.org>");
2110 MODULE_DESCRIPTION("sn65dsi86 DSI to eDP bridge driver");
2111 MODULE_LICENSE("GPL v2");
2112