1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (C) 2020 Justin Hibbits
5 * Copyright (C) 2007-2009 Semihalf, Rafal Jaworowski <raj@semihalf.com>
6 * Copyright (C) 2006 Semihalf, Marian Balakowicz <m8@semihalf.com>
7 * All rights reserved.
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
21 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
23 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
24 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
25 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
26 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
27 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 *
29 * Some hw specific parts of this pmap were derived or influenced
30 * by NetBSD's ibm4xx pmap module. More generic code is shared with
31 * a few other pmap modules from the FreeBSD tree.
32 */
33
34 /*
35 * VM layout notes:
36 *
37 * Kernel and user threads run within one common virtual address space
38 * defined by AS=0.
39 *
40 * 32-bit pmap:
41 * Virtual address space layout:
42 * -----------------------------
43 * 0x0000_0000 - 0x7fff_ffff : user process
44 * 0x8000_0000 - 0xbfff_ffff : pmap_mapdev()-ed area (PCI/PCIE etc.)
45 * 0xc000_0000 - 0xffff_efff : KVA
46 */
47
48 #include <sys/cdefs.h>
49 #include "opt_ddb.h"
50 #include "opt_kstack_pages.h"
51
52 #include <sys/param.h>
53 #include <sys/conf.h>
54 #include <sys/malloc.h>
55 #include <sys/ktr.h>
56 #include <sys/proc.h>
57 #include <sys/user.h>
58 #include <sys/queue.h>
59 #include <sys/systm.h>
60 #include <sys/kernel.h>
61 #include <sys/kerneldump.h>
62 #include <sys/linker.h>
63 #include <sys/msgbuf.h>
64 #include <sys/lock.h>
65 #include <sys/mutex.h>
66 #include <sys/rwlock.h>
67 #include <sys/sched.h>
68 #include <sys/smp.h>
69 #include <sys/vmmeter.h>
70
71 #include <vm/vm.h>
72 #include <vm/vm_page.h>
73 #include <vm/vm_kern.h>
74 #include <vm/vm_pageout.h>
75 #include <vm/vm_extern.h>
76 #include <vm/vm_object.h>
77 #include <vm/vm_param.h>
78 #include <vm/vm_map.h>
79 #include <vm/vm_pager.h>
80 #include <vm/vm_phys.h>
81 #include <vm/vm_pagequeue.h>
82 #include <vm/uma.h>
83
84 #include <machine/_inttypes.h>
85 #include <machine/cpu.h>
86 #include <machine/pcb.h>
87 #include <machine/platform.h>
88
89 #include <machine/tlb.h>
90 #include <machine/spr.h>
91 #include <machine/md_var.h>
92 #include <machine/mmuvar.h>
93 #include <machine/pmap.h>
94 #include <machine/pte.h>
95
96 #include <ddb/ddb.h>
97
98 #define PRI0ptrX "08x"
99
100 /* Reserved KVA space and mutex for mmu_booke_zero_page. */
101 static vm_offset_t zero_page_va;
102 static struct mtx zero_page_mutex;
103
104 /* Reserved KVA space and mutex for mmu_booke_copy_page. */
105 static vm_offset_t copy_page_src_va;
106 static vm_offset_t copy_page_dst_va;
107 static struct mtx copy_page_mutex;
108
109 static vm_offset_t kernel_ptbl_root;
110 static unsigned int kernel_ptbls; /* Number of KVA ptbls. */
111
112 /**************************************************************************/
113 /* PMAP */
114 /**************************************************************************/
115
116 #define VM_MAPDEV_BASE ((vm_offset_t)VM_MAXUSER_ADDRESS + PAGE_SIZE)
117
118 static void tid_flush(tlbtid_t tid);
119
120 /**************************************************************************/
121 /* Page table management */
122 /**************************************************************************/
123
124 #define PMAP_ROOT_SIZE (sizeof(pte_t**) * PDIR_NENTRIES)
125 static void ptbl_init(void);
126 static struct ptbl_buf *ptbl_buf_alloc(void);
127 static void ptbl_buf_free(struct ptbl_buf *);
128 static void ptbl_free_pmap_ptbl(pmap_t, pte_t *);
129
130 static pte_t *ptbl_alloc(pmap_t, unsigned int, bool);
131 static void ptbl_free(pmap_t, unsigned int);
132 static void ptbl_hold(pmap_t, unsigned int);
133 static int ptbl_unhold(pmap_t, unsigned int);
134
135 static vm_paddr_t pte_vatopa(pmap_t, vm_offset_t);
136 static int pte_enter(pmap_t, vm_page_t, vm_offset_t, uint32_t, bool);
137 static int pte_remove(pmap_t, vm_offset_t, uint8_t);
138 static pte_t *pte_find(pmap_t, vm_offset_t);
139
140 struct ptbl_buf {
141 TAILQ_ENTRY(ptbl_buf) link; /* list link */
142 vm_offset_t kva; /* va of mapping */
143 };
144
145 /* Number of kva ptbl buffers, each covering one ptbl (PTBL_PAGES). */
146 #define PTBL_BUFS (128 * 16)
147
148 /* ptbl free list and a lock used for access synchronization. */
149 static TAILQ_HEAD(, ptbl_buf) ptbl_buf_freelist;
150 static struct mtx ptbl_buf_freelist_lock;
151
152 /* Base address of kva space allocated fot ptbl bufs. */
153 static vm_offset_t ptbl_buf_pool_vabase;
154
155 /* Pointer to ptbl_buf structures. */
156 static struct ptbl_buf *ptbl_bufs;
157
158 /**************************************************************************/
159 /* Page table related */
160 /**************************************************************************/
161
162 /* Initialize pool of kva ptbl buffers. */
163 static void
ptbl_init(void)164 ptbl_init(void)
165 {
166 int i;
167
168 /* Create the UMA zone for page table roots. */
169 ptbl_root_zone = uma_zcreate("pmap root", PMAP_ROOT_SIZE,
170 NULL, NULL, NULL, NULL, UMA_ALIGN_CACHE, UMA_ZONE_VM);
171
172 CTR3(KTR_PMAP, "%s: s (ptbl_bufs = 0x%08x size 0x%08x)", __func__,
173 (uint32_t)ptbl_bufs, sizeof(struct ptbl_buf) * PTBL_BUFS);
174 CTR3(KTR_PMAP, "%s: s (ptbl_buf_pool_vabase = 0x%08x size = 0x%08x)",
175 __func__, ptbl_buf_pool_vabase, PTBL_BUFS * PTBL_PAGES * PAGE_SIZE);
176
177 mtx_init(&ptbl_buf_freelist_lock, "ptbl bufs lock", NULL, MTX_DEF);
178 TAILQ_INIT(&ptbl_buf_freelist);
179
180 for (i = 0; i < PTBL_BUFS; i++) {
181 ptbl_bufs[i].kva =
182 ptbl_buf_pool_vabase + i * PTBL_PAGES * PAGE_SIZE;
183 TAILQ_INSERT_TAIL(&ptbl_buf_freelist, &ptbl_bufs[i], link);
184 }
185 }
186
187 /* Get a ptbl_buf from the freelist. */
188 static struct ptbl_buf *
ptbl_buf_alloc(void)189 ptbl_buf_alloc(void)
190 {
191 struct ptbl_buf *buf;
192
193 mtx_lock(&ptbl_buf_freelist_lock);
194 buf = TAILQ_FIRST(&ptbl_buf_freelist);
195 if (buf != NULL)
196 TAILQ_REMOVE(&ptbl_buf_freelist, buf, link);
197 mtx_unlock(&ptbl_buf_freelist_lock);
198
199 CTR2(KTR_PMAP, "%s: buf = %p", __func__, buf);
200
201 return (buf);
202 }
203
204 /* Return ptbl buff to free pool. */
205 static void
ptbl_buf_free(struct ptbl_buf * buf)206 ptbl_buf_free(struct ptbl_buf *buf)
207 {
208
209 CTR2(KTR_PMAP, "%s: buf = %p", __func__, buf);
210
211 mtx_lock(&ptbl_buf_freelist_lock);
212 TAILQ_INSERT_TAIL(&ptbl_buf_freelist, buf, link);
213 mtx_unlock(&ptbl_buf_freelist_lock);
214 }
215
216 /*
217 * Search the list of allocated ptbl bufs and find on list of allocated ptbls
218 */
219 static void
ptbl_free_pmap_ptbl(pmap_t pmap,pte_t * ptbl)220 ptbl_free_pmap_ptbl(pmap_t pmap, pte_t *ptbl)
221 {
222 struct ptbl_buf *pbuf;
223
224 CTR2(KTR_PMAP, "%s: ptbl = %p", __func__, ptbl);
225
226 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
227
228 TAILQ_FOREACH(pbuf, &pmap->pm_ptbl_list, link)
229 if (pbuf->kva == (vm_offset_t)ptbl) {
230 /* Remove from pmap ptbl buf list. */
231 TAILQ_REMOVE(&pmap->pm_ptbl_list, pbuf, link);
232
233 /* Free corresponding ptbl buf. */
234 ptbl_buf_free(pbuf);
235 break;
236 }
237 }
238
239 /* Allocate page table. */
240 static pte_t *
ptbl_alloc(pmap_t pmap,unsigned int pdir_idx,bool nosleep)241 ptbl_alloc(pmap_t pmap, unsigned int pdir_idx, bool nosleep)
242 {
243 vm_page_t mtbl[PTBL_PAGES];
244 vm_page_t m;
245 struct ptbl_buf *pbuf;
246 unsigned int pidx;
247 pte_t *ptbl;
248 int i, j;
249
250 CTR4(KTR_PMAP, "%s: pmap = %p su = %d pdir_idx = %d", __func__, pmap,
251 (pmap == kernel_pmap), pdir_idx);
252
253 KASSERT((pdir_idx <= (VM_MAXUSER_ADDRESS / PDIR_SIZE)),
254 ("ptbl_alloc: invalid pdir_idx"));
255 KASSERT((pmap->pm_pdir[pdir_idx] == NULL),
256 ("pte_alloc: valid ptbl entry exists!"));
257
258 pbuf = ptbl_buf_alloc();
259 if (pbuf == NULL)
260 panic("pte_alloc: couldn't alloc kernel virtual memory");
261
262 ptbl = (pte_t *)pbuf->kva;
263
264 CTR2(KTR_PMAP, "%s: ptbl kva = %p", __func__, ptbl);
265
266 for (i = 0; i < PTBL_PAGES; i++) {
267 pidx = (PTBL_PAGES * pdir_idx) + i;
268 while ((m = vm_page_alloc_noobj(VM_ALLOC_WIRED)) == NULL) {
269 if (nosleep) {
270 ptbl_free_pmap_ptbl(pmap, ptbl);
271 for (j = 0; j < i; j++)
272 vm_page_free(mtbl[j]);
273 vm_wire_sub(i);
274 return (NULL);
275 }
276 PMAP_UNLOCK(pmap);
277 rw_wunlock(&pvh_global_lock);
278 vm_wait(NULL);
279 rw_wlock(&pvh_global_lock);
280 PMAP_LOCK(pmap);
281 }
282 m->pindex = pidx;
283 mtbl[i] = m;
284 }
285
286 /* Map allocated pages into kernel_pmap. */
287 mmu_booke_qenter(ptbl, mtbl, PTBL_PAGES);
288
289 /* Zero whole ptbl. */
290 bzero(ptbl, PTBL_PAGES * PAGE_SIZE);
291
292 /* Add pbuf to the pmap ptbl bufs list. */
293 TAILQ_INSERT_TAIL(&pmap->pm_ptbl_list, pbuf, link);
294
295 return (ptbl);
296 }
297
298 /* Free ptbl pages and invalidate pdir entry. */
299 static void
ptbl_free(pmap_t pmap,unsigned int pdir_idx)300 ptbl_free(pmap_t pmap, unsigned int pdir_idx)
301 {
302 pte_t *ptbl;
303 vm_paddr_t pa;
304 vm_offset_t va;
305 vm_page_t m;
306 int i;
307
308 CTR4(KTR_PMAP, "%s: pmap = %p su = %d pdir_idx = %d", __func__, pmap,
309 (pmap == kernel_pmap), pdir_idx);
310
311 KASSERT((pdir_idx <= (VM_MAXUSER_ADDRESS / PDIR_SIZE)),
312 ("ptbl_free: invalid pdir_idx"));
313
314 ptbl = pmap->pm_pdir[pdir_idx];
315
316 CTR2(KTR_PMAP, "%s: ptbl = %p", __func__, ptbl);
317
318 KASSERT((ptbl != NULL), ("ptbl_free: null ptbl"));
319
320 /*
321 * Invalidate the pdir entry as soon as possible, so that other CPUs
322 * don't attempt to look up the page tables we are releasing.
323 */
324 mtx_lock_spin(&tlbivax_mutex);
325 tlb_miss_lock();
326
327 pmap->pm_pdir[pdir_idx] = NULL;
328
329 tlb_miss_unlock();
330 mtx_unlock_spin(&tlbivax_mutex);
331
332 for (i = 0; i < PTBL_PAGES; i++) {
333 va = ((vm_offset_t)ptbl + (i * PAGE_SIZE));
334 pa = pte_vatopa(kernel_pmap, va);
335 m = PHYS_TO_VM_PAGE(pa);
336 vm_page_free_zero(m);
337 vm_wire_sub(1);
338 mmu_booke_kremove(va);
339 }
340
341 ptbl_free_pmap_ptbl(pmap, ptbl);
342 }
343
344 /*
345 * Decrement ptbl pages hold count and attempt to free ptbl pages.
346 * Called when removing pte entry from ptbl.
347 *
348 * Return 1 if ptbl pages were freed.
349 */
350 static int
ptbl_unhold(pmap_t pmap,unsigned int pdir_idx)351 ptbl_unhold(pmap_t pmap, unsigned int pdir_idx)
352 {
353 pte_t *ptbl;
354 vm_paddr_t pa;
355 vm_page_t m;
356 int i;
357
358 CTR4(KTR_PMAP, "%s: pmap = %p su = %d pdir_idx = %d", __func__, pmap,
359 (pmap == kernel_pmap), pdir_idx);
360
361 KASSERT((pdir_idx <= (VM_MAXUSER_ADDRESS / PDIR_SIZE)),
362 ("ptbl_unhold: invalid pdir_idx"));
363 KASSERT((pmap != kernel_pmap),
364 ("ptbl_unhold: unholding kernel ptbl!"));
365
366 ptbl = pmap->pm_pdir[pdir_idx];
367
368 //debugf("ptbl_unhold: ptbl = 0x%08x\n", (u_int32_t)ptbl);
369 KASSERT(((vm_offset_t)ptbl >= VM_MIN_KERNEL_ADDRESS),
370 ("ptbl_unhold: non kva ptbl"));
371
372 /* decrement hold count */
373 for (i = 0; i < PTBL_PAGES; i++) {
374 pa = pte_vatopa(kernel_pmap,
375 (vm_offset_t)ptbl + (i * PAGE_SIZE));
376 m = PHYS_TO_VM_PAGE(pa);
377 m->ref_count--;
378 }
379
380 /*
381 * Free ptbl pages if there are no pte etries in this ptbl.
382 * ref_count has the same value for all ptbl pages, so check the last
383 * page.
384 */
385 if (m->ref_count == 0) {
386 ptbl_free(pmap, pdir_idx);
387
388 //debugf("ptbl_unhold: e (freed ptbl)\n");
389 return (1);
390 }
391
392 return (0);
393 }
394
395 /*
396 * Increment hold count for ptbl pages. This routine is used when a new pte
397 * entry is being inserted into the ptbl.
398 */
399 static void
ptbl_hold(pmap_t pmap,unsigned int pdir_idx)400 ptbl_hold(pmap_t pmap, unsigned int pdir_idx)
401 {
402 vm_paddr_t pa;
403 pte_t *ptbl;
404 vm_page_t m;
405 int i;
406
407 CTR3(KTR_PMAP, "%s: pmap = %p pdir_idx = %d", __func__, pmap,
408 pdir_idx);
409
410 KASSERT((pdir_idx <= (VM_MAXUSER_ADDRESS / PDIR_SIZE)),
411 ("ptbl_hold: invalid pdir_idx"));
412 KASSERT((pmap != kernel_pmap),
413 ("ptbl_hold: holding kernel ptbl!"));
414
415 ptbl = pmap->pm_pdir[pdir_idx];
416
417 KASSERT((ptbl != NULL), ("ptbl_hold: null ptbl"));
418
419 for (i = 0; i < PTBL_PAGES; i++) {
420 pa = pte_vatopa(kernel_pmap,
421 (vm_offset_t)ptbl + (i * PAGE_SIZE));
422 m = PHYS_TO_VM_PAGE(pa);
423 m->ref_count++;
424 }
425 }
426
427 /*
428 * Clean pte entry, try to free page table page if requested.
429 *
430 * Return 1 if ptbl pages were freed, otherwise return 0.
431 */
432 static int
pte_remove(pmap_t pmap,vm_offset_t va,uint8_t flags)433 pte_remove(pmap_t pmap, vm_offset_t va, uint8_t flags)
434 {
435 unsigned int pdir_idx = PDIR_IDX(va);
436 unsigned int ptbl_idx = PTBL_IDX(va);
437 vm_page_t m;
438 pte_t *ptbl;
439 pte_t *pte;
440
441 //int su = (pmap == kernel_pmap);
442 //debugf("pte_remove: s (su = %d pmap = 0x%08x va = 0x%08x flags = %d)\n",
443 // su, (u_int32_t)pmap, va, flags);
444
445 ptbl = pmap->pm_pdir[pdir_idx];
446 KASSERT(ptbl, ("pte_remove: null ptbl"));
447
448 pte = &ptbl[ptbl_idx];
449
450 if (pte == NULL || !PTE_ISVALID(pte))
451 return (0);
452
453 if (PTE_ISWIRED(pte))
454 pmap->pm_stats.wired_count--;
455
456 /* Get vm_page_t for mapped pte. */
457 m = PHYS_TO_VM_PAGE(PTE_PA(pte));
458
459 /* Handle managed entry. */
460 if (PTE_ISMANAGED(pte)) {
461 if (PTE_ISMODIFIED(pte))
462 vm_page_dirty(m);
463
464 if (PTE_ISREFERENCED(pte))
465 vm_page_aflag_set(m, PGA_REFERENCED);
466
467 pv_remove(pmap, va, m);
468 } else if (pmap == kernel_pmap && m && m->md.pv_tracked) {
469 /*
470 * Always pv_insert()/pv_remove() on MPC85XX, in case DPAA is
471 * used. This is needed by the NCSW support code for fast
472 * VA<->PA translation.
473 */
474 pv_remove(pmap, va, m);
475 if (TAILQ_EMPTY(&m->md.pv_list))
476 m->md.pv_tracked = false;
477 }
478
479 mtx_lock_spin(&tlbivax_mutex);
480 tlb_miss_lock();
481
482 tlb0_flush_entry(va);
483 *pte = 0;
484
485 tlb_miss_unlock();
486 mtx_unlock_spin(&tlbivax_mutex);
487
488 pmap->pm_stats.resident_count--;
489
490 if (flags & PTBL_UNHOLD) {
491 //debugf("pte_remove: e (unhold)\n");
492 return (ptbl_unhold(pmap, pdir_idx));
493 }
494
495 //debugf("pte_remove: e\n");
496 return (0);
497 }
498
499 /*
500 * Insert PTE for a given page and virtual address.
501 */
502 static int
pte_enter(pmap_t pmap,vm_page_t m,vm_offset_t va,uint32_t flags,bool nosleep)503 pte_enter(pmap_t pmap, vm_page_t m, vm_offset_t va, uint32_t flags,
504 bool nosleep)
505 {
506 unsigned int pdir_idx = PDIR_IDX(va);
507 unsigned int ptbl_idx = PTBL_IDX(va);
508 pte_t *ptbl, *pte, pte_tmp;
509
510 CTR4(KTR_PMAP, "%s: su = %d pmap = %p va = %p", __func__,
511 pmap == kernel_pmap, pmap, va);
512
513 /* Get the page table pointer. */
514 ptbl = pmap->pm_pdir[pdir_idx];
515
516 if (ptbl == NULL) {
517 /* Allocate page table pages. */
518 ptbl = ptbl_alloc(pmap, pdir_idx, nosleep);
519 if (ptbl == NULL) {
520 KASSERT(nosleep, ("nosleep and NULL ptbl"));
521 return (ENOMEM);
522 }
523 pmap->pm_pdir[pdir_idx] = ptbl;
524 pte = &ptbl[ptbl_idx];
525 } else {
526 /*
527 * Check if there is valid mapping for requested
528 * va, if there is, remove it.
529 */
530 pte = &pmap->pm_pdir[pdir_idx][ptbl_idx];
531 if (PTE_ISVALID(pte)) {
532 pte_remove(pmap, va, PTBL_HOLD);
533 } else {
534 /*
535 * pte is not used, increment hold count
536 * for ptbl pages.
537 */
538 if (pmap != kernel_pmap)
539 ptbl_hold(pmap, pdir_idx);
540 }
541 }
542
543 /*
544 * Insert pv_entry into pv_list for mapped page if part of managed
545 * memory.
546 */
547 if ((m->oflags & VPO_UNMANAGED) == 0) {
548 flags |= PTE_MANAGED;
549
550 /* Create and insert pv entry. */
551 pv_insert(pmap, va, m);
552 }
553
554 pmap->pm_stats.resident_count++;
555
556 pte_tmp = PTE_RPN_FROM_PA(VM_PAGE_TO_PHYS(m));
557 pte_tmp |= (PTE_VALID | flags | PTE_PS_4KB); /* 4KB pages only */
558
559 mtx_lock_spin(&tlbivax_mutex);
560 tlb_miss_lock();
561
562 tlb0_flush_entry(va);
563 *pte = pte_tmp;
564
565 tlb_miss_unlock();
566 mtx_unlock_spin(&tlbivax_mutex);
567 return (0);
568 }
569
570 /* Return the pa for the given pmap/va. */
571 static vm_paddr_t
pte_vatopa(pmap_t pmap,vm_offset_t va)572 pte_vatopa(pmap_t pmap, vm_offset_t va)
573 {
574 vm_paddr_t pa = 0;
575 pte_t *pte;
576
577 pte = pte_find(pmap, va);
578 if ((pte != NULL) && PTE_ISVALID(pte))
579 pa = (PTE_PA(pte) | (va & PTE_PA_MASK));
580 return (pa);
581 }
582
583 /* Get a pointer to a PTE in a page table. */
584 static pte_t *
pte_find(pmap_t pmap,vm_offset_t va)585 pte_find(pmap_t pmap, vm_offset_t va)
586 {
587 unsigned int pdir_idx = PDIR_IDX(va);
588 unsigned int ptbl_idx = PTBL_IDX(va);
589
590 KASSERT((pmap != NULL), ("pte_find: invalid pmap"));
591
592 if (pmap->pm_pdir[pdir_idx])
593 return (&(pmap->pm_pdir[pdir_idx][ptbl_idx]));
594
595 return (NULL);
596 }
597
598 /* Get a pointer to a PTE in a page table, or the next closest (greater) one. */
599 static __inline pte_t *
pte_find_next(pmap_t pmap,vm_offset_t * pva)600 pte_find_next(pmap_t pmap, vm_offset_t *pva)
601 {
602 vm_offset_t va;
603 pte_t **pdir;
604 pte_t *pte;
605 unsigned long i, j;
606
607 KASSERT((pmap != NULL), ("pte_find: invalid pmap"));
608
609 va = *pva;
610 i = PDIR_IDX(va);
611 j = PTBL_IDX(va);
612 pdir = pmap->pm_pdir;
613 for (; i < PDIR_NENTRIES; i++, j = 0) {
614 if (pdir[i] == NULL)
615 continue;
616 for (; j < PTBL_NENTRIES; j++) {
617 pte = &pdir[i][j];
618 if (!PTE_ISVALID(pte))
619 continue;
620 *pva = PDIR_SIZE * i + PAGE_SIZE * j;
621 return (pte);
622 }
623 }
624 return (NULL);
625 }
626
627 /* Set up kernel page tables. */
628 static void
kernel_pte_alloc(vm_offset_t data_end,vm_offset_t addr)629 kernel_pte_alloc(vm_offset_t data_end, vm_offset_t addr)
630 {
631 pte_t *pte;
632 vm_offset_t va;
633 vm_offset_t pdir_start;
634 int i;
635
636 kptbl_min = VM_MIN_KERNEL_ADDRESS / PDIR_SIZE;
637 kernel_pmap->pm_pdir = (pte_t **)kernel_ptbl_root;
638
639 pdir_start = kernel_ptbl_root + PDIR_NENTRIES * sizeof(pte_t);
640
641 /* Initialize kernel pdir */
642 for (i = 0; i < kernel_ptbls; i++) {
643 kernel_pmap->pm_pdir[kptbl_min + i] =
644 (pte_t *)(pdir_start + (i * PAGE_SIZE * PTBL_PAGES));
645 }
646
647 /*
648 * Fill in PTEs covering kernel code and data. They are not required
649 * for address translation, as this area is covered by static TLB1
650 * entries, but for pte_vatopa() to work correctly with kernel area
651 * addresses.
652 */
653 for (va = addr; va < data_end; va += PAGE_SIZE) {
654 pte = &(kernel_pmap->pm_pdir[PDIR_IDX(va)][PTBL_IDX(va)]);
655 powerpc_sync();
656 *pte = PTE_RPN_FROM_PA(kernload + (va - kernstart));
657 *pte |= PTE_M | PTE_SR | PTE_SW | PTE_SX | PTE_WIRED |
658 PTE_VALID | PTE_PS_4KB;
659 }
660 }
661
662 static vm_offset_t
mmu_booke_alloc_kernel_pgtables(vm_offset_t data_end)663 mmu_booke_alloc_kernel_pgtables(vm_offset_t data_end)
664 {
665 /* Allocate space for ptbl_bufs. */
666 ptbl_bufs = (struct ptbl_buf *)data_end;
667 data_end += sizeof(struct ptbl_buf) * PTBL_BUFS;
668 debugf(" ptbl_bufs at 0x%"PRI0ptrX" end = 0x%"PRI0ptrX"\n",
669 (uintptr_t)ptbl_bufs, data_end);
670
671 data_end = round_page(data_end);
672
673 kernel_ptbl_root = data_end;
674 data_end += PDIR_NENTRIES * sizeof(pte_t*);
675
676 /* Allocate PTE tables for kernel KVA. */
677 kernel_ptbls = howmany(VM_MAX_KERNEL_ADDRESS - VM_MIN_KERNEL_ADDRESS,
678 PDIR_SIZE);
679 data_end += kernel_ptbls * PTBL_PAGES * PAGE_SIZE;
680 debugf(" kernel ptbls: %d\n", kernel_ptbls);
681 debugf(" kernel pdir at %#jx end = %#jx\n",
682 (uintmax_t)kernel_ptbl_root, (uintmax_t)data_end);
683
684 return (data_end);
685 }
686
687 /*
688 * Initialize a preallocated and zeroed pmap structure,
689 * such as one in a vmspace structure.
690 */
691 static int
mmu_booke_pinit(pmap_t pmap)692 mmu_booke_pinit(pmap_t pmap)
693 {
694 int i;
695
696 CTR4(KTR_PMAP, "%s: pmap = %p, proc %d '%s'", __func__, pmap,
697 curthread->td_proc->p_pid, curthread->td_proc->p_comm);
698
699 KASSERT((pmap != kernel_pmap), ("pmap_pinit: initializing kernel_pmap"));
700
701 for (i = 0; i < MAXCPU; i++)
702 pmap->pm_tid[i] = TID_NONE;
703 CPU_ZERO(&kernel_pmap->pm_active);
704 bzero(&pmap->pm_stats, sizeof(pmap->pm_stats));
705 pmap->pm_pdir = uma_zalloc(ptbl_root_zone, M_WAITOK);
706 bzero(pmap->pm_pdir, sizeof(pte_t *) * PDIR_NENTRIES);
707 TAILQ_INIT(&pmap->pm_ptbl_list);
708
709 return (1);
710 }
711
712 /*
713 * Release any resources held by the given physical map.
714 * Called when a pmap initialized by mmu_booke_pinit is being released.
715 * Should only be called if the map contains no valid mappings.
716 */
717 static void
mmu_booke_release(pmap_t pmap)718 mmu_booke_release(pmap_t pmap)
719 {
720
721 KASSERT(pmap->pm_stats.resident_count == 0,
722 ("pmap_release: pmap resident count %ld != 0",
723 pmap->pm_stats.resident_count));
724 uma_zfree(ptbl_root_zone, pmap->pm_pdir);
725 }
726
727 static void
mmu_booke_sync_icache(pmap_t pm,vm_offset_t va,vm_size_t sz)728 mmu_booke_sync_icache(pmap_t pm, vm_offset_t va, vm_size_t sz)
729 {
730 pte_t *pte;
731 vm_paddr_t pa = 0;
732 int sync_sz, valid;
733 pmap_t pmap;
734 vm_page_t m;
735 vm_offset_t addr;
736 int active;
737
738 rw_wlock(&pvh_global_lock);
739 pmap = PCPU_GET(curpmap);
740 active = (pm == kernel_pmap || pm == pmap) ? 1 : 0;
741 while (sz > 0) {
742 PMAP_LOCK(pm);
743 pte = pte_find(pm, va);
744 valid = (pte != NULL && PTE_ISVALID(pte)) ? 1 : 0;
745 if (valid)
746 pa = PTE_PA(pte);
747 PMAP_UNLOCK(pm);
748 sync_sz = PAGE_SIZE - (va & PAGE_MASK);
749 sync_sz = min(sync_sz, sz);
750 if (valid) {
751 if (!active) {
752 /*
753 * Create a mapping in the active pmap.
754 *
755 * XXX: We use the zero page here, because
756 * it isn't likely to be in use.
757 * If we ever decide to support
758 * security.bsd.map_at_zero on Book-E, change
759 * this to some other address that isn't
760 * normally mappable.
761 */
762 addr = 0;
763 m = PHYS_TO_VM_PAGE(pa);
764 PMAP_LOCK(pmap);
765 pte_enter(pmap, m, addr,
766 PTE_SR | PTE_VALID, false);
767 __syncicache((void *)(addr + (va & PAGE_MASK)),
768 sync_sz);
769 pte_remove(pmap, addr, PTBL_UNHOLD);
770 PMAP_UNLOCK(pmap);
771 } else
772 __syncicache((void *)va, sync_sz);
773 }
774 va += sync_sz;
775 sz -= sync_sz;
776 }
777 rw_wunlock(&pvh_global_lock);
778 }
779
780 /*
781 * mmu_booke_zero_page_area zeros the specified hardware page by
782 * mapping it into virtual memory and using bzero to clear
783 * its contents.
784 *
785 * off and size must reside within a single page.
786 */
787 static void
mmu_booke_zero_page_area(vm_page_t m,int off,int size)788 mmu_booke_zero_page_area(vm_page_t m, int off, int size)
789 {
790 vm_offset_t va;
791
792 /* XXX KASSERT off and size are within a single page? */
793
794 mtx_lock(&zero_page_mutex);
795 va = zero_page_va;
796
797 mmu_booke_kenter(va, VM_PAGE_TO_PHYS(m));
798 bzero((caddr_t)va + off, size);
799 mmu_booke_kremove(va);
800
801 mtx_unlock(&zero_page_mutex);
802 }
803
804 /*
805 * mmu_booke_zero_page zeros the specified hardware page.
806 */
807 static void
mmu_booke_zero_page(vm_page_t m)808 mmu_booke_zero_page(vm_page_t m)
809 {
810 vm_offset_t va;
811
812 va = zero_page_va;
813 mtx_lock(&zero_page_mutex);
814
815 mmu_booke_kenter(va, VM_PAGE_TO_PHYS(m));
816
817 bzero((void *)va, PAGE_SIZE);
818
819 mmu_booke_kremove(va);
820
821 mtx_unlock(&zero_page_mutex);
822 }
823
824 /*
825 * mmu_booke_copy_page copies the specified (machine independent) page by
826 * mapping the page into virtual memory and using memcopy to copy the page,
827 * one machine dependent page at a time.
828 */
829 static void
mmu_booke_copy_page(vm_page_t sm,vm_page_t dm)830 mmu_booke_copy_page(vm_page_t sm, vm_page_t dm)
831 {
832 vm_offset_t sva, dva;
833
834 sva = copy_page_src_va;
835 dva = copy_page_dst_va;
836
837 mtx_lock(©_page_mutex);
838 mmu_booke_kenter(sva, VM_PAGE_TO_PHYS(sm));
839 mmu_booke_kenter(dva, VM_PAGE_TO_PHYS(dm));
840
841 memcpy((caddr_t)dva, (caddr_t)sva, PAGE_SIZE);
842
843 mmu_booke_kremove(dva);
844 mmu_booke_kremove(sva);
845 mtx_unlock(©_page_mutex);
846 }
847
848 static inline void
mmu_booke_copy_pages(vm_page_t * ma,vm_offset_t a_offset,vm_page_t * mb,vm_offset_t b_offset,int xfersize)849 mmu_booke_copy_pages(vm_page_t *ma, vm_offset_t a_offset,
850 vm_page_t *mb, vm_offset_t b_offset, int xfersize)
851 {
852 void *a_cp, *b_cp;
853 vm_offset_t a_pg_offset, b_pg_offset;
854 int cnt;
855
856 mtx_lock(©_page_mutex);
857 while (xfersize > 0) {
858 a_pg_offset = a_offset & PAGE_MASK;
859 cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
860 mmu_booke_kenter(copy_page_src_va,
861 VM_PAGE_TO_PHYS(ma[a_offset >> PAGE_SHIFT]));
862 a_cp = (char *)copy_page_src_va + a_pg_offset;
863 b_pg_offset = b_offset & PAGE_MASK;
864 cnt = min(cnt, PAGE_SIZE - b_pg_offset);
865 mmu_booke_kenter(copy_page_dst_va,
866 VM_PAGE_TO_PHYS(mb[b_offset >> PAGE_SHIFT]));
867 b_cp = (char *)copy_page_dst_va + b_pg_offset;
868 bcopy(a_cp, b_cp, cnt);
869 mmu_booke_kremove(copy_page_dst_va);
870 mmu_booke_kremove(copy_page_src_va);
871 a_offset += cnt;
872 b_offset += cnt;
873 xfersize -= cnt;
874 }
875 mtx_unlock(©_page_mutex);
876 }
877
878 static void *
mmu_booke_quick_enter_page(vm_page_t m)879 mmu_booke_quick_enter_page(vm_page_t m)
880 {
881 vm_paddr_t paddr;
882 void *qaddr;
883 uint32_t flags;
884 pte_t *pte;
885
886 paddr = VM_PAGE_TO_PHYS(m);
887
888 flags = PTE_SR | PTE_SW | PTE_SX | PTE_WIRED | PTE_VALID;
889 flags |= tlb_calc_wimg(paddr, pmap_page_get_memattr(m)) << PTE_MAS2_SHIFT;
890 flags |= PTE_PS_4KB;
891
892 critical_enter();
893 qaddr = PCPU_GET(qmap_addr);
894
895 pte = pte_find(kernel_pmap, (vm_offset_t)qaddr);
896
897 KASSERT(*pte == 0, ("mmu_booke_quick_enter_page: PTE busy"));
898
899 /*
900 * XXX: tlbivax is broadcast to other cores, but qaddr should
901 * not be present in other TLBs. Is there a better instruction
902 * sequence to use? Or just forget it & use mmu_booke_kenter()...
903 */
904 __asm __volatile("tlbivax 0, %0" ::
905 "r" ((vm_offset_t)qaddr & MAS2_EPN_MASK));
906 __asm __volatile("isync; msync");
907
908 *pte = PTE_RPN_FROM_PA(paddr) | flags;
909
910 /* Flush the real memory from the instruction cache. */
911 if ((flags & (PTE_I | PTE_G)) == 0)
912 __syncicache(qaddr, PAGE_SIZE);
913
914 return (qaddr);
915 }
916
917 static void
mmu_booke_quick_remove_page(void * addr)918 mmu_booke_quick_remove_page(void *addr)
919 {
920 pte_t *pte;
921
922 pte = pte_find(kernel_pmap, (vm_offset_t)addr);
923
924 KASSERT(PCPU_GET(qmap_addr) == addr,
925 ("mmu_booke_quick_remove_page: invalid address"));
926 KASSERT(*pte != 0,
927 ("mmu_booke_quick_remove_page: PTE not in use"));
928
929 *pte = 0;
930 critical_exit();
931 }
932
933 /**************************************************************************/
934 /* TID handling */
935 /**************************************************************************/
936
937 /*
938 * Invalidate all TLB0 entries which match the given TID. Note this is
939 * dedicated for cases when invalidations should NOT be propagated to other
940 * CPUs.
941 */
942 static void
tid_flush(tlbtid_t tid)943 tid_flush(tlbtid_t tid)
944 {
945 register_t msr;
946
947 /* Don't evict kernel translations */
948 if (tid == TID_KERNEL)
949 return;
950
951 msr = mfmsr();
952 __asm __volatile("wrteei 0");
953
954 /*
955 * Newer (e500mc and later) have tlbilx, which doesn't broadcast, so use
956 * it for PID invalidation.
957 */
958 switch ((mfpvr() >> 16) & 0xffff) {
959 case FSL_E500mc:
960 case FSL_E5500:
961 case FSL_E6500:
962 mtspr(SPR_MAS6, tid << MAS6_SPID0_SHIFT);
963 /* tlbilxpid */
964 __asm __volatile("isync; .long 0x7c200024; isync; msync");
965 __asm __volatile("wrtee %0" :: "r"(msr));
966 return;
967 }
968 /* Flash invalidate TLB0 instead of walking the TLB to invalidate. */
969 mtspr(SPR_MMUCSR0, MMUCSR0_L2TLB0_FI);
970
971 __asm __volatile("wrtee %0" :: "r"(msr));
972 }
973