1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Analogix DP (Display Port) core interface driver.
4 *
5 * Copyright (C) 2012 Samsung Electronics Co., Ltd.
6 * Author: Jingoo Han <jg1.han@samsung.com>
7 */
8
9 #include <linux/clk.h>
10 #include <linux/component.h>
11 #include <linux/err.h>
12 #include <linux/gpio/consumer.h>
13 #include <linux/interrupt.h>
14 #include <linux/io.h>
15 #include <linux/iopoll.h>
16 #include <linux/module.h>
17 #include <linux/of.h>
18 #include <linux/phy/phy.h>
19 #include <linux/platform_device.h>
20
21 #include <drm/bridge/analogix_dp.h>
22 #include <drm/drm_atomic.h>
23 #include <drm/drm_atomic_helper.h>
24 #include <drm/drm_bridge.h>
25 #include <drm/drm_crtc.h>
26 #include <drm/drm_device.h>
27 #include <drm/drm_edid.h>
28 #include <drm/drm_panel.h>
29 #include <drm/drm_print.h>
30 #include <drm/drm_probe_helper.h>
31
32 #include "analogix_dp_core.h"
33 #include "analogix_dp_reg.h"
34
35 #define to_dp(nm) container_of(nm, struct analogix_dp_device, nm)
36
37 static const bool verify_fast_training;
38
analogix_dp_init_dp(struct analogix_dp_device * dp)39 static void analogix_dp_init_dp(struct analogix_dp_device *dp)
40 {
41 analogix_dp_reset(dp);
42
43 analogix_dp_swreset(dp);
44
45 analogix_dp_init_analog_param(dp);
46 analogix_dp_init_interrupt(dp);
47
48 /* SW defined function Normal operation */
49 analogix_dp_enable_sw_function(dp);
50
51 analogix_dp_config_interrupt(dp);
52
53 analogix_dp_init_hpd(dp);
54 analogix_dp_init_aux(dp);
55 }
56
analogix_dp_detect_hpd(struct analogix_dp_device * dp)57 static int analogix_dp_detect_hpd(struct analogix_dp_device *dp)
58 {
59 int timeout_loop = 0;
60
61 while (timeout_loop < DP_TIMEOUT_LOOP_COUNT) {
62 if (analogix_dp_get_plug_in_status(dp) == 0)
63 return 0;
64
65 timeout_loop++;
66 usleep_range(1000, 1100);
67 }
68
69 /*
70 * Some edp screen do not have hpd signal, so we can't just
71 * return failed when hpd plug in detect failed, DT property
72 * "force-hpd" would indicate whether driver need this.
73 */
74 if (!dp->force_hpd)
75 return -ETIMEDOUT;
76
77 /*
78 * The eDP TRM indicate that if HPD_STATUS(RO) is 0, AUX CH
79 * will not work, so we need to give a force hpd action to
80 * set HPD_STATUS manually.
81 */
82 dev_dbg(dp->dev, "failed to get hpd plug status, try to force hpd\n");
83
84 analogix_dp_force_hpd(dp);
85
86 if (analogix_dp_get_plug_in_status(dp) != 0) {
87 dev_err(dp->dev, "failed to get hpd plug in status\n");
88 return -EINVAL;
89 }
90
91 dev_dbg(dp->dev, "success to get plug in status after force hpd\n");
92
93 return 0;
94 }
95
analogix_dp_detect_sink_psr(struct analogix_dp_device * dp)96 static bool analogix_dp_detect_sink_psr(struct analogix_dp_device *dp)
97 {
98 unsigned char psr_version;
99 int ret;
100
101 ret = drm_dp_dpcd_readb(&dp->aux, DP_PSR_SUPPORT, &psr_version);
102 if (ret != 1) {
103 dev_err(dp->dev, "failed to get PSR version, disable it\n");
104 return false;
105 }
106
107 dev_dbg(dp->dev, "Panel PSR version : %x\n", psr_version);
108 return psr_version & DP_PSR_IS_SUPPORTED;
109 }
110
analogix_dp_enable_sink_psr(struct analogix_dp_device * dp)111 static int analogix_dp_enable_sink_psr(struct analogix_dp_device *dp)
112 {
113 unsigned char psr_en;
114 int ret;
115
116 /* Disable psr function */
117 ret = drm_dp_dpcd_readb(&dp->aux, DP_PSR_EN_CFG, &psr_en);
118 if (ret != 1) {
119 dev_err(dp->dev, "failed to get psr config\n");
120 goto end;
121 }
122
123 psr_en &= ~DP_PSR_ENABLE;
124 ret = drm_dp_dpcd_writeb(&dp->aux, DP_PSR_EN_CFG, psr_en);
125 if (ret != 1) {
126 dev_err(dp->dev, "failed to disable panel psr\n");
127 goto end;
128 }
129
130 /* Main-Link transmitter remains active during PSR active states */
131 psr_en = DP_PSR_CRC_VERIFICATION;
132 ret = drm_dp_dpcd_writeb(&dp->aux, DP_PSR_EN_CFG, psr_en);
133 if (ret != 1) {
134 dev_err(dp->dev, "failed to set panel psr\n");
135 goto end;
136 }
137
138 /* Enable psr function */
139 psr_en = DP_PSR_ENABLE | DP_PSR_CRC_VERIFICATION;
140 ret = drm_dp_dpcd_writeb(&dp->aux, DP_PSR_EN_CFG, psr_en);
141 if (ret != 1) {
142 dev_err(dp->dev, "failed to set panel psr\n");
143 goto end;
144 }
145
146 analogix_dp_enable_psr_crc(dp);
147
148 dp->psr_supported = true;
149
150 return 0;
151 end:
152 dev_err(dp->dev, "enable psr fail, force to disable psr\n");
153
154 return ret;
155 }
156
157 static int
analogix_dp_enable_rx_to_enhanced_mode(struct analogix_dp_device * dp,bool enable)158 analogix_dp_enable_rx_to_enhanced_mode(struct analogix_dp_device *dp,
159 bool enable)
160 {
161 u8 data;
162 int ret;
163
164 ret = drm_dp_dpcd_readb(&dp->aux, DP_LANE_COUNT_SET, &data);
165 if (ret != 1)
166 return ret;
167
168 if (enable)
169 ret = drm_dp_dpcd_writeb(&dp->aux, DP_LANE_COUNT_SET,
170 DP_LANE_COUNT_ENHANCED_FRAME_EN |
171 DPCD_LANE_COUNT_SET(data));
172 else
173 ret = drm_dp_dpcd_writeb(&dp->aux, DP_LANE_COUNT_SET,
174 DPCD_LANE_COUNT_SET(data));
175
176 return ret < 0 ? ret : 0;
177 }
178
analogix_dp_is_enhanced_mode_available(struct analogix_dp_device * dp,u8 * enhanced_mode_support)179 static int analogix_dp_is_enhanced_mode_available(struct analogix_dp_device *dp,
180 u8 *enhanced_mode_support)
181 {
182 u8 data;
183 int ret;
184
185 ret = drm_dp_dpcd_readb(&dp->aux, DP_MAX_LANE_COUNT, &data);
186 if (ret != 1) {
187 *enhanced_mode_support = 0;
188 return ret;
189 }
190
191 *enhanced_mode_support = DPCD_ENHANCED_FRAME_CAP(data);
192
193 return 0;
194 }
195
analogix_dp_set_enhanced_mode(struct analogix_dp_device * dp)196 static int analogix_dp_set_enhanced_mode(struct analogix_dp_device *dp)
197 {
198 u8 data;
199 int ret;
200
201 ret = analogix_dp_is_enhanced_mode_available(dp, &data);
202 if (ret < 0)
203 return ret;
204
205 ret = analogix_dp_enable_rx_to_enhanced_mode(dp, data);
206 if (ret < 0)
207 return ret;
208
209 analogix_dp_enable_enhanced_mode(dp, data);
210
211 return 0;
212 }
213
analogix_dp_training_pattern_dis(struct analogix_dp_device * dp)214 static int analogix_dp_training_pattern_dis(struct analogix_dp_device *dp)
215 {
216 int ret;
217
218 analogix_dp_set_training_pattern(dp, DP_NONE);
219
220 ret = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET,
221 DP_TRAINING_PATTERN_DISABLE);
222
223 return ret < 0 ? ret : 0;
224 }
225
analogix_dp_link_start(struct analogix_dp_device * dp)226 static int analogix_dp_link_start(struct analogix_dp_device *dp)
227 {
228 u8 buf[4];
229 int lane, lane_count, retval;
230
231 lane_count = dp->link_train.lane_count;
232
233 dp->link_train.lt_state = CLOCK_RECOVERY;
234 dp->link_train.eq_loop = 0;
235
236 for (lane = 0; lane < lane_count; lane++)
237 dp->link_train.cr_loop[lane] = 0;
238
239 /* Set link rate and count as you want to establish*/
240 analogix_dp_set_link_bandwidth(dp, dp->link_train.link_rate);
241 retval = analogix_dp_wait_pll_locked(dp);
242 if (retval) {
243 DRM_DEV_ERROR(dp->dev, "Wait for pll lock failed %d\n", retval);
244 return retval;
245 }
246 /*
247 * MACRO_RST must be applied after the PLL_LOCK to avoid
248 * the DP inter pair skew issue for at least 10 us
249 */
250 analogix_dp_reset_macro(dp);
251 analogix_dp_set_lane_count(dp, dp->link_train.lane_count);
252
253 /* Setup RX configuration */
254 buf[0] = dp->link_train.link_rate;
255 buf[1] = dp->link_train.lane_count;
256 retval = drm_dp_dpcd_write(&dp->aux, DP_LINK_BW_SET, buf, 2);
257 if (retval < 0)
258 return retval;
259 /* set enhanced mode if available */
260 retval = analogix_dp_set_enhanced_mode(dp);
261 if (retval < 0) {
262 dev_err(dp->dev, "failed to set enhance mode\n");
263 return retval;
264 }
265
266 /* Set TX voltage-swing and pre-emphasis to minimum */
267 for (lane = 0; lane < lane_count; lane++)
268 dp->link_train.training_lane[lane] =
269 DP_TRAIN_VOLTAGE_SWING_LEVEL_0 |
270 DP_TRAIN_PRE_EMPH_LEVEL_0;
271 analogix_dp_set_lane_link_training(dp);
272
273 /* Set training pattern 1 */
274 analogix_dp_set_training_pattern(dp, TRAINING_PTN1);
275
276 /* Set RX training pattern */
277 retval = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET,
278 DP_LINK_SCRAMBLING_DISABLE |
279 DP_TRAINING_PATTERN_1);
280 if (retval < 0)
281 return retval;
282
283 for (lane = 0; lane < lane_count; lane++)
284 buf[lane] = DP_TRAIN_PRE_EMPH_LEVEL_0 |
285 DP_TRAIN_VOLTAGE_SWING_LEVEL_0;
286
287 retval = drm_dp_dpcd_write(&dp->aux, DP_TRAINING_LANE0_SET, buf,
288 lane_count);
289 if (retval < 0)
290 return retval;
291
292 return 0;
293 }
294
analogix_dp_get_lane_status(u8 link_status[2],int lane)295 static unsigned char analogix_dp_get_lane_status(u8 link_status[2], int lane)
296 {
297 int shift = (lane & 1) * 4;
298 u8 link_value = link_status[lane >> 1];
299
300 return (link_value >> shift) & 0xf;
301 }
302
analogix_dp_clock_recovery_ok(u8 link_status[2],int lane_count)303 static int analogix_dp_clock_recovery_ok(u8 link_status[2], int lane_count)
304 {
305 int lane;
306 u8 lane_status;
307
308 for (lane = 0; lane < lane_count; lane++) {
309 lane_status = analogix_dp_get_lane_status(link_status, lane);
310 if ((lane_status & DP_LANE_CR_DONE) == 0)
311 return -EINVAL;
312 }
313 return 0;
314 }
315
analogix_dp_channel_eq_ok(u8 link_status[2],u8 link_align,int lane_count)316 static int analogix_dp_channel_eq_ok(u8 link_status[2], u8 link_align,
317 int lane_count)
318 {
319 int lane;
320 u8 lane_status;
321
322 if ((link_align & DP_INTERLANE_ALIGN_DONE) == 0)
323 return -EINVAL;
324
325 for (lane = 0; lane < lane_count; lane++) {
326 lane_status = analogix_dp_get_lane_status(link_status, lane);
327 lane_status &= DP_CHANNEL_EQ_BITS;
328 if (lane_status != DP_CHANNEL_EQ_BITS)
329 return -EINVAL;
330 }
331
332 return 0;
333 }
334
335 static unsigned char
analogix_dp_get_adjust_request_voltage(u8 adjust_request[2],int lane)336 analogix_dp_get_adjust_request_voltage(u8 adjust_request[2], int lane)
337 {
338 int shift = (lane & 1) * 4;
339 u8 link_value = adjust_request[lane >> 1];
340
341 return (link_value >> shift) & 0x3;
342 }
343
analogix_dp_get_adjust_request_pre_emphasis(u8 adjust_request[2],int lane)344 static unsigned char analogix_dp_get_adjust_request_pre_emphasis(
345 u8 adjust_request[2],
346 int lane)
347 {
348 int shift = (lane & 1) * 4;
349 u8 link_value = adjust_request[lane >> 1];
350
351 return ((link_value >> shift) & 0xc) >> 2;
352 }
353
analogix_dp_reduce_link_rate(struct analogix_dp_device * dp)354 static void analogix_dp_reduce_link_rate(struct analogix_dp_device *dp)
355 {
356 analogix_dp_training_pattern_dis(dp);
357 analogix_dp_set_enhanced_mode(dp);
358
359 dp->link_train.lt_state = FAILED;
360 }
361
analogix_dp_get_adjust_training_lane(struct analogix_dp_device * dp,u8 adjust_request[2])362 static void analogix_dp_get_adjust_training_lane(struct analogix_dp_device *dp,
363 u8 adjust_request[2])
364 {
365 int lane, lane_count;
366 u8 voltage_swing, pre_emphasis, training_lane;
367
368 lane_count = dp->link_train.lane_count;
369 for (lane = 0; lane < lane_count; lane++) {
370 voltage_swing = analogix_dp_get_adjust_request_voltage(
371 adjust_request, lane);
372 pre_emphasis = analogix_dp_get_adjust_request_pre_emphasis(
373 adjust_request, lane);
374 training_lane = DPCD_VOLTAGE_SWING_SET(voltage_swing) |
375 DPCD_PRE_EMPHASIS_SET(pre_emphasis);
376
377 if (voltage_swing == VOLTAGE_LEVEL_3)
378 training_lane |= DP_TRAIN_MAX_SWING_REACHED;
379 if (pre_emphasis == PRE_EMPHASIS_LEVEL_3)
380 training_lane |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
381
382 dp->link_train.training_lane[lane] = training_lane;
383 }
384 }
385
analogix_dp_process_clock_recovery(struct analogix_dp_device * dp)386 static int analogix_dp_process_clock_recovery(struct analogix_dp_device *dp)
387 {
388 int lane, lane_count, retval;
389 u8 voltage_swing, pre_emphasis, training_lane;
390 u8 link_status[2], adjust_request[2];
391
392 usleep_range(100, 101);
393
394 lane_count = dp->link_train.lane_count;
395
396 retval = drm_dp_dpcd_read(&dp->aux, DP_LANE0_1_STATUS, link_status, 2);
397 if (retval < 0)
398 return retval;
399
400 if (analogix_dp_clock_recovery_ok(link_status, lane_count) == 0) {
401 /* set training pattern 2 for EQ */
402 analogix_dp_set_training_pattern(dp, TRAINING_PTN2);
403
404 retval = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET,
405 DP_LINK_SCRAMBLING_DISABLE |
406 DP_TRAINING_PATTERN_2);
407 if (retval < 0)
408 return retval;
409
410 dev_dbg(dp->dev, "Link Training Clock Recovery success\n");
411 dp->link_train.lt_state = EQUALIZER_TRAINING;
412
413 return 0;
414 }
415
416 retval = drm_dp_dpcd_read(&dp->aux, DP_ADJUST_REQUEST_LANE0_1,
417 adjust_request, 2);
418 if (retval < 0)
419 return retval;
420
421 for (lane = 0; lane < lane_count; lane++) {
422 training_lane = analogix_dp_get_lane_link_training(dp, lane);
423 voltage_swing = analogix_dp_get_adjust_request_voltage(adjust_request, lane);
424 pre_emphasis = analogix_dp_get_adjust_request_pre_emphasis(adjust_request, lane);
425
426 if (DPCD_VOLTAGE_SWING_GET(training_lane) == voltage_swing &&
427 DPCD_PRE_EMPHASIS_GET(training_lane) == pre_emphasis)
428 dp->link_train.cr_loop[lane]++;
429
430 if (dp->link_train.cr_loop[lane] == MAX_CR_LOOP ||
431 voltage_swing == VOLTAGE_LEVEL_3 ||
432 pre_emphasis == PRE_EMPHASIS_LEVEL_3) {
433 dev_err(dp->dev, "CR Max reached (%d,%d,%d)\n",
434 dp->link_train.cr_loop[lane],
435 voltage_swing, pre_emphasis);
436 analogix_dp_reduce_link_rate(dp);
437 return -EIO;
438 }
439 }
440
441 analogix_dp_get_adjust_training_lane(dp, adjust_request);
442 analogix_dp_set_lane_link_training(dp);
443
444 retval = drm_dp_dpcd_write(&dp->aux, DP_TRAINING_LANE0_SET,
445 dp->link_train.training_lane, lane_count);
446 if (retval < 0)
447 return retval;
448
449 return 0;
450 }
451
analogix_dp_process_equalizer_training(struct analogix_dp_device * dp)452 static int analogix_dp_process_equalizer_training(struct analogix_dp_device *dp)
453 {
454 int lane_count, retval;
455 u32 reg;
456 u8 link_align, link_status[2], adjust_request[2];
457
458 usleep_range(400, 401);
459
460 lane_count = dp->link_train.lane_count;
461
462 retval = drm_dp_dpcd_read(&dp->aux, DP_LANE0_1_STATUS, link_status, 2);
463 if (retval < 0)
464 return retval;
465
466 if (analogix_dp_clock_recovery_ok(link_status, lane_count)) {
467 analogix_dp_reduce_link_rate(dp);
468 return -EIO;
469 }
470
471 retval = drm_dp_dpcd_read(&dp->aux, DP_ADJUST_REQUEST_LANE0_1,
472 adjust_request, 2);
473 if (retval < 0)
474 return retval;
475
476 retval = drm_dp_dpcd_readb(&dp->aux, DP_LANE_ALIGN_STATUS_UPDATED,
477 &link_align);
478 if (retval < 0)
479 return retval;
480
481 analogix_dp_get_adjust_training_lane(dp, adjust_request);
482
483 if (!analogix_dp_channel_eq_ok(link_status, link_align, lane_count)) {
484 /* traing pattern Set to Normal */
485 retval = analogix_dp_training_pattern_dis(dp);
486 if (retval < 0)
487 return retval;
488
489 dev_dbg(dp->dev, "Link Training success!\n");
490 analogix_dp_get_link_bandwidth(dp, ®);
491 dp->link_train.link_rate = reg;
492 dev_dbg(dp->dev, "final bandwidth = %.2x\n",
493 dp->link_train.link_rate);
494
495 analogix_dp_get_lane_count(dp, ®);
496 dp->link_train.lane_count = reg;
497 dev_dbg(dp->dev, "final lane count = %.2x\n",
498 dp->link_train.lane_count);
499
500 dp->link_train.lt_state = FINISHED;
501
502 return 0;
503 }
504
505 /* not all locked */
506 dp->link_train.eq_loop++;
507
508 if (dp->link_train.eq_loop > MAX_EQ_LOOP) {
509 dev_err(dp->dev, "EQ Max loop\n");
510 analogix_dp_reduce_link_rate(dp);
511 return -EIO;
512 }
513
514 analogix_dp_set_lane_link_training(dp);
515
516 retval = drm_dp_dpcd_write(&dp->aux, DP_TRAINING_LANE0_SET,
517 dp->link_train.training_lane, lane_count);
518 if (retval < 0)
519 return retval;
520
521 return 0;
522 }
523
analogix_dp_get_max_rx_bandwidth(struct analogix_dp_device * dp,u8 * bandwidth)524 static void analogix_dp_get_max_rx_bandwidth(struct analogix_dp_device *dp,
525 u8 *bandwidth)
526 {
527 u8 data;
528
529 /*
530 * For DP rev.1.1, Maximum link rate of Main Link lanes
531 * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps
532 * For DP rev.1.2, Maximum link rate of Main Link lanes
533 * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps, 0x14 = 5.4Gbps
534 */
535 drm_dp_dpcd_readb(&dp->aux, DP_MAX_LINK_RATE, &data);
536 *bandwidth = data;
537 }
538
analogix_dp_get_max_rx_lane_count(struct analogix_dp_device * dp,u8 * lane_count)539 static void analogix_dp_get_max_rx_lane_count(struct analogix_dp_device *dp,
540 u8 *lane_count)
541 {
542 u8 data;
543
544 /*
545 * For DP rev.1.1, Maximum number of Main Link lanes
546 * 0x01 = 1 lane, 0x02 = 2 lanes, 0x04 = 4 lanes
547 */
548 drm_dp_dpcd_readb(&dp->aux, DP_MAX_LANE_COUNT, &data);
549 *lane_count = DPCD_MAX_LANE_COUNT(data);
550 }
551
analogix_dp_full_link_train(struct analogix_dp_device * dp,u32 max_lanes,u32 max_rate)552 static int analogix_dp_full_link_train(struct analogix_dp_device *dp,
553 u32 max_lanes, u32 max_rate)
554 {
555 int retval = 0;
556 bool training_finished = false;
557
558 /* Initialize by reading RX's DPCD */
559 analogix_dp_get_max_rx_bandwidth(dp, &dp->link_train.link_rate);
560 analogix_dp_get_max_rx_lane_count(dp, &dp->link_train.lane_count);
561
562 if ((dp->link_train.link_rate != DP_LINK_BW_1_62) &&
563 (dp->link_train.link_rate != DP_LINK_BW_2_7) &&
564 (dp->link_train.link_rate != DP_LINK_BW_5_4)) {
565 dev_err(dp->dev, "Rx Max Link Rate is abnormal :%x !\n",
566 dp->link_train.link_rate);
567 dp->link_train.link_rate = DP_LINK_BW_1_62;
568 }
569
570 if (dp->link_train.lane_count == 0) {
571 dev_err(dp->dev, "Rx Max Lane count is abnormal :%x !\n",
572 dp->link_train.lane_count);
573 dp->link_train.lane_count = (u8)LANE_COUNT1;
574 }
575
576 /* Setup TX lane count & rate */
577 if (dp->link_train.lane_count > max_lanes)
578 dp->link_train.lane_count = max_lanes;
579 if (dp->link_train.link_rate > max_rate)
580 dp->link_train.link_rate = max_rate;
581
582 /* All DP analog module power up */
583 analogix_dp_set_analog_power_down(dp, POWER_ALL, 0);
584
585 dp->link_train.lt_state = START;
586
587 /* Process here */
588 while (!retval && !training_finished) {
589 switch (dp->link_train.lt_state) {
590 case START:
591 retval = analogix_dp_link_start(dp);
592 if (retval)
593 dev_err(dp->dev, "LT link start failed!\n");
594 break;
595 case CLOCK_RECOVERY:
596 retval = analogix_dp_process_clock_recovery(dp);
597 if (retval)
598 dev_err(dp->dev, "LT CR failed!\n");
599 break;
600 case EQUALIZER_TRAINING:
601 retval = analogix_dp_process_equalizer_training(dp);
602 if (retval)
603 dev_err(dp->dev, "LT EQ failed!\n");
604 break;
605 case FINISHED:
606 training_finished = 1;
607 break;
608 case FAILED:
609 return -EREMOTEIO;
610 }
611 }
612 if (retval)
613 dev_err(dp->dev, "eDP link training failed (%d)\n", retval);
614
615 return retval;
616 }
617
analogix_dp_fast_link_train(struct analogix_dp_device * dp)618 static int analogix_dp_fast_link_train(struct analogix_dp_device *dp)
619 {
620 int ret;
621 u8 link_align, link_status[2];
622
623 analogix_dp_set_link_bandwidth(dp, dp->link_train.link_rate);
624 ret = analogix_dp_wait_pll_locked(dp);
625 if (ret) {
626 DRM_DEV_ERROR(dp->dev, "Wait for pll lock failed %d\n", ret);
627 return ret;
628 }
629
630 /*
631 * MACRO_RST must be applied after the PLL_LOCK to avoid
632 * the DP inter pair skew issue for at least 10 us
633 */
634 analogix_dp_reset_macro(dp);
635 analogix_dp_set_lane_count(dp, dp->link_train.lane_count);
636 analogix_dp_set_lane_link_training(dp);
637
638 /* source Set training pattern 1 */
639 analogix_dp_set_training_pattern(dp, TRAINING_PTN1);
640 /* From DP spec, pattern must be on-screen for a minimum 500us */
641 usleep_range(500, 600);
642
643 analogix_dp_set_training_pattern(dp, TRAINING_PTN2);
644 /* From DP spec, pattern must be on-screen for a minimum 500us */
645 usleep_range(500, 600);
646
647 /* TODO: enhanced_mode?*/
648 analogix_dp_set_training_pattern(dp, DP_NONE);
649
650 /*
651 * Useful for debugging issues with fast link training, disable for more
652 * speed
653 */
654 if (verify_fast_training) {
655 ret = drm_dp_dpcd_readb(&dp->aux, DP_LANE_ALIGN_STATUS_UPDATED,
656 &link_align);
657 if (ret < 0) {
658 DRM_DEV_ERROR(dp->dev, "Read align status failed %d\n",
659 ret);
660 return ret;
661 }
662
663 ret = drm_dp_dpcd_read(&dp->aux, DP_LANE0_1_STATUS, link_status,
664 2);
665 if (ret < 0) {
666 DRM_DEV_ERROR(dp->dev, "Read link status failed %d\n",
667 ret);
668 return ret;
669 }
670
671 if (analogix_dp_clock_recovery_ok(link_status,
672 dp->link_train.lane_count)) {
673 DRM_DEV_ERROR(dp->dev, "Clock recovery failed\n");
674 analogix_dp_reduce_link_rate(dp);
675 return -EIO;
676 }
677
678 if (analogix_dp_channel_eq_ok(link_status, link_align,
679 dp->link_train.lane_count)) {
680 DRM_DEV_ERROR(dp->dev, "Channel EQ failed\n");
681 analogix_dp_reduce_link_rate(dp);
682 return -EIO;
683 }
684 }
685
686 return 0;
687 }
688
analogix_dp_train_link(struct analogix_dp_device * dp)689 static int analogix_dp_train_link(struct analogix_dp_device *dp)
690 {
691 if (dp->fast_train_enable)
692 return analogix_dp_fast_link_train(dp);
693
694 return analogix_dp_full_link_train(dp, dp->video_info.max_lane_count,
695 dp->video_info.max_link_rate);
696 }
697
analogix_dp_config_video(struct analogix_dp_device * dp)698 static int analogix_dp_config_video(struct analogix_dp_device *dp)
699 {
700 int timeout_loop = 0;
701 int done_count = 0;
702
703 analogix_dp_config_video_slave_mode(dp);
704
705 analogix_dp_set_video_color_format(dp);
706
707 for (;;) {
708 timeout_loop++;
709 if (analogix_dp_is_slave_video_stream_clock_on(dp) == 0)
710 break;
711 if (timeout_loop > DP_TIMEOUT_LOOP_COUNT) {
712 dev_err(dp->dev, "Timeout of slave video streamclk ok\n");
713 return -ETIMEDOUT;
714 }
715 usleep_range(1000, 1001);
716 }
717
718 /* Set to use the register calculated M/N video */
719 analogix_dp_set_video_cr_mn(dp, CALCULATED_M, 0, 0);
720
721 /* For video bist, Video timing must be generated by register */
722 analogix_dp_set_video_timing_mode(dp, VIDEO_TIMING_FROM_CAPTURE);
723
724 /* Disable video mute */
725 analogix_dp_enable_video_mute(dp, 0);
726
727 /* Configure video slave mode */
728 analogix_dp_enable_video_master(dp, 0);
729
730 /* Enable video */
731 analogix_dp_start_video(dp);
732
733 timeout_loop = 0;
734
735 for (;;) {
736 timeout_loop++;
737 if (analogix_dp_is_video_stream_on(dp) == 0) {
738 done_count++;
739 if (done_count > 10)
740 break;
741 } else if (done_count) {
742 done_count = 0;
743 }
744 if (timeout_loop > DP_TIMEOUT_LOOP_COUNT) {
745 dev_warn(dp->dev,
746 "Ignoring timeout of video streamclk ok\n");
747 break;
748 }
749
750 usleep_range(1000, 1001);
751 }
752
753 return 0;
754 }
755
analogix_dp_enable_scramble(struct analogix_dp_device * dp,bool enable)756 static int analogix_dp_enable_scramble(struct analogix_dp_device *dp,
757 bool enable)
758 {
759 u8 data;
760 int ret;
761
762 if (enable) {
763 analogix_dp_enable_scrambling(dp);
764
765 ret = drm_dp_dpcd_readb(&dp->aux, DP_TRAINING_PATTERN_SET,
766 &data);
767 if (ret != 1)
768 return ret;
769 ret = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET,
770 (u8)(data & ~DP_LINK_SCRAMBLING_DISABLE));
771 } else {
772 analogix_dp_disable_scrambling(dp);
773
774 ret = drm_dp_dpcd_readb(&dp->aux, DP_TRAINING_PATTERN_SET,
775 &data);
776 if (ret != 1)
777 return ret;
778 ret = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET,
779 (u8)(data | DP_LINK_SCRAMBLING_DISABLE));
780 }
781 return ret < 0 ? ret : 0;
782 }
783
analogix_dp_hardirq(int irq,void * arg)784 static irqreturn_t analogix_dp_hardirq(int irq, void *arg)
785 {
786 struct analogix_dp_device *dp = arg;
787 irqreturn_t ret = IRQ_NONE;
788 enum dp_irq_type irq_type;
789
790 irq_type = analogix_dp_get_irq_type(dp);
791 if (irq_type != DP_IRQ_TYPE_UNKNOWN) {
792 analogix_dp_mute_hpd_interrupt(dp);
793 ret = IRQ_WAKE_THREAD;
794 }
795
796 return ret;
797 }
798
analogix_dp_irq_thread(int irq,void * arg)799 static irqreturn_t analogix_dp_irq_thread(int irq, void *arg)
800 {
801 struct analogix_dp_device *dp = arg;
802 enum dp_irq_type irq_type;
803
804 irq_type = analogix_dp_get_irq_type(dp);
805 if (irq_type & DP_IRQ_TYPE_HP_CABLE_IN ||
806 irq_type & DP_IRQ_TYPE_HP_CABLE_OUT) {
807 dev_dbg(dp->dev, "Detected cable status changed!\n");
808 if (dp->drm_dev)
809 drm_helper_hpd_irq_event(dp->drm_dev);
810 }
811
812 if (irq_type != DP_IRQ_TYPE_UNKNOWN) {
813 analogix_dp_clear_hotplug_interrupts(dp);
814 analogix_dp_unmute_hpd_interrupt(dp);
815 }
816
817 return IRQ_HANDLED;
818 }
819
analogix_dp_fast_link_train_detection(struct analogix_dp_device * dp)820 static int analogix_dp_fast_link_train_detection(struct analogix_dp_device *dp)
821 {
822 int ret;
823 u8 spread;
824
825 ret = drm_dp_dpcd_readb(&dp->aux, DP_MAX_DOWNSPREAD, &spread);
826 if (ret != 1) {
827 dev_err(dp->dev, "failed to read downspread %d\n", ret);
828 return ret;
829 }
830 dp->fast_train_enable = !!(spread & DP_NO_AUX_HANDSHAKE_LINK_TRAINING);
831 dev_dbg(dp->dev, "fast link training %s\n",
832 dp->fast_train_enable ? "supported" : "unsupported");
833 return 0;
834 }
835
analogix_dp_commit(struct analogix_dp_device * dp)836 static int analogix_dp_commit(struct analogix_dp_device *dp)
837 {
838 int ret;
839
840 /* Keep the panel disabled while we configure video */
841 drm_panel_disable(dp->plat_data->panel);
842
843 ret = analogix_dp_train_link(dp);
844 if (ret) {
845 dev_err(dp->dev, "unable to do link train, ret=%d\n", ret);
846 return ret;
847 }
848
849 ret = analogix_dp_enable_scramble(dp, 1);
850 if (ret < 0) {
851 dev_err(dp->dev, "can not enable scramble\n");
852 return ret;
853 }
854
855 analogix_dp_init_video(dp);
856 ret = analogix_dp_config_video(dp);
857 if (ret) {
858 dev_err(dp->dev, "unable to config video\n");
859 return ret;
860 }
861
862 /* Safe to enable the panel now */
863 drm_panel_enable(dp->plat_data->panel);
864
865 /* Check whether panel supports fast training */
866 ret = analogix_dp_fast_link_train_detection(dp);
867 if (ret)
868 return ret;
869
870 if (analogix_dp_detect_sink_psr(dp)) {
871 ret = analogix_dp_enable_sink_psr(dp);
872 if (ret)
873 return ret;
874 }
875
876 return ret;
877 }
878
analogix_dp_enable_psr(struct analogix_dp_device * dp)879 static int analogix_dp_enable_psr(struct analogix_dp_device *dp)
880 {
881 struct dp_sdp psr_vsc;
882 int ret;
883 u8 sink;
884
885 ret = drm_dp_dpcd_readb(&dp->aux, DP_PSR_STATUS, &sink);
886 if (ret != 1)
887 DRM_DEV_ERROR(dp->dev, "Failed to read psr status %d\n", ret);
888 else if (sink == DP_PSR_SINK_ACTIVE_RFB)
889 return 0;
890
891 /* Prepare VSC packet as per EDP 1.4 spec, Table 6.9 */
892 memset(&psr_vsc, 0, sizeof(psr_vsc));
893 psr_vsc.sdp_header.HB0 = 0;
894 psr_vsc.sdp_header.HB1 = 0x7;
895 psr_vsc.sdp_header.HB2 = 0x2;
896 psr_vsc.sdp_header.HB3 = 0x8;
897 psr_vsc.db[0] = 0;
898 psr_vsc.db[1] = EDP_VSC_PSR_STATE_ACTIVE | EDP_VSC_PSR_CRC_VALUES_VALID;
899
900 ret = analogix_dp_send_psr_spd(dp, &psr_vsc, true);
901 if (!ret)
902 analogix_dp_set_analog_power_down(dp, POWER_ALL, true);
903
904 return ret;
905 }
906
analogix_dp_disable_psr(struct analogix_dp_device * dp)907 static int analogix_dp_disable_psr(struct analogix_dp_device *dp)
908 {
909 struct dp_sdp psr_vsc;
910 int ret;
911 u8 sink;
912
913 analogix_dp_set_analog_power_down(dp, POWER_ALL, false);
914
915 ret = drm_dp_dpcd_writeb(&dp->aux, DP_SET_POWER, DP_SET_POWER_D0);
916 if (ret != 1) {
917 DRM_DEV_ERROR(dp->dev, "Failed to set DP Power0 %d\n", ret);
918 return ret;
919 }
920
921 ret = drm_dp_dpcd_readb(&dp->aux, DP_PSR_STATUS, &sink);
922 if (ret != 1) {
923 DRM_DEV_ERROR(dp->dev, "Failed to read psr status %d\n", ret);
924 return ret;
925 } else if (sink == DP_PSR_SINK_INACTIVE) {
926 DRM_DEV_ERROR(dp->dev, "sink inactive, skip disable psr");
927 return 0;
928 }
929
930 ret = analogix_dp_train_link(dp);
931 if (ret) {
932 DRM_DEV_ERROR(dp->dev, "Failed to train the link %d\n", ret);
933 return ret;
934 }
935
936 /* Prepare VSC packet as per EDP 1.4 spec, Table 6.9 */
937 memset(&psr_vsc, 0, sizeof(psr_vsc));
938 psr_vsc.sdp_header.HB0 = 0;
939 psr_vsc.sdp_header.HB1 = 0x7;
940 psr_vsc.sdp_header.HB2 = 0x2;
941 psr_vsc.sdp_header.HB3 = 0x8;
942
943 psr_vsc.db[0] = 0;
944 psr_vsc.db[1] = 0;
945
946 return analogix_dp_send_psr_spd(dp, &psr_vsc, true);
947 }
948
analogix_dp_get_modes(struct drm_connector * connector)949 static int analogix_dp_get_modes(struct drm_connector *connector)
950 {
951 struct analogix_dp_device *dp = to_dp(connector);
952 const struct drm_edid *drm_edid;
953 int num_modes = 0;
954
955 if (dp->plat_data->panel) {
956 num_modes += drm_panel_get_modes(dp->plat_data->panel, connector);
957 } else {
958 drm_edid = drm_edid_read_ddc(connector, &dp->aux.ddc);
959
960 drm_edid_connector_update(&dp->connector, drm_edid);
961
962 if (drm_edid) {
963 num_modes += drm_edid_connector_add_modes(&dp->connector);
964 drm_edid_free(drm_edid);
965 }
966 }
967
968 if (dp->plat_data->get_modes)
969 num_modes += dp->plat_data->get_modes(dp->plat_data, connector);
970
971 return num_modes;
972 }
973
974 static struct drm_encoder *
analogix_dp_best_encoder(struct drm_connector * connector)975 analogix_dp_best_encoder(struct drm_connector *connector)
976 {
977 struct analogix_dp_device *dp = to_dp(connector);
978
979 return dp->encoder;
980 }
981
982
analogix_dp_atomic_check(struct drm_connector * connector,struct drm_atomic_state * state)983 static int analogix_dp_atomic_check(struct drm_connector *connector,
984 struct drm_atomic_state *state)
985 {
986 struct analogix_dp_device *dp = to_dp(connector);
987 struct drm_connector_state *conn_state;
988 struct drm_crtc_state *crtc_state;
989
990 conn_state = drm_atomic_get_new_connector_state(state, connector);
991 if (WARN_ON(!conn_state))
992 return -ENODEV;
993
994 conn_state->self_refresh_aware = true;
995
996 if (!conn_state->crtc)
997 return 0;
998
999 crtc_state = drm_atomic_get_new_crtc_state(state, conn_state->crtc);
1000 if (!crtc_state)
1001 return 0;
1002
1003 if (crtc_state->self_refresh_active && !dp->psr_supported)
1004 return -EINVAL;
1005
1006 return 0;
1007 }
1008
1009 static const struct drm_connector_helper_funcs analogix_dp_connector_helper_funcs = {
1010 .get_modes = analogix_dp_get_modes,
1011 .best_encoder = analogix_dp_best_encoder,
1012 .atomic_check = analogix_dp_atomic_check,
1013 };
1014
1015 static enum drm_connector_status
analogix_dp_detect(struct drm_connector * connector,bool force)1016 analogix_dp_detect(struct drm_connector *connector, bool force)
1017 {
1018 struct analogix_dp_device *dp = to_dp(connector);
1019 enum drm_connector_status status = connector_status_disconnected;
1020
1021 if (dp->plat_data->panel)
1022 return connector_status_connected;
1023
1024 if (!analogix_dp_detect_hpd(dp))
1025 status = connector_status_connected;
1026
1027 return status;
1028 }
1029
1030 static const struct drm_connector_funcs analogix_dp_connector_funcs = {
1031 .fill_modes = drm_helper_probe_single_connector_modes,
1032 .detect = analogix_dp_detect,
1033 .destroy = drm_connector_cleanup,
1034 .reset = drm_atomic_helper_connector_reset,
1035 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1036 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1037 };
1038
analogix_dp_bridge_attach(struct drm_bridge * bridge,struct drm_encoder * encoder,enum drm_bridge_attach_flags flags)1039 static int analogix_dp_bridge_attach(struct drm_bridge *bridge,
1040 struct drm_encoder *encoder,
1041 enum drm_bridge_attach_flags flags)
1042 {
1043 struct analogix_dp_device *dp = bridge->driver_private;
1044 struct drm_connector *connector = NULL;
1045 int ret = 0;
1046
1047 if (flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR) {
1048 DRM_ERROR("Fix bridge driver to make connector optional!");
1049 return -EINVAL;
1050 }
1051
1052 if (!dp->plat_data->skip_connector) {
1053 connector = &dp->connector;
1054 connector->polled = DRM_CONNECTOR_POLL_HPD;
1055
1056 ret = drm_connector_init(dp->drm_dev, connector,
1057 &analogix_dp_connector_funcs,
1058 DRM_MODE_CONNECTOR_eDP);
1059 if (ret) {
1060 DRM_ERROR("Failed to initialize connector with drm\n");
1061 return ret;
1062 }
1063
1064 drm_connector_helper_add(connector,
1065 &analogix_dp_connector_helper_funcs);
1066 drm_connector_attach_encoder(connector, encoder);
1067 }
1068
1069 /*
1070 * NOTE: the connector registration is implemented in analogix
1071 * platform driver, that to say connector would be exist after
1072 * plat_data->attch return, that's why we record the connector
1073 * point after plat attached.
1074 */
1075 if (dp->plat_data->attach) {
1076 ret = dp->plat_data->attach(dp->plat_data, bridge, connector);
1077 if (ret) {
1078 DRM_ERROR("Failed at platform attach func\n");
1079 return ret;
1080 }
1081 }
1082
1083 return 0;
1084 }
1085
1086 static
analogix_dp_get_old_crtc(struct analogix_dp_device * dp,struct drm_atomic_state * state)1087 struct drm_crtc *analogix_dp_get_old_crtc(struct analogix_dp_device *dp,
1088 struct drm_atomic_state *state)
1089 {
1090 struct drm_encoder *encoder = dp->encoder;
1091 struct drm_connector *connector;
1092 struct drm_connector_state *conn_state;
1093
1094 connector = drm_atomic_get_old_connector_for_encoder(state, encoder);
1095 if (!connector)
1096 return NULL;
1097
1098 conn_state = drm_atomic_get_old_connector_state(state, connector);
1099 if (!conn_state)
1100 return NULL;
1101
1102 return conn_state->crtc;
1103 }
1104
1105 static
analogix_dp_get_new_crtc(struct analogix_dp_device * dp,struct drm_atomic_state * state)1106 struct drm_crtc *analogix_dp_get_new_crtc(struct analogix_dp_device *dp,
1107 struct drm_atomic_state *state)
1108 {
1109 struct drm_encoder *encoder = dp->encoder;
1110 struct drm_connector *connector;
1111 struct drm_connector_state *conn_state;
1112
1113 connector = drm_atomic_get_new_connector_for_encoder(state, encoder);
1114 if (!connector)
1115 return NULL;
1116
1117 conn_state = drm_atomic_get_new_connector_state(state, connector);
1118 if (!conn_state)
1119 return NULL;
1120
1121 return conn_state->crtc;
1122 }
1123
analogix_dp_bridge_atomic_pre_enable(struct drm_bridge * bridge,struct drm_atomic_state * old_state)1124 static void analogix_dp_bridge_atomic_pre_enable(struct drm_bridge *bridge,
1125 struct drm_atomic_state *old_state)
1126 {
1127 struct analogix_dp_device *dp = bridge->driver_private;
1128 struct drm_crtc *crtc;
1129 struct drm_crtc_state *old_crtc_state;
1130
1131 crtc = analogix_dp_get_new_crtc(dp, old_state);
1132 if (!crtc)
1133 return;
1134
1135 old_crtc_state = drm_atomic_get_old_crtc_state(old_state, crtc);
1136 /* Don't touch the panel if we're coming back from PSR */
1137 if (old_crtc_state && old_crtc_state->self_refresh_active)
1138 return;
1139
1140 drm_panel_prepare(dp->plat_data->panel);
1141 }
1142
analogix_dp_set_bridge(struct analogix_dp_device * dp)1143 static int analogix_dp_set_bridge(struct analogix_dp_device *dp)
1144 {
1145 int ret;
1146
1147 pm_runtime_get_sync(dp->dev);
1148
1149 ret = analogix_dp_init_analog_func(dp);
1150 if (ret)
1151 return ret;
1152
1153 /*
1154 * According to DP spec v1.3 chap 3.5.1.2 Link Training,
1155 * We should first make sure the HPD signal is asserted high by device
1156 * when we want to establish a link with it.
1157 */
1158 ret = analogix_dp_detect_hpd(dp);
1159 if (ret) {
1160 DRM_ERROR("failed to get hpd single ret = %d\n", ret);
1161 goto out_dp_init;
1162 }
1163
1164 ret = analogix_dp_commit(dp);
1165 if (ret) {
1166 DRM_ERROR("dp commit error, ret = %d\n", ret);
1167 goto out_dp_init;
1168 }
1169
1170 enable_irq(dp->irq);
1171 return 0;
1172
1173 out_dp_init:
1174 pm_runtime_put_sync(dp->dev);
1175
1176 return ret;
1177 }
1178
analogix_dp_bridge_atomic_enable(struct drm_bridge * bridge,struct drm_atomic_state * old_state)1179 static void analogix_dp_bridge_atomic_enable(struct drm_bridge *bridge,
1180 struct drm_atomic_state *old_state)
1181 {
1182 struct analogix_dp_device *dp = bridge->driver_private;
1183 struct drm_crtc *crtc;
1184 struct drm_crtc_state *old_crtc_state;
1185 int timeout_loop = 0;
1186 int ret;
1187
1188 crtc = analogix_dp_get_new_crtc(dp, old_state);
1189 if (!crtc)
1190 return;
1191
1192 old_crtc_state = drm_atomic_get_old_crtc_state(old_state, crtc);
1193 /* Not a full enable, just disable PSR and continue */
1194 if (old_crtc_state && old_crtc_state->self_refresh_active) {
1195 ret = analogix_dp_disable_psr(dp);
1196 if (ret)
1197 DRM_ERROR("Failed to disable psr %d\n", ret);
1198 return;
1199 }
1200
1201 if (dp->dpms_mode == DRM_MODE_DPMS_ON)
1202 return;
1203
1204 while (timeout_loop < MAX_PLL_LOCK_LOOP) {
1205 if (analogix_dp_set_bridge(dp) == 0) {
1206 dp->dpms_mode = DRM_MODE_DPMS_ON;
1207 return;
1208 }
1209 dev_err(dp->dev, "failed to set bridge, retry: %d\n",
1210 timeout_loop);
1211 timeout_loop++;
1212 usleep_range(10, 11);
1213 }
1214 dev_err(dp->dev, "too many times retry set bridge, give it up\n");
1215 }
1216
analogix_dp_bridge_disable(struct drm_bridge * bridge)1217 static void analogix_dp_bridge_disable(struct drm_bridge *bridge)
1218 {
1219 struct analogix_dp_device *dp = bridge->driver_private;
1220
1221 if (dp->dpms_mode != DRM_MODE_DPMS_ON)
1222 return;
1223
1224 drm_panel_disable(dp->plat_data->panel);
1225
1226 disable_irq(dp->irq);
1227
1228 analogix_dp_set_analog_power_down(dp, POWER_ALL, 1);
1229
1230 pm_runtime_put_sync(dp->dev);
1231
1232 drm_panel_unprepare(dp->plat_data->panel);
1233
1234 dp->fast_train_enable = false;
1235 dp->psr_supported = false;
1236 dp->dpms_mode = DRM_MODE_DPMS_OFF;
1237 }
1238
analogix_dp_bridge_atomic_disable(struct drm_bridge * bridge,struct drm_atomic_state * old_state)1239 static void analogix_dp_bridge_atomic_disable(struct drm_bridge *bridge,
1240 struct drm_atomic_state *old_state)
1241 {
1242 struct analogix_dp_device *dp = bridge->driver_private;
1243 struct drm_crtc *old_crtc, *new_crtc;
1244 struct drm_crtc_state *old_crtc_state = NULL;
1245 struct drm_crtc_state *new_crtc_state = NULL;
1246 int ret;
1247
1248 new_crtc = analogix_dp_get_new_crtc(dp, old_state);
1249 if (!new_crtc)
1250 goto out;
1251
1252 new_crtc_state = drm_atomic_get_new_crtc_state(old_state, new_crtc);
1253 if (!new_crtc_state)
1254 goto out;
1255
1256 /* Don't do a full disable on PSR transitions */
1257 if (new_crtc_state->self_refresh_active)
1258 return;
1259
1260 out:
1261 old_crtc = analogix_dp_get_old_crtc(dp, old_state);
1262 if (old_crtc) {
1263 old_crtc_state = drm_atomic_get_old_crtc_state(old_state,
1264 old_crtc);
1265
1266 /* When moving from PSR to fully disabled, exit PSR first. */
1267 if (old_crtc_state && old_crtc_state->self_refresh_active) {
1268 ret = analogix_dp_disable_psr(dp);
1269 if (ret)
1270 DRM_ERROR("Failed to disable psr (%d)\n", ret);
1271 }
1272 }
1273
1274 analogix_dp_bridge_disable(bridge);
1275 }
1276
analogix_dp_bridge_atomic_post_disable(struct drm_bridge * bridge,struct drm_atomic_state * old_state)1277 static void analogix_dp_bridge_atomic_post_disable(struct drm_bridge *bridge,
1278 struct drm_atomic_state *old_state)
1279 {
1280 struct analogix_dp_device *dp = bridge->driver_private;
1281 struct drm_crtc *crtc;
1282 struct drm_crtc_state *new_crtc_state;
1283 int ret;
1284
1285 crtc = analogix_dp_get_new_crtc(dp, old_state);
1286 if (!crtc)
1287 return;
1288
1289 new_crtc_state = drm_atomic_get_new_crtc_state(old_state, crtc);
1290 if (!new_crtc_state || !new_crtc_state->self_refresh_active)
1291 return;
1292
1293 ret = analogix_dp_enable_psr(dp);
1294 if (ret)
1295 DRM_ERROR("Failed to enable psr (%d)\n", ret);
1296 }
1297
analogix_dp_bridge_mode_set(struct drm_bridge * bridge,const struct drm_display_mode * orig_mode,const struct drm_display_mode * mode)1298 static void analogix_dp_bridge_mode_set(struct drm_bridge *bridge,
1299 const struct drm_display_mode *orig_mode,
1300 const struct drm_display_mode *mode)
1301 {
1302 struct analogix_dp_device *dp = bridge->driver_private;
1303 struct drm_display_info *display_info = &dp->connector.display_info;
1304 struct video_info *video = &dp->video_info;
1305 struct device_node *dp_node = dp->dev->of_node;
1306 int vic;
1307
1308 /* Input video interlaces & hsync pol & vsync pol */
1309 video->interlaced = !!(mode->flags & DRM_MODE_FLAG_INTERLACE);
1310 video->v_sync_polarity = !!(mode->flags & DRM_MODE_FLAG_NVSYNC);
1311 video->h_sync_polarity = !!(mode->flags & DRM_MODE_FLAG_NHSYNC);
1312
1313 /* Input video dynamic_range & colorimetry */
1314 vic = drm_match_cea_mode(mode);
1315 if ((vic == 6) || (vic == 7) || (vic == 21) || (vic == 22) ||
1316 (vic == 2) || (vic == 3) || (vic == 17) || (vic == 18)) {
1317 video->dynamic_range = CEA;
1318 video->ycbcr_coeff = COLOR_YCBCR601;
1319 } else if (vic) {
1320 video->dynamic_range = CEA;
1321 video->ycbcr_coeff = COLOR_YCBCR709;
1322 } else {
1323 video->dynamic_range = VESA;
1324 video->ycbcr_coeff = COLOR_YCBCR709;
1325 }
1326
1327 /* Input vide bpc and color_formats */
1328 switch (display_info->bpc) {
1329 case 12:
1330 video->color_depth = COLOR_12;
1331 break;
1332 case 10:
1333 video->color_depth = COLOR_10;
1334 break;
1335 case 8:
1336 video->color_depth = COLOR_8;
1337 break;
1338 case 6:
1339 video->color_depth = COLOR_6;
1340 break;
1341 default:
1342 video->color_depth = COLOR_8;
1343 break;
1344 }
1345 if (display_info->color_formats & DRM_COLOR_FORMAT_YCBCR444)
1346 video->color_space = COLOR_YCBCR444;
1347 else if (display_info->color_formats & DRM_COLOR_FORMAT_YCBCR422)
1348 video->color_space = COLOR_YCBCR422;
1349 else
1350 video->color_space = COLOR_RGB;
1351
1352 /*
1353 * NOTE: those property parsing code is used for providing backward
1354 * compatibility for samsung platform.
1355 * Due to we used the "of_property_read_u32" interfaces, when this
1356 * property isn't present, the "video_info" can keep the original
1357 * values and wouldn't be modified.
1358 */
1359 of_property_read_u32(dp_node, "samsung,color-space",
1360 &video->color_space);
1361 of_property_read_u32(dp_node, "samsung,dynamic-range",
1362 &video->dynamic_range);
1363 of_property_read_u32(dp_node, "samsung,ycbcr-coeff",
1364 &video->ycbcr_coeff);
1365 of_property_read_u32(dp_node, "samsung,color-depth",
1366 &video->color_depth);
1367 if (of_property_read_bool(dp_node, "hsync-active-high"))
1368 video->h_sync_polarity = true;
1369 if (of_property_read_bool(dp_node, "vsync-active-high"))
1370 video->v_sync_polarity = true;
1371 if (of_property_read_bool(dp_node, "interlaced"))
1372 video->interlaced = true;
1373 }
1374
1375 static const struct drm_bridge_funcs analogix_dp_bridge_funcs = {
1376 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
1377 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
1378 .atomic_reset = drm_atomic_helper_bridge_reset,
1379 .atomic_pre_enable = analogix_dp_bridge_atomic_pre_enable,
1380 .atomic_enable = analogix_dp_bridge_atomic_enable,
1381 .atomic_disable = analogix_dp_bridge_atomic_disable,
1382 .atomic_post_disable = analogix_dp_bridge_atomic_post_disable,
1383 .mode_set = analogix_dp_bridge_mode_set,
1384 .attach = analogix_dp_bridge_attach,
1385 };
1386
analogix_dp_create_bridge(struct drm_device * drm_dev,struct analogix_dp_device * dp)1387 static int analogix_dp_create_bridge(struct drm_device *drm_dev,
1388 struct analogix_dp_device *dp)
1389 {
1390 struct drm_bridge *bridge;
1391
1392 bridge = devm_kzalloc(drm_dev->dev, sizeof(*bridge), GFP_KERNEL);
1393 if (!bridge) {
1394 DRM_ERROR("failed to allocate for drm bridge\n");
1395 return -ENOMEM;
1396 }
1397
1398 dp->bridge = bridge;
1399
1400 bridge->driver_private = dp;
1401 bridge->funcs = &analogix_dp_bridge_funcs;
1402
1403 return drm_bridge_attach(dp->encoder, bridge, NULL, 0);
1404 }
1405
analogix_dp_dt_parse_pdata(struct analogix_dp_device * dp)1406 static int analogix_dp_dt_parse_pdata(struct analogix_dp_device *dp)
1407 {
1408 struct device_node *dp_node = dp->dev->of_node;
1409 struct video_info *video_info = &dp->video_info;
1410
1411 switch (dp->plat_data->dev_type) {
1412 case RK3288_DP:
1413 case RK3399_EDP:
1414 /*
1415 * Like Rk3288 DisplayPort TRM indicate that "Main link
1416 * containing 4 physical lanes of 2.7/1.62 Gbps/lane".
1417 */
1418 video_info->max_link_rate = 0x0A;
1419 video_info->max_lane_count = 0x04;
1420 break;
1421 case RK3588_EDP:
1422 video_info->max_link_rate = 0x14;
1423 video_info->max_lane_count = 0x04;
1424 break;
1425 case EXYNOS_DP:
1426 /*
1427 * NOTE: those property parseing code is used for
1428 * providing backward compatibility for samsung platform.
1429 */
1430 of_property_read_u32(dp_node, "samsung,link-rate",
1431 &video_info->max_link_rate);
1432 of_property_read_u32(dp_node, "samsung,lane-count",
1433 &video_info->max_lane_count);
1434 break;
1435 }
1436
1437 return 0;
1438 }
1439
analogix_dpaux_transfer(struct drm_dp_aux * aux,struct drm_dp_aux_msg * msg)1440 static ssize_t analogix_dpaux_transfer(struct drm_dp_aux *aux,
1441 struct drm_dp_aux_msg *msg)
1442 {
1443 struct analogix_dp_device *dp = to_dp(aux);
1444 int ret;
1445
1446 pm_runtime_get_sync(dp->dev);
1447
1448 ret = analogix_dp_detect_hpd(dp);
1449 if (ret)
1450 goto out;
1451
1452 ret = analogix_dp_transfer(dp, msg);
1453 out:
1454 pm_runtime_mark_last_busy(dp->dev);
1455 pm_runtime_put_autosuspend(dp->dev);
1456
1457 return ret;
1458 }
1459
analogix_dpaux_wait_hpd_asserted(struct drm_dp_aux * aux,unsigned long wait_us)1460 static int analogix_dpaux_wait_hpd_asserted(struct drm_dp_aux *aux, unsigned long wait_us)
1461 {
1462 struct analogix_dp_device *dp = to_dp(aux);
1463 int val;
1464 int ret;
1465
1466 if (dp->force_hpd)
1467 return 0;
1468
1469 pm_runtime_get_sync(dp->dev);
1470
1471 ret = readx_poll_timeout(analogix_dp_get_plug_in_status, dp, val, !val,
1472 wait_us / 100, wait_us);
1473
1474 pm_runtime_mark_last_busy(dp->dev);
1475 pm_runtime_put_autosuspend(dp->dev);
1476
1477 return ret;
1478 }
1479
1480 struct analogix_dp_device *
analogix_dp_probe(struct device * dev,struct analogix_dp_plat_data * plat_data)1481 analogix_dp_probe(struct device *dev, struct analogix_dp_plat_data *plat_data)
1482 {
1483 struct platform_device *pdev = to_platform_device(dev);
1484 struct analogix_dp_device *dp;
1485 unsigned int irq_flags;
1486 int ret;
1487
1488 if (!plat_data) {
1489 dev_err(dev, "Invalided input plat_data\n");
1490 return ERR_PTR(-EINVAL);
1491 }
1492
1493 dp = devm_kzalloc(dev, sizeof(struct analogix_dp_device), GFP_KERNEL);
1494 if (!dp)
1495 return ERR_PTR(-ENOMEM);
1496
1497 dp->dev = &pdev->dev;
1498 dp->dpms_mode = DRM_MODE_DPMS_OFF;
1499
1500 /*
1501 * platform dp driver need containor_of the plat_data to get
1502 * the driver private data, so we need to store the point of
1503 * plat_data, not the context of plat_data.
1504 */
1505 dp->plat_data = plat_data;
1506
1507 ret = analogix_dp_dt_parse_pdata(dp);
1508 if (ret)
1509 return ERR_PTR(ret);
1510
1511 dp->phy = devm_phy_get(dp->dev, "dp");
1512 if (IS_ERR(dp->phy)) {
1513 dev_err(dp->dev, "no DP phy configured\n");
1514 ret = PTR_ERR(dp->phy);
1515 if (ret) {
1516 /*
1517 * phy itself is not enabled, so we can move forward
1518 * assigning NULL to phy pointer.
1519 */
1520 if (ret == -ENOSYS || ret == -ENODEV)
1521 dp->phy = NULL;
1522 else
1523 return ERR_PTR(ret);
1524 }
1525 }
1526
1527 dp->clock = devm_clk_get(&pdev->dev, "dp");
1528 if (IS_ERR(dp->clock)) {
1529 dev_err(&pdev->dev, "failed to get clock\n");
1530 return ERR_CAST(dp->clock);
1531 }
1532
1533 dp->reg_base = devm_platform_ioremap_resource(pdev, 0);
1534 if (IS_ERR(dp->reg_base))
1535 return ERR_CAST(dp->reg_base);
1536
1537 dp->force_hpd = of_property_read_bool(dev->of_node, "force-hpd");
1538
1539 /* Try two different names */
1540 dp->hpd_gpiod = devm_gpiod_get_optional(dev, "hpd", GPIOD_IN);
1541 if (!dp->hpd_gpiod)
1542 dp->hpd_gpiod = devm_gpiod_get_optional(dev, "samsung,hpd",
1543 GPIOD_IN);
1544 if (IS_ERR(dp->hpd_gpiod)) {
1545 dev_err(dev, "error getting HDP GPIO: %ld\n",
1546 PTR_ERR(dp->hpd_gpiod));
1547 return ERR_CAST(dp->hpd_gpiod);
1548 }
1549
1550 if (dp->hpd_gpiod) {
1551 /*
1552 * Set up the hotplug GPIO from the device tree as an interrupt.
1553 * Simply specifying a different interrupt in the device tree
1554 * doesn't work since we handle hotplug rather differently when
1555 * using a GPIO. We also need the actual GPIO specifier so
1556 * that we can get the current state of the GPIO.
1557 */
1558 dp->irq = gpiod_to_irq(dp->hpd_gpiod);
1559 irq_flags = IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING | IRQF_NO_AUTOEN;
1560 } else {
1561 dp->irq = platform_get_irq(pdev, 0);
1562 irq_flags = IRQF_NO_AUTOEN;
1563 }
1564
1565 if (dp->irq == -ENXIO) {
1566 dev_err(&pdev->dev, "failed to get irq\n");
1567 return ERR_PTR(-ENODEV);
1568 }
1569
1570 ret = devm_request_threaded_irq(&pdev->dev, dp->irq,
1571 analogix_dp_hardirq,
1572 analogix_dp_irq_thread,
1573 irq_flags, "analogix-dp", dp);
1574 if (ret) {
1575 dev_err(&pdev->dev, "failed to request irq\n");
1576 return ERR_PTR(ret);
1577 }
1578
1579 dp->aux.name = "DP-AUX";
1580 dp->aux.transfer = analogix_dpaux_transfer;
1581 dp->aux.wait_hpd_asserted = analogix_dpaux_wait_hpd_asserted;
1582 dp->aux.dev = dp->dev;
1583 drm_dp_aux_init(&dp->aux);
1584
1585 pm_runtime_use_autosuspend(dp->dev);
1586 pm_runtime_set_autosuspend_delay(dp->dev, 100);
1587 ret = devm_pm_runtime_enable(dp->dev);
1588 if (ret)
1589 return ERR_PTR(ret);
1590
1591 return dp;
1592 }
1593 EXPORT_SYMBOL_GPL(analogix_dp_probe);
1594
analogix_dp_suspend(struct analogix_dp_device * dp)1595 int analogix_dp_suspend(struct analogix_dp_device *dp)
1596 {
1597 phy_power_off(dp->phy);
1598
1599 if (dp->plat_data->power_off)
1600 dp->plat_data->power_off(dp->plat_data);
1601
1602 clk_disable_unprepare(dp->clock);
1603
1604 return 0;
1605 }
1606 EXPORT_SYMBOL_GPL(analogix_dp_suspend);
1607
analogix_dp_resume(struct analogix_dp_device * dp)1608 int analogix_dp_resume(struct analogix_dp_device *dp)
1609 {
1610 int ret;
1611
1612 ret = clk_prepare_enable(dp->clock);
1613 if (ret < 0) {
1614 DRM_ERROR("Failed to prepare_enable the clock clk [%d]\n", ret);
1615 return ret;
1616 }
1617
1618 if (dp->plat_data->power_on)
1619 dp->plat_data->power_on(dp->plat_data);
1620
1621 phy_set_mode(dp->phy, PHY_MODE_DP);
1622 phy_power_on(dp->phy);
1623
1624 analogix_dp_init_dp(dp);
1625
1626 return 0;
1627 }
1628 EXPORT_SYMBOL_GPL(analogix_dp_resume);
1629
analogix_dp_bind(struct analogix_dp_device * dp,struct drm_device * drm_dev)1630 int analogix_dp_bind(struct analogix_dp_device *dp, struct drm_device *drm_dev)
1631 {
1632 int ret;
1633
1634 dp->drm_dev = drm_dev;
1635 dp->encoder = dp->plat_data->encoder;
1636
1637 dp->aux.drm_dev = drm_dev;
1638
1639 ret = drm_dp_aux_register(&dp->aux);
1640 if (ret) {
1641 DRM_ERROR("failed to register AUX (%d)\n", ret);
1642 return ret;
1643 }
1644
1645 ret = analogix_dp_create_bridge(drm_dev, dp);
1646 if (ret) {
1647 DRM_ERROR("failed to create bridge (%d)\n", ret);
1648 goto err_unregister_aux;
1649 }
1650
1651 return 0;
1652
1653 err_unregister_aux:
1654 drm_dp_aux_unregister(&dp->aux);
1655
1656 return ret;
1657 }
1658 EXPORT_SYMBOL_GPL(analogix_dp_bind);
1659
analogix_dp_unbind(struct analogix_dp_device * dp)1660 void analogix_dp_unbind(struct analogix_dp_device *dp)
1661 {
1662 analogix_dp_bridge_disable(dp->bridge);
1663 dp->connector.funcs->destroy(&dp->connector);
1664
1665 drm_panel_unprepare(dp->plat_data->panel);
1666
1667 drm_dp_aux_unregister(&dp->aux);
1668 }
1669 EXPORT_SYMBOL_GPL(analogix_dp_unbind);
1670
analogix_dp_start_crc(struct drm_connector * connector)1671 int analogix_dp_start_crc(struct drm_connector *connector)
1672 {
1673 struct analogix_dp_device *dp = to_dp(connector);
1674
1675 if (!connector->state->crtc) {
1676 DRM_ERROR("Connector %s doesn't currently have a CRTC.\n",
1677 connector->name);
1678 return -EINVAL;
1679 }
1680
1681 return drm_dp_start_crc(&dp->aux, connector->state->crtc);
1682 }
1683 EXPORT_SYMBOL_GPL(analogix_dp_start_crc);
1684
analogix_dp_stop_crc(struct drm_connector * connector)1685 int analogix_dp_stop_crc(struct drm_connector *connector)
1686 {
1687 struct analogix_dp_device *dp = to_dp(connector);
1688
1689 return drm_dp_stop_crc(&dp->aux);
1690 }
1691 EXPORT_SYMBOL_GPL(analogix_dp_stop_crc);
1692
analogix_dp_aux_to_plat_data(struct drm_dp_aux * aux)1693 struct analogix_dp_plat_data *analogix_dp_aux_to_plat_data(struct drm_dp_aux *aux)
1694 {
1695 struct analogix_dp_device *dp = to_dp(aux);
1696
1697 return dp->plat_data;
1698 }
1699 EXPORT_SYMBOL_GPL(analogix_dp_aux_to_plat_data);
1700
analogix_dp_get_aux(struct analogix_dp_device * dp)1701 struct drm_dp_aux *analogix_dp_get_aux(struct analogix_dp_device *dp)
1702 {
1703 return &dp->aux;
1704 }
1705 EXPORT_SYMBOL_GPL(analogix_dp_get_aux);
1706
1707 MODULE_AUTHOR("Jingoo Han <jg1.han@samsung.com>");
1708 MODULE_DESCRIPTION("Analogix DP Core Driver");
1709 MODULE_LICENSE("GPL v2");
1710