1 /*
2 * Copyright 2020 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23 #include <drm/drm_drv.h>
24 #include <linux/vmalloc.h>
25 #include "amdgpu.h"
26 #include "amdgpu_psp.h"
27 #include "amdgpu_ucode.h"
28 #include "soc15_common.h"
29 #include "psp_v13_0.h"
30 #include "amdgpu_ras.h"
31
32 #include "mp/mp_13_0_2_offset.h"
33 #include "mp/mp_13_0_2_sh_mask.h"
34
35 MODULE_FIRMWARE("amdgpu/aldebaran_sos.bin");
36 MODULE_FIRMWARE("amdgpu/aldebaran_ta.bin");
37 MODULE_FIRMWARE("amdgpu/aldebaran_cap.bin");
38 MODULE_FIRMWARE("amdgpu/yellow_carp_toc.bin");
39 MODULE_FIRMWARE("amdgpu/yellow_carp_ta.bin");
40 MODULE_FIRMWARE("amdgpu/psp_13_0_5_toc.bin");
41 MODULE_FIRMWARE("amdgpu/psp_13_0_5_ta.bin");
42 MODULE_FIRMWARE("amdgpu/psp_13_0_8_toc.bin");
43 MODULE_FIRMWARE("amdgpu/psp_13_0_8_ta.bin");
44 MODULE_FIRMWARE("amdgpu/psp_13_0_0_sos.bin");
45 MODULE_FIRMWARE("amdgpu/psp_13_0_0_sos_kicker.bin");
46 MODULE_FIRMWARE("amdgpu/psp_13_0_0_ta.bin");
47 MODULE_FIRMWARE("amdgpu/psp_13_0_0_ta_kicker.bin");
48 MODULE_FIRMWARE("amdgpu/psp_13_0_7_sos.bin");
49 MODULE_FIRMWARE("amdgpu/psp_13_0_7_ta.bin");
50 MODULE_FIRMWARE("amdgpu/psp_13_0_10_sos.bin");
51 MODULE_FIRMWARE("amdgpu/psp_13_0_10_ta.bin");
52 MODULE_FIRMWARE("amdgpu/psp_13_0_11_toc.bin");
53 MODULE_FIRMWARE("amdgpu/psp_13_0_11_ta.bin");
54 MODULE_FIRMWARE("amdgpu/psp_13_0_6_sos.bin");
55 MODULE_FIRMWARE("amdgpu/psp_13_0_6_ta.bin");
56 MODULE_FIRMWARE("amdgpu/psp_13_0_12_sos.bin");
57 MODULE_FIRMWARE("amdgpu/psp_13_0_12_ta.bin");
58 MODULE_FIRMWARE("amdgpu/psp_13_0_14_sos.bin");
59 MODULE_FIRMWARE("amdgpu/psp_13_0_14_ta.bin");
60 MODULE_FIRMWARE("amdgpu/psp_13_0_15_sos.bin");
61 MODULE_FIRMWARE("amdgpu/psp_13_0_15_ta.bin");
62 MODULE_FIRMWARE("amdgpu/psp_14_0_0_toc.bin");
63 MODULE_FIRMWARE("amdgpu/psp_14_0_0_ta.bin");
64 MODULE_FIRMWARE("amdgpu/psp_14_0_1_toc.bin");
65 MODULE_FIRMWARE("amdgpu/psp_14_0_1_ta.bin");
66 MODULE_FIRMWARE("amdgpu/psp_14_0_4_toc.bin");
67 MODULE_FIRMWARE("amdgpu/psp_14_0_4_ta.bin");
68
69 /* For large FW files the time to complete can be very long */
70 #define USBC_PD_POLLING_LIMIT_S 240
71
72 /* Read USB-PD from LFB */
73 #define GFX_CMD_USB_PD_USE_LFB 0x480
74
75 /* Retry times for vmbx ready wait */
76 #define PSP_VMBX_POLLING_LIMIT 3000
77
78 /* memory training timeout define */
79 #define MEM_TRAIN_SEND_MSG_TIMEOUT_US 3000000
80
81 #define regMP1_PUB_SCRATCH0 0x3b10090
82
83 #define PSP13_BL_STATUS_SIZE 100
84
psp_v13_0_init_microcode(struct psp_context * psp)85 static int psp_v13_0_init_microcode(struct psp_context *psp)
86 {
87 struct amdgpu_device *adev = psp->adev;
88 char ucode_prefix[30];
89 int err = 0;
90
91 amdgpu_ucode_ip_version_decode(adev, MP0_HWIP, ucode_prefix, sizeof(ucode_prefix));
92
93 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) {
94 case IP_VERSION(13, 0, 2):
95 err = psp_init_sos_microcode(psp, ucode_prefix);
96 if (err)
97 return err;
98 /* It's not necessary to load ras ta on Guest side */
99 if (!amdgpu_sriov_vf(adev)) {
100 err = psp_init_ta_microcode(psp, ucode_prefix);
101 if (err)
102 return err;
103 }
104 break;
105 case IP_VERSION(13, 0, 1):
106 case IP_VERSION(13, 0, 3):
107 case IP_VERSION(13, 0, 5):
108 case IP_VERSION(13, 0, 8):
109 case IP_VERSION(13, 0, 11):
110 case IP_VERSION(14, 0, 0):
111 case IP_VERSION(14, 0, 1):
112 case IP_VERSION(14, 0, 4):
113 err = psp_init_toc_microcode(psp, ucode_prefix);
114 if (err)
115 return err;
116 err = psp_init_ta_microcode(psp, ucode_prefix);
117 if (err)
118 return err;
119 break;
120 case IP_VERSION(13, 0, 0):
121 case IP_VERSION(13, 0, 6):
122 case IP_VERSION(13, 0, 7):
123 case IP_VERSION(13, 0, 10):
124 case IP_VERSION(13, 0, 12):
125 case IP_VERSION(13, 0, 14):
126 case IP_VERSION(13, 0, 15):
127 err = psp_init_sos_microcode(psp, ucode_prefix);
128 if (err)
129 return err;
130 /* It's not necessary to load ras ta on Guest side */
131 err = psp_init_ta_microcode(psp, ucode_prefix);
132 if (err)
133 return err;
134 break;
135 default:
136 BUG();
137 }
138
139 return 0;
140 }
141
psp_v13_0_is_sos_alive(struct psp_context * psp)142 static bool psp_v13_0_is_sos_alive(struct psp_context *psp)
143 {
144 struct amdgpu_device *adev = psp->adev;
145 uint32_t sol_reg;
146
147 sol_reg = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81);
148
149 return sol_reg != 0x0;
150 }
151
psp_v13_0_bootloader_print_status(struct psp_context * psp,const char * msg)152 static void psp_v13_0_bootloader_print_status(struct psp_context *psp,
153 const char *msg)
154 {
155 struct amdgpu_device *adev = psp->adev;
156 u32 bl_status_reg;
157 char bl_status_msg[PSP13_BL_STATUS_SIZE];
158 int i, at;
159
160 if (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 6) ||
161 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 12) ||
162 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 14) ||
163 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 15)) {
164 at = 0;
165 for_each_inst(i, adev->aid_mask) {
166 bl_status_reg =
167 (SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_92)
168 << 2) +
169 adev->asic_funcs->encode_ext_smn_addressing(i);
170 at += snprintf(bl_status_msg + at,
171 PSP13_BL_STATUS_SIZE - at,
172 " status(%02i): 0x%08x", i,
173 RREG32_PCIE_EXT(bl_status_reg));
174 }
175 dev_info(adev->dev, "%s - %s", msg, bl_status_msg);
176 }
177 }
178
psp_v13_0_wait_for_vmbx_ready(struct psp_context * psp)179 static int psp_v13_0_wait_for_vmbx_ready(struct psp_context *psp)
180 {
181 struct amdgpu_device *adev = psp->adev;
182 int retry_loop, ret;
183
184 for (retry_loop = 0; retry_loop < PSP_VMBX_POLLING_LIMIT; retry_loop++) {
185 /* Wait for bootloader to signify that is
186 ready having bit 31 of C2PMSG_33 set to 1 */
187 ret = psp_wait_for(
188 psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_33),
189 0x80000000, 0xffffffff, PSP_WAITREG_NOVERBOSE);
190
191 if (ret == 0)
192 break;
193 }
194
195 if (ret)
196 dev_warn(adev->dev, "Bootloader wait timed out");
197
198 return ret;
199 }
200
psp_v13_0_wait_for_bootloader(struct psp_context * psp)201 static int psp_v13_0_wait_for_bootloader(struct psp_context *psp)
202 {
203 struct amdgpu_device *adev = psp->adev;
204 int retry_loop, retry_cnt, ret;
205
206 retry_cnt =
207 ((amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 6) ||
208 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 12) ||
209 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 14) ||
210 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 15))) ?
211 PSP_VMBX_POLLING_LIMIT :
212 10;
213 /* Wait for bootloader to signify that it is ready having bit 31 of
214 * C2PMSG_35 set to 1. All other bits are expected to be cleared.
215 * If there is an error in processing command, bits[7:0] will be set.
216 * This is applicable for PSP v13.0.6 and newer.
217 */
218 for (retry_loop = 0; retry_loop < retry_cnt; retry_loop++) {
219 ret = psp_wait_for(
220 psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35),
221 0x80000000, 0xffffffff, PSP_WAITREG_NOVERBOSE);
222
223 if (ret == 0)
224 return 0;
225 if (retry_loop && !(retry_loop % 10))
226 psp_v13_0_bootloader_print_status(
227 psp, "Waiting for bootloader completion");
228 }
229
230 return ret;
231 }
232
psp_v13_0_wait_for_bootloader_steady_state(struct psp_context * psp)233 static int psp_v13_0_wait_for_bootloader_steady_state(struct psp_context *psp)
234 {
235 struct amdgpu_device *adev = psp->adev;
236 int ret;
237
238 if (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 6) ||
239 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 12) ||
240 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 14) ||
241 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 15)) {
242 ret = psp_v13_0_wait_for_vmbx_ready(psp);
243 if (ret)
244 amdgpu_ras_query_boot_status(adev, 4);
245
246 ret = psp_v13_0_wait_for_bootloader(psp);
247 if (ret)
248 amdgpu_ras_query_boot_status(adev, 4);
249
250 return ret;
251 }
252
253 return 0;
254 }
255
psp_v13_0_bootloader_load_component(struct psp_context * psp,struct psp_bin_desc * bin_desc,enum psp_bootloader_cmd bl_cmd)256 static int psp_v13_0_bootloader_load_component(struct psp_context *psp,
257 struct psp_bin_desc *bin_desc,
258 enum psp_bootloader_cmd bl_cmd)
259 {
260 int ret;
261 uint32_t psp_gfxdrv_command_reg = 0;
262 struct amdgpu_device *adev = psp->adev;
263
264 /* Check tOS sign of life register to confirm sys driver and sOS
265 * are already been loaded.
266 */
267 if (psp_v13_0_is_sos_alive(psp))
268 return 0;
269
270 ret = psp_v13_0_wait_for_bootloader(psp);
271 if (ret)
272 return ret;
273
274 memset(psp->fw_pri_buf, 0, PSP_1_MEG);
275
276 /* Copy PSP KDB binary to memory */
277 memcpy(psp->fw_pri_buf, bin_desc->start_addr, bin_desc->size_bytes);
278
279 /* Provide the PSP KDB to bootloader */
280 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36,
281 (uint32_t)(psp->fw_pri_mc_addr >> 20));
282 psp_gfxdrv_command_reg = bl_cmd;
283 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35,
284 psp_gfxdrv_command_reg);
285
286 ret = psp_v13_0_wait_for_bootloader(psp);
287
288 return ret;
289 }
290
psp_v13_0_bootloader_load_kdb(struct psp_context * psp)291 static int psp_v13_0_bootloader_load_kdb(struct psp_context *psp)
292 {
293 return psp_v13_0_bootloader_load_component(psp, &psp->kdb, PSP_BL__LOAD_KEY_DATABASE);
294 }
295
psp_v13_0_bootloader_load_spl(struct psp_context * psp)296 static int psp_v13_0_bootloader_load_spl(struct psp_context *psp)
297 {
298 return psp_v13_0_bootloader_load_component(psp, &psp->kdb, PSP_BL__LOAD_TOS_SPL_TABLE);
299 }
300
psp_v13_0_bootloader_load_sysdrv(struct psp_context * psp)301 static int psp_v13_0_bootloader_load_sysdrv(struct psp_context *psp)
302 {
303 return psp_v13_0_bootloader_load_component(psp, &psp->sys, PSP_BL__LOAD_SYSDRV);
304 }
305
psp_v13_0_bootloader_load_soc_drv(struct psp_context * psp)306 static int psp_v13_0_bootloader_load_soc_drv(struct psp_context *psp)
307 {
308 return psp_v13_0_bootloader_load_component(psp, &psp->soc_drv, PSP_BL__LOAD_SOCDRV);
309 }
310
psp_v13_0_bootloader_load_intf_drv(struct psp_context * psp)311 static int psp_v13_0_bootloader_load_intf_drv(struct psp_context *psp)
312 {
313 return psp_v13_0_bootloader_load_component(psp, &psp->intf_drv, PSP_BL__LOAD_INTFDRV);
314 }
315
psp_v13_0_bootloader_load_dbg_drv(struct psp_context * psp)316 static int psp_v13_0_bootloader_load_dbg_drv(struct psp_context *psp)
317 {
318 return psp_v13_0_bootloader_load_component(psp, &psp->dbg_drv, PSP_BL__LOAD_DBGDRV);
319 }
320
psp_v13_0_bootloader_load_ras_drv(struct psp_context * psp)321 static int psp_v13_0_bootloader_load_ras_drv(struct psp_context *psp)
322 {
323 return psp_v13_0_bootloader_load_component(psp, &psp->ras_drv, PSP_BL__LOAD_RASDRV);
324 }
325
psp_v13_0_bootloader_load_spdm_drv(struct psp_context * psp)326 static int psp_v13_0_bootloader_load_spdm_drv(struct psp_context *psp)
327 {
328 return psp_v13_0_bootloader_load_component(psp, &psp->spdm_drv, PSP_BL__LOAD_SPDMDRV);
329 }
330
psp_v13_0_init_sos_version(struct psp_context * psp)331 static inline void psp_v13_0_init_sos_version(struct psp_context *psp)
332 {
333 struct amdgpu_device *adev = psp->adev;
334
335 psp->sos.fw_version = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_58);
336 }
337
psp_v13_0_bootloader_load_sos(struct psp_context * psp)338 static int psp_v13_0_bootloader_load_sos(struct psp_context *psp)
339 {
340 int ret;
341 unsigned int psp_gfxdrv_command_reg = 0;
342 struct amdgpu_device *adev = psp->adev;
343
344 /* Check sOS sign of life register to confirm sys driver and sOS
345 * are already been loaded.
346 */
347 if (psp_v13_0_is_sos_alive(psp)) {
348 psp_v13_0_init_sos_version(psp);
349 return 0;
350 }
351
352 ret = psp_v13_0_wait_for_bootloader(psp);
353 if (ret)
354 return ret;
355
356 memset(psp->fw_pri_buf, 0, PSP_1_MEG);
357
358 /* Copy Secure OS binary to PSP memory */
359 memcpy(psp->fw_pri_buf, psp->sos.start_addr, psp->sos.size_bytes);
360
361 /* Provide the PSP secure OS to bootloader */
362 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36,
363 (uint32_t)(psp->fw_pri_mc_addr >> 20));
364 psp_gfxdrv_command_reg = PSP_BL__LOAD_SOSDRV;
365 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35,
366 psp_gfxdrv_command_reg);
367
368 /* there might be handshake issue with hardware which needs delay */
369 mdelay(20);
370 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_81),
371 RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81), 0,
372 PSP_WAITREG_CHANGED);
373
374 if (!ret)
375 psp_v13_0_init_sos_version(psp);
376
377 return ret;
378 }
379
psp_v13_0_ring_stop(struct psp_context * psp,enum psp_ring_type ring_type)380 static int psp_v13_0_ring_stop(struct psp_context *psp,
381 enum psp_ring_type ring_type)
382 {
383 int ret = 0;
384 struct amdgpu_device *adev = psp->adev;
385
386 if (amdgpu_sriov_vf(adev)) {
387 /* Write the ring destroy command*/
388 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_101,
389 GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING);
390 /* there might be handshake issue with hardware which needs delay */
391 mdelay(20);
392 /* Wait for response flag (bit 31) */
393 ret = psp_wait_for(
394 psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_101),
395 MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, 0);
396 } else {
397 /* Write the ring destroy command*/
398 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_64,
399 GFX_CTRL_CMD_ID_DESTROY_RINGS);
400 /* there might be handshake issue with hardware which needs delay */
401 mdelay(20);
402 /* Wait for response flag (bit 31) */
403 ret = psp_wait_for(
404 psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64),
405 MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, 0);
406 }
407
408 return ret;
409 }
410
psp_v13_0_ring_create(struct psp_context * psp,enum psp_ring_type ring_type)411 static int psp_v13_0_ring_create(struct psp_context *psp,
412 enum psp_ring_type ring_type)
413 {
414 int ret = 0;
415 unsigned int psp_ring_reg = 0;
416 struct psp_ring *ring = &psp->km_ring;
417 struct amdgpu_device *adev = psp->adev;
418
419 if (amdgpu_sriov_vf(adev)) {
420 ret = psp_v13_0_ring_stop(psp, ring_type);
421 if (ret) {
422 DRM_ERROR("psp_v13_0_ring_stop_sriov failed!\n");
423 return ret;
424 }
425
426 /* Write low address of the ring to C2PMSG_102 */
427 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
428 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102, psp_ring_reg);
429 /* Write high address of the ring to C2PMSG_103 */
430 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
431 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_103, psp_ring_reg);
432
433 /* Write the ring initialization command to C2PMSG_101 */
434 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_101,
435 GFX_CTRL_CMD_ID_INIT_GPCOM_RING);
436
437 /* there might be handshake issue with hardware which needs delay */
438 mdelay(20);
439
440 /* Wait for response flag (bit 31) in C2PMSG_101 */
441 ret = psp_wait_for(
442 psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_101),
443 MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, 0);
444
445 } else {
446 /* Wait for sOS ready for ring creation */
447 ret = psp_wait_for(
448 psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64),
449 MBOX_TOS_READY_FLAG, MBOX_TOS_READY_MASK, 0);
450 if (ret) {
451 DRM_ERROR("Failed to wait for trust OS ready for ring creation\n");
452 return ret;
453 }
454
455 /* Write low address of the ring to C2PMSG_69 */
456 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
457 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_69, psp_ring_reg);
458 /* Write high address of the ring to C2PMSG_70 */
459 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
460 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_70, psp_ring_reg);
461 /* Write size of ring to C2PMSG_71 */
462 psp_ring_reg = ring->ring_size;
463 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_71, psp_ring_reg);
464 /* Write the ring initialization command to C2PMSG_64 */
465 psp_ring_reg = ring_type;
466 psp_ring_reg = psp_ring_reg << 16;
467 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_64, psp_ring_reg);
468
469 /* there might be handshake issue with hardware which needs delay */
470 mdelay(20);
471
472 /* Wait for response flag (bit 31) in C2PMSG_64 */
473 ret = psp_wait_for(
474 psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64),
475 MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, 0);
476 }
477
478 return ret;
479 }
480
psp_v13_0_ring_destroy(struct psp_context * psp,enum psp_ring_type ring_type)481 static int psp_v13_0_ring_destroy(struct psp_context *psp,
482 enum psp_ring_type ring_type)
483 {
484 int ret = 0;
485 struct psp_ring *ring = &psp->km_ring;
486 struct amdgpu_device *adev = psp->adev;
487
488 ret = psp_v13_0_ring_stop(psp, ring_type);
489 if (ret)
490 DRM_ERROR("Fail to stop psp ring\n");
491
492 amdgpu_bo_free_kernel(&adev->firmware.rbuf,
493 &ring->ring_mem_mc_addr,
494 (void **)&ring->ring_mem);
495
496 return ret;
497 }
498
psp_v13_0_ring_get_wptr(struct psp_context * psp)499 static uint32_t psp_v13_0_ring_get_wptr(struct psp_context *psp)
500 {
501 uint32_t data;
502 struct amdgpu_device *adev = psp->adev;
503
504 if (amdgpu_sriov_vf(adev))
505 data = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102);
506 else
507 data = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_67);
508
509 return data;
510 }
511
psp_v13_0_ring_set_wptr(struct psp_context * psp,uint32_t value)512 static void psp_v13_0_ring_set_wptr(struct psp_context *psp, uint32_t value)
513 {
514 struct amdgpu_device *adev = psp->adev;
515
516 if (amdgpu_sriov_vf(adev)) {
517 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102, value);
518 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_101,
519 GFX_CTRL_CMD_ID_CONSUME_CMD);
520 } else
521 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_67, value);
522 }
523
psp_v13_0_memory_training_send_msg(struct psp_context * psp,int msg)524 static int psp_v13_0_memory_training_send_msg(struct psp_context *psp, int msg)
525 {
526 int ret;
527 int i;
528 uint32_t data_32;
529 int max_wait;
530 struct amdgpu_device *adev = psp->adev;
531
532 data_32 = (psp->mem_train_ctx.c2p_train_data_offset >> 20);
533 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36, data_32);
534 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35, msg);
535
536 max_wait = MEM_TRAIN_SEND_MSG_TIMEOUT_US / adev->usec_timeout;
537 for (i = 0; i < max_wait; i++) {
538 ret = psp_wait_for(
539 psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35),
540 0x80000000, 0x80000000, PSP_WAITREG_NOVERBOSE);
541 if (ret == 0)
542 break;
543 }
544 if (i < max_wait)
545 ret = 0;
546 else
547 ret = -ETIME;
548
549 dev_dbg(adev->dev, "training %s %s, cost %d @ %d ms\n",
550 (msg == PSP_BL__DRAM_SHORT_TRAIN) ? "short" : "long",
551 (ret == 0) ? "succeed" : "failed",
552 i, adev->usec_timeout/1000);
553 return ret;
554 }
555
556
psp_v13_0_memory_training(struct psp_context * psp,uint32_t ops)557 static int psp_v13_0_memory_training(struct psp_context *psp, uint32_t ops)
558 {
559 struct psp_memory_training_context *ctx = &psp->mem_train_ctx;
560 uint32_t *pcache = (uint32_t *)ctx->sys_cache;
561 struct amdgpu_device *adev = psp->adev;
562 uint32_t p2c_header[4];
563 uint32_t sz;
564 void *buf;
565 int ret, idx;
566
567 if (ctx->init == PSP_MEM_TRAIN_NOT_SUPPORT) {
568 dev_dbg(adev->dev, "Memory training is not supported.\n");
569 return 0;
570 } else if (ctx->init != PSP_MEM_TRAIN_INIT_SUCCESS) {
571 dev_err(adev->dev, "Memory training initialization failure.\n");
572 return -EINVAL;
573 }
574
575 if (psp_v13_0_is_sos_alive(psp)) {
576 dev_dbg(adev->dev, "SOS is alive, skip memory training.\n");
577 return 0;
578 }
579
580 amdgpu_device_vram_access(adev, ctx->p2c_train_data_offset, p2c_header, sizeof(p2c_header), false);
581 dev_dbg(adev->dev, "sys_cache[%08x,%08x,%08x,%08x] p2c_header[%08x,%08x,%08x,%08x]\n",
582 pcache[0], pcache[1], pcache[2], pcache[3],
583 p2c_header[0], p2c_header[1], p2c_header[2], p2c_header[3]);
584
585 if (ops & PSP_MEM_TRAIN_SEND_SHORT_MSG) {
586 dev_dbg(adev->dev, "Short training depends on restore.\n");
587 ops |= PSP_MEM_TRAIN_RESTORE;
588 }
589
590 if ((ops & PSP_MEM_TRAIN_RESTORE) &&
591 pcache[0] != MEM_TRAIN_SYSTEM_SIGNATURE) {
592 dev_dbg(adev->dev, "sys_cache[0] is invalid, restore depends on save.\n");
593 ops |= PSP_MEM_TRAIN_SAVE;
594 }
595
596 if (p2c_header[0] == MEM_TRAIN_SYSTEM_SIGNATURE &&
597 !(pcache[0] == MEM_TRAIN_SYSTEM_SIGNATURE &&
598 pcache[3] == p2c_header[3])) {
599 dev_dbg(adev->dev, "sys_cache is invalid or out-of-date, need save training data to sys_cache.\n");
600 ops |= PSP_MEM_TRAIN_SAVE;
601 }
602
603 if ((ops & PSP_MEM_TRAIN_SAVE) &&
604 p2c_header[0] != MEM_TRAIN_SYSTEM_SIGNATURE) {
605 dev_dbg(adev->dev, "p2c_header[0] is invalid, save depends on long training.\n");
606 ops |= PSP_MEM_TRAIN_SEND_LONG_MSG;
607 }
608
609 if (ops & PSP_MEM_TRAIN_SEND_LONG_MSG) {
610 ops &= ~PSP_MEM_TRAIN_SEND_SHORT_MSG;
611 ops |= PSP_MEM_TRAIN_SAVE;
612 }
613
614 dev_dbg(adev->dev, "Memory training ops:%x.\n", ops);
615
616 if (ops & PSP_MEM_TRAIN_SEND_LONG_MSG) {
617 /*
618 * Long training will encroach a certain amount on the bottom of VRAM;
619 * save the content from the bottom of VRAM to system memory
620 * before training, and restore it after training to avoid
621 * VRAM corruption.
622 */
623 sz = BIST_MEM_TRAINING_ENCROACHED_SIZE;
624
625 if (adev->gmc.visible_vram_size < sz || !adev->mman.aper_base_kaddr) {
626 dev_err(adev->dev, "visible_vram_size %llx or aper_base_kaddr %p is not initialized.\n",
627 adev->gmc.visible_vram_size,
628 adev->mman.aper_base_kaddr);
629 return -EINVAL;
630 }
631
632 buf = vmalloc(sz);
633 if (!buf) {
634 dev_err(adev->dev, "failed to allocate system memory.\n");
635 return -ENOMEM;
636 }
637
638 if (drm_dev_enter(adev_to_drm(adev), &idx)) {
639 memcpy_fromio(buf, adev->mman.aper_base_kaddr, sz);
640 ret = psp_v13_0_memory_training_send_msg(psp, PSP_BL__DRAM_LONG_TRAIN);
641 if (ret) {
642 DRM_ERROR("Send long training msg failed.\n");
643 vfree(buf);
644 drm_dev_exit(idx);
645 return ret;
646 }
647
648 memcpy_toio(adev->mman.aper_base_kaddr, buf, sz);
649 amdgpu_device_flush_hdp(adev, NULL);
650 vfree(buf);
651 drm_dev_exit(idx);
652 } else {
653 vfree(buf);
654 return -ENODEV;
655 }
656 }
657
658 if (ops & PSP_MEM_TRAIN_SAVE) {
659 amdgpu_device_vram_access(psp->adev, ctx->p2c_train_data_offset, ctx->sys_cache, ctx->train_data_size, false);
660 }
661
662 if (ops & PSP_MEM_TRAIN_RESTORE) {
663 amdgpu_device_vram_access(psp->adev, ctx->c2p_train_data_offset, ctx->sys_cache, ctx->train_data_size, true);
664 }
665
666 if (ops & PSP_MEM_TRAIN_SEND_SHORT_MSG) {
667 ret = psp_v13_0_memory_training_send_msg(psp, (amdgpu_force_long_training > 0) ?
668 PSP_BL__DRAM_LONG_TRAIN : PSP_BL__DRAM_SHORT_TRAIN);
669 if (ret) {
670 dev_err(adev->dev, "send training msg failed.\n");
671 return ret;
672 }
673 }
674 ctx->training_cnt++;
675 return 0;
676 }
677
psp_v13_0_load_usbc_pd_fw(struct psp_context * psp,uint64_t fw_pri_mc_addr)678 static int psp_v13_0_load_usbc_pd_fw(struct psp_context *psp, uint64_t fw_pri_mc_addr)
679 {
680 struct amdgpu_device *adev = psp->adev;
681 uint32_t reg_status;
682 int ret, i = 0;
683
684 /*
685 * LFB address which is aligned to 1MB address and has to be
686 * right-shifted by 20 so that LFB address can be passed on a 32-bit C2P
687 * register
688 */
689 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36, (fw_pri_mc_addr >> 20));
690
691 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35),
692 0x80000000, 0x80000000, 0);
693 if (ret)
694 return ret;
695
696 /* Fireup interrupt so PSP can pick up the address */
697 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35, (GFX_CMD_USB_PD_USE_LFB << 16));
698
699 /* FW load takes very long time */
700 do {
701 msleep(1000);
702 reg_status = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35);
703
704 if (reg_status & 0x80000000)
705 goto done;
706
707 } while (++i < USBC_PD_POLLING_LIMIT_S);
708
709 return -ETIME;
710 done:
711
712 if ((reg_status & 0xFFFF) != 0) {
713 DRM_ERROR("Address load failed - MP0_SMN_C2PMSG_35.Bits [15:0] = %04x\n",
714 reg_status & 0xFFFF);
715 return -EIO;
716 }
717
718 return 0;
719 }
720
psp_v13_0_read_usbc_pd_fw(struct psp_context * psp,uint32_t * fw_ver)721 static int psp_v13_0_read_usbc_pd_fw(struct psp_context *psp, uint32_t *fw_ver)
722 {
723 struct amdgpu_device *adev = psp->adev;
724 int ret;
725
726 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35, C2PMSG_CMD_GFX_USB_PD_FW_VER);
727
728 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35),
729 0x80000000, 0x80000000, 0);
730 if (!ret)
731 *fw_ver = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36);
732
733 return ret;
734 }
735
psp_v13_0_exec_spi_cmd(struct psp_context * psp,int cmd)736 static int psp_v13_0_exec_spi_cmd(struct psp_context *psp, int cmd)
737 {
738 uint32_t reg_status = 0, reg_val = 0;
739 struct amdgpu_device *adev = psp->adev;
740 int ret;
741
742 /* clear MBX ready (MBOX_READY_MASK bit is 0) and set update command */
743 reg_val |= (cmd << 16);
744 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_115, reg_val);
745
746 /* Ring the doorbell */
747 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_73, 1);
748
749 if (cmd == C2PMSG_CMD_SPI_UPDATE_FLASH_IMAGE ||
750 cmd == C2PMSG_CMD_SPI_GET_FLASH_IMAGE)
751 ret = psp_wait_for_spirom_update(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_115),
752 MBOX_READY_FLAG, MBOX_READY_MASK, PSP_SPIROM_UPDATE_TIMEOUT);
753 else
754 ret = psp_wait_for(
755 psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_115),
756 MBOX_READY_FLAG, MBOX_READY_MASK, 0);
757 if (ret) {
758 dev_err(adev->dev, "SPI cmd %x timed out, ret = %d", cmd, ret);
759 return ret;
760 }
761
762 reg_status = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_115);
763 if ((reg_status & 0xFFFF) != 0) {
764 dev_err(adev->dev, "SPI cmd %x failed, fail status = %04x\n",
765 cmd, reg_status & 0xFFFF);
766 return -EIO;
767 }
768
769 return 0;
770 }
771
psp_v13_0_update_spirom(struct psp_context * psp,uint64_t fw_pri_mc_addr)772 static int psp_v13_0_update_spirom(struct psp_context *psp,
773 uint64_t fw_pri_mc_addr)
774 {
775 struct amdgpu_device *adev = psp->adev;
776 int ret;
777
778 /* Confirm PSP is ready to start */
779 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_115),
780 MBOX_READY_FLAG, MBOX_READY_MASK, 0);
781 if (ret) {
782 dev_err(adev->dev, "PSP Not ready to start processing, ret = %d", ret);
783 return ret;
784 }
785
786 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_116, lower_32_bits(fw_pri_mc_addr));
787
788 ret = psp_v13_0_exec_spi_cmd(psp, C2PMSG_CMD_SPI_UPDATE_ROM_IMAGE_ADDR_LO);
789 if (ret)
790 return ret;
791
792 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_116, upper_32_bits(fw_pri_mc_addr));
793
794 ret = psp_v13_0_exec_spi_cmd(psp, C2PMSG_CMD_SPI_UPDATE_ROM_IMAGE_ADDR_HI);
795 if (ret)
796 return ret;
797
798 psp->vbflash_done = true;
799
800 ret = psp_v13_0_exec_spi_cmd(psp, C2PMSG_CMD_SPI_UPDATE_FLASH_IMAGE);
801 if (ret)
802 return ret;
803
804 return 0;
805 }
806
psp_v13_0_dump_spirom(struct psp_context * psp,uint64_t fw_pri_mc_addr)807 static int psp_v13_0_dump_spirom(struct psp_context *psp,
808 uint64_t fw_pri_mc_addr)
809 {
810 struct amdgpu_device *adev = psp->adev;
811 int ret;
812
813 /* Confirm PSP is ready to start */
814 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_115),
815 MBOX_READY_FLAG, MBOX_READY_MASK, 0);
816 if (ret) {
817 dev_err(adev->dev, "PSP Not ready to start processing, ret = %d", ret);
818 return ret;
819 }
820
821 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_116, lower_32_bits(fw_pri_mc_addr));
822
823 ret = psp_v13_0_exec_spi_cmd(psp, C2PMSG_CMD_SPI_GET_ROM_IMAGE_ADDR_LO);
824 if (ret)
825 return ret;
826
827 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_116, upper_32_bits(fw_pri_mc_addr));
828
829 ret = psp_v13_0_exec_spi_cmd(psp, C2PMSG_CMD_SPI_GET_ROM_IMAGE_ADDR_HI);
830 if (ret)
831 return ret;
832
833 ret = psp_v13_0_exec_spi_cmd(psp, C2PMSG_CMD_SPI_GET_FLASH_IMAGE);
834
835 return ret;
836 }
837
psp_v13_0_vbflash_status(struct psp_context * psp)838 static int psp_v13_0_vbflash_status(struct psp_context *psp)
839 {
840 struct amdgpu_device *adev = psp->adev;
841
842 return RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_115);
843 }
844
psp_v13_0_fatal_error_recovery_quirk(struct psp_context * psp)845 static int psp_v13_0_fatal_error_recovery_quirk(struct psp_context *psp)
846 {
847 struct amdgpu_device *adev = psp->adev;
848
849 if (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 10)) {
850 uint32_t reg_data;
851 /* MP1 fatal error: trigger PSP dram read to unhalt PSP
852 * during MP1 triggered sync flood.
853 */
854 reg_data = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_67);
855 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_67, reg_data + 0x10);
856
857 /* delay 1000ms for the mode1 reset for fatal error
858 * to be recovered back.
859 */
860 msleep(1000);
861 }
862
863 return 0;
864 }
865
psp_v13_0_get_ras_capability(struct psp_context * psp)866 static bool psp_v13_0_get_ras_capability(struct psp_context *psp)
867 {
868 struct amdgpu_device *adev = psp->adev;
869 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
870 u32 reg_data;
871
872 /* query ras cap should be done from host side */
873 if (amdgpu_sriov_vf(adev))
874 return false;
875
876 if (!con)
877 return false;
878
879 if ((amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 6) ||
880 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 12) ||
881 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 14) ||
882 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 15)) &&
883 (!(adev->flags & AMD_IS_APU))) {
884 reg_data = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_127);
885 adev->ras_hw_enabled = (reg_data & GENMASK_ULL(23, 0));
886 con->poison_supported = ((reg_data & GENMASK_ULL(24, 24)) >> 24) ? true : false;
887 return true;
888 } else {
889 return false;
890 }
891 }
892
psp_v13_0_is_aux_sos_load_required(struct psp_context * psp)893 static bool psp_v13_0_is_aux_sos_load_required(struct psp_context *psp)
894 {
895 struct amdgpu_device *adev = psp->adev;
896 u32 pmfw_ver;
897
898 if (amdgpu_ip_version(adev, MP0_HWIP, 0) != IP_VERSION(13, 0, 6))
899 return false;
900
901 /* load 4e version of sos if pmfw version less than 85.115.0 */
902 pmfw_ver = RREG32(regMP1_PUB_SCRATCH0 / 4);
903
904 return (pmfw_ver < 0x557300);
905 }
906
psp_v13_0_is_reload_needed(struct psp_context * psp)907 static bool psp_v13_0_is_reload_needed(struct psp_context *psp)
908 {
909 uint32_t ucode_ver;
910
911 if (!psp_v13_0_is_sos_alive(psp))
912 return false;
913
914 /* Restrict reload support only to specific IP versions */
915 switch (amdgpu_ip_version(psp->adev, MP0_HWIP, 0)) {
916 case IP_VERSION(13, 0, 2):
917 case IP_VERSION(13, 0, 6):
918 case IP_VERSION(13, 0, 14):
919 /* TOS version read from microcode header */
920 ucode_ver = psp->sos.fw_version;
921 /* Read TOS version from hardware */
922 psp_v13_0_init_sos_version(psp);
923 return (ucode_ver != psp->sos.fw_version);
924 default:
925 return false;
926 }
927
928 return false;
929 }
930
psp_v13_0_reg_program_no_ring(struct psp_context * psp,uint32_t val,enum psp_reg_prog_id id)931 static int psp_v13_0_reg_program_no_ring(struct psp_context *psp, uint32_t val,
932 enum psp_reg_prog_id id)
933 {
934 struct amdgpu_device *adev = psp->adev;
935 int ret = -EOPNOTSUPP;
936
937 /* PSP will broadcast the value to all instances */
938 if (amdgpu_sriov_vf(adev)) {
939 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_101, GFX_CTRL_CMD_ID_GBR_IH_SET);
940 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102, id);
941 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_103, val);
942
943 ret = psp_wait_for(
944 psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_101),
945 0x80000000, 0x80000000, 0);
946 }
947
948 return ret;
949 }
950
951 static const struct psp_funcs psp_v13_0_funcs = {
952 .init_microcode = psp_v13_0_init_microcode,
953 .wait_for_bootloader = psp_v13_0_wait_for_bootloader_steady_state,
954 .bootloader_load_kdb = psp_v13_0_bootloader_load_kdb,
955 .bootloader_load_spl = psp_v13_0_bootloader_load_spl,
956 .bootloader_load_sysdrv = psp_v13_0_bootloader_load_sysdrv,
957 .bootloader_load_soc_drv = psp_v13_0_bootloader_load_soc_drv,
958 .bootloader_load_intf_drv = psp_v13_0_bootloader_load_intf_drv,
959 .bootloader_load_dbg_drv = psp_v13_0_bootloader_load_dbg_drv,
960 .bootloader_load_ras_drv = psp_v13_0_bootloader_load_ras_drv,
961 .bootloader_load_spdm_drv = psp_v13_0_bootloader_load_spdm_drv,
962 .bootloader_load_sos = psp_v13_0_bootloader_load_sos,
963 .ring_create = psp_v13_0_ring_create,
964 .ring_stop = psp_v13_0_ring_stop,
965 .ring_destroy = psp_v13_0_ring_destroy,
966 .ring_get_wptr = psp_v13_0_ring_get_wptr,
967 .ring_set_wptr = psp_v13_0_ring_set_wptr,
968 .mem_training = psp_v13_0_memory_training,
969 .load_usbc_pd_fw = psp_v13_0_load_usbc_pd_fw,
970 .read_usbc_pd_fw = psp_v13_0_read_usbc_pd_fw,
971 .update_spirom = psp_v13_0_update_spirom,
972 .dump_spirom = psp_v13_0_dump_spirom,
973 .vbflash_stat = psp_v13_0_vbflash_status,
974 .fatal_error_recovery_quirk = psp_v13_0_fatal_error_recovery_quirk,
975 .get_ras_capability = psp_v13_0_get_ras_capability,
976 .is_aux_sos_load_required = psp_v13_0_is_aux_sos_load_required,
977 .is_reload_needed = psp_v13_0_is_reload_needed,
978 .reg_program_no_ring = psp_v13_0_reg_program_no_ring,
979 };
980
psp_v13_0_set_psp_funcs(struct psp_context * psp)981 void psp_v13_0_set_psp_funcs(struct psp_context *psp)
982 {
983 psp->funcs = &psp_v13_0_funcs;
984 }
985