1 /*-
2 * Copyright (c) 2013-2021, Mellanox Technologies. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
6 * are met:
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 *
13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
23 * SUCH DAMAGE.
24 */
25
26 #include "opt_rss.h"
27 #include "opt_ratelimit.h"
28
29 #include <linux/module.h>
30 #include <rdma/ib_umem.h>
31 #include <rdma/ib_cache.h>
32 #include <rdma/ib_user_verbs.h>
33 #include <rdma/uverbs_ioctl.h>
34 #include <dev/mlx5/mlx5_ib/mlx5_ib.h>
35
36 /* not supported currently */
37 static int wq_signature;
38
39 enum {
40 MLX5_IB_ACK_REQ_FREQ = 8,
41 };
42
43 enum {
44 MLX5_IB_DEFAULT_SCHED_QUEUE = 0x83,
45 MLX5_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f,
46 MLX5_IB_LINK_TYPE_IB = 0,
47 MLX5_IB_LINK_TYPE_ETH = 1
48 };
49
50 enum {
51 MLX5_IB_SQ_STRIDE = 6,
52 };
53
54 static const u32 mlx5_ib_opcode[] = {
55 [IB_WR_SEND] = MLX5_OPCODE_SEND,
56 [IB_WR_LSO] = MLX5_OPCODE_LSO,
57 [IB_WR_SEND_WITH_IMM] = MLX5_OPCODE_SEND_IMM,
58 [IB_WR_RDMA_WRITE] = MLX5_OPCODE_RDMA_WRITE,
59 [IB_WR_RDMA_WRITE_WITH_IMM] = MLX5_OPCODE_RDMA_WRITE_IMM,
60 [IB_WR_RDMA_READ] = MLX5_OPCODE_RDMA_READ,
61 [IB_WR_ATOMIC_CMP_AND_SWP] = MLX5_OPCODE_ATOMIC_CS,
62 [IB_WR_ATOMIC_FETCH_AND_ADD] = MLX5_OPCODE_ATOMIC_FA,
63 [IB_WR_SEND_WITH_INV] = MLX5_OPCODE_SEND_INVAL,
64 [IB_WR_LOCAL_INV] = MLX5_OPCODE_UMR,
65 [IB_WR_REG_MR] = MLX5_OPCODE_UMR,
66 [IB_WR_MASKED_ATOMIC_CMP_AND_SWP] = MLX5_OPCODE_ATOMIC_MASKED_CS,
67 [IB_WR_MASKED_ATOMIC_FETCH_AND_ADD] = MLX5_OPCODE_ATOMIC_MASKED_FA,
68 [MLX5_IB_WR_UMR] = MLX5_OPCODE_UMR,
69 };
70
71 struct mlx5_wqe_eth_pad {
72 u8 rsvd0[16];
73 };
74
75 enum raw_qp_set_mask_map {
76 MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID = 1UL << 0,
77 };
78
79 struct mlx5_modify_raw_qp_param {
80 u16 operation;
81
82 u32 set_mask; /* raw_qp_set_mask_map */
83 u8 rq_q_ctr_id;
84 };
85
86 static void get_cqs(enum ib_qp_type qp_type,
87 struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq,
88 struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq);
89
is_qp0(enum ib_qp_type qp_type)90 static int is_qp0(enum ib_qp_type qp_type)
91 {
92 return qp_type == IB_QPT_SMI;
93 }
94
is_sqp(enum ib_qp_type qp_type)95 static int is_sqp(enum ib_qp_type qp_type)
96 {
97 return is_qp0(qp_type) || is_qp1(qp_type);
98 }
99
get_wqe(struct mlx5_ib_qp * qp,int offset)100 static void *get_wqe(struct mlx5_ib_qp *qp, int offset)
101 {
102 return mlx5_buf_offset(&qp->buf, offset);
103 }
104
get_recv_wqe(struct mlx5_ib_qp * qp,int n)105 static void *get_recv_wqe(struct mlx5_ib_qp *qp, int n)
106 {
107 return get_wqe(qp, qp->rq.offset + (n << qp->rq.wqe_shift));
108 }
109
mlx5_get_send_wqe(struct mlx5_ib_qp * qp,int n)110 void *mlx5_get_send_wqe(struct mlx5_ib_qp *qp, int n)
111 {
112 return get_wqe(qp, qp->sq.offset + (n << MLX5_IB_SQ_STRIDE));
113 }
114
115 /**
116 * mlx5_ib_read_user_wqe() - Copy a user-space WQE to kernel space.
117 *
118 * @qp: QP to copy from.
119 * @send: copy from the send queue when non-zero, use the receive queue
120 * otherwise.
121 * @wqe_index: index to start copying from. For send work queues, the
122 * wqe_index is in units of MLX5_SEND_WQE_BB.
123 * For receive work queue, it is the number of work queue
124 * element in the queue.
125 * @buffer: destination buffer.
126 * @length: maximum number of bytes to copy.
127 *
128 * Copies at least a single WQE, but may copy more data.
129 *
130 * Return: the number of bytes copied, or an error code.
131 */
mlx5_ib_read_user_wqe(struct mlx5_ib_qp * qp,int send,int wqe_index,void * buffer,u32 length,struct mlx5_ib_qp_base * base)132 int mlx5_ib_read_user_wqe(struct mlx5_ib_qp *qp, int send, int wqe_index,
133 void *buffer, u32 length,
134 struct mlx5_ib_qp_base *base)
135 {
136 struct ib_device *ibdev = qp->ibqp.device;
137 struct mlx5_ib_dev *dev = to_mdev(ibdev);
138 struct mlx5_ib_wq *wq = send ? &qp->sq : &qp->rq;
139 size_t offset;
140 size_t wq_end;
141 struct ib_umem *umem = base->ubuffer.umem;
142 u32 first_copy_length;
143 int wqe_length;
144 int ret;
145
146 if (wq->wqe_cnt == 0) {
147 mlx5_ib_dbg(dev, "mlx5_ib_read_user_wqe for a QP with wqe_cnt == 0. qp_type: 0x%x\n",
148 qp->ibqp.qp_type);
149 return -EINVAL;
150 }
151
152 offset = wq->offset + ((wqe_index % wq->wqe_cnt) << wq->wqe_shift);
153 wq_end = wq->offset + (wq->wqe_cnt << wq->wqe_shift);
154
155 if (send && length < sizeof(struct mlx5_wqe_ctrl_seg))
156 return -EINVAL;
157
158 if (offset > umem->length ||
159 (send && offset + sizeof(struct mlx5_wqe_ctrl_seg) > umem->length))
160 return -EINVAL;
161
162 first_copy_length = min_t(u32, offset + length, wq_end) - offset;
163 ret = ib_umem_copy_from(buffer, umem, offset, first_copy_length);
164 if (ret)
165 return ret;
166
167 if (send) {
168 struct mlx5_wqe_ctrl_seg *ctrl = buffer;
169 int ds = be32_to_cpu(ctrl->qpn_ds) & MLX5_WQE_CTRL_DS_MASK;
170
171 wqe_length = ds * MLX5_WQE_DS_UNITS;
172 } else {
173 wqe_length = 1 << wq->wqe_shift;
174 }
175
176 if (wqe_length <= first_copy_length)
177 return first_copy_length;
178
179 ret = ib_umem_copy_from(buffer + first_copy_length, umem, wq->offset,
180 wqe_length - first_copy_length);
181 if (ret)
182 return ret;
183
184 return wqe_length;
185 }
186
mlx5_ib_qp_event(struct mlx5_core_qp * qp,int type)187 static void mlx5_ib_qp_event(struct mlx5_core_qp *qp, int type)
188 {
189 struct ib_qp *ibqp = &to_mibqp(qp)->ibqp;
190 struct ib_event event;
191
192 if (type == MLX5_EVENT_TYPE_PATH_MIG) {
193 /* This event is only valid for trans_qps */
194 to_mibqp(qp)->port = to_mibqp(qp)->trans_qp.alt_port;
195 }
196
197 if (ibqp->event_handler) {
198 event.device = ibqp->device;
199 event.element.qp = ibqp;
200 switch (type) {
201 case MLX5_EVENT_TYPE_PATH_MIG:
202 event.event = IB_EVENT_PATH_MIG;
203 break;
204 case MLX5_EVENT_TYPE_COMM_EST:
205 event.event = IB_EVENT_COMM_EST;
206 break;
207 case MLX5_EVENT_TYPE_SQ_DRAINED:
208 event.event = IB_EVENT_SQ_DRAINED;
209 break;
210 case MLX5_EVENT_TYPE_SRQ_LAST_WQE:
211 event.event = IB_EVENT_QP_LAST_WQE_REACHED;
212 break;
213 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR:
214 event.event = IB_EVENT_QP_FATAL;
215 break;
216 case MLX5_EVENT_TYPE_PATH_MIG_FAILED:
217 event.event = IB_EVENT_PATH_MIG_ERR;
218 break;
219 case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
220 event.event = IB_EVENT_QP_REQ_ERR;
221 break;
222 case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR:
223 event.event = IB_EVENT_QP_ACCESS_ERR;
224 break;
225 default:
226 pr_warn("mlx5_ib: Unexpected event type %d on QP %06x\n", type, qp->qpn);
227 return;
228 }
229
230 ibqp->event_handler(&event, ibqp->qp_context);
231 }
232 }
233
set_rq_size(struct mlx5_ib_dev * dev,struct ib_qp_cap * cap,int has_rq,struct mlx5_ib_qp * qp,struct mlx5_ib_create_qp * ucmd)234 static int set_rq_size(struct mlx5_ib_dev *dev, struct ib_qp_cap *cap,
235 int has_rq, struct mlx5_ib_qp *qp, struct mlx5_ib_create_qp *ucmd)
236 {
237 int wqe_size;
238 int wq_size;
239
240 /* Sanity check RQ size before proceeding */
241 if (cap->max_recv_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz)))
242 return -EINVAL;
243
244 if (!has_rq) {
245 qp->rq.max_gs = 0;
246 qp->rq.wqe_cnt = 0;
247 qp->rq.wqe_shift = 0;
248 cap->max_recv_wr = 0;
249 cap->max_recv_sge = 0;
250 } else {
251 if (ucmd) {
252 qp->rq.wqe_cnt = ucmd->rq_wqe_count;
253 qp->rq.wqe_shift = ucmd->rq_wqe_shift;
254 qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig;
255 qp->rq.max_post = qp->rq.wqe_cnt;
256 } else {
257 wqe_size = qp->wq_sig ? sizeof(struct mlx5_wqe_signature_seg) : 0;
258 wqe_size += cap->max_recv_sge * sizeof(struct mlx5_wqe_data_seg);
259 wqe_size = roundup_pow_of_two(wqe_size);
260 wq_size = roundup_pow_of_two(cap->max_recv_wr) * wqe_size;
261 wq_size = max_t(int, wq_size, MLX5_SEND_WQE_BB);
262 qp->rq.wqe_cnt = wq_size / wqe_size;
263 if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq)) {
264 mlx5_ib_dbg(dev, "wqe_size %d, max %d\n",
265 wqe_size,
266 MLX5_CAP_GEN(dev->mdev,
267 max_wqe_sz_rq));
268 return -EINVAL;
269 }
270 qp->rq.wqe_shift = ilog2(wqe_size);
271 qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig;
272 qp->rq.max_post = qp->rq.wqe_cnt;
273 }
274 }
275
276 return 0;
277 }
278
sq_overhead(struct ib_qp_init_attr * attr)279 static int sq_overhead(struct ib_qp_init_attr *attr)
280 {
281 int size = 0;
282
283 switch (attr->qp_type) {
284 case IB_QPT_XRC_INI:
285 size += sizeof(struct mlx5_wqe_xrc_seg);
286 /* fall through */
287 case IB_QPT_RC:
288 size += sizeof(struct mlx5_wqe_ctrl_seg) +
289 max(sizeof(struct mlx5_wqe_atomic_seg) +
290 sizeof(struct mlx5_wqe_raddr_seg),
291 sizeof(struct mlx5_wqe_umr_ctrl_seg) +
292 sizeof(struct mlx5_mkey_seg));
293 break;
294
295 case IB_QPT_XRC_TGT:
296 return 0;
297
298 case IB_QPT_UC:
299 size += sizeof(struct mlx5_wqe_ctrl_seg) +
300 max(sizeof(struct mlx5_wqe_raddr_seg),
301 sizeof(struct mlx5_wqe_umr_ctrl_seg) +
302 sizeof(struct mlx5_mkey_seg));
303 break;
304
305 case IB_QPT_UD:
306 if (attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)
307 size += sizeof(struct mlx5_wqe_eth_pad) +
308 sizeof(struct mlx5_wqe_eth_seg);
309 /* fall through */
310 case IB_QPT_SMI:
311 case MLX5_IB_QPT_HW_GSI:
312 size += sizeof(struct mlx5_wqe_ctrl_seg) +
313 sizeof(struct mlx5_wqe_datagram_seg);
314 break;
315
316 case MLX5_IB_QPT_REG_UMR:
317 size += sizeof(struct mlx5_wqe_ctrl_seg) +
318 sizeof(struct mlx5_wqe_umr_ctrl_seg) +
319 sizeof(struct mlx5_mkey_seg);
320 break;
321
322 default:
323 return -EINVAL;
324 }
325
326 return size;
327 }
328
calc_send_wqe(struct ib_qp_init_attr * attr)329 static int calc_send_wqe(struct ib_qp_init_attr *attr)
330 {
331 int inl_size = 0;
332 int size;
333
334 size = sq_overhead(attr);
335 if (size < 0)
336 return size;
337
338 if (attr->cap.max_inline_data) {
339 inl_size = size + sizeof(struct mlx5_wqe_inline_seg) +
340 attr->cap.max_inline_data;
341 }
342
343 size += attr->cap.max_send_sge * sizeof(struct mlx5_wqe_data_seg);
344 if (attr->create_flags & IB_QP_CREATE_SIGNATURE_EN &&
345 ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB) < MLX5_SIG_WQE_SIZE)
346 return MLX5_SIG_WQE_SIZE;
347 else
348 return ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB);
349 }
350
get_send_sge(struct ib_qp_init_attr * attr,int wqe_size)351 static int get_send_sge(struct ib_qp_init_attr *attr, int wqe_size)
352 {
353 int max_sge;
354
355 if (attr->qp_type == IB_QPT_RC)
356 max_sge = (min_t(int, wqe_size, 512) -
357 sizeof(struct mlx5_wqe_ctrl_seg) -
358 sizeof(struct mlx5_wqe_raddr_seg)) /
359 sizeof(struct mlx5_wqe_data_seg);
360 else if (attr->qp_type == IB_QPT_XRC_INI)
361 max_sge = (min_t(int, wqe_size, 512) -
362 sizeof(struct mlx5_wqe_ctrl_seg) -
363 sizeof(struct mlx5_wqe_xrc_seg) -
364 sizeof(struct mlx5_wqe_raddr_seg)) /
365 sizeof(struct mlx5_wqe_data_seg);
366 else
367 max_sge = (wqe_size - sq_overhead(attr)) /
368 sizeof(struct mlx5_wqe_data_seg);
369
370 return min_t(int, max_sge, wqe_size - sq_overhead(attr) /
371 sizeof(struct mlx5_wqe_data_seg));
372 }
373
calc_sq_size(struct mlx5_ib_dev * dev,struct ib_qp_init_attr * attr,struct mlx5_ib_qp * qp)374 static int calc_sq_size(struct mlx5_ib_dev *dev, struct ib_qp_init_attr *attr,
375 struct mlx5_ib_qp *qp)
376 {
377 int wqe_size;
378 int wq_size;
379
380 if (!attr->cap.max_send_wr)
381 return 0;
382
383 wqe_size = calc_send_wqe(attr);
384 mlx5_ib_dbg(dev, "wqe_size %d\n", wqe_size);
385 if (wqe_size < 0)
386 return wqe_size;
387
388 if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) {
389 mlx5_ib_dbg(dev, "wqe_size(%d) > max_sq_desc_sz(%d)\n",
390 wqe_size, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq));
391 return -EINVAL;
392 }
393
394 qp->max_inline_data = wqe_size - sq_overhead(attr) -
395 sizeof(struct mlx5_wqe_inline_seg);
396 attr->cap.max_inline_data = qp->max_inline_data;
397
398 if (attr->create_flags & IB_QP_CREATE_SIGNATURE_EN)
399 qp->signature_en = true;
400
401 wq_size = roundup_pow_of_two(attr->cap.max_send_wr * wqe_size);
402 qp->sq.wqe_cnt = wq_size / MLX5_SEND_WQE_BB;
403 if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) {
404 mlx5_ib_dbg(dev, "wqe count(%d) exceeds limits(%d)\n",
405 qp->sq.wqe_cnt,
406 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz));
407 return -ENOMEM;
408 }
409 qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB);
410 qp->sq.max_gs = get_send_sge(attr, wqe_size);
411 if (qp->sq.max_gs < attr->cap.max_send_sge)
412 return -ENOMEM;
413
414 attr->cap.max_send_sge = qp->sq.max_gs;
415 qp->sq.max_post = wq_size / wqe_size;
416 attr->cap.max_send_wr = qp->sq.max_post;
417
418 return wq_size;
419 }
420
set_user_buf_size(struct mlx5_ib_dev * dev,struct mlx5_ib_qp * qp,struct mlx5_ib_create_qp * ucmd,struct mlx5_ib_qp_base * base,struct ib_qp_init_attr * attr)421 static int set_user_buf_size(struct mlx5_ib_dev *dev,
422 struct mlx5_ib_qp *qp,
423 struct mlx5_ib_create_qp *ucmd,
424 struct mlx5_ib_qp_base *base,
425 struct ib_qp_init_attr *attr)
426 {
427 int desc_sz = 1 << qp->sq.wqe_shift;
428
429 if (desc_sz > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) {
430 mlx5_ib_warn(dev, "desc_sz %d, max_sq_desc_sz %d\n",
431 desc_sz, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq));
432 return -EINVAL;
433 }
434
435 if (ucmd->sq_wqe_count && ((1 << ilog2(ucmd->sq_wqe_count)) != ucmd->sq_wqe_count)) {
436 mlx5_ib_warn(dev, "sq_wqe_count %d, sq_wqe_count %d\n",
437 ucmd->sq_wqe_count, ucmd->sq_wqe_count);
438 return -EINVAL;
439 }
440
441 qp->sq.wqe_cnt = ucmd->sq_wqe_count;
442
443 if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) {
444 mlx5_ib_warn(dev, "wqe_cnt %d, max_wqes %d\n",
445 qp->sq.wqe_cnt,
446 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz));
447 return -EINVAL;
448 }
449
450 if (attr->qp_type == IB_QPT_RAW_PACKET) {
451 base->ubuffer.buf_size = qp->rq.wqe_cnt << qp->rq.wqe_shift;
452 qp->raw_packet_qp.sq.ubuffer.buf_size = qp->sq.wqe_cnt << 6;
453 } else {
454 base->ubuffer.buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
455 (qp->sq.wqe_cnt << 6);
456 }
457
458 return 0;
459 }
460
qp_has_rq(struct ib_qp_init_attr * attr)461 static int qp_has_rq(struct ib_qp_init_attr *attr)
462 {
463 if (attr->qp_type == IB_QPT_XRC_INI ||
464 attr->qp_type == IB_QPT_XRC_TGT || attr->srq ||
465 attr->qp_type == MLX5_IB_QPT_REG_UMR ||
466 !attr->cap.max_recv_wr)
467 return 0;
468
469 return 1;
470 }
471
472 enum {
473 /* this is the first blue flame register in the array of bfregs assigned
474 * to a processes. Since we do not use it for blue flame but rather
475 * regular 64 bit doorbells, we do not need a lock for maintaiing
476 * "odd/even" order
477 */
478 NUM_NON_BLUE_FLAME_BFREGS = 1,
479 };
480
max_bfregs(struct mlx5_ib_dev * dev,struct mlx5_bfreg_info * bfregi)481 static int max_bfregs(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi)
482 {
483 return get_num_static_uars(dev, bfregi) * MLX5_NON_FP_BFREGS_PER_UAR;
484 }
485
num_med_bfreg(struct mlx5_ib_dev * dev,struct mlx5_bfreg_info * bfregi)486 static int num_med_bfreg(struct mlx5_ib_dev *dev,
487 struct mlx5_bfreg_info *bfregi)
488 {
489 int n;
490
491 n = max_bfregs(dev, bfregi) - bfregi->num_low_latency_bfregs -
492 NUM_NON_BLUE_FLAME_BFREGS;
493
494 return n >= 0 ? n : 0;
495 }
496
first_med_bfreg(struct mlx5_ib_dev * dev,struct mlx5_bfreg_info * bfregi)497 static int first_med_bfreg(struct mlx5_ib_dev *dev,
498 struct mlx5_bfreg_info *bfregi)
499 {
500 return num_med_bfreg(dev, bfregi) ? 1 : -ENOMEM;
501 }
502
first_hi_bfreg(struct mlx5_ib_dev * dev,struct mlx5_bfreg_info * bfregi)503 static int first_hi_bfreg(struct mlx5_ib_dev *dev,
504 struct mlx5_bfreg_info *bfregi)
505 {
506 int med;
507
508 med = num_med_bfreg(dev, bfregi);
509 return ++med;
510 }
511
alloc_high_class_bfreg(struct mlx5_ib_dev * dev,struct mlx5_bfreg_info * bfregi)512 static int alloc_high_class_bfreg(struct mlx5_ib_dev *dev,
513 struct mlx5_bfreg_info *bfregi)
514 {
515 int i;
516
517 for (i = first_hi_bfreg(dev, bfregi); i < max_bfregs(dev, bfregi); i++) {
518 if (!bfregi->count[i]) {
519 bfregi->count[i]++;
520 return i;
521 }
522 }
523
524 return -ENOMEM;
525 }
526
alloc_med_class_bfreg(struct mlx5_ib_dev * dev,struct mlx5_bfreg_info * bfregi)527 static int alloc_med_class_bfreg(struct mlx5_ib_dev *dev,
528 struct mlx5_bfreg_info *bfregi)
529 {
530 int minidx = first_med_bfreg(dev, bfregi);
531 int i;
532
533 if (minidx < 0)
534 return minidx;
535
536 for (i = minidx; i < first_hi_bfreg(dev, bfregi); i++) {
537 if (bfregi->count[i] < bfregi->count[minidx])
538 minidx = i;
539 if (!bfregi->count[minidx])
540 break;
541 }
542
543 bfregi->count[minidx]++;
544 return minidx;
545 }
546
alloc_bfreg(struct mlx5_ib_dev * dev,struct mlx5_bfreg_info * bfregi)547 static int alloc_bfreg(struct mlx5_ib_dev *dev,
548 struct mlx5_bfreg_info *bfregi)
549 {
550 int bfregn = -ENOMEM;
551
552 if (bfregi->lib_uar_dyn)
553 return -EINVAL;
554
555 mutex_lock(&bfregi->lock);
556 if (bfregi->ver >= 2) {
557 bfregn = alloc_high_class_bfreg(dev, bfregi);
558 if (bfregn < 0)
559 bfregn = alloc_med_class_bfreg(dev, bfregi);
560 }
561
562 if (bfregn < 0) {
563 BUILD_BUG_ON(NUM_NON_BLUE_FLAME_BFREGS != 1);
564 bfregn = 0;
565 bfregi->count[bfregn]++;
566 }
567 mutex_unlock(&bfregi->lock);
568
569 return bfregn;
570 }
571
mlx5_ib_free_bfreg(struct mlx5_ib_dev * dev,struct mlx5_bfreg_info * bfregi,int bfregn)572 void mlx5_ib_free_bfreg(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi, int bfregn)
573 {
574 mutex_lock(&bfregi->lock);
575 bfregi->count[bfregn]--;
576 mutex_unlock(&bfregi->lock);
577 }
578
to_mlx5_state(enum ib_qp_state state)579 static enum mlx5_qp_state to_mlx5_state(enum ib_qp_state state)
580 {
581 switch (state) {
582 case IB_QPS_RESET: return MLX5_QP_STATE_RST;
583 case IB_QPS_INIT: return MLX5_QP_STATE_INIT;
584 case IB_QPS_RTR: return MLX5_QP_STATE_RTR;
585 case IB_QPS_RTS: return MLX5_QP_STATE_RTS;
586 case IB_QPS_SQD: return MLX5_QP_STATE_SQD;
587 case IB_QPS_SQE: return MLX5_QP_STATE_SQER;
588 case IB_QPS_ERR: return MLX5_QP_STATE_ERR;
589 default: return -1;
590 }
591 }
592
to_mlx5_st(enum ib_qp_type type)593 static int to_mlx5_st(enum ib_qp_type type)
594 {
595 switch (type) {
596 case IB_QPT_RC: return MLX5_QP_ST_RC;
597 case IB_QPT_UC: return MLX5_QP_ST_UC;
598 case IB_QPT_UD: return MLX5_QP_ST_UD;
599 case MLX5_IB_QPT_REG_UMR: return MLX5_QP_ST_REG_UMR;
600 case IB_QPT_XRC_INI:
601 case IB_QPT_XRC_TGT: return MLX5_QP_ST_XRC;
602 case IB_QPT_SMI: return MLX5_QP_ST_QP0;
603 case MLX5_IB_QPT_HW_GSI: return MLX5_QP_ST_QP1;
604 case IB_QPT_RAW_IPV6: return MLX5_QP_ST_RAW_IPV6;
605 case IB_QPT_RAW_PACKET:
606 case IB_QPT_RAW_ETHERTYPE: return MLX5_QP_ST_RAW_ETHERTYPE;
607 case IB_QPT_MAX:
608 default: return -EINVAL;
609 }
610 }
611
612 static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq,
613 struct mlx5_ib_cq *recv_cq);
614 static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq,
615 struct mlx5_ib_cq *recv_cq);
616
bfregn_to_uar_index(struct mlx5_ib_dev * dev,struct mlx5_bfreg_info * bfregi,u32 bfregn,bool dyn_bfreg)617 int bfregn_to_uar_index(struct mlx5_ib_dev *dev,
618 struct mlx5_bfreg_info *bfregi, u32 bfregn,
619 bool dyn_bfreg)
620 {
621 unsigned int bfregs_per_sys_page;
622 u32 index_of_sys_page;
623 u32 offset;
624
625 if (bfregi->lib_uar_dyn)
626 return -EINVAL;
627
628 bfregs_per_sys_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k) *
629 MLX5_NON_FP_BFREGS_PER_UAR;
630 index_of_sys_page = bfregn / bfregs_per_sys_page;
631
632 if (dyn_bfreg) {
633 index_of_sys_page += bfregi->num_static_sys_pages;
634
635 if (index_of_sys_page >= bfregi->num_sys_pages)
636 return -EINVAL;
637
638 if (bfregn > bfregi->num_dyn_bfregs ||
639 bfregi->sys_pages[index_of_sys_page] == MLX5_IB_INVALID_UAR_INDEX) {
640 mlx5_ib_dbg(dev, "Invalid dynamic uar index\n");
641 return -EINVAL;
642 }
643 }
644
645 offset = bfregn % bfregs_per_sys_page / MLX5_NON_FP_BFREGS_PER_UAR;
646 return bfregi->sys_pages[index_of_sys_page] + offset;
647 }
648
mlx5_ib_umem_get(struct mlx5_ib_dev * dev,struct ib_pd * pd,unsigned long addr,size_t size,struct ib_umem ** umem,int * npages,int * page_shift,int * ncont,u32 * offset)649 static int mlx5_ib_umem_get(struct mlx5_ib_dev *dev,
650 struct ib_pd *pd,
651 unsigned long addr, size_t size,
652 struct ib_umem **umem,
653 int *npages, int *page_shift, int *ncont,
654 u32 *offset)
655 {
656 int err;
657
658 *umem = ib_umem_get(pd->uobject->context, addr, size, 0, 0);
659 if (IS_ERR(*umem)) {
660 mlx5_ib_dbg(dev, "umem_get failed\n");
661 return PTR_ERR(*umem);
662 }
663
664 mlx5_ib_cont_pages(*umem, addr, 0, npages, page_shift, ncont, NULL);
665
666 err = mlx5_ib_get_buf_offset(addr, *page_shift, offset);
667 if (err) {
668 mlx5_ib_warn(dev, "bad offset\n");
669 goto err_umem;
670 }
671
672 mlx5_ib_dbg(dev, "addr 0x%lx, size %zu, npages %d, page_shift %d, ncont %d, offset %d\n",
673 addr, size, *npages, *page_shift, *ncont, *offset);
674
675 return 0;
676
677 err_umem:
678 ib_umem_release(*umem);
679 *umem = NULL;
680
681 return err;
682 }
683
destroy_user_rq(struct ib_pd * pd,struct mlx5_ib_rwq * rwq,struct ib_udata * udata)684 static void destroy_user_rq(struct ib_pd *pd, struct mlx5_ib_rwq *rwq,
685 struct ib_udata *udata)
686 {
687 struct mlx5_ib_ucontext *context =
688 rdma_udata_to_drv_context(
689 udata,
690 struct mlx5_ib_ucontext,
691 ibucontext);
692
693 mlx5_ib_db_unmap_user(context, &rwq->db);
694 if (rwq->umem)
695 ib_umem_release(rwq->umem);
696 }
697
create_user_rq(struct mlx5_ib_dev * dev,struct ib_pd * pd,struct mlx5_ib_rwq * rwq,struct mlx5_ib_create_wq * ucmd)698 static int create_user_rq(struct mlx5_ib_dev *dev, struct ib_pd *pd,
699 struct mlx5_ib_rwq *rwq,
700 struct mlx5_ib_create_wq *ucmd)
701 {
702 struct mlx5_ib_ucontext *context;
703 int page_shift = 0;
704 int npages;
705 u32 offset = 0;
706 int ncont = 0;
707 int err;
708
709 if (!ucmd->buf_addr)
710 return -EINVAL;
711
712 context = to_mucontext(pd->uobject->context);
713 rwq->umem = ib_umem_get(pd->uobject->context, ucmd->buf_addr,
714 rwq->buf_size, 0, 0);
715 if (IS_ERR(rwq->umem)) {
716 mlx5_ib_dbg(dev, "umem_get failed\n");
717 err = PTR_ERR(rwq->umem);
718 return err;
719 }
720
721 mlx5_ib_cont_pages(rwq->umem, ucmd->buf_addr, 0, &npages, &page_shift,
722 &ncont, NULL);
723 err = mlx5_ib_get_buf_offset(ucmd->buf_addr, page_shift,
724 &rwq->rq_page_offset);
725 if (err) {
726 mlx5_ib_warn(dev, "bad offset\n");
727 goto err_umem;
728 }
729
730 rwq->rq_num_pas = ncont;
731 rwq->page_shift = page_shift;
732 rwq->log_page_size = page_shift - MLX5_ADAPTER_PAGE_SHIFT;
733 rwq->wq_sig = !!(ucmd->flags & MLX5_WQ_FLAG_SIGNATURE);
734
735 mlx5_ib_dbg(dev, "addr 0x%llx, size %zd, npages %d, page_shift %d, ncont %d, offset %d\n",
736 (unsigned long long)ucmd->buf_addr, rwq->buf_size,
737 npages, page_shift, ncont, offset);
738
739 err = mlx5_ib_db_map_user(context, ucmd->db_addr, &rwq->db);
740 if (err) {
741 mlx5_ib_dbg(dev, "map failed\n");
742 goto err_umem;
743 }
744
745 rwq->create_type = MLX5_WQ_USER;
746 return 0;
747
748 err_umem:
749 ib_umem_release(rwq->umem);
750 return err;
751 }
752
adjust_bfregn(struct mlx5_ib_dev * dev,struct mlx5_bfreg_info * bfregi,int bfregn)753 static int adjust_bfregn(struct mlx5_ib_dev *dev,
754 struct mlx5_bfreg_info *bfregi, int bfregn)
755 {
756 return bfregn / MLX5_NON_FP_BFREGS_PER_UAR * MLX5_BFREGS_PER_UAR +
757 bfregn % MLX5_NON_FP_BFREGS_PER_UAR;
758 }
759
create_user_qp(struct mlx5_ib_dev * dev,struct ib_pd * pd,struct mlx5_ib_qp * qp,struct ib_udata * udata,struct ib_qp_init_attr * attr,u32 ** in,struct mlx5_ib_create_qp_resp * resp,int * inlen,struct mlx5_ib_qp_base * base)760 static int create_user_qp(struct mlx5_ib_dev *dev, struct ib_pd *pd,
761 struct mlx5_ib_qp *qp, struct ib_udata *udata,
762 struct ib_qp_init_attr *attr,
763 u32 **in,
764 struct mlx5_ib_create_qp_resp *resp, int *inlen,
765 struct mlx5_ib_qp_base *base)
766 {
767 struct mlx5_ib_ucontext *context;
768 struct mlx5_ib_create_qp ucmd;
769 struct mlx5_ib_ubuffer *ubuffer = &base->ubuffer;
770 int page_shift = 0;
771 int uar_index = 0;
772 int npages;
773 u32 offset = 0;
774 int bfregn;
775 int ncont = 0;
776 __be64 *pas;
777 void *qpc;
778 int err;
779 u16 uid;
780 u32 uar_flags;
781
782 err = ib_copy_from_udata(&ucmd, udata, sizeof(ucmd));
783 if (err) {
784 mlx5_ib_dbg(dev, "copy failed\n");
785 return err;
786 }
787
788 context = to_mucontext(pd->uobject->context);
789 uar_flags = ucmd.flags & (MLX5_QP_FLAG_UAR_PAGE_INDEX |
790 MLX5_QP_FLAG_BFREG_INDEX);
791 switch (uar_flags) {
792 case MLX5_QP_FLAG_UAR_PAGE_INDEX:
793 uar_index = ucmd.bfreg_index;
794 bfregn = MLX5_IB_INVALID_BFREG;
795 break;
796 case MLX5_QP_FLAG_BFREG_INDEX:
797 uar_index = bfregn_to_uar_index(dev, &context->bfregi,
798 ucmd.bfreg_index, true);
799 if (uar_index < 0)
800 return uar_index;
801 bfregn = MLX5_IB_INVALID_BFREG;
802 break;
803 case 0:
804 if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL)
805 return -EINVAL;
806 bfregn = alloc_bfreg(dev, &context->bfregi);
807 if (bfregn < 0)
808 return bfregn;
809 break;
810 default:
811 return -EINVAL;
812 }
813
814 mlx5_ib_dbg(dev, "bfregn 0x%x, uar_index 0x%x\n", bfregn, uar_index);
815 if (bfregn != MLX5_IB_INVALID_BFREG)
816 uar_index = bfregn_to_uar_index(dev, &context->bfregi, bfregn,
817 false);
818
819 qp->rq.offset = 0;
820 qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB);
821 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
822
823 err = set_user_buf_size(dev, qp, &ucmd, base, attr);
824 if (err)
825 goto err_bfreg;
826
827 if (ucmd.buf_addr && ubuffer->buf_size) {
828 ubuffer->buf_addr = ucmd.buf_addr;
829 err = mlx5_ib_umem_get(dev, pd, ubuffer->buf_addr,
830 ubuffer->buf_size,
831 &ubuffer->umem, &npages, &page_shift,
832 &ncont, &offset);
833 if (err)
834 goto err_bfreg;
835 } else {
836 ubuffer->umem = NULL;
837 }
838
839 *inlen = MLX5_ST_SZ_BYTES(create_qp_in) +
840 MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * ncont;
841 *in = mlx5_vzalloc(*inlen);
842 if (!*in) {
843 err = -ENOMEM;
844 goto err_umem;
845 }
846
847 uid = (attr->qp_type != IB_QPT_XRC_TGT &&
848 attr->qp_type != IB_QPT_XRC_INI) ? to_mpd(pd)->uid : 0;
849 MLX5_SET(create_qp_in, *in, uid, uid);
850 pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, *in, pas);
851 if (ubuffer->umem)
852 mlx5_ib_populate_pas(dev, ubuffer->umem, page_shift, pas, 0);
853
854 qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc);
855
856 MLX5_SET(qpc, qpc, log_page_size, page_shift - MLX5_ADAPTER_PAGE_SHIFT);
857 MLX5_SET(qpc, qpc, page_offset, offset);
858
859 MLX5_SET(qpc, qpc, uar_page, uar_index);
860 if (bfregn != MLX5_IB_INVALID_BFREG)
861 resp->bfreg_index = adjust_bfregn(dev, &context->bfregi, bfregn);
862 else
863 resp->bfreg_index = MLX5_IB_INVALID_BFREG;
864 qp->bfregn = bfregn;
865
866 err = mlx5_ib_db_map_user(context, ucmd.db_addr, &qp->db);
867 if (err) {
868 mlx5_ib_dbg(dev, "map failed\n");
869 goto err_free;
870 }
871
872 err = ib_copy_to_udata(udata, resp, sizeof(*resp));
873 if (err) {
874 mlx5_ib_dbg(dev, "copy failed\n");
875 goto err_unmap;
876 }
877 qp->create_type = MLX5_QP_USER;
878
879 return 0;
880
881 err_unmap:
882 mlx5_ib_db_unmap_user(context, &qp->db);
883
884 err_free:
885 kvfree(*in);
886
887 err_umem:
888 if (ubuffer->umem)
889 ib_umem_release(ubuffer->umem);
890
891 err_bfreg:
892 if (bfregn != MLX5_IB_INVALID_BFREG)
893 mlx5_ib_free_bfreg(dev, &context->bfregi, bfregn);
894 return err;
895 }
896
destroy_qp_user(struct mlx5_ib_dev * dev,struct ib_pd * pd,struct mlx5_ib_qp * qp,struct mlx5_ib_qp_base * base,struct ib_udata * udata)897 static void destroy_qp_user(struct mlx5_ib_dev *dev, struct ib_pd *pd, struct mlx5_ib_qp *qp,
898 struct mlx5_ib_qp_base *base,
899 struct ib_udata *udata)
900 {
901 struct mlx5_ib_ucontext *context =
902 rdma_udata_to_drv_context(
903 udata,
904 struct mlx5_ib_ucontext,
905 ibucontext);
906
907 mlx5_ib_db_unmap_user(context, &qp->db);
908 if (base->ubuffer.umem)
909 ib_umem_release(base->ubuffer.umem);
910
911 /*
912 * Free only the BFREGs which are handled by the kernel.
913 * BFREGs of UARs allocated dynamically are handled by user.
914 */
915 if (qp->bfregn != MLX5_IB_INVALID_BFREG)
916 mlx5_ib_free_bfreg(dev, &context->bfregi, qp->bfregn);
917 }
918
create_kernel_qp(struct mlx5_ib_dev * dev,struct ib_qp_init_attr * init_attr,struct mlx5_ib_qp * qp,u32 ** in,int * inlen,struct mlx5_ib_qp_base * base)919 static int create_kernel_qp(struct mlx5_ib_dev *dev,
920 struct ib_qp_init_attr *init_attr,
921 struct mlx5_ib_qp *qp,
922 u32 **in, int *inlen,
923 struct mlx5_ib_qp_base *base)
924 {
925 int uar_index;
926 void *qpc;
927 int err;
928
929 if (init_attr->create_flags & ~(IB_QP_CREATE_SIGNATURE_EN |
930 IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK |
931 IB_QP_CREATE_IPOIB_UD_LSO |
932 IB_QP_CREATE_SCATTER_FCS |
933 IB_QP_CREATE_CVLAN_STRIPPING |
934 MLX5_IB_QP_CREATE_SQPN_QP1 |
935 MLX5_IB_QP_CREATE_WC_TEST))
936 return -EINVAL;
937
938 spin_lock_init(&qp->bf.lock32);
939
940 if (init_attr->qp_type == MLX5_IB_QPT_REG_UMR)
941 qp->bf.bfreg = &dev->fp_bfreg;
942 else if (init_attr->create_flags & MLX5_IB_QP_CREATE_WC_TEST)
943 qp->bf.bfreg = &dev->wc_bfreg;
944 else
945 qp->bf.bfreg = &dev->bfreg;
946
947 /* We need to divide by two since each register is comprised of
948 * two buffers of identical size, namely odd and even
949 */
950 qp->bf.buf_size = (1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size)) / 2;
951 uar_index = qp->bf.bfreg->index;
952
953 err = calc_sq_size(dev, init_attr, qp);
954 if (err < 0) {
955 mlx5_ib_dbg(dev, "err %d\n", err);
956 return err;
957 }
958
959 qp->rq.offset = 0;
960 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
961 base->ubuffer.buf_size = err + (qp->rq.wqe_cnt << qp->rq.wqe_shift);
962
963 err = mlx5_buf_alloc(dev->mdev, base->ubuffer.buf_size,
964 2 * PAGE_SIZE, &qp->buf);
965 if (err) {
966 mlx5_ib_dbg(dev, "err %d\n", err);
967 return err;
968 }
969
970 qp->sq.qend = mlx5_get_send_wqe(qp, qp->sq.wqe_cnt);
971 *inlen = MLX5_ST_SZ_BYTES(create_qp_in) +
972 MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * qp->buf.npages;
973 *in = mlx5_vzalloc(*inlen);
974 if (!*in) {
975 err = -ENOMEM;
976 goto err_buf;
977 }
978
979 qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc);
980 MLX5_SET(qpc, qpc, uar_page, uar_index);
981 MLX5_SET(qpc, qpc, ts_format, mlx5_get_qp_default_ts(dev->mdev));
982 MLX5_SET(qpc, qpc, log_page_size, qp->buf.page_shift - MLX5_ADAPTER_PAGE_SHIFT);
983
984 /* Set "fast registration enabled" for all kernel QPs */
985 MLX5_SET(qpc, qpc, fre, 1);
986 MLX5_SET(qpc, qpc, rlky, 1);
987
988 if (init_attr->create_flags & MLX5_IB_QP_CREATE_SQPN_QP1) {
989 MLX5_SET(qpc, qpc, deth_sqpn, 1);
990 qp->flags |= MLX5_IB_QP_SQPN_QP1;
991 }
992
993 mlx5_fill_page_array(&qp->buf,
994 (__be64 *)MLX5_ADDR_OF(create_qp_in, *in, pas));
995
996 err = mlx5_db_alloc(dev->mdev, &qp->db);
997 if (err) {
998 mlx5_ib_dbg(dev, "err %d\n", err);
999 goto err_free;
1000 }
1001
1002 qp->sq.wrid = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.wrid), GFP_KERNEL);
1003 qp->sq.wr_data = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.wr_data), GFP_KERNEL);
1004 qp->rq.wrid = kmalloc(qp->rq.wqe_cnt * sizeof(*qp->rq.wrid), GFP_KERNEL);
1005 qp->sq.w_list = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.w_list), GFP_KERNEL);
1006 qp->sq.wqe_head = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.wqe_head), GFP_KERNEL);
1007
1008 if (!qp->sq.wrid || !qp->sq.wr_data || !qp->rq.wrid ||
1009 !qp->sq.w_list || !qp->sq.wqe_head) {
1010 err = -ENOMEM;
1011 goto err_wrid;
1012 }
1013 qp->create_type = MLX5_QP_KERNEL;
1014
1015 return 0;
1016
1017 err_wrid:
1018 kfree(qp->sq.wqe_head);
1019 kfree(qp->sq.w_list);
1020 kfree(qp->sq.wrid);
1021 kfree(qp->sq.wr_data);
1022 kfree(qp->rq.wrid);
1023 mlx5_db_free(dev->mdev, &qp->db);
1024
1025 err_free:
1026 kvfree(*in);
1027
1028 err_buf:
1029 mlx5_buf_free(dev->mdev, &qp->buf);
1030 return err;
1031 }
1032
destroy_qp_kernel(struct mlx5_ib_dev * dev,struct mlx5_ib_qp * qp)1033 static void destroy_qp_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
1034 {
1035 kfree(qp->sq.wqe_head);
1036 kfree(qp->sq.w_list);
1037 kfree(qp->sq.wrid);
1038 kfree(qp->sq.wr_data);
1039 kfree(qp->rq.wrid);
1040 mlx5_db_free(dev->mdev, &qp->db);
1041 mlx5_buf_free(dev->mdev, &qp->buf);
1042 }
1043
get_rx_type(struct mlx5_ib_qp * qp,struct ib_qp_init_attr * attr)1044 static u32 get_rx_type(struct mlx5_ib_qp *qp, struct ib_qp_init_attr *attr)
1045 {
1046 if (attr->srq || (attr->qp_type == IB_QPT_XRC_TGT) ||
1047 (attr->qp_type == IB_QPT_XRC_INI))
1048 return MLX5_SRQ_RQ;
1049 else if (!qp->has_rq)
1050 return MLX5_ZERO_LEN_RQ;
1051 else
1052 return MLX5_NON_ZERO_RQ;
1053 }
1054
is_connected(enum ib_qp_type qp_type)1055 static int is_connected(enum ib_qp_type qp_type)
1056 {
1057 if (qp_type == IB_QPT_RC || qp_type == IB_QPT_UC)
1058 return 1;
1059
1060 return 0;
1061 }
1062
create_raw_packet_qp_tis(struct mlx5_ib_dev * dev,struct mlx5_ib_sq * sq,u32 tdn,struct ib_pd * pd)1063 static int create_raw_packet_qp_tis(struct mlx5_ib_dev *dev,
1064 struct mlx5_ib_sq *sq, u32 tdn,
1065 struct ib_pd *pd)
1066 {
1067 u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {0};
1068 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
1069
1070 MLX5_SET(create_tis_in, in, uid, to_mpd(pd)->uid);
1071 MLX5_SET(tisc, tisc, transport_domain, tdn);
1072 return mlx5_core_create_tis(dev->mdev, in, sizeof(in), &sq->tisn);
1073 }
1074
destroy_raw_packet_qp_tis(struct mlx5_ib_dev * dev,struct mlx5_ib_sq * sq,struct ib_pd * pd)1075 static void destroy_raw_packet_qp_tis(struct mlx5_ib_dev *dev,
1076 struct mlx5_ib_sq *sq, struct ib_pd *pd)
1077 {
1078 mlx5_core_destroy_tis(dev->mdev, sq->tisn, to_mpd(pd)->uid);
1079 }
1080
create_raw_packet_qp_sq(struct mlx5_ib_dev * dev,struct mlx5_ib_sq * sq,void * qpin,struct ib_pd * pd)1081 static int create_raw_packet_qp_sq(struct mlx5_ib_dev *dev,
1082 struct mlx5_ib_sq *sq, void *qpin,
1083 struct ib_pd *pd)
1084 {
1085 struct mlx5_ib_ubuffer *ubuffer = &sq->ubuffer;
1086 __be64 *pas;
1087 void *in;
1088 void *sqc;
1089 void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc);
1090 void *wq;
1091 int inlen;
1092 int err;
1093 int page_shift = 0;
1094 int npages;
1095 int ncont = 0;
1096 u32 offset = 0;
1097 u8 ts_format;
1098
1099 ts_format = mlx5_get_sq_default_ts(dev->mdev);
1100
1101 err = mlx5_ib_umem_get(dev, pd, ubuffer->buf_addr, ubuffer->buf_size,
1102 &sq->ubuffer.umem, &npages, &page_shift,
1103 &ncont, &offset);
1104 if (err)
1105 return err;
1106
1107 inlen = MLX5_ST_SZ_BYTES(create_sq_in) + sizeof(u64) * ncont;
1108 in = mlx5_vzalloc(inlen);
1109 if (!in) {
1110 err = -ENOMEM;
1111 goto err_umem;
1112 }
1113
1114 MLX5_SET(create_sq_in, in, uid, to_mpd(pd)->uid);
1115 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1116 MLX5_SET(sqc, sqc, flush_in_error_en, 1);
1117 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
1118 MLX5_SET(sqc, sqc, ts_format, ts_format);
1119 MLX5_SET(sqc, sqc, user_index, MLX5_GET(qpc, qpc, user_index));
1120 MLX5_SET(sqc, sqc, cqn, MLX5_GET(qpc, qpc, cqn_snd));
1121 MLX5_SET(sqc, sqc, tis_lst_sz, 1);
1122 MLX5_SET(sqc, sqc, tis_num_0, sq->tisn);
1123 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
1124 MLX5_CAP_ETH(dev->mdev, swp))
1125 MLX5_SET(sqc, sqc, allow_swp, 1);
1126
1127 wq = MLX5_ADDR_OF(sqc, sqc, wq);
1128 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1129 MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd));
1130 MLX5_SET(wq, wq, uar_page, MLX5_GET(qpc, qpc, uar_page));
1131 MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr));
1132 MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1133 MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_sq_size));
1134 MLX5_SET(wq, wq, log_wq_pg_sz, page_shift - MLX5_ADAPTER_PAGE_SHIFT);
1135 MLX5_SET(wq, wq, page_offset, offset);
1136
1137 pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
1138 mlx5_ib_populate_pas(dev, sq->ubuffer.umem, page_shift, pas, 0);
1139
1140 err = mlx5_core_create_sq_tracked(dev->mdev, in, inlen, &sq->base.mqp);
1141
1142 kvfree(in);
1143
1144 if (err)
1145 goto err_umem;
1146
1147 return 0;
1148
1149 err_umem:
1150 ib_umem_release(sq->ubuffer.umem);
1151 sq->ubuffer.umem = NULL;
1152
1153 return err;
1154 }
1155
destroy_raw_packet_qp_sq(struct mlx5_ib_dev * dev,struct mlx5_ib_sq * sq)1156 static void destroy_raw_packet_qp_sq(struct mlx5_ib_dev *dev,
1157 struct mlx5_ib_sq *sq)
1158 {
1159 mlx5_core_destroy_sq_tracked(dev->mdev, &sq->base.mqp);
1160 ib_umem_release(sq->ubuffer.umem);
1161 }
1162
get_rq_pas_size(void * qpc)1163 static int get_rq_pas_size(void *qpc)
1164 {
1165 u32 log_page_size = MLX5_GET(qpc, qpc, log_page_size) + 12;
1166 u32 log_rq_stride = MLX5_GET(qpc, qpc, log_rq_stride);
1167 u32 log_rq_size = MLX5_GET(qpc, qpc, log_rq_size);
1168 u32 page_offset = MLX5_GET(qpc, qpc, page_offset);
1169 u32 po_quanta = 1 << (log_page_size - 6);
1170 u32 rq_sz = 1 << (log_rq_size + 4 + log_rq_stride);
1171 u32 page_size = 1 << log_page_size;
1172 u32 rq_sz_po = rq_sz + (page_offset * po_quanta);
1173 u32 rq_num_pas = (rq_sz_po + page_size - 1) / page_size;
1174
1175 return rq_num_pas * sizeof(u64);
1176 }
1177
create_raw_packet_qp_rq(struct mlx5_ib_dev * dev,struct mlx5_ib_rq * rq,void * qpin,struct ib_pd * pd)1178 static int create_raw_packet_qp_rq(struct mlx5_ib_dev *dev,
1179 struct mlx5_ib_rq *rq, void *qpin,
1180 struct ib_pd *pd)
1181 {
1182 struct mlx5_ib_qp *mqp = rq->base.container_mibqp;
1183 __be64 *pas;
1184 __be64 *qp_pas;
1185 void *in;
1186 void *rqc;
1187 void *wq;
1188 void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc);
1189 int inlen;
1190 int err;
1191 u32 rq_pas_size = get_rq_pas_size(qpc);
1192 u8 ts_format;
1193
1194 ts_format = mlx5_get_rq_default_ts(dev->mdev);
1195
1196 inlen = MLX5_ST_SZ_BYTES(create_rq_in) + rq_pas_size;
1197 in = mlx5_vzalloc(inlen);
1198 if (!in)
1199 return -ENOMEM;
1200
1201 MLX5_SET(create_rq_in, in, uid, to_mpd(pd)->uid);
1202 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
1203 if (!(rq->flags & MLX5_IB_RQ_CVLAN_STRIPPING))
1204 MLX5_SET(rqc, rqc, vlan_strip_disable, 1);
1205 MLX5_SET(rqc, rqc, mem_rq_type, MLX5_RQC_RQ_TYPE_MEMORY_RQ_INLINE);
1206 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
1207 MLX5_SET(rqc, rqc, ts_format, ts_format);
1208 MLX5_SET(rqc, rqc, flush_in_error_en, 1);
1209 MLX5_SET(rqc, rqc, user_index, MLX5_GET(qpc, qpc, user_index));
1210 MLX5_SET(rqc, rqc, cqn, MLX5_GET(qpc, qpc, cqn_rcv));
1211
1212 if (mqp->flags & MLX5_IB_QP_CAP_SCATTER_FCS)
1213 MLX5_SET(rqc, rqc, scatter_fcs, 1);
1214
1215 wq = MLX5_ADDR_OF(rqc, rqc, wq);
1216 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1217 MLX5_SET(wq, wq, end_padding_mode,
1218 MLX5_GET(qpc, qpc, end_padding_mode));
1219 MLX5_SET(wq, wq, page_offset, MLX5_GET(qpc, qpc, page_offset));
1220 MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd));
1221 MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr));
1222 MLX5_SET(wq, wq, log_wq_stride, MLX5_GET(qpc, qpc, log_rq_stride) + 4);
1223 MLX5_SET(wq, wq, log_wq_pg_sz, MLX5_GET(qpc, qpc, log_page_size));
1224 MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_rq_size));
1225
1226 pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
1227 qp_pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, qpin, pas);
1228 memcpy(pas, qp_pas, rq_pas_size);
1229
1230 err = mlx5_core_create_rq_tracked(dev->mdev, in, inlen, &rq->base.mqp);
1231
1232 kvfree(in);
1233
1234 return err;
1235 }
1236
destroy_raw_packet_qp_rq(struct mlx5_ib_dev * dev,struct mlx5_ib_rq * rq)1237 static void destroy_raw_packet_qp_rq(struct mlx5_ib_dev *dev,
1238 struct mlx5_ib_rq *rq)
1239 {
1240 mlx5_core_destroy_rq_tracked(dev->mdev, &rq->base.mqp);
1241 }
1242
tunnel_offload_supported(struct mlx5_core_dev * dev)1243 static bool tunnel_offload_supported(struct mlx5_core_dev *dev)
1244 {
1245 return (MLX5_CAP_ETH(dev, tunnel_stateless_vxlan) ||
1246 MLX5_CAP_ETH(dev, tunnel_stateless_gre) ||
1247 MLX5_CAP_ETH(dev, tunnel_stateless_geneve_rx));
1248 }
1249
create_raw_packet_qp_tir(struct mlx5_ib_dev * dev,struct mlx5_ib_rq * rq,u32 tdn,struct ib_pd * pd,bool tunnel_offload_en)1250 static int create_raw_packet_qp_tir(struct mlx5_ib_dev *dev,
1251 struct mlx5_ib_rq *rq, u32 tdn,
1252 struct ib_pd *pd, bool tunnel_offload_en)
1253 {
1254 u32 *in;
1255 void *tirc;
1256 int inlen;
1257 int err;
1258
1259 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1260 in = mlx5_vzalloc(inlen);
1261 if (!in)
1262 return -ENOMEM;
1263
1264 MLX5_SET(create_tir_in, in, uid, to_mpd(pd)->uid);
1265 tirc = MLX5_ADDR_OF(create_tir_in, in, tir_context);
1266 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_DIRECT);
1267 MLX5_SET(tirc, tirc, inline_rqn, rq->base.mqp.qpn);
1268 MLX5_SET(tirc, tirc, transport_domain, tdn);
1269 if (tunnel_offload_en)
1270 MLX5_SET(tirc, tirc, tunneled_offload_en, 1);
1271
1272 err = mlx5_core_create_tir(dev->mdev, in, inlen, &rq->tirn);
1273
1274 kvfree(in);
1275
1276 return err;
1277 }
1278
destroy_raw_packet_qp_tir(struct mlx5_ib_dev * dev,struct mlx5_ib_rq * rq,struct ib_pd * pd)1279 static void destroy_raw_packet_qp_tir(struct mlx5_ib_dev *dev,
1280 struct mlx5_ib_rq *rq,
1281 struct ib_pd *pd)
1282 {
1283 mlx5_core_destroy_tir(dev->mdev, rq->tirn, to_mpd(pd)->uid);
1284 }
1285
create_raw_packet_qp(struct mlx5_ib_dev * dev,struct mlx5_ib_qp * qp,u32 * in,struct ib_pd * pd)1286 static int create_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
1287 u32 *in,
1288 struct ib_pd *pd)
1289 {
1290 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
1291 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1292 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1293 struct ib_uobject *uobj = pd->uobject;
1294 struct ib_ucontext *ucontext = uobj->context;
1295 struct mlx5_ib_ucontext *mucontext = to_mucontext(ucontext);
1296 int err;
1297 u32 tdn = mucontext->tdn;
1298
1299 if (qp->sq.wqe_cnt) {
1300 err = create_raw_packet_qp_tis(dev, sq, tdn, pd);
1301 if (err)
1302 return err;
1303
1304 err = create_raw_packet_qp_sq(dev, sq, in, pd);
1305 if (err)
1306 goto err_destroy_tis;
1307
1308 sq->base.container_mibqp = qp;
1309 }
1310
1311 if (qp->rq.wqe_cnt) {
1312 rq->base.container_mibqp = qp;
1313
1314 if (qp->flags & MLX5_IB_QP_CVLAN_STRIPPING)
1315 rq->flags |= MLX5_IB_RQ_CVLAN_STRIPPING;
1316 err = create_raw_packet_qp_rq(dev, rq, in, pd);
1317 if (err)
1318 goto err_destroy_sq;
1319
1320
1321 err = create_raw_packet_qp_tir(dev, rq, tdn, pd,
1322 qp->tunnel_offload_en);
1323 if (err)
1324 goto err_destroy_rq;
1325 }
1326
1327 qp->trans_qp.base.mqp.qpn = qp->sq.wqe_cnt ? sq->base.mqp.qpn :
1328 rq->base.mqp.qpn;
1329
1330 return 0;
1331
1332 err_destroy_rq:
1333 destroy_raw_packet_qp_rq(dev, rq);
1334 err_destroy_sq:
1335 if (!qp->sq.wqe_cnt)
1336 return err;
1337 destroy_raw_packet_qp_sq(dev, sq);
1338 err_destroy_tis:
1339 destroy_raw_packet_qp_tis(dev, sq, pd);
1340
1341 return err;
1342 }
1343
destroy_raw_packet_qp(struct mlx5_ib_dev * dev,struct mlx5_ib_qp * qp)1344 static void destroy_raw_packet_qp(struct mlx5_ib_dev *dev,
1345 struct mlx5_ib_qp *qp)
1346 {
1347 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
1348 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1349 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1350
1351 if (qp->rq.wqe_cnt) {
1352 destroy_raw_packet_qp_tir(dev, rq, qp->ibqp.pd);
1353 destroy_raw_packet_qp_rq(dev, rq);
1354 }
1355
1356 if (qp->sq.wqe_cnt) {
1357 destroy_raw_packet_qp_sq(dev, sq);
1358 destroy_raw_packet_qp_tis(dev, sq, qp->ibqp.pd);
1359 }
1360 }
1361
raw_packet_qp_copy_info(struct mlx5_ib_qp * qp,struct mlx5_ib_raw_packet_qp * raw_packet_qp)1362 static void raw_packet_qp_copy_info(struct mlx5_ib_qp *qp,
1363 struct mlx5_ib_raw_packet_qp *raw_packet_qp)
1364 {
1365 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1366 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1367
1368 sq->sq = &qp->sq;
1369 rq->rq = &qp->rq;
1370 sq->doorbell = &qp->db;
1371 rq->doorbell = &qp->db;
1372 }
1373
destroy_rss_raw_qp_tir(struct mlx5_ib_dev * dev,struct mlx5_ib_qp * qp)1374 static void destroy_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
1375 {
1376 mlx5_core_destroy_tir(dev->mdev, qp->rss_qp.tirn,
1377 to_mpd(qp->ibqp.pd)->uid);
1378 }
1379
create_rss_raw_qp_tir(struct mlx5_ib_dev * dev,struct mlx5_ib_qp * qp,struct ib_pd * pd,struct ib_qp_init_attr * init_attr,struct ib_udata * udata)1380 static int create_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
1381 struct ib_pd *pd,
1382 struct ib_qp_init_attr *init_attr,
1383 struct ib_udata *udata)
1384 {
1385 struct ib_uobject *uobj = pd->uobject;
1386 struct ib_ucontext *ucontext = uobj->context;
1387 struct mlx5_ib_ucontext *mucontext = to_mucontext(ucontext);
1388 struct mlx5_ib_create_qp_resp resp = {};
1389 int inlen;
1390 int err;
1391 u32 *in;
1392 void *tirc;
1393 void *hfso;
1394 u32 selected_fields = 0;
1395 size_t min_resp_len;
1396 u32 tdn = mucontext->tdn;
1397 struct mlx5_ib_create_qp_rss ucmd = {};
1398 size_t required_cmd_sz;
1399
1400 if (init_attr->qp_type != IB_QPT_RAW_PACKET)
1401 return -EOPNOTSUPP;
1402
1403 if (init_attr->create_flags || init_attr->send_cq)
1404 return -EINVAL;
1405
1406 min_resp_len = offsetof(typeof(resp), bfreg_index) + sizeof(resp.bfreg_index);
1407 if (udata->outlen < min_resp_len)
1408 return -EINVAL;
1409
1410 required_cmd_sz = offsetof(typeof(ucmd), flags) + sizeof(ucmd.flags);
1411 if (udata->inlen < required_cmd_sz) {
1412 mlx5_ib_dbg(dev, "invalid inlen\n");
1413 return -EINVAL;
1414 }
1415
1416 if (udata->inlen > sizeof(ucmd) &&
1417 !ib_is_udata_cleared(udata, sizeof(ucmd),
1418 udata->inlen - sizeof(ucmd))) {
1419 mlx5_ib_dbg(dev, "inlen is not supported\n");
1420 return -EOPNOTSUPP;
1421 }
1422
1423 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) {
1424 mlx5_ib_dbg(dev, "copy failed\n");
1425 return -EFAULT;
1426 }
1427
1428 if (ucmd.comp_mask) {
1429 mlx5_ib_dbg(dev, "invalid comp mask\n");
1430 return -EOPNOTSUPP;
1431 }
1432
1433 if (ucmd.flags & ~MLX5_QP_FLAG_TUNNEL_OFFLOADS) {
1434 mlx5_ib_dbg(dev, "invalid flags\n");
1435 return -EOPNOTSUPP;
1436 }
1437
1438 if (ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS &&
1439 !tunnel_offload_supported(dev->mdev)) {
1440 mlx5_ib_dbg(dev, "tunnel offloads isn't supported\n");
1441 return -EOPNOTSUPP;
1442 }
1443
1444 if (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_INNER &&
1445 !(ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS)) {
1446 mlx5_ib_dbg(dev, "Tunnel offloads must be set for inner RSS\n");
1447 return -EOPNOTSUPP;
1448 }
1449
1450 err = ib_copy_to_udata(udata, &resp, min_resp_len);
1451 if (err) {
1452 mlx5_ib_dbg(dev, "copy failed\n");
1453 return -EINVAL;
1454 }
1455
1456 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1457 in = mlx5_vzalloc(inlen);
1458 if (!in)
1459 return -ENOMEM;
1460
1461 MLX5_SET(create_tir_in, in, uid, to_mpd(pd)->uid);
1462 tirc = MLX5_ADDR_OF(create_tir_in, in, tir_context);
1463 MLX5_SET(tirc, tirc, disp_type,
1464 MLX5_TIRC_DISP_TYPE_INDIRECT);
1465 MLX5_SET(tirc, tirc, indirect_table,
1466 init_attr->rwq_ind_tbl->ind_tbl_num);
1467 MLX5_SET(tirc, tirc, transport_domain, tdn);
1468
1469 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
1470
1471 if (ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS)
1472 MLX5_SET(tirc, tirc, tunneled_offload_en, 1);
1473
1474 if (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_INNER)
1475 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_inner);
1476 else
1477 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
1478
1479 switch (ucmd.rx_hash_function) {
1480 case MLX5_RX_HASH_FUNC_TOEPLITZ:
1481 {
1482 void *rss_key = MLX5_ADDR_OF(tirc, tirc, rx_hash_toeplitz_key);
1483 size_t len = MLX5_FLD_SZ_BYTES(tirc, rx_hash_toeplitz_key);
1484
1485 if (len != ucmd.rx_key_len) {
1486 err = -EINVAL;
1487 goto err;
1488 }
1489
1490 MLX5_SET(tirc, tirc, rx_hash_fn,
1491 MLX5_TIRC_RX_HASH_FN_HASH_TOEPLITZ);
1492 memcpy(rss_key, ucmd.rx_hash_key, len);
1493 break;
1494 }
1495 default:
1496 err = -EOPNOTSUPP;
1497 goto err;
1498 }
1499
1500 if (!ucmd.rx_hash_fields_mask) {
1501 /* special case when this TIR serves as steering entry without hashing */
1502 if (!init_attr->rwq_ind_tbl->log_ind_tbl_size)
1503 goto create_tir;
1504 err = -EINVAL;
1505 goto err;
1506 }
1507
1508 if (((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1509 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4)) &&
1510 ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) ||
1511 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))) {
1512 err = -EINVAL;
1513 goto err;
1514 }
1515
1516 /* If none of IPV4 & IPV6 SRC/DST was set - this bit field is ignored */
1517 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1518 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4))
1519 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1520 MLX5_L3_PROT_TYPE_IPV4);
1521 else if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) ||
1522 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))
1523 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1524 MLX5_L3_PROT_TYPE_IPV6);
1525
1526 if (((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1527 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP)) &&
1528 ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) ||
1529 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))) {
1530 err = -EINVAL;
1531 goto err;
1532 }
1533
1534 /* If none of TCP & UDP SRC/DST was set - this bit field is ignored */
1535 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1536 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP))
1537 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1538 MLX5_L4_PROT_TYPE_TCP);
1539 else if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) ||
1540 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))
1541 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1542 MLX5_L4_PROT_TYPE_UDP);
1543
1544 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1545 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6))
1546 selected_fields |= MLX5_HASH_FIELD_SEL_SRC_IP;
1547
1548 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4) ||
1549 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))
1550 selected_fields |= MLX5_HASH_FIELD_SEL_DST_IP;
1551
1552 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1553 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP))
1554 selected_fields |= MLX5_HASH_FIELD_SEL_L4_SPORT;
1555
1556 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP) ||
1557 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))
1558 selected_fields |= MLX5_HASH_FIELD_SEL_L4_DPORT;
1559
1560 MLX5_SET(rx_hash_field_select, hfso, selected_fields, selected_fields);
1561
1562 create_tir:
1563 err = mlx5_core_create_tir(dev->mdev, in, inlen, &qp->rss_qp.tirn);
1564
1565 if (err)
1566 goto err;
1567
1568 kvfree(in);
1569 /* qpn is reserved for that QP */
1570 qp->trans_qp.base.mqp.qpn = 0;
1571 qp->flags |= MLX5_IB_QP_RSS;
1572 return 0;
1573
1574 err:
1575 kvfree(in);
1576 return err;
1577 }
1578
atomic_size_to_mode(int size_mask)1579 static int atomic_size_to_mode(int size_mask)
1580 {
1581 /* driver does not support atomic_size > 256B
1582 * and does not know how to translate bigger sizes
1583 */
1584 int supported_size_mask = size_mask & 0x1ff;
1585 int log_max_size;
1586
1587 if (!supported_size_mask)
1588 return -EOPNOTSUPP;
1589
1590 log_max_size = __fls(supported_size_mask);
1591
1592 if (log_max_size > 3)
1593 return log_max_size;
1594
1595 return MLX5_ATOMIC_MODE_8B;
1596 }
1597
get_atomic_mode(struct mlx5_ib_dev * dev,enum ib_qp_type qp_type)1598 static int get_atomic_mode(struct mlx5_ib_dev *dev,
1599 enum ib_qp_type qp_type)
1600 {
1601 u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations);
1602 u8 atomic = MLX5_CAP_GEN(dev->mdev, atomic);
1603 int atomic_mode = -EOPNOTSUPP;
1604 int atomic_size_mask;
1605
1606 if (!atomic)
1607 return -EOPNOTSUPP;
1608
1609 if (qp_type == MLX5_IB_QPT_DCT)
1610 atomic_size_mask = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_dc);
1611 else
1612 atomic_size_mask = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp);
1613
1614 if ((atomic_operations & MLX5_ATOMIC_OPS_MASKED_CMP_SWAP) ||
1615 (atomic_operations & MLX5_ATOMIC_OPS_MASKED_FETCH_ADD))
1616 atomic_mode = atomic_size_to_mode(atomic_size_mask);
1617
1618 if (atomic_mode <= 0 &&
1619 (atomic_operations & MLX5_ATOMIC_OPS_CMP_SWAP &&
1620 atomic_operations & MLX5_ATOMIC_OPS_FETCH_ADD))
1621 atomic_mode = MLX5_ATOMIC_MODE_IB_COMP;
1622
1623 return atomic_mode;
1624 }
1625
create_qp_common(struct mlx5_ib_dev * dev,struct ib_pd * pd,struct ib_qp_init_attr * init_attr,struct ib_udata * udata,struct mlx5_ib_qp * qp)1626 static int create_qp_common(struct mlx5_ib_dev *dev, struct ib_pd *pd,
1627 struct ib_qp_init_attr *init_attr,
1628 struct ib_udata *udata, struct mlx5_ib_qp *qp)
1629 {
1630 struct mlx5_ib_resources *devr = &dev->devr;
1631 int inlen = MLX5_ST_SZ_BYTES(create_qp_in);
1632 struct mlx5_core_dev *mdev = dev->mdev;
1633 struct mlx5_ib_create_qp_resp resp;
1634 struct mlx5_ib_cq *send_cq;
1635 struct mlx5_ib_cq *recv_cq;
1636 unsigned long flags;
1637 u32 uidx = MLX5_IB_DEFAULT_UIDX;
1638 struct mlx5_ib_create_qp ucmd;
1639 struct mlx5_ib_qp_base *base;
1640 void *qpc;
1641 u32 *in;
1642 int err;
1643
1644 base = init_attr->qp_type == IB_QPT_RAW_PACKET ?
1645 &qp->raw_packet_qp.rq.base :
1646 &qp->trans_qp.base;
1647
1648 if (init_attr->qp_type != IB_QPT_RAW_PACKET)
1649 mlx5_ib_odp_create_qp(qp);
1650
1651 mutex_init(&qp->mutex);
1652 spin_lock_init(&qp->sq.lock);
1653 spin_lock_init(&qp->rq.lock);
1654
1655 if (init_attr->rwq_ind_tbl) {
1656 if (!udata)
1657 return -ENOSYS;
1658
1659 err = create_rss_raw_qp_tir(dev, qp, pd, init_attr, udata);
1660 return err;
1661 }
1662
1663 if (init_attr->create_flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK) {
1664 if (!MLX5_CAP_GEN(mdev, block_lb_mc)) {
1665 mlx5_ib_dbg(dev, "block multicast loopback isn't supported\n");
1666 return -EINVAL;
1667 } else {
1668 qp->flags |= MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK;
1669 }
1670 }
1671
1672 if (init_attr->create_flags &
1673 (IB_QP_CREATE_CROSS_CHANNEL |
1674 IB_QP_CREATE_MANAGED_SEND |
1675 IB_QP_CREATE_MANAGED_RECV)) {
1676 if (!MLX5_CAP_GEN(mdev, cd)) {
1677 mlx5_ib_dbg(dev, "cross-channel isn't supported\n");
1678 return -EINVAL;
1679 }
1680 if (init_attr->create_flags & IB_QP_CREATE_CROSS_CHANNEL)
1681 qp->flags |= MLX5_IB_QP_CROSS_CHANNEL;
1682 if (init_attr->create_flags & IB_QP_CREATE_MANAGED_SEND)
1683 qp->flags |= MLX5_IB_QP_MANAGED_SEND;
1684 if (init_attr->create_flags & IB_QP_CREATE_MANAGED_RECV)
1685 qp->flags |= MLX5_IB_QP_MANAGED_RECV;
1686 }
1687
1688 if (init_attr->qp_type == IB_QPT_UD &&
1689 (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO))
1690 if (!MLX5_CAP_GEN(mdev, ipoib_ipoib_offloads)) {
1691 mlx5_ib_dbg(dev, "ipoib UD lso qp isn't supported\n");
1692 return -EOPNOTSUPP;
1693 }
1694
1695 if (init_attr->create_flags & IB_QP_CREATE_SCATTER_FCS) {
1696 if (init_attr->qp_type != IB_QPT_RAW_PACKET) {
1697 mlx5_ib_dbg(dev, "Scatter FCS is supported only for Raw Packet QPs");
1698 return -EOPNOTSUPP;
1699 }
1700 if (!MLX5_CAP_GEN(dev->mdev, eth_net_offloads) ||
1701 !MLX5_CAP_ETH(dev->mdev, scatter_fcs)) {
1702 mlx5_ib_dbg(dev, "Scatter FCS isn't supported\n");
1703 return -EOPNOTSUPP;
1704 }
1705 qp->flags |= MLX5_IB_QP_CAP_SCATTER_FCS;
1706 }
1707
1708 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR)
1709 qp->sq_signal_bits = MLX5_WQE_CTRL_CQ_UPDATE;
1710
1711 if (init_attr->create_flags & IB_QP_CREATE_CVLAN_STRIPPING) {
1712 if (!(MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
1713 MLX5_CAP_ETH(dev->mdev, vlan_cap)) ||
1714 (init_attr->qp_type != IB_QPT_RAW_PACKET))
1715 return -EOPNOTSUPP;
1716 qp->flags |= MLX5_IB_QP_CVLAN_STRIPPING;
1717 }
1718
1719 if (pd && pd->uobject) {
1720 if (ib_copy_from_udata(&ucmd, udata, sizeof(ucmd))) {
1721 mlx5_ib_dbg(dev, "copy failed\n");
1722 return -EFAULT;
1723 }
1724
1725 err = get_qp_user_index(to_mucontext(pd->uobject->context),
1726 &ucmd, udata->inlen, &uidx);
1727 if (err)
1728 return err;
1729
1730 qp->wq_sig = !!(ucmd.flags & MLX5_QP_FLAG_SIGNATURE);
1731 qp->scat_cqe = !!(ucmd.flags & MLX5_QP_FLAG_SCATTER_CQE);
1732 if (ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS) {
1733 if (init_attr->qp_type != IB_QPT_RAW_PACKET ||
1734 !tunnel_offload_supported(mdev)) {
1735 mlx5_ib_dbg(dev, "Tunnel offload isn't supported\n");
1736 return -EOPNOTSUPP;
1737 }
1738 qp->tunnel_offload_en = true;
1739 }
1740 } else {
1741 qp->wq_sig = !!wq_signature;
1742 }
1743
1744 qp->has_rq = qp_has_rq(init_attr);
1745 err = set_rq_size(dev, &init_attr->cap, qp->has_rq,
1746 qp, (pd && pd->uobject) ? &ucmd : NULL);
1747 if (err) {
1748 mlx5_ib_dbg(dev, "err %d\n", err);
1749 return err;
1750 }
1751
1752 if (pd) {
1753 if (pd->uobject) {
1754 __u32 max_wqes =
1755 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
1756 mlx5_ib_dbg(dev, "requested sq_wqe_count (%d)\n", ucmd.sq_wqe_count);
1757 if (ucmd.rq_wqe_shift != qp->rq.wqe_shift ||
1758 ucmd.rq_wqe_count != qp->rq.wqe_cnt) {
1759 mlx5_ib_dbg(dev, "invalid rq params\n");
1760 return -EINVAL;
1761 }
1762 if (ucmd.sq_wqe_count > max_wqes) {
1763 mlx5_ib_dbg(dev, "requested sq_wqe_count (%d) > max allowed (%d)\n",
1764 ucmd.sq_wqe_count, max_wqes);
1765 return -EINVAL;
1766 }
1767 if (init_attr->create_flags &
1768 MLX5_IB_QP_CREATE_SQPN_QP1) {
1769 mlx5_ib_dbg(dev, "user-space is not allowed to create UD QPs spoofing as QP1\n");
1770 return -EINVAL;
1771 }
1772 err = create_user_qp(dev, pd, qp, udata, init_attr, &in,
1773 &resp, &inlen, base);
1774 if (err)
1775 mlx5_ib_dbg(dev, "err %d\n", err);
1776 } else {
1777 err = create_kernel_qp(dev, init_attr, qp, &in, &inlen,
1778 base);
1779 if (err)
1780 mlx5_ib_dbg(dev, "err %d\n", err);
1781 }
1782
1783 if (err)
1784 return err;
1785 } else {
1786 in = mlx5_vzalloc(inlen);
1787 if (!in)
1788 return -ENOMEM;
1789
1790 qp->create_type = MLX5_QP_EMPTY;
1791 }
1792
1793 if (is_sqp(init_attr->qp_type))
1794 qp->port = init_attr->port_num;
1795
1796 qpc = MLX5_ADDR_OF(create_qp_in, in, qpc);
1797
1798 MLX5_SET(qpc, qpc, st, to_mlx5_st(init_attr->qp_type));
1799 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED);
1800
1801 if (init_attr->qp_type != MLX5_IB_QPT_REG_UMR)
1802 MLX5_SET(qpc, qpc, pd, to_mpd(pd ? pd : devr->p0)->pdn);
1803 else
1804 MLX5_SET(qpc, qpc, latency_sensitive, 1);
1805
1806
1807 if (qp->wq_sig)
1808 MLX5_SET(qpc, qpc, wq_signature, 1);
1809
1810 if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK)
1811 MLX5_SET(qpc, qpc, block_lb_mc, 1);
1812
1813 if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL)
1814 MLX5_SET(qpc, qpc, cd_master, 1);
1815 if (qp->flags & MLX5_IB_QP_MANAGED_SEND)
1816 MLX5_SET(qpc, qpc, cd_slave_send, 1);
1817 if (qp->flags & MLX5_IB_QP_MANAGED_RECV)
1818 MLX5_SET(qpc, qpc, cd_slave_receive, 1);
1819
1820 if (qp->scat_cqe && is_connected(init_attr->qp_type)) {
1821 int rcqe_sz;
1822 int scqe_sz;
1823
1824 rcqe_sz = mlx5_ib_get_cqe_size(dev, init_attr->recv_cq);
1825 scqe_sz = mlx5_ib_get_cqe_size(dev, init_attr->send_cq);
1826
1827 if (rcqe_sz == 128)
1828 MLX5_SET(qpc, qpc, cs_res, MLX5_RES_SCAT_DATA64_CQE);
1829 else
1830 MLX5_SET(qpc, qpc, cs_res, MLX5_RES_SCAT_DATA32_CQE);
1831
1832 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR) {
1833 if (scqe_sz == 128)
1834 MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA64_CQE);
1835 else
1836 MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA32_CQE);
1837 }
1838 }
1839
1840 if (qp->rq.wqe_cnt) {
1841 MLX5_SET(qpc, qpc, log_rq_stride, qp->rq.wqe_shift - 4);
1842 MLX5_SET(qpc, qpc, log_rq_size, ilog2(qp->rq.wqe_cnt));
1843 }
1844
1845 if (init_attr->qp_type != IB_QPT_RAW_PACKET)
1846 MLX5_SET(qpc, qpc, ts_format, mlx5_get_qp_default_ts(dev->mdev));
1847
1848 MLX5_SET(qpc, qpc, rq_type, get_rx_type(qp, init_attr));
1849
1850 if (qp->sq.wqe_cnt)
1851 MLX5_SET(qpc, qpc, log_sq_size, ilog2(qp->sq.wqe_cnt));
1852 else
1853 MLX5_SET(qpc, qpc, no_sq, 1);
1854
1855 /* Set default resources */
1856 switch (init_attr->qp_type) {
1857 case IB_QPT_XRC_TGT:
1858 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn);
1859 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(devr->c0)->mcq.cqn);
1860 MLX5_SET(qpc, qpc, srqn_rmpn, to_msrq(devr->s0)->msrq.srqn);
1861 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(init_attr->xrcd)->xrcdn);
1862 break;
1863 case IB_QPT_XRC_INI:
1864 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn);
1865 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x1)->xrcdn);
1866 MLX5_SET(qpc, qpc, srqn_rmpn, to_msrq(devr->s0)->msrq.srqn);
1867 break;
1868 default:
1869 if (init_attr->srq) {
1870 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x0)->xrcdn);
1871 MLX5_SET(qpc, qpc, srqn_rmpn, to_msrq(init_attr->srq)->msrq.srqn);
1872 } else {
1873 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x1)->xrcdn);
1874 MLX5_SET(qpc, qpc, srqn_rmpn, to_msrq(devr->s1)->msrq.srqn);
1875 }
1876 }
1877
1878 if (init_attr->send_cq)
1879 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(init_attr->send_cq)->mcq.cqn);
1880
1881 if (init_attr->recv_cq)
1882 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(init_attr->recv_cq)->mcq.cqn);
1883
1884 MLX5_SET64(qpc, qpc, dbr_addr, qp->db.dma);
1885
1886 /* 0xffffff means we ask to work with cqe version 0 */
1887 if (MLX5_CAP_GEN(mdev, cqe_version) == MLX5_CQE_VERSION_V1)
1888 MLX5_SET(qpc, qpc, user_index, uidx);
1889
1890 /* we use IB_QP_CREATE_IPOIB_UD_LSO to indicates ipoib qp */
1891 if (init_attr->qp_type == IB_QPT_UD &&
1892 (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)) {
1893 MLX5_SET(qpc, qpc, ulp_stateless_offload_mode, 1);
1894 qp->flags |= MLX5_IB_QP_LSO;
1895 }
1896
1897 if (init_attr->qp_type == IB_QPT_RAW_PACKET) {
1898 qp->raw_packet_qp.sq.ubuffer.buf_addr = ucmd.sq_buf_addr;
1899 raw_packet_qp_copy_info(qp, &qp->raw_packet_qp);
1900 err = create_raw_packet_qp(dev, qp, in, pd);
1901 } else {
1902 err = mlx5_core_create_qp(dev->mdev, &base->mqp, in, inlen);
1903 }
1904
1905 if (err) {
1906 mlx5_ib_dbg(dev, "create qp failed\n");
1907 goto err_create;
1908 }
1909
1910 kvfree(in);
1911
1912 base->container_mibqp = qp;
1913 base->mqp.event = mlx5_ib_qp_event;
1914
1915 get_cqs(init_attr->qp_type, init_attr->send_cq, init_attr->recv_cq,
1916 &send_cq, &recv_cq);
1917 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
1918 mlx5_ib_lock_cqs(send_cq, recv_cq);
1919 /* Maintain device to QPs access, needed for further handling via reset
1920 * flow
1921 */
1922 list_add_tail(&qp->qps_list, &dev->qp_list);
1923 /* Maintain CQ to QPs access, needed for further handling via reset flow
1924 */
1925 if (send_cq)
1926 list_add_tail(&qp->cq_send_list, &send_cq->list_send_qp);
1927 if (recv_cq)
1928 list_add_tail(&qp->cq_recv_list, &recv_cq->list_recv_qp);
1929 mlx5_ib_unlock_cqs(send_cq, recv_cq);
1930 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
1931
1932 return 0;
1933
1934 err_create:
1935 if (qp->create_type == MLX5_QP_USER)
1936 destroy_qp_user(dev, pd, qp, base, udata);
1937 else if (qp->create_type == MLX5_QP_KERNEL)
1938 destroy_qp_kernel(dev, qp);
1939
1940 kvfree(in);
1941 return err;
1942 }
1943
mlx5_ib_lock_cqs(struct mlx5_ib_cq * send_cq,struct mlx5_ib_cq * recv_cq)1944 static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq)
1945 __acquires(&send_cq->lock) __acquires(&recv_cq->lock)
1946 {
1947 if (send_cq) {
1948 if (recv_cq) {
1949 if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
1950 spin_lock(&send_cq->lock);
1951 spin_lock_nested(&recv_cq->lock,
1952 SINGLE_DEPTH_NESTING);
1953 } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) {
1954 spin_lock(&send_cq->lock);
1955 __acquire(&recv_cq->lock);
1956 } else {
1957 spin_lock(&recv_cq->lock);
1958 spin_lock_nested(&send_cq->lock,
1959 SINGLE_DEPTH_NESTING);
1960 }
1961 } else {
1962 spin_lock(&send_cq->lock);
1963 __acquire(&recv_cq->lock);
1964 }
1965 } else if (recv_cq) {
1966 spin_lock(&recv_cq->lock);
1967 __acquire(&send_cq->lock);
1968 } else {
1969 __acquire(&send_cq->lock);
1970 __acquire(&recv_cq->lock);
1971 }
1972 }
1973
mlx5_ib_unlock_cqs(struct mlx5_ib_cq * send_cq,struct mlx5_ib_cq * recv_cq)1974 static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq)
1975 __releases(&send_cq->lock) __releases(&recv_cq->lock)
1976 {
1977 if (send_cq) {
1978 if (recv_cq) {
1979 if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
1980 spin_unlock(&recv_cq->lock);
1981 spin_unlock(&send_cq->lock);
1982 } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) {
1983 __release(&recv_cq->lock);
1984 spin_unlock(&send_cq->lock);
1985 } else {
1986 spin_unlock(&send_cq->lock);
1987 spin_unlock(&recv_cq->lock);
1988 }
1989 } else {
1990 __release(&recv_cq->lock);
1991 spin_unlock(&send_cq->lock);
1992 }
1993 } else if (recv_cq) {
1994 __release(&send_cq->lock);
1995 spin_unlock(&recv_cq->lock);
1996 } else {
1997 __release(&recv_cq->lock);
1998 __release(&send_cq->lock);
1999 }
2000 }
2001
get_pd(struct mlx5_ib_qp * qp)2002 static struct mlx5_ib_pd *get_pd(struct mlx5_ib_qp *qp)
2003 {
2004 return to_mpd(qp->ibqp.pd);
2005 }
2006
get_cqs(enum ib_qp_type qp_type,struct ib_cq * ib_send_cq,struct ib_cq * ib_recv_cq,struct mlx5_ib_cq ** send_cq,struct mlx5_ib_cq ** recv_cq)2007 static void get_cqs(enum ib_qp_type qp_type,
2008 struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq,
2009 struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq)
2010 {
2011 switch (qp_type) {
2012 case IB_QPT_XRC_TGT:
2013 *send_cq = NULL;
2014 *recv_cq = NULL;
2015 break;
2016 case MLX5_IB_QPT_REG_UMR:
2017 case IB_QPT_XRC_INI:
2018 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL;
2019 *recv_cq = NULL;
2020 break;
2021
2022 case IB_QPT_SMI:
2023 case MLX5_IB_QPT_HW_GSI:
2024 case IB_QPT_RC:
2025 case IB_QPT_UC:
2026 case IB_QPT_UD:
2027 case IB_QPT_RAW_IPV6:
2028 case IB_QPT_RAW_ETHERTYPE:
2029 case IB_QPT_RAW_PACKET:
2030 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL;
2031 *recv_cq = ib_recv_cq ? to_mcq(ib_recv_cq) : NULL;
2032 break;
2033
2034 case IB_QPT_MAX:
2035 default:
2036 *send_cq = NULL;
2037 *recv_cq = NULL;
2038 break;
2039 }
2040 }
2041
2042 static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
2043 const struct mlx5_modify_raw_qp_param *raw_qp_param,
2044 u8 lag_tx_affinity);
2045
destroy_qp_common(struct mlx5_ib_dev * dev,struct mlx5_ib_qp * qp,struct ib_udata * udata)2046 static void destroy_qp_common(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
2047 struct ib_udata *udata)
2048 {
2049 struct mlx5_ib_cq *send_cq, *recv_cq;
2050 struct mlx5_ib_qp_base *base = &qp->trans_qp.base;
2051 unsigned long flags;
2052 int err;
2053
2054 if (qp->ibqp.rwq_ind_tbl) {
2055 destroy_rss_raw_qp_tir(dev, qp);
2056 return;
2057 }
2058
2059 base = qp->ibqp.qp_type == IB_QPT_RAW_PACKET ?
2060 &qp->raw_packet_qp.rq.base :
2061 &qp->trans_qp.base;
2062
2063 if (qp->state != IB_QPS_RESET) {
2064 if (qp->ibqp.qp_type != IB_QPT_RAW_PACKET) {
2065 mlx5_ib_qp_disable_pagefaults(qp);
2066 err = mlx5_core_qp_modify(dev->mdev,
2067 MLX5_CMD_OP_2RST_QP, 0,
2068 NULL, &base->mqp);
2069 } else {
2070 struct mlx5_modify_raw_qp_param raw_qp_param = {
2071 .operation = MLX5_CMD_OP_2RST_QP
2072 };
2073
2074 err = modify_raw_packet_qp(dev, qp, &raw_qp_param, 0);
2075 }
2076 if (err)
2077 mlx5_ib_warn(dev, "mlx5_ib: modify QP 0x%06x to RESET failed\n",
2078 base->mqp.qpn);
2079 }
2080
2081 get_cqs(qp->ibqp.qp_type, qp->ibqp.send_cq, qp->ibqp.recv_cq,
2082 &send_cq, &recv_cq);
2083
2084 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
2085 mlx5_ib_lock_cqs(send_cq, recv_cq);
2086 /* del from lists under both locks above to protect reset flow paths */
2087 list_del(&qp->qps_list);
2088 if (send_cq)
2089 list_del(&qp->cq_send_list);
2090
2091 if (recv_cq)
2092 list_del(&qp->cq_recv_list);
2093
2094 if (qp->create_type == MLX5_QP_KERNEL) {
2095 __mlx5_ib_cq_clean(recv_cq, base->mqp.qpn,
2096 qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL);
2097 if (send_cq != recv_cq)
2098 __mlx5_ib_cq_clean(send_cq, base->mqp.qpn,
2099 NULL);
2100 }
2101 mlx5_ib_unlock_cqs(send_cq, recv_cq);
2102 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
2103
2104 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET) {
2105 destroy_raw_packet_qp(dev, qp);
2106 } else {
2107 err = mlx5_core_destroy_qp(dev->mdev, &base->mqp);
2108 if (err)
2109 mlx5_ib_warn(dev, "failed to destroy QP 0x%x\n",
2110 base->mqp.qpn);
2111 }
2112
2113 if (qp->create_type == MLX5_QP_KERNEL)
2114 destroy_qp_kernel(dev, qp);
2115 else if (qp->create_type == MLX5_QP_USER)
2116 destroy_qp_user(dev, &get_pd(qp)->ibpd, qp, base, udata);
2117 }
2118
ib_qp_type_str(enum ib_qp_type type)2119 static const char *ib_qp_type_str(enum ib_qp_type type)
2120 {
2121 switch (type) {
2122 case IB_QPT_SMI:
2123 return "IB_QPT_SMI";
2124 case IB_QPT_GSI:
2125 return "IB_QPT_GSI";
2126 case IB_QPT_RC:
2127 return "IB_QPT_RC";
2128 case IB_QPT_UC:
2129 return "IB_QPT_UC";
2130 case IB_QPT_UD:
2131 return "IB_QPT_UD";
2132 case IB_QPT_RAW_IPV6:
2133 return "IB_QPT_RAW_IPV6";
2134 case IB_QPT_RAW_ETHERTYPE:
2135 return "IB_QPT_RAW_ETHERTYPE";
2136 case IB_QPT_XRC_INI:
2137 return "IB_QPT_XRC_INI";
2138 case IB_QPT_XRC_TGT:
2139 return "IB_QPT_XRC_TGT";
2140 case IB_QPT_RAW_PACKET:
2141 return "IB_QPT_RAW_PACKET";
2142 case MLX5_IB_QPT_REG_UMR:
2143 return "MLX5_IB_QPT_REG_UMR";
2144 case IB_QPT_MAX:
2145 default:
2146 return "Invalid QP type";
2147 }
2148 }
2149
mlx5_ib_create_qp(struct ib_pd * pd,struct ib_qp_init_attr * init_attr,struct ib_udata * udata)2150 struct ib_qp *mlx5_ib_create_qp(struct ib_pd *pd,
2151 struct ib_qp_init_attr *init_attr,
2152 struct ib_udata *udata)
2153 {
2154 struct mlx5_ib_dev *dev;
2155 struct mlx5_ib_qp *qp;
2156 u16 xrcdn = 0;
2157 int err;
2158
2159 if (pd) {
2160 dev = to_mdev(pd->device);
2161
2162 if (init_attr->qp_type == IB_QPT_RAW_PACKET) {
2163 if (!pd->uobject) {
2164 mlx5_ib_dbg(dev, "Raw Packet QP is not supported for kernel consumers\n");
2165 return ERR_PTR(-EINVAL);
2166 } else if (!to_mucontext(pd->uobject->context)->cqe_version) {
2167 mlx5_ib_dbg(dev, "Raw Packet QP is only supported for CQE version > 0\n");
2168 return ERR_PTR(-EINVAL);
2169 }
2170 }
2171 } else {
2172 /* being cautious here */
2173 if (init_attr->qp_type != IB_QPT_XRC_TGT &&
2174 init_attr->qp_type != MLX5_IB_QPT_REG_UMR) {
2175 pr_warn("%s: no PD for transport %s\n", __func__,
2176 ib_qp_type_str(init_attr->qp_type));
2177 return ERR_PTR(-EINVAL);
2178 }
2179 dev = to_mdev(to_mxrcd(init_attr->xrcd)->ibxrcd.device);
2180 }
2181
2182 switch (init_attr->qp_type) {
2183 case IB_QPT_XRC_TGT:
2184 case IB_QPT_XRC_INI:
2185 if (!MLX5_CAP_GEN(dev->mdev, xrc)) {
2186 mlx5_ib_dbg(dev, "XRC not supported\n");
2187 return ERR_PTR(-ENOSYS);
2188 }
2189 init_attr->recv_cq = NULL;
2190 if (init_attr->qp_type == IB_QPT_XRC_TGT) {
2191 xrcdn = to_mxrcd(init_attr->xrcd)->xrcdn;
2192 init_attr->send_cq = NULL;
2193 }
2194
2195 /* fall through */
2196 case IB_QPT_RAW_PACKET:
2197 case IB_QPT_RC:
2198 case IB_QPT_UC:
2199 case IB_QPT_UD:
2200 case IB_QPT_SMI:
2201 case MLX5_IB_QPT_HW_GSI:
2202 case MLX5_IB_QPT_REG_UMR:
2203 qp = kzalloc(sizeof(*qp), GFP_KERNEL);
2204 if (!qp)
2205 return ERR_PTR(-ENOMEM);
2206
2207 err = create_qp_common(dev, pd, init_attr, udata, qp);
2208 if (err) {
2209 mlx5_ib_dbg(dev, "create_qp_common failed\n");
2210 kfree(qp);
2211 return ERR_PTR(err);
2212 }
2213
2214 if (is_qp0(init_attr->qp_type))
2215 qp->ibqp.qp_num = 0;
2216 else if (is_qp1(init_attr->qp_type))
2217 qp->ibqp.qp_num = 1;
2218 else
2219 qp->ibqp.qp_num = qp->trans_qp.base.mqp.qpn;
2220
2221 mlx5_ib_dbg(dev, "ib qpnum 0x%x, mlx qpn 0x%x, rcqn 0x%x, scqn 0x%x\n",
2222 qp->ibqp.qp_num, qp->trans_qp.base.mqp.qpn,
2223 init_attr->recv_cq ? to_mcq(init_attr->recv_cq)->mcq.cqn : -1,
2224 init_attr->send_cq ? to_mcq(init_attr->send_cq)->mcq.cqn : -1);
2225
2226 qp->trans_qp.xrcdn = xrcdn;
2227
2228 break;
2229
2230 case IB_QPT_GSI:
2231 return mlx5_ib_gsi_create_qp(pd, init_attr);
2232
2233 case IB_QPT_RAW_IPV6:
2234 case IB_QPT_RAW_ETHERTYPE:
2235 case IB_QPT_MAX:
2236 default:
2237 mlx5_ib_dbg(dev, "unsupported qp type %d\n",
2238 init_attr->qp_type);
2239 /* Don't support raw QPs */
2240 return ERR_PTR(-EINVAL);
2241 }
2242
2243 return &qp->ibqp;
2244 }
2245
mlx5_ib_destroy_qp(struct ib_qp * qp,struct ib_udata * udata)2246 int mlx5_ib_destroy_qp(struct ib_qp *qp, struct ib_udata *udata)
2247 {
2248 struct mlx5_ib_dev *dev = to_mdev(qp->device);
2249 struct mlx5_ib_qp *mqp = to_mqp(qp);
2250
2251 if (unlikely(qp->qp_type == IB_QPT_GSI))
2252 return mlx5_ib_gsi_destroy_qp(qp);
2253
2254 destroy_qp_common(dev, mqp, udata);
2255
2256 kfree(mqp);
2257
2258 return 0;
2259 }
2260
to_mlx5_access_flags(struct mlx5_ib_qp * qp,const struct ib_qp_attr * attr,int attr_mask,__be32 * hw_access_flags_be)2261 static int to_mlx5_access_flags(struct mlx5_ib_qp *qp,
2262 const struct ib_qp_attr *attr,
2263 int attr_mask, __be32 *hw_access_flags_be)
2264 {
2265 u8 dest_rd_atomic;
2266 u32 access_flags, hw_access_flags = 0;
2267
2268 struct mlx5_ib_dev *dev = to_mdev(qp->ibqp.device);
2269
2270 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
2271 dest_rd_atomic = attr->max_dest_rd_atomic;
2272 else
2273 dest_rd_atomic = qp->trans_qp.resp_depth;
2274
2275 if (attr_mask & IB_QP_ACCESS_FLAGS)
2276 access_flags = attr->qp_access_flags;
2277 else
2278 access_flags = qp->trans_qp.atomic_rd_en;
2279
2280 if (!dest_rd_atomic)
2281 access_flags &= IB_ACCESS_REMOTE_WRITE;
2282
2283 if (access_flags & IB_ACCESS_REMOTE_READ)
2284 hw_access_flags |= MLX5_QP_BIT_RRE;
2285 if (access_flags & IB_ACCESS_REMOTE_ATOMIC) {
2286 int atomic_mode;
2287
2288 atomic_mode = get_atomic_mode(dev, qp->ibqp.qp_type);
2289 if (atomic_mode < 0)
2290 return -EOPNOTSUPP;
2291
2292 hw_access_flags |= MLX5_QP_BIT_RAE;
2293 hw_access_flags |= atomic_mode << MLX5_ATOMIC_MODE_OFF;
2294 }
2295
2296 if (access_flags & IB_ACCESS_REMOTE_WRITE)
2297 hw_access_flags |= MLX5_QP_BIT_RWE;
2298
2299 *hw_access_flags_be = cpu_to_be32(hw_access_flags);
2300
2301 return 0;
2302 }
2303
2304 enum {
2305 MLX5_PATH_FLAG_FL = 1 << 0,
2306 MLX5_PATH_FLAG_FREE_AR = 1 << 1,
2307 MLX5_PATH_FLAG_COUNTER = 1 << 2,
2308 };
2309
ib_rate_to_mlx5(struct mlx5_ib_dev * dev,u8 rate)2310 static int ib_rate_to_mlx5(struct mlx5_ib_dev *dev, u8 rate)
2311 {
2312 if (rate == IB_RATE_PORT_CURRENT) {
2313 return 0;
2314 } else if (rate < IB_RATE_2_5_GBPS || rate > IB_RATE_600_GBPS) {
2315 return -EINVAL;
2316 } else {
2317 while (rate != IB_RATE_2_5_GBPS &&
2318 !(1 << (rate + MLX5_STAT_RATE_OFFSET) &
2319 MLX5_CAP_GEN(dev->mdev, stat_rate_support)))
2320 --rate;
2321 }
2322
2323 return rate + MLX5_STAT_RATE_OFFSET;
2324 }
2325
modify_raw_packet_eth_prio(struct mlx5_core_dev * dev,struct mlx5_ib_sq * sq,u8 sl,struct ib_pd * pd)2326 static int modify_raw_packet_eth_prio(struct mlx5_core_dev *dev,
2327 struct mlx5_ib_sq *sq, u8 sl,
2328 struct ib_pd *pd)
2329 {
2330 void *in;
2331 void *tisc;
2332 int inlen;
2333 int err;
2334
2335 inlen = MLX5_ST_SZ_BYTES(modify_tis_in);
2336 in = mlx5_vzalloc(inlen);
2337 if (!in)
2338 return -ENOMEM;
2339
2340 MLX5_SET(modify_tis_in, in, bitmask.prio, 1);
2341 MLX5_SET(modify_tis_in, in, uid, to_mpd(pd)->uid);
2342
2343 tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx);
2344 MLX5_SET(tisc, tisc, prio, ((sl & 0x7) << 1));
2345
2346 err = mlx5_core_modify_tis(dev, sq->tisn, in, inlen);
2347
2348 kvfree(in);
2349
2350 return err;
2351 }
2352
modify_raw_packet_tx_affinity(struct mlx5_core_dev * dev,struct mlx5_ib_sq * sq,u8 tx_affinity,struct ib_pd * pd)2353 static int modify_raw_packet_tx_affinity(struct mlx5_core_dev *dev,
2354 struct mlx5_ib_sq *sq, u8 tx_affinity,
2355 struct ib_pd *pd)
2356 {
2357 void *in;
2358 void *tisc;
2359 int inlen;
2360 int err;
2361
2362 inlen = MLX5_ST_SZ_BYTES(modify_tis_in);
2363 in = mlx5_vzalloc(inlen);
2364 if (!in)
2365 return -ENOMEM;
2366
2367 MLX5_SET(modify_tis_in, in, bitmask.lag_tx_port_affinity, 1);
2368 MLX5_SET(modify_tis_in, in, uid, to_mpd(pd)->uid);
2369
2370 tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx);
2371 MLX5_SET(tisc, tisc, lag_tx_port_affinity, tx_affinity);
2372
2373 err = mlx5_core_modify_tis(dev, sq->tisn, in, inlen);
2374
2375 kvfree(in);
2376
2377 return err;
2378 }
2379
mlx5_set_path(struct mlx5_ib_dev * dev,struct mlx5_ib_qp * qp,const struct rdma_ah_attr * ah,struct mlx5_qp_path * path,u8 port,int attr_mask,u32 path_flags,const struct ib_qp_attr * attr,bool alt)2380 static int mlx5_set_path(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
2381 const struct rdma_ah_attr *ah,
2382 struct mlx5_qp_path *path, u8 port, int attr_mask,
2383 u32 path_flags, const struct ib_qp_attr *attr,
2384 bool alt)
2385 {
2386 const struct ib_global_route *grh = rdma_ah_read_grh(ah);
2387 int err;
2388 enum ib_gid_type gid_type;
2389 u8 ah_flags = rdma_ah_get_ah_flags(ah);
2390 u8 sl = rdma_ah_get_sl(ah);
2391
2392 if (attr_mask & IB_QP_PKEY_INDEX)
2393 path->pkey_index = cpu_to_be16(alt ? attr->alt_pkey_index :
2394 attr->pkey_index);
2395
2396 if (ah_flags & IB_AH_GRH) {
2397 if (grh->sgid_index >=
2398 dev->mdev->port_caps[port - 1].gid_table_len) {
2399 pr_err("sgid_index (%u) too large. max is %d\n",
2400 grh->sgid_index,
2401 dev->mdev->port_caps[port - 1].gid_table_len);
2402 return -EINVAL;
2403 }
2404 }
2405
2406 if (ah->type == RDMA_AH_ATTR_TYPE_ROCE) {
2407 if (!(ah_flags & IB_AH_GRH))
2408 return -EINVAL;
2409
2410 memcpy(path->rmac, ah->roce.dmac, sizeof(ah->roce.dmac));
2411 path->udp_sport =
2412 mlx5_get_roce_udp_sport(dev, ah->grh.sgid_attr);
2413 path->dci_cfi_prio_sl = (sl & 0x7) << 4;
2414 gid_type = ah->grh.sgid_attr->gid_type;
2415 if (gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP)
2416 path->ecn_dscp = (grh->traffic_class >> 2) & 0x3f;
2417 } else {
2418 path->fl_free_ar = (path_flags & MLX5_PATH_FLAG_FL) ? 0x80 : 0;
2419 path->fl_free_ar |=
2420 (path_flags & MLX5_PATH_FLAG_FREE_AR) ? 0x40 : 0;
2421 path->rlid = cpu_to_be16(rdma_ah_get_dlid(ah));
2422 path->grh_mlid = rdma_ah_get_path_bits(ah) & 0x7f;
2423 if (ah_flags & IB_AH_GRH)
2424 path->grh_mlid |= 1 << 7;
2425 path->dci_cfi_prio_sl = sl & 0xf;
2426 }
2427
2428 if (ah_flags & IB_AH_GRH) {
2429 path->mgid_index = grh->sgid_index;
2430 path->hop_limit = grh->hop_limit;
2431 path->tclass_flowlabel =
2432 cpu_to_be32((grh->traffic_class << 20) |
2433 (grh->flow_label));
2434 memcpy(path->rgid, grh->dgid.raw, 16);
2435 }
2436
2437 err = ib_rate_to_mlx5(dev, rdma_ah_get_static_rate(ah));
2438 if (err < 0)
2439 return err;
2440 path->static_rate = err;
2441 path->port = port;
2442
2443 if (attr_mask & IB_QP_TIMEOUT)
2444 path->ackto_lt = (alt ? attr->alt_timeout : attr->timeout) << 3;
2445
2446 if ((qp->ibqp.qp_type == IB_QPT_RAW_PACKET) && qp->sq.wqe_cnt)
2447 return modify_raw_packet_eth_prio(dev->mdev,
2448 &qp->raw_packet_qp.sq,
2449 sl & 0xf, qp->ibqp.pd);
2450
2451 return 0;
2452 }
2453
2454 static enum mlx5_qp_optpar opt_mask[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE][MLX5_QP_ST_MAX] = {
2455 [MLX5_QP_STATE_INIT] = {
2456 [MLX5_QP_STATE_INIT] = {
2457 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE |
2458 MLX5_QP_OPTPAR_RAE |
2459 MLX5_QP_OPTPAR_RWE |
2460 MLX5_QP_OPTPAR_PKEY_INDEX |
2461 MLX5_QP_OPTPAR_PRI_PORT,
2462 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE |
2463 MLX5_QP_OPTPAR_PKEY_INDEX |
2464 MLX5_QP_OPTPAR_PRI_PORT,
2465 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX |
2466 MLX5_QP_OPTPAR_Q_KEY |
2467 MLX5_QP_OPTPAR_PRI_PORT,
2468 },
2469 [MLX5_QP_STATE_RTR] = {
2470 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
2471 MLX5_QP_OPTPAR_RRE |
2472 MLX5_QP_OPTPAR_RAE |
2473 MLX5_QP_OPTPAR_RWE |
2474 MLX5_QP_OPTPAR_PKEY_INDEX,
2475 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
2476 MLX5_QP_OPTPAR_RWE |
2477 MLX5_QP_OPTPAR_PKEY_INDEX,
2478 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX |
2479 MLX5_QP_OPTPAR_Q_KEY,
2480 [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_PKEY_INDEX |
2481 MLX5_QP_OPTPAR_Q_KEY,
2482 [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
2483 MLX5_QP_OPTPAR_RRE |
2484 MLX5_QP_OPTPAR_RAE |
2485 MLX5_QP_OPTPAR_RWE |
2486 MLX5_QP_OPTPAR_PKEY_INDEX,
2487 },
2488 },
2489 [MLX5_QP_STATE_RTR] = {
2490 [MLX5_QP_STATE_RTS] = {
2491 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
2492 MLX5_QP_OPTPAR_RRE |
2493 MLX5_QP_OPTPAR_RAE |
2494 MLX5_QP_OPTPAR_RWE |
2495 MLX5_QP_OPTPAR_PM_STATE |
2496 MLX5_QP_OPTPAR_RNR_TIMEOUT,
2497 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
2498 MLX5_QP_OPTPAR_RWE |
2499 MLX5_QP_OPTPAR_PM_STATE,
2500 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY,
2501 },
2502 },
2503 [MLX5_QP_STATE_RTS] = {
2504 [MLX5_QP_STATE_RTS] = {
2505 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE |
2506 MLX5_QP_OPTPAR_RAE |
2507 MLX5_QP_OPTPAR_RWE |
2508 MLX5_QP_OPTPAR_RNR_TIMEOUT |
2509 MLX5_QP_OPTPAR_PM_STATE |
2510 MLX5_QP_OPTPAR_ALT_ADDR_PATH,
2511 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE |
2512 MLX5_QP_OPTPAR_PM_STATE |
2513 MLX5_QP_OPTPAR_ALT_ADDR_PATH,
2514 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY |
2515 MLX5_QP_OPTPAR_SRQN |
2516 MLX5_QP_OPTPAR_CQN_RCV,
2517 },
2518 },
2519 [MLX5_QP_STATE_SQER] = {
2520 [MLX5_QP_STATE_RTS] = {
2521 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY,
2522 [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_Q_KEY,
2523 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE,
2524 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RNR_TIMEOUT |
2525 MLX5_QP_OPTPAR_RWE |
2526 MLX5_QP_OPTPAR_RAE |
2527 MLX5_QP_OPTPAR_RRE,
2528 },
2529 },
2530 };
2531
ib_nr_to_mlx5_nr(int ib_mask)2532 static int ib_nr_to_mlx5_nr(int ib_mask)
2533 {
2534 switch (ib_mask) {
2535 case IB_QP_STATE:
2536 return 0;
2537 case IB_QP_CUR_STATE:
2538 return 0;
2539 case IB_QP_EN_SQD_ASYNC_NOTIFY:
2540 return 0;
2541 case IB_QP_ACCESS_FLAGS:
2542 return MLX5_QP_OPTPAR_RWE | MLX5_QP_OPTPAR_RRE |
2543 MLX5_QP_OPTPAR_RAE;
2544 case IB_QP_PKEY_INDEX:
2545 return MLX5_QP_OPTPAR_PKEY_INDEX;
2546 case IB_QP_PORT:
2547 return MLX5_QP_OPTPAR_PRI_PORT;
2548 case IB_QP_QKEY:
2549 return MLX5_QP_OPTPAR_Q_KEY;
2550 case IB_QP_AV:
2551 return MLX5_QP_OPTPAR_PRIMARY_ADDR_PATH |
2552 MLX5_QP_OPTPAR_PRI_PORT;
2553 case IB_QP_PATH_MTU:
2554 return 0;
2555 case IB_QP_TIMEOUT:
2556 return MLX5_QP_OPTPAR_ACK_TIMEOUT;
2557 case IB_QP_RETRY_CNT:
2558 return MLX5_QP_OPTPAR_RETRY_COUNT;
2559 case IB_QP_RNR_RETRY:
2560 return MLX5_QP_OPTPAR_RNR_RETRY;
2561 case IB_QP_RQ_PSN:
2562 return 0;
2563 case IB_QP_MAX_QP_RD_ATOMIC:
2564 return MLX5_QP_OPTPAR_SRA_MAX;
2565 case IB_QP_ALT_PATH:
2566 return MLX5_QP_OPTPAR_ALT_ADDR_PATH;
2567 case IB_QP_MIN_RNR_TIMER:
2568 return MLX5_QP_OPTPAR_RNR_TIMEOUT;
2569 case IB_QP_SQ_PSN:
2570 return 0;
2571 case IB_QP_MAX_DEST_RD_ATOMIC:
2572 return MLX5_QP_OPTPAR_RRA_MAX | MLX5_QP_OPTPAR_RWE |
2573 MLX5_QP_OPTPAR_RRE | MLX5_QP_OPTPAR_RAE;
2574 case IB_QP_PATH_MIG_STATE:
2575 return MLX5_QP_OPTPAR_PM_STATE;
2576 case IB_QP_CAP:
2577 return 0;
2578 case IB_QP_DEST_QPN:
2579 return 0;
2580 }
2581 return 0;
2582 }
2583
ib_mask_to_mlx5_opt(int ib_mask)2584 static int ib_mask_to_mlx5_opt(int ib_mask)
2585 {
2586 int result = 0;
2587 int i;
2588
2589 for (i = 0; i < 8 * sizeof(int); i++) {
2590 if ((1 << i) & ib_mask)
2591 result |= ib_nr_to_mlx5_nr(1 << i);
2592 }
2593
2594 return result;
2595 }
2596
modify_raw_packet_qp_rq(struct mlx5_ib_dev * dev,struct mlx5_ib_rq * rq,int new_state,const struct mlx5_modify_raw_qp_param * raw_qp_param,struct ib_pd * pd)2597 static int modify_raw_packet_qp_rq(
2598 struct mlx5_ib_dev *dev, struct mlx5_ib_rq *rq, int new_state,
2599 const struct mlx5_modify_raw_qp_param *raw_qp_param, struct ib_pd *pd)
2600 {
2601 void *in;
2602 void *rqc;
2603 int inlen;
2604 int err;
2605
2606 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
2607 in = mlx5_vzalloc(inlen);
2608 if (!in)
2609 return -ENOMEM;
2610
2611 MLX5_SET(modify_rq_in, in, rqn, rq->base.mqp.qpn);
2612 MLX5_SET(modify_rq_in, in, rq_state, rq->state);
2613 MLX5_SET(modify_rq_in, in, uid, to_mpd(pd)->uid);
2614
2615 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
2616 MLX5_SET(rqc, rqc, state, new_state);
2617
2618 if (raw_qp_param->set_mask & MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID) {
2619 if (MLX5_CAP_GEN(dev->mdev, modify_rq_counters_set_id)) {
2620 MLX5_SET64(modify_rq_in, in, modify_bitmask,
2621 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_MODIFY_RQ_COUNTER_SET_ID);
2622 MLX5_SET(rqc, rqc, counter_set_id, raw_qp_param->rq_q_ctr_id);
2623 } else
2624 pr_info_once("%s: RAW PACKET QP counters are not supported on current FW\n",
2625 dev->ib_dev.name);
2626 }
2627
2628 err = mlx5_core_modify_rq(dev->mdev, in, inlen);
2629 if (err)
2630 goto out;
2631
2632 rq->state = new_state;
2633
2634 out:
2635 kvfree(in);
2636 return err;
2637 }
2638
modify_raw_packet_qp_sq(struct mlx5_core_dev * dev,struct mlx5_ib_sq * sq,int new_state,struct ib_pd * pd)2639 static int modify_raw_packet_qp_sq(struct mlx5_core_dev *dev,
2640 struct mlx5_ib_sq *sq, int new_state,
2641 struct ib_pd *pd)
2642 {
2643 void *in;
2644 void *sqc;
2645 int inlen;
2646 int err;
2647
2648 inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
2649 in = mlx5_vzalloc(inlen);
2650 if (!in)
2651 return -ENOMEM;
2652
2653 MLX5_SET(modify_sq_in, in, sqn, sq->base.mqp.qpn);
2654 MLX5_SET(modify_sq_in, in, uid, to_mpd(pd)->uid);
2655 MLX5_SET(modify_sq_in, in, sq_state, sq->state);
2656
2657 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
2658 MLX5_SET(sqc, sqc, state, new_state);
2659
2660 err = mlx5_core_modify_sq(dev, in, inlen);
2661 if (err)
2662 goto out;
2663
2664 sq->state = new_state;
2665
2666 out:
2667 kvfree(in);
2668 return err;
2669 }
2670
modify_raw_packet_qp(struct mlx5_ib_dev * dev,struct mlx5_ib_qp * qp,const struct mlx5_modify_raw_qp_param * raw_qp_param,u8 tx_affinity)2671 static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
2672 const struct mlx5_modify_raw_qp_param *raw_qp_param,
2673 u8 tx_affinity)
2674 {
2675 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
2676 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
2677 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
2678 int modify_rq = !!qp->rq.wqe_cnt;
2679 int modify_sq = !!qp->sq.wqe_cnt;
2680 int rq_state;
2681 int sq_state;
2682 int err;
2683
2684 switch (raw_qp_param->operation) {
2685 case MLX5_CMD_OP_RST2INIT_QP:
2686 rq_state = MLX5_RQC_STATE_RDY;
2687 sq_state = MLX5_SQC_STATE_RDY;
2688 break;
2689 case MLX5_CMD_OP_2ERR_QP:
2690 rq_state = MLX5_RQC_STATE_ERR;
2691 sq_state = MLX5_SQC_STATE_ERR;
2692 break;
2693 case MLX5_CMD_OP_2RST_QP:
2694 rq_state = MLX5_RQC_STATE_RST;
2695 sq_state = MLX5_SQC_STATE_RST;
2696 break;
2697 case MLX5_CMD_OP_RTR2RTS_QP:
2698 case MLX5_CMD_OP_RTS2RTS_QP:
2699 return raw_qp_param->set_mask ? -EINVAL : 0;
2700 case MLX5_CMD_OP_INIT2INIT_QP:
2701 case MLX5_CMD_OP_INIT2RTR_QP:
2702 if (raw_qp_param->set_mask)
2703 return -EINVAL;
2704 else
2705 return 0;
2706 default:
2707 WARN_ON(1);
2708 return -EINVAL;
2709 }
2710
2711 if (modify_rq) {
2712 err = modify_raw_packet_qp_rq(dev, rq, rq_state, raw_qp_param,
2713 qp->ibqp.pd);
2714 if (err)
2715 return err;
2716 }
2717
2718 if (modify_sq) {
2719 if (tx_affinity) {
2720 err = modify_raw_packet_tx_affinity(dev->mdev, sq,
2721 tx_affinity,
2722 qp->ibqp.pd);
2723 if (err)
2724 return err;
2725 }
2726
2727 return modify_raw_packet_qp_sq(dev->mdev, sq, sq_state, qp->ibqp.pd);
2728 }
2729
2730 return 0;
2731 }
2732
__mlx5_ib_modify_qp(struct ib_qp * ibqp,const struct ib_qp_attr * attr,int attr_mask,enum ib_qp_state cur_state,enum ib_qp_state new_state)2733 static int __mlx5_ib_modify_qp(struct ib_qp *ibqp,
2734 const struct ib_qp_attr *attr, int attr_mask,
2735 enum ib_qp_state cur_state, enum ib_qp_state new_state)
2736 {
2737 static const u16 optab[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE] = {
2738 [MLX5_QP_STATE_RST] = {
2739 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2740 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2741 [MLX5_QP_STATE_INIT] = MLX5_CMD_OP_RST2INIT_QP,
2742 },
2743 [MLX5_QP_STATE_INIT] = {
2744 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2745 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2746 [MLX5_QP_STATE_INIT] = MLX5_CMD_OP_INIT2INIT_QP,
2747 [MLX5_QP_STATE_RTR] = MLX5_CMD_OP_INIT2RTR_QP,
2748 },
2749 [MLX5_QP_STATE_RTR] = {
2750 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2751 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2752 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_RTR2RTS_QP,
2753 },
2754 [MLX5_QP_STATE_RTS] = {
2755 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2756 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2757 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_RTS2RTS_QP,
2758 },
2759 [MLX5_QP_STATE_SQD] = {
2760 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2761 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2762 },
2763 [MLX5_QP_STATE_SQER] = {
2764 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2765 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2766 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_SQERR2RTS_QP,
2767 },
2768 [MLX5_QP_STATE_ERR] = {
2769 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2770 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2771 }
2772 };
2773
2774 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
2775 struct mlx5_ib_qp *qp = to_mqp(ibqp);
2776 struct mlx5_ib_qp_base *base = &qp->trans_qp.base;
2777 struct mlx5_ib_cq *send_cq, *recv_cq;
2778 struct mlx5_qp_context *context;
2779 struct mlx5_ib_pd *pd;
2780 struct mlx5_ib_port *mibport = NULL;
2781 enum mlx5_qp_state mlx5_cur, mlx5_new;
2782 enum mlx5_qp_optpar optpar;
2783 int mlx5_st;
2784 int err;
2785 u16 op;
2786
2787 context = kzalloc(sizeof(*context), GFP_KERNEL);
2788 if (!context)
2789 return -ENOMEM;
2790
2791 err = to_mlx5_st(ibqp->qp_type);
2792 if (err < 0) {
2793 mlx5_ib_dbg(dev, "unsupported qp type %d\n", ibqp->qp_type);
2794 goto out;
2795 }
2796
2797 context->flags = cpu_to_be32(err << 16);
2798
2799 if (!(attr_mask & IB_QP_PATH_MIG_STATE)) {
2800 context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11);
2801 } else {
2802 switch (attr->path_mig_state) {
2803 case IB_MIG_MIGRATED:
2804 context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11);
2805 break;
2806 case IB_MIG_REARM:
2807 context->flags |= cpu_to_be32(MLX5_QP_PM_REARM << 11);
2808 break;
2809 case IB_MIG_ARMED:
2810 context->flags |= cpu_to_be32(MLX5_QP_PM_ARMED << 11);
2811 break;
2812 }
2813 }
2814
2815 if (is_sqp(ibqp->qp_type)) {
2816 context->mtu_msgmax = (IB_MTU_256 << 5) | 8;
2817 } else if (ibqp->qp_type == IB_QPT_UD ||
2818 ibqp->qp_type == MLX5_IB_QPT_REG_UMR) {
2819 context->mtu_msgmax = (IB_MTU_4096 << 5) | 12;
2820 } else if (attr_mask & IB_QP_PATH_MTU) {
2821 if (attr->path_mtu < IB_MTU_256 ||
2822 attr->path_mtu > IB_MTU_4096) {
2823 mlx5_ib_warn(dev, "invalid mtu %d\n", attr->path_mtu);
2824 err = -EINVAL;
2825 goto out;
2826 }
2827 context->mtu_msgmax = (attr->path_mtu << 5) |
2828 (u8)MLX5_CAP_GEN(dev->mdev, log_max_msg);
2829 }
2830
2831 if (attr_mask & IB_QP_DEST_QPN)
2832 context->log_pg_sz_remote_qpn = cpu_to_be32(attr->dest_qp_num);
2833
2834 if (attr_mask & IB_QP_PKEY_INDEX)
2835 context->pri_path.pkey_index = cpu_to_be16(attr->pkey_index);
2836
2837 /* todo implement counter_index functionality */
2838
2839 if (is_sqp(ibqp->qp_type))
2840 context->pri_path.port = qp->port;
2841
2842 if (attr_mask & IB_QP_PORT)
2843 context->pri_path.port = attr->port_num;
2844
2845 if (attr_mask & IB_QP_AV) {
2846 err = mlx5_set_path(dev, qp, &attr->ah_attr, &context->pri_path,
2847 attr_mask & IB_QP_PORT ? attr->port_num : qp->port,
2848 attr_mask, 0, attr, false);
2849 if (err)
2850 goto out;
2851 }
2852
2853 if (attr_mask & IB_QP_TIMEOUT)
2854 context->pri_path.ackto_lt |= attr->timeout << 3;
2855
2856 if (attr_mask & IB_QP_ALT_PATH) {
2857 err = mlx5_set_path(dev, qp, &attr->alt_ah_attr,
2858 &context->alt_path,
2859 attr->alt_port_num,
2860 attr_mask | IB_QP_PKEY_INDEX | IB_QP_TIMEOUT,
2861 0, attr, true);
2862 if (err)
2863 goto out;
2864 }
2865
2866 pd = get_pd(qp);
2867 get_cqs(qp->ibqp.qp_type, qp->ibqp.send_cq, qp->ibqp.recv_cq,
2868 &send_cq, &recv_cq);
2869
2870 context->flags_pd = cpu_to_be32(pd ? pd->pdn : to_mpd(dev->devr.p0)->pdn);
2871 context->cqn_send = send_cq ? cpu_to_be32(send_cq->mcq.cqn) : 0;
2872 context->cqn_recv = recv_cq ? cpu_to_be32(recv_cq->mcq.cqn) : 0;
2873 context->params1 = cpu_to_be32(MLX5_IB_ACK_REQ_FREQ << 28);
2874
2875 if (attr_mask & IB_QP_RNR_RETRY)
2876 context->params1 |= cpu_to_be32(attr->rnr_retry << 13);
2877
2878 if (attr_mask & IB_QP_RETRY_CNT)
2879 context->params1 |= cpu_to_be32(attr->retry_cnt << 16);
2880
2881 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
2882 if (attr->max_rd_atomic)
2883 context->params1 |=
2884 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21);
2885 }
2886
2887 if (attr_mask & IB_QP_SQ_PSN)
2888 context->next_send_psn = cpu_to_be32(attr->sq_psn);
2889
2890 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
2891 if (attr->max_dest_rd_atomic)
2892 context->params2 |=
2893 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21);
2894 }
2895
2896 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) {
2897 __be32 access_flags;
2898
2899 err = to_mlx5_access_flags(qp, attr, attr_mask, &access_flags);
2900 if (err)
2901 goto out;
2902
2903 context->params2 |= access_flags;
2904 }
2905
2906 if (attr_mask & IB_QP_MIN_RNR_TIMER)
2907 context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24);
2908
2909 if (attr_mask & IB_QP_RQ_PSN)
2910 context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn);
2911
2912 if (attr_mask & IB_QP_QKEY)
2913 context->qkey = cpu_to_be32(attr->qkey);
2914
2915 if (qp->rq.wqe_cnt && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
2916 context->db_rec_addr = cpu_to_be64(qp->db.dma);
2917
2918 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
2919 u8 port_num = (attr_mask & IB_QP_PORT ? attr->port_num :
2920 qp->port) - 1;
2921 mibport = &dev->port[port_num];
2922 context->qp_counter_set_usr_page |=
2923 cpu_to_be32((u32)(mibport->q_cnt_id) << 24);
2924 }
2925
2926 if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
2927 context->sq_crq_size |= cpu_to_be16(1 << 4);
2928
2929 if (qp->flags & MLX5_IB_QP_SQPN_QP1)
2930 context->deth_sqpn = cpu_to_be32(1);
2931
2932 mlx5_cur = to_mlx5_state(cur_state);
2933 mlx5_new = to_mlx5_state(new_state);
2934 mlx5_st = to_mlx5_st(ibqp->qp_type);
2935 if (mlx5_st < 0)
2936 goto out;
2937
2938 /* If moving to a reset or error state, we must disable page faults on
2939 * this QP and flush all current page faults. Otherwise a stale page
2940 * fault may attempt to work on this QP after it is reset and moved
2941 * again to RTS, and may cause the driver and the device to get out of
2942 * sync. */
2943 if (cur_state != IB_QPS_RESET && cur_state != IB_QPS_ERR &&
2944 (new_state == IB_QPS_RESET || new_state == IB_QPS_ERR) &&
2945 (qp->ibqp.qp_type != IB_QPT_RAW_PACKET))
2946 mlx5_ib_qp_disable_pagefaults(qp);
2947
2948 if (mlx5_cur >= MLX5_QP_NUM_STATE || mlx5_new >= MLX5_QP_NUM_STATE ||
2949 !optab[mlx5_cur][mlx5_new])
2950 goto out;
2951
2952 op = optab[mlx5_cur][mlx5_new];
2953 optpar = ib_mask_to_mlx5_opt(attr_mask);
2954 optpar &= opt_mask[mlx5_cur][mlx5_new][mlx5_st];
2955
2956 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET) {
2957 struct mlx5_modify_raw_qp_param raw_qp_param = {};
2958
2959 raw_qp_param.operation = op;
2960 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
2961 raw_qp_param.rq_q_ctr_id = mibport->q_cnt_id;
2962 raw_qp_param.set_mask |= MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID;
2963 }
2964 err = modify_raw_packet_qp(dev, qp, &raw_qp_param, 0);
2965 } else {
2966 err = mlx5_core_qp_modify(dev->mdev, op, optpar, context,
2967 &base->mqp);
2968 }
2969
2970 if (err)
2971 goto out;
2972
2973 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT &&
2974 (qp->ibqp.qp_type != IB_QPT_RAW_PACKET))
2975 mlx5_ib_qp_enable_pagefaults(qp);
2976
2977 qp->state = new_state;
2978
2979 if (attr_mask & IB_QP_ACCESS_FLAGS)
2980 qp->trans_qp.atomic_rd_en = attr->qp_access_flags;
2981 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
2982 qp->trans_qp.resp_depth = attr->max_dest_rd_atomic;
2983 if (attr_mask & IB_QP_PORT)
2984 qp->port = attr->port_num;
2985 if (attr_mask & IB_QP_ALT_PATH)
2986 qp->trans_qp.alt_port = attr->alt_port_num;
2987
2988 /*
2989 * If we moved a kernel QP to RESET, clean up all old CQ
2990 * entries and reinitialize the QP.
2991 */
2992 if (new_state == IB_QPS_RESET && !ibqp->uobject) {
2993 mlx5_ib_cq_clean(recv_cq, base->mqp.qpn,
2994 ibqp->srq ? to_msrq(ibqp->srq) : NULL);
2995 if (send_cq != recv_cq)
2996 mlx5_ib_cq_clean(send_cq, base->mqp.qpn, NULL);
2997
2998 qp->rq.head = 0;
2999 qp->rq.tail = 0;
3000 qp->sq.head = 0;
3001 qp->sq.tail = 0;
3002 qp->sq.cur_post = 0;
3003 qp->sq.last_poll = 0;
3004 qp->db.db[MLX5_RCV_DBR] = 0;
3005 qp->db.db[MLX5_SND_DBR] = 0;
3006 }
3007
3008 out:
3009 kfree(context);
3010 return err;
3011 }
3012
mlx5_ib_modify_qp(struct ib_qp * ibqp,struct ib_qp_attr * attr,int attr_mask,struct ib_udata * udata)3013 int mlx5_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
3014 int attr_mask, struct ib_udata *udata)
3015 {
3016 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
3017 struct mlx5_ib_qp *qp = to_mqp(ibqp);
3018 enum ib_qp_type qp_type;
3019 enum ib_qp_state cur_state, new_state;
3020 int err = -EINVAL;
3021 int port;
3022
3023 if (ibqp->rwq_ind_tbl)
3024 return -ENOSYS;
3025
3026 if (unlikely(ibqp->qp_type == IB_QPT_GSI))
3027 return mlx5_ib_gsi_modify_qp(ibqp, attr, attr_mask);
3028
3029 qp_type = (unlikely(ibqp->qp_type == MLX5_IB_QPT_HW_GSI)) ?
3030 IB_QPT_GSI : ibqp->qp_type;
3031
3032 mutex_lock(&qp->mutex);
3033
3034 cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state;
3035 new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state;
3036
3037 if (qp_type != MLX5_IB_QPT_REG_UMR &&
3038 !ib_modify_qp_is_ok(cur_state, new_state, qp_type, attr_mask)) {
3039 mlx5_ib_dbg(dev, "invalid QP state transition from %d to %d, qp_type %d, attr_mask 0x%x\n",
3040 cur_state, new_state, ibqp->qp_type, attr_mask);
3041 goto out;
3042 }
3043
3044 if ((attr_mask & IB_QP_PORT) &&
3045 (attr->port_num == 0 ||
3046 attr->port_num > MLX5_CAP_GEN(dev->mdev, num_ports))) {
3047 mlx5_ib_dbg(dev, "invalid port number %d. number of ports is %d\n",
3048 attr->port_num, dev->num_ports);
3049 goto out;
3050 }
3051
3052 if (attr_mask & IB_QP_PKEY_INDEX) {
3053 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
3054 if (attr->pkey_index >=
3055 dev->mdev->port_caps[port - 1].pkey_table_len) {
3056 mlx5_ib_dbg(dev, "invalid pkey index %d\n",
3057 attr->pkey_index);
3058 goto out;
3059 }
3060 }
3061
3062 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC &&
3063 attr->max_rd_atomic >
3064 (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_res_qp))) {
3065 mlx5_ib_dbg(dev, "invalid max_rd_atomic value %d\n",
3066 attr->max_rd_atomic);
3067 goto out;
3068 }
3069
3070 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC &&
3071 attr->max_dest_rd_atomic >
3072 (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_req_qp))) {
3073 mlx5_ib_dbg(dev, "invalid max_dest_rd_atomic value %d\n",
3074 attr->max_dest_rd_atomic);
3075 goto out;
3076 }
3077
3078 if (cur_state == new_state && cur_state == IB_QPS_RESET) {
3079 err = 0;
3080 goto out;
3081 }
3082
3083 err = __mlx5_ib_modify_qp(ibqp, attr, attr_mask, cur_state, new_state);
3084
3085 out:
3086 mutex_unlock(&qp->mutex);
3087 return err;
3088 }
3089
mlx5_wq_overflow(struct mlx5_ib_wq * wq,int nreq,struct ib_cq * ib_cq)3090 static int mlx5_wq_overflow(struct mlx5_ib_wq *wq, int nreq, struct ib_cq *ib_cq)
3091 {
3092 struct mlx5_ib_cq *cq;
3093 unsigned cur;
3094
3095 cur = wq->head - wq->tail;
3096 if (likely(cur + nreq < wq->max_post))
3097 return 0;
3098
3099 cq = to_mcq(ib_cq);
3100 spin_lock(&cq->lock);
3101 cur = wq->head - wq->tail;
3102 spin_unlock(&cq->lock);
3103
3104 return cur + nreq >= wq->max_post;
3105 }
3106
set_raddr_seg(struct mlx5_wqe_raddr_seg * rseg,u64 remote_addr,u32 rkey)3107 static __always_inline void set_raddr_seg(struct mlx5_wqe_raddr_seg *rseg,
3108 u64 remote_addr, u32 rkey)
3109 {
3110 rseg->raddr = cpu_to_be64(remote_addr);
3111 rseg->rkey = cpu_to_be32(rkey);
3112 rseg->reserved = 0;
3113 }
3114
set_eth_seg(struct mlx5_wqe_eth_seg * eseg,const struct ib_send_wr * wr,void * qend,struct mlx5_ib_qp * qp,int * size)3115 static void *set_eth_seg(struct mlx5_wqe_eth_seg *eseg,
3116 const struct ib_send_wr *wr, void *qend,
3117 struct mlx5_ib_qp *qp, int *size)
3118 {
3119 void *seg = eseg;
3120
3121 memset(eseg, 0, sizeof(struct mlx5_wqe_eth_seg));
3122
3123 if (wr->send_flags & IB_SEND_IP_CSUM)
3124 eseg->cs_flags = MLX5_ETH_WQE_L3_CSUM |
3125 MLX5_ETH_WQE_L4_CSUM;
3126
3127 seg += sizeof(struct mlx5_wqe_eth_seg);
3128 *size += sizeof(struct mlx5_wqe_eth_seg) / 16;
3129
3130 if (wr->opcode == IB_WR_LSO) {
3131 struct ib_ud_wr *ud_wr = container_of(wr, struct ib_ud_wr, wr);
3132 int size_of_inl_hdr_start = sizeof(eseg->inline_hdr_start);
3133 u64 left, leftlen, copysz;
3134 void *pdata = ud_wr->header;
3135
3136 left = ud_wr->hlen;
3137 eseg->mss = cpu_to_be16(ud_wr->mss);
3138 eseg->inline_hdr_sz = cpu_to_be16(left);
3139
3140 /*
3141 * check if there is space till the end of queue, if yes,
3142 * copy all in one shot, otherwise copy till the end of queue,
3143 * rollback and than the copy the left
3144 */
3145 leftlen = qend - (void *)eseg->inline_hdr_start;
3146 copysz = min_t(u64, leftlen, left);
3147
3148 memcpy(seg - size_of_inl_hdr_start, pdata, copysz);
3149
3150 if (likely(copysz > size_of_inl_hdr_start)) {
3151 seg += ALIGN(copysz - size_of_inl_hdr_start, 16);
3152 *size += ALIGN(copysz - size_of_inl_hdr_start, 16) / 16;
3153 }
3154
3155 if (unlikely(copysz < left)) { /* the last wqe in the queue */
3156 seg = mlx5_get_send_wqe(qp, 0);
3157 left -= copysz;
3158 pdata += copysz;
3159 memcpy(seg, pdata, left);
3160 seg += ALIGN(left, 16);
3161 *size += ALIGN(left, 16) / 16;
3162 }
3163 }
3164
3165 return seg;
3166 }
3167
set_datagram_seg(struct mlx5_wqe_datagram_seg * dseg,const struct ib_send_wr * wr)3168 static void set_datagram_seg(struct mlx5_wqe_datagram_seg *dseg,
3169 const struct ib_send_wr *wr)
3170 {
3171 memcpy(&dseg->av, &to_mah(ud_wr(wr)->ah)->av, sizeof(struct mlx5_av));
3172 dseg->av.dqp_dct = cpu_to_be32(ud_wr(wr)->remote_qpn | MLX5_EXTENDED_UD_AV);
3173 dseg->av.key.qkey.qkey = cpu_to_be32(ud_wr(wr)->remote_qkey);
3174 }
3175
set_data_ptr_seg(struct mlx5_wqe_data_seg * dseg,struct ib_sge * sg)3176 static void set_data_ptr_seg(struct mlx5_wqe_data_seg *dseg, struct ib_sge *sg)
3177 {
3178 dseg->byte_count = cpu_to_be32(sg->length);
3179 dseg->lkey = cpu_to_be32(sg->lkey);
3180 dseg->addr = cpu_to_be64(sg->addr);
3181 }
3182
get_klm_octo(int npages)3183 static __be16 get_klm_octo(int npages)
3184 {
3185 return cpu_to_be16(ALIGN(npages, 8) / 2);
3186 }
3187
frwr_mkey_mask(void)3188 static __be64 frwr_mkey_mask(void)
3189 {
3190 u64 result;
3191
3192 result = MLX5_MKEY_MASK_LEN |
3193 MLX5_MKEY_MASK_PAGE_SIZE |
3194 MLX5_MKEY_MASK_START_ADDR |
3195 MLX5_MKEY_MASK_EN_RINVAL |
3196 MLX5_MKEY_MASK_KEY |
3197 MLX5_MKEY_MASK_LR |
3198 MLX5_MKEY_MASK_LW |
3199 MLX5_MKEY_MASK_RR |
3200 MLX5_MKEY_MASK_RW |
3201 MLX5_MKEY_MASK_A |
3202 MLX5_MKEY_MASK_SMALL_FENCE |
3203 MLX5_MKEY_MASK_FREE;
3204
3205 return cpu_to_be64(result);
3206 }
3207
sig_mkey_mask(void)3208 static __be64 sig_mkey_mask(void)
3209 {
3210 u64 result;
3211
3212 result = MLX5_MKEY_MASK_LEN |
3213 MLX5_MKEY_MASK_PAGE_SIZE |
3214 MLX5_MKEY_MASK_START_ADDR |
3215 MLX5_MKEY_MASK_EN_SIGERR |
3216 MLX5_MKEY_MASK_EN_RINVAL |
3217 MLX5_MKEY_MASK_KEY |
3218 MLX5_MKEY_MASK_LR |
3219 MLX5_MKEY_MASK_LW |
3220 MLX5_MKEY_MASK_RR |
3221 MLX5_MKEY_MASK_RW |
3222 MLX5_MKEY_MASK_SMALL_FENCE |
3223 MLX5_MKEY_MASK_FREE |
3224 MLX5_MKEY_MASK_BSF_EN;
3225
3226 return cpu_to_be64(result);
3227 }
3228
set_reg_umr_seg(struct mlx5_wqe_umr_ctrl_seg * umr,struct mlx5_ib_mr * mr)3229 static void set_reg_umr_seg(struct mlx5_wqe_umr_ctrl_seg *umr,
3230 struct mlx5_ib_mr *mr)
3231 {
3232 int ndescs = mr->ndescs;
3233
3234 memset(umr, 0, sizeof(*umr));
3235
3236 if (mr->access_mode == MLX5_ACCESS_MODE_KLM)
3237 /* KLMs take twice the size of MTTs */
3238 ndescs *= 2;
3239
3240 umr->flags = MLX5_UMR_CHECK_NOT_FREE;
3241 umr->klm_octowords = get_klm_octo(ndescs);
3242 umr->mkey_mask = frwr_mkey_mask();
3243 }
3244
set_linv_umr_seg(struct mlx5_wqe_umr_ctrl_seg * umr)3245 static void set_linv_umr_seg(struct mlx5_wqe_umr_ctrl_seg *umr)
3246 {
3247 memset(umr, 0, sizeof(*umr));
3248 umr->mkey_mask = cpu_to_be64(MLX5_MKEY_MASK_FREE);
3249 umr->flags = 1 << 7;
3250 }
3251
get_umr_reg_mr_mask(void)3252 static __be64 get_umr_reg_mr_mask(void)
3253 {
3254 u64 result;
3255
3256 result = MLX5_MKEY_MASK_LEN |
3257 MLX5_MKEY_MASK_PAGE_SIZE |
3258 MLX5_MKEY_MASK_START_ADDR |
3259 MLX5_MKEY_MASK_PD |
3260 MLX5_MKEY_MASK_LR |
3261 MLX5_MKEY_MASK_LW |
3262 MLX5_MKEY_MASK_KEY |
3263 MLX5_MKEY_MASK_RR |
3264 MLX5_MKEY_MASK_RW |
3265 MLX5_MKEY_MASK_A |
3266 MLX5_MKEY_MASK_FREE;
3267
3268 return cpu_to_be64(result);
3269 }
3270
get_umr_unreg_mr_mask(void)3271 static __be64 get_umr_unreg_mr_mask(void)
3272 {
3273 u64 result;
3274
3275 result = MLX5_MKEY_MASK_FREE;
3276
3277 return cpu_to_be64(result);
3278 }
3279
get_umr_update_mtt_mask(void)3280 static __be64 get_umr_update_mtt_mask(void)
3281 {
3282 u64 result;
3283
3284 result = MLX5_MKEY_MASK_FREE;
3285
3286 return cpu_to_be64(result);
3287 }
3288
get_umr_update_translation_mask(void)3289 static __be64 get_umr_update_translation_mask(void)
3290 {
3291 u64 result;
3292
3293 result = MLX5_MKEY_MASK_LEN |
3294 MLX5_MKEY_MASK_PAGE_SIZE |
3295 MLX5_MKEY_MASK_START_ADDR |
3296 MLX5_MKEY_MASK_KEY |
3297 MLX5_MKEY_MASK_FREE;
3298
3299 return cpu_to_be64(result);
3300 }
3301
get_umr_update_access_mask(void)3302 static __be64 get_umr_update_access_mask(void)
3303 {
3304 u64 result;
3305
3306 result = MLX5_MKEY_MASK_LW |
3307 MLX5_MKEY_MASK_RR |
3308 MLX5_MKEY_MASK_RW |
3309 MLX5_MKEY_MASK_A |
3310 MLX5_MKEY_MASK_KEY |
3311 MLX5_MKEY_MASK_FREE;
3312
3313 return cpu_to_be64(result);
3314 }
3315
get_umr_update_pd_mask(void)3316 static __be64 get_umr_update_pd_mask(void)
3317 {
3318 u64 result;
3319
3320 result = MLX5_MKEY_MASK_PD |
3321 MLX5_MKEY_MASK_KEY |
3322 MLX5_MKEY_MASK_FREE;
3323
3324 return cpu_to_be64(result);
3325 }
3326
set_reg_umr_segment(struct mlx5_wqe_umr_ctrl_seg * umr,const struct ib_send_wr * wr)3327 static void set_reg_umr_segment(struct mlx5_wqe_umr_ctrl_seg *umr,
3328 const struct ib_send_wr *wr)
3329 {
3330 const struct mlx5_umr_wr *umrwr = umr_wr(wr);
3331
3332 memset(umr, 0, sizeof(*umr));
3333
3334 if (wr->send_flags & MLX5_IB_SEND_UMR_FAIL_IF_FREE)
3335 umr->flags = MLX5_UMR_CHECK_FREE; /* fail if free */
3336 else
3337 umr->flags = MLX5_UMR_CHECK_NOT_FREE; /* fail if not free */
3338
3339 if (!(wr->send_flags & MLX5_IB_SEND_UMR_UNREG)) {
3340 umr->klm_octowords = get_klm_octo(umrwr->npages);
3341 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_MTT) {
3342 umr->mkey_mask = get_umr_update_mtt_mask();
3343 umr->bsf_octowords = get_klm_octo(umrwr->target.offset);
3344 umr->flags |= MLX5_UMR_TRANSLATION_OFFSET_EN;
3345 }
3346 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_TRANSLATION)
3347 umr->mkey_mask |= get_umr_update_translation_mask();
3348 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_ACCESS)
3349 umr->mkey_mask |= get_umr_update_access_mask();
3350 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_PD)
3351 umr->mkey_mask |= get_umr_update_pd_mask();
3352 if (!umr->mkey_mask)
3353 umr->mkey_mask = get_umr_reg_mr_mask();
3354 } else {
3355 umr->mkey_mask = get_umr_unreg_mr_mask();
3356 }
3357
3358 if (!wr->num_sge)
3359 umr->flags |= MLX5_UMR_INLINE;
3360 }
3361
get_umr_flags(int acc)3362 static u8 get_umr_flags(int acc)
3363 {
3364 return (acc & IB_ACCESS_REMOTE_ATOMIC ? MLX5_PERM_ATOMIC : 0) |
3365 (acc & IB_ACCESS_REMOTE_WRITE ? MLX5_PERM_REMOTE_WRITE : 0) |
3366 (acc & IB_ACCESS_REMOTE_READ ? MLX5_PERM_REMOTE_READ : 0) |
3367 (acc & IB_ACCESS_LOCAL_WRITE ? MLX5_PERM_LOCAL_WRITE : 0) |
3368 MLX5_PERM_LOCAL_READ | MLX5_PERM_UMR_EN;
3369 }
3370
set_reg_mkey_seg(struct mlx5_mkey_seg * seg,struct mlx5_ib_mr * mr,u32 key,int access)3371 static void set_reg_mkey_seg(struct mlx5_mkey_seg *seg,
3372 struct mlx5_ib_mr *mr,
3373 u32 key, int access)
3374 {
3375 int ndescs = ALIGN(mr->ndescs, 8) >> 1;
3376
3377 memset(seg, 0, sizeof(*seg));
3378
3379 if (mr->access_mode == MLX5_ACCESS_MODE_MTT)
3380 seg->log2_page_size = ilog2(mr->ibmr.page_size);
3381 else if (mr->access_mode == MLX5_ACCESS_MODE_KLM)
3382 /* KLMs take twice the size of MTTs */
3383 ndescs *= 2;
3384
3385 seg->flags = get_umr_flags(access) | mr->access_mode;
3386 seg->qpn_mkey7_0 = cpu_to_be32((key & 0xff) | 0xffffff00);
3387 seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL);
3388 seg->start_addr = cpu_to_be64(mr->ibmr.iova);
3389 seg->len = cpu_to_be64(mr->ibmr.length);
3390 seg->xlt_oct_size = cpu_to_be32(ndescs);
3391 }
3392
set_linv_mkey_seg(struct mlx5_mkey_seg * seg)3393 static void set_linv_mkey_seg(struct mlx5_mkey_seg *seg)
3394 {
3395 memset(seg, 0, sizeof(*seg));
3396 seg->status = MLX5_MKEY_STATUS_FREE;
3397 }
3398
set_reg_mkey_segment(struct mlx5_mkey_seg * seg,const struct ib_send_wr * wr)3399 static void set_reg_mkey_segment(struct mlx5_mkey_seg *seg, const struct ib_send_wr *wr)
3400 {
3401 const struct mlx5_umr_wr *umrwr = umr_wr(wr);
3402
3403 memset(seg, 0, sizeof(*seg));
3404 if (wr->send_flags & MLX5_IB_SEND_UMR_UNREG) {
3405 seg->status = MLX5_MKEY_STATUS_FREE;
3406 return;
3407 }
3408
3409 seg->flags = convert_access(umrwr->access_flags);
3410 if (!(wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_MTT)) {
3411 if (umrwr->pd)
3412 seg->flags_pd = cpu_to_be32(to_mpd(umrwr->pd)->pdn);
3413 seg->start_addr = cpu_to_be64(umrwr->target.virt_addr);
3414 }
3415 seg->len = cpu_to_be64(umrwr->length);
3416 seg->log2_page_size = umrwr->page_shift;
3417 seg->qpn_mkey7_0 = cpu_to_be32(0xffffff00 |
3418 mlx5_mkey_variant(umrwr->mkey));
3419 }
3420
set_reg_data_seg(struct mlx5_wqe_data_seg * dseg,struct mlx5_ib_mr * mr,struct mlx5_ib_pd * pd)3421 static void set_reg_data_seg(struct mlx5_wqe_data_seg *dseg,
3422 struct mlx5_ib_mr *mr,
3423 struct mlx5_ib_pd *pd)
3424 {
3425 int bcount = mr->desc_size * mr->ndescs;
3426
3427 dseg->addr = cpu_to_be64(mr->desc_map);
3428 dseg->byte_count = cpu_to_be32(ALIGN(bcount, 64));
3429 dseg->lkey = cpu_to_be32(pd->ibpd.local_dma_lkey);
3430 }
3431
send_ieth(const struct ib_send_wr * wr)3432 static __be32 send_ieth(const struct ib_send_wr *wr)
3433 {
3434 switch (wr->opcode) {
3435 case IB_WR_SEND_WITH_IMM:
3436 case IB_WR_RDMA_WRITE_WITH_IMM:
3437 return wr->ex.imm_data;
3438
3439 case IB_WR_SEND_WITH_INV:
3440 return cpu_to_be32(wr->ex.invalidate_rkey);
3441
3442 default:
3443 return 0;
3444 }
3445 }
3446
calc_sig(void * wqe,int size)3447 static u8 calc_sig(void *wqe, int size)
3448 {
3449 u8 *p = wqe;
3450 u8 res = 0;
3451 int i;
3452
3453 for (i = 0; i < size; i++)
3454 res ^= p[i];
3455
3456 return ~res;
3457 }
3458
wq_sig(void * wqe)3459 static u8 wq_sig(void *wqe)
3460 {
3461 return calc_sig(wqe, (*((u8 *)wqe + 8) & 0x3f) << 4);
3462 }
3463
set_data_inl_seg(struct mlx5_ib_qp * qp,const struct ib_send_wr * wr,void * wqe,int * sz)3464 static int set_data_inl_seg(struct mlx5_ib_qp *qp, const struct ib_send_wr *wr,
3465 void *wqe, int *sz)
3466 {
3467 struct mlx5_wqe_inline_seg *seg;
3468 void *qend = qp->sq.qend;
3469 void *addr;
3470 int inl = 0;
3471 int copy;
3472 int len;
3473 int i;
3474
3475 seg = wqe;
3476 wqe += sizeof(*seg);
3477 for (i = 0; i < wr->num_sge; i++) {
3478 addr = (void *)(unsigned long)(wr->sg_list[i].addr);
3479 len = wr->sg_list[i].length;
3480 inl += len;
3481
3482 if (unlikely(inl > qp->max_inline_data))
3483 return -ENOMEM;
3484
3485 if (unlikely(wqe + len > qend)) {
3486 copy = qend - wqe;
3487 memcpy(wqe, addr, copy);
3488 addr += copy;
3489 len -= copy;
3490 wqe = mlx5_get_send_wqe(qp, 0);
3491 }
3492 memcpy(wqe, addr, len);
3493 wqe += len;
3494 }
3495
3496 seg->byte_count = cpu_to_be32(inl | MLX5_INLINE_SEG);
3497
3498 *sz = ALIGN(inl + sizeof(seg->byte_count), 16) / 16;
3499
3500 return 0;
3501 }
3502
prot_field_size(enum ib_signature_type type)3503 static u16 prot_field_size(enum ib_signature_type type)
3504 {
3505 switch (type) {
3506 case IB_SIG_TYPE_T10_DIF:
3507 return MLX5_DIF_SIZE;
3508 default:
3509 return 0;
3510 }
3511 }
3512
bs_selector(int block_size)3513 static u8 bs_selector(int block_size)
3514 {
3515 switch (block_size) {
3516 case 512: return 0x1;
3517 case 520: return 0x2;
3518 case 4096: return 0x3;
3519 case 4160: return 0x4;
3520 case 1073741824: return 0x5;
3521 default: return 0;
3522 }
3523 }
3524
mlx5_fill_inl_bsf(struct ib_sig_domain * domain,struct mlx5_bsf_inl * inl)3525 static void mlx5_fill_inl_bsf(struct ib_sig_domain *domain,
3526 struct mlx5_bsf_inl *inl)
3527 {
3528 /* Valid inline section and allow BSF refresh */
3529 inl->vld_refresh = cpu_to_be16(MLX5_BSF_INL_VALID |
3530 MLX5_BSF_REFRESH_DIF);
3531 inl->dif_apptag = cpu_to_be16(domain->sig.dif.app_tag);
3532 inl->dif_reftag = cpu_to_be32(domain->sig.dif.ref_tag);
3533 /* repeating block */
3534 inl->rp_inv_seed = MLX5_BSF_REPEAT_BLOCK;
3535 inl->sig_type = domain->sig.dif.bg_type == IB_T10DIF_CRC ?
3536 MLX5_DIF_CRC : MLX5_DIF_IPCS;
3537
3538 if (domain->sig.dif.ref_remap)
3539 inl->dif_inc_ref_guard_check |= MLX5_BSF_INC_REFTAG;
3540
3541 if (domain->sig.dif.app_escape) {
3542 if (domain->sig.dif.ref_escape)
3543 inl->dif_inc_ref_guard_check |= MLX5_BSF_APPREF_ESCAPE;
3544 else
3545 inl->dif_inc_ref_guard_check |= MLX5_BSF_APPTAG_ESCAPE;
3546 }
3547
3548 inl->dif_app_bitmask_check =
3549 cpu_to_be16(domain->sig.dif.apptag_check_mask);
3550 }
3551
mlx5_set_bsf(struct ib_mr * sig_mr,struct ib_sig_attrs * sig_attrs,struct mlx5_bsf * bsf,u32 data_size)3552 static int mlx5_set_bsf(struct ib_mr *sig_mr,
3553 struct ib_sig_attrs *sig_attrs,
3554 struct mlx5_bsf *bsf, u32 data_size)
3555 {
3556 struct mlx5_core_sig_ctx *msig = to_mmr(sig_mr)->sig;
3557 struct mlx5_bsf_basic *basic = &bsf->basic;
3558 struct ib_sig_domain *mem = &sig_attrs->mem;
3559 struct ib_sig_domain *wire = &sig_attrs->wire;
3560
3561 memset(bsf, 0, sizeof(*bsf));
3562
3563 /* Basic + Extended + Inline */
3564 basic->bsf_size_sbs = 1 << 7;
3565 /* Input domain check byte mask */
3566 basic->check_byte_mask = sig_attrs->check_mask;
3567 basic->raw_data_size = cpu_to_be32(data_size);
3568
3569 /* Memory domain */
3570 switch (sig_attrs->mem.sig_type) {
3571 case IB_SIG_TYPE_NONE:
3572 break;
3573 case IB_SIG_TYPE_T10_DIF:
3574 basic->mem.bs_selector = bs_selector(mem->sig.dif.pi_interval);
3575 basic->m_bfs_psv = cpu_to_be32(msig->psv_memory.psv_idx);
3576 mlx5_fill_inl_bsf(mem, &bsf->m_inl);
3577 break;
3578 default:
3579 return -EINVAL;
3580 }
3581
3582 /* Wire domain */
3583 switch (sig_attrs->wire.sig_type) {
3584 case IB_SIG_TYPE_NONE:
3585 break;
3586 case IB_SIG_TYPE_T10_DIF:
3587 if (mem->sig.dif.pi_interval == wire->sig.dif.pi_interval &&
3588 mem->sig_type == wire->sig_type) {
3589 /* Same block structure */
3590 basic->bsf_size_sbs |= 1 << 4;
3591 if (mem->sig.dif.bg_type == wire->sig.dif.bg_type)
3592 basic->wire.copy_byte_mask |= MLX5_CPY_GRD_MASK;
3593 if (mem->sig.dif.app_tag == wire->sig.dif.app_tag)
3594 basic->wire.copy_byte_mask |= MLX5_CPY_APP_MASK;
3595 if (mem->sig.dif.ref_tag == wire->sig.dif.ref_tag)
3596 basic->wire.copy_byte_mask |= MLX5_CPY_REF_MASK;
3597 } else
3598 basic->wire.bs_selector = bs_selector(wire->sig.dif.pi_interval);
3599
3600 basic->w_bfs_psv = cpu_to_be32(msig->psv_wire.psv_idx);
3601 mlx5_fill_inl_bsf(wire, &bsf->w_inl);
3602 break;
3603 default:
3604 return -EINVAL;
3605 }
3606
3607 return 0;
3608 }
3609
set_sig_data_segment(const struct ib_sig_handover_wr * wr,struct mlx5_ib_qp * qp,void ** seg,int * size)3610 static int set_sig_data_segment(const struct ib_sig_handover_wr *wr,
3611 struct mlx5_ib_qp *qp, void **seg, int *size)
3612 {
3613 struct ib_sig_attrs *sig_attrs = wr->sig_attrs;
3614 struct ib_mr *sig_mr = wr->sig_mr;
3615 struct mlx5_bsf *bsf;
3616 u32 data_len = wr->wr.sg_list->length;
3617 u32 data_key = wr->wr.sg_list->lkey;
3618 u64 data_va = wr->wr.sg_list->addr;
3619 int ret;
3620 int wqe_size;
3621
3622 if (!wr->prot ||
3623 (data_key == wr->prot->lkey &&
3624 data_va == wr->prot->addr &&
3625 data_len == wr->prot->length)) {
3626 /**
3627 * Source domain doesn't contain signature information
3628 * or data and protection are interleaved in memory.
3629 * So need construct:
3630 * ------------------
3631 * | data_klm |
3632 * ------------------
3633 * | BSF |
3634 * ------------------
3635 **/
3636 struct mlx5_klm *data_klm = *seg;
3637
3638 data_klm->bcount = cpu_to_be32(data_len);
3639 data_klm->key = cpu_to_be32(data_key);
3640 data_klm->va = cpu_to_be64(data_va);
3641 wqe_size = ALIGN(sizeof(*data_klm), 64);
3642 } else {
3643 /**
3644 * Source domain contains signature information
3645 * So need construct a strided block format:
3646 * ---------------------------
3647 * | stride_block_ctrl |
3648 * ---------------------------
3649 * | data_klm |
3650 * ---------------------------
3651 * | prot_klm |
3652 * ---------------------------
3653 * | BSF |
3654 * ---------------------------
3655 **/
3656 struct mlx5_stride_block_ctrl_seg *sblock_ctrl;
3657 struct mlx5_stride_block_entry *data_sentry;
3658 struct mlx5_stride_block_entry *prot_sentry;
3659 u32 prot_key = wr->prot->lkey;
3660 u64 prot_va = wr->prot->addr;
3661 u16 block_size = sig_attrs->mem.sig.dif.pi_interval;
3662 int prot_size;
3663
3664 sblock_ctrl = *seg;
3665 data_sentry = (void *)sblock_ctrl + sizeof(*sblock_ctrl);
3666 prot_sentry = (void *)data_sentry + sizeof(*data_sentry);
3667
3668 prot_size = prot_field_size(sig_attrs->mem.sig_type);
3669 if (!prot_size) {
3670 pr_err("Bad block size given: %u\n", block_size);
3671 return -EINVAL;
3672 }
3673 sblock_ctrl->bcount_per_cycle = cpu_to_be32(block_size +
3674 prot_size);
3675 sblock_ctrl->op = cpu_to_be32(MLX5_STRIDE_BLOCK_OP);
3676 sblock_ctrl->repeat_count = cpu_to_be32(data_len / block_size);
3677 sblock_ctrl->num_entries = cpu_to_be16(2);
3678
3679 data_sentry->bcount = cpu_to_be16(block_size);
3680 data_sentry->key = cpu_to_be32(data_key);
3681 data_sentry->va = cpu_to_be64(data_va);
3682 data_sentry->stride = cpu_to_be16(block_size);
3683
3684 prot_sentry->bcount = cpu_to_be16(prot_size);
3685 prot_sentry->key = cpu_to_be32(prot_key);
3686 prot_sentry->va = cpu_to_be64(prot_va);
3687 prot_sentry->stride = cpu_to_be16(prot_size);
3688
3689 wqe_size = ALIGN(sizeof(*sblock_ctrl) + sizeof(*data_sentry) +
3690 sizeof(*prot_sentry), 64);
3691 }
3692
3693 *seg += wqe_size;
3694 *size += wqe_size / 16;
3695 if (unlikely((*seg == qp->sq.qend)))
3696 *seg = mlx5_get_send_wqe(qp, 0);
3697
3698 bsf = *seg;
3699 ret = mlx5_set_bsf(sig_mr, sig_attrs, bsf, data_len);
3700 if (ret)
3701 return -EINVAL;
3702
3703 *seg += sizeof(*bsf);
3704 *size += sizeof(*bsf) / 16;
3705 if (unlikely((*seg == qp->sq.qend)))
3706 *seg = mlx5_get_send_wqe(qp, 0);
3707
3708 return 0;
3709 }
3710
set_sig_mkey_segment(struct mlx5_mkey_seg * seg,const struct ib_sig_handover_wr * wr,u32 nelements,u32 length,u32 pdn)3711 static void set_sig_mkey_segment(struct mlx5_mkey_seg *seg,
3712 const struct ib_sig_handover_wr *wr, u32 nelements,
3713 u32 length, u32 pdn)
3714 {
3715 struct ib_mr *sig_mr = wr->sig_mr;
3716 u32 sig_key = sig_mr->rkey;
3717 u8 sigerr = to_mmr(sig_mr)->sig->sigerr_count & 1;
3718
3719 memset(seg, 0, sizeof(*seg));
3720
3721 seg->flags = get_umr_flags(wr->access_flags) |
3722 MLX5_ACCESS_MODE_KLM;
3723 seg->qpn_mkey7_0 = cpu_to_be32((sig_key & 0xff) | 0xffffff00);
3724 seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL | sigerr << 26 |
3725 MLX5_MKEY_BSF_EN | pdn);
3726 seg->len = cpu_to_be64(length);
3727 seg->xlt_oct_size = cpu_to_be32(be16_to_cpu(get_klm_octo(nelements)));
3728 seg->bsfs_octo_size = cpu_to_be32(MLX5_MKEY_BSF_OCTO_SIZE);
3729 }
3730
set_sig_umr_segment(struct mlx5_wqe_umr_ctrl_seg * umr,u32 nelements)3731 static void set_sig_umr_segment(struct mlx5_wqe_umr_ctrl_seg *umr,
3732 u32 nelements)
3733 {
3734 memset(umr, 0, sizeof(*umr));
3735
3736 umr->flags = MLX5_FLAGS_INLINE | MLX5_FLAGS_CHECK_FREE;
3737 umr->klm_octowords = get_klm_octo(nelements);
3738 umr->bsf_octowords = cpu_to_be16(MLX5_MKEY_BSF_OCTO_SIZE);
3739 umr->mkey_mask = sig_mkey_mask();
3740 }
3741
3742
set_sig_umr_wr(const struct ib_send_wr * send_wr,struct mlx5_ib_qp * qp,void ** seg,int * size)3743 static int set_sig_umr_wr(const struct ib_send_wr *send_wr, struct mlx5_ib_qp *qp,
3744 void **seg, int *size)
3745 {
3746 const struct ib_sig_handover_wr *wr = sig_handover_wr(send_wr);
3747 struct mlx5_ib_mr *sig_mr = to_mmr(wr->sig_mr);
3748 u32 pdn = get_pd(qp)->pdn;
3749 u32 klm_oct_size;
3750 int region_len, ret;
3751
3752 if (unlikely(wr->wr.num_sge != 1) ||
3753 unlikely(wr->access_flags & IB_ACCESS_REMOTE_ATOMIC) ||
3754 unlikely(!sig_mr->sig) || unlikely(!qp->signature_en) ||
3755 unlikely(!sig_mr->sig->sig_status_checked))
3756 return -EINVAL;
3757
3758 /* length of the protected region, data + protection */
3759 region_len = wr->wr.sg_list->length;
3760 if (wr->prot &&
3761 (wr->prot->lkey != wr->wr.sg_list->lkey ||
3762 wr->prot->addr != wr->wr.sg_list->addr ||
3763 wr->prot->length != wr->wr.sg_list->length))
3764 region_len += wr->prot->length;
3765
3766 /**
3767 * KLM octoword size - if protection was provided
3768 * then we use strided block format (3 octowords),
3769 * else we use single KLM (1 octoword)
3770 **/
3771 klm_oct_size = wr->prot ? 3 : 1;
3772
3773 set_sig_umr_segment(*seg, klm_oct_size);
3774 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
3775 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
3776 if (unlikely((*seg == qp->sq.qend)))
3777 *seg = mlx5_get_send_wqe(qp, 0);
3778
3779 set_sig_mkey_segment(*seg, wr, klm_oct_size, region_len, pdn);
3780 *seg += sizeof(struct mlx5_mkey_seg);
3781 *size += sizeof(struct mlx5_mkey_seg) / 16;
3782 if (unlikely((*seg == qp->sq.qend)))
3783 *seg = mlx5_get_send_wqe(qp, 0);
3784
3785 ret = set_sig_data_segment(wr, qp, seg, size);
3786 if (ret)
3787 return ret;
3788
3789 sig_mr->sig->sig_status_checked = false;
3790 return 0;
3791 }
3792
set_psv_wr(struct ib_sig_domain * domain,u32 psv_idx,void ** seg,int * size)3793 static int set_psv_wr(struct ib_sig_domain *domain,
3794 u32 psv_idx, void **seg, int *size)
3795 {
3796 struct mlx5_seg_set_psv *psv_seg = *seg;
3797
3798 memset(psv_seg, 0, sizeof(*psv_seg));
3799 psv_seg->psv_num = cpu_to_be32(psv_idx);
3800 switch (domain->sig_type) {
3801 case IB_SIG_TYPE_NONE:
3802 break;
3803 case IB_SIG_TYPE_T10_DIF:
3804 psv_seg->transient_sig = cpu_to_be32(domain->sig.dif.bg << 16 |
3805 domain->sig.dif.app_tag);
3806 psv_seg->ref_tag = cpu_to_be32(domain->sig.dif.ref_tag);
3807 break;
3808 default:
3809 pr_err("Bad signature type given.\n");
3810 return 1;
3811 }
3812
3813 *seg += sizeof(*psv_seg);
3814 *size += sizeof(*psv_seg) / 16;
3815
3816 return 0;
3817 }
3818
set_reg_wr(struct mlx5_ib_qp * qp,const struct ib_reg_wr * wr,void ** seg,int * size)3819 static int set_reg_wr(struct mlx5_ib_qp *qp,
3820 const struct ib_reg_wr *wr,
3821 void **seg, int *size)
3822 {
3823 struct mlx5_ib_mr *mr = to_mmr(wr->mr);
3824 struct mlx5_ib_pd *pd = to_mpd(qp->ibqp.pd);
3825
3826 if (unlikely(wr->wr.send_flags & IB_SEND_INLINE)) {
3827 mlx5_ib_warn(to_mdev(qp->ibqp.device),
3828 "Invalid IB_SEND_INLINE send flag\n");
3829 return -EINVAL;
3830 }
3831
3832 set_reg_umr_seg(*seg, mr);
3833 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
3834 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
3835 if (unlikely((*seg == qp->sq.qend)))
3836 *seg = mlx5_get_send_wqe(qp, 0);
3837
3838 set_reg_mkey_seg(*seg, mr, wr->key, wr->access);
3839 *seg += sizeof(struct mlx5_mkey_seg);
3840 *size += sizeof(struct mlx5_mkey_seg) / 16;
3841 if (unlikely((*seg == qp->sq.qend)))
3842 *seg = mlx5_get_send_wqe(qp, 0);
3843
3844 set_reg_data_seg(*seg, mr, pd);
3845 *seg += sizeof(struct mlx5_wqe_data_seg);
3846 *size += (sizeof(struct mlx5_wqe_data_seg) / 16);
3847
3848 return 0;
3849 }
3850
set_linv_wr(struct mlx5_ib_qp * qp,void ** seg,int * size)3851 static void set_linv_wr(struct mlx5_ib_qp *qp, void **seg, int *size)
3852 {
3853 set_linv_umr_seg(*seg);
3854 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
3855 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
3856 if (unlikely((*seg == qp->sq.qend)))
3857 *seg = mlx5_get_send_wqe(qp, 0);
3858 set_linv_mkey_seg(*seg);
3859 *seg += sizeof(struct mlx5_mkey_seg);
3860 *size += sizeof(struct mlx5_mkey_seg) / 16;
3861 if (unlikely((*seg == qp->sq.qend)))
3862 *seg = mlx5_get_send_wqe(qp, 0);
3863 }
3864
dump_wqe(struct mlx5_ib_qp * qp,int idx,int size_16)3865 static void dump_wqe(struct mlx5_ib_qp *qp, int idx, int size_16)
3866 {
3867 __be32 *p = NULL;
3868 int tidx = idx;
3869 int i, j;
3870
3871 pr_debug("dump wqe at %p\n", mlx5_get_send_wqe(qp, tidx));
3872 for (i = 0, j = 0; i < size_16 * 4; i += 4, j += 4) {
3873 if ((i & 0xf) == 0) {
3874 void *buf = mlx5_get_send_wqe(qp, tidx);
3875 tidx = (tidx + 1) & (qp->sq.wqe_cnt - 1);
3876 p = buf;
3877 j = 0;
3878 }
3879 pr_debug("%08x %08x %08x %08x\n", be32_to_cpu(p[j]),
3880 be32_to_cpu(p[j + 1]), be32_to_cpu(p[j + 2]),
3881 be32_to_cpu(p[j + 3]));
3882 }
3883 }
3884
get_fence(u8 fence,const struct ib_send_wr * wr)3885 static u8 get_fence(u8 fence, const struct ib_send_wr *wr)
3886 {
3887 if (unlikely(wr->opcode == IB_WR_LOCAL_INV &&
3888 wr->send_flags & IB_SEND_FENCE))
3889 return MLX5_FENCE_MODE_STRONG_ORDERING;
3890
3891 if (unlikely(fence)) {
3892 if (wr->send_flags & IB_SEND_FENCE)
3893 return MLX5_FENCE_MODE_SMALL_AND_FENCE;
3894 else
3895 return fence;
3896 } else if (unlikely(wr->send_flags & IB_SEND_FENCE)) {
3897 return MLX5_FENCE_MODE_FENCE;
3898 }
3899
3900 return 0;
3901 }
3902
begin_wqe(struct mlx5_ib_qp * qp,void ** seg,struct mlx5_wqe_ctrl_seg ** ctrl,const struct ib_send_wr * wr,unsigned * idx,int * size,int nreq,int send_flags)3903 static int begin_wqe(struct mlx5_ib_qp *qp, void **seg,
3904 struct mlx5_wqe_ctrl_seg **ctrl,
3905 const struct ib_send_wr *wr, unsigned *idx,
3906 int *size, int nreq, int send_flags)
3907 {
3908 if (unlikely(mlx5_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)))
3909 return -ENOMEM;
3910
3911 *idx = qp->sq.cur_post & (qp->sq.wqe_cnt - 1);
3912 *seg = mlx5_get_send_wqe(qp, *idx);
3913 *ctrl = *seg;
3914 *(uint32_t *)(*seg + 8) = 0;
3915 (*ctrl)->imm = send_ieth(wr);
3916 (*ctrl)->fm_ce_se = qp->sq_signal_bits |
3917 (send_flags & IB_SEND_SIGNALED ?
3918 MLX5_WQE_CTRL_CQ_UPDATE : 0) |
3919 (send_flags & IB_SEND_SOLICITED ?
3920 MLX5_WQE_CTRL_SOLICITED : 0);
3921
3922 *seg += sizeof(**ctrl);
3923 *size = sizeof(**ctrl) / 16;
3924
3925 return 0;
3926 }
3927
finish_wqe(struct mlx5_ib_qp * qp,struct mlx5_wqe_ctrl_seg * ctrl,u8 size,unsigned idx,u64 wr_id,int nreq,u8 fence,u8 next_fence,u32 mlx5_opcode)3928 static void finish_wqe(struct mlx5_ib_qp *qp,
3929 struct mlx5_wqe_ctrl_seg *ctrl,
3930 u8 size, unsigned idx, u64 wr_id,
3931 int nreq, u8 fence, u8 next_fence,
3932 u32 mlx5_opcode)
3933 {
3934 u8 opmod = 0;
3935
3936 ctrl->opmod_idx_opcode = cpu_to_be32(((u32)(qp->sq.cur_post) << 8) |
3937 mlx5_opcode | ((u32)opmod << 24));
3938 ctrl->qpn_ds = cpu_to_be32(size | (qp->trans_qp.base.mqp.qpn << 8));
3939 ctrl->fm_ce_se |= fence;
3940 qp->fm_cache = next_fence;
3941 if (unlikely(qp->wq_sig))
3942 ctrl->signature = wq_sig(ctrl);
3943
3944 qp->sq.wrid[idx] = wr_id;
3945 qp->sq.w_list[idx].opcode = mlx5_opcode;
3946 qp->sq.wqe_head[idx] = qp->sq.head + nreq;
3947 qp->sq.cur_post += DIV_ROUND_UP(size * 16, MLX5_SEND_WQE_BB);
3948 qp->sq.w_list[idx].next = qp->sq.cur_post;
3949 }
3950
3951
mlx5_ib_post_send(struct ib_qp * ibqp,const struct ib_send_wr * wr,const struct ib_send_wr ** bad_wr)3952 int mlx5_ib_post_send(struct ib_qp *ibqp, const struct ib_send_wr *wr,
3953 const struct ib_send_wr **bad_wr)
3954 {
3955 struct mlx5_wqe_ctrl_seg *ctrl = NULL; /* compiler warning */
3956 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
3957 struct mlx5_core_dev *mdev = dev->mdev;
3958 struct mlx5_ib_qp *qp;
3959 struct mlx5_ib_mr *mr;
3960 struct mlx5_wqe_data_seg *dpseg;
3961 struct mlx5_wqe_xrc_seg *xrc;
3962 struct mlx5_bf *bf;
3963 int uninitialized_var(size);
3964 void *qend;
3965 unsigned long flags;
3966 unsigned idx;
3967 int err = 0;
3968 int num_sge;
3969 void *seg;
3970 int nreq;
3971 int i;
3972 u8 next_fence = 0;
3973 u8 fence;
3974
3975 if (unlikely(ibqp->qp_type == IB_QPT_GSI))
3976 return mlx5_ib_gsi_post_send(ibqp, wr, bad_wr);
3977
3978 qp = to_mqp(ibqp);
3979 bf = &qp->bf;
3980 qend = qp->sq.qend;
3981
3982 spin_lock_irqsave(&qp->sq.lock, flags);
3983
3984 if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
3985 err = -EIO;
3986 *bad_wr = wr;
3987 nreq = 0;
3988 goto out;
3989 }
3990
3991 for (nreq = 0; wr; nreq++, wr = wr->next) {
3992 if (unlikely(wr->opcode < 0 || wr->opcode >= ARRAY_SIZE(mlx5_ib_opcode))) {
3993 mlx5_ib_warn(dev, "\n");
3994 err = -EINVAL;
3995 *bad_wr = wr;
3996 goto out;
3997 }
3998
3999 fence = qp->fm_cache;
4000 num_sge = wr->num_sge;
4001 if (unlikely(num_sge > qp->sq.max_gs)) {
4002 mlx5_ib_warn(dev, "\n");
4003 err = -EINVAL;
4004 *bad_wr = wr;
4005 goto out;
4006 }
4007
4008 err = begin_wqe(qp, &seg, &ctrl, wr, &idx, &size, nreq, wr->send_flags);
4009 if (err) {
4010 mlx5_ib_warn(dev, "\n");
4011 err = -ENOMEM;
4012 *bad_wr = wr;
4013 goto out;
4014 }
4015
4016 switch (ibqp->qp_type) {
4017 case IB_QPT_XRC_INI:
4018 xrc = seg;
4019 seg += sizeof(*xrc);
4020 size += sizeof(*xrc) / 16;
4021 /* fall through */
4022 case IB_QPT_RC:
4023 switch (wr->opcode) {
4024 case IB_WR_RDMA_READ:
4025 case IB_WR_RDMA_WRITE:
4026 case IB_WR_RDMA_WRITE_WITH_IMM:
4027 set_raddr_seg(seg, rdma_wr(wr)->remote_addr,
4028 rdma_wr(wr)->rkey);
4029 seg += sizeof(struct mlx5_wqe_raddr_seg);
4030 size += sizeof(struct mlx5_wqe_raddr_seg) / 16;
4031 break;
4032
4033 case IB_WR_ATOMIC_CMP_AND_SWP:
4034 case IB_WR_ATOMIC_FETCH_AND_ADD:
4035 case IB_WR_MASKED_ATOMIC_CMP_AND_SWP:
4036 mlx5_ib_warn(dev, "Atomic operations are not supported yet\n");
4037 err = -ENOSYS;
4038 *bad_wr = wr;
4039 goto out;
4040
4041 case IB_WR_LOCAL_INV:
4042 next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL;
4043 qp->sq.wr_data[idx] = IB_WR_LOCAL_INV;
4044 ctrl->imm = cpu_to_be32(wr->ex.invalidate_rkey);
4045 set_linv_wr(qp, &seg, &size);
4046 num_sge = 0;
4047 break;
4048
4049 case IB_WR_REG_MR:
4050 next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL;
4051 qp->sq.wr_data[idx] = IB_WR_REG_MR;
4052 ctrl->imm = cpu_to_be32(reg_wr(wr)->key);
4053 err = set_reg_wr(qp, reg_wr(wr), &seg, &size);
4054 if (err) {
4055 *bad_wr = wr;
4056 goto out;
4057 }
4058 num_sge = 0;
4059 break;
4060
4061 case IB_WR_REG_SIG_MR:
4062 qp->sq.wr_data[idx] = IB_WR_REG_SIG_MR;
4063 mr = to_mmr(sig_handover_wr(wr)->sig_mr);
4064
4065 ctrl->imm = cpu_to_be32(mr->ibmr.rkey);
4066 err = set_sig_umr_wr(wr, qp, &seg, &size);
4067 if (err) {
4068 mlx5_ib_warn(dev, "\n");
4069 *bad_wr = wr;
4070 goto out;
4071 }
4072
4073 finish_wqe(qp, ctrl, size, idx, wr->wr_id,
4074 nreq, get_fence(fence, wr),
4075 next_fence, MLX5_OPCODE_UMR);
4076 /*
4077 * SET_PSV WQEs are not signaled and solicited
4078 * on error
4079 */
4080 err = begin_wqe(qp, &seg, &ctrl, wr,
4081 &idx, &size, nreq, IB_SEND_SOLICITED);
4082 if (err) {
4083 mlx5_ib_warn(dev, "\n");
4084 err = -ENOMEM;
4085 *bad_wr = wr;
4086 goto out;
4087 }
4088
4089 err = set_psv_wr(&sig_handover_wr(wr)->sig_attrs->mem,
4090 mr->sig->psv_memory.psv_idx, &seg,
4091 &size);
4092 if (err) {
4093 mlx5_ib_warn(dev, "\n");
4094 *bad_wr = wr;
4095 goto out;
4096 }
4097
4098 finish_wqe(qp, ctrl, size, idx, wr->wr_id,
4099 nreq, get_fence(fence, wr),
4100 next_fence, MLX5_OPCODE_SET_PSV);
4101 err = begin_wqe(qp, &seg, &ctrl, wr,
4102 &idx, &size, nreq, wr->send_flags);
4103 if (err) {
4104 mlx5_ib_warn(dev, "\n");
4105 err = -ENOMEM;
4106 *bad_wr = wr;
4107 goto out;
4108 }
4109
4110 next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL;
4111 err = set_psv_wr(&sig_handover_wr(wr)->sig_attrs->wire,
4112 mr->sig->psv_wire.psv_idx, &seg,
4113 &size);
4114 if (err) {
4115 mlx5_ib_warn(dev, "\n");
4116 *bad_wr = wr;
4117 goto out;
4118 }
4119
4120 finish_wqe(qp, ctrl, size, idx, wr->wr_id,
4121 nreq, get_fence(fence, wr),
4122 next_fence, MLX5_OPCODE_SET_PSV);
4123 num_sge = 0;
4124 goto skip_psv;
4125
4126 default:
4127 break;
4128 }
4129 break;
4130
4131 case IB_QPT_UC:
4132 switch (wr->opcode) {
4133 case IB_WR_RDMA_WRITE:
4134 case IB_WR_RDMA_WRITE_WITH_IMM:
4135 set_raddr_seg(seg, rdma_wr(wr)->remote_addr,
4136 rdma_wr(wr)->rkey);
4137 seg += sizeof(struct mlx5_wqe_raddr_seg);
4138 size += sizeof(struct mlx5_wqe_raddr_seg) / 16;
4139 break;
4140
4141 default:
4142 break;
4143 }
4144 break;
4145
4146 case IB_QPT_SMI:
4147 case MLX5_IB_QPT_HW_GSI:
4148 set_datagram_seg(seg, wr);
4149 seg += sizeof(struct mlx5_wqe_datagram_seg);
4150 size += sizeof(struct mlx5_wqe_datagram_seg) / 16;
4151 if (unlikely((seg == qend)))
4152 seg = mlx5_get_send_wqe(qp, 0);
4153 break;
4154 case IB_QPT_UD:
4155 set_datagram_seg(seg, wr);
4156 seg += sizeof(struct mlx5_wqe_datagram_seg);
4157 size += sizeof(struct mlx5_wqe_datagram_seg) / 16;
4158
4159 if (unlikely((seg == qend)))
4160 seg = mlx5_get_send_wqe(qp, 0);
4161
4162 /* handle qp that supports ud offload */
4163 if (qp->flags & IB_QP_CREATE_IPOIB_UD_LSO) {
4164 struct mlx5_wqe_eth_pad *pad;
4165
4166 pad = seg;
4167 memset(pad, 0, sizeof(struct mlx5_wqe_eth_pad));
4168 seg += sizeof(struct mlx5_wqe_eth_pad);
4169 size += sizeof(struct mlx5_wqe_eth_pad) / 16;
4170
4171 seg = set_eth_seg(seg, wr, qend, qp, &size);
4172
4173 if (unlikely((seg == qend)))
4174 seg = mlx5_get_send_wqe(qp, 0);
4175 }
4176 break;
4177 case MLX5_IB_QPT_REG_UMR:
4178 if (wr->opcode != MLX5_IB_WR_UMR) {
4179 err = -EINVAL;
4180 mlx5_ib_warn(dev, "bad opcode\n");
4181 goto out;
4182 }
4183 qp->sq.wr_data[idx] = MLX5_IB_WR_UMR;
4184 ctrl->imm = cpu_to_be32(umr_wr(wr)->mkey);
4185 set_reg_umr_segment(seg, wr);
4186 seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
4187 size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
4188 if (unlikely((seg == qend)))
4189 seg = mlx5_get_send_wqe(qp, 0);
4190 set_reg_mkey_segment(seg, wr);
4191 seg += sizeof(struct mlx5_mkey_seg);
4192 size += sizeof(struct mlx5_mkey_seg) / 16;
4193 if (unlikely((seg == qend)))
4194 seg = mlx5_get_send_wqe(qp, 0);
4195 break;
4196
4197 default:
4198 break;
4199 }
4200
4201 if (wr->send_flags & IB_SEND_INLINE && num_sge) {
4202 int uninitialized_var(sz);
4203
4204 err = set_data_inl_seg(qp, wr, seg, &sz);
4205 if (unlikely(err)) {
4206 mlx5_ib_warn(dev, "\n");
4207 *bad_wr = wr;
4208 goto out;
4209 }
4210 size += sz;
4211 } else {
4212 dpseg = seg;
4213 for (i = 0; i < num_sge; i++) {
4214 if (unlikely(dpseg == qend)) {
4215 seg = mlx5_get_send_wqe(qp, 0);
4216 dpseg = seg;
4217 }
4218 if (likely(wr->sg_list[i].length)) {
4219 set_data_ptr_seg(dpseg, wr->sg_list + i);
4220 size += sizeof(struct mlx5_wqe_data_seg) / 16;
4221 dpseg++;
4222 }
4223 }
4224 }
4225
4226 finish_wqe(qp, ctrl, size, idx, wr->wr_id, nreq,
4227 get_fence(fence, wr), next_fence,
4228 mlx5_ib_opcode[wr->opcode]);
4229 skip_psv:
4230 if (0)
4231 dump_wqe(qp, idx, size);
4232 }
4233
4234 out:
4235 if (likely(nreq)) {
4236 qp->sq.head += nreq;
4237
4238 /* Make sure that descriptors are written before
4239 * updating doorbell record and ringing the doorbell
4240 */
4241 wmb();
4242
4243 qp->db.db[MLX5_SND_DBR] = cpu_to_be32(qp->sq.cur_post);
4244
4245 /* Make sure doorbell record is visible to the HCA before
4246 * we hit doorbell */
4247 wmb();
4248
4249 mlx5_write64((__be32 *)ctrl, bf->bfreg->map + bf->offset,
4250 MLX5_GET_DOORBELL_LOCK(&bf->lock32));
4251 /* Make sure doorbells don't leak out of SQ spinlock
4252 * and reach the HCA out of order.
4253 */
4254 bf->offset ^= bf->buf_size;
4255 }
4256
4257 spin_unlock_irqrestore(&qp->sq.lock, flags);
4258
4259 return err;
4260 }
4261
set_sig_seg(struct mlx5_rwqe_sig * sig,int size)4262 static void set_sig_seg(struct mlx5_rwqe_sig *sig, int size)
4263 {
4264 sig->signature = calc_sig(sig, size);
4265 }
4266
mlx5_ib_post_recv(struct ib_qp * ibqp,const struct ib_recv_wr * wr,const struct ib_recv_wr ** bad_wr)4267 int mlx5_ib_post_recv(struct ib_qp *ibqp, const struct ib_recv_wr *wr,
4268 const struct ib_recv_wr **bad_wr)
4269 {
4270 struct mlx5_ib_qp *qp = to_mqp(ibqp);
4271 struct mlx5_wqe_data_seg *scat;
4272 struct mlx5_rwqe_sig *sig;
4273 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
4274 struct mlx5_core_dev *mdev = dev->mdev;
4275 unsigned long flags;
4276 int err = 0;
4277 int nreq;
4278 int ind;
4279 int i;
4280
4281 if (unlikely(ibqp->qp_type == IB_QPT_GSI))
4282 return mlx5_ib_gsi_post_recv(ibqp, wr, bad_wr);
4283
4284 spin_lock_irqsave(&qp->rq.lock, flags);
4285
4286 if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
4287 err = -EIO;
4288 *bad_wr = wr;
4289 nreq = 0;
4290 goto out;
4291 }
4292
4293 ind = qp->rq.head & (qp->rq.wqe_cnt - 1);
4294
4295 for (nreq = 0; wr; nreq++, wr = wr->next) {
4296 if (mlx5_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
4297 err = -ENOMEM;
4298 *bad_wr = wr;
4299 goto out;
4300 }
4301
4302 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
4303 err = -EINVAL;
4304 *bad_wr = wr;
4305 goto out;
4306 }
4307
4308 scat = get_recv_wqe(qp, ind);
4309 if (qp->wq_sig)
4310 scat++;
4311
4312 for (i = 0; i < wr->num_sge; i++)
4313 set_data_ptr_seg(scat + i, wr->sg_list + i);
4314
4315 if (i < qp->rq.max_gs) {
4316 scat[i].byte_count = 0;
4317 scat[i].lkey = cpu_to_be32(MLX5_INVALID_LKEY);
4318 scat[i].addr = 0;
4319 }
4320
4321 if (qp->wq_sig) {
4322 sig = (struct mlx5_rwqe_sig *)scat;
4323 set_sig_seg(sig, (qp->rq.max_gs + 1) << 2);
4324 }
4325
4326 qp->rq.wrid[ind] = wr->wr_id;
4327
4328 ind = (ind + 1) & (qp->rq.wqe_cnt - 1);
4329 }
4330
4331 out:
4332 if (likely(nreq)) {
4333 qp->rq.head += nreq;
4334
4335 /* Make sure that descriptors are written before
4336 * doorbell record.
4337 */
4338 wmb();
4339
4340 *qp->db.db = cpu_to_be32(qp->rq.head & 0xffff);
4341 }
4342
4343 spin_unlock_irqrestore(&qp->rq.lock, flags);
4344
4345 return err;
4346 }
4347
to_ib_qp_state(enum mlx5_qp_state mlx5_state)4348 static inline enum ib_qp_state to_ib_qp_state(enum mlx5_qp_state mlx5_state)
4349 {
4350 switch (mlx5_state) {
4351 case MLX5_QP_STATE_RST: return IB_QPS_RESET;
4352 case MLX5_QP_STATE_INIT: return IB_QPS_INIT;
4353 case MLX5_QP_STATE_RTR: return IB_QPS_RTR;
4354 case MLX5_QP_STATE_RTS: return IB_QPS_RTS;
4355 case MLX5_QP_STATE_SQ_DRAINING:
4356 case MLX5_QP_STATE_SQD: return IB_QPS_SQD;
4357 case MLX5_QP_STATE_SQER: return IB_QPS_SQE;
4358 case MLX5_QP_STATE_ERR: return IB_QPS_ERR;
4359 default: return -1;
4360 }
4361 }
4362
to_ib_mig_state(int mlx5_mig_state)4363 static inline enum ib_mig_state to_ib_mig_state(int mlx5_mig_state)
4364 {
4365 switch (mlx5_mig_state) {
4366 case MLX5_QP_PM_ARMED: return IB_MIG_ARMED;
4367 case MLX5_QP_PM_REARM: return IB_MIG_REARM;
4368 case MLX5_QP_PM_MIGRATED: return IB_MIG_MIGRATED;
4369 default: return -1;
4370 }
4371 }
4372
to_ib_qp_access_flags(int mlx5_flags)4373 static int to_ib_qp_access_flags(int mlx5_flags)
4374 {
4375 int ib_flags = 0;
4376
4377 if (mlx5_flags & MLX5_QP_BIT_RRE)
4378 ib_flags |= IB_ACCESS_REMOTE_READ;
4379 if (mlx5_flags & MLX5_QP_BIT_RWE)
4380 ib_flags |= IB_ACCESS_REMOTE_WRITE;
4381 if (mlx5_flags & MLX5_QP_BIT_RAE)
4382 ib_flags |= IB_ACCESS_REMOTE_ATOMIC;
4383
4384 return ib_flags;
4385 }
4386
to_rdma_ah_attr(struct mlx5_ib_dev * ibdev,struct rdma_ah_attr * ah_attr,struct mlx5_qp_path * path)4387 static void to_rdma_ah_attr(struct mlx5_ib_dev *ibdev,
4388 struct rdma_ah_attr *ah_attr,
4389 struct mlx5_qp_path *path)
4390 {
4391 struct mlx5_core_dev *dev = ibdev->mdev;
4392
4393 memset(ah_attr, 0, sizeof(*ah_attr));
4394
4395 ah_attr->type = rdma_ah_find_type(&ibdev->ib_dev, path->port);
4396 rdma_ah_set_port_num(ah_attr, path->port);
4397 if (rdma_ah_get_port_num(ah_attr) == 0 ||
4398 rdma_ah_get_port_num(ah_attr) > MLX5_CAP_GEN(dev, num_ports))
4399 return;
4400
4401 rdma_ah_set_port_num(ah_attr, path->port);
4402 rdma_ah_set_sl(ah_attr, path->dci_cfi_prio_sl & 0xf);
4403
4404 rdma_ah_set_dlid(ah_attr, be16_to_cpu(path->rlid));
4405 rdma_ah_set_path_bits(ah_attr, path->grh_mlid & 0x7f);
4406 rdma_ah_set_static_rate(ah_attr,
4407 path->static_rate ? path->static_rate - 5 : 0);
4408 if (path->grh_mlid & (1 << 7)) {
4409 u32 tc_fl = be32_to_cpu(path->tclass_flowlabel);
4410
4411 rdma_ah_set_grh(ah_attr, NULL,
4412 tc_fl & 0xfffff,
4413 path->mgid_index,
4414 path->hop_limit,
4415 (tc_fl >> 20) & 0xff);
4416 rdma_ah_set_dgid_raw(ah_attr, path->rgid);
4417 }
4418 }
4419
query_raw_packet_qp_sq_state(struct mlx5_ib_dev * dev,struct mlx5_ib_sq * sq,u8 * sq_state)4420 static int query_raw_packet_qp_sq_state(struct mlx5_ib_dev *dev,
4421 struct mlx5_ib_sq *sq,
4422 u8 *sq_state)
4423 {
4424 void *out;
4425 void *sqc;
4426 int inlen;
4427 int err;
4428
4429 inlen = MLX5_ST_SZ_BYTES(query_sq_out);
4430 out = mlx5_vzalloc(inlen);
4431 if (!out)
4432 return -ENOMEM;
4433
4434 err = mlx5_core_query_sq(dev->mdev, sq->base.mqp.qpn, out);
4435 if (err)
4436 goto out;
4437
4438 sqc = MLX5_ADDR_OF(query_sq_out, out, sq_context);
4439 *sq_state = MLX5_GET(sqc, sqc, state);
4440 sq->state = *sq_state;
4441
4442 out:
4443 kvfree(out);
4444 return err;
4445 }
4446
query_raw_packet_qp_rq_state(struct mlx5_ib_dev * dev,struct mlx5_ib_rq * rq,u8 * rq_state)4447 static int query_raw_packet_qp_rq_state(struct mlx5_ib_dev *dev,
4448 struct mlx5_ib_rq *rq,
4449 u8 *rq_state)
4450 {
4451 void *out;
4452 void *rqc;
4453 int inlen;
4454 int err;
4455
4456 inlen = MLX5_ST_SZ_BYTES(query_rq_out);
4457 out = mlx5_vzalloc(inlen);
4458 if (!out)
4459 return -ENOMEM;
4460
4461 err = mlx5_core_query_rq(dev->mdev, rq->base.mqp.qpn, out);
4462 if (err)
4463 goto out;
4464
4465 rqc = MLX5_ADDR_OF(query_rq_out, out, rq_context);
4466 *rq_state = MLX5_GET(rqc, rqc, state);
4467 rq->state = *rq_state;
4468
4469 out:
4470 kvfree(out);
4471 return err;
4472 }
4473
sqrq_state_to_qp_state(u8 sq_state,u8 rq_state,struct mlx5_ib_qp * qp,u8 * qp_state)4474 static int sqrq_state_to_qp_state(u8 sq_state, u8 rq_state,
4475 struct mlx5_ib_qp *qp, u8 *qp_state)
4476 {
4477 static const u8 sqrq_trans[MLX5_RQ_NUM_STATE][MLX5_SQ_NUM_STATE] = {
4478 [MLX5_RQC_STATE_RST] = {
4479 [MLX5_SQC_STATE_RST] = IB_QPS_RESET,
4480 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE_BAD,
4481 [MLX5_SQC_STATE_ERR] = MLX5_QP_STATE_BAD,
4482 [MLX5_SQ_STATE_NA] = IB_QPS_RESET,
4483 },
4484 [MLX5_RQC_STATE_RDY] = {
4485 [MLX5_SQC_STATE_RST] = MLX5_QP_STATE_BAD,
4486 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE,
4487 [MLX5_SQC_STATE_ERR] = IB_QPS_SQE,
4488 [MLX5_SQ_STATE_NA] = MLX5_QP_STATE,
4489 },
4490 [MLX5_RQC_STATE_ERR] = {
4491 [MLX5_SQC_STATE_RST] = MLX5_QP_STATE_BAD,
4492 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE_BAD,
4493 [MLX5_SQC_STATE_ERR] = IB_QPS_ERR,
4494 [MLX5_SQ_STATE_NA] = IB_QPS_ERR,
4495 },
4496 [MLX5_RQ_STATE_NA] = {
4497 [MLX5_SQC_STATE_RST] = IB_QPS_RESET,
4498 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE,
4499 [MLX5_SQC_STATE_ERR] = MLX5_QP_STATE,
4500 [MLX5_SQ_STATE_NA] = MLX5_QP_STATE_BAD,
4501 },
4502 };
4503
4504 *qp_state = sqrq_trans[rq_state][sq_state];
4505
4506 if (*qp_state == MLX5_QP_STATE_BAD) {
4507 WARN(1, "Buggy Raw Packet QP state, SQ 0x%x state: 0x%x, RQ 0x%x state: 0x%x",
4508 qp->raw_packet_qp.sq.base.mqp.qpn, sq_state,
4509 qp->raw_packet_qp.rq.base.mqp.qpn, rq_state);
4510 return -EINVAL;
4511 }
4512
4513 if (*qp_state == MLX5_QP_STATE)
4514 *qp_state = qp->state;
4515
4516 return 0;
4517 }
4518
query_raw_packet_qp_state(struct mlx5_ib_dev * dev,struct mlx5_ib_qp * qp,u8 * raw_packet_qp_state)4519 static int query_raw_packet_qp_state(struct mlx5_ib_dev *dev,
4520 struct mlx5_ib_qp *qp,
4521 u8 *raw_packet_qp_state)
4522 {
4523 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
4524 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
4525 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
4526 int err;
4527 u8 sq_state = MLX5_SQ_STATE_NA;
4528 u8 rq_state = MLX5_RQ_STATE_NA;
4529
4530 if (qp->sq.wqe_cnt) {
4531 err = query_raw_packet_qp_sq_state(dev, sq, &sq_state);
4532 if (err)
4533 return err;
4534 }
4535
4536 if (qp->rq.wqe_cnt) {
4537 err = query_raw_packet_qp_rq_state(dev, rq, &rq_state);
4538 if (err)
4539 return err;
4540 }
4541
4542 return sqrq_state_to_qp_state(sq_state, rq_state, qp,
4543 raw_packet_qp_state);
4544 }
4545
query_qp_attr(struct mlx5_ib_dev * dev,struct mlx5_ib_qp * qp,struct ib_qp_attr * qp_attr)4546 static int query_qp_attr(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
4547 struct ib_qp_attr *qp_attr)
4548 {
4549 int outlen = MLX5_ST_SZ_BYTES(query_qp_out);
4550 struct mlx5_qp_context *context;
4551 int mlx5_state;
4552 u32 *outb;
4553 int err = 0;
4554
4555 outb = kzalloc(outlen, GFP_KERNEL);
4556 if (!outb)
4557 return -ENOMEM;
4558
4559 err = mlx5_core_qp_query(dev->mdev, &qp->trans_qp.base.mqp, outb,
4560 outlen);
4561 if (err)
4562 goto out;
4563
4564 /* FIXME: use MLX5_GET rather than mlx5_qp_context manual struct */
4565 context = (struct mlx5_qp_context *)MLX5_ADDR_OF(query_qp_out, outb, qpc);
4566
4567 mlx5_state = be32_to_cpu(context->flags) >> 28;
4568
4569 qp->state = to_ib_qp_state(mlx5_state);
4570 qp_attr->path_mtu = context->mtu_msgmax >> 5;
4571 qp_attr->path_mig_state =
4572 to_ib_mig_state((be32_to_cpu(context->flags) >> 11) & 0x3);
4573 qp_attr->qkey = be32_to_cpu(context->qkey);
4574 qp_attr->rq_psn = be32_to_cpu(context->rnr_nextrecvpsn) & 0xffffff;
4575 qp_attr->sq_psn = be32_to_cpu(context->next_send_psn) & 0xffffff;
4576 qp_attr->dest_qp_num = be32_to_cpu(context->log_pg_sz_remote_qpn) & 0xffffff;
4577 qp_attr->qp_access_flags =
4578 to_ib_qp_access_flags(be32_to_cpu(context->params2));
4579
4580 if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC) {
4581 to_rdma_ah_attr(dev, &qp_attr->ah_attr, &context->pri_path);
4582 to_rdma_ah_attr(dev, &qp_attr->alt_ah_attr, &context->alt_path);
4583 qp_attr->alt_pkey_index =
4584 be16_to_cpu(context->alt_path.pkey_index);
4585 qp_attr->alt_port_num =
4586 rdma_ah_get_port_num(&qp_attr->alt_ah_attr);
4587 }
4588
4589 qp_attr->pkey_index = be16_to_cpu(context->pri_path.pkey_index);
4590 qp_attr->port_num = context->pri_path.port;
4591
4592 /* qp_attr->en_sqd_async_notify is only applicable in modify qp */
4593 qp_attr->sq_draining = mlx5_state == MLX5_QP_STATE_SQ_DRAINING;
4594
4595 qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context->params1) >> 21) & 0x7);
4596
4597 qp_attr->max_dest_rd_atomic =
4598 1 << ((be32_to_cpu(context->params2) >> 21) & 0x7);
4599 qp_attr->min_rnr_timer =
4600 (be32_to_cpu(context->rnr_nextrecvpsn) >> 24) & 0x1f;
4601 qp_attr->timeout = context->pri_path.ackto_lt >> 3;
4602 qp_attr->retry_cnt = (be32_to_cpu(context->params1) >> 16) & 0x7;
4603 qp_attr->rnr_retry = (be32_to_cpu(context->params1) >> 13) & 0x7;
4604 qp_attr->alt_timeout = context->alt_path.ackto_lt >> 3;
4605
4606 out:
4607 kfree(outb);
4608 return err;
4609 }
4610
mlx5_ib_query_qp(struct ib_qp * ibqp,struct ib_qp_attr * qp_attr,int qp_attr_mask,struct ib_qp_init_attr * qp_init_attr)4611 int mlx5_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr,
4612 int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr)
4613 {
4614 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
4615 struct mlx5_ib_qp *qp = to_mqp(ibqp);
4616 int err = 0;
4617 u8 raw_packet_qp_state;
4618
4619 if (ibqp->rwq_ind_tbl)
4620 return -ENOSYS;
4621
4622 if (unlikely(ibqp->qp_type == IB_QPT_GSI))
4623 return mlx5_ib_gsi_query_qp(ibqp, qp_attr, qp_attr_mask,
4624 qp_init_attr);
4625
4626 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
4627 /*
4628 * Wait for any outstanding page faults, in case the user frees memory
4629 * based upon this query's result.
4630 */
4631 flush_workqueue(mlx5_ib_page_fault_wq);
4632 #endif
4633
4634 mutex_lock(&qp->mutex);
4635
4636 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET) {
4637 err = query_raw_packet_qp_state(dev, qp, &raw_packet_qp_state);
4638 if (err)
4639 goto out;
4640 qp->state = raw_packet_qp_state;
4641 qp_attr->port_num = 1;
4642 } else {
4643 err = query_qp_attr(dev, qp, qp_attr);
4644 if (err)
4645 goto out;
4646 }
4647
4648 qp_attr->qp_state = qp->state;
4649 qp_attr->cur_qp_state = qp_attr->qp_state;
4650 qp_attr->cap.max_recv_wr = qp->rq.wqe_cnt;
4651 qp_attr->cap.max_recv_sge = qp->rq.max_gs;
4652
4653 if (!ibqp->uobject) {
4654 qp_attr->cap.max_send_wr = qp->sq.max_post;
4655 qp_attr->cap.max_send_sge = qp->sq.max_gs;
4656 qp_init_attr->qp_context = ibqp->qp_context;
4657 } else {
4658 qp_attr->cap.max_send_wr = 0;
4659 qp_attr->cap.max_send_sge = 0;
4660 }
4661
4662 qp_init_attr->qp_type = ibqp->qp_type;
4663 qp_init_attr->recv_cq = ibqp->recv_cq;
4664 qp_init_attr->send_cq = ibqp->send_cq;
4665 qp_init_attr->srq = ibqp->srq;
4666 qp_attr->cap.max_inline_data = qp->max_inline_data;
4667
4668 qp_init_attr->cap = qp_attr->cap;
4669
4670 qp_init_attr->create_flags = 0;
4671 if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK)
4672 qp_init_attr->create_flags |= IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK;
4673
4674 if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL)
4675 qp_init_attr->create_flags |= IB_QP_CREATE_CROSS_CHANNEL;
4676 if (qp->flags & MLX5_IB_QP_MANAGED_SEND)
4677 qp_init_attr->create_flags |= IB_QP_CREATE_MANAGED_SEND;
4678 if (qp->flags & MLX5_IB_QP_MANAGED_RECV)
4679 qp_init_attr->create_flags |= IB_QP_CREATE_MANAGED_RECV;
4680 if (qp->flags & MLX5_IB_QP_SQPN_QP1)
4681 qp_init_attr->create_flags |= MLX5_IB_QP_CREATE_SQPN_QP1;
4682
4683 qp_init_attr->sq_sig_type = qp->sq_signal_bits & MLX5_WQE_CTRL_CQ_UPDATE ?
4684 IB_SIGNAL_ALL_WR : IB_SIGNAL_REQ_WR;
4685
4686 out:
4687 mutex_unlock(&qp->mutex);
4688 return err;
4689 }
4690
mlx5_ib_alloc_xrcd(struct ib_device * ibdev,struct ib_udata * udata)4691 struct ib_xrcd *mlx5_ib_alloc_xrcd(struct ib_device *ibdev,
4692 struct ib_udata *udata)
4693 {
4694 struct mlx5_ib_dev *dev = to_mdev(ibdev);
4695 struct mlx5_ib_xrcd *xrcd;
4696 int err;
4697
4698 if (!MLX5_CAP_GEN(dev->mdev, xrc))
4699 return ERR_PTR(-ENOSYS);
4700
4701 xrcd = kmalloc(sizeof(*xrcd), GFP_KERNEL);
4702 if (!xrcd)
4703 return ERR_PTR(-ENOMEM);
4704
4705 err = mlx5_core_xrcd_alloc(dev->mdev, &xrcd->xrcdn);
4706 if (err) {
4707 kfree(xrcd);
4708 return ERR_PTR(-ENOMEM);
4709 }
4710
4711 return &xrcd->ibxrcd;
4712 }
4713
mlx5_ib_dealloc_xrcd(struct ib_xrcd * xrcd,struct ib_udata * udata)4714 int mlx5_ib_dealloc_xrcd(struct ib_xrcd *xrcd, struct ib_udata *udata)
4715 {
4716 struct mlx5_ib_dev *dev = to_mdev(xrcd->device);
4717 u32 xrcdn = to_mxrcd(xrcd)->xrcdn;
4718 int err;
4719
4720 err = mlx5_core_xrcd_dealloc(dev->mdev, xrcdn);
4721 if (err)
4722 mlx5_ib_warn(dev, "failed to dealloc xrcdn 0x%x\n", xrcdn);
4723
4724 kfree(xrcd);
4725 return 0;
4726 }
4727
mlx5_ib_wq_event(struct mlx5_core_qp * core_qp,int type)4728 static void mlx5_ib_wq_event(struct mlx5_core_qp *core_qp, int type)
4729 {
4730 struct mlx5_ib_rwq *rwq = to_mibrwq(core_qp);
4731 struct mlx5_ib_dev *dev = to_mdev(rwq->ibwq.device);
4732 struct ib_event event;
4733
4734 if (rwq->ibwq.event_handler) {
4735 event.device = rwq->ibwq.device;
4736 event.element.wq = &rwq->ibwq;
4737 switch (type) {
4738 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR:
4739 event.event = IB_EVENT_WQ_FATAL;
4740 break;
4741 default:
4742 mlx5_ib_warn(dev, "Unexpected event type %d on WQ %06x\n", type, core_qp->qpn);
4743 return;
4744 }
4745
4746 rwq->ibwq.event_handler(&event, rwq->ibwq.wq_context);
4747 }
4748 }
4749
create_rq(struct mlx5_ib_rwq * rwq,struct ib_pd * pd,struct ib_wq_init_attr * init_attr)4750 static int create_rq(struct mlx5_ib_rwq *rwq, struct ib_pd *pd,
4751 struct ib_wq_init_attr *init_attr)
4752 {
4753 struct mlx5_ib_dev *dev;
4754 int has_net_offloads;
4755 __be64 *rq_pas0;
4756 void *in;
4757 void *rqc;
4758 void *wq;
4759 int inlen;
4760 int err;
4761
4762 dev = to_mdev(pd->device);
4763
4764 inlen = MLX5_ST_SZ_BYTES(create_rq_in) + sizeof(u64) * rwq->rq_num_pas;
4765 in = mlx5_vzalloc(inlen);
4766 if (!in)
4767 return -ENOMEM;
4768
4769 MLX5_SET(create_rq_in, in, uid, to_mpd(pd)->uid);
4770 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
4771 MLX5_SET(rqc, rqc, mem_rq_type,
4772 MLX5_RQC_RQ_TYPE_MEMORY_RQ_INLINE);
4773 MLX5_SET(rqc, rqc, user_index, rwq->user_index);
4774 MLX5_SET(rqc, rqc, cqn, to_mcq(init_attr->cq)->mcq.cqn);
4775 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
4776 MLX5_SET(rqc, rqc, flush_in_error_en, 1);
4777 wq = MLX5_ADDR_OF(rqc, rqc, wq);
4778 MLX5_SET(wq, wq, wq_type,
4779 rwq->create_flags & MLX5_IB_WQ_FLAGS_STRIDING_RQ ?
4780 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ : MLX5_WQ_TYPE_CYCLIC);
4781 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
4782 MLX5_SET(wq, wq, log_wq_stride, rwq->log_rq_stride);
4783 if (rwq->create_flags & MLX5_IB_WQ_FLAGS_STRIDING_RQ) {
4784 MLX5_SET(wq, wq, two_byte_shift_en, rwq->two_byte_shift_en);
4785 MLX5_SET(wq, wq, single_stride_log_num_of_bytes,
4786 rwq->single_stride_log_num_of_bytes -
4787 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES);
4788 MLX5_SET(wq, wq, single_wqe_log_num_of_strides,
4789 rwq->log_num_strides -
4790 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES);
4791 }
4792 MLX5_SET(wq, wq, log_wq_sz, rwq->log_rq_size);
4793 MLX5_SET(wq, wq, pd, to_mpd(pd)->pdn);
4794 MLX5_SET(wq, wq, page_offset, rwq->rq_page_offset);
4795 MLX5_SET(wq, wq, log_wq_pg_sz, rwq->log_page_size);
4796 MLX5_SET(wq, wq, wq_signature, rwq->wq_sig);
4797 MLX5_SET64(wq, wq, dbr_addr, rwq->db.dma);
4798 has_net_offloads = MLX5_CAP_GEN(dev->mdev, eth_net_offloads);
4799 if (init_attr->create_flags & IB_WQ_FLAGS_CVLAN_STRIPPING) {
4800 if (!(has_net_offloads && MLX5_CAP_ETH(dev->mdev, vlan_cap))) {
4801 mlx5_ib_dbg(dev, "VLAN offloads are not supported\n");
4802 err = -EOPNOTSUPP;
4803 goto out;
4804 }
4805 } else {
4806 MLX5_SET(rqc, rqc, vlan_strip_disable, 1);
4807 }
4808 if (init_attr->create_flags & IB_WQ_FLAGS_SCATTER_FCS) {
4809 if (!(has_net_offloads && MLX5_CAP_ETH(dev->mdev, scatter_fcs))) {
4810 mlx5_ib_dbg(dev, "Scatter FCS is not supported\n");
4811 err = -EOPNOTSUPP;
4812 goto out;
4813 }
4814 MLX5_SET(rqc, rqc, scatter_fcs, 1);
4815 }
4816 rq_pas0 = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
4817 mlx5_ib_populate_pas(dev, rwq->umem, rwq->page_shift, rq_pas0, 0);
4818 err = mlx5_core_create_rq_tracked(dev->mdev, in, inlen, &rwq->core_qp);
4819 out:
4820 kvfree(in);
4821 return err;
4822 }
4823
set_user_rq_size(struct mlx5_ib_dev * dev,struct ib_wq_init_attr * wq_init_attr,struct mlx5_ib_create_wq * ucmd,struct mlx5_ib_rwq * rwq)4824 static int set_user_rq_size(struct mlx5_ib_dev *dev,
4825 struct ib_wq_init_attr *wq_init_attr,
4826 struct mlx5_ib_create_wq *ucmd,
4827 struct mlx5_ib_rwq *rwq)
4828 {
4829 /* Sanity check RQ size before proceeding */
4830 if (wq_init_attr->max_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_wq_sz)))
4831 return -EINVAL;
4832
4833 if (!ucmd->rq_wqe_count)
4834 return -EINVAL;
4835
4836 rwq->wqe_count = ucmd->rq_wqe_count;
4837 rwq->wqe_shift = ucmd->rq_wqe_shift;
4838 rwq->buf_size = (rwq->wqe_count << rwq->wqe_shift);
4839 rwq->log_rq_stride = rwq->wqe_shift;
4840 rwq->log_rq_size = ilog2(rwq->wqe_count);
4841 return 0;
4842 }
4843
prepare_user_rq(struct ib_pd * pd,struct ib_wq_init_attr * init_attr,struct ib_udata * udata,struct mlx5_ib_rwq * rwq)4844 static int prepare_user_rq(struct ib_pd *pd,
4845 struct ib_wq_init_attr *init_attr,
4846 struct ib_udata *udata,
4847 struct mlx5_ib_rwq *rwq)
4848 {
4849 struct mlx5_ib_dev *dev = to_mdev(pd->device);
4850 struct mlx5_ib_create_wq ucmd = {};
4851 int err;
4852 size_t required_cmd_sz;
4853
4854 required_cmd_sz = offsetof(typeof(ucmd), single_stride_log_num_of_bytes)
4855 + sizeof(ucmd.single_stride_log_num_of_bytes);
4856 if (udata->inlen < required_cmd_sz) {
4857 mlx5_ib_dbg(dev, "invalid inlen\n");
4858 return -EINVAL;
4859 }
4860
4861 if (udata->inlen > sizeof(ucmd) &&
4862 !ib_is_udata_cleared(udata, sizeof(ucmd),
4863 udata->inlen - sizeof(ucmd))) {
4864 mlx5_ib_dbg(dev, "inlen is not supported\n");
4865 return -EOPNOTSUPP;
4866 }
4867
4868 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) {
4869 mlx5_ib_dbg(dev, "copy failed\n");
4870 return -EFAULT;
4871 }
4872
4873 if (ucmd.comp_mask & (~MLX5_IB_CREATE_WQ_STRIDING_RQ)) {
4874 mlx5_ib_dbg(dev, "invalid comp mask\n");
4875 return -EOPNOTSUPP;
4876 } else if (ucmd.comp_mask & MLX5_IB_CREATE_WQ_STRIDING_RQ) {
4877 if (!MLX5_CAP_GEN(dev->mdev, striding_rq)) {
4878 mlx5_ib_dbg(dev, "Striding RQ is not supported\n");
4879 return -EOPNOTSUPP;
4880 }
4881 if ((ucmd.single_stride_log_num_of_bytes <
4882 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES) ||
4883 (ucmd.single_stride_log_num_of_bytes >
4884 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES)) {
4885 mlx5_ib_dbg(dev, "Invalid log stride size (%u. Range is %u - %u)\n",
4886 ucmd.single_stride_log_num_of_bytes,
4887 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES,
4888 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES);
4889 return -EINVAL;
4890 }
4891 if ((ucmd.single_wqe_log_num_of_strides >
4892 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES) ||
4893 (ucmd.single_wqe_log_num_of_strides <
4894 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES)) {
4895 mlx5_ib_dbg(dev, "Invalid log num strides (%u. Range is %u - %u)\n",
4896 ucmd.single_wqe_log_num_of_strides,
4897 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES,
4898 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES);
4899 return -EINVAL;
4900 }
4901 rwq->single_stride_log_num_of_bytes =
4902 ucmd.single_stride_log_num_of_bytes;
4903 rwq->log_num_strides = ucmd.single_wqe_log_num_of_strides;
4904 rwq->two_byte_shift_en = !!ucmd.two_byte_shift_en;
4905 rwq->create_flags |= MLX5_IB_WQ_FLAGS_STRIDING_RQ;
4906 }
4907
4908 err = set_user_rq_size(dev, init_attr, &ucmd, rwq);
4909 if (err) {
4910 mlx5_ib_dbg(dev, "err %d\n", err);
4911 return err;
4912 }
4913
4914 err = create_user_rq(dev, pd, rwq, &ucmd);
4915 if (err) {
4916 mlx5_ib_dbg(dev, "err %d\n", err);
4917 if (err)
4918 return err;
4919 }
4920
4921 rwq->user_index = ucmd.user_index;
4922 return 0;
4923 }
4924
mlx5_ib_create_wq(struct ib_pd * pd,struct ib_wq_init_attr * init_attr,struct ib_udata * udata)4925 struct ib_wq *mlx5_ib_create_wq(struct ib_pd *pd,
4926 struct ib_wq_init_attr *init_attr,
4927 struct ib_udata *udata)
4928 {
4929 struct mlx5_ib_dev *dev;
4930 struct mlx5_ib_rwq *rwq;
4931 struct mlx5_ib_create_wq_resp resp = {};
4932 size_t min_resp_len;
4933 int err;
4934
4935 if (!udata)
4936 return ERR_PTR(-ENOSYS);
4937
4938 min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved);
4939 if (udata->outlen && udata->outlen < min_resp_len)
4940 return ERR_PTR(-EINVAL);
4941
4942 dev = to_mdev(pd->device);
4943 switch (init_attr->wq_type) {
4944 case IB_WQT_RQ:
4945 rwq = kzalloc(sizeof(*rwq), GFP_KERNEL);
4946 if (!rwq)
4947 return ERR_PTR(-ENOMEM);
4948 err = prepare_user_rq(pd, init_attr, udata, rwq);
4949 if (err)
4950 goto err;
4951 err = create_rq(rwq, pd, init_attr);
4952 if (err)
4953 goto err_user_rq;
4954 break;
4955 default:
4956 mlx5_ib_dbg(dev, "unsupported wq type %d\n",
4957 init_attr->wq_type);
4958 return ERR_PTR(-EINVAL);
4959 }
4960
4961 rwq->ibwq.wq_num = rwq->core_qp.qpn;
4962 rwq->ibwq.state = IB_WQS_RESET;
4963 if (udata->outlen) {
4964 resp.response_length = offsetof(typeof(resp), response_length) +
4965 sizeof(resp.response_length);
4966 err = ib_copy_to_udata(udata, &resp, resp.response_length);
4967 if (err)
4968 goto err_copy;
4969 }
4970
4971 rwq->core_qp.event = mlx5_ib_wq_event;
4972 rwq->ibwq.event_handler = init_attr->event_handler;
4973 return &rwq->ibwq;
4974
4975 err_copy:
4976 mlx5_core_destroy_rq_tracked(dev->mdev, &rwq->core_qp);
4977 err_user_rq:
4978 destroy_user_rq(pd, rwq, udata);
4979 err:
4980 kfree(rwq);
4981 return ERR_PTR(err);
4982 }
4983
mlx5_ib_destroy_wq(struct ib_wq * wq,struct ib_udata * udata)4984 void mlx5_ib_destroy_wq(struct ib_wq *wq, struct ib_udata *udata)
4985 {
4986 struct mlx5_ib_dev *dev = to_mdev(wq->device);
4987 struct mlx5_ib_rwq *rwq = to_mrwq(wq);
4988
4989 mlx5_core_destroy_rq_tracked(dev->mdev, &rwq->core_qp);
4990 destroy_user_rq(wq->pd, rwq, udata);
4991 kfree(rwq);
4992 }
4993
mlx5_ib_create_rwq_ind_table(struct ib_device * device,struct ib_rwq_ind_table_init_attr * init_attr,struct ib_udata * udata)4994 struct ib_rwq_ind_table *mlx5_ib_create_rwq_ind_table(struct ib_device *device,
4995 struct ib_rwq_ind_table_init_attr *init_attr,
4996 struct ib_udata *udata)
4997 {
4998 struct mlx5_ib_dev *dev = to_mdev(device);
4999 struct mlx5_ib_rwq_ind_table *rwq_ind_tbl;
5000 int sz = 1 << init_attr->log_ind_tbl_size;
5001 struct mlx5_ib_create_rwq_ind_tbl_resp resp = {};
5002 size_t min_resp_len;
5003 int inlen;
5004 int err;
5005 int i;
5006 u32 *in;
5007 void *rqtc;
5008
5009 if (udata->inlen > 0 &&
5010 !ib_is_udata_cleared(udata, 0,
5011 udata->inlen))
5012 return ERR_PTR(-EOPNOTSUPP);
5013
5014 if (init_attr->log_ind_tbl_size >
5015 MLX5_CAP_GEN(dev->mdev, log_max_rqt_size)) {
5016 mlx5_ib_dbg(dev, "log_ind_tbl_size = %d is bigger than supported = %d\n",
5017 init_attr->log_ind_tbl_size,
5018 MLX5_CAP_GEN(dev->mdev, log_max_rqt_size));
5019 return ERR_PTR(-EINVAL);
5020 }
5021
5022 min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved);
5023 if (udata->outlen && udata->outlen < min_resp_len)
5024 return ERR_PTR(-EINVAL);
5025
5026 rwq_ind_tbl = kzalloc(sizeof(*rwq_ind_tbl), GFP_KERNEL);
5027 if (!rwq_ind_tbl)
5028 return ERR_PTR(-ENOMEM);
5029
5030 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
5031 in = mlx5_vzalloc(inlen);
5032 if (!in) {
5033 err = -ENOMEM;
5034 goto err;
5035 }
5036
5037 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
5038
5039 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
5040 MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
5041
5042 for (i = 0; i < sz; i++)
5043 MLX5_SET(rqtc, rqtc, rq_num[i], init_attr->ind_tbl[i]->wq_num);
5044
5045 rwq_ind_tbl->uid = to_mpd(init_attr->ind_tbl[0]->pd)->uid;
5046 MLX5_SET(create_rqt_in, in, uid, rwq_ind_tbl->uid);
5047
5048 err = mlx5_core_create_rqt(dev->mdev, in, inlen, &rwq_ind_tbl->rqtn);
5049 kvfree(in);
5050
5051 if (err)
5052 goto err;
5053
5054 rwq_ind_tbl->ib_rwq_ind_tbl.ind_tbl_num = rwq_ind_tbl->rqtn;
5055 if (udata->outlen) {
5056 resp.response_length = offsetof(typeof(resp), response_length) +
5057 sizeof(resp.response_length);
5058 err = ib_copy_to_udata(udata, &resp, resp.response_length);
5059 if (err)
5060 goto err_copy;
5061 }
5062
5063 return &rwq_ind_tbl->ib_rwq_ind_tbl;
5064
5065 err_copy:
5066 mlx5_core_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn, rwq_ind_tbl->uid);
5067 err:
5068 kfree(rwq_ind_tbl);
5069 return ERR_PTR(err);
5070 }
5071
mlx5_ib_destroy_rwq_ind_table(struct ib_rwq_ind_table * ib_rwq_ind_tbl)5072 int mlx5_ib_destroy_rwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_tbl)
5073 {
5074 struct mlx5_ib_rwq_ind_table *rwq_ind_tbl = to_mrwq_ind_table(ib_rwq_ind_tbl);
5075 struct mlx5_ib_dev *dev = to_mdev(ib_rwq_ind_tbl->device);
5076
5077 mlx5_core_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn, rwq_ind_tbl->uid);
5078
5079 kfree(rwq_ind_tbl);
5080 return 0;
5081 }
5082
mlx5_ib_modify_wq(struct ib_wq * wq,struct ib_wq_attr * wq_attr,u32 wq_attr_mask,struct ib_udata * udata)5083 int mlx5_ib_modify_wq(struct ib_wq *wq, struct ib_wq_attr *wq_attr,
5084 u32 wq_attr_mask, struct ib_udata *udata)
5085 {
5086 struct mlx5_ib_dev *dev = to_mdev(wq->device);
5087 struct mlx5_ib_rwq *rwq = to_mrwq(wq);
5088 struct mlx5_ib_modify_wq ucmd = {};
5089 size_t required_cmd_sz;
5090 int curr_wq_state;
5091 int wq_state;
5092 int inlen;
5093 int err;
5094 void *rqc;
5095 void *in;
5096
5097 required_cmd_sz = offsetof(typeof(ucmd), reserved) + sizeof(ucmd.reserved);
5098 if (udata->inlen < required_cmd_sz)
5099 return -EINVAL;
5100
5101 if (udata->inlen > sizeof(ucmd) &&
5102 !ib_is_udata_cleared(udata, sizeof(ucmd),
5103 udata->inlen - sizeof(ucmd)))
5104 return -EOPNOTSUPP;
5105
5106 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen)))
5107 return -EFAULT;
5108
5109 if (ucmd.comp_mask || ucmd.reserved)
5110 return -EOPNOTSUPP;
5111
5112 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
5113 in = mlx5_vzalloc(inlen);
5114 if (!in)
5115 return -ENOMEM;
5116
5117 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
5118
5119 MLX5_SET(modify_rq_in, in, rqn, rwq->core_qp.qpn);
5120 curr_wq_state = (wq_attr_mask & IB_WQ_CUR_STATE) ?
5121 wq_attr->curr_wq_state : wq->state;
5122 wq_state = (wq_attr_mask & IB_WQ_STATE) ?
5123 wq_attr->wq_state : curr_wq_state;
5124 if (curr_wq_state == IB_WQS_ERR)
5125 curr_wq_state = MLX5_RQC_STATE_ERR;
5126 if (wq_state == IB_WQS_ERR)
5127 wq_state = MLX5_RQC_STATE_ERR;
5128 MLX5_SET(modify_rq_in, in, rq_state, curr_wq_state);
5129 MLX5_SET(modify_rq_in, in, uid, to_mpd(wq->pd)->uid);
5130 MLX5_SET(rqc, rqc, state, wq_state);
5131
5132 if (wq_attr_mask & IB_WQ_FLAGS) {
5133 if (wq_attr->flags_mask & IB_WQ_FLAGS_CVLAN_STRIPPING) {
5134 if (!(MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
5135 MLX5_CAP_ETH(dev->mdev, vlan_cap))) {
5136 mlx5_ib_dbg(dev, "VLAN offloads are not "
5137 "supported\n");
5138 err = -EOPNOTSUPP;
5139 goto out;
5140 }
5141 MLX5_SET64(modify_rq_in, in, modify_bitmask,
5142 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD);
5143 MLX5_SET(rqc, rqc, vlan_strip_disable,
5144 (wq_attr->flags & IB_WQ_FLAGS_CVLAN_STRIPPING) ? 0 : 1);
5145 }
5146 }
5147
5148 err = mlx5_core_modify_rq(dev->mdev, in, inlen);
5149 if (!err)
5150 rwq->ibwq.state = (wq_state == MLX5_RQC_STATE_ERR) ? IB_WQS_ERR : wq_state;
5151 out:
5152 kvfree(in);
5153 return err;
5154 }
5155