1 /*-
2 * Copyright (c) 2016 Jared McNeill <jmcneill@invisible.ca>
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
6 * are met:
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 *
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
14 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
15 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
16 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
17 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
18 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
19 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
20 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
21 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
23 * SUCH DAMAGE.
24 */
25
26 /*
27 * Allwinner USB PHY
28 */
29
30 #include <sys/param.h>
31 #include <sys/systm.h>
32 #include <sys/bus.h>
33 #include <sys/rman.h>
34 #include <sys/kernel.h>
35 #include <sys/module.h>
36 #include <sys/gpio.h>
37 #include <machine/bus.h>
38
39 #include <dev/ofw/ofw_bus.h>
40 #include <dev/ofw/ofw_bus_subr.h>
41 #include <dev/gpio/gpiobusvar.h>
42
43 #include <dev/clk/clk.h>
44 #include <dev/hwreset/hwreset.h>
45 #include <dev/regulator/regulator.h>
46 #include <dev/phy/phy_usb.h>
47
48 #include "phynode_if.h"
49
50 enum awusbphy_type {
51 AWUSBPHY_TYPE_A10 = 1,
52 AWUSBPHY_TYPE_A13,
53 AWUSBPHY_TYPE_A20,
54 AWUSBPHY_TYPE_A31,
55 AWUSBPHY_TYPE_H3,
56 AWUSBPHY_TYPE_A64,
57 AWUSBPHY_TYPE_A83T,
58 AWUSBPHY_TYPE_H6,
59 AWUSBPHY_TYPE_H616,
60 AWUSBPHY_TYPE_D1,
61 };
62
63 struct aw_usbphy_conf {
64 int num_phys;
65 enum awusbphy_type phy_type;
66 bool pmu_unk1;
67 bool phy0_route;
68 };
69
70 static const struct aw_usbphy_conf a10_usbphy_conf = {
71 .num_phys = 3,
72 .phy_type = AWUSBPHY_TYPE_A10,
73 .pmu_unk1 = false,
74 .phy0_route = false,
75 };
76
77 static const struct aw_usbphy_conf a13_usbphy_conf = {
78 .num_phys = 2,
79 .phy_type = AWUSBPHY_TYPE_A13,
80 .pmu_unk1 = false,
81 .phy0_route = false,
82 };
83
84 static const struct aw_usbphy_conf a20_usbphy_conf = {
85 .num_phys = 3,
86 .phy_type = AWUSBPHY_TYPE_A20,
87 .pmu_unk1 = false,
88 .phy0_route = false,
89 };
90
91 static const struct aw_usbphy_conf a31_usbphy_conf = {
92 .num_phys = 3,
93 .phy_type = AWUSBPHY_TYPE_A31,
94 .pmu_unk1 = false,
95 .phy0_route = false,
96 };
97
98 static const struct aw_usbphy_conf h3_usbphy_conf = {
99 .num_phys = 4,
100 .phy_type = AWUSBPHY_TYPE_H3,
101 .pmu_unk1 = true,
102 .phy0_route = true,
103 };
104
105 static const struct aw_usbphy_conf a64_usbphy_conf = {
106 .num_phys = 2,
107 .phy_type = AWUSBPHY_TYPE_A64,
108 .pmu_unk1 = true,
109 .phy0_route = true,
110 };
111
112 static const struct aw_usbphy_conf a83t_usbphy_conf = {
113 .num_phys = 3,
114 .phy_type = AWUSBPHY_TYPE_A83T,
115 .pmu_unk1 = false,
116 .phy0_route = false,
117 };
118
119 static const struct aw_usbphy_conf h6_usbphy_conf = {
120 .num_phys = 4,
121 .phy_type = AWUSBPHY_TYPE_H6,
122 .pmu_unk1 = false,
123 .phy0_route = true,
124 };
125
126 static const struct aw_usbphy_conf h616_usbphy_conf = {
127 .num_phys = 4,
128 .phy_type = AWUSBPHY_TYPE_H616,
129 .pmu_unk1 = false,
130 .phy0_route = true,
131 };
132
133 static const struct aw_usbphy_conf d1_usbphy_conf = {
134 .num_phys = 2,
135 .phy_type = AWUSBPHY_TYPE_D1,
136 .pmu_unk1 = true,
137 .phy0_route = true,
138 };
139
140 static struct ofw_compat_data compat_data[] = {
141 { "allwinner,sun4i-a10-usb-phy", (uintptr_t)&a10_usbphy_conf },
142 { "allwinner,sun5i-a13-usb-phy", (uintptr_t)&a13_usbphy_conf },
143 { "allwinner,sun6i-a31-usb-phy", (uintptr_t)&a31_usbphy_conf },
144 { "allwinner,sun7i-a20-usb-phy", (uintptr_t)&a20_usbphy_conf },
145 { "allwinner,sun8i-h3-usb-phy", (uintptr_t)&h3_usbphy_conf },
146 { "allwinner,sun50i-a64-usb-phy", (uintptr_t)&a64_usbphy_conf },
147 { "allwinner,sun8i-a83t-usb-phy", (uintptr_t)&a83t_usbphy_conf },
148 { "allwinner,sun50i-h6-usb-phy", (uintptr_t)&h6_usbphy_conf },
149 { "allwinner,sun50i-h616-usb-phy", (uintptr_t)&h616_usbphy_conf },
150 { "allwinner,sun20i-d1-usb-phy", (uintptr_t)&d1_usbphy_conf },
151 { NULL, 0 }
152 };
153
154 struct awusbphy_softc {
155 struct resource * phy_ctrl;
156 struct resource ** pmu;
157 regulator_t * reg;
158 gpio_pin_t id_det_pin;
159 int id_det_valid;
160 gpio_pin_t vbus_det_pin;
161 int vbus_det_valid;
162 struct aw_usbphy_conf *phy_conf;
163 int mode;
164 };
165
166 /* Phy class and methods. */
167 static int awusbphy_phy_enable(struct phynode *phy, bool enable);
168 static int awusbphy_get_mode(struct phynode *phy, int *mode);
169 static int awusbphy_set_mode(struct phynode *phy, int mode);
170 static phynode_usb_method_t awusbphy_phynode_methods[] = {
171 PHYNODEMETHOD(phynode_enable, awusbphy_phy_enable),
172 PHYNODEMETHOD(phynode_usb_get_mode, awusbphy_get_mode),
173 PHYNODEMETHOD(phynode_usb_set_mode, awusbphy_set_mode),
174
175 PHYNODEMETHOD_END
176 };
177 DEFINE_CLASS_1(awusbphy_phynode, awusbphy_phynode_class, awusbphy_phynode_methods,
178 sizeof(struct phynode_usb_sc), phynode_usb_class);
179
180 #define RD4(res, o) bus_read_4(res, (o))
181 #define WR4(res, o, v) bus_write_4(res, (o), (v))
182 #define CLR4(res, o, m) WR4(res, o, RD4(res, o) & ~(m))
183 #define SET4(res, o, m) WR4(res, o, RD4(res, o) | (m))
184
185 #define PHY_CSR 0x00
186 #define ID_PULLUP_EN (1 << 17)
187 #define DPDM_PULLUP_EN (1 << 16)
188 #define FORCE_ID (0x3 << 14)
189 #define FORCE_ID_SHIFT 14
190 #define FORCE_ID_LOW 2
191 #define FORCE_ID_HIGH 3
192 #define FORCE_VBUS_VALID (0x3 << 12)
193 #define FORCE_VBUS_VALID_SHIFT 12
194 #define FORCE_VBUS_VALID_LOW 2
195 #define FORCE_VBUS_VALID_HIGH 3
196 #define VBUS_CHANGE_DET (1 << 6)
197 #define ID_CHANGE_DET (1 << 5)
198 #define DPDM_CHANGE_DET (1 << 4)
199 #define OTG_PHY_CFG 0x20
200 #define OTG_PHY_ROUTE_OTG (1 << 0)
201 #define PMU_IRQ_ENABLE 0x00
202 #define PMU_AHB_INCR8 (1 << 10)
203 #define PMU_AHB_INCR4 (1 << 9)
204 #define PMU_AHB_INCRX_ALIGN (1 << 8)
205 #define PMU_ULPI_BYPASS (1 << 0)
206 #define PMU_UNK_H3 0x10
207 #define PMU_UNK_H3_CLR 0x2
208
209 static void
awusbphy_configure(device_t dev,int phyno)210 awusbphy_configure(device_t dev, int phyno)
211 {
212 struct awusbphy_softc *sc;
213
214 sc = device_get_softc(dev);
215
216 if (sc->pmu[phyno] == NULL)
217 return;
218
219 if (sc->phy_conf->pmu_unk1 == true)
220 CLR4(sc->pmu[phyno], PMU_UNK_H3, PMU_UNK_H3_CLR);
221
222 SET4(sc->pmu[phyno], PMU_IRQ_ENABLE, PMU_ULPI_BYPASS |
223 PMU_AHB_INCR8 | PMU_AHB_INCR4 | PMU_AHB_INCRX_ALIGN);
224 }
225
226 static int
awusbphy_init(device_t dev)227 awusbphy_init(device_t dev)
228 {
229 struct awusbphy_softc *sc;
230 phandle_t node;
231 char pname[20];
232 uint32_t val;
233 int error, off, rid;
234 regulator_t reg;
235 hwreset_t rst;
236 clk_t clk;
237
238 sc = device_get_softc(dev);
239 node = ofw_bus_get_node(dev);
240
241 sc->phy_conf = (struct aw_usbphy_conf *)ofw_bus_search_compatible(dev, compat_data)->ocd_data;
242
243 /* Get phy_ctrl region */
244 if (ofw_bus_find_string_index(node, "reg-names", "phy_ctrl", &rid) != 0) {
245 device_printf(dev, "Cannot locate phy control resource\n");
246 return (ENXIO);
247 }
248 sc->phy_ctrl = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
249 RF_ACTIVE);
250 if (sc->phy_ctrl == NULL) {
251 device_printf(dev, "Cannot allocate resource\n");
252 return (ENXIO);
253 }
254
255 /* Enable clocks */
256 for (off = 0; clk_get_by_ofw_index(dev, 0, off, &clk) == 0; off++) {
257 error = clk_enable(clk);
258 if (error != 0) {
259 device_printf(dev, "couldn't enable clock %s\n",
260 clk_get_name(clk));
261 return (error);
262 }
263 }
264
265 /* De-assert resets */
266 for (off = 0; hwreset_get_by_ofw_idx(dev, 0, off, &rst) == 0; off++) {
267 error = hwreset_deassert(rst);
268 if (error != 0) {
269 device_printf(dev, "couldn't de-assert reset %d\n",
270 off);
271 return (error);
272 }
273 }
274
275 /* Get GPIOs */
276 error = gpio_pin_get_by_ofw_property(dev, node, "usb0_id_det-gpios",
277 &sc->id_det_pin);
278 if (error == 0)
279 sc->id_det_valid = 1;
280 error = gpio_pin_get_by_ofw_property(dev, node, "usb0_vbus_det-gpios",
281 &sc->vbus_det_pin);
282 if (error == 0)
283 sc->vbus_det_valid = 1;
284
285 sc->reg = malloc(sizeof(*(sc->reg)) * sc->phy_conf->num_phys, M_DEVBUF,
286 M_WAITOK | M_ZERO);
287 sc->pmu = malloc(sizeof(*(sc->pmu)) * sc->phy_conf->num_phys, M_DEVBUF,
288 M_WAITOK | M_ZERO);
289 /* Get regulators */
290 for (off = 0; off < sc->phy_conf->num_phys; off++) {
291 snprintf(pname, sizeof(pname), "usb%d_vbus-supply", off);
292 if (regulator_get_by_ofw_property(dev, 0, pname, ®) == 0)
293 sc->reg[off] = reg;
294
295 snprintf(pname, sizeof(pname), "pmu%d", off);
296 if (ofw_bus_find_string_index(node, "reg-names",
297 pname, &rid) != 0)
298 continue;
299
300 sc->pmu[off] = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
301 RF_ACTIVE);
302 if (sc->pmu[off] == NULL) {
303 device_printf(dev, "Cannot allocate resource\n");
304 return (ENXIO);
305 }
306 }
307
308 /* Enable OTG PHY for host mode */
309 val = bus_read_4(sc->phy_ctrl, PHY_CSR);
310 val &= ~(VBUS_CHANGE_DET | ID_CHANGE_DET | DPDM_CHANGE_DET);
311 val |= (ID_PULLUP_EN | DPDM_PULLUP_EN);
312 val &= ~FORCE_ID;
313 val |= (FORCE_ID_LOW << FORCE_ID_SHIFT);
314 val &= ~FORCE_VBUS_VALID;
315 val |= (FORCE_VBUS_VALID_HIGH << FORCE_VBUS_VALID_SHIFT);
316 bus_write_4(sc->phy_ctrl, PHY_CSR, val);
317
318 return (0);
319 }
320
321 static int
awusbphy_vbus_detect(device_t dev,int * val)322 awusbphy_vbus_detect(device_t dev, int *val)
323 {
324 struct awusbphy_softc *sc;
325 bool active;
326 int error;
327
328 sc = device_get_softc(dev);
329
330 if (sc->vbus_det_valid) {
331 error = gpio_pin_is_active(sc->vbus_det_pin, &active);
332 if (error != 0) {
333 device_printf(dev, "Cannot get status of id pin %d\n",
334 error);
335 return (error);
336 }
337 *val = active;
338 return (0);
339 }
340
341 /* TODO check vbus_power-supply. */
342
343 /*
344 * If there is no way to detect, assume present.
345 */
346 *val = 1;
347 return (0);
348 }
349
350 static int
awusbphy_phy_enable(struct phynode * phynode,bool enable)351 awusbphy_phy_enable(struct phynode *phynode, bool enable)
352 {
353 device_t dev;
354 intptr_t phy;
355 struct awusbphy_softc *sc;
356 regulator_t reg;
357 int error, vbus_det;
358
359 dev = phynode_get_device(phynode);
360 phy = phynode_get_id(phynode);
361 sc = device_get_softc(dev);
362
363 if (phy < 0 || phy >= sc->phy_conf->num_phys)
364 return (ERANGE);
365
366 /* Configure PHY */
367 awusbphy_configure(dev, phy);
368
369 /* Regulators are optional. If not found, return success. */
370 reg = sc->reg[phy];
371 if (reg == NULL)
372 return (0);
373
374 if (phy == 0) {
375 /* If an external vbus is detected, do not enable phy 0 */
376 error = awusbphy_vbus_detect(dev, &vbus_det);
377 if (error)
378 goto out;
379
380 /* TODO check vbus_power-supply as well. */
381 if (sc->vbus_det_valid && vbus_det == 1) {
382 if (bootverbose)
383 device_printf(dev, "External VBUS detected, "
384 "not enabling the regulator\n");
385 return (0);
386 }
387 }
388 if (enable) {
389 /* Depending on the PHY we need to route OTG to OHCI/EHCI */
390 error = regulator_enable(reg);
391 } else
392 error = regulator_disable(reg);
393
394 out:
395 if (error != 0) {
396 device_printf(dev,
397 "couldn't %s regulator for phy %jd\n",
398 enable ? "enable" : "disable", (intmax_t)phy);
399 return (error);
400 }
401
402 return (0);
403 }
404
405 static int
awusbphy_get_mode(struct phynode * phynode,int * mode)406 awusbphy_get_mode(struct phynode *phynode, int *mode)
407 {
408 struct awusbphy_softc *sc;
409 device_t dev;
410
411 dev = phynode_get_device(phynode);
412 sc = device_get_softc(dev);
413
414 *mode = sc->mode;
415
416 return (0);
417 }
418
419 static int
awusbphy_set_mode(struct phynode * phynode,int mode)420 awusbphy_set_mode(struct phynode *phynode, int mode)
421 {
422 device_t dev;
423 intptr_t phy;
424 struct awusbphy_softc *sc;
425 uint32_t val;
426 int error, vbus_det;
427
428 dev = phynode_get_device(phynode);
429 phy = phynode_get_id(phynode);
430 sc = device_get_softc(dev);
431
432 if (phy != 0) {
433 if (mode != PHY_USB_MODE_HOST)
434 return (EINVAL);
435 return (0);
436 }
437
438 if (sc->mode == mode)
439 return (0);
440 if (mode == PHY_USB_MODE_OTG) /* TODO */
441 return (EOPNOTSUPP);
442
443 error = awusbphy_vbus_detect(dev, &vbus_det);
444 if (error != 0)
445 return (error);
446
447 val = bus_read_4(sc->phy_ctrl, PHY_CSR);
448 val &= ~(VBUS_CHANGE_DET | ID_CHANGE_DET | DPDM_CHANGE_DET);
449 val |= (ID_PULLUP_EN | DPDM_PULLUP_EN);
450 val &= ~FORCE_VBUS_VALID;
451 val |= (vbus_det ? FORCE_VBUS_VALID_HIGH : FORCE_VBUS_VALID_LOW) <<
452 FORCE_VBUS_VALID_SHIFT;
453 val &= ~FORCE_ID;
454
455 switch (mode) {
456 case PHY_USB_MODE_HOST:
457 val |= (FORCE_ID_LOW << FORCE_ID_SHIFT);
458 if (sc->phy_conf->phy0_route)
459 CLR4(sc->phy_ctrl, OTG_PHY_CFG, OTG_PHY_ROUTE_OTG);
460 break;
461 case PHY_USB_MODE_DEVICE:
462 val |= (FORCE_ID_HIGH << FORCE_ID_SHIFT);
463 if (sc->phy_conf->phy0_route)
464 SET4(sc->phy_ctrl, OTG_PHY_CFG, OTG_PHY_ROUTE_OTG);
465 break;
466 default:
467 return (EINVAL);
468 }
469
470 bus_write_4(sc->phy_ctrl, PHY_CSR, val);
471 sc->mode = mode;
472 return (0);
473 }
474
475 static int
awusbphy_probe(device_t dev)476 awusbphy_probe(device_t dev)
477 {
478 if (!ofw_bus_status_okay(dev))
479 return (ENXIO);
480
481 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
482 return (ENXIO);
483
484 device_set_desc(dev, "Allwinner USB PHY");
485 return (BUS_PROBE_DEFAULT);
486 }
487
488 static int
awusbphy_attach(device_t dev)489 awusbphy_attach(device_t dev)
490 {
491 int error;
492 struct phynode *phynode;
493 struct phynode_init_def phy_init;
494 struct awusbphy_softc *sc;
495 int i;
496
497 sc = device_get_softc(dev);
498 error = awusbphy_init(dev);
499 if (error) {
500 device_printf(dev, "failed to initialize USB PHY, error %d\n",
501 error);
502 return (error);
503 }
504
505 /* Create and register phys. */
506 for (i = 0; i < sc->phy_conf->num_phys; i++) {
507 bzero(&phy_init, sizeof(phy_init));
508 phy_init.id = i;
509 phy_init.ofw_node = ofw_bus_get_node(dev);
510 phynode = phynode_create(dev, &awusbphy_phynode_class,
511 &phy_init);
512 if (phynode == NULL) {
513 device_printf(dev, "failed to create USB PHY\n");
514 return (ENXIO);
515 }
516 if (phynode_register(phynode) == NULL) {
517 device_printf(dev, "failed to create USB PHY\n");
518 return (ENXIO);
519 }
520 }
521
522 return (error);
523 }
524
525 static device_method_t awusbphy_methods[] = {
526 /* Device interface */
527 DEVMETHOD(device_probe, awusbphy_probe),
528 DEVMETHOD(device_attach, awusbphy_attach),
529
530 DEVMETHOD_END
531 };
532
533 static driver_t awusbphy_driver = {
534 "awusbphy",
535 awusbphy_methods,
536 sizeof(struct awusbphy_softc)
537 };
538
539 /* aw_usbphy needs to come up after regulators/gpio/etc, but before ehci/ohci */
540 EARLY_DRIVER_MODULE(awusbphy, simplebus, awusbphy_driver, 0, 0,
541 BUS_PASS_SUPPORTDEV + BUS_PASS_ORDER_MIDDLE);
542 MODULE_VERSION(awusbphy, 1);
543