1// SPDX-License-Identifier: GPL-2.0-or-later 2/* 3 * dts file for AppliedMicro (APM) X-Gene Shadowcat SOC 4 * 5 * Copyright (C) 2015, Applied Micro Circuits Corporation 6 */ 7 8/ { 9 compatible = "apm,xgene-shadowcat"; 10 interrupt-parent = <&gic>; 11 #address-cells = <2>; 12 #size-cells = <2>; 13 14 cpus { 15 #address-cells = <2>; 16 #size-cells = <0>; 17 18 cpu@0 { 19 device_type = "cpu"; 20 compatible = "apm,strega"; 21 reg = <0x0 0x000>; 22 enable-method = "spin-table"; 23 cpu-release-addr = <0x1 0x0000fff8>; 24 next-level-cache = <&xgene_L2_0>; 25 clocks = <&pmd0clk 0>; 26 }; 27 cpu@1 { 28 device_type = "cpu"; 29 compatible = "apm,strega"; 30 reg = <0x0 0x001>; 31 enable-method = "spin-table"; 32 cpu-release-addr = <0x1 0x0000fff8>; 33 next-level-cache = <&xgene_L2_0>; 34 clocks = <&pmd0clk 0>; 35 }; 36 cpu@100 { 37 device_type = "cpu"; 38 compatible = "apm,strega"; 39 reg = <0x0 0x100>; 40 enable-method = "spin-table"; 41 cpu-release-addr = <0x1 0x0000fff8>; 42 next-level-cache = <&xgene_L2_1>; 43 clocks = <&pmd1clk 0>; 44 }; 45 cpu@101 { 46 device_type = "cpu"; 47 compatible = "apm,strega"; 48 reg = <0x0 0x101>; 49 enable-method = "spin-table"; 50 cpu-release-addr = <0x1 0x0000fff8>; 51 next-level-cache = <&xgene_L2_1>; 52 clocks = <&pmd1clk 0>; 53 }; 54 cpu@200 { 55 device_type = "cpu"; 56 compatible = "apm,strega"; 57 reg = <0x0 0x200>; 58 enable-method = "spin-table"; 59 cpu-release-addr = <0x1 0x0000fff8>; 60 next-level-cache = <&xgene_L2_2>; 61 clocks = <&pmd2clk 0>; 62 }; 63 cpu@201 { 64 device_type = "cpu"; 65 compatible = "apm,strega"; 66 reg = <0x0 0x201>; 67 enable-method = "spin-table"; 68 cpu-release-addr = <0x1 0x0000fff8>; 69 next-level-cache = <&xgene_L2_2>; 70 clocks = <&pmd2clk 0>; 71 }; 72 cpu@300 { 73 device_type = "cpu"; 74 compatible = "apm,strega"; 75 reg = <0x0 0x300>; 76 enable-method = "spin-table"; 77 cpu-release-addr = <0x1 0x0000fff8>; 78 next-level-cache = <&xgene_L2_3>; 79 clocks = <&pmd3clk 0>; 80 }; 81 cpu@301 { 82 device_type = "cpu"; 83 compatible = "apm,strega"; 84 reg = <0x0 0x301>; 85 enable-method = "spin-table"; 86 cpu-release-addr = <0x1 0x0000fff8>; 87 next-level-cache = <&xgene_L2_3>; 88 clocks = <&pmd3clk 0>; 89 }; 90 xgene_L2_0: l2-cache-0 { 91 compatible = "cache"; 92 cache-level = <2>; 93 cache-unified; 94 }; 95 xgene_L2_1: l2-cache-1 { 96 compatible = "cache"; 97 cache-level = <2>; 98 cache-unified; 99 }; 100 xgene_L2_2: l2-cache-2 { 101 compatible = "cache"; 102 cache-level = <2>; 103 cache-unified; 104 }; 105 xgene_L2_3: l2-cache-3 { 106 compatible = "cache"; 107 cache-level = <2>; 108 cache-unified; 109 }; 110 }; 111 112 gic: interrupt-controller@78090000 { 113 compatible = "arm,cortex-a15-gic"; 114 #interrupt-cells = <3>; 115 #address-cells = <2>; 116 #size-cells = <2>; 117 interrupt-controller; 118 interrupts = <1 9 0xf04>; /* GIC Maintenence IRQ */ 119 ranges = <0 0 0 0x79000000 0x0 0x800000>; /* MSI Range */ 120 reg = <0x0 0x78090000 0x0 0x10000>, /* GIC Dist */ 121 <0x0 0x780a0000 0x0 0x20000>, /* GIC CPU */ 122 <0x0 0x780c0000 0x0 0x10000>, /* GIC VCPU Control */ 123 <0x0 0x780e0000 0x0 0x20000>; /* GIC VCPU */ 124 v2m0: v2m@0 { 125 compatible = "arm,gic-v2m-frame"; 126 msi-controller; 127 reg = <0x0 0x0 0x0 0x1000>; 128 }; 129 v2m1: v2m@10000 { 130 compatible = "arm,gic-v2m-frame"; 131 msi-controller; 132 reg = <0x0 0x10000 0x0 0x1000>; 133 }; 134 v2m2: v2m@20000 { 135 compatible = "arm,gic-v2m-frame"; 136 msi-controller; 137 reg = <0x0 0x20000 0x0 0x1000>; 138 }; 139 v2m3: v2m@30000 { 140 compatible = "arm,gic-v2m-frame"; 141 msi-controller; 142 reg = <0x0 0x30000 0x0 0x1000>; 143 }; 144 v2m4: v2m@40000 { 145 compatible = "arm,gic-v2m-frame"; 146 msi-controller; 147 reg = <0x0 0x40000 0x0 0x1000>; 148 }; 149 v2m5: v2m@50000 { 150 compatible = "arm,gic-v2m-frame"; 151 msi-controller; 152 reg = <0x0 0x50000 0x0 0x1000>; 153 }; 154 v2m6: v2m@60000 { 155 compatible = "arm,gic-v2m-frame"; 156 msi-controller; 157 reg = <0x0 0x60000 0x0 0x1000>; 158 }; 159 v2m7: v2m@70000 { 160 compatible = "arm,gic-v2m-frame"; 161 msi-controller; 162 reg = <0x0 0x70000 0x0 0x1000>; 163 }; 164 v2m8: v2m@80000 { 165 compatible = "arm,gic-v2m-frame"; 166 msi-controller; 167 reg = <0x0 0x80000 0x0 0x1000>; 168 }; 169 v2m9: v2m@90000 { 170 compatible = "arm,gic-v2m-frame"; 171 msi-controller; 172 reg = <0x0 0x90000 0x0 0x1000>; 173 }; 174 v2m10: v2m@a0000 { 175 compatible = "arm,gic-v2m-frame"; 176 msi-controller; 177 reg = <0x0 0xa0000 0x0 0x1000>; 178 }; 179 v2m11: v2m@b0000 { 180 compatible = "arm,gic-v2m-frame"; 181 msi-controller; 182 reg = <0x0 0xb0000 0x0 0x1000>; 183 }; 184 v2m12: v2m@c0000 { 185 compatible = "arm,gic-v2m-frame"; 186 msi-controller; 187 reg = <0x0 0xc0000 0x0 0x1000>; 188 }; 189 v2m13: v2m@d0000 { 190 compatible = "arm,gic-v2m-frame"; 191 msi-controller; 192 reg = <0x0 0xd0000 0x0 0x1000>; 193 }; 194 v2m14: v2m@e0000 { 195 compatible = "arm,gic-v2m-frame"; 196 msi-controller; 197 reg = <0x0 0xe0000 0x0 0x1000>; 198 }; 199 v2m15: v2m@f0000 { 200 compatible = "arm,gic-v2m-frame"; 201 msi-controller; 202 reg = <0x0 0xf0000 0x0 0x1000>; 203 }; 204 }; 205 206 refclk: clock-100000000 { 207 compatible = "fixed-clock"; 208 #clock-cells = <0>; 209 clock-frequency = <100000000>; 210 clock-output-names = "refclk"; 211 }; 212 213 pmu { 214 compatible = "arm,armv8-pmuv3"; 215 interrupts = <1 12 0xff04>; 216 }; 217 218 timer { 219 compatible = "arm,armv8-timer"; 220 interrupts = <1 0 0xff08>, /* Secure Phys IRQ */ 221 <1 13 0xff08>, /* Non-secure Phys IRQ */ 222 <1 14 0xff08>, /* Virt IRQ */ 223 <1 15 0xff08>; /* Hyp IRQ */ 224 clock-frequency = <50000000>; 225 }; 226 227 i2c { 228 compatible = "apm,xgene-slimpro-i2c"; 229 mboxes = <&mailbox 0>; 230 }; 231 232 hwmonslimpro { 233 compatible = "apm,xgene-slimpro-hwmon"; 234 mboxes = <&mailbox 7>; 235 }; 236 237 soc { 238 compatible = "simple-bus"; 239 #address-cells = <2>; 240 #size-cells = <2>; 241 ranges; 242 243 clocks { 244 #address-cells = <2>; 245 #size-cells = <2>; 246 ranges; 247 248 pmdpll: pmdpll@170000f0 { 249 compatible = "apm,xgene-pcppll-v2-clock"; 250 #clock-cells = <1>; 251 clocks = <&refclk>; 252 reg = <0x0 0x170000f0 0x0 0x10>; 253 clock-output-names = "pmdpll"; 254 }; 255 256 pmd0clk: pmd0clk@7e200200 { 257 compatible = "apm,xgene-pmd-clock"; 258 #clock-cells = <1>; 259 clocks = <&pmdpll 0>; 260 reg = <0x0 0x7e200200 0x0 0x10>; 261 clock-output-names = "pmd0clk"; 262 }; 263 264 pmd1clk: pmd1clk@7e200210 { 265 compatible = "apm,xgene-pmd-clock"; 266 #clock-cells = <1>; 267 clocks = <&pmdpll 0>; 268 reg = <0x0 0x7e200210 0x0 0x10>; 269 clock-output-names = "pmd1clk"; 270 }; 271 272 pmd2clk: pmd2clk@7e200220 { 273 compatible = "apm,xgene-pmd-clock"; 274 #clock-cells = <1>; 275 clocks = <&pmdpll 0>; 276 reg = <0x0 0x7e200220 0x0 0x10>; 277 clock-output-names = "pmd2clk"; 278 }; 279 280 pmd3clk: pmd3clk@7e200230 { 281 compatible = "apm,xgene-pmd-clock"; 282 #clock-cells = <1>; 283 clocks = <&pmdpll 0>; 284 reg = <0x0 0x7e200230 0x0 0x10>; 285 clock-output-names = "pmd3clk"; 286 }; 287 288 socpll: socpll@17000120 { 289 compatible = "apm,xgene-socpll-v2-clock"; 290 #clock-cells = <1>; 291 clocks = <&refclk>; 292 reg = <0x0 0x17000120 0x0 0x1000>; 293 clock-output-names = "socpll"; 294 }; 295 296 socplldiv2: socplldiv2 { 297 compatible = "fixed-factor-clock"; 298 #clock-cells = <0>; 299 clocks = <&socpll 0>; 300 clock-mult = <1>; 301 clock-div = <2>; 302 clock-output-names = "socplldiv2"; 303 }; 304 305 ahbclk: ahbclk@17000000 { 306 compatible = "apm,xgene-device-clock"; 307 #clock-cells = <1>; 308 clocks = <&socplldiv2>; 309 reg = <0x0 0x17000000 0x0 0x2000>; 310 reg-names = "div-reg"; 311 divider-offset = <0x164>; 312 divider-width = <0x5>; 313 divider-shift = <0x0>; 314 clock-output-names = "ahbclk"; 315 }; 316 317 sbapbclk: sbapbclk@1704c000 { 318 compatible = "apm,xgene-device-clock"; 319 #clock-cells = <1>; 320 clocks = <&ahbclk 0>; 321 reg = <0x0 0x1704c000 0x0 0x2000>; 322 reg-names = "div-reg"; 323 divider-offset = <0x10>; 324 divider-width = <0x2>; 325 divider-shift = <0x0>; 326 clock-output-names = "sbapbclk"; 327 }; 328 329 sdioclk: sdioclk@1f2ac000 { 330 compatible = "apm,xgene-device-clock"; 331 #clock-cells = <1>; 332 clocks = <&socplldiv2>; 333 reg = <0x0 0x1f2ac000 0x0 0x1000 334 0x0 0x17000000 0x0 0x2000>; 335 reg-names = "csr-reg", "div-reg"; 336 csr-offset = <0x0>; 337 csr-mask = <0x2>; 338 enable-offset = <0x8>; 339 enable-mask = <0x2>; 340 divider-offset = <0x178>; 341 divider-width = <0x8>; 342 divider-shift = <0x0>; 343 clock-output-names = "sdioclk"; 344 }; 345 346 pcie0clk: pcie0clk@1f2bc000 { 347 compatible = "apm,xgene-device-clock"; 348 #clock-cells = <1>; 349 clocks = <&socplldiv2>; 350 reg = <0x0 0x1f2bc000 0x0 0x1000>; 351 reg-names = "csr-reg"; 352 clock-output-names = "pcie0clk"; 353 }; 354 355 pcie1clk: pcie1clk@1f2cc000 { 356 compatible = "apm,xgene-device-clock"; 357 #clock-cells = <1>; 358 clocks = <&socplldiv2>; 359 reg = <0x0 0x1f2cc000 0x0 0x1000>; 360 reg-names = "csr-reg"; 361 clock-output-names = "pcie1clk"; 362 }; 363 364 xge0clk: xge0clk@1f61c000 { 365 compatible = "apm,xgene-device-clock"; 366 #clock-cells = <1>; 367 clocks = <&socplldiv2>; 368 reg = <0x0 0x1f61c000 0x0 0x1000>; 369 reg-names = "csr-reg"; 370 enable-mask = <0x3>; 371 csr-mask = <0x3>; 372 clock-output-names = "xge0clk"; 373 }; 374 375 xge1clk: xge1clk@1f62c000 { 376 compatible = "apm,xgene-device-clock"; 377 #clock-cells = <1>; 378 clocks = <&socplldiv2>; 379 reg = <0x0 0x1f62c000 0x0 0x1000>; 380 reg-names = "csr-reg"; 381 enable-mask = <0x3>; 382 csr-mask = <0x3>; 383 clock-output-names = "xge1clk"; 384 }; 385 386 rngpkaclk: rngpkaclk@17000000 { 387 compatible = "apm,xgene-device-clock"; 388 #clock-cells = <1>; 389 clocks = <&socplldiv2>; 390 reg = <0x0 0x17000000 0x0 0x2000>; 391 reg-names = "csr-reg"; 392 csr-offset = <0xc>; 393 csr-mask = <0x10>; 394 enable-offset = <0x10>; 395 enable-mask = <0x10>; 396 clock-output-names = "rngpkaclk"; 397 }; 398 399 i2c4clk: i2c4clk@1704c000 { 400 compatible = "apm,xgene-device-clock"; 401 #clock-cells = <1>; 402 clocks = <&sbapbclk 0>; 403 reg = <0x0 0x1704c000 0x0 0x1000>; 404 reg-names = "csr-reg"; 405 csr-offset = <0x0>; 406 csr-mask = <0x40>; 407 enable-offset = <0x8>; 408 enable-mask = <0x40>; 409 clock-output-names = "i2c4clk"; 410 }; 411 }; 412 413 scu: system-clk-controller@17000000 { 414 compatible = "apm,xgene-scu","syscon"; 415 reg = <0x0 0x17000000 0x0 0x400>; 416 }; 417 418 reboot: reboot@17000014 { 419 compatible = "syscon-reboot"; 420 reg = <0x0 0x17000014 0x0 0x4>; 421 regmap = <&scu>; 422 offset = <0x14>; 423 mask = <0x1>; 424 }; 425 426 csw: csw@7e200000 { 427 compatible = "apm,xgene-csw", "syscon"; 428 reg = <0x0 0x7e200000 0x0 0x1000>; 429 }; 430 431 mcba: mcba@7e700000 { 432 compatible = "apm,xgene-mcb", "syscon"; 433 reg = <0x0 0x7e700000 0x0 0x1000>; 434 }; 435 436 mcbb: mcbb@7e720000 { 437 compatible = "apm,xgene-mcb", "syscon"; 438 reg = <0x0 0x7e720000 0x0 0x1000>; 439 }; 440 441 efuse: efuse@1054a000 { 442 compatible = "apm,xgene-efuse", "syscon"; 443 reg = <0x0 0x1054a000 0x0 0x20>; 444 }; 445 446 edac@78800000 { 447 compatible = "apm,xgene-edac"; 448 #address-cells = <2>; 449 #size-cells = <2>; 450 ranges; 451 regmap-csw = <&csw>; 452 regmap-mcba = <&mcba>; 453 regmap-mcbb = <&mcbb>; 454 regmap-efuse = <&efuse>; 455 reg = <0x0 0x78800000 0x0 0x100>; 456 interrupts = <0x0 0x20 0x4>, 457 <0x0 0x21 0x4>, 458 <0x0 0x27 0x4>; 459 460 edacmc@7e800000 { 461 compatible = "apm,xgene-edac-mc"; 462 reg = <0x0 0x7e800000 0x0 0x1000>; 463 memory-controller = <0>; 464 }; 465 466 edacmc@7e840000 { 467 compatible = "apm,xgene-edac-mc"; 468 reg = <0x0 0x7e840000 0x0 0x1000>; 469 memory-controller = <1>; 470 }; 471 472 edacmc@7e880000 { 473 compatible = "apm,xgene-edac-mc"; 474 reg = <0x0 0x7e880000 0x0 0x1000>; 475 memory-controller = <2>; 476 }; 477 478 edacmc@7e8c0000 { 479 compatible = "apm,xgene-edac-mc"; 480 reg = <0x0 0x7e8c0000 0x0 0x1000>; 481 memory-controller = <3>; 482 }; 483 484 edacpmd@7c000000 { 485 compatible = "apm,xgene-edac-pmd"; 486 reg = <0x0 0x7c000000 0x0 0x200000>; 487 pmd-controller = <0>; 488 }; 489 490 edacpmd@7c200000 { 491 compatible = "apm,xgene-edac-pmd"; 492 reg = <0x0 0x7c200000 0x0 0x200000>; 493 pmd-controller = <1>; 494 }; 495 496 edacpmd@7c400000 { 497 compatible = "apm,xgene-edac-pmd"; 498 reg = <0x0 0x7c400000 0x0 0x200000>; 499 pmd-controller = <2>; 500 }; 501 502 edacpmd@7c600000 { 503 compatible = "apm,xgene-edac-pmd"; 504 reg = <0x0 0x7c600000 0x0 0x200000>; 505 pmd-controller = <3>; 506 }; 507 508 edacl3@7e600000 { 509 compatible = "apm,xgene-edac-l3-v2"; 510 reg = <0x0 0x7e600000 0x0 0x1000>; 511 }; 512 513 edacsoc@7e930000 { 514 compatible = "apm,xgene-edac-soc"; 515 reg = <0x0 0x7e930000 0x0 0x1000>; 516 }; 517 }; 518 519 pmu: pmu@78810000 { 520 compatible = "apm,xgene-pmu-v2"; 521 #address-cells = <2>; 522 #size-cells = <2>; 523 ranges; 524 regmap-csw = <&csw>; 525 regmap-mcba = <&mcba>; 526 regmap-mcbb = <&mcbb>; 527 reg = <0x0 0x78810000 0x0 0x1000>; 528 interrupts = <0x0 0x22 0x4>; 529 530 pmul3c@7e610000 { 531 compatible = "apm,xgene-pmu-l3c"; 532 reg = <0x0 0x7e610000 0x0 0x1000>; 533 }; 534 535 pmuiob@7e940000 { 536 compatible = "apm,xgene-pmu-iob"; 537 reg = <0x0 0x7e940000 0x0 0x1000>; 538 }; 539 540 pmucmcb@7e710000 { 541 compatible = "apm,xgene-pmu-mcb"; 542 reg = <0x0 0x7e710000 0x0 0x1000>; 543 enable-bit-index = <0>; 544 }; 545 546 pmucmcb@7e730000 { 547 compatible = "apm,xgene-pmu-mcb"; 548 reg = <0x0 0x7e730000 0x0 0x1000>; 549 enable-bit-index = <1>; 550 }; 551 552 pmucmc@7e810000 { 553 compatible = "apm,xgene-pmu-mc"; 554 reg = <0x0 0x7e810000 0x0 0x1000>; 555 enable-bit-index = <0>; 556 }; 557 558 pmucmc@7e850000 { 559 compatible = "apm,xgene-pmu-mc"; 560 reg = <0x0 0x7e850000 0x0 0x1000>; 561 enable-bit-index = <1>; 562 }; 563 564 pmucmc@7e890000 { 565 compatible = "apm,xgene-pmu-mc"; 566 reg = <0x0 0x7e890000 0x0 0x1000>; 567 enable-bit-index = <2>; 568 }; 569 570 pmucmc@7e8d0000 { 571 compatible = "apm,xgene-pmu-mc"; 572 reg = <0x0 0x7e8d0000 0x0 0x1000>; 573 enable-bit-index = <3>; 574 }; 575 }; 576 577 mailbox: mailbox@10540000 { 578 compatible = "apm,xgene-slimpro-mbox"; 579 reg = <0x0 0x10540000 0x0 0x8000>; 580 #mbox-cells = <1>; 581 interrupts = <0x0 0x0 0x4 582 0x0 0x1 0x4 583 0x0 0x2 0x4 584 0x0 0x3 0x4 585 0x0 0x4 0x4 586 0x0 0x5 0x4 587 0x0 0x6 0x4 588 0x0 0x7 0x4>; 589 }; 590 591 serial0: serial@10600000 { 592 compatible = "ns16550"; 593 reg = <0 0x10600000 0x0 0x1000>; 594 reg-shift = <2>; 595 clock-frequency = <10000000>; 596 interrupt-parent = <&gic>; 597 interrupts = <0x0 0x4c 0x4>; 598 }; 599 600 /* Node-name might need to be coded as dwusb for backward compatibility */ 601 usb0: usb@19000000 { 602 status = "disabled"; 603 compatible = "snps,dwc3"; 604 reg = <0x0 0x19000000 0x0 0x100000>; 605 interrupts = <0x0 0x5d 0x4>; 606 dma-coherent; 607 dr_mode = "host"; 608 }; 609 610 pcie0: pcie@1f2b0000 { 611 status = "disabled"; 612 device_type = "pci"; 613 compatible = "apm,xgene-pcie"; 614 #interrupt-cells = <1>; 615 #size-cells = <2>; 616 #address-cells = <3>; 617 reg = < 0x00 0x1f2b0000 0x0 0x00010000 /* Controller registers */ 618 0xc0 0xd0000000 0x0 0x00040000>; /* PCI config space */ 619 reg-names = "csr", "cfg"; 620 ranges = <0x01000000 0x00 0x00000000 0xc0 0x10000000 0x00 0x00010000 /* io */ 621 0x02000000 0x00 0x20000000 0xc1 0x20000000 0x00 0x20000000 /* mem */ 622 0x43000000 0xe0 0x00000000 0xe0 0x00000000 0x20 0x00000000>; /* mem */ 623 dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000 624 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>; 625 bus-range = <0x00 0xff>; 626 interrupt-map-mask = <0x0 0x0 0x0 0x7>; 627 interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0x0 0x0 0x10 0x4 628 0x0 0x0 0x0 0x2 &gic 0x0 0x0 0x0 0x11 0x4 629 0x0 0x0 0x0 0x3 &gic 0x0 0x0 0x0 0x12 0x4 630 0x0 0x0 0x0 0x4 &gic 0x0 0x0 0x0 0x13 0x4>; 631 dma-coherent; 632 clocks = <&pcie0clk 0>; 633 msi-parent = <&v2m0>; 634 }; 635 636 pcie1: pcie@1f2c0000 { 637 status = "disabled"; 638 device_type = "pci"; 639 compatible = "apm,xgene-pcie"; 640 #interrupt-cells = <1>; 641 #size-cells = <2>; 642 #address-cells = <3>; 643 reg = < 0x00 0x1f2c0000 0x0 0x00010000 /* Controller registers */ 644 0xa0 0xd0000000 0x0 0x00040000>; /* PCI config space */ 645 reg-names = "csr", "cfg"; 646 ranges = <0x01000000 0x00 0x00000000 0xa0 0x10000000 0x00 0x00010000 /* io */ 647 0x02000000 0x00 0x20000000 0xa1 0x20000000 0x00 0x20000000 /* mem */ 648 0x43000000 0xb0 0x00000000 0xb0 0x00000000 0x10 0x00000000>; /* mem */ 649 dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000 650 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>; 651 bus-range = <0x00 0xff>; 652 interrupt-map-mask = <0x0 0x0 0x0 0x7>; 653 interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0x0 0x0 0x16 0x4 654 0x0 0x0 0x0 0x2 &gic 0x0 0x0 0x0 0x17 0x4 655 0x0 0x0 0x0 0x3 &gic 0x0 0x0 0x0 0x18 0x4 656 0x0 0x0 0x0 0x4 &gic 0x0 0x0 0x0 0x19 0x4>; 657 dma-coherent; 658 clocks = <&pcie1clk 0>; 659 msi-parent = <&v2m0>; 660 }; 661 662 sata1: sata@1a000000 { 663 compatible = "apm,xgene-ahci-v2"; 664 reg = <0x0 0x1a000000 0x0 0x1000>, 665 <0x0 0x1f200000 0x0 0x1000>, 666 <0x0 0x1f20d000 0x0 0x1000>, 667 <0x0 0x1f20e000 0x0 0x1000>; 668 interrupts = <0x0 0x5a 0x4>; 669 dma-coherent; 670 }; 671 672 sata2: sata@1a200000 { 673 compatible = "apm,xgene-ahci-v2"; 674 reg = <0x0 0x1a200000 0x0 0x1000>, 675 <0x0 0x1f210000 0x0 0x1000>, 676 <0x0 0x1f21d000 0x0 0x1000>, 677 <0x0 0x1f21e000 0x0 0x1000>; 678 interrupts = <0x0 0x5b 0x4>; 679 dma-coherent; 680 }; 681 682 sata3: sata@1a400000 { 683 compatible = "apm,xgene-ahci-v2"; 684 reg = <0x0 0x1a400000 0x0 0x1000>, 685 <0x0 0x1f220000 0x0 0x1000>, 686 <0x0 0x1f22d000 0x0 0x1000>, 687 <0x0 0x1f22e000 0x0 0x1000>; 688 interrupts = <0x0 0x5c 0x4>; 689 dma-coherent; 690 }; 691 692 mmc0: mmc@1c000000 { 693 compatible = "arasan,sdhci-4.9a"; 694 reg = <0x0 0x1c000000 0x0 0x100>; 695 interrupts = <0x0 0x49 0x4>; 696 dma-coherent; 697 no-1-8-v; 698 clock-names = "clk_xin", "clk_ahb"; 699 clocks = <&sdioclk 0>, <&ahbclk 0>; 700 }; 701 702 gfcgpio: gpio@1f63c000 { 703 compatible = "apm,xgene-gpio"; 704 reg = <0x0 0x1f63c000 0x0 0x40>; 705 gpio-controller; 706 #gpio-cells = <2>; 707 }; 708 709 dwgpio: gpio@1c024000 { 710 compatible = "snps,dw-apb-gpio"; 711 reg = <0x0 0x1c024000 0x0 0x1000>; 712 #address-cells = <1>; 713 #size-cells = <0>; 714 715 porta: gpio-controller@0 { 716 compatible = "snps,dw-apb-gpio-port"; 717 gpio-controller; 718 #gpio-cells = <2>; 719 snps,nr-gpios = <32>; 720 reg = <0>; 721 }; 722 }; 723 724 sbgpio: gpio@17001000 { 725 compatible = "apm,xgene-gpio-sb"; 726 reg = <0x0 0x17001000 0x0 0x400>; 727 #gpio-cells = <2>; 728 gpio-controller; 729 interrupts = <0x0 0x28 0x1>, 730 <0x0 0x29 0x1>, 731 <0x0 0x2a 0x1>, 732 <0x0 0x2b 0x1>, 733 <0x0 0x2c 0x1>, 734 <0x0 0x2d 0x1>, 735 <0x0 0x2e 0x1>, 736 <0x0 0x2f 0x1>; 737 interrupt-parent = <&gic>; 738 #interrupt-cells = <2>; 739 interrupt-controller; 740 apm,nr-gpios = <22>; 741 apm,nr-irqs = <8>; 742 apm,irq-start = <8>; 743 }; 744 745 mdio: mdio@1f610000 { 746 compatible = "apm,xgene-mdio-xfi"; 747 #address-cells = <1>; 748 #size-cells = <0>; 749 reg = <0x0 0x1f610000 0x0 0xd100>; 750 clocks = <&xge0clk 0>; 751 }; 752 753 sgenet0: ethernet@1f610000 { 754 compatible = "apm,xgene2-sgenet"; 755 status = "disabled"; 756 reg = <0x0 0x1f610000 0x0 0xd100>, 757 <0x0 0x1f600000 0x0 0xd100>, 758 <0x0 0x20000000 0x0 0x20000>; 759 interrupts = <0 96 4>, 760 <0 97 4>; 761 dma-coherent; 762 clocks = <&xge0clk 0>; 763 local-mac-address = [00 01 73 00 00 01]; 764 phy-connection-type = "sgmii"; 765 phy-handle = <&sgenet0phy>; 766 }; 767 768 xgenet1: ethernet@1f620000 { 769 compatible = "apm,xgene2-xgenet"; 770 status = "disabled"; 771 reg = <0x0 0x1f620000 0x0 0x10000>, 772 <0x0 0x1f600000 0x0 0xd100>, 773 <0x0 0x20000000 0x0 0x220000>; 774 interrupts = <0 108 4>, 775 <0 109 4>, 776 <0 110 4>, 777 <0 111 4>, 778 <0 112 4>, 779 <0 113 4>, 780 <0 114 4>, 781 <0 115 4>; 782 channel = <12>; 783 port-id = <1>; 784 dma-coherent; 785 clocks = <&xge1clk 0>; 786 local-mac-address = [00 01 73 00 00 02]; 787 phy-connection-type = "xgmii"; 788 }; 789 790 rng: rng@10520000 { 791 compatible = "apm,xgene-rng"; 792 reg = <0x0 0x10520000 0x0 0x100>; 793 interrupts = <0x0 0x41 0x4>; 794 clocks = <&rngpkaclk 0>; 795 }; 796 797 i2c1: i2c@10511000 { 798 #address-cells = <1>; 799 #size-cells = <0>; 800 compatible = "snps,designware-i2c"; 801 reg = <0x0 0x10511000 0x0 0x1000>; 802 interrupts = <0 0x45 0x4>; 803 clocks = <&sbapbclk 0>; 804 }; 805 806 i2c4: i2c@10640000 { 807 #address-cells = <1>; 808 #size-cells = <0>; 809 compatible = "snps,designware-i2c"; 810 reg = <0x0 0x10640000 0x0 0x1000>; 811 interrupts = <0 0x3a 0x4>; 812 clocks = <&i2c4clk 0>; 813 }; 814 }; 815}; 816