1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2003-2008 Joseph Koshy
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29 #include <sys/types.h>
30 #include <sys/param.h>
31 #include <sys/module.h>
32 #include <sys/pmc.h>
33 #include <sys/syscall.h>
34
35 #include <ctype.h>
36 #include <errno.h>
37 #include <err.h>
38 #include <fcntl.h>
39 #include <pmc.h>
40 #include <stdio.h>
41 #include <stdlib.h>
42 #include <string.h>
43 #include <strings.h>
44 #include <sysexits.h>
45 #include <unistd.h>
46
47 #include "libpmcinternal.h"
48
49 /* Function prototypes */
50 #if defined(__amd64__) || defined(__i386__)
51 static int k8_allocate_pmc(enum pmc_event _pe, char *_ctrspec,
52 struct pmc_op_pmcallocate *_pmc_config);
53 static int ibs_allocate_pmc(enum pmc_event _pe, char *_ctrspec,
54 struct pmc_op_pmcallocate *_pmc_config);
55 static int tsc_allocate_pmc(enum pmc_event _pe, char *_ctrspec,
56 struct pmc_op_pmcallocate *_pmc_config);
57 #endif
58 #if defined(__arm__)
59 static int armv7_allocate_pmc(enum pmc_event _pe, char *_ctrspec,
60 struct pmc_op_pmcallocate *_pmc_config);
61 #endif
62 #if defined(__aarch64__)
63 static int arm64_allocate_pmc(enum pmc_event _pe, char *_ctrspec,
64 struct pmc_op_pmcallocate *_pmc_config);
65 static int cmn600_pmu_allocate_pmc(enum pmc_event _pe, char *_ctrspec,
66 struct pmc_op_pmcallocate *_pmc_config);
67 static int dmc620_pmu_allocate_pmc(enum pmc_event _pe, char *_ctrspec,
68 struct pmc_op_pmcallocate *_pmc_config);
69 #endif
70 static int soft_allocate_pmc(enum pmc_event _pe, char *_ctrspec,
71 struct pmc_op_pmcallocate *_pmc_config);
72
73 #if defined(__powerpc__)
74 static int powerpc_allocate_pmc(enum pmc_event _pe, char* ctrspec,
75 struct pmc_op_pmcallocate *_pmc_config);
76 #endif /* __powerpc__ */
77
78 #define PMC_CALL(op, params) syscall(pmc_syscall, (op), (params))
79
80 /*
81 * Event aliases provide a way for the user to ask for generic events
82 * like "cache-misses", or "instructions-retired". These aliases are
83 * mapped to the appropriate canonical event descriptions using a
84 * lookup table.
85 */
86 struct pmc_event_alias {
87 const char *pm_alias;
88 const char *pm_spec;
89 };
90
91 static const struct pmc_event_alias *pmc_mdep_event_aliases;
92
93 /*
94 * The pmc_event_descr structure maps symbolic names known to the user
95 * to integer codes used by the PMC KLD.
96 */
97 struct pmc_event_descr {
98 const char *pm_ev_name;
99 enum pmc_event pm_ev_code;
100 };
101
102 /*
103 * The pmc_class_descr structure maps class name prefixes for
104 * event names to event tables and other PMC class data.
105 */
106 struct pmc_class_descr {
107 const char *pm_evc_name;
108 size_t pm_evc_name_size;
109 enum pmc_class pm_evc_class;
110 const struct pmc_event_descr *pm_evc_event_table;
111 size_t pm_evc_event_table_size;
112 int (*pm_evc_allocate_pmc)(enum pmc_event _pe,
113 char *_ctrspec, struct pmc_op_pmcallocate *_pa);
114 };
115
116 #define PMC_TABLE_SIZE(N) (sizeof(N)/sizeof(N[0]))
117 #define PMC_EVENT_TABLE_SIZE(N) PMC_TABLE_SIZE(N##_event_table)
118
119 #undef __PMC_EV
120 #define __PMC_EV(C,N) { #N, PMC_EV_ ## C ## _ ## N },
121
122 /*
123 * PMC_CLASSDEP_TABLE(NAME, CLASS)
124 *
125 * Define a table mapping event names and aliases to HWPMC event IDs.
126 */
127 #define PMC_CLASSDEP_TABLE(N, C) \
128 static const struct pmc_event_descr N##_event_table[] = \
129 { \
130 __PMC_EV_##C() \
131 }
132
133 PMC_CLASSDEP_TABLE(iaf, IAF);
134 PMC_CLASSDEP_TABLE(k8, K8);
135 PMC_CLASSDEP_TABLE(ibs, IBS);
136 PMC_CLASSDEP_TABLE(armv7, ARMV7);
137 PMC_CLASSDEP_TABLE(armv8, ARMV8);
138 PMC_CLASSDEP_TABLE(cmn600_pmu, CMN600_PMU);
139 PMC_CLASSDEP_TABLE(dmc620_pmu_cd2, DMC620_PMU_CD2);
140 PMC_CLASSDEP_TABLE(dmc620_pmu_c, DMC620_PMU_C);
141 PMC_CLASSDEP_TABLE(ppc7450, PPC7450);
142 PMC_CLASSDEP_TABLE(ppc970, PPC970);
143 PMC_CLASSDEP_TABLE(e500, E500);
144
145 static struct pmc_event_descr soft_event_table[PMC_EV_DYN_COUNT];
146
147 #undef __PMC_EV_ALIAS
148 #define __PMC_EV_ALIAS(N,CODE) { N, PMC_EV_##CODE },
149
150 /*
151 * TODO: Factor out the __PMC_EV_ARMV7/8 list into a single separate table
152 * rather than duplicating for each core.
153 */
154
155 static const struct pmc_event_descr cortex_a8_event_table[] =
156 {
157 __PMC_EV_ALIAS_ARMV7_CORTEX_A8()
158 __PMC_EV_ARMV7()
159 };
160
161 static const struct pmc_event_descr cortex_a9_event_table[] =
162 {
163 __PMC_EV_ALIAS_ARMV7_CORTEX_A9()
164 __PMC_EV_ARMV7()
165 };
166
167 static const struct pmc_event_descr cortex_a53_event_table[] =
168 {
169 __PMC_EV_ALIAS_ARMV8_CORTEX_A53()
170 __PMC_EV_ARMV8()
171 };
172
173 static const struct pmc_event_descr cortex_a57_event_table[] =
174 {
175 __PMC_EV_ALIAS_ARMV8_CORTEX_A57()
176 __PMC_EV_ARMV8()
177 };
178
179 static const struct pmc_event_descr cortex_a76_event_table[] =
180 {
181 __PMC_EV_ALIAS_ARMV8_CORTEX_A76()
182 __PMC_EV_ARMV8()
183 };
184
185 static const struct pmc_event_descr tsc_event_table[] =
186 {
187 __PMC_EV_ALIAS_TSC()
188 };
189
190 #undef PMC_CLASS_TABLE_DESC
191 #define PMC_CLASS_TABLE_DESC(NAME, CLASS, EVENTS, ALLOCATOR) \
192 static const struct pmc_class_descr NAME##_class_table_descr = \
193 { \
194 .pm_evc_name = #CLASS "-", \
195 .pm_evc_name_size = sizeof(#CLASS "-") - 1, \
196 .pm_evc_class = PMC_CLASS_##CLASS , \
197 .pm_evc_event_table = EVENTS##_event_table , \
198 .pm_evc_event_table_size = \
199 PMC_EVENT_TABLE_SIZE(EVENTS), \
200 .pm_evc_allocate_pmc = ALLOCATOR##_allocate_pmc \
201 }
202
203 #if defined(__i386__) || defined(__amd64__)
204 PMC_CLASS_TABLE_DESC(k8, K8, k8, k8);
205 PMC_CLASS_TABLE_DESC(ibs, IBS, ibs, ibs);
206 PMC_CLASS_TABLE_DESC(tsc, TSC, tsc, tsc);
207 #endif
208 #if defined(__arm__)
209 PMC_CLASS_TABLE_DESC(cortex_a8, ARMV7, cortex_a8, armv7);
210 PMC_CLASS_TABLE_DESC(cortex_a9, ARMV7, cortex_a9, armv7);
211 #endif
212 #if defined(__aarch64__)
213 PMC_CLASS_TABLE_DESC(cortex_a53, ARMV8, cortex_a53, arm64);
214 PMC_CLASS_TABLE_DESC(cortex_a57, ARMV8, cortex_a57, arm64);
215 PMC_CLASS_TABLE_DESC(cortex_a76, ARMV8, cortex_a76, arm64);
216 PMC_CLASS_TABLE_DESC(cmn600_pmu, CMN600_PMU, cmn600_pmu, cmn600_pmu);
217 PMC_CLASS_TABLE_DESC(dmc620_pmu_cd2, DMC620_PMU_CD2, dmc620_pmu_cd2, dmc620_pmu);
218 PMC_CLASS_TABLE_DESC(dmc620_pmu_c, DMC620_PMU_C, dmc620_pmu_c, dmc620_pmu);
219 #endif
220 #if defined(__powerpc__)
221 PMC_CLASS_TABLE_DESC(ppc7450, PPC7450, ppc7450, powerpc);
222 PMC_CLASS_TABLE_DESC(ppc970, PPC970, ppc970, powerpc);
223 PMC_CLASS_TABLE_DESC(e500, E500, e500, powerpc);
224 #endif
225
226 static struct pmc_class_descr soft_class_table_descr =
227 {
228 .pm_evc_name = "SOFT-",
229 .pm_evc_name_size = sizeof("SOFT-") - 1,
230 .pm_evc_class = PMC_CLASS_SOFT,
231 .pm_evc_event_table = NULL,
232 .pm_evc_event_table_size = 0,
233 .pm_evc_allocate_pmc = soft_allocate_pmc
234 };
235
236 #undef PMC_CLASS_TABLE_DESC
237
238 static const struct pmc_class_descr **pmc_class_table;
239 #define PMC_CLASS_TABLE_SIZE cpu_info.pm_nclass
240
241 /*
242 * Mapping tables, mapping enumeration values to human readable
243 * strings.
244 */
245
246 static const char * pmc_capability_names[] = {
247 #undef __PMC_CAP
248 #define __PMC_CAP(N,V,D) #N ,
249 __PMC_CAPS()
250 };
251
252 struct pmc_class_map {
253 enum pmc_class pm_class;
254 const char *pm_name;
255 };
256
257 static const struct pmc_class_map pmc_class_names[] = {
258 #undef __PMC_CLASS
259 #define __PMC_CLASS(S,V,D) { .pm_class = PMC_CLASS_##S, .pm_name = #S } ,
260 __PMC_CLASSES()
261 };
262
263 struct pmc_cputype_map {
264 enum pmc_cputype pm_cputype;
265 const char *pm_name;
266 };
267
268 static const struct pmc_cputype_map pmc_cputype_names[] = {
269 #undef __PMC_CPU
270 #define __PMC_CPU(S, V, D) { .pm_cputype = PMC_CPU_##S, .pm_name = #S } ,
271 __PMC_CPUS()
272 };
273
274 static const char * pmc_disposition_names[] = {
275 #undef __PMC_DISP
276 #define __PMC_DISP(D) #D ,
277 __PMC_DISPOSITIONS()
278 };
279
280 static const char * pmc_mode_names[] = {
281 #undef __PMC_MODE
282 #define __PMC_MODE(M,N) #M ,
283 __PMC_MODES()
284 };
285
286 static const char * pmc_state_names[] = {
287 #undef __PMC_STATE
288 #define __PMC_STATE(S) #S ,
289 __PMC_STATES()
290 };
291
292 /*
293 * Filled in by pmc_init().
294 */
295 static int pmc_syscall = -1;
296 static struct pmc_cpuinfo cpu_info;
297 static struct pmc_op_getdyneventinfo soft_event_info;
298
299 /* Event masks for events */
300 struct pmc_masks {
301 const char *pm_name;
302 const uint64_t pm_value;
303 };
304 #define PMCMASK(N,V) { .pm_name = #N, .pm_value = (V) }
305 #define NULLMASK { .pm_name = NULL }
306
307 #if defined(__amd64__) || defined(__i386__)
308 static int
pmc_parse_mask(const struct pmc_masks * pmask,char * p,uint64_t * evmask)309 pmc_parse_mask(const struct pmc_masks *pmask, char *p, uint64_t *evmask)
310 {
311 const struct pmc_masks *pm;
312 char *q, *r;
313 int c;
314
315 if (pmask == NULL) /* no mask keywords */
316 return (-1);
317 q = strchr(p, '='); /* skip '=' */
318 if (*++q == '\0') /* no more data */
319 return (-1);
320 c = 0; /* count of mask keywords seen */
321 while ((r = strsep(&q, "+")) != NULL) {
322 for (pm = pmask; pm->pm_name && strcasecmp(r, pm->pm_name);
323 pm++)
324 ;
325 if (pm->pm_name == NULL) /* not found */
326 return (-1);
327 *evmask |= pm->pm_value;
328 c++;
329 }
330 return (c);
331 }
332 #endif
333
334 #define KWMATCH(p,kw) (strcasecmp((p), (kw)) == 0)
335 #define KWPREFIXMATCH(p,kw) (strncasecmp((p), (kw), sizeof((kw)) - 1) == 0)
336 #define EV_ALIAS(N,S) { .pm_alias = N, .pm_spec = S }
337
338 #if defined(__amd64__) || defined(__i386__)
339 /*
340 * AMD K8 PMCs.
341 *
342 */
343
344 static struct pmc_event_alias k8_aliases[] = {
345 EV_ALIAS("branches", "k8-fr-retired-taken-branches"),
346 EV_ALIAS("branch-mispredicts",
347 "k8-fr-retired-taken-branches-mispredicted"),
348 EV_ALIAS("cycles", "tsc"),
349 EV_ALIAS("dc-misses", "k8-dc-miss"),
350 EV_ALIAS("ic-misses", "k8-ic-miss"),
351 EV_ALIAS("instructions", "k8-fr-retired-x86-instructions"),
352 EV_ALIAS("interrupts", "k8-fr-taken-hardware-interrupts"),
353 EV_ALIAS("unhalted-cycles", "k8-bu-cpu-clk-unhalted"),
354 EV_ALIAS(NULL, NULL)
355 };
356
357 #define __K8MASK(N,V) PMCMASK(N,(1 << (V)))
358
359 /*
360 * Parsing tables
361 */
362
363 /* fp dispatched fpu ops */
364 static const struct pmc_masks k8_mask_fdfo[] = {
365 __K8MASK(add-pipe-excluding-junk-ops, 0),
366 __K8MASK(multiply-pipe-excluding-junk-ops, 1),
367 __K8MASK(store-pipe-excluding-junk-ops, 2),
368 __K8MASK(add-pipe-junk-ops, 3),
369 __K8MASK(multiply-pipe-junk-ops, 4),
370 __K8MASK(store-pipe-junk-ops, 5),
371 NULLMASK
372 };
373
374 /* ls segment register loads */
375 static const struct pmc_masks k8_mask_lsrl[] = {
376 __K8MASK(es, 0),
377 __K8MASK(cs, 1),
378 __K8MASK(ss, 2),
379 __K8MASK(ds, 3),
380 __K8MASK(fs, 4),
381 __K8MASK(gs, 5),
382 __K8MASK(hs, 6),
383 NULLMASK
384 };
385
386 /* ls locked operation */
387 static const struct pmc_masks k8_mask_llo[] = {
388 __K8MASK(locked-instructions, 0),
389 __K8MASK(cycles-in-request, 1),
390 __K8MASK(cycles-to-complete, 2),
391 NULLMASK
392 };
393
394 /* dc refill from {l2,system} and dc copyback */
395 static const struct pmc_masks k8_mask_dc[] = {
396 __K8MASK(invalid, 0),
397 __K8MASK(shared, 1),
398 __K8MASK(exclusive, 2),
399 __K8MASK(owner, 3),
400 __K8MASK(modified, 4),
401 NULLMASK
402 };
403
404 /* dc one bit ecc error */
405 static const struct pmc_masks k8_mask_dobee[] = {
406 __K8MASK(scrubber, 0),
407 __K8MASK(piggyback, 1),
408 NULLMASK
409 };
410
411 /* dc dispatched prefetch instructions */
412 static const struct pmc_masks k8_mask_ddpi[] = {
413 __K8MASK(load, 0),
414 __K8MASK(store, 1),
415 __K8MASK(nta, 2),
416 NULLMASK
417 };
418
419 /* dc dcache accesses by locks */
420 static const struct pmc_masks k8_mask_dabl[] = {
421 __K8MASK(accesses, 0),
422 __K8MASK(misses, 1),
423 NULLMASK
424 };
425
426 /* bu internal l2 request */
427 static const struct pmc_masks k8_mask_bilr[] = {
428 __K8MASK(ic-fill, 0),
429 __K8MASK(dc-fill, 1),
430 __K8MASK(tlb-reload, 2),
431 __K8MASK(tag-snoop, 3),
432 __K8MASK(cancelled, 4),
433 NULLMASK
434 };
435
436 /* bu fill request l2 miss */
437 static const struct pmc_masks k8_mask_bfrlm[] = {
438 __K8MASK(ic-fill, 0),
439 __K8MASK(dc-fill, 1),
440 __K8MASK(tlb-reload, 2),
441 NULLMASK
442 };
443
444 /* bu fill into l2 */
445 static const struct pmc_masks k8_mask_bfil[] = {
446 __K8MASK(dirty-l2-victim, 0),
447 __K8MASK(victim-from-l2, 1),
448 NULLMASK
449 };
450
451 /* fr retired fpu instructions */
452 static const struct pmc_masks k8_mask_frfi[] = {
453 __K8MASK(x87, 0),
454 __K8MASK(mmx-3dnow, 1),
455 __K8MASK(packed-sse-sse2, 2),
456 __K8MASK(scalar-sse-sse2, 3),
457 NULLMASK
458 };
459
460 /* fr retired fastpath double op instructions */
461 static const struct pmc_masks k8_mask_frfdoi[] = {
462 __K8MASK(low-op-pos-0, 0),
463 __K8MASK(low-op-pos-1, 1),
464 __K8MASK(low-op-pos-2, 2),
465 NULLMASK
466 };
467
468 /* fr fpu exceptions */
469 static const struct pmc_masks k8_mask_ffe[] = {
470 __K8MASK(x87-reclass-microfaults, 0),
471 __K8MASK(sse-retype-microfaults, 1),
472 __K8MASK(sse-reclass-microfaults, 2),
473 __K8MASK(sse-and-x87-microtraps, 3),
474 NULLMASK
475 };
476
477 /* nb memory controller page access event */
478 static const struct pmc_masks k8_mask_nmcpae[] = {
479 __K8MASK(page-hit, 0),
480 __K8MASK(page-miss, 1),
481 __K8MASK(page-conflict, 2),
482 NULLMASK
483 };
484
485 /* nb memory controller turnaround */
486 static const struct pmc_masks k8_mask_nmct[] = {
487 __K8MASK(dimm-turnaround, 0),
488 __K8MASK(read-to-write-turnaround, 1),
489 __K8MASK(write-to-read-turnaround, 2),
490 NULLMASK
491 };
492
493 /* nb memory controller bypass saturation */
494 static const struct pmc_masks k8_mask_nmcbs[] = {
495 __K8MASK(memory-controller-hi-pri-bypass, 0),
496 __K8MASK(memory-controller-lo-pri-bypass, 1),
497 __K8MASK(dram-controller-interface-bypass, 2),
498 __K8MASK(dram-controller-queue-bypass, 3),
499 NULLMASK
500 };
501
502 /* nb sized commands */
503 static const struct pmc_masks k8_mask_nsc[] = {
504 __K8MASK(nonpostwrszbyte, 0),
505 __K8MASK(nonpostwrszdword, 1),
506 __K8MASK(postwrszbyte, 2),
507 __K8MASK(postwrszdword, 3),
508 __K8MASK(rdszbyte, 4),
509 __K8MASK(rdszdword, 5),
510 __K8MASK(rdmodwr, 6),
511 NULLMASK
512 };
513
514 /* nb probe result */
515 static const struct pmc_masks k8_mask_npr[] = {
516 __K8MASK(probe-miss, 0),
517 __K8MASK(probe-hit, 1),
518 __K8MASK(probe-hit-dirty-no-memory-cancel, 2),
519 __K8MASK(probe-hit-dirty-with-memory-cancel, 3),
520 NULLMASK
521 };
522
523 /* nb hypertransport bus bandwidth */
524 static const struct pmc_masks k8_mask_nhbb[] = { /* HT bus bandwidth */
525 __K8MASK(command, 0),
526 __K8MASK(data, 1),
527 __K8MASK(buffer-release, 2),
528 __K8MASK(nop, 3),
529 NULLMASK
530 };
531
532 #undef __K8MASK
533
534 #define K8_KW_COUNT "count"
535 #define K8_KW_EDGE "edge"
536 #define K8_KW_INV "inv"
537 #define K8_KW_MASK "mask"
538 #define K8_KW_OS "os"
539 #define K8_KW_USR "usr"
540
541 static int
k8_allocate_pmc(enum pmc_event pe,char * ctrspec,struct pmc_op_pmcallocate * pmc_config)542 k8_allocate_pmc(enum pmc_event pe, char *ctrspec,
543 struct pmc_op_pmcallocate *pmc_config)
544 {
545 char *e, *p, *q;
546 int n;
547 uint32_t count;
548 uint64_t evmask;
549 const struct pmc_masks *pm, *pmask;
550
551 pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE);
552 pmc_config->pm_md.pm_amd.pm_amd_config = 0;
553
554 pmask = NULL;
555 evmask = 0;
556
557 #define __K8SETMASK(M) pmask = k8_mask_##M
558
559 /* setup parsing tables */
560 switch (pe) {
561 case PMC_EV_K8_FP_DISPATCHED_FPU_OPS:
562 __K8SETMASK(fdfo);
563 break;
564 case PMC_EV_K8_LS_SEGMENT_REGISTER_LOAD:
565 __K8SETMASK(lsrl);
566 break;
567 case PMC_EV_K8_LS_LOCKED_OPERATION:
568 __K8SETMASK(llo);
569 break;
570 case PMC_EV_K8_DC_REFILL_FROM_L2:
571 case PMC_EV_K8_DC_REFILL_FROM_SYSTEM:
572 case PMC_EV_K8_DC_COPYBACK:
573 __K8SETMASK(dc);
574 break;
575 case PMC_EV_K8_DC_ONE_BIT_ECC_ERROR:
576 __K8SETMASK(dobee);
577 break;
578 case PMC_EV_K8_DC_DISPATCHED_PREFETCH_INSTRUCTIONS:
579 __K8SETMASK(ddpi);
580 break;
581 case PMC_EV_K8_DC_DCACHE_ACCESSES_BY_LOCKS:
582 __K8SETMASK(dabl);
583 break;
584 case PMC_EV_K8_BU_INTERNAL_L2_REQUEST:
585 __K8SETMASK(bilr);
586 break;
587 case PMC_EV_K8_BU_FILL_REQUEST_L2_MISS:
588 __K8SETMASK(bfrlm);
589 break;
590 case PMC_EV_K8_BU_FILL_INTO_L2:
591 __K8SETMASK(bfil);
592 break;
593 case PMC_EV_K8_FR_RETIRED_FPU_INSTRUCTIONS:
594 __K8SETMASK(frfi);
595 break;
596 case PMC_EV_K8_FR_RETIRED_FASTPATH_DOUBLE_OP_INSTRUCTIONS:
597 __K8SETMASK(frfdoi);
598 break;
599 case PMC_EV_K8_FR_FPU_EXCEPTIONS:
600 __K8SETMASK(ffe);
601 break;
602 case PMC_EV_K8_NB_MEMORY_CONTROLLER_PAGE_ACCESS_EVENT:
603 __K8SETMASK(nmcpae);
604 break;
605 case PMC_EV_K8_NB_MEMORY_CONTROLLER_TURNAROUND:
606 __K8SETMASK(nmct);
607 break;
608 case PMC_EV_K8_NB_MEMORY_CONTROLLER_BYPASS_SATURATION:
609 __K8SETMASK(nmcbs);
610 break;
611 case PMC_EV_K8_NB_SIZED_COMMANDS:
612 __K8SETMASK(nsc);
613 break;
614 case PMC_EV_K8_NB_PROBE_RESULT:
615 __K8SETMASK(npr);
616 break;
617 case PMC_EV_K8_NB_HT_BUS0_BANDWIDTH:
618 case PMC_EV_K8_NB_HT_BUS1_BANDWIDTH:
619 case PMC_EV_K8_NB_HT_BUS2_BANDWIDTH:
620 __K8SETMASK(nhbb);
621 break;
622
623 default:
624 break; /* no options defined */
625 }
626
627 while ((p = strsep(&ctrspec, ",")) != NULL) {
628 if (KWPREFIXMATCH(p, K8_KW_COUNT "=")) {
629 q = strchr(p, '=');
630 if (*++q == '\0') /* skip '=' */
631 return (-1);
632
633 count = strtol(q, &e, 0);
634 if (e == q || *e != '\0')
635 return (-1);
636
637 pmc_config->pm_caps |= PMC_CAP_THRESHOLD;
638 pmc_config->pm_md.pm_amd.pm_amd_config |=
639 AMD_PMC_TO_COUNTER(count);
640
641 } else if (KWMATCH(p, K8_KW_EDGE)) {
642 pmc_config->pm_caps |= PMC_CAP_EDGE;
643 } else if (KWMATCH(p, K8_KW_INV)) {
644 pmc_config->pm_caps |= PMC_CAP_INVERT;
645 } else if (KWPREFIXMATCH(p, K8_KW_MASK "=")) {
646 if ((n = pmc_parse_mask(pmask, p, &evmask)) < 0)
647 return (-1);
648 pmc_config->pm_caps |= PMC_CAP_QUALIFIER;
649 } else if (KWMATCH(p, K8_KW_OS)) {
650 pmc_config->pm_caps |= PMC_CAP_SYSTEM;
651 } else if (KWMATCH(p, K8_KW_USR)) {
652 pmc_config->pm_caps |= PMC_CAP_USER;
653 } else
654 return (-1);
655 }
656
657 /* other post processing */
658 switch (pe) {
659 case PMC_EV_K8_FP_DISPATCHED_FPU_OPS:
660 case PMC_EV_K8_FP_CYCLES_WITH_NO_FPU_OPS_RETIRED:
661 case PMC_EV_K8_FP_DISPATCHED_FPU_FAST_FLAG_OPS:
662 case PMC_EV_K8_FR_RETIRED_FASTPATH_DOUBLE_OP_INSTRUCTIONS:
663 case PMC_EV_K8_FR_RETIRED_FPU_INSTRUCTIONS:
664 case PMC_EV_K8_FR_FPU_EXCEPTIONS:
665 /* XXX only available in rev B and later */
666 break;
667 case PMC_EV_K8_DC_DCACHE_ACCESSES_BY_LOCKS:
668 /* XXX only available in rev C and later */
669 break;
670 case PMC_EV_K8_LS_LOCKED_OPERATION:
671 /* XXX CPU Rev A,B evmask is to be zero */
672 if (evmask & (evmask - 1)) /* > 1 bit set */
673 return (-1);
674 if (evmask == 0) {
675 evmask = 0x01; /* Rev C and later: #instrs */
676 pmc_config->pm_caps |= PMC_CAP_QUALIFIER;
677 }
678 break;
679 default:
680 if (evmask == 0 && pmask != NULL) {
681 for (pm = pmask; pm->pm_name; pm++)
682 evmask |= pm->pm_value;
683 pmc_config->pm_caps |= PMC_CAP_QUALIFIER;
684 }
685 }
686
687 if (pmc_config->pm_caps & PMC_CAP_QUALIFIER)
688 pmc_config->pm_md.pm_amd.pm_amd_config =
689 AMD_PMC_TO_UNITMASK(evmask);
690
691 return (0);
692 }
693
694 static int
ibs_allocate_pmc(enum pmc_event pe,char * ctrspec,struct pmc_op_pmcallocate * pmc_config)695 ibs_allocate_pmc(enum pmc_event pe, char *ctrspec,
696 struct pmc_op_pmcallocate *pmc_config)
697 {
698 char *e, *p, *q;
699 uint64_t ctl, ldlat;
700
701 pmc_config->pm_caps |=
702 (PMC_CAP_SYSTEM | PMC_CAP_EDGE | PMC_CAP_PRECISE);
703 pmc_config->pm_md.pm_ibs.ibs_ctl = 0;
704
705 /* setup parsing tables */
706 switch (pe) {
707 case PMC_EV_IBS_FETCH:
708 pmc_config->pm_md.pm_ibs.ibs_type = IBS_PMC_FETCH;
709 break;
710 case PMC_EV_IBS_OP:
711 pmc_config->pm_md.pm_ibs.ibs_type = IBS_PMC_OP;
712 break;
713 default:
714 return (-1);
715 }
716
717 /* IBS only supports sampling mode */
718 if (!PMC_IS_SAMPLING_MODE(pmc_config->pm_mode)) {
719 return (-1);
720 }
721
722 /* parse parameters */
723 ctl = 0;
724 if (pe == PMC_EV_IBS_FETCH) {
725 while ((p = strsep(&ctrspec, ",")) != NULL) {
726 if (KWMATCH(p, "l3miss")) {
727 ctl |= IBS_FETCH_CTL_L3MISSONLY;
728 } else if (KWMATCH(p, "randomize")) {
729 ctl |= IBS_FETCH_CTL_RANDOMIZE;
730 } else {
731 return (-1);
732 }
733 }
734
735 if (pmc_config->pm_count < IBS_FETCH_MIN_RATE ||
736 pmc_config->pm_count > IBS_FETCH_MAX_RATE)
737 return (-1);
738
739 ctl |= IBS_FETCH_INTERVAL_TO_CTL(pmc_config->pm_count);
740 } else {
741 while ((p = strsep(&ctrspec, ",")) != NULL) {
742 if (KWMATCH(p, "l3miss")) {
743 ctl |= IBS_OP_CTL_L3MISSONLY;
744 } else if (KWPREFIXMATCH(p, "ldlat=")) {
745 q = strchr(p, '=');
746 if (*++q == '\0') /* skip '=' */
747 return (-1);
748
749 ldlat = strtoull(q, &e, 0);
750 if (e == q || *e != '\0')
751 return (-1);
752
753 /*
754 * IBS load latency filtering requires the
755 * latency to be a multiple of 128 and between
756 * 128 and 2048. The latency is stored in the
757 * IbsOpLatThrsh field, which only contains
758 * four bits so the processor computes
759 * (IbsOpLatThrsh+1)*128 as the value.
760 *
761 * AMD PPR Vol 1 for AMD Family 1Ah Model 02h
762 * C1 (57238) 2026-03-06 Revision 0.49.
763 */
764 if (ldlat < 128 || ldlat > 2048)
765 return (-1);
766 ctl |= IBS_OP_CTL_LDLAT_TO_CTL(ldlat);
767 ctl |= IBS_OP_CTL_L3MISSONLY | IBS_OP_CTL_LATFLTEN;
768 } else if (KWMATCH(p, "randomize")) {
769 ctl |= IBS_OP_CTL_COUNTERCONTROL;
770 } else {
771 return (-1);
772 }
773 }
774
775 if (pmc_config->pm_count < IBS_OP_MIN_RATE ||
776 pmc_config->pm_count > IBS_OP_MAX_RATE)
777 return (-1);
778
779 ctl |= IBS_OP_INTERVAL_TO_CTL(pmc_config->pm_count);
780 }
781
782
783 pmc_config->pm_md.pm_ibs.ibs_ctl |= ctl;
784
785 return (0);
786 }
787
788 static int
tsc_allocate_pmc(enum pmc_event pe,char * ctrspec,struct pmc_op_pmcallocate * pmc_config)789 tsc_allocate_pmc(enum pmc_event pe, char *ctrspec,
790 struct pmc_op_pmcallocate *pmc_config)
791 {
792 if (pe != PMC_EV_TSC_TSC)
793 return (-1);
794
795 /* TSC events must be unqualified. */
796 if (ctrspec && *ctrspec != '\0')
797 return (-1);
798
799 pmc_config->pm_md.pm_amd.pm_amd_config = 0;
800 pmc_config->pm_caps |= PMC_CAP_READ;
801
802 return (0);
803 }
804 #endif
805
806 static struct pmc_event_alias generic_aliases[] = {
807 EV_ALIAS("instructions", "SOFT-CLOCK.HARD"),
808 EV_ALIAS(NULL, NULL)
809 };
810
811 static int
soft_allocate_pmc(enum pmc_event pe,char * ctrspec,struct pmc_op_pmcallocate * pmc_config)812 soft_allocate_pmc(enum pmc_event pe, char *ctrspec,
813 struct pmc_op_pmcallocate *pmc_config)
814 {
815 (void)ctrspec;
816 (void)pmc_config;
817
818 if ((int)pe < PMC_EV_SOFT_FIRST || (int)pe > PMC_EV_SOFT_LAST)
819 return (-1);
820
821 pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE);
822 return (0);
823 }
824
825 #if defined(__arm__)
826 static struct pmc_event_alias cortex_a8_aliases[] = {
827 EV_ALIAS("dc-misses", "L1_DCACHE_REFILL"),
828 EV_ALIAS("ic-misses", "L1_ICACHE_REFILL"),
829 EV_ALIAS("instructions", "INSTR_EXECUTED"),
830 EV_ALIAS(NULL, NULL)
831 };
832
833 static struct pmc_event_alias cortex_a9_aliases[] = {
834 EV_ALIAS("dc-misses", "L1_DCACHE_REFILL"),
835 EV_ALIAS("ic-misses", "L1_ICACHE_REFILL"),
836 EV_ALIAS("instructions", "INSTR_EXECUTED"),
837 EV_ALIAS(NULL, NULL)
838 };
839
840 static int
armv7_allocate_pmc(enum pmc_event pe,char * ctrspec __unused,struct pmc_op_pmcallocate * pmc_config __unused)841 armv7_allocate_pmc(enum pmc_event pe, char *ctrspec __unused,
842 struct pmc_op_pmcallocate *pmc_config __unused)
843 {
844 switch (pe) {
845 default:
846 break;
847 }
848
849 return (0);
850 }
851 #endif
852
853 #if defined(__aarch64__)
854 static struct pmc_event_alias cortex_a53_aliases[] = {
855 EV_ALIAS(NULL, NULL)
856 };
857 static struct pmc_event_alias cortex_a57_aliases[] = {
858 EV_ALIAS(NULL, NULL)
859 };
860 static struct pmc_event_alias cortex_a76_aliases[] = {
861 EV_ALIAS(NULL, NULL)
862 };
863
864 static int
arm64_allocate_pmc(enum pmc_event pe,char * ctrspec,struct pmc_op_pmcallocate * pmc_config)865 arm64_allocate_pmc(enum pmc_event pe, char *ctrspec,
866 struct pmc_op_pmcallocate *pmc_config)
867 {
868 char *p;
869
870 while ((p = strsep(&ctrspec, ",")) != NULL) {
871 if (KWMATCH(p, "os"))
872 pmc_config->pm_caps |= PMC_CAP_SYSTEM;
873 else if (KWMATCH(p, "usr"))
874 pmc_config->pm_caps |= PMC_CAP_USER;
875 else
876 return (-1);
877 }
878
879 return (0);
880 }
881
882 static int
cmn600_pmu_allocate_pmc(enum pmc_event pe,char * ctrspec,struct pmc_op_pmcallocate * pmc_config)883 cmn600_pmu_allocate_pmc(enum pmc_event pe, char *ctrspec,
884 struct pmc_op_pmcallocate *pmc_config)
885 {
886 uint32_t nodeid, occupancy, xpport, xpchannel;
887 char *e, *p, *q;
888 unsigned int i;
889 char *xpport_names[] = { "East", "West", "North", "South", "devport0",
890 "devport1" };
891 char *xpchannel_names[] = { "REQ", "RSP", "SNP", "DAT" };
892
893 pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE);
894 pmc_config->pm_caps |= PMC_CAP_SYSTEM;
895 pmc_config->pm_md.pm_cmn600.pma_cmn600_config = 0;
896 /*
897 * CMN600 extra fields:
898 * * nodeid - node coordinates x[2-3],y[2-3],p[1],s[2]
899 * width of x and y fields depend on matrix size.
900 * * occupancy - numeric value to select desired filter.
901 * * xpport - East, West, North, South, devport0, devport1 (or 0, 1, ..., 5)
902 * * xpchannel - REQ, RSP, SNP, DAT (or 0, 1, 2, 3)
903 */
904
905 while ((p = strsep(&ctrspec, ",")) != NULL) {
906 if (KWPREFIXMATCH(p, "nodeid=")) {
907 q = strchr(p, '=');
908 if (*++q == '\0') /* skip '=' */
909 return (-1);
910
911 nodeid = strtol(q, &e, 0);
912 if (e == q || *e != '\0')
913 return (-1);
914
915 pmc_config->pm_md.pm_cmn600.pma_cmn600_nodeid |= nodeid;
916
917 } else if (KWPREFIXMATCH(p, "occupancy=")) {
918 q = strchr(p, '=');
919 if (*++q == '\0') /* skip '=' */
920 return (-1);
921
922 occupancy = strtol(q, &e, 0);
923 if (e == q || *e != '\0')
924 return (-1);
925
926 pmc_config->pm_md.pm_cmn600.pma_cmn600_occupancy = occupancy;
927 } else if (KWPREFIXMATCH(p, "xpport=")) {
928 q = strchr(p, '=');
929 if (*++q == '\0') /* skip '=' */
930 return (-1);
931
932 xpport = strtol(q, &e, 0);
933 if (e == q || *e != '\0') {
934 for (i = 0; i < nitems(xpport_names); i++) {
935 if (strcasecmp(xpport_names[i], q) == 0) {
936 xpport = i;
937 break;
938 }
939 }
940 if (i == nitems(xpport_names))
941 return (-1);
942 }
943
944 pmc_config->pm_md.pm_cmn600.pma_cmn600_config |= xpport << 2;
945 } else if (KWPREFIXMATCH(p, "xpchannel=")) {
946 q = strchr(p, '=');
947 if (*++q == '\0') /* skip '=' */
948 return (-1);
949
950 xpchannel = strtol(q, &e, 0);
951 if (e == q || *e != '\0') {
952 for (i = 0; i < nitems(xpchannel_names); i++) {
953 if (strcasecmp(xpchannel_names[i], q) == 0) {
954 xpchannel = i;
955 break;
956 }
957 }
958 if (i == nitems(xpchannel_names))
959 return (-1);
960 }
961
962 pmc_config->pm_md.pm_cmn600.pma_cmn600_config |= xpchannel << 5;
963 } else
964 return (-1);
965 }
966
967 return (0);
968 }
969
970 static int
dmc620_pmu_allocate_pmc(enum pmc_event pe,char * ctrspec,struct pmc_op_pmcallocate * pmc_config)971 dmc620_pmu_allocate_pmc(enum pmc_event pe, char *ctrspec,
972 struct pmc_op_pmcallocate *pmc_config)
973 {
974 char *e, *p, *q;
975 uint64_t match, mask;
976 uint32_t count;
977
978 pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE);
979 pmc_config->pm_caps |= PMC_CAP_SYSTEM;
980 pmc_config->pm_md.pm_dmc620.pm_dmc620_config = 0;
981
982 while ((p = strsep(&ctrspec, ",")) != NULL) {
983 if (KWPREFIXMATCH(p, "count=")) {
984 q = strchr(p, '=');
985 if (*++q == '\0') /* skip '=' */
986 return (-1);
987
988 count = strtol(q, &e, 0);
989 if (e == q || *e != '\0')
990 return (-1);
991
992 pmc_config->pm_caps |= PMC_CAP_THRESHOLD;
993 pmc_config->pm_md.pm_dmc620.pm_dmc620_config |= count;
994
995 } else if (KWMATCH(p, "inv")) {
996 pmc_config->pm_caps |= PMC_CAP_INVERT;
997 } else if (KWPREFIXMATCH(p, "match=")) {
998 match = strtol(q, &e, 0);
999 if (e == q || *e != '\0')
1000 return (-1);
1001
1002 pmc_config->pm_caps |= PMC_CAP_QUALIFIER;
1003 pmc_config->pm_md.pm_dmc620.pm_dmc620_match = match;
1004 } else if (KWPREFIXMATCH(p, "mask=")) {
1005 q = strchr(p, '=');
1006 if (*++q == '\0') /* skip '=' */
1007 return (-1);
1008
1009 mask = strtol(q, &e, 0);
1010 if (e == q || *e != '\0')
1011 return (-1);
1012
1013 pmc_config->pm_md.pm_dmc620.pm_dmc620_mask = mask;
1014 pmc_config->pm_caps |= PMC_CAP_QUALIFIER;
1015 } else
1016 return (-1);
1017 }
1018
1019 return (0);
1020 }
1021 #endif
1022
1023 #if defined(__powerpc__)
1024
1025 static struct pmc_event_alias ppc7450_aliases[] = {
1026 EV_ALIAS("instructions", "INSTR_COMPLETED"),
1027 EV_ALIAS("branches", "BRANCHES_COMPLETED"),
1028 EV_ALIAS("branch-mispredicts", "MISPREDICTED_BRANCHES"),
1029 EV_ALIAS(NULL, NULL)
1030 };
1031
1032 static struct pmc_event_alias ppc970_aliases[] = {
1033 EV_ALIAS("instructions", "INSTR_COMPLETED"),
1034 EV_ALIAS("cycles", "CYCLES"),
1035 EV_ALIAS(NULL, NULL)
1036 };
1037
1038 static struct pmc_event_alias e500_aliases[] = {
1039 EV_ALIAS("instructions", "INSTR_COMPLETED"),
1040 EV_ALIAS("cycles", "CYCLES"),
1041 EV_ALIAS(NULL, NULL)
1042 };
1043
1044 #define POWERPC_KW_OS "os"
1045 #define POWERPC_KW_USR "usr"
1046 #define POWERPC_KW_ANYTHREAD "anythread"
1047
1048 static int
powerpc_allocate_pmc(enum pmc_event pe,char * ctrspec __unused,struct pmc_op_pmcallocate * pmc_config __unused)1049 powerpc_allocate_pmc(enum pmc_event pe, char *ctrspec __unused,
1050 struct pmc_op_pmcallocate *pmc_config __unused)
1051 {
1052 char *p;
1053
1054 (void) pe;
1055
1056 pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE);
1057
1058 while ((p = strsep(&ctrspec, ",")) != NULL) {
1059 if (KWMATCH(p, POWERPC_KW_OS))
1060 pmc_config->pm_caps |= PMC_CAP_SYSTEM;
1061 else if (KWMATCH(p, POWERPC_KW_USR))
1062 pmc_config->pm_caps |= PMC_CAP_USER;
1063 else if (KWMATCH(p, POWERPC_KW_ANYTHREAD))
1064 pmc_config->pm_caps |= (PMC_CAP_USER | PMC_CAP_SYSTEM);
1065 else
1066 return (-1);
1067 }
1068
1069 return (0);
1070 }
1071
1072 #endif /* __powerpc__ */
1073
1074
1075 /*
1076 * Match an event name `name' with its canonical form.
1077 *
1078 * Matches are case insensitive and spaces, periods, underscores and
1079 * hyphen characters are considered to match each other.
1080 *
1081 * Returns 1 for a match, 0 otherwise.
1082 */
1083
1084 static int
pmc_match_event_name(const char * name,const char * canonicalname)1085 pmc_match_event_name(const char *name, const char *canonicalname)
1086 {
1087 int cc, nc;
1088 const unsigned char *c, *n;
1089
1090 c = (const unsigned char *) canonicalname;
1091 n = (const unsigned char *) name;
1092
1093 for (; (nc = *n) && (cc = *c); n++, c++) {
1094
1095 if ((nc == ' ' || nc == '_' || nc == '-' || nc == '.') &&
1096 (cc == ' ' || cc == '_' || cc == '-' || cc == '.'))
1097 continue;
1098
1099 if (toupper(nc) == toupper(cc))
1100 continue;
1101
1102
1103 return (0);
1104 }
1105
1106 if (*n == '\0' && *c == '\0')
1107 return (1);
1108
1109 return (0);
1110 }
1111
1112 /*
1113 * Match an event name against all the event named supported by a
1114 * PMC class.
1115 *
1116 * Returns an event descriptor pointer on match or NULL otherwise.
1117 */
1118 static const struct pmc_event_descr *
pmc_match_event_class(const char * name,const struct pmc_class_descr * pcd)1119 pmc_match_event_class(const char *name,
1120 const struct pmc_class_descr *pcd)
1121 {
1122 size_t n;
1123 const struct pmc_event_descr *ev;
1124
1125 ev = pcd->pm_evc_event_table;
1126 for (n = 0; n < pcd->pm_evc_event_table_size; n++, ev++)
1127 if (pmc_match_event_name(name, ev->pm_ev_name))
1128 return (ev);
1129
1130 return (NULL);
1131 }
1132
1133 /*
1134 * API entry points
1135 */
1136
1137 int
pmc_allocate(const char * ctrspec,enum pmc_mode mode,uint32_t flags,int cpu,pmc_id_t * pmcid,uint64_t count)1138 pmc_allocate(const char *ctrspec, enum pmc_mode mode,
1139 uint32_t flags, int cpu, pmc_id_t *pmcid,
1140 uint64_t count)
1141 {
1142 size_t n;
1143 int retval;
1144 char *r, *spec_copy;
1145 const char *ctrname;
1146 const struct pmc_event_descr *ev;
1147 const struct pmc_event_alias *alias;
1148 struct pmc_op_pmcallocate pmc_config;
1149 const struct pmc_class_descr *pcd;
1150
1151 spec_copy = NULL;
1152 retval = -1;
1153
1154 if (mode != PMC_MODE_SS && mode != PMC_MODE_TS &&
1155 mode != PMC_MODE_SC && mode != PMC_MODE_TC) {
1156 errno = EINVAL;
1157 goto out;
1158 }
1159 bzero(&pmc_config, sizeof(pmc_config));
1160 pmc_config.pm_cpu = cpu;
1161 pmc_config.pm_mode = mode;
1162 pmc_config.pm_flags = flags;
1163 pmc_config.pm_count = count;
1164 if (PMC_IS_SAMPLING_MODE(mode))
1165 pmc_config.pm_caps |= PMC_CAP_INTERRUPT;
1166
1167 /*
1168 * Try to pull the raw event ID directly from the pmu-events table. If
1169 * this is unsupported on the platform, or the event is not found,
1170 * continue with searching the regular event tables.
1171 */
1172 r = spec_copy = strdup(ctrspec);
1173 ctrname = strsep(&r, ",");
1174 if (pmc_pmu_enabled()) {
1175 errno = pmc_pmu_pmcallocate(ctrname, &pmc_config);
1176 if (errno == 0)
1177 goto found;
1178 if (errno == EOPNOTSUPP)
1179 goto out;
1180 }
1181 free(spec_copy);
1182 spec_copy = NULL;
1183
1184 /* replace an event alias with the canonical event specifier */
1185 if (pmc_mdep_event_aliases)
1186 for (alias = pmc_mdep_event_aliases; alias->pm_alias; alias++)
1187 if (!strcasecmp(ctrspec, alias->pm_alias)) {
1188 spec_copy = strdup(alias->pm_spec);
1189 break;
1190 }
1191
1192 if (spec_copy == NULL)
1193 spec_copy = strdup(ctrspec);
1194
1195 r = spec_copy;
1196 ctrname = strsep(&r, ",");
1197
1198 /*
1199 * If a explicit class prefix was given by the user, restrict the
1200 * search for the event to the specified PMC class.
1201 */
1202 ev = NULL;
1203 for (n = 0; n < PMC_CLASS_TABLE_SIZE; n++) {
1204 pcd = pmc_class_table[n];
1205 if (pcd != NULL && strncasecmp(ctrname, pcd->pm_evc_name,
1206 pcd->pm_evc_name_size) == 0) {
1207 if ((ev = pmc_match_event_class(ctrname +
1208 pcd->pm_evc_name_size, pcd)) == NULL) {
1209 errno = EINVAL;
1210 goto out;
1211 }
1212 break;
1213 }
1214 }
1215
1216 /*
1217 * Otherwise, search for this event in all compatible PMC
1218 * classes.
1219 */
1220 for (n = 0; ev == NULL && n < PMC_CLASS_TABLE_SIZE; n++) {
1221 pcd = pmc_class_table[n];
1222 if (pcd != NULL)
1223 ev = pmc_match_event_class(ctrname, pcd);
1224 }
1225
1226 if (ev == NULL) {
1227 errno = EINVAL;
1228 goto out;
1229 }
1230
1231 pmc_config.pm_ev = ev->pm_ev_code;
1232 pmc_config.pm_class = pcd->pm_evc_class;
1233
1234 if (pcd->pm_evc_allocate_pmc(ev->pm_ev_code, r, &pmc_config) < 0) {
1235 errno = EINVAL;
1236 goto out;
1237 }
1238
1239 found:
1240 if (PMC_CALL(PMC_OP_PMCALLOCATE, &pmc_config) == 0) {
1241 *pmcid = pmc_config.pm_pmcid;
1242 retval = 0;
1243 }
1244 out:
1245 if (spec_copy)
1246 free(spec_copy);
1247
1248 return (retval);
1249 }
1250
1251 int
pmc_attach(pmc_id_t pmc,pid_t pid)1252 pmc_attach(pmc_id_t pmc, pid_t pid)
1253 {
1254 struct pmc_op_pmcattach pmc_attach_args;
1255
1256 pmc_attach_args.pm_pmc = pmc;
1257 pmc_attach_args.pm_pid = pid;
1258
1259 return (PMC_CALL(PMC_OP_PMCATTACH, &pmc_attach_args));
1260 }
1261
1262 int
pmc_capabilities(pmc_id_t pmcid,uint32_t * caps)1263 pmc_capabilities(pmc_id_t pmcid, uint32_t *caps)
1264 {
1265 struct pmc_op_caps args;
1266 int status;
1267
1268 args.pm_pmcid = pmcid;
1269 args.pm_caps = 0;
1270
1271 status = PMC_CALL(PMC_OP_GETCAPS, &args);
1272 *caps = args.pm_caps;
1273
1274 return (status);
1275 }
1276
1277 int
pmc_configure_logfile(int fd)1278 pmc_configure_logfile(int fd)
1279 {
1280 struct pmc_op_configurelog cla;
1281
1282 cla.pm_flags = 0;
1283 cla.pm_logfd = fd;
1284 if (PMC_CALL(PMC_OP_CONFIGURELOG, &cla) < 0)
1285 return (-1);
1286 return (0);
1287 }
1288
1289 int
pmc_cpuinfo(const struct pmc_cpuinfo ** pci)1290 pmc_cpuinfo(const struct pmc_cpuinfo **pci)
1291 {
1292 if (pmc_syscall == -1) {
1293 errno = ENXIO;
1294 return (-1);
1295 }
1296
1297 *pci = &cpu_info;
1298 return (0);
1299 }
1300
1301 int
pmc_detach(pmc_id_t pmc,pid_t pid)1302 pmc_detach(pmc_id_t pmc, pid_t pid)
1303 {
1304 struct pmc_op_pmcattach pmc_detach_args;
1305
1306 pmc_detach_args.pm_pmc = pmc;
1307 pmc_detach_args.pm_pid = pid;
1308 return (PMC_CALL(PMC_OP_PMCDETACH, &pmc_detach_args));
1309 }
1310
1311 int
pmc_disable(int cpu,int pmc)1312 pmc_disable(int cpu, int pmc)
1313 {
1314 struct pmc_op_pmcadmin ssa;
1315
1316 ssa.pm_cpu = cpu;
1317 ssa.pm_pmc = pmc;
1318 ssa.pm_state = PMC_STATE_DISABLED;
1319 return (PMC_CALL(PMC_OP_PMCADMIN, &ssa));
1320 }
1321
1322 int
pmc_enable(int cpu,int pmc)1323 pmc_enable(int cpu, int pmc)
1324 {
1325 struct pmc_op_pmcadmin ssa;
1326
1327 ssa.pm_cpu = cpu;
1328 ssa.pm_pmc = pmc;
1329 ssa.pm_state = PMC_STATE_FREE;
1330 return (PMC_CALL(PMC_OP_PMCADMIN, &ssa));
1331 }
1332
1333 /*
1334 * Return a list of events known to a given PMC class. 'cl' is the
1335 * PMC class identifier, 'eventnames' is the returned list of 'const
1336 * char *' pointers pointing to the names of the events. 'nevents' is
1337 * the number of event name pointers returned.
1338 *
1339 * The space for 'eventnames' is allocated using malloc(3). The caller
1340 * is responsible for freeing this space when done.
1341 */
1342 int
pmc_event_names_of_class(enum pmc_class cl,const char *** eventnames,int * nevents)1343 pmc_event_names_of_class(enum pmc_class cl, const char ***eventnames,
1344 int *nevents)
1345 {
1346 int count;
1347 const char **names;
1348 const struct pmc_event_descr *ev;
1349
1350 switch (cl)
1351 {
1352 case PMC_CLASS_IAF:
1353 ev = iaf_event_table;
1354 count = PMC_EVENT_TABLE_SIZE(iaf);
1355 break;
1356 case PMC_CLASS_TSC:
1357 ev = tsc_event_table;
1358 count = PMC_EVENT_TABLE_SIZE(tsc);
1359 break;
1360 case PMC_CLASS_K8:
1361 ev = k8_event_table;
1362 count = PMC_EVENT_TABLE_SIZE(k8);
1363 break;
1364 case PMC_CLASS_IBS:
1365 ev = ibs_event_table;
1366 count = PMC_EVENT_TABLE_SIZE(ibs);
1367 break;
1368 case PMC_CLASS_ARMV7:
1369 switch (cpu_info.pm_cputype) {
1370 default:
1371 case PMC_CPU_ARMV7_CORTEX_A8:
1372 ev = cortex_a8_event_table;
1373 count = PMC_EVENT_TABLE_SIZE(cortex_a8);
1374 break;
1375 case PMC_CPU_ARMV7_CORTEX_A9:
1376 ev = cortex_a9_event_table;
1377 count = PMC_EVENT_TABLE_SIZE(cortex_a9);
1378 break;
1379 }
1380 break;
1381 case PMC_CLASS_ARMV8:
1382 switch (cpu_info.pm_cputype) {
1383 default:
1384 case PMC_CPU_ARMV8_CORTEX_A53:
1385 ev = cortex_a53_event_table;
1386 count = PMC_EVENT_TABLE_SIZE(cortex_a53);
1387 break;
1388 case PMC_CPU_ARMV8_CORTEX_A57:
1389 ev = cortex_a57_event_table;
1390 count = PMC_EVENT_TABLE_SIZE(cortex_a57);
1391 break;
1392 case PMC_CPU_ARMV8_CORTEX_A76:
1393 ev = cortex_a76_event_table;
1394 count = PMC_EVENT_TABLE_SIZE(cortex_a76);
1395 break;
1396 }
1397 break;
1398 case PMC_CLASS_CMN600_PMU:
1399 ev = cmn600_pmu_event_table;
1400 count = PMC_EVENT_TABLE_SIZE(cmn600_pmu);
1401 break;
1402 case PMC_CLASS_DMC620_PMU_CD2:
1403 ev = dmc620_pmu_cd2_event_table;
1404 count = PMC_EVENT_TABLE_SIZE(dmc620_pmu_cd2);
1405 break;
1406 case PMC_CLASS_DMC620_PMU_C:
1407 ev = dmc620_pmu_c_event_table;
1408 count = PMC_EVENT_TABLE_SIZE(dmc620_pmu_c);
1409 break;
1410 case PMC_CLASS_PPC7450:
1411 ev = ppc7450_event_table;
1412 count = PMC_EVENT_TABLE_SIZE(ppc7450);
1413 break;
1414 case PMC_CLASS_PPC970:
1415 ev = ppc970_event_table;
1416 count = PMC_EVENT_TABLE_SIZE(ppc970);
1417 break;
1418 case PMC_CLASS_E500:
1419 ev = e500_event_table;
1420 count = PMC_EVENT_TABLE_SIZE(e500);
1421 break;
1422 case PMC_CLASS_SOFT:
1423 ev = soft_event_table;
1424 count = soft_event_info.pm_nevent;
1425 break;
1426 default:
1427 errno = EINVAL;
1428 return (-1);
1429 }
1430
1431 if ((names = malloc(count * sizeof(const char *))) == NULL)
1432 return (-1);
1433
1434 *eventnames = names;
1435 *nevents = count;
1436
1437 for (;count--; ev++, names++)
1438 *names = ev->pm_ev_name;
1439
1440 return (0);
1441 }
1442
1443 int
pmc_flush_logfile(void)1444 pmc_flush_logfile(void)
1445 {
1446 return (PMC_CALL(PMC_OP_FLUSHLOG, 0));
1447 }
1448
1449 int
pmc_close_logfile(void)1450 pmc_close_logfile(void)
1451 {
1452 return (PMC_CALL(PMC_OP_CLOSELOG, 0));
1453 }
1454
1455 int
pmc_get_driver_stats(struct pmc_driverstats * ds)1456 pmc_get_driver_stats(struct pmc_driverstats *ds)
1457 {
1458 struct pmc_op_getdriverstats gms;
1459
1460 if (PMC_CALL(PMC_OP_GETDRIVERSTATS, &gms) < 0)
1461 return (-1);
1462
1463 /* copy out fields in the current userland<->library interface */
1464 ds->pm_intr_ignored = gms.pm_intr_ignored;
1465 ds->pm_intr_processed = gms.pm_intr_processed;
1466 ds->pm_intr_bufferfull = gms.pm_intr_bufferfull;
1467 ds->pm_syscalls = gms.pm_syscalls;
1468 ds->pm_syscall_errors = gms.pm_syscall_errors;
1469 ds->pm_buffer_requests = gms.pm_buffer_requests;
1470 ds->pm_buffer_requests_failed = gms.pm_buffer_requests_failed;
1471 ds->pm_log_sweeps = gms.pm_log_sweeps;
1472 return (0);
1473 }
1474
1475 int
pmc_get_msr(pmc_id_t pmc,uint32_t * msr)1476 pmc_get_msr(pmc_id_t pmc, uint32_t *msr)
1477 {
1478 struct pmc_op_getmsr gm;
1479
1480 gm.pm_pmcid = pmc;
1481 if (PMC_CALL(PMC_OP_PMCGETMSR, &gm) < 0)
1482 return (-1);
1483 *msr = gm.pm_msr;
1484 return (0);
1485 }
1486
1487 int
pmc_init(void)1488 pmc_init(void)
1489 {
1490 int error, pmc_mod_id;
1491 unsigned int n;
1492 uint32_t abi_version;
1493 struct module_stat pmc_modstat;
1494 struct pmc_op_getcpuinfo op_cpu_info;
1495
1496 if (pmc_syscall != -1) /* already inited */
1497 return (0);
1498
1499 /* retrieve the system call number from the KLD */
1500 if ((pmc_mod_id = modfind(PMC_MODULE_NAME)) < 0)
1501 return (-1);
1502
1503 pmc_modstat.version = sizeof(struct module_stat);
1504 if ((error = modstat(pmc_mod_id, &pmc_modstat)) < 0)
1505 return (-1);
1506
1507 pmc_syscall = pmc_modstat.data.intval;
1508
1509 /* check the kernel module's ABI against our compiled-in version */
1510 abi_version = PMC_VERSION;
1511 if (PMC_CALL(PMC_OP_GETMODULEVERSION, &abi_version) < 0)
1512 return (pmc_syscall = -1);
1513
1514 /* ignore patch & minor numbers for the comparison */
1515 if ((abi_version & 0xFF000000) != (PMC_VERSION & 0xFF000000)) {
1516 errno = EPROGMISMATCH;
1517 return (pmc_syscall = -1);
1518 }
1519
1520 bzero(&op_cpu_info, sizeof(op_cpu_info));
1521 if (PMC_CALL(PMC_OP_GETCPUINFO, &op_cpu_info) < 0)
1522 return (pmc_syscall = -1);
1523
1524 cpu_info.pm_cputype = op_cpu_info.pm_cputype;
1525 cpu_info.pm_ncpu = op_cpu_info.pm_ncpu;
1526 cpu_info.pm_npmc = op_cpu_info.pm_npmc;
1527 cpu_info.pm_nclass = op_cpu_info.pm_nclass;
1528 for (n = 0; n < op_cpu_info.pm_nclass; n++)
1529 memcpy(&cpu_info.pm_classes[n], &op_cpu_info.pm_classes[n],
1530 sizeof(cpu_info.pm_classes[n]));
1531
1532 pmc_class_table = calloc(PMC_CLASS_TABLE_SIZE,
1533 sizeof(struct pmc_class_descr *));
1534
1535 if (pmc_class_table == NULL)
1536 return (-1);
1537
1538 /*
1539 * Get soft events list.
1540 */
1541 soft_event_info.pm_class = PMC_CLASS_SOFT;
1542 if (PMC_CALL(PMC_OP_GETDYNEVENTINFO, &soft_event_info) < 0)
1543 return (pmc_syscall = -1);
1544
1545 /* Map soft events to static list. */
1546 for (n = 0; n < soft_event_info.pm_nevent; n++) {
1547 soft_event_table[n].pm_ev_name =
1548 soft_event_info.pm_events[n].pm_ev_name;
1549 soft_event_table[n].pm_ev_code =
1550 soft_event_info.pm_events[n].pm_ev_code;
1551 }
1552 soft_class_table_descr.pm_evc_event_table_size = \
1553 soft_event_info.pm_nevent;
1554 soft_class_table_descr.pm_evc_event_table = \
1555 soft_event_table;
1556
1557 /*
1558 * Fill in the class table.
1559 */
1560 n = 0;
1561 for (unsigned i = 0; i < PMC_CLASS_TABLE_SIZE; i++) {
1562 switch (cpu_info.pm_classes[i].pm_class) {
1563 #if defined(__amd64__) || defined(__i386__)
1564 case PMC_CLASS_TSC:
1565 pmc_class_table[n++] = &tsc_class_table_descr;
1566 break;
1567
1568 case PMC_CLASS_K8:
1569 pmc_class_table[n++] = &k8_class_table_descr;
1570 break;
1571
1572 case PMC_CLASS_IBS:
1573 pmc_class_table[n++] = &ibs_class_table_descr;
1574 break;
1575 #endif
1576
1577 case PMC_CLASS_SOFT:
1578 pmc_class_table[n++] = &soft_class_table_descr;
1579 break;
1580
1581 #if defined(__arm__)
1582 case PMC_CLASS_ARMV7:
1583 switch (cpu_info.pm_cputype) {
1584 case PMC_CPU_ARMV7_CORTEX_A8:
1585 pmc_class_table[n++] =
1586 &cortex_a8_class_table_descr;
1587 break;
1588 case PMC_CPU_ARMV7_CORTEX_A9:
1589 pmc_class_table[n++] =
1590 &cortex_a9_class_table_descr;
1591 break;
1592 default:
1593 errno = ENXIO;
1594 return (pmc_syscall = -1);
1595 }
1596 break;
1597 #endif
1598
1599 #if defined(__aarch64__)
1600 case PMC_CLASS_ARMV8:
1601 switch (cpu_info.pm_cputype) {
1602 case PMC_CPU_ARMV8_CORTEX_A53:
1603 pmc_class_table[n++] =
1604 &cortex_a53_class_table_descr;
1605 break;
1606 case PMC_CPU_ARMV8_CORTEX_A57:
1607 pmc_class_table[n++] =
1608 &cortex_a57_class_table_descr;
1609 break;
1610 case PMC_CPU_ARMV8_CORTEX_A76:
1611 pmc_class_table[n++] =
1612 &cortex_a76_class_table_descr;
1613 break;
1614 default:
1615 errno = ENXIO;
1616 return (pmc_syscall = -1);
1617 }
1618 break;
1619
1620 case PMC_CLASS_DMC620_PMU_CD2:
1621 pmc_class_table[n++] =
1622 &dmc620_pmu_cd2_class_table_descr;
1623 break;
1624
1625 case PMC_CLASS_DMC620_PMU_C:
1626 pmc_class_table[n++] = &dmc620_pmu_c_class_table_descr;
1627 break;
1628
1629 case PMC_CLASS_CMN600_PMU:
1630 pmc_class_table[n++] = &cmn600_pmu_class_table_descr;
1631 break;
1632 #endif
1633
1634 #if defined(__powerpc__)
1635 case PMC_CLASS_PPC7450:
1636 pmc_class_table[n++] = &ppc7450_class_table_descr;
1637 break;
1638
1639 case PMC_CLASS_PPC970:
1640 pmc_class_table[n++] = &ppc970_class_table_descr;
1641 break;
1642
1643 case PMC_CLASS_E500:
1644 pmc_class_table[n++] = &e500_class_table_descr;
1645 break;
1646 #endif
1647
1648 default:
1649 #if defined(DEBUG)
1650 printf("pm_class: 0x%x\n",
1651 cpu_info.pm_classes[i].pm_class);
1652 #endif
1653 break;
1654 }
1655 }
1656
1657 #define PMC_MDEP_INIT(C) pmc_mdep_event_aliases = C##_aliases
1658
1659 /* Configure the event name parser. */
1660 switch (cpu_info.pm_cputype) {
1661 #if defined(__amd64__) || defined(__i386__)
1662 case PMC_CPU_AMD_K8:
1663 PMC_MDEP_INIT(k8);
1664 break;
1665 #endif
1666 case PMC_CPU_GENERIC:
1667 PMC_MDEP_INIT(generic);
1668 break;
1669 #if defined(__arm__)
1670 case PMC_CPU_ARMV7_CORTEX_A8:
1671 PMC_MDEP_INIT(cortex_a8);
1672 break;
1673 case PMC_CPU_ARMV7_CORTEX_A9:
1674 PMC_MDEP_INIT(cortex_a9);
1675 break;
1676 #endif
1677 #if defined(__aarch64__)
1678 case PMC_CPU_ARMV8_CORTEX_A53:
1679 PMC_MDEP_INIT(cortex_a53);
1680 break;
1681 case PMC_CPU_ARMV8_CORTEX_A57:
1682 PMC_MDEP_INIT(cortex_a57);
1683 break;
1684 case PMC_CPU_ARMV8_CORTEX_A76:
1685 PMC_MDEP_INIT(cortex_a76);
1686 break;
1687 #endif
1688 #if defined(__powerpc__)
1689 case PMC_CPU_PPC_7450:
1690 PMC_MDEP_INIT(ppc7450);
1691 break;
1692 case PMC_CPU_PPC_970:
1693 PMC_MDEP_INIT(ppc970);
1694 break;
1695 case PMC_CPU_PPC_E500:
1696 PMC_MDEP_INIT(e500);
1697 break;
1698 #endif
1699 default:
1700 /*
1701 * Some kind of CPU this version of the library knows nothing
1702 * about. This shouldn't happen since the abi version check
1703 * should have caught this.
1704 */
1705 #if defined(__amd64__) || defined(__i386__) || defined(__powerpc64__)
1706 break;
1707 #endif
1708 errno = ENXIO;
1709 return (pmc_syscall = -1);
1710 }
1711
1712 return (0);
1713 }
1714
1715 const char *
pmc_name_of_capability(enum pmc_caps cap)1716 pmc_name_of_capability(enum pmc_caps cap)
1717 {
1718 int i;
1719
1720 /*
1721 * 'cap' should have a single bit set and should be in
1722 * range.
1723 */
1724 if ((cap & (cap - 1)) || cap < PMC_CAP_FIRST ||
1725 cap > PMC_CAP_LAST) {
1726 errno = EINVAL;
1727 return (NULL);
1728 }
1729
1730 i = ffs(cap);
1731 return (pmc_capability_names[i - 1]);
1732 }
1733
1734 const char *
pmc_name_of_class(enum pmc_class pc)1735 pmc_name_of_class(enum pmc_class pc)
1736 {
1737 size_t n;
1738
1739 for (n = 0; n < PMC_TABLE_SIZE(pmc_class_names); n++)
1740 if (pc == pmc_class_names[n].pm_class)
1741 return (pmc_class_names[n].pm_name);
1742
1743 errno = EINVAL;
1744 return (NULL);
1745 }
1746
1747 const char *
pmc_name_of_cputype(enum pmc_cputype cp)1748 pmc_name_of_cputype(enum pmc_cputype cp)
1749 {
1750 size_t n;
1751
1752 for (n = 0; n < PMC_TABLE_SIZE(pmc_cputype_names); n++)
1753 if (cp == pmc_cputype_names[n].pm_cputype)
1754 return (pmc_cputype_names[n].pm_name);
1755
1756 errno = EINVAL;
1757 return (NULL);
1758 }
1759
1760 const char *
pmc_name_of_disposition(enum pmc_disp pd)1761 pmc_name_of_disposition(enum pmc_disp pd)
1762 {
1763 if ((int) pd >= PMC_DISP_FIRST &&
1764 pd <= PMC_DISP_LAST)
1765 return (pmc_disposition_names[pd]);
1766
1767 errno = EINVAL;
1768 return (NULL);
1769 }
1770
1771 const char *
_pmc_name_of_event(enum pmc_event pe,enum pmc_cputype cpu)1772 _pmc_name_of_event(enum pmc_event pe, enum pmc_cputype cpu)
1773 {
1774 const struct pmc_event_descr *ev, *evfence;
1775
1776 ev = evfence = NULL;
1777 if (pe >= PMC_EV_K8_FIRST && pe <= PMC_EV_K8_LAST) {
1778 ev = k8_event_table;
1779 evfence = k8_event_table + PMC_EVENT_TABLE_SIZE(k8);
1780 } else if (pe >= PMC_EV_IBS_FIRST && pe <= PMC_EV_IBS_LAST) {
1781 ev = ibs_event_table;
1782 evfence = ibs_event_table + PMC_EVENT_TABLE_SIZE(ibs);
1783 } else if (pe >= PMC_EV_ARMV7_FIRST && pe <= PMC_EV_ARMV7_LAST) {
1784 switch (cpu) {
1785 case PMC_CPU_ARMV7_CORTEX_A8:
1786 ev = cortex_a8_event_table;
1787 evfence = cortex_a8_event_table + PMC_EVENT_TABLE_SIZE(cortex_a8);
1788 break;
1789 case PMC_CPU_ARMV7_CORTEX_A9:
1790 ev = cortex_a9_event_table;
1791 evfence = cortex_a9_event_table + PMC_EVENT_TABLE_SIZE(cortex_a9);
1792 break;
1793 default: /* Unknown CPU type. */
1794 break;
1795 }
1796 } else if (pe >= PMC_EV_ARMV8_FIRST && pe <= PMC_EV_ARMV8_LAST) {
1797 switch (cpu) {
1798 case PMC_CPU_ARMV8_CORTEX_A53:
1799 ev = cortex_a53_event_table;
1800 evfence = cortex_a53_event_table + PMC_EVENT_TABLE_SIZE(cortex_a53);
1801 break;
1802 case PMC_CPU_ARMV8_CORTEX_A57:
1803 ev = cortex_a57_event_table;
1804 evfence = cortex_a57_event_table + PMC_EVENT_TABLE_SIZE(cortex_a57);
1805 break;
1806 case PMC_CPU_ARMV8_CORTEX_A76:
1807 ev = cortex_a76_event_table;
1808 evfence = cortex_a76_event_table + PMC_EVENT_TABLE_SIZE(cortex_a76);
1809 break;
1810 default: /* Unknown CPU type. */
1811 break;
1812 }
1813 } else if (pe >= PMC_EV_CMN600_PMU_FIRST &&
1814 pe <= PMC_EV_CMN600_PMU_LAST) {
1815 ev = cmn600_pmu_event_table;
1816 evfence = cmn600_pmu_event_table +
1817 PMC_EVENT_TABLE_SIZE(cmn600_pmu);
1818 } else if (pe >= PMC_EV_DMC620_PMU_CD2_FIRST &&
1819 pe <= PMC_EV_DMC620_PMU_CD2_LAST) {
1820 ev = dmc620_pmu_cd2_event_table;
1821 evfence = dmc620_pmu_cd2_event_table +
1822 PMC_EVENT_TABLE_SIZE(dmc620_pmu_cd2);
1823 } else if (pe >= PMC_EV_DMC620_PMU_C_FIRST &&
1824 pe <= PMC_EV_DMC620_PMU_C_LAST) {
1825 ev = dmc620_pmu_c_event_table;
1826 evfence = dmc620_pmu_c_event_table +
1827 PMC_EVENT_TABLE_SIZE(dmc620_pmu_c);
1828 } else if (pe >= PMC_EV_PPC7450_FIRST && pe <= PMC_EV_PPC7450_LAST) {
1829 ev = ppc7450_event_table;
1830 evfence = ppc7450_event_table + PMC_EVENT_TABLE_SIZE(ppc7450);
1831 } else if (pe >= PMC_EV_PPC970_FIRST && pe <= PMC_EV_PPC970_LAST) {
1832 ev = ppc970_event_table;
1833 evfence = ppc970_event_table + PMC_EVENT_TABLE_SIZE(ppc970);
1834 } else if (pe >= PMC_EV_E500_FIRST && pe <= PMC_EV_E500_LAST) {
1835 ev = e500_event_table;
1836 evfence = e500_event_table + PMC_EVENT_TABLE_SIZE(e500);
1837 } else if (pe == PMC_EV_TSC_TSC) {
1838 ev = tsc_event_table;
1839 evfence = tsc_event_table + PMC_EVENT_TABLE_SIZE(tsc);
1840 } else if ((int)pe >= PMC_EV_SOFT_FIRST && (int)pe <= PMC_EV_SOFT_LAST) {
1841 ev = soft_event_table;
1842 evfence = soft_event_table + soft_event_info.pm_nevent;
1843 }
1844
1845 for (; ev != evfence; ev++)
1846 if (pe == ev->pm_ev_code)
1847 return (ev->pm_ev_name);
1848
1849 return (NULL);
1850 }
1851
1852 const char *
pmc_name_of_event(enum pmc_event pe)1853 pmc_name_of_event(enum pmc_event pe)
1854 {
1855 const char *n;
1856
1857 if ((n = _pmc_name_of_event(pe, cpu_info.pm_cputype)) != NULL)
1858 return (n);
1859
1860 errno = EINVAL;
1861 return (NULL);
1862 }
1863
1864 const char *
pmc_name_of_mode(enum pmc_mode pm)1865 pmc_name_of_mode(enum pmc_mode pm)
1866 {
1867 if ((int) pm >= PMC_MODE_FIRST &&
1868 pm <= PMC_MODE_LAST)
1869 return (pmc_mode_names[pm]);
1870
1871 errno = EINVAL;
1872 return (NULL);
1873 }
1874
1875 const char *
pmc_name_of_state(enum pmc_state ps)1876 pmc_name_of_state(enum pmc_state ps)
1877 {
1878 if ((int) ps >= PMC_STATE_FIRST &&
1879 ps <= PMC_STATE_LAST)
1880 return (pmc_state_names[ps]);
1881
1882 errno = EINVAL;
1883 return (NULL);
1884 }
1885
1886 int
pmc_ncpu(void)1887 pmc_ncpu(void)
1888 {
1889 if (pmc_syscall == -1) {
1890 errno = ENXIO;
1891 return (-1);
1892 }
1893
1894 return (cpu_info.pm_ncpu);
1895 }
1896
1897 int
pmc_npmc(int cpu)1898 pmc_npmc(int cpu)
1899 {
1900 if (pmc_syscall == -1) {
1901 errno = ENXIO;
1902 return (-1);
1903 }
1904
1905 if (cpu < 0 || cpu >= (int) cpu_info.pm_ncpu) {
1906 errno = EINVAL;
1907 return (-1);
1908 }
1909
1910 return (cpu_info.pm_npmc);
1911 }
1912
1913 int
pmc_pmcinfo(int cpu,struct pmc_pmcinfo ** ppmci)1914 pmc_pmcinfo(int cpu, struct pmc_pmcinfo **ppmci)
1915 {
1916 int nbytes, npmc;
1917 struct pmc_op_getpmcinfo *pmci;
1918
1919 if ((npmc = pmc_npmc(cpu)) < 0)
1920 return (-1);
1921
1922 nbytes = sizeof(struct pmc_op_getpmcinfo) +
1923 npmc * sizeof(struct pmc_info);
1924
1925 if ((pmci = calloc(1, nbytes)) == NULL)
1926 return (-1);
1927
1928 pmci->pm_cpu = cpu;
1929
1930 if (PMC_CALL(PMC_OP_GETPMCINFO, pmci) < 0) {
1931 free(pmci);
1932 return (-1);
1933 }
1934
1935 /* kernel<->library, library<->userland interfaces are identical */
1936 *ppmci = (struct pmc_pmcinfo *) pmci;
1937 return (0);
1938 }
1939
1940 int
pmc_read(pmc_id_t pmc,pmc_value_t * value)1941 pmc_read(pmc_id_t pmc, pmc_value_t *value)
1942 {
1943 struct pmc_op_pmcrw pmc_read_op;
1944
1945 pmc_read_op.pm_pmcid = pmc;
1946 pmc_read_op.pm_flags = PMC_F_OLDVALUE;
1947 pmc_read_op.pm_value = -1;
1948
1949 if (PMC_CALL(PMC_OP_PMCRW, &pmc_read_op) < 0)
1950 return (-1);
1951
1952 *value = pmc_read_op.pm_value;
1953 return (0);
1954 }
1955
1956 int
pmc_release(pmc_id_t pmc)1957 pmc_release(pmc_id_t pmc)
1958 {
1959 struct pmc_op_simple pmc_release_args;
1960
1961 pmc_release_args.pm_pmcid = pmc;
1962 return (PMC_CALL(PMC_OP_PMCRELEASE, &pmc_release_args));
1963 }
1964
1965 int
pmc_rw(pmc_id_t pmc,pmc_value_t newvalue,pmc_value_t * oldvaluep)1966 pmc_rw(pmc_id_t pmc, pmc_value_t newvalue, pmc_value_t *oldvaluep)
1967 {
1968 struct pmc_op_pmcrw pmc_rw_op;
1969
1970 pmc_rw_op.pm_pmcid = pmc;
1971 pmc_rw_op.pm_flags = PMC_F_NEWVALUE | PMC_F_OLDVALUE;
1972 pmc_rw_op.pm_value = newvalue;
1973
1974 if (PMC_CALL(PMC_OP_PMCRW, &pmc_rw_op) < 0)
1975 return (-1);
1976
1977 *oldvaluep = pmc_rw_op.pm_value;
1978 return (0);
1979 }
1980
1981 int
pmc_set(pmc_id_t pmc,pmc_value_t value)1982 pmc_set(pmc_id_t pmc, pmc_value_t value)
1983 {
1984 struct pmc_op_pmcsetcount sc;
1985
1986 sc.pm_pmcid = pmc;
1987 sc.pm_count = value;
1988
1989 if (PMC_CALL(PMC_OP_PMCSETCOUNT, &sc) < 0)
1990 return (-1);
1991 return (0);
1992 }
1993
1994 int
pmc_start(pmc_id_t pmc)1995 pmc_start(pmc_id_t pmc)
1996 {
1997 struct pmc_op_simple pmc_start_args;
1998
1999 pmc_start_args.pm_pmcid = pmc;
2000 return (PMC_CALL(PMC_OP_PMCSTART, &pmc_start_args));
2001 }
2002
2003 int
pmc_stop(pmc_id_t pmc)2004 pmc_stop(pmc_id_t pmc)
2005 {
2006 struct pmc_op_simple pmc_stop_args;
2007
2008 pmc_stop_args.pm_pmcid = pmc;
2009 return (PMC_CALL(PMC_OP_PMCSTOP, &pmc_stop_args));
2010 }
2011
2012 int
pmc_width(pmc_id_t pmcid,uint32_t * width)2013 pmc_width(pmc_id_t pmcid, uint32_t *width)
2014 {
2015 unsigned int i;
2016 enum pmc_class cl;
2017
2018 cl = PMC_ID_TO_CLASS(pmcid);
2019 for (i = 0; i < cpu_info.pm_nclass; i++)
2020 if (cpu_info.pm_classes[i].pm_class == cl) {
2021 *width = cpu_info.pm_classes[i].pm_width;
2022 return (0);
2023 }
2024 errno = EINVAL;
2025 return (-1);
2026 }
2027
2028 int
pmc_write(pmc_id_t pmc,pmc_value_t value)2029 pmc_write(pmc_id_t pmc, pmc_value_t value)
2030 {
2031 struct pmc_op_pmcrw pmc_write_op;
2032
2033 pmc_write_op.pm_pmcid = pmc;
2034 pmc_write_op.pm_flags = PMC_F_NEWVALUE;
2035 pmc_write_op.pm_value = value;
2036 return (PMC_CALL(PMC_OP_PMCRW, &pmc_write_op));
2037 }
2038
2039 int
pmc_writelog(uint32_t userdata)2040 pmc_writelog(uint32_t userdata)
2041 {
2042 struct pmc_op_writelog wl;
2043
2044 wl.pm_userdata = userdata;
2045 return (PMC_CALL(PMC_OP_WRITELOG, &wl));
2046 }
2047