1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Spreadtrum Whale2 platform peripherals 4 * 5 * Copyright (C) 2016, Spreadtrum Communications Inc. 6 */ 7 8#include <dt-bindings/clock/sprd,sc9860-clk.h> 9 10/ { 11 interrupt-parent = <&gic>; 12 #address-cells = <2>; 13 #size-cells = <2>; 14 15 soc: soc { 16 compatible = "simple-bus"; 17 #address-cells = <2>; 18 #size-cells = <2>; 19 ranges; 20 21 apahb_gate: clock-controller@20210000 { 22 reg = <0 0x20210000 0 0x10000>; 23 compatible = "sprd,sc9860-apahb-gate"; 24 clocks = <&aon_prediv 0>; 25 #clock-cells = <1>; 26 }; 27 28 pmu_gate: clock-controller@402b0000 { 29 reg = <0 0x402b0000 0 0x10000>; 30 compatible = "sprd,sc9860-pmu-gate"; 31 clocks = <&ext_26m>; 32 #clock-cells = <1>; 33 }; 34 35 aon_gate: clock-controller@402e0000 { 36 reg = <0 0x402e0000 0 0x10000>; 37 compatible = "sprd,sc9860-aon-gate"; 38 clocks = <&aon_prediv 0>; 39 #clock-cells = <1>; 40 }; 41 42 pll: clock-controller@40400000 { 43 reg = <0 0x40400000 0 0x10000>; 44 compatible = "sprd,sc9860-pll"; 45 clocks = <&pmu_gate 0>; 46 #clock-cells = <1>; 47 }; 48 49 agcp_gate: clock-controller@415e0000 { 50 reg = <0 0x415e0000 0 0x1000000>; 51 compatible = "sprd,sc9860-agcp-gate"; 52 clocks = <&aon_prediv 0>; 53 #clock-cells = <1>; 54 }; 55 56 vsp_gate: clock-controller@61100000 { 57 reg = <0 0x61100000 0 0x10000>; 58 compatible = "sprd,sc9860-vsp-gate"; 59 clocks = <&vsp_clk 0>; 60 #clock-cells = <1>; 61 }; 62 63 cam_gate: clock-controller@62100000 { 64 reg = <0 0x62100000 0 0x10000>; 65 compatible = "sprd,sc9860-cam-gate"; 66 clocks = <&cam_clk 0>; 67 #clock-cells = <1>; 68 }; 69 70 disp_gate: clock-controller@63100000 { 71 reg = <0 0x63100000 0 0x10000>; 72 compatible = "sprd,sc9860-disp-gate"; 73 clocks = <&disp_clk 0>; 74 #clock-cells = <1>; 75 }; 76 77 apapb_gate: clock-controller@70b00000 { 78 reg = <0 0x70b00000 0 0x40000>; 79 compatible = "sprd,sc9860-apapb-gate"; 80 clocks = <&ap_clk 0>; 81 #clock-cells = <1>; 82 }; 83 84 ap-apb@70000000 { 85 compatible = "simple-bus"; 86 #address-cells = <1>; 87 #size-cells = <1>; 88 ranges = <0 0x0 0x70000000 0x10000000>; 89 90 uart0: serial@0 { 91 compatible = "sprd,sc9860-uart", 92 "sprd,sc9836-uart"; 93 reg = <0x0 0x100>; 94 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 95 clocks = <&apapb_gate CLK_UART0_EB>, 96 <&ap_clk CLK_UART0>, 97 <&ext_26m>; 98 clock-names = "enable", "uart", "source"; 99 status = "disabled"; 100 }; 101 102 uart1: serial@100000 { 103 compatible = "sprd,sc9860-uart", 104 "sprd,sc9836-uart"; 105 reg = <0x100000 0x100>; 106 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 107 clocks = <&apapb_gate CLK_UART1_EB>, 108 <&ap_clk CLK_UART1>, 109 <&ext_26m>; 110 clock-names = "enable", "uart", "source"; 111 status = "disabled"; 112 }; 113 114 uart2: serial@200000 { 115 compatible = "sprd,sc9860-uart", 116 "sprd,sc9836-uart"; 117 reg = <0x200000 0x100>; 118 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 119 clocks = <&apapb_gate CLK_UART2_EB>, 120 <&ap_clk CLK_UART2>, 121 <&ext_26m>; 122 clock-names = "enable", "uart", "source"; 123 status = "disabled"; 124 }; 125 126 uart3: serial@300000 { 127 compatible = "sprd,sc9860-uart", 128 "sprd,sc9836-uart"; 129 reg = <0x300000 0x100>; 130 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 131 clocks = <&apapb_gate CLK_UART3_EB>, 132 <&ap_clk CLK_UART3>, 133 <&ext_26m>; 134 clock-names = "enable", "uart", "source"; 135 status = "disabled"; 136 }; 137 }; 138 139 ap-ahb { 140 compatible = "simple-bus"; 141 #address-cells = <2>; 142 #size-cells = <2>; 143 ranges; 144 145 ap_dma: dma-controller@20100000 { 146 compatible = "sprd,sc9860-dma"; 147 reg = <0 0x20100000 0 0x4000>; 148 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 149 #dma-cells = <1>; 150 /* For backwards compatibility: */ 151 #dma-channels = <32>; 152 dma-channels = <32>; 153 clocks = <&apahb_gate CLK_DMA_EB>; 154 clock-names = "enable"; 155 }; 156 157 sdio3: mmc@50430000 { 158 compatible = "sprd,sdhci-r11"; 159 reg = <0 0x50430000 0 0x1000>; 160 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 161 162 clocks = <&aon_prediv CLK_EMMC_2X>, 163 <&apahb_gate CLK_EMMC_EB>, 164 <&aon_gate CLK_EMMC_2X_EN>; 165 clock-names = "sdio", "enable", "2x_enable"; 166 assigned-clocks = <&aon_prediv CLK_EMMC_2X>; 167 assigned-clock-parents = <&clk_l0_409m6>; 168 169 sprd,phy-delay-mmc-hs400 = <0x44 0x7f 0x2e 0x2e>; 170 sprd,phy-delay-mmc-hs200 = <0x0 0x8c 0x8c 0x8c>; 171 sprd,phy-delay-mmc-ddr52 = <0x3f 0x75 0x14 0x14>; 172 sprd,phy-delay-mmc-hs400es = <0x3f 0x3f 0x2e 0x2e>; 173 vmmc-supply = <&vddemmccore>; 174 bus-width = <8>; 175 non-removable; 176 no-sdio; 177 no-sd; 178 cap-mmc-hw-reset; 179 mmc-hs400-enhanced-strobe; 180 mmc-hs400-1_8v; 181 mmc-hs200-1_8v; 182 mmc-ddr-1_8v; 183 }; 184 }; 185 186 aon { 187 compatible = "simple-bus"; 188 #address-cells = <2>; 189 #size-cells = <2>; 190 ranges; 191 192 adi_bus: spi@40030000 { 193 compatible = "sprd,sc9860-adi"; 194 reg = <0 0x40030000 0 0x10000>; 195 hwlocks = <&hwlock 0>; 196 hwlock-names = "adi"; 197 #address-cells = <1>; 198 #size-cells = <0>; 199 }; 200 201 timer@40050000 { 202 compatible = "sprd,sc9860-timer"; 203 reg = <0 0x40050000 0 0x20>; 204 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 205 clocks = <&ext_32k>; 206 }; 207 208 timer@40050020 { 209 compatible = "sprd,sc9860-suspend-timer"; 210 reg = <0 0x40050020 0 0x20>; 211 clocks = <&ext_32k>; 212 }; 213 214 hwlock: hwspinlock@40500000 { 215 compatible = "sprd,hwspinlock-r3p0"; 216 reg = <0 0x40500000 0 0x1000>; 217 #hwlock-cells = <1>; 218 clocks = <&aon_gate CLK_SPLK_EB>; 219 clock-names = "enable"; 220 }; 221 222 eic_debounce: gpio@40210000 { 223 compatible = "sprd,sc9860-eic-debounce"; 224 reg = <0 0x40210000 0 0x80>; 225 gpio-controller; 226 #gpio-cells = <2>; 227 interrupt-controller; 228 #interrupt-cells = <2>; 229 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 230 }; 231 232 eic_latch: gpio@40210080 { 233 compatible = "sprd,sc9860-eic-latch"; 234 reg = <0 0x40210080 0 0x20>; 235 gpio-controller; 236 #gpio-cells = <2>; 237 interrupt-controller; 238 #interrupt-cells = <2>; 239 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 240 }; 241 242 eic_async: gpio@402100a0 { 243 compatible = "sprd,sc9860-eic-async"; 244 reg = <0 0x402100a0 0 0x20>; 245 gpio-controller; 246 #gpio-cells = <2>; 247 interrupt-controller; 248 #interrupt-cells = <2>; 249 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 250 }; 251 252 eic_sync: gpio@402100c0 { 253 compatible = "sprd,sc9860-eic-sync"; 254 reg = <0 0x402100c0 0 0x20>; 255 gpio-controller; 256 #gpio-cells = <2>; 257 interrupt-controller; 258 #interrupt-cells = <2>; 259 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 260 }; 261 262 ap_gpio: gpio@40280000 { 263 compatible = "sprd,sc9860-gpio"; 264 reg = <0 0x40280000 0 0x1000>; 265 gpio-controller; 266 #gpio-cells = <2>; 267 interrupt-controller; 268 #interrupt-cells = <2>; 269 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 270 }; 271 272 pin_controller: pinctrl@402a0000 { 273 compatible = "sprd,sc9860-pinctrl"; 274 reg = <0 0x402a0000 0 0x10000>; 275 }; 276 277 watchdog@40310000 { 278 compatible = "sprd,sp9860-wdt"; 279 reg = <0 0x40310000 0 0x1000>; 280 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 281 timeout-sec = <12>; 282 clocks = <&aon_gate CLK_APCPU_WDG_EB>, 283 <&aon_gate CLK_AP_WDG_RTC_EB>; 284 clock-names = "enable", "rtc_enable"; 285 }; 286 }; 287 288 agcp { 289 compatible = "simple-bus"; 290 #address-cells = <2>; 291 #size-cells = <2>; 292 ranges; 293 294 agcp_dma: dma-controller@41580000 { 295 compatible = "sprd,sc9860-dma"; 296 reg = <0 0x41580000 0 0x4000>; 297 #dma-cells = <1>; 298 /* For backwards compatibility: */ 299 #dma-channels = <32>; 300 dma-channels = <32>; 301 clocks = <&agcp_gate CLK_AGCP_DMAAP_EB>, 302 <&agcp_gate CLK_AGCP_AP_ASHB_EB>; 303 clock-names = "enable", "ashb_eb"; 304 }; 305 }; 306 }; 307 308 ext_32k: ext_32k { 309 compatible = "fixed-clock"; 310 #clock-cells = <0>; 311 clock-frequency = <32768>; 312 clock-output-names = "ext-32k"; 313 }; 314 315 ext_26m: ext_26m { 316 compatible = "fixed-clock"; 317 #clock-cells = <0>; 318 clock-frequency = <26000000>; 319 clock-output-names = "ext-26m"; 320 }; 321 322 ext_rco_100m: ext_rco_100m { 323 compatible = "fixed-clock"; 324 #clock-cells = <0>; 325 clock-frequency = <100000000>; 326 clock-output-names = "ext-rco-100m"; 327 }; 328 329 clk_l0_409m6: clk_l0_409m6 { 330 compatible = "fixed-clock"; 331 #clock-cells = <0>; 332 clock-frequency = <409600000>; 333 clock-output-names = "ext-409m6"; 334 }; 335}; 336