1 /* 2 * Copyright (c) 2015-2024, Broadcom. All rights reserved. The term 3 * Broadcom refers to Broadcom Limited and/or its subsidiaries. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in 13 * the documentation and/or other materials provided with the 14 * distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' 17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 18 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 23 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE 25 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN 26 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Description: Slow Path Operators 29 */ 30 31 #include <linux/interrupt.h> 32 #include <linux/spinlock.h> 33 #include <linux/sched.h> 34 #include <linux/pci.h> 35 #include <linux/if_ether.h> 36 #include <linux/printk.h> 37 38 #include "hsi_struct_def.h" 39 #include "qplib_tlv.h" 40 #include "qplib_res.h" 41 #include "qplib_rcfw.h" 42 #include "qplib_sp.h" 43 #include "bnxt_ulp.h" 44 45 const struct bnxt_qplib_gid bnxt_qplib_gid_zero = {{ 0, 0, 0, 0, 0, 0, 0, 0, 46 0, 0, 0, 0, 0, 0, 0, 0 }}; 47 48 /* Device */ 49 static u8 bnxt_qplib_is_atomic_cap(struct bnxt_qplib_rcfw *rcfw) 50 { 51 u16 pcie_ctl2 = 0; 52 53 if (!_is_chip_gen_p5_p7(rcfw->res->cctx)) 54 return false; 55 pcie_capability_read_word(rcfw->pdev, PCI_EXP_DEVCTL2, &pcie_ctl2); 56 return (pcie_ctl2 & PCI_EXP_DEVCTL2_ATOMIC_REQ); 57 } 58 59 static void bnxt_qplib_query_version(struct bnxt_qplib_rcfw *rcfw, char *fw_ver) 60 { 61 struct creq_query_version_resp resp = {}; 62 struct bnxt_qplib_cmdqmsg msg = {}; 63 struct cmdq_query_version req = {}; 64 int rc = 0; 65 66 bnxt_qplib_rcfw_cmd_prep(&req, CMDQ_BASE_OPCODE_QUERY_VERSION, 67 sizeof(req)); 68 bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, NULL, sizeof(req), 69 sizeof(resp), 0); 70 rc = bnxt_qplib_rcfw_send_message(rcfw, &msg); 71 if (rc) { 72 dev_err(&rcfw->pdev->dev, "QPLIB: Failed to query version\n"); 73 return; 74 } 75 fw_ver[0] = resp.fw_maj; 76 fw_ver[1] = resp.fw_minor; 77 fw_ver[2] = resp.fw_bld; 78 fw_ver[3] = resp.fw_rsvd; 79 } 80 81 int bnxt_qplib_get_dev_attr(struct bnxt_qplib_rcfw *rcfw) 82 { 83 struct bnxt_qplib_max_res dev_res = {}; 84 struct creq_query_func_resp resp = {}; 85 struct bnxt_qplib_cmdqmsg msg = {}; 86 struct creq_query_func_resp_sb *sb; 87 struct bnxt_qplib_rcfw_sbuf sbuf; 88 struct bnxt_qplib_dev_attr *attr; 89 struct bnxt_qplib_chip_ctx *cctx; 90 struct cmdq_query_func req = {}; 91 bool sw_max_en; 92 u8 *tqm_alloc; 93 int i, rc = 0; 94 u32 temp; 95 96 cctx = rcfw->res->cctx; 97 attr = rcfw->res->dattr; 98 99 bnxt_qplib_rcfw_cmd_prep(&req, CMDQ_BASE_OPCODE_QUERY_FUNC, 100 sizeof(req)); 101 102 sbuf.size = sizeof(*sb); 103 sbuf.sb = dma_zalloc_coherent(&rcfw->pdev->dev, sbuf.size, 104 &sbuf.dma_addr, GFP_KERNEL); 105 if (!sbuf.sb) 106 return -ENOMEM; 107 108 sb = sbuf.sb; 109 req.resp_size = sbuf.size / BNXT_QPLIB_CMDQE_UNITS; 110 bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, &sbuf, sizeof(req), 111 sizeof(resp), 0); 112 rc = bnxt_qplib_rcfw_send_message(rcfw, &msg); 113 if (rc) 114 goto bail; 115 bnxt_qplib_max_res_supported(cctx, rcfw->res, &dev_res, false); 116 sw_max_en = BNXT_EN_SW_RES_LMT(rcfw->res->en_dev); 117 /* Extract the context from the side buffer */ 118 attr->max_qp = bnxt_re_cap_fw_res(le32_to_cpu(sb->max_qp), 119 dev_res.max_qp, sw_max_en); 120 /* max_qp value reported by FW does not include the QP1 */ 121 attr->max_qp += 1; 122 attr->max_qp_rd_atom = 123 sb->max_qp_rd_atom > BNXT_QPLIB_MAX_OUT_RD_ATOM ? 124 BNXT_QPLIB_MAX_OUT_RD_ATOM : sb->max_qp_rd_atom; 125 attr->max_qp_init_rd_atom = 126 sb->max_qp_init_rd_atom > BNXT_QPLIB_MAX_OUT_RD_ATOM ? 127 BNXT_QPLIB_MAX_OUT_RD_ATOM : sb->max_qp_init_rd_atom; 128 /* Report 1 less than the max_qp_wqes reported by FW as driver adds 129 * one extra entry while creating the qp 130 */ 131 attr->max_qp_wqes = le16_to_cpu(sb->max_qp_wr) - 1; 132 if (!_is_chip_gen_p5_p7(cctx)) { 133 /* 134 * 128 WQEs needs to be reserved for the HW (8916). Prevent 135 * reporting the max number for gen-p4 only. 136 */ 137 attr->max_qp_wqes -= BNXT_QPLIB_RESERVED_QP_WRS; 138 } 139 140 /* Adjust for max_qp_wqes for variable wqe */ 141 if (cctx->modes.wqe_mode == BNXT_QPLIB_WQE_MODE_VARIABLE) 142 attr->max_qp_wqes = BNXT_VAR_MAX_WQE - 1; 143 144 attr->max_qp_sges = cctx->modes.wqe_mode == BNXT_QPLIB_WQE_MODE_VARIABLE ? 145 min_t(u32, sb->max_sge_var_wqe, BNXT_VAR_MAX_SGE) : sb->max_sge; 146 attr->max_cq = bnxt_re_cap_fw_res(le32_to_cpu(sb->max_cq), 147 dev_res.max_cq, sw_max_en); 148 149 attr->max_cq_wqes = le32_to_cpu(sb->max_cqe); 150 attr->max_cq_wqes = min_t(u32, BNXT_QPLIB_MAX_CQ_WQES, attr->max_cq_wqes); 151 152 attr->max_cq_sges = attr->max_qp_sges; 153 attr->max_mr = bnxt_re_cap_fw_res(le32_to_cpu(sb->max_mr), 154 dev_res.max_mr, sw_max_en); 155 attr->max_mw = bnxt_re_cap_fw_res(le32_to_cpu(sb->max_mw), 156 dev_res.max_mr, sw_max_en); 157 158 attr->max_mr_size = le64_to_cpu(sb->max_mr_size); 159 attr->max_pd = BNXT_QPLIB_MAX_PD; 160 attr->max_raw_ethy_qp = le32_to_cpu(sb->max_raw_eth_qp); 161 attr->max_ah = bnxt_re_cap_fw_res(le32_to_cpu(sb->max_ah), 162 dev_res.max_ah, sw_max_en); 163 164 attr->max_fmr = le32_to_cpu(sb->max_fmr); 165 attr->max_map_per_fmr = sb->max_map_per_fmr; 166 167 attr->max_srq = bnxt_re_cap_fw_res(le16_to_cpu(sb->max_srq), 168 dev_res.max_srq, sw_max_en); 169 attr->max_srq_wqes = le32_to_cpu(sb->max_srq_wr) - 1; 170 attr->max_srq_sges = sb->max_srq_sge; 171 attr->max_pkey = 1; 172 173 attr->max_inline_data = !cctx->modes.wqe_mode ? 174 le32_to_cpu(sb->max_inline_data) : 175 le16_to_cpu(sb->max_inline_data_var_wqe); 176 if (!_is_chip_p7(cctx)) { 177 attr->l2_db_size = (sb->l2_db_space_size + 1) * 178 (0x01 << RCFW_DBR_BASE_PAGE_SHIFT); 179 } 180 attr->max_sgid = le32_to_cpu(sb->max_gid); 181 182 /* TODO: remove this hack for statically allocated gid_map */ 183 bnxt_re_set_max_gid(&attr->max_sgid); 184 185 attr->dev_cap_flags = le16_to_cpu(sb->dev_cap_flags); 186 attr->page_size_cap = BIT_ULL(28) | BIT_ULL(21) | BIT_ULL(12); 187 188 bnxt_qplib_query_version(rcfw, attr->fw_ver); 189 attr->dev_cap_ext_flags2 = le16_to_cpu(sb->dev_cap_ext_flags_2); 190 191 for (i = 0; i < MAX_TQM_ALLOC_REQ / 4; i++) { 192 temp = le32_to_cpu(sb->tqm_alloc_reqs[i]); 193 tqm_alloc = (u8 *)&temp; 194 attr->tqm_alloc_reqs[i * 4] = *tqm_alloc; 195 attr->tqm_alloc_reqs[i * 4 + 1] = *(++tqm_alloc); 196 attr->tqm_alloc_reqs[i * 4 + 2] = *(++tqm_alloc); 197 attr->tqm_alloc_reqs[i * 4 + 3] = *(++tqm_alloc); 198 } 199 200 if (rcfw->res->cctx->hwrm_intf_ver >= HWRM_VERSION_DEV_ATTR_MAX_DPI) 201 attr->max_dpi = le32_to_cpu(sb->max_dpi); 202 203 attr->is_atomic = bnxt_qplib_is_atomic_cap(rcfw); 204 bail: 205 dma_free_coherent(&rcfw->pdev->dev, sbuf.size, 206 sbuf.sb, sbuf.dma_addr); 207 return rc; 208 } 209 210 int bnxt_qplib_set_func_resources(struct bnxt_qplib_res *res) 211 { 212 struct creq_set_func_resources_resp resp = {}; 213 struct cmdq_set_func_resources req = {}; 214 struct bnxt_qplib_cmdqmsg msg = {}; 215 struct bnxt_qplib_rcfw *rcfw; 216 struct bnxt_qplib_ctx *hctx; 217 int rc = 0; 218 219 rcfw = res->rcfw; 220 hctx = res->hctx; 221 bnxt_qplib_rcfw_cmd_prep(&req, CMDQ_BASE_OPCODE_SET_FUNC_RESOURCES, 222 sizeof(req)); 223 224 req.number_of_qp = cpu_to_le32(hctx->qp_ctx.max); 225 req.number_of_mrw = cpu_to_le32(hctx->mrw_ctx.max); 226 req.number_of_srq = cpu_to_le32(hctx->srq_ctx.max); 227 req.number_of_cq = cpu_to_le32(hctx->cq_ctx.max); 228 229 req.max_qp_per_vf = cpu_to_le32(hctx->vf_res.max_qp); 230 req.max_mrw_per_vf = cpu_to_le32(hctx->vf_res.max_mrw); 231 req.max_srq_per_vf = cpu_to_le32(hctx->vf_res.max_srq); 232 req.max_cq_per_vf = cpu_to_le32(hctx->vf_res.max_cq); 233 req.max_gid_per_vf = cpu_to_le32(hctx->vf_res.max_gid); 234 235 /* Keep the old stats context id of PF */ 236 req.stat_ctx_id = cpu_to_le32(hctx->stats.fw_id); 237 238 bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, NULL, sizeof(req), 239 sizeof(resp), 0); 240 rc = bnxt_qplib_rcfw_send_message(rcfw, &msg); 241 if (rc) 242 dev_err(&res->pdev->dev, 243 "QPLIB: Failed to set function resources\n"); 244 245 return rc; 246 } 247 248 int bnxt_qplib_update_sgid(struct bnxt_qplib_sgid_tbl *sgid_tbl, 249 struct bnxt_qplib_gid *gid, u16 gid_idx, const u8 *smac) 250 { 251 struct bnxt_qplib_res *res = to_bnxt_qplib(sgid_tbl, 252 struct bnxt_qplib_res, 253 sgid_tbl); 254 struct bnxt_qplib_rcfw *rcfw = res->rcfw; 255 struct creq_modify_gid_resp resp = {}; 256 struct bnxt_qplib_cmdqmsg msg = {}; 257 struct cmdq_modify_gid req = {}; 258 int rc; 259 260 bnxt_qplib_rcfw_cmd_prep(&req, CMDQ_BASE_OPCODE_MODIFY_GID, 261 sizeof(req)); 262 263 req.gid[0] = cpu_to_be32(((u32 *)gid->data)[3]); 264 req.gid[1] = cpu_to_be32(((u32 *)gid->data)[2]); 265 req.gid[2] = cpu_to_be32(((u32 *)gid->data)[1]); 266 req.gid[3] = cpu_to_be32(((u32 *)gid->data)[0]); 267 if (res->prio) { 268 req.vlan |= cpu_to_le16(CMDQ_ADD_GID_VLAN_TPID_TPID_8100 | 269 CMDQ_ADD_GID_VLAN_VLAN_EN); 270 } 271 272 /* MAC in network format */ 273 req.src_mac[0] = cpu_to_be16(((u16 *)smac)[0]); 274 req.src_mac[1] = cpu_to_be16(((u16 *)smac)[1]); 275 req.src_mac[2] = cpu_to_be16(((u16 *)smac)[2]); 276 req.gid_index = cpu_to_le16(gid_idx); 277 278 bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, NULL, sizeof(req), 279 sizeof(resp), 0); 280 rc = bnxt_qplib_rcfw_send_message(rcfw, &msg); 281 if (rc) { 282 dev_err(&res->pdev->dev, 283 "QPLIB: update SGID table failed\n"); 284 return rc; 285 } 286 return 0; 287 } 288 289 /* SGID */ 290 int bnxt_qplib_get_sgid(struct bnxt_qplib_res *res, 291 struct bnxt_qplib_sgid_tbl *sgid_tbl, int index, 292 struct bnxt_qplib_gid *gid) 293 { 294 if (index > sgid_tbl->max) { 295 dev_err(&res->pdev->dev, 296 "QPLIB: Index %d exceeded SGID table max (%d)\n", 297 index, sgid_tbl->max); 298 return -EINVAL; 299 } 300 memcpy(gid, &sgid_tbl->tbl[index].gid, sizeof(*gid)); 301 return 0; 302 } 303 304 int bnxt_qplib_del_sgid(struct bnxt_qplib_sgid_tbl *sgid_tbl, 305 struct bnxt_qplib_gid *gid, 306 u16 vlan_id, bool update) 307 { 308 struct bnxt_qplib_res *res = to_bnxt_qplib(sgid_tbl, 309 struct bnxt_qplib_res, 310 sgid_tbl); 311 struct bnxt_qplib_rcfw *rcfw = res->rcfw; 312 int index; 313 314 if (sgid_tbl == NULL) { 315 dev_err(&res->pdev->dev, "QPLIB: SGID table not allocated\n"); 316 return -EINVAL; 317 } 318 /* Do we need a sgid_lock here? */ 319 if (!sgid_tbl->active) { 320 dev_err(&res->pdev->dev, 321 "QPLIB: SGID table has no active entries\n"); 322 return -ENOMEM; 323 } 324 for (index = 0; index < sgid_tbl->max; index++) { 325 if (!memcmp(&sgid_tbl->tbl[index].gid, gid, sizeof(*gid)) && 326 vlan_id == sgid_tbl->tbl[index].vlan_id) 327 break; 328 } 329 if (index == sgid_tbl->max) { 330 dev_warn(&res->pdev->dev, "GID not found in the SGID table\n"); 331 return 0; 332 } 333 334 if (update) { 335 struct creq_delete_gid_resp resp = {}; 336 struct bnxt_qplib_cmdqmsg msg = {}; 337 struct cmdq_delete_gid req = {}; 338 int rc; 339 340 bnxt_qplib_rcfw_cmd_prep(&req, CMDQ_BASE_OPCODE_DELETE_GID, 341 sizeof(req)); 342 if (sgid_tbl->hw_id[index] == 0xFFFF) { 343 dev_err(&res->pdev->dev, 344 "QPLIB: GID entry contains an invalid HW id"); 345 return -EINVAL; 346 } 347 req.gid_index = cpu_to_le16(sgid_tbl->hw_id[index]); 348 bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, NULL, sizeof(req), 349 sizeof(resp), 0); 350 rc = bnxt_qplib_rcfw_send_message(rcfw, &msg); 351 if (rc) 352 return rc; 353 } 354 memcpy(&sgid_tbl->tbl[index].gid, &bnxt_qplib_gid_zero, 355 sizeof(bnxt_qplib_gid_zero)); 356 sgid_tbl->tbl[index].vlan_id = 0xFFFF; 357 sgid_tbl->vlan[index] = false; 358 sgid_tbl->active--; 359 dev_dbg(&res->pdev->dev, 360 "QPLIB: SGID deleted hw_id[0x%x] = 0x%x active = 0x%x\n", 361 index, sgid_tbl->hw_id[index], sgid_tbl->active); 362 sgid_tbl->hw_id[index] = (u16)-1; 363 364 return 0; 365 } 366 367 int bnxt_qplib_add_sgid(struct bnxt_qplib_sgid_tbl *sgid_tbl, 368 const union ib_gid *gid, const u8 *smac, u16 vlan_id, 369 bool update, u32 *index) 370 { 371 struct bnxt_qplib_res *res = to_bnxt_qplib(sgid_tbl, 372 struct bnxt_qplib_res, 373 sgid_tbl); 374 struct bnxt_qplib_rcfw *rcfw = res->rcfw; 375 int i, free_idx; 376 377 if (sgid_tbl == NULL) { 378 dev_err(&res->pdev->dev, "QPLIB: SGID table not allocated\n"); 379 return -EINVAL; 380 } 381 /* Do we need a sgid_lock here? */ 382 if (sgid_tbl->active == sgid_tbl->max) { 383 dev_err(&res->pdev->dev, "QPLIB: SGID table is full\n"); 384 return -ENOMEM; 385 } 386 free_idx = sgid_tbl->max; 387 for (i = 0; i < sgid_tbl->max; i++) { 388 if (!memcmp(&sgid_tbl->tbl[i], gid, sizeof(*gid)) && 389 sgid_tbl->tbl[i].vlan_id == vlan_id) { 390 dev_dbg(&res->pdev->dev, 391 "QPLIB: SGID entry already exist in entry %d!\n", 392 i); 393 *index = i; 394 return -EALREADY; 395 } else if (!memcmp(&sgid_tbl->tbl[i], &bnxt_qplib_gid_zero, 396 sizeof(bnxt_qplib_gid_zero)) && 397 free_idx == sgid_tbl->max) { 398 free_idx = i; 399 } 400 } 401 if (free_idx == sgid_tbl->max) { 402 dev_err(&res->pdev->dev, 403 "QPLIB: SGID table is FULL but count is not MAX??\n"); 404 return -ENOMEM; 405 } 406 if (update) { 407 struct creq_add_gid_resp resp = {}; 408 struct bnxt_qplib_cmdqmsg msg = {}; 409 struct cmdq_add_gid req = {}; 410 int rc; 411 412 bnxt_qplib_rcfw_cmd_prep(&req, CMDQ_BASE_OPCODE_ADD_GID, 413 sizeof(req)); 414 415 req.gid[0] = cpu_to_be32(((u32 *)gid->raw)[3]); 416 req.gid[1] = cpu_to_be32(((u32 *)gid->raw)[2]); 417 req.gid[2] = cpu_to_be32(((u32 *)gid->raw)[1]); 418 req.gid[3] = cpu_to_be32(((u32 *)gid->raw)[0]); 419 /* driver should ensure that all RoCE traffic is always VLAN tagged 420 * if RoCE traffic is running on non-zero VLAN ID or 421 * RoCE traffic is running on non-zero Priority. 422 */ 423 if ((vlan_id != 0xFFFF) || res->prio) { 424 if (vlan_id != 0xFFFF) 425 req.vlan = cpu_to_le16(vlan_id & 426 CMDQ_ADD_GID_VLAN_VLAN_ID_MASK); 427 req.vlan |= 428 cpu_to_le16(CMDQ_ADD_GID_VLAN_TPID_TPID_8100 | 429 CMDQ_ADD_GID_VLAN_VLAN_EN); 430 } 431 432 /* MAC in network format */ 433 req.src_mac[0] = cpu_to_be16(((u16 *)smac)[0]); 434 req.src_mac[1] = cpu_to_be16(((u16 *)smac)[1]); 435 req.src_mac[2] = cpu_to_be16(((u16 *)smac)[2]); 436 437 bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, NULL, sizeof(req), 438 sizeof(resp), 0); 439 rc = bnxt_qplib_rcfw_send_message(rcfw, &msg); 440 if (rc) 441 return rc; 442 sgid_tbl->hw_id[free_idx] = le32_to_cpu(resp.xid); 443 } 444 445 if (vlan_id != 0xFFFF) 446 sgid_tbl->vlan[free_idx] = true; 447 448 memcpy(&sgid_tbl->tbl[free_idx], gid, sizeof(*gid)); 449 sgid_tbl->tbl[free_idx].vlan_id = vlan_id; 450 sgid_tbl->active++; 451 dev_dbg(&res->pdev->dev, 452 "QPLIB: SGID added hw_id[0x%x] = 0x%x active = 0x%x\n", 453 free_idx, sgid_tbl->hw_id[free_idx], sgid_tbl->active); 454 455 *index = free_idx; 456 /* unlock */ 457 return 0; 458 } 459 460 /* AH */ 461 int bnxt_qplib_create_ah(struct bnxt_qplib_res *res, struct bnxt_qplib_ah *ah, 462 bool block) 463 { 464 struct bnxt_qplib_rcfw *rcfw = res->rcfw; 465 struct creq_create_ah_resp resp = {}; 466 struct bnxt_qplib_cmdqmsg msg = {}; 467 struct cmdq_create_ah req = {}; 468 u32 temp32[4]; 469 u16 temp16[3]; 470 int rc; 471 472 bnxt_qplib_rcfw_cmd_prep(&req, CMDQ_BASE_OPCODE_CREATE_AH, 473 sizeof(req)); 474 475 memcpy(temp32, ah->dgid.data, sizeof(struct bnxt_qplib_gid)); 476 req.dgid[0] = cpu_to_le32(temp32[0]); 477 req.dgid[1] = cpu_to_le32(temp32[1]); 478 req.dgid[2] = cpu_to_le32(temp32[2]); 479 req.dgid[3] = cpu_to_le32(temp32[3]); 480 481 req.type = ah->nw_type; 482 req.hop_limit = ah->hop_limit; 483 req.sgid_index = cpu_to_le16(res->sgid_tbl.hw_id[ah->sgid_index]); 484 req.dest_vlan_id_flow_label = cpu_to_le32((ah->flow_label & 485 CMDQ_CREATE_AH_FLOW_LABEL_MASK) | 486 CMDQ_CREATE_AH_DEST_VLAN_ID_MASK); 487 req.pd_id = cpu_to_le32(ah->pd->id); 488 req.traffic_class = ah->traffic_class; 489 490 /* MAC in network format */ 491 memcpy(temp16, ah->dmac, ETH_ALEN); 492 req.dest_mac[0] = cpu_to_le16(temp16[0]); 493 req.dest_mac[1] = cpu_to_le16(temp16[1]); 494 req.dest_mac[2] = cpu_to_le16(temp16[2]); 495 496 bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, NULL, sizeof(req), 497 sizeof(resp), block); 498 rc = bnxt_qplib_rcfw_send_message(rcfw, &msg); 499 if (rc) 500 return rc; 501 502 ah->id = le32_to_cpu(resp.xid); 503 /* for Cu/Wh AHID 0 is not valid */ 504 if (!_is_chip_gen_p5_p7(res->cctx) && !ah->id) 505 rc = -EINVAL; 506 507 return rc; 508 } 509 510 int bnxt_qplib_destroy_ah(struct bnxt_qplib_res *res, struct bnxt_qplib_ah *ah, 511 bool block) 512 { 513 struct bnxt_qplib_rcfw *rcfw = res->rcfw; 514 struct creq_destroy_ah_resp resp = {}; 515 struct bnxt_qplib_cmdqmsg msg = {}; 516 struct cmdq_destroy_ah req = {}; 517 int rc; 518 519 bnxt_qplib_rcfw_cmd_prep(&req, CMDQ_BASE_OPCODE_DESTROY_AH, 520 sizeof(req)); 521 522 req.ah_cid = cpu_to_le32(ah->id); 523 524 bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, NULL, sizeof(req), 525 sizeof(resp), block); 526 rc = bnxt_qplib_rcfw_send_message(rcfw, &msg); 527 return rc; 528 } 529 530 /* MRW */ 531 int bnxt_qplib_free_mrw(struct bnxt_qplib_res *res, struct bnxt_qplib_mrw *mrw) 532 { 533 struct creq_deallocate_key_resp resp = {}; 534 struct bnxt_qplib_rcfw *rcfw = res->rcfw; 535 struct cmdq_deallocate_key req = {}; 536 struct bnxt_qplib_cmdqmsg msg = {}; 537 int rc; 538 539 if (mrw->lkey == 0xFFFFFFFF) { 540 dev_info(&res->pdev->dev, 541 "QPLIB: SP: Free a reserved lkey MRW\n"); 542 return 0; 543 } 544 545 bnxt_qplib_rcfw_cmd_prep(&req, CMDQ_BASE_OPCODE_DEALLOCATE_KEY, 546 sizeof(req)); 547 548 req.mrw_flags = mrw->type; 549 550 if ((mrw->type == CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE1) || 551 (mrw->type == CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE2A) || 552 (mrw->type == CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE2B)) 553 req.key = cpu_to_le32(mrw->rkey); 554 else 555 req.key = cpu_to_le32(mrw->lkey); 556 557 bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, NULL, sizeof(req), 558 sizeof(resp), 0); 559 rc = bnxt_qplib_rcfw_send_message(rcfw, &msg); 560 if (rc) 561 return rc; 562 563 if (mrw->hwq.max_elements) 564 bnxt_qplib_free_hwq(res, &mrw->hwq); 565 566 return 0; 567 } 568 569 int bnxt_qplib_alloc_mrw(struct bnxt_qplib_res *res, struct bnxt_qplib_mrw *mrw) 570 { 571 struct bnxt_qplib_rcfw *rcfw = res->rcfw; 572 struct creq_allocate_mrw_resp resp = {}; 573 struct bnxt_qplib_cmdqmsg msg = {}; 574 struct cmdq_allocate_mrw req = {}; 575 int rc; 576 577 bnxt_qplib_rcfw_cmd_prep(&req, CMDQ_BASE_OPCODE_ALLOCATE_MRW, 578 sizeof(req)); 579 580 req.pd_id = cpu_to_le32(mrw->pd->id); 581 req.mrw_flags = mrw->type; 582 if ((mrw->type == CMDQ_ALLOCATE_MRW_MRW_FLAGS_PMR && 583 mrw->flags & BNXT_QPLIB_FR_PMR) || 584 mrw->type == CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE2A || 585 mrw->type == CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE2B) 586 req.access = CMDQ_ALLOCATE_MRW_ACCESS_CONSUMER_OWNED_KEY; 587 req.mrw_handle = cpu_to_le64((uintptr_t)mrw); 588 589 bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, NULL, sizeof(req), 590 sizeof(resp), 0); 591 rc = bnxt_qplib_rcfw_send_message(rcfw, &msg); 592 if (rc) 593 return rc; 594 if ((mrw->type == CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE1) || 595 (mrw->type == CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE2A) || 596 (mrw->type == CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE2B)) 597 mrw->rkey = le32_to_cpu(resp.xid); 598 else 599 mrw->lkey = le32_to_cpu(resp.xid); 600 601 return 0; 602 } 603 604 int bnxt_qplib_dereg_mrw(struct bnxt_qplib_res *res, struct bnxt_qplib_mrw *mrw, 605 bool block) 606 { 607 struct bnxt_qplib_rcfw *rcfw = res->rcfw; 608 struct creq_deregister_mr_resp resp = {}; 609 struct bnxt_qplib_cmdqmsg msg = {}; 610 struct cmdq_deregister_mr req = {}; 611 int rc; 612 613 bnxt_qplib_rcfw_cmd_prep(&req, CMDQ_BASE_OPCODE_DEREGISTER_MR, 614 sizeof(req)); 615 616 req.lkey = cpu_to_le32(mrw->lkey); 617 bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, NULL, sizeof(req), 618 sizeof(resp), block); 619 rc = bnxt_qplib_rcfw_send_message(rcfw, &msg); 620 if (rc) 621 return rc; 622 623 if (mrw->hwq.max_elements) { 624 mrw->va = 0; 625 mrw->total_size = 0; 626 bnxt_qplib_free_hwq(res, &mrw->hwq); 627 } 628 629 return 0; 630 } 631 632 int bnxt_qplib_reg_mr(struct bnxt_qplib_res *res, 633 struct bnxt_qplib_mrinfo *mrinfo, 634 bool block) 635 { 636 struct bnxt_qplib_hwq_attr hwq_attr = {}; 637 struct bnxt_qplib_rcfw *rcfw = res->rcfw; 638 struct creq_register_mr_resp resp = {}; 639 struct bnxt_qplib_cmdqmsg msg = {}; 640 struct cmdq_register_mr req = {}; 641 struct bnxt_qplib_mrw *mr; 642 u32 buf_pg_size; 643 u32 pg_size; 644 u16 level; 645 u16 flags; 646 int rc; 647 648 mr = mrinfo->mrw; 649 buf_pg_size = 0x01ULL << mrinfo->sg.pgshft; 650 if (mrinfo->sg.npages) { 651 /* Free the hwq if it already exist, must be a rereg */ 652 if (mr->hwq.max_elements) 653 bnxt_qplib_free_hwq(res, &mr->hwq); 654 /* Use system PAGE_SIZE */ 655 hwq_attr.res = res; 656 hwq_attr.depth = mrinfo->sg.npages; 657 hwq_attr.stride = PAGE_SIZE; 658 hwq_attr.type = HWQ_TYPE_MR; 659 hwq_attr.sginfo = &mrinfo->sg; 660 rc = bnxt_qplib_alloc_init_hwq(&mr->hwq, &hwq_attr); 661 if (rc) { 662 dev_err(&res->pdev->dev, 663 "SP: Reg MR memory allocation failed\n"); 664 return -ENOMEM; 665 } 666 } 667 668 bnxt_qplib_rcfw_cmd_prep(&req, CMDQ_BASE_OPCODE_REGISTER_MR, 669 sizeof(req)); 670 /* Configure the request */ 671 if (mrinfo->is_dma) { 672 /* No PBL provided, just use system PAGE_SIZE */ 673 level = 0; 674 req.pbl = 0; 675 pg_size = PAGE_SIZE; 676 } else { 677 level = mr->hwq.level; 678 req.pbl = cpu_to_le64(mr->hwq.pbl[PBL_LVL_0].pg_map_arr[0]); 679 } 680 681 pg_size = buf_pg_size ? buf_pg_size : PAGE_SIZE; 682 req.log2_pg_size_lvl = (level << CMDQ_REGISTER_MR_LVL_SFT) | 683 ((ilog2(pg_size) << 684 CMDQ_REGISTER_MR_LOG2_PG_SIZE_SFT) & 685 CMDQ_REGISTER_MR_LOG2_PG_SIZE_MASK); 686 req.log2_pbl_pg_size = cpu_to_le16(((ilog2(PAGE_SIZE) << 687 CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_SFT) & 688 CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_MASK)); 689 req.access = (mr->flags & 0xFFFF); 690 req.va = cpu_to_le64(mr->va); 691 req.key = cpu_to_le32(mr->lkey); 692 if (_is_alloc_mr_unified(res->dattr)) { 693 flags = 0; 694 req.key = cpu_to_le32(mr->pd->id); 695 flags |= CMDQ_REGISTER_MR_FLAGS_ALLOC_MR; 696 req.flags = cpu_to_le16(flags); 697 } 698 req.mr_size = cpu_to_le64(mr->total_size); 699 700 bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, NULL, sizeof(req), 701 sizeof(resp), block); 702 rc = bnxt_qplib_rcfw_send_message(rcfw, &msg); 703 if (rc) 704 goto fail; 705 706 if (_is_alloc_mr_unified(res->dattr)) { 707 mr->lkey = le32_to_cpu(resp.xid); 708 mr->rkey = mr->lkey; 709 } 710 711 return 0; 712 fail: 713 if (mr->hwq.max_elements) 714 bnxt_qplib_free_hwq(res, &mr->hwq); 715 return rc; 716 } 717 718 int bnxt_qplib_alloc_fast_reg_page_list(struct bnxt_qplib_res *res, 719 struct bnxt_qplib_frpl *frpl, 720 int max_pg_ptrs) 721 { 722 struct bnxt_qplib_hwq_attr hwq_attr = {}; 723 struct bnxt_qplib_sg_info sginfo = {}; 724 int pg_ptrs, rc; 725 726 /* Re-calculate the max to fit the HWQ allocation model */ 727 pg_ptrs = roundup_pow_of_two(max_pg_ptrs); 728 729 sginfo.pgsize = PAGE_SIZE; 730 sginfo.nopte = true; 731 732 hwq_attr.res = res; 733 hwq_attr.depth = pg_ptrs; 734 hwq_attr.stride = PAGE_SIZE; 735 hwq_attr.sginfo = &sginfo; 736 hwq_attr.type = HWQ_TYPE_CTX; 737 rc = bnxt_qplib_alloc_init_hwq(&frpl->hwq, &hwq_attr); 738 if (!rc) 739 frpl->max_pg_ptrs = pg_ptrs; 740 741 return rc; 742 } 743 744 void bnxt_qplib_free_fast_reg_page_list(struct bnxt_qplib_res *res, 745 struct bnxt_qplib_frpl *frpl) 746 { 747 bnxt_qplib_free_hwq(res, &frpl->hwq); 748 } 749 750 int bnxt_qplib_map_tc2cos(struct bnxt_qplib_res *res, u16 *cids) 751 { 752 struct bnxt_qplib_rcfw *rcfw = res->rcfw; 753 struct creq_map_tc_to_cos_resp resp = {}; 754 struct bnxt_qplib_cmdqmsg msg = {}; 755 struct cmdq_map_tc_to_cos req = {}; 756 int rc; 757 758 bnxt_qplib_rcfw_cmd_prep(&req, CMDQ_BASE_OPCODE_MAP_TC_TO_COS, 759 sizeof(req)); 760 req.cos0 = cpu_to_le16(cids[0]); 761 req.cos1 = cpu_to_le16(cids[1]); 762 763 bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, NULL, sizeof(req), 764 sizeof(resp), 0); 765 rc = bnxt_qplib_rcfw_send_message(rcfw, &msg); 766 return rc; 767 } 768 769 static void bnxt_qplib_fill_cc_gen1(struct cmdq_modify_roce_cc_gen1_tlv *ext_req, 770 struct bnxt_qplib_cc_param_ext *cc_ext) 771 { 772 ext_req->modify_mask = cpu_to_le64(cc_ext->ext_mask); 773 cc_ext->ext_mask = 0; 774 ext_req->inactivity_th_hi = cpu_to_le16(cc_ext->inact_th_hi); 775 ext_req->min_time_between_cnps = cpu_to_le16(cc_ext->min_delta_cnp); 776 ext_req->init_cp = cpu_to_le16(cc_ext->init_cp); 777 ext_req->tr_update_mode = cc_ext->tr_update_mode; 778 ext_req->tr_update_cycles = cc_ext->tr_update_cyls; 779 ext_req->fr_num_rtts = cc_ext->fr_rtt; 780 ext_req->ai_rate_increase = cc_ext->ai_rate_incr; 781 ext_req->reduction_relax_rtts_th = cpu_to_le16(cc_ext->rr_rtt_th); 782 ext_req->additional_relax_cr_th = cpu_to_le16(cc_ext->ar_cr_th); 783 ext_req->cr_min_th = cpu_to_le16(cc_ext->cr_min_th); 784 ext_req->bw_avg_weight = cc_ext->bw_avg_weight; 785 ext_req->actual_cr_factor = cc_ext->cr_factor; 786 ext_req->max_cp_cr_th = cpu_to_le16(cc_ext->cr_th_max_cp); 787 ext_req->cp_bias_en = cc_ext->cp_bias_en; 788 ext_req->cp_bias = cc_ext->cp_bias; 789 ext_req->cnp_ecn = cc_ext->cnp_ecn; 790 ext_req->rtt_jitter_en = cc_ext->rtt_jitter_en; 791 ext_req->link_bytes_per_usec = cpu_to_le16(cc_ext->bytes_per_usec); 792 ext_req->reset_cc_cr_th = cpu_to_le16(cc_ext->cc_cr_reset_th); 793 ext_req->cr_width = cc_ext->cr_width; 794 ext_req->quota_period_min = cc_ext->min_quota; 795 ext_req->quota_period_max = cc_ext->max_quota; 796 ext_req->quota_period_abs_max = cc_ext->abs_max_quota; 797 ext_req->tr_lower_bound = cpu_to_le16(cc_ext->tr_lb); 798 ext_req->cr_prob_factor = cc_ext->cr_prob_fac; 799 ext_req->tr_prob_factor = cc_ext->tr_prob_fac; 800 ext_req->fairness_cr_th = cpu_to_le16(cc_ext->fair_cr_th); 801 ext_req->red_div = cc_ext->red_div; 802 ext_req->cnp_ratio_th = cc_ext->cnp_ratio_th; 803 ext_req->exp_ai_rtts = cpu_to_le16(cc_ext->ai_ext_rtt); 804 ext_req->exp_ai_cr_cp_ratio = cc_ext->exp_crcp_ratio; 805 ext_req->use_rate_table = cc_ext->low_rate_en; 806 ext_req->cp_exp_update_th = cpu_to_le16(cc_ext->cpcr_update_th); 807 ext_req->high_exp_ai_rtts_th1 = cpu_to_le16(cc_ext->ai_rtt_th1); 808 ext_req->high_exp_ai_rtts_th2 = cpu_to_le16(cc_ext->ai_rtt_th2); 809 ext_req->actual_cr_cong_free_rtts_th = cpu_to_le16(cc_ext->cf_rtt_th); 810 ext_req->severe_cong_cr_th1 = cpu_to_le16(cc_ext->sc_cr_th1); 811 ext_req->severe_cong_cr_th2 = cpu_to_le16(cc_ext->sc_cr_th2); 812 ext_req->link64B_per_rtt = cpu_to_le32(cc_ext->l64B_per_rtt); 813 ext_req->cc_ack_bytes = cc_ext->cc_ack_bytes; 814 ext_req->reduce_init_cong_free_rtts_th = cpu_to_le16(cc_ext->reduce_cf_rtt_th); 815 } 816 817 int bnxt_qplib_modify_cc(struct bnxt_qplib_res *res, 818 struct bnxt_qplib_cc_param *cc_param) 819 { 820 struct bnxt_qplib_tlv_modify_cc_req tlv_req = {}; 821 struct creq_modify_roce_cc_resp resp = {}; 822 struct bnxt_qplib_cmdqmsg msg = {}; 823 struct cmdq_modify_roce_cc *req; 824 int req_size; 825 void *cmd; 826 int rc; 827 828 /* Prepare the older base command */ 829 req = &tlv_req.base_req; 830 cmd = req; 831 req_size = sizeof(*req); 832 bnxt_qplib_rcfw_cmd_prep(req, CMDQ_BASE_OPCODE_MODIFY_ROCE_CC, 833 sizeof(*req)); 834 req->modify_mask = cpu_to_le32(cc_param->mask); 835 req->enable_cc = cc_param->enable; 836 req->g = cc_param->g; 837 req->num_phases_per_state = cc_param->nph_per_state; 838 req->time_per_phase = cc_param->time_pph; 839 req->pkts_per_phase = cc_param->pkts_pph; 840 req->init_cr = cpu_to_le16(cc_param->init_cr); 841 req->init_tr = cpu_to_le16(cc_param->init_tr); 842 req->tos_dscp_tos_ecn = (cc_param->tos_dscp << 843 CMDQ_MODIFY_ROCE_CC_TOS_DSCP_SFT) | 844 (cc_param->tos_ecn & 845 CMDQ_MODIFY_ROCE_CC_TOS_ECN_MASK); 846 req->alt_vlan_pcp = cc_param->alt_vlan_pcp; 847 req->alt_tos_dscp = cpu_to_le16(cc_param->alt_tos_dscp); 848 req->rtt = cpu_to_le16(cc_param->rtt); 849 req->tcp_cp = cpu_to_le16(cc_param->tcp_cp); 850 req->cc_mode = cc_param->cc_mode; 851 req->inactivity_th = cpu_to_le16(cc_param->inact_th); 852 853 /* For chip gen P5 onwards fill extended cmd and header */ 854 if (_is_chip_gen_p5_p7(res->cctx)) { 855 struct roce_tlv *hdr; 856 u32 payload; 857 u32 chunks; 858 859 cmd = &tlv_req; 860 req_size = sizeof(tlv_req); 861 /* Prepare primary tlv header */ 862 hdr = &tlv_req.tlv_hdr; 863 chunks = CHUNKS(sizeof(struct bnxt_qplib_tlv_modify_cc_req)); 864 payload = sizeof(struct cmdq_modify_roce_cc); 865 ROCE_1ST_TLV_PREP(hdr, chunks, payload, true); 866 /* Prepare secondary tlv header */ 867 hdr = (struct roce_tlv *)&tlv_req.ext_req; 868 payload = sizeof(struct cmdq_modify_roce_cc_gen1_tlv) - 869 sizeof(struct roce_tlv); 870 ROCE_EXT_TLV_PREP(hdr, TLV_TYPE_MODIFY_ROCE_CC_GEN1, payload, 871 false, true); 872 bnxt_qplib_fill_cc_gen1(&tlv_req.ext_req, &cc_param->cc_ext); 873 } 874 875 bnxt_qplib_fill_cmdqmsg(&msg, cmd, &resp, NULL, req_size, 876 sizeof(resp), 0); 877 rc = bnxt_qplib_rcfw_send_message(res->rcfw, &msg); 878 return rc; 879 } 880 881 static void bnxt_qplib_read_cc_gen1(struct bnxt_qplib_cc_param_ext *cc_ext, 882 struct creq_query_roce_cc_gen1_resp_sb_tlv *sb) 883 { 884 cc_ext->inact_th_hi = le16_to_cpu(sb->inactivity_th_hi); 885 cc_ext->min_delta_cnp = le16_to_cpu(sb->min_time_between_cnps); 886 cc_ext->init_cp = le16_to_cpu(sb->init_cp); 887 cc_ext->tr_update_mode = sb->tr_update_mode; 888 cc_ext->tr_update_cyls = sb->tr_update_cycles; 889 cc_ext->fr_rtt = sb->fr_num_rtts; 890 cc_ext->ai_rate_incr = sb->ai_rate_increase; 891 cc_ext->rr_rtt_th = le16_to_cpu(sb->reduction_relax_rtts_th); 892 cc_ext->ar_cr_th = le16_to_cpu(sb->additional_relax_cr_th); 893 cc_ext->cr_min_th = le16_to_cpu(sb->cr_min_th); 894 cc_ext->bw_avg_weight = sb->bw_avg_weight; 895 cc_ext->cr_factor = sb->actual_cr_factor; 896 cc_ext->cr_th_max_cp = le16_to_cpu(sb->max_cp_cr_th); 897 cc_ext->cp_bias_en = sb->cp_bias_en; 898 cc_ext->cp_bias = sb->cp_bias; 899 cc_ext->cnp_ecn = sb->cnp_ecn; 900 cc_ext->rtt_jitter_en = sb->rtt_jitter_en; 901 cc_ext->bytes_per_usec = le16_to_cpu(sb->link_bytes_per_usec); 902 cc_ext->cc_cr_reset_th = le16_to_cpu(sb->reset_cc_cr_th); 903 cc_ext->cr_width = sb->cr_width; 904 cc_ext->min_quota = sb->quota_period_min; 905 cc_ext->max_quota = sb->quota_period_max; 906 cc_ext->abs_max_quota = sb->quota_period_abs_max; 907 cc_ext->tr_lb = le16_to_cpu(sb->tr_lower_bound); 908 cc_ext->cr_prob_fac = sb->cr_prob_factor; 909 cc_ext->tr_prob_fac = sb->tr_prob_factor; 910 cc_ext->fair_cr_th = le16_to_cpu(sb->fairness_cr_th); 911 cc_ext->red_div = sb->red_div; 912 cc_ext->cnp_ratio_th = sb->cnp_ratio_th; 913 cc_ext->ai_ext_rtt = le16_to_cpu(sb->exp_ai_rtts); 914 cc_ext->exp_crcp_ratio = sb->exp_ai_cr_cp_ratio; 915 cc_ext->low_rate_en = sb->use_rate_table; 916 cc_ext->cpcr_update_th = le16_to_cpu(sb->cp_exp_update_th); 917 cc_ext->ai_rtt_th1 = le16_to_cpu(sb->high_exp_ai_rtts_th1); 918 cc_ext->ai_rtt_th2 = le16_to_cpu(sb->high_exp_ai_rtts_th2); 919 cc_ext->cf_rtt_th = le16_to_cpu(sb->actual_cr_cong_free_rtts_th); 920 cc_ext->sc_cr_th1 = le16_to_cpu(sb->severe_cong_cr_th1); 921 cc_ext->sc_cr_th2 = le16_to_cpu(sb->severe_cong_cr_th2); 922 cc_ext->l64B_per_rtt = le32_to_cpu(sb->link64B_per_rtt); 923 cc_ext->cc_ack_bytes = sb->cc_ack_bytes; 924 cc_ext->reduce_cf_rtt_th = le16_to_cpu(sb->reduce_init_cong_free_rtts_th); 925 } 926 927 int bnxt_qplib_query_cc_param(struct bnxt_qplib_res *res, 928 struct bnxt_qplib_cc_param *cc_param) 929 { 930 struct creq_query_roce_cc_gen1_resp_sb_tlv *gen1_sb; 931 struct bnxt_qplib_tlv_query_rcc_sb *ext_sb; 932 struct bnxt_qplib_rcfw *rcfw = res->rcfw; 933 struct creq_query_roce_cc_resp resp = {}; 934 struct creq_query_roce_cc_resp_sb *sb; 935 struct bnxt_qplib_cmdqmsg msg = {}; 936 struct cmdq_query_roce_cc req = {}; 937 struct bnxt_qplib_rcfw_sbuf sbuf; 938 size_t resp_size; 939 int rc; 940 941 /* Query the parameters from chip */ 942 bnxt_qplib_rcfw_cmd_prep(&req, CMDQ_BASE_OPCODE_QUERY_ROCE_CC, 943 sizeof(req)); 944 if (_is_chip_gen_p5_p7(res->cctx)) 945 resp_size = sizeof(*ext_sb); 946 else 947 resp_size = sizeof(*sb); 948 sbuf.size = ALIGN(resp_size, BNXT_QPLIB_CMDQE_UNITS); 949 sbuf.sb = dma_zalloc_coherent(&rcfw->pdev->dev, sbuf.size, 950 &sbuf.dma_addr, GFP_KERNEL); 951 if (!sbuf.sb) 952 return -ENOMEM; 953 954 req.resp_size = sbuf.size / BNXT_QPLIB_CMDQE_UNITS; 955 bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, &sbuf, sizeof(req), 956 sizeof(resp), 0); 957 rc = bnxt_qplib_rcfw_send_message(res->rcfw, &msg); 958 if (rc) { 959 dev_dbg(&res->pdev->dev, "%s:Query CC param failed:0x%x\n", 960 __func__, rc); 961 goto out; 962 } 963 964 ext_sb = sbuf.sb; 965 gen1_sb = &ext_sb->gen1_sb; 966 sb = _is_chip_gen_p5_p7(res->cctx) ? &ext_sb->base_sb : 967 (struct creq_query_roce_cc_resp_sb *)ext_sb; 968 969 cc_param->enable = sb->enable_cc & CREQ_QUERY_ROCE_CC_RESP_SB_ENABLE_CC; 970 cc_param->tos_ecn = (sb->tos_dscp_tos_ecn & 971 CREQ_QUERY_ROCE_CC_RESP_SB_TOS_ECN_MASK) >> 972 CREQ_QUERY_ROCE_CC_RESP_SB_TOS_ECN_SFT; 973 cc_param->tos_dscp = (sb->tos_dscp_tos_ecn & 974 CREQ_QUERY_ROCE_CC_RESP_SB_TOS_DSCP_MASK) >> 975 CREQ_QUERY_ROCE_CC_RESP_SB_TOS_DSCP_SFT; 976 cc_param->alt_tos_dscp = sb->alt_tos_dscp; 977 cc_param->alt_vlan_pcp = sb->alt_vlan_pcp; 978 979 cc_param->g = sb->g; 980 cc_param->nph_per_state = sb->num_phases_per_state; 981 cc_param->init_cr = le16_to_cpu(sb->init_cr); 982 cc_param->init_tr = le16_to_cpu(sb->init_tr); 983 cc_param->cc_mode = sb->cc_mode; 984 cc_param->inact_th = le16_to_cpu(sb->inactivity_th); 985 cc_param->rtt = le16_to_cpu(sb->rtt); 986 cc_param->tcp_cp = le16_to_cpu(sb->tcp_cp); 987 cc_param->time_pph = sb->time_per_phase; 988 cc_param->pkts_pph = sb->pkts_per_phase; 989 if (_is_chip_gen_p5_p7(res->cctx)) 990 bnxt_qplib_read_cc_gen1(&cc_param->cc_ext, gen1_sb); 991 out: 992 dma_free_coherent(&rcfw->pdev->dev, sbuf.size, 993 sbuf.sb, sbuf.dma_addr); 994 return rc; 995 } 996 997 998 int bnxt_qplib_get_roce_error_stats(struct bnxt_qplib_rcfw *rcfw, 999 struct bnxt_qplib_roce_stats *stats, 1000 struct bnxt_qplib_query_stats_info *sinfo) 1001 { 1002 struct creq_query_roce_stats_resp resp = {}; 1003 struct creq_query_roce_stats_resp_sb *sb; 1004 struct cmdq_query_roce_stats req = {}; 1005 struct bnxt_qplib_cmdqmsg msg = {}; 1006 struct bnxt_qplib_rcfw_sbuf sbuf; 1007 u16 cmd_flags = 0; 1008 u32 fn_id = 0; 1009 int rc = 0; 1010 1011 bnxt_qplib_rcfw_cmd_prep(&req, CMDQ_BASE_OPCODE_QUERY_ROCE_STATS, 1012 sizeof(req)); 1013 1014 sbuf.size = sizeof(*sb); 1015 sbuf.sb = dma_zalloc_coherent(&rcfw->pdev->dev, sbuf.size, 1016 &sbuf.dma_addr, GFP_KERNEL); 1017 if (!sbuf.sb) 1018 return -ENOMEM; 1019 sb = sbuf.sb; 1020 1021 if (rcfw->res->cctx->hwrm_intf_ver >= HWRM_VERSION_ROCE_STATS_FN_ID) { 1022 if (sinfo->function_id != 0xFFFFFFFF) { 1023 cmd_flags = CMDQ_QUERY_ROCE_STATS_FLAGS_FUNCTION_ID; 1024 if (sinfo->vf_valid) { 1025 fn_id = CMDQ_QUERY_ROCE_STATS_VF_VALID; 1026 fn_id |= (sinfo->function_id << 1027 CMDQ_QUERY_ROCE_STATS_VF_NUM_SFT) & 1028 CMDQ_QUERY_ROCE_STATS_VF_NUM_MASK; 1029 } else { 1030 fn_id = sinfo->function_id & 1031 CMDQ_QUERY_ROCE_STATS_PF_NUM_MASK; 1032 } 1033 } 1034 1035 req.flags = cpu_to_le16(cmd_flags); 1036 req.function_id = cpu_to_le32(fn_id); 1037 1038 if (sinfo->collection_id != 0xFF) { 1039 cmd_flags |= CMDQ_QUERY_ROCE_STATS_FLAGS_COLLECTION_ID; 1040 req.collection_id = sinfo->collection_id; 1041 } 1042 } else { 1043 /* For older HWRM version, the command length has to be 1044 * adjusted. 8 bytes are more in the newer command. 1045 * So subtract these 8 bytes for older HWRM version. 1046 * command units are adjusted inside 1047 * bnxt_qplib_rcfw_send_message. 1048 */ 1049 req.cmd_size -= 8; 1050 } 1051 1052 req.resp_size = sbuf.size / BNXT_QPLIB_CMDQE_UNITS; 1053 bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, &sbuf, sizeof(req), 1054 sizeof(resp), 0); 1055 rc = bnxt_qplib_rcfw_send_message(rcfw, &msg); 1056 if (rc) 1057 goto bail; 1058 /* Extract the context from the side buffer */ 1059 stats->to_retransmits = le64_to_cpu(sb->to_retransmits); 1060 stats->seq_err_naks_rcvd = le64_to_cpu(sb->seq_err_naks_rcvd); 1061 stats->max_retry_exceeded = le64_to_cpu(sb->max_retry_exceeded); 1062 stats->rnr_naks_rcvd = le64_to_cpu(sb->rnr_naks_rcvd); 1063 stats->missing_resp = le64_to_cpu(sb->missing_resp); 1064 stats->unrecoverable_err = le64_to_cpu(sb->unrecoverable_err); 1065 stats->bad_resp_err = le64_to_cpu(sb->bad_resp_err); 1066 stats->local_qp_op_err = le64_to_cpu(sb->local_qp_op_err); 1067 stats->local_protection_err = le64_to_cpu(sb->local_protection_err); 1068 stats->mem_mgmt_op_err = le64_to_cpu(sb->mem_mgmt_op_err); 1069 stats->remote_invalid_req_err = le64_to_cpu(sb->remote_invalid_req_err); 1070 stats->remote_access_err = le64_to_cpu(sb->remote_access_err); 1071 stats->remote_op_err = le64_to_cpu(sb->remote_op_err); 1072 stats->dup_req = le64_to_cpu(sb->dup_req); 1073 stats->res_exceed_max = le64_to_cpu(sb->res_exceed_max); 1074 stats->res_length_mismatch = le64_to_cpu(sb->res_length_mismatch); 1075 stats->res_exceeds_wqe = le64_to_cpu(sb->res_exceeds_wqe); 1076 stats->res_opcode_err = le64_to_cpu(sb->res_opcode_err); 1077 stats->res_rx_invalid_rkey = le64_to_cpu(sb->res_rx_invalid_rkey); 1078 stats->res_rx_domain_err = le64_to_cpu(sb->res_rx_domain_err); 1079 stats->res_rx_no_perm = le64_to_cpu(sb->res_rx_no_perm); 1080 stats->res_rx_range_err = le64_to_cpu(sb->res_rx_range_err); 1081 stats->res_tx_invalid_rkey = le64_to_cpu(sb->res_tx_invalid_rkey); 1082 stats->res_tx_domain_err = le64_to_cpu(sb->res_tx_domain_err); 1083 stats->res_tx_no_perm = le64_to_cpu(sb->res_tx_no_perm); 1084 stats->res_tx_range_err = le64_to_cpu(sb->res_tx_range_err); 1085 stats->res_irrq_oflow = le64_to_cpu(sb->res_irrq_oflow); 1086 stats->res_unsup_opcode = le64_to_cpu(sb->res_unsup_opcode); 1087 stats->res_unaligned_atomic = le64_to_cpu(sb->res_unaligned_atomic); 1088 stats->res_rem_inv_err = le64_to_cpu(sb->res_rem_inv_err); 1089 stats->res_mem_error = le64_to_cpu(sb->res_mem_error); 1090 stats->res_srq_err = le64_to_cpu(sb->res_srq_err); 1091 stats->res_cmp_err = le64_to_cpu(sb->res_cmp_err); 1092 stats->res_invalid_dup_rkey = le64_to_cpu(sb->res_invalid_dup_rkey); 1093 stats->res_wqe_format_err = le64_to_cpu(sb->res_wqe_format_err); 1094 stats->res_cq_load_err = le64_to_cpu(sb->res_cq_load_err); 1095 stats->res_srq_load_err = le64_to_cpu(sb->res_srq_load_err); 1096 stats->res_tx_pci_err = le64_to_cpu(sb->res_tx_pci_err); 1097 stats->res_rx_pci_err = le64_to_cpu(sb->res_rx_pci_err); 1098 1099 if (!rcfw->init_oos_stats) { 1100 rcfw->oos_prev = le64_to_cpu(sb->res_oos_drop_count); 1101 rcfw->init_oos_stats = true; 1102 } else { 1103 stats->res_oos_drop_count += (le64_to_cpu(sb->res_oos_drop_count) - 1104 rcfw->oos_prev) & 1105 BNXT_QPLIB_OOS_COUNT_MASK; 1106 rcfw->oos_prev = le64_to_cpu(sb->res_oos_drop_count); 1107 } 1108 1109 stats->active_qp_count_p0 = le64_to_cpu(sb->active_qp_count_p0); 1110 stats->active_qp_count_p1 = le64_to_cpu(sb->active_qp_count_p1); 1111 stats->active_qp_count_p2 = le64_to_cpu(sb->active_qp_count_p2); 1112 stats->active_qp_count_p3 = le64_to_cpu(sb->active_qp_count_p3); 1113 bail: 1114 dma_free_coherent(&rcfw->pdev->dev, sbuf.size, 1115 sbuf.sb, sbuf.dma_addr); 1116 return rc; 1117 } 1118 1119 int bnxt_qplib_set_link_aggr_mode(struct bnxt_qplib_res *res, 1120 u8 aggr_mode, u8 member_port_map, 1121 u8 active_port_map, bool aggr_en, 1122 u32 stats_fw_id) 1123 { 1124 struct creq_set_link_aggr_mode_resources_resp resp = {}; 1125 struct cmdq_set_link_aggr_mode_cc req = {}; 1126 struct bnxt_qplib_rcfw *rcfw = res->rcfw; 1127 struct bnxt_qplib_cmdqmsg msg = {}; 1128 int rc = 0; 1129 1130 bnxt_qplib_rcfw_cmd_prep(&req, CMDQ_BASE_OPCODE_SET_LINK_AGGR_MODE, 1131 sizeof(req)); 1132 1133 req.aggr_enable = aggr_en; 1134 req.active_port_map = active_port_map; 1135 req.member_port_map = member_port_map; 1136 req.link_aggr_mode = aggr_mode; 1137 1138 /* need to specify only second port stats ctx id for now */ 1139 req.stat_ctx_id[1] = cpu_to_le16((u16)(stats_fw_id)); 1140 1141 req.modify_mask = 1142 cpu_to_le32(CMDQ_SET_LINK_AGGR_MODE_MODIFY_MASK_AGGR_EN | 1143 CMDQ_SET_LINK_AGGR_MODE_MODIFY_MASK_ACTIVE_PORT_MAP | 1144 CMDQ_SET_LINK_AGGR_MODE_MODIFY_MASK_MEMBER_PORT_MAP | 1145 CMDQ_SET_LINK_AGGR_MODE_MODIFY_MASK_AGGR_MODE | 1146 CMDQ_SET_LINK_AGGR_MODE_MODIFY_MASK_STAT_CTX_ID); 1147 1148 bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, NULL, sizeof(req), 1149 sizeof(resp), 0); 1150 rc = bnxt_qplib_rcfw_send_message(rcfw, &msg); 1151 if (rc) 1152 dev_err(&res->pdev->dev, 1153 "QPLIB: Failed to set link aggr mode, %#x\n", rc); 1154 1155 return rc; 1156 } 1157 1158 int bnxt_qplib_qext_stat(struct bnxt_qplib_rcfw *rcfw, u32 fid, 1159 struct bnxt_qplib_ext_stat *estat, 1160 struct bnxt_qplib_query_stats_info *sinfo) 1161 { 1162 struct creq_query_roce_stats_ext_resp resp = {}; 1163 struct creq_query_roce_stats_ext_resp_sb *sb; 1164 struct cmdq_query_roce_stats_ext req = {}; 1165 struct bnxt_qplib_cmdqmsg msg = {}; 1166 struct bnxt_qplib_rcfw_sbuf sbuf; 1167 int rc; 1168 1169 sbuf.size = sizeof(*sb); 1170 sbuf.sb = dma_zalloc_coherent(&rcfw->pdev->dev, sbuf.size, 1171 &sbuf.dma_addr, GFP_KERNEL); 1172 if (!sbuf.sb) { 1173 dev_err(&rcfw->pdev->dev, 1174 "QPLIB: SP: QUERY_ROCE_STATS_EXT alloc sb failed\n"); 1175 return -ENOMEM; 1176 } 1177 sb = sbuf.sb; 1178 1179 bnxt_qplib_rcfw_cmd_prep(&req, 1180 CMDQ_QUERY_ROCE_STATS_EXT_OPCODE_QUERY_ROCE_STATS, 1181 sizeof(req)); 1182 req.resp_size = sbuf.size; 1183 req.resp_addr = cpu_to_le64(sbuf.dma_addr); 1184 req.flags = cpu_to_le16(CMDQ_QUERY_ROCE_STATS_EXT_FLAGS_FUNCTION_ID); 1185 if (_is_chip_p7(rcfw->res->cctx) && rcfw->res->is_vf) { 1186 if (sinfo->vf_valid) 1187 req.function_id = 1188 cpu_to_le32(CMDQ_QUERY_ROCE_STATS_EXT_VF_VALID | 1189 (fid << CMDQ_QUERY_ROCE_STATS_EXT_VF_NUM_SFT)); 1190 else 1191 req.flags = cpu_to_le16(0); 1192 } else { 1193 req.function_id = cpu_to_le32(fid); 1194 } 1195 1196 bnxt_qplib_fill_cmdqmsg(&msg, &req, &resp, &sbuf, sizeof(req), 1197 sizeof(resp), 0); 1198 rc = bnxt_qplib_rcfw_send_message(rcfw, &msg); 1199 if (rc) 1200 goto bail; 1201 1202 /* dump when dyndbg is enabled */ 1203 if (bootverbose) 1204 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, sb, sizeof(*sb)); 1205 1206 estat->tx_atomic_req = le64_to_cpu(sb->tx_atomic_req_pkts); 1207 estat->tx_read_req = le64_to_cpu(sb->tx_read_req_pkts); 1208 estat->tx_read_res = le64_to_cpu(sb->tx_read_res_pkts); 1209 estat->tx_write_req = le64_to_cpu(sb->tx_write_req_pkts); 1210 estat->tx_send_req = le64_to_cpu(sb->tx_send_req_pkts); 1211 estat->tx_roce_pkts = le64_to_cpu(sb->tx_roce_pkts); 1212 estat->tx_roce_bytes = le64_to_cpu(sb->tx_roce_bytes); 1213 estat->rx_atomic_req = le64_to_cpu(sb->rx_atomic_req_pkts); 1214 estat->rx_read_req = le64_to_cpu(sb->rx_read_req_pkts); 1215 estat->rx_read_res = le64_to_cpu(sb->rx_read_res_pkts); 1216 estat->rx_write_req = le64_to_cpu(sb->rx_write_req_pkts); 1217 estat->rx_send_req = le64_to_cpu(sb->rx_send_req_pkts); 1218 estat->rx_roce_pkts = le64_to_cpu(sb->rx_roce_pkts); 1219 estat->rx_roce_bytes = le64_to_cpu(sb->rx_roce_bytes); 1220 estat->rx_roce_good_pkts = le64_to_cpu(sb->rx_roce_good_pkts); 1221 estat->rx_roce_good_bytes = le64_to_cpu(sb->rx_roce_good_bytes); 1222 estat->rx_out_of_buffer = le64_to_cpu(sb->rx_out_of_buffer_pkts); 1223 estat->rx_out_of_sequence = le64_to_cpu(sb->rx_out_of_sequence_pkts); 1224 estat->tx_cnp = le64_to_cpu(sb->tx_cnp_pkts); 1225 estat->rx_cnp = le64_to_cpu(sb->rx_cnp_pkts); 1226 estat->rx_ecn_marked = le64_to_cpu(sb->rx_ecn_marked_pkts); 1227 estat->seq_err_naks_rcvd = le64_to_cpu(sb->seq_err_naks_rcvd); 1228 estat->rnr_naks_rcvd = le64_to_cpu(sb->rnr_naks_rcvd); 1229 estat->missing_resp = le64_to_cpu(sb->missing_resp); 1230 estat->to_retransmits = le64_to_cpu(sb->to_retransmit); 1231 estat->dup_req = le64_to_cpu(sb->dup_req); 1232 estat->rx_dcn_payload_cut = le64_to_cpu(sb->rx_dcn_payload_cut); 1233 estat->te_bypassed = le64_to_cpu(sb->te_bypassed); 1234 bail: 1235 dma_free_coherent(&rcfw->pdev->dev, sbuf.size, 1236 sbuf.sb, sbuf.dma_addr); 1237 return rc; 1238 } 1239