1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2021, The Linux Foundation. All rights reserved. 4 * Copyright (c) 2022, Linaro Limited 5 */ 6 7#include <dt-bindings/clock/qcom,dispcc-sc8280xp.h> 8#include <dt-bindings/clock/qcom,gcc-sc8280xp.h> 9#include <dt-bindings/clock/qcom,gpucc-sc8280xp.h> 10#include <dt-bindings/clock/qcom,rpmh.h> 11#include <dt-bindings/clock/qcom,sc8280xp-camcc.h> 12#include <dt-bindings/clock/qcom,sc8280xp-lpasscc.h> 13#include <dt-bindings/dma/qcom-gpi.h> 14#include <dt-bindings/interconnect/qcom,osm-l3.h> 15#include <dt-bindings/interconnect/qcom,sc8280xp.h> 16#include <dt-bindings/interrupt-controller/arm-gic.h> 17#include <dt-bindings/mailbox/qcom-ipcc.h> 18#include <dt-bindings/phy/phy-qcom-qmp.h> 19#include <dt-bindings/power/qcom-rpmpd.h> 20#include <dt-bindings/soc/qcom,gpr.h> 21#include <dt-bindings/soc/qcom,rpmh-rsc.h> 22#include <dt-bindings/sound/qcom,q6afe.h> 23#include <dt-bindings/thermal/thermal.h> 24 25/ { 26 interrupt-parent = <&intc>; 27 28 #address-cells = <2>; 29 #size-cells = <2>; 30 31 clocks { 32 xo_board_clk: xo-board-clk { 33 compatible = "fixed-clock"; 34 #clock-cells = <0>; 35 }; 36 37 sleep_clk: sleep-clk { 38 compatible = "fixed-clock"; 39 #clock-cells = <0>; 40 clock-frequency = <32764>; 41 }; 42 }; 43 44 cpus { 45 #address-cells = <2>; 46 #size-cells = <0>; 47 48 cpu0: cpu@0 { 49 device_type = "cpu"; 50 compatible = "arm,cortex-a78c"; 51 reg = <0x0 0x0>; 52 clocks = <&cpufreq_hw 0>; 53 enable-method = "psci"; 54 capacity-dmips-mhz = <981>; 55 dynamic-power-coefficient = <549>; 56 next-level-cache = <&l2_0>; 57 power-domains = <&cpu_pd0>; 58 power-domain-names = "psci"; 59 qcom,freq-domain = <&cpufreq_hw 0>; 60 operating-points-v2 = <&cpu0_opp_table>; 61 interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 62 #cooling-cells = <2>; 63 l2_0: l2-cache { 64 compatible = "cache"; 65 cache-level = <2>; 66 cache-unified; 67 next-level-cache = <&l3_0>; 68 l3_0: l3-cache { 69 compatible = "cache"; 70 cache-level = <3>; 71 cache-unified; 72 }; 73 }; 74 }; 75 76 cpu1: cpu@100 { 77 device_type = "cpu"; 78 compatible = "arm,cortex-a78c"; 79 reg = <0x0 0x100>; 80 clocks = <&cpufreq_hw 0>; 81 enable-method = "psci"; 82 capacity-dmips-mhz = <981>; 83 dynamic-power-coefficient = <549>; 84 next-level-cache = <&l2_100>; 85 power-domains = <&cpu_pd1>; 86 power-domain-names = "psci"; 87 qcom,freq-domain = <&cpufreq_hw 0>; 88 operating-points-v2 = <&cpu0_opp_table>; 89 interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 90 #cooling-cells = <2>; 91 l2_100: l2-cache { 92 compatible = "cache"; 93 cache-level = <2>; 94 cache-unified; 95 next-level-cache = <&l3_0>; 96 }; 97 }; 98 99 cpu2: cpu@200 { 100 device_type = "cpu"; 101 compatible = "arm,cortex-a78c"; 102 reg = <0x0 0x200>; 103 clocks = <&cpufreq_hw 0>; 104 enable-method = "psci"; 105 capacity-dmips-mhz = <981>; 106 dynamic-power-coefficient = <549>; 107 next-level-cache = <&l2_200>; 108 power-domains = <&cpu_pd2>; 109 power-domain-names = "psci"; 110 qcom,freq-domain = <&cpufreq_hw 0>; 111 operating-points-v2 = <&cpu0_opp_table>; 112 interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 113 #cooling-cells = <2>; 114 l2_200: l2-cache { 115 compatible = "cache"; 116 cache-level = <2>; 117 cache-unified; 118 next-level-cache = <&l3_0>; 119 }; 120 }; 121 122 cpu3: cpu@300 { 123 device_type = "cpu"; 124 compatible = "arm,cortex-a78c"; 125 reg = <0x0 0x300>; 126 clocks = <&cpufreq_hw 0>; 127 enable-method = "psci"; 128 capacity-dmips-mhz = <981>; 129 dynamic-power-coefficient = <549>; 130 next-level-cache = <&l2_300>; 131 power-domains = <&cpu_pd3>; 132 power-domain-names = "psci"; 133 qcom,freq-domain = <&cpufreq_hw 0>; 134 operating-points-v2 = <&cpu0_opp_table>; 135 interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 136 #cooling-cells = <2>; 137 l2_300: l2-cache { 138 compatible = "cache"; 139 cache-level = <2>; 140 cache-unified; 141 next-level-cache = <&l3_0>; 142 }; 143 }; 144 145 cpu4: cpu@400 { 146 device_type = "cpu"; 147 compatible = "arm,cortex-x1c"; 148 reg = <0x0 0x400>; 149 clocks = <&cpufreq_hw 1>; 150 enable-method = "psci"; 151 capacity-dmips-mhz = <1024>; 152 dynamic-power-coefficient = <590>; 153 next-level-cache = <&l2_400>; 154 power-domains = <&cpu_pd4>; 155 power-domain-names = "psci"; 156 qcom,freq-domain = <&cpufreq_hw 1>; 157 operating-points-v2 = <&cpu4_opp_table>; 158 interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 159 #cooling-cells = <2>; 160 l2_400: l2-cache { 161 compatible = "cache"; 162 cache-level = <2>; 163 cache-unified; 164 next-level-cache = <&l3_0>; 165 }; 166 }; 167 168 cpu5: cpu@500 { 169 device_type = "cpu"; 170 compatible = "arm,cortex-x1c"; 171 reg = <0x0 0x500>; 172 clocks = <&cpufreq_hw 1>; 173 enable-method = "psci"; 174 capacity-dmips-mhz = <1024>; 175 dynamic-power-coefficient = <590>; 176 next-level-cache = <&l2_500>; 177 power-domains = <&cpu_pd5>; 178 power-domain-names = "psci"; 179 qcom,freq-domain = <&cpufreq_hw 1>; 180 operating-points-v2 = <&cpu4_opp_table>; 181 interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 182 #cooling-cells = <2>; 183 l2_500: l2-cache { 184 compatible = "cache"; 185 cache-level = <2>; 186 cache-unified; 187 next-level-cache = <&l3_0>; 188 }; 189 }; 190 191 cpu6: cpu@600 { 192 device_type = "cpu"; 193 compatible = "arm,cortex-x1c"; 194 reg = <0x0 0x600>; 195 clocks = <&cpufreq_hw 1>; 196 enable-method = "psci"; 197 capacity-dmips-mhz = <1024>; 198 dynamic-power-coefficient = <590>; 199 next-level-cache = <&l2_600>; 200 power-domains = <&cpu_pd6>; 201 power-domain-names = "psci"; 202 qcom,freq-domain = <&cpufreq_hw 1>; 203 operating-points-v2 = <&cpu4_opp_table>; 204 interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 205 #cooling-cells = <2>; 206 l2_600: l2-cache { 207 compatible = "cache"; 208 cache-level = <2>; 209 cache-unified; 210 next-level-cache = <&l3_0>; 211 }; 212 }; 213 214 cpu7: cpu@700 { 215 device_type = "cpu"; 216 compatible = "arm,cortex-x1c"; 217 reg = <0x0 0x700>; 218 clocks = <&cpufreq_hw 1>; 219 enable-method = "psci"; 220 capacity-dmips-mhz = <1024>; 221 dynamic-power-coefficient = <590>; 222 next-level-cache = <&l2_700>; 223 power-domains = <&cpu_pd7>; 224 power-domain-names = "psci"; 225 qcom,freq-domain = <&cpufreq_hw 1>; 226 operating-points-v2 = <&cpu4_opp_table>; 227 interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 228 #cooling-cells = <2>; 229 l2_700: l2-cache { 230 compatible = "cache"; 231 cache-level = <2>; 232 cache-unified; 233 next-level-cache = <&l3_0>; 234 }; 235 }; 236 237 cpu-map { 238 cluster0 { 239 core0 { 240 cpu = <&cpu0>; 241 }; 242 243 core1 { 244 cpu = <&cpu1>; 245 }; 246 247 core2 { 248 cpu = <&cpu2>; 249 }; 250 251 core3 { 252 cpu = <&cpu3>; 253 }; 254 255 core4 { 256 cpu = <&cpu4>; 257 }; 258 259 core5 { 260 cpu = <&cpu5>; 261 }; 262 263 core6 { 264 cpu = <&cpu6>; 265 }; 266 267 core7 { 268 cpu = <&cpu7>; 269 }; 270 }; 271 }; 272 273 idle-states { 274 entry-method = "psci"; 275 276 little_cpu_sleep_0: cpu-sleep-0-0 { 277 compatible = "arm,idle-state"; 278 idle-state-name = "little-rail-power-collapse"; 279 arm,psci-suspend-param = <0x40000004>; 280 entry-latency-us = <355>; 281 exit-latency-us = <909>; 282 min-residency-us = <3934>; 283 local-timer-stop; 284 }; 285 286 big_cpu_sleep_0: cpu-sleep-1-0 { 287 compatible = "arm,idle-state"; 288 idle-state-name = "big-rail-power-collapse"; 289 arm,psci-suspend-param = <0x40000004>; 290 entry-latency-us = <241>; 291 exit-latency-us = <1461>; 292 min-residency-us = <4488>; 293 local-timer-stop; 294 }; 295 }; 296 297 domain-idle-states { 298 cluster_sleep_0: cluster-sleep-0 { 299 compatible = "domain-idle-state"; 300 arm,psci-suspend-param = <0x4100c344>; 301 entry-latency-us = <3263>; 302 exit-latency-us = <6562>; 303 min-residency-us = <9987>; 304 }; 305 }; 306 }; 307 308 firmware { 309 scm: scm { 310 compatible = "qcom,scm-sc8280xp", "qcom,scm"; 311 interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>; 312 qcom,dload-mode = <&tcsr 0x13000>; 313 }; 314 }; 315 316 aggre1_noc: interconnect-aggre1-noc { 317 compatible = "qcom,sc8280xp-aggre1-noc"; 318 #interconnect-cells = <2>; 319 qcom,bcm-voters = <&apps_bcm_voter>; 320 }; 321 322 aggre2_noc: interconnect-aggre2-noc { 323 compatible = "qcom,sc8280xp-aggre2-noc"; 324 #interconnect-cells = <2>; 325 qcom,bcm-voters = <&apps_bcm_voter>; 326 }; 327 328 clk_virt: interconnect-clk-virt { 329 compatible = "qcom,sc8280xp-clk-virt"; 330 #interconnect-cells = <2>; 331 qcom,bcm-voters = <&apps_bcm_voter>; 332 }; 333 334 config_noc: interconnect-config-noc { 335 compatible = "qcom,sc8280xp-config-noc"; 336 #interconnect-cells = <2>; 337 qcom,bcm-voters = <&apps_bcm_voter>; 338 }; 339 340 dc_noc: interconnect-dc-noc { 341 compatible = "qcom,sc8280xp-dc-noc"; 342 #interconnect-cells = <2>; 343 qcom,bcm-voters = <&apps_bcm_voter>; 344 }; 345 346 gem_noc: interconnect-gem-noc { 347 compatible = "qcom,sc8280xp-gem-noc"; 348 #interconnect-cells = <2>; 349 qcom,bcm-voters = <&apps_bcm_voter>; 350 }; 351 352 lpass_noc: interconnect-lpass-ag-noc { 353 compatible = "qcom,sc8280xp-lpass-ag-noc"; 354 #interconnect-cells = <2>; 355 qcom,bcm-voters = <&apps_bcm_voter>; 356 }; 357 358 mc_virt: interconnect-mc-virt { 359 compatible = "qcom,sc8280xp-mc-virt"; 360 #interconnect-cells = <2>; 361 qcom,bcm-voters = <&apps_bcm_voter>; 362 }; 363 364 mmss_noc: interconnect-mmss-noc { 365 compatible = "qcom,sc8280xp-mmss-noc"; 366 #interconnect-cells = <2>; 367 qcom,bcm-voters = <&apps_bcm_voter>; 368 }; 369 370 nspa_noc: interconnect-nspa-noc { 371 compatible = "qcom,sc8280xp-nspa-noc"; 372 #interconnect-cells = <2>; 373 qcom,bcm-voters = <&apps_bcm_voter>; 374 }; 375 376 nspb_noc: interconnect-nspb-noc { 377 compatible = "qcom,sc8280xp-nspb-noc"; 378 #interconnect-cells = <2>; 379 qcom,bcm-voters = <&apps_bcm_voter>; 380 }; 381 382 system_noc: interconnect-system-noc { 383 compatible = "qcom,sc8280xp-system-noc"; 384 #interconnect-cells = <2>; 385 qcom,bcm-voters = <&apps_bcm_voter>; 386 }; 387 388 memory@80000000 { 389 device_type = "memory"; 390 /* We expect the bootloader to fill in the size */ 391 reg = <0x0 0x80000000 0x0 0x0>; 392 }; 393 394 cpu0_opp_table: opp-table-cpu0 { 395 compatible = "operating-points-v2"; 396 opp-shared; 397 398 opp-300000000 { 399 opp-hz = /bits/ 64 <300000000>; 400 opp-peak-kBps = <(300000 * 32)>; 401 }; 402 opp-403200000 { 403 opp-hz = /bits/ 64 <403200000>; 404 opp-peak-kBps = <(384000 * 32)>; 405 }; 406 opp-499200000 { 407 opp-hz = /bits/ 64 <499200000>; 408 opp-peak-kBps = <(480000 * 32)>; 409 }; 410 opp-595200000 { 411 opp-hz = /bits/ 64 <595200000>; 412 opp-peak-kBps = <(576000 * 32)>; 413 }; 414 opp-691200000 { 415 opp-hz = /bits/ 64 <691200000>; 416 opp-peak-kBps = <(672000 * 32)>; 417 }; 418 opp-806400000 { 419 opp-hz = /bits/ 64 <806400000>; 420 opp-peak-kBps = <(768000 * 32)>; 421 }; 422 opp-902400000 { 423 opp-hz = /bits/ 64 <902400000>; 424 opp-peak-kBps = <(864000 * 32)>; 425 }; 426 opp-1017600000 { 427 opp-hz = /bits/ 64 <1017600000>; 428 opp-peak-kBps = <(960000 * 32)>; 429 }; 430 opp-1113600000 { 431 opp-hz = /bits/ 64 <1113600000>; 432 opp-peak-kBps = <(1075200 * 32)>; 433 }; 434 opp-1209600000 { 435 opp-hz = /bits/ 64 <1209600000>; 436 opp-peak-kBps = <(1171200 * 32)>; 437 }; 438 opp-1324800000 { 439 opp-hz = /bits/ 64 <1324800000>; 440 opp-peak-kBps = <(1267200 * 32)>; 441 }; 442 opp-1440000000 { 443 opp-hz = /bits/ 64 <1440000000>; 444 opp-peak-kBps = <(1363200 * 32)>; 445 }; 446 opp-1555200000 { 447 opp-hz = /bits/ 64 <1555200000>; 448 opp-peak-kBps = <(1536000 * 32)>; 449 }; 450 opp-1670400000 { 451 opp-hz = /bits/ 64 <1670400000>; 452 opp-peak-kBps = <(1612800 * 32)>; 453 }; 454 opp-1785600000 { 455 opp-hz = /bits/ 64 <1785600000>; 456 opp-peak-kBps = <(1689600 * 32)>; 457 }; 458 opp-1881600000 { 459 opp-hz = /bits/ 64 <1881600000>; 460 opp-peak-kBps = <(1689600 * 32)>; 461 }; 462 opp-1996800000 { 463 opp-hz = /bits/ 64 <1996800000>; 464 opp-peak-kBps = <(1689600 * 32)>; 465 }; 466 opp-2112000000 { 467 opp-hz = /bits/ 64 <2112000000>; 468 opp-peak-kBps = <(1689600 * 32)>; 469 }; 470 opp-2227200000 { 471 opp-hz = /bits/ 64 <2227200000>; 472 opp-peak-kBps = <(1689600 * 32)>; 473 }; 474 opp-2342400000 { 475 opp-hz = /bits/ 64 <2342400000>; 476 opp-peak-kBps = <(1689600 * 32)>; 477 }; 478 opp-2438400000 { 479 opp-hz = /bits/ 64 <2438400000>; 480 opp-peak-kBps = <(1689600 * 32)>; 481 }; 482 }; 483 484 cpu4_opp_table: opp-table-cpu4 { 485 compatible = "operating-points-v2"; 486 opp-shared; 487 488 opp-825600000 { 489 opp-hz = /bits/ 64 <825600000>; 490 opp-peak-kBps = <(768000 * 32)>; 491 }; 492 opp-940800000 { 493 opp-hz = /bits/ 64 <940800000>; 494 opp-peak-kBps = <(864000 * 32)>; 495 }; 496 opp-1056000000 { 497 opp-hz = /bits/ 64 <1056000000>; 498 opp-peak-kBps = <(960000 * 32)>; 499 }; 500 opp-1171200000 { 501 opp-hz = /bits/ 64 <1171200000>; 502 opp-peak-kBps = <(1171200 * 32)>; 503 }; 504 opp-1286400000 { 505 opp-hz = /bits/ 64 <1286400000>; 506 opp-peak-kBps = <(1267200 * 32)>; 507 }; 508 opp-1401600000 { 509 opp-hz = /bits/ 64 <1401600000>; 510 opp-peak-kBps = <(1363200 * 32)>; 511 }; 512 opp-1516800000 { 513 opp-hz = /bits/ 64 <1516800000>; 514 opp-peak-kBps = <(1459200 * 32)>; 515 }; 516 opp-1632000000 { 517 opp-hz = /bits/ 64 <1632000000>; 518 opp-peak-kBps = <(1612800 * 32)>; 519 }; 520 opp-1747200000 { 521 opp-hz = /bits/ 64 <1747200000>; 522 opp-peak-kBps = <(1689600 * 32)>; 523 }; 524 opp-1862400000 { 525 opp-hz = /bits/ 64 <1862400000>; 526 opp-peak-kBps = <(1689600 * 32)>; 527 }; 528 opp-1977600000 { 529 opp-hz = /bits/ 64 <1977600000>; 530 opp-peak-kBps = <(1689600 * 32)>; 531 }; 532 opp-2073600000 { 533 opp-hz = /bits/ 64 <2073600000>; 534 opp-peak-kBps = <(1689600 * 32)>; 535 }; 536 opp-2169600000 { 537 opp-hz = /bits/ 64 <2169600000>; 538 opp-peak-kBps = <(1689600 * 32)>; 539 }; 540 opp-2284800000 { 541 opp-hz = /bits/ 64 <2284800000>; 542 opp-peak-kBps = <(1689600 * 32)>; 543 }; 544 opp-2400000000 { 545 opp-hz = /bits/ 64 <2400000000>; 546 opp-peak-kBps = <(1689600 * 32)>; 547 }; 548 opp-2496000000 { 549 opp-hz = /bits/ 64 <2496000000>; 550 opp-peak-kBps = <(1689600 * 32)>; 551 }; 552 opp-2592000000 { 553 opp-hz = /bits/ 64 <2592000000>; 554 opp-peak-kBps = <(1689600 * 32)>; 555 }; 556 opp-2688000000 { 557 opp-hz = /bits/ 64 <2688000000>; 558 opp-peak-kBps = <(1689600 * 32)>; 559 }; 560 opp-2803200000 { 561 opp-hz = /bits/ 64 <2803200000>; 562 opp-peak-kBps = <(1689600 * 32)>; 563 }; 564 opp-2899200000 { 565 opp-hz = /bits/ 64 <2899200000>; 566 opp-peak-kBps = <(1689600 * 32)>; 567 }; 568 opp-2995200000 { 569 opp-hz = /bits/ 64 <2995200000>; 570 opp-peak-kBps = <(1689600 * 32)>; 571 }; 572 }; 573 574 qup_opp_table_100mhz: opp-table-qup100mhz { 575 compatible = "operating-points-v2"; 576 577 opp-75000000 { 578 opp-hz = /bits/ 64 <75000000>; 579 required-opps = <&rpmhpd_opp_low_svs>; 580 }; 581 582 opp-100000000 { 583 opp-hz = /bits/ 64 <100000000>; 584 required-opps = <&rpmhpd_opp_svs>; 585 }; 586 }; 587 588 pmu { 589 compatible = "arm,armv8-pmuv3"; 590 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 591 }; 592 593 psci { 594 compatible = "arm,psci-1.0"; 595 method = "smc"; 596 597 cpu_pd0: power-domain-cpu0 { 598 #power-domain-cells = <0>; 599 power-domains = <&cluster_pd>; 600 domain-idle-states = <&little_cpu_sleep_0>; 601 }; 602 603 cpu_pd1: power-domain-cpu1 { 604 #power-domain-cells = <0>; 605 power-domains = <&cluster_pd>; 606 domain-idle-states = <&little_cpu_sleep_0>; 607 }; 608 609 cpu_pd2: power-domain-cpu2 { 610 #power-domain-cells = <0>; 611 power-domains = <&cluster_pd>; 612 domain-idle-states = <&little_cpu_sleep_0>; 613 }; 614 615 cpu_pd3: power-domain-cpu3 { 616 #power-domain-cells = <0>; 617 power-domains = <&cluster_pd>; 618 domain-idle-states = <&little_cpu_sleep_0>; 619 }; 620 621 cpu_pd4: power-domain-cpu4 { 622 #power-domain-cells = <0>; 623 power-domains = <&cluster_pd>; 624 domain-idle-states = <&big_cpu_sleep_0>; 625 }; 626 627 cpu_pd5: power-domain-cpu5 { 628 #power-domain-cells = <0>; 629 power-domains = <&cluster_pd>; 630 domain-idle-states = <&big_cpu_sleep_0>; 631 }; 632 633 cpu_pd6: power-domain-cpu6 { 634 #power-domain-cells = <0>; 635 power-domains = <&cluster_pd>; 636 domain-idle-states = <&big_cpu_sleep_0>; 637 }; 638 639 cpu_pd7: power-domain-cpu7 { 640 #power-domain-cells = <0>; 641 power-domains = <&cluster_pd>; 642 domain-idle-states = <&big_cpu_sleep_0>; 643 }; 644 645 cluster_pd: power-domain-cpu-cluster0 { 646 #power-domain-cells = <0>; 647 domain-idle-states = <&cluster_sleep_0>; 648 }; 649 }; 650 651 reserved-memory { 652 #address-cells = <2>; 653 #size-cells = <2>; 654 ranges; 655 656 reserved-region@80000000 { 657 reg = <0 0x80000000 0 0x860000>; 658 no-map; 659 }; 660 661 cmd_db: cmd-db-region@80860000 { 662 compatible = "qcom,cmd-db"; 663 reg = <0 0x80860000 0 0x20000>; 664 no-map; 665 }; 666 667 reserved-region@80880000 { 668 reg = <0 0x80880000 0 0x80000>; 669 no-map; 670 }; 671 672 smem_mem: smem-region@80900000 { 673 compatible = "qcom,smem"; 674 reg = <0 0x80900000 0 0x200000>; 675 no-map; 676 hwlocks = <&tcsr_mutex 3>; 677 }; 678 679 reserved-region@80b00000 { 680 reg = <0 0x80b00000 0 0x100000>; 681 no-map; 682 }; 683 684 reserved-region@83b00000 { 685 reg = <0 0x83b00000 0 0x1700000>; 686 no-map; 687 }; 688 689 reserved-region@85b00000 { 690 reg = <0 0x85b00000 0 0xc00000>; 691 no-map; 692 }; 693 694 pil_gpu_mem: gpu-mem@8bf00000 { 695 reg = <0 0x8bf00000 0 0x2000>; 696 no-map; 697 }; 698 699 pil_adsp_mem: adsp-region@86c00000 { 700 reg = <0 0x86c00000 0 0x2000000>; 701 no-map; 702 }; 703 704 pil_slpi_mem: slpi-region@88c00000 { 705 reg = <0 0x88c00000 0 0x1500000>; 706 no-map; 707 }; 708 709 pil_nsp0_mem: cdsp0-region@8a100000 { 710 reg = <0 0x8a100000 0 0x1e00000>; 711 no-map; 712 }; 713 714 pil_nsp1_mem: cdsp1-region@8c600000 { 715 reg = <0 0x8c600000 0 0x1e00000>; 716 no-map; 717 }; 718 719 reserved-region@aeb00000 { 720 reg = <0 0xaeb00000 0 0x16600000>; 721 no-map; 722 }; 723 }; 724 725 smp2p-adsp { 726 compatible = "qcom,smp2p"; 727 qcom,smem = <443>, <429>; 728 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 729 IPCC_MPROC_SIGNAL_SMP2P 730 IRQ_TYPE_EDGE_RISING>; 731 mboxes = <&ipcc IPCC_CLIENT_LPASS 732 IPCC_MPROC_SIGNAL_SMP2P>; 733 734 qcom,local-pid = <0>; 735 qcom,remote-pid = <2>; 736 737 smp2p_adsp_out: master-kernel { 738 qcom,entry-name = "master-kernel"; 739 #qcom,smem-state-cells = <1>; 740 }; 741 742 smp2p_adsp_in: slave-kernel { 743 qcom,entry-name = "slave-kernel"; 744 interrupt-controller; 745 #interrupt-cells = <2>; 746 }; 747 }; 748 749 smp2p-nsp0 { 750 compatible = "qcom,smp2p"; 751 qcom,smem = <94>, <432>; 752 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 753 IPCC_MPROC_SIGNAL_SMP2P 754 IRQ_TYPE_EDGE_RISING>; 755 mboxes = <&ipcc IPCC_CLIENT_CDSP 756 IPCC_MPROC_SIGNAL_SMP2P>; 757 758 qcom,local-pid = <0>; 759 qcom,remote-pid = <5>; 760 761 smp2p_nsp0_out: master-kernel { 762 qcom,entry-name = "master-kernel"; 763 #qcom,smem-state-cells = <1>; 764 }; 765 766 smp2p_nsp0_in: slave-kernel { 767 qcom,entry-name = "slave-kernel"; 768 interrupt-controller; 769 #interrupt-cells = <2>; 770 }; 771 }; 772 773 smp2p-nsp1 { 774 compatible = "qcom,smp2p"; 775 qcom,smem = <617>, <616>; 776 interrupts-extended = <&ipcc IPCC_CLIENT_NSP1 777 IPCC_MPROC_SIGNAL_SMP2P 778 IRQ_TYPE_EDGE_RISING>; 779 mboxes = <&ipcc IPCC_CLIENT_NSP1 780 IPCC_MPROC_SIGNAL_SMP2P>; 781 782 qcom,local-pid = <0>; 783 qcom,remote-pid = <12>; 784 785 smp2p_nsp1_out: master-kernel { 786 qcom,entry-name = "master-kernel"; 787 #qcom,smem-state-cells = <1>; 788 }; 789 790 smp2p_nsp1_in: slave-kernel { 791 qcom,entry-name = "slave-kernel"; 792 interrupt-controller; 793 #interrupt-cells = <2>; 794 }; 795 }; 796 797 smp2p-slpi { 798 compatible = "qcom,smp2p"; 799 qcom,smem = <481>, <430>; 800 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI 801 IPCC_MPROC_SIGNAL_SMP2P 802 IRQ_TYPE_EDGE_RISING>; 803 mboxes = <&ipcc IPCC_CLIENT_SLPI 804 IPCC_MPROC_SIGNAL_SMP2P>; 805 806 qcom,local-pid = <0>; 807 qcom,remote-pid = <3>; 808 809 smp2p_slpi_out: master-kernel { 810 qcom,entry-name = "master-kernel"; 811 #qcom,smem-state-cells = <1>; 812 }; 813 814 smp2p_slpi_in: slave-kernel { 815 qcom,entry-name = "slave-kernel"; 816 interrupt-controller; 817 #interrupt-cells = <2>; 818 }; 819 }; 820 821 soc: soc@0 { 822 compatible = "simple-bus"; 823 #address-cells = <2>; 824 #size-cells = <2>; 825 ranges = <0 0 0 0 0x10 0>; 826 dma-ranges = <0 0 0 0 0x10 0>; 827 828 ethernet0: ethernet@20000 { 829 compatible = "qcom,sc8280xp-ethqos"; 830 reg = <0x0 0x00020000 0x0 0x10000>, 831 <0x0 0x00036000 0x0 0x100>; 832 reg-names = "stmmaceth", "rgmii"; 833 834 clocks = <&gcc GCC_EMAC0_AXI_CLK>, 835 <&gcc GCC_EMAC0_SLV_AHB_CLK>, 836 <&gcc GCC_EMAC0_PTP_CLK>, 837 <&gcc GCC_EMAC0_RGMII_CLK>; 838 clock-names = "stmmaceth", 839 "pclk", 840 "ptp_ref", 841 "rgmii"; 842 843 interrupts = <GIC_SPI 946 IRQ_TYPE_LEVEL_HIGH>, 844 <GIC_SPI 936 IRQ_TYPE_LEVEL_HIGH>; 845 interrupt-names = "macirq", "eth_lpi"; 846 847 iommus = <&apps_smmu 0x4c0 0xf>; 848 power-domains = <&gcc EMAC_0_GDSC>; 849 850 snps,tso; 851 snps,pbl = <32>; 852 rx-fifo-depth = <4096>; 853 tx-fifo-depth = <4096>; 854 855 status = "disabled"; 856 }; 857 858 gcc: clock-controller@100000 { 859 compatible = "qcom,gcc-sc8280xp"; 860 reg = <0x0 0x00100000 0x0 0x1f0000>; 861 #clock-cells = <1>; 862 #reset-cells = <1>; 863 #power-domain-cells = <1>; 864 clocks = <&rpmhcc RPMH_CXO_CLK>, 865 <&sleep_clk>, 866 <0>, 867 <0>, 868 <0>, 869 <0>, 870 <0>, 871 <0>, 872 <&usb_0_qmpphy QMP_USB43DP_USB3_PIPE_CLK>, 873 <0>, 874 <0>, 875 <0>, 876 <0>, 877 <0>, 878 <0>, 879 <0>, 880 <&usb_1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>, 881 <0>, 882 <0>, 883 <0>, 884 <0>, 885 <0>, 886 <0>, 887 <0>, 888 <0>, 889 <0>, 890 <&pcie2a_phy>, 891 <&pcie2b_phy>, 892 <&pcie3a_phy>, 893 <&pcie3b_phy>, 894 <&pcie4_phy>, 895 <0>, 896 <0>; 897 power-domains = <&rpmhpd SC8280XP_CX>; 898 }; 899 900 ipcc: mailbox@408000 { 901 compatible = "qcom,sc8280xp-ipcc", "qcom,ipcc"; 902 reg = <0 0x00408000 0 0x1000>; 903 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 904 interrupt-controller; 905 #interrupt-cells = <3>; 906 #mbox-cells = <2>; 907 }; 908 909 qfprom: efuse@784000 { 910 compatible = "qcom,sc8280xp-qfprom", "qcom,qfprom"; 911 reg = <0 0x00784000 0 0x3000>; 912 #address-cells = <1>; 913 #size-cells = <1>; 914 915 gpu_speed_bin: gpu-speed-bin@18b { 916 reg = <0x18b 0x1>; 917 bits = <5 3>; 918 }; 919 }; 920 921 gpi_dma2: dma-controller@800000 { 922 compatible = "qcom,sc8280xp-gpi-dma", "qcom,sm6350-gpi-dma"; 923 reg = <0 0x00800000 0 0x60000>; 924 925 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 926 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>, 927 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, 928 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 929 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>, 930 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>, 931 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 932 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>, 933 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>, 934 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>, 935 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>, 936 <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>; 937 938 dma-channels = <12>; 939 dma-channel-mask = <0xfff>; 940 #dma-cells = <3>; 941 942 iommus = <&apps_smmu 0xb6 0x0>; 943 944 status = "disabled"; 945 }; 946 947 qup2: geniqup@8c0000 { 948 compatible = "qcom,geni-se-qup"; 949 reg = <0 0x008c0000 0 0x2000>; 950 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 951 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 952 clock-names = "m-ahb", "s-ahb"; 953 iommus = <&apps_smmu 0xa3 0>; 954 955 #address-cells = <2>; 956 #size-cells = <2>; 957 ranges; 958 959 status = "disabled"; 960 961 i2c16: i2c@880000 { 962 compatible = "qcom,geni-i2c"; 963 reg = <0 0x00880000 0 0x4000>; 964 #address-cells = <1>; 965 #size-cells = <0>; 966 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 967 clock-names = "se"; 968 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 969 power-domains = <&rpmhpd SC8280XP_CX>; 970 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 971 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 972 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 973 interconnect-names = "qup-core", "qup-config", "qup-memory"; 974 975 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, 976 <&gpi_dma2 1 0 QCOM_GPI_I2C>; 977 dma-names = "tx", 978 "rx"; 979 980 status = "disabled"; 981 }; 982 983 spi16: spi@880000 { 984 compatible = "qcom,geni-spi"; 985 reg = <0 0x00880000 0 0x4000>; 986 #address-cells = <1>; 987 #size-cells = <0>; 988 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 989 clock-names = "se"; 990 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 991 power-domains = <&rpmhpd SC8280XP_CX>; 992 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 993 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 994 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 995 interconnect-names = "qup-core", "qup-config", "qup-memory"; 996 997 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, 998 <&gpi_dma2 1 0 QCOM_GPI_SPI>; 999 dma-names = "tx", 1000 "rx"; 1001 1002 status = "disabled"; 1003 }; 1004 1005 i2c17: i2c@884000 { 1006 compatible = "qcom,geni-i2c"; 1007 reg = <0 0x00884000 0 0x4000>; 1008 #address-cells = <1>; 1009 #size-cells = <0>; 1010 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 1011 clock-names = "se"; 1012 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 1013 power-domains = <&rpmhpd SC8280XP_CX>; 1014 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1015 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1016 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1017 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1018 1019 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, 1020 <&gpi_dma2 1 1 QCOM_GPI_I2C>; 1021 dma-names = "tx", 1022 "rx"; 1023 1024 status = "disabled"; 1025 }; 1026 1027 spi17: spi@884000 { 1028 compatible = "qcom,geni-spi"; 1029 reg = <0 0x00884000 0 0x4000>; 1030 #address-cells = <1>; 1031 #size-cells = <0>; 1032 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 1033 clock-names = "se"; 1034 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 1035 power-domains = <&rpmhpd SC8280XP_CX>; 1036 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1037 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1038 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1039 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1040 1041 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, 1042 <&gpi_dma2 1 1 QCOM_GPI_SPI>; 1043 dma-names = "tx", 1044 "rx"; 1045 1046 status = "disabled"; 1047 }; 1048 1049 uart17: serial@884000 { 1050 compatible = "qcom,geni-uart"; 1051 reg = <0 0x00884000 0 0x4000>; 1052 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 1053 clock-names = "se"; 1054 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 1055 operating-points-v2 = <&qup_opp_table_100mhz>; 1056 power-domains = <&rpmhpd SC8280XP_CX>; 1057 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1058 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>; 1059 interconnect-names = "qup-core", "qup-config"; 1060 status = "disabled"; 1061 }; 1062 1063 i2c18: i2c@888000 { 1064 compatible = "qcom,geni-i2c"; 1065 reg = <0 0x00888000 0 0x4000>; 1066 #address-cells = <1>; 1067 #size-cells = <0>; 1068 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1069 clock-names = "se"; 1070 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 1071 power-domains = <&rpmhpd SC8280XP_CX>; 1072 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1073 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1074 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1075 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1076 1077 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, 1078 <&gpi_dma2 1 2 QCOM_GPI_I2C>; 1079 dma-names = "tx", 1080 "rx"; 1081 1082 status = "disabled"; 1083 }; 1084 1085 spi18: spi@888000 { 1086 compatible = "qcom,geni-spi"; 1087 reg = <0 0x00888000 0 0x4000>; 1088 #address-cells = <1>; 1089 #size-cells = <0>; 1090 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1091 clock-names = "se"; 1092 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 1093 power-domains = <&rpmhpd SC8280XP_CX>; 1094 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1095 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1096 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1097 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1098 1099 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, 1100 <&gpi_dma2 1 2 QCOM_GPI_SPI>; 1101 dma-names = "tx", 1102 "rx"; 1103 1104 status = "disabled"; 1105 }; 1106 1107 uart18: serial@888000 { 1108 compatible = "qcom,geni-uart"; 1109 reg = <0 0x00888000 0 0x4000>; 1110 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1111 clock-names = "se"; 1112 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 1113 operating-points-v2 = <&qup_opp_table_100mhz>; 1114 power-domains = <&rpmhpd SC8280XP_CX>; 1115 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1116 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>; 1117 interconnect-names = "qup-core", "qup-config"; 1118 1119 pinctrl-0 = <&qup_uart18_default>; 1120 pinctrl-names = "default"; 1121 1122 status = "disabled"; 1123 }; 1124 1125 i2c19: i2c@88c000 { 1126 compatible = "qcom,geni-i2c"; 1127 reg = <0 0x0088c000 0 0x4000>; 1128 #address-cells = <1>; 1129 #size-cells = <0>; 1130 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1131 clock-names = "se"; 1132 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1133 power-domains = <&rpmhpd SC8280XP_CX>; 1134 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1135 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1136 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1137 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1138 1139 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 1140 <&gpi_dma2 1 3 QCOM_GPI_I2C>; 1141 dma-names = "tx", 1142 "rx"; 1143 1144 status = "disabled"; 1145 }; 1146 1147 spi19: spi@88c000 { 1148 compatible = "qcom,geni-spi"; 1149 reg = <0 0x0088c000 0 0x4000>; 1150 #address-cells = <1>; 1151 #size-cells = <0>; 1152 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1153 clock-names = "se"; 1154 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1155 power-domains = <&rpmhpd SC8280XP_CX>; 1156 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1157 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1158 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1159 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1160 1161 dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>, 1162 <&gpi_dma2 1 3 QCOM_GPI_SPI>; 1163 dma-names = "tx", 1164 "rx"; 1165 1166 status = "disabled"; 1167 }; 1168 1169 i2c20: i2c@890000 { 1170 compatible = "qcom,geni-i2c"; 1171 reg = <0 0x00890000 0 0x4000>; 1172 #address-cells = <1>; 1173 #size-cells = <0>; 1174 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1175 clock-names = "se"; 1176 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1177 power-domains = <&rpmhpd SC8280XP_CX>; 1178 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1179 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1180 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1181 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1182 1183 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, 1184 <&gpi_dma2 1 4 QCOM_GPI_I2C>; 1185 dma-names = "tx", 1186 "rx"; 1187 1188 status = "disabled"; 1189 }; 1190 1191 spi20: spi@890000 { 1192 compatible = "qcom,geni-spi"; 1193 reg = <0 0x00890000 0 0x4000>; 1194 #address-cells = <1>; 1195 #size-cells = <0>; 1196 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1197 clock-names = "se"; 1198 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1199 power-domains = <&rpmhpd SC8280XP_CX>; 1200 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1201 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1202 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1203 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1204 1205 dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>, 1206 <&gpi_dma2 1 4 QCOM_GPI_SPI>; 1207 dma-names = "tx", 1208 "rx"; 1209 1210 status = "disabled"; 1211 }; 1212 1213 i2c21: i2c@894000 { 1214 compatible = "qcom,geni-i2c"; 1215 reg = <0 0x00894000 0 0x4000>; 1216 clock-names = "se"; 1217 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1218 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1219 #address-cells = <1>; 1220 #size-cells = <0>; 1221 power-domains = <&rpmhpd SC8280XP_CX>; 1222 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1223 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1224 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1225 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1226 1227 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, 1228 <&gpi_dma2 1 5 QCOM_GPI_I2C>; 1229 dma-names = "tx", 1230 "rx"; 1231 1232 status = "disabled"; 1233 }; 1234 1235 spi21: spi@894000 { 1236 compatible = "qcom,geni-spi"; 1237 reg = <0 0x00894000 0 0x4000>; 1238 #address-cells = <1>; 1239 #size-cells = <0>; 1240 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1241 clock-names = "se"; 1242 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1243 power-domains = <&rpmhpd SC8280XP_CX>; 1244 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1245 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1246 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1247 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1248 1249 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, 1250 <&gpi_dma2 1 5 QCOM_GPI_SPI>; 1251 dma-names = "tx", 1252 "rx"; 1253 1254 status = "disabled"; 1255 }; 1256 1257 i2c22: i2c@898000 { 1258 compatible = "qcom,geni-i2c"; 1259 reg = <0 0x00898000 0 0x4000>; 1260 #address-cells = <1>; 1261 #size-cells = <0>; 1262 clock-names = "se"; 1263 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1264 interrupts = <GIC_SPI 833 IRQ_TYPE_LEVEL_HIGH>; 1265 power-domains = <&rpmhpd SC8280XP_CX>; 1266 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1267 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1268 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1269 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1270 1271 dmas = <&gpi_dma2 0 6 QCOM_GPI_I2C>, 1272 <&gpi_dma2 1 6 QCOM_GPI_I2C>; 1273 dma-names = "tx", 1274 "rx"; 1275 1276 status = "disabled"; 1277 }; 1278 1279 spi22: spi@898000 { 1280 compatible = "qcom,geni-spi"; 1281 reg = <0 0x00898000 0 0x4000>; 1282 #address-cells = <1>; 1283 #size-cells = <0>; 1284 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1285 clock-names = "se"; 1286 interrupts = <GIC_SPI 833 IRQ_TYPE_LEVEL_HIGH>; 1287 power-domains = <&rpmhpd SC8280XP_CX>; 1288 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1289 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1290 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1291 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1292 1293 dmas = <&gpi_dma2 0 6 QCOM_GPI_SPI>, 1294 <&gpi_dma2 1 6 QCOM_GPI_SPI>; 1295 dma-names = "tx", 1296 "rx"; 1297 1298 status = "disabled"; 1299 }; 1300 1301 i2c23: i2c@89c000 { 1302 compatible = "qcom,geni-i2c"; 1303 reg = <0 0x0089c000 0 0x4000>; 1304 #address-cells = <1>; 1305 #size-cells = <0>; 1306 clock-names = "se"; 1307 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; 1308 interrupts = <GIC_SPI 834 IRQ_TYPE_LEVEL_HIGH>; 1309 power-domains = <&rpmhpd SC8280XP_CX>; 1310 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1311 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1312 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1313 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1314 1315 dmas = <&gpi_dma2 0 7 QCOM_GPI_I2C>, 1316 <&gpi_dma2 1 7 QCOM_GPI_I2C>; 1317 dma-names = "tx", 1318 "rx"; 1319 1320 status = "disabled"; 1321 }; 1322 1323 spi23: spi@89c000 { 1324 compatible = "qcom,geni-spi"; 1325 reg = <0 0x0089c000 0 0x4000>; 1326 #address-cells = <1>; 1327 #size-cells = <0>; 1328 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; 1329 clock-names = "se"; 1330 interrupts = <GIC_SPI 834 IRQ_TYPE_LEVEL_HIGH>; 1331 power-domains = <&rpmhpd SC8280XP_CX>; 1332 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1333 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1334 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1335 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1336 1337 dmas = <&gpi_dma2 0 7 QCOM_GPI_SPI>, 1338 <&gpi_dma2 1 7 QCOM_GPI_SPI>; 1339 dma-names = "tx", 1340 "rx"; 1341 1342 status = "disabled"; 1343 }; 1344 }; 1345 1346 gpi_dma0: dma-controller@900000 { 1347 compatible = "qcom,sc8280xp-gpi-dma", "qcom,sm6350-gpi-dma"; 1348 reg = <0 0x00900000 0 0x60000>; 1349 1350 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 1351 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 1352 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 1353 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 1354 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 1355 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 1356 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 1357 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 1358 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 1359 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 1360 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 1361 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, 1362 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>; 1363 1364 dma-channels = <13>; 1365 dma-channel-mask = <0x1fff>; 1366 #dma-cells = <3>; 1367 1368 iommus = <&apps_smmu 0x576 0x0>; 1369 1370 status = "disabled"; 1371 }; 1372 1373 qup0: geniqup@9c0000 { 1374 compatible = "qcom,geni-se-qup"; 1375 reg = <0 0x009c0000 0 0x6000>; 1376 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 1377 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 1378 clock-names = "m-ahb", "s-ahb"; 1379 iommus = <&apps_smmu 0x563 0>; 1380 1381 #address-cells = <2>; 1382 #size-cells = <2>; 1383 ranges; 1384 1385 status = "disabled"; 1386 1387 i2c0: i2c@980000 { 1388 compatible = "qcom,geni-i2c"; 1389 reg = <0 0x00980000 0 0x4000>; 1390 #address-cells = <1>; 1391 #size-cells = <0>; 1392 clock-names = "se"; 1393 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1394 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1395 power-domains = <&rpmhpd SC8280XP_CX>; 1396 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1397 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1398 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1399 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1400 1401 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 1402 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 1403 dma-names = "tx", 1404 "rx"; 1405 1406 status = "disabled"; 1407 }; 1408 1409 spi0: spi@980000 { 1410 compatible = "qcom,geni-spi"; 1411 reg = <0 0x00980000 0 0x4000>; 1412 #address-cells = <1>; 1413 #size-cells = <0>; 1414 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1415 clock-names = "se"; 1416 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1417 power-domains = <&rpmhpd SC8280XP_CX>; 1418 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1419 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1420 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1421 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1422 1423 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 1424 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 1425 dma-names = "tx", 1426 "rx"; 1427 1428 status = "disabled"; 1429 }; 1430 1431 i2c1: i2c@984000 { 1432 compatible = "qcom,geni-i2c"; 1433 reg = <0 0x00984000 0 0x4000>; 1434 #address-cells = <1>; 1435 #size-cells = <0>; 1436 clock-names = "se"; 1437 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1438 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1439 power-domains = <&rpmhpd SC8280XP_CX>; 1440 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1441 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1442 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1443 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1444 1445 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 1446 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 1447 dma-names = "tx", 1448 "rx"; 1449 1450 status = "disabled"; 1451 }; 1452 1453 spi1: spi@984000 { 1454 compatible = "qcom,geni-spi"; 1455 reg = <0 0x00984000 0 0x4000>; 1456 #address-cells = <1>; 1457 #size-cells = <0>; 1458 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1459 clock-names = "se"; 1460 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1461 power-domains = <&rpmhpd SC8280XP_CX>; 1462 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1463 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1464 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1465 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1466 1467 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 1468 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 1469 dma-names = "tx", 1470 "rx"; 1471 1472 status = "disabled"; 1473 }; 1474 1475 i2c2: i2c@988000 { 1476 compatible = "qcom,geni-i2c"; 1477 reg = <0 0x00988000 0 0x4000>; 1478 #address-cells = <1>; 1479 #size-cells = <0>; 1480 clock-names = "se"; 1481 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1482 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1483 power-domains = <&rpmhpd SC8280XP_CX>; 1484 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1485 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1486 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1487 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1488 1489 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 1490 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 1491 dma-names = "tx", 1492 "rx"; 1493 1494 status = "disabled"; 1495 }; 1496 1497 spi2: spi@988000 { 1498 compatible = "qcom,geni-spi"; 1499 reg = <0 0x00988000 0 0x4000>; 1500 #address-cells = <1>; 1501 #size-cells = <0>; 1502 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1503 clock-names = "se"; 1504 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1505 power-domains = <&rpmhpd SC8280XP_CX>; 1506 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1507 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1508 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1509 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1510 1511 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 1512 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 1513 dma-names = "tx", 1514 "rx"; 1515 1516 status = "disabled"; 1517 }; 1518 1519 uart2: serial@988000 { 1520 compatible = "qcom,geni-uart"; 1521 reg = <0 0x00988000 0 0x4000>; 1522 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1523 clock-names = "se"; 1524 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1525 operating-points-v2 = <&qup_opp_table_100mhz>; 1526 power-domains = <&rpmhpd SC8280XP_CX>; 1527 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1528 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 1529 interconnect-names = "qup-core", "qup-config"; 1530 status = "disabled"; 1531 }; 1532 1533 i2c3: i2c@98c000 { 1534 compatible = "qcom,geni-i2c"; 1535 reg = <0 0x0098c000 0 0x4000>; 1536 #address-cells = <1>; 1537 #size-cells = <0>; 1538 clock-names = "se"; 1539 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1540 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1541 power-domains = <&rpmhpd SC8280XP_CX>; 1542 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1543 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1544 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1545 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1546 1547 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 1548 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 1549 dma-names = "tx", 1550 "rx"; 1551 1552 status = "disabled"; 1553 }; 1554 1555 spi3: spi@98c000 { 1556 compatible = "qcom,geni-spi"; 1557 reg = <0 0x0098c000 0 0x4000>; 1558 #address-cells = <1>; 1559 #size-cells = <0>; 1560 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1561 clock-names = "se"; 1562 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1563 power-domains = <&rpmhpd SC8280XP_CX>; 1564 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1565 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1566 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1567 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1568 1569 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 1570 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 1571 dma-names = "tx", 1572 "rx"; 1573 1574 status = "disabled"; 1575 }; 1576 1577 i2c4: i2c@990000 { 1578 compatible = "qcom,geni-i2c"; 1579 reg = <0 0x00990000 0 0x4000>; 1580 clock-names = "se"; 1581 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1582 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1583 #address-cells = <1>; 1584 #size-cells = <0>; 1585 power-domains = <&rpmhpd SC8280XP_CX>; 1586 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1587 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1588 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1589 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1590 1591 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 1592 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 1593 dma-names = "tx", 1594 "rx"; 1595 1596 status = "disabled"; 1597 }; 1598 1599 spi4: spi@990000 { 1600 compatible = "qcom,geni-spi"; 1601 reg = <0 0x00990000 0 0x4000>; 1602 #address-cells = <1>; 1603 #size-cells = <0>; 1604 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1605 clock-names = "se"; 1606 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1607 power-domains = <&rpmhpd SC8280XP_CX>; 1608 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1609 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1610 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1611 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1612 1613 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 1614 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 1615 dma-names = "tx", 1616 "rx"; 1617 1618 status = "disabled"; 1619 }; 1620 1621 i2c5: i2c@994000 { 1622 compatible = "qcom,geni-i2c"; 1623 reg = <0 0x00994000 0 0x4000>; 1624 #address-cells = <1>; 1625 #size-cells = <0>; 1626 clock-names = "se"; 1627 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1628 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1629 power-domains = <&rpmhpd SC8280XP_CX>; 1630 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1631 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1632 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1633 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1634 1635 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 1636 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 1637 dma-names = "tx", 1638 "rx"; 1639 1640 status = "disabled"; 1641 }; 1642 1643 spi5: spi@994000 { 1644 compatible = "qcom,geni-spi"; 1645 reg = <0 0x00994000 0 0x4000>; 1646 #address-cells = <1>; 1647 #size-cells = <0>; 1648 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1649 clock-names = "se"; 1650 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1651 power-domains = <&rpmhpd SC8280XP_CX>; 1652 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1653 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1654 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1655 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1656 1657 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 1658 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 1659 dma-names = "tx", 1660 "rx"; 1661 1662 status = "disabled"; 1663 }; 1664 1665 i2c6: i2c@998000 { 1666 compatible = "qcom,geni-i2c"; 1667 reg = <0 0x00998000 0 0x4000>; 1668 #address-cells = <1>; 1669 #size-cells = <0>; 1670 clock-names = "se"; 1671 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1672 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1673 power-domains = <&rpmhpd SC8280XP_CX>; 1674 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1675 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1676 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1677 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1678 1679 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, 1680 <&gpi_dma0 1 6 QCOM_GPI_I2C>; 1681 dma-names = "tx", 1682 "rx"; 1683 1684 status = "disabled"; 1685 }; 1686 1687 spi6: spi@998000 { 1688 compatible = "qcom,geni-spi"; 1689 reg = <0 0x00998000 0 0x4000>; 1690 #address-cells = <1>; 1691 #size-cells = <0>; 1692 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1693 clock-names = "se"; 1694 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1695 power-domains = <&rpmhpd SC8280XP_CX>; 1696 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1697 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1698 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1699 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1700 1701 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, 1702 <&gpi_dma0 1 6 QCOM_GPI_SPI>; 1703 dma-names = "tx", 1704 "rx"; 1705 1706 status = "disabled"; 1707 }; 1708 1709 i2c7: i2c@99c000 { 1710 compatible = "qcom,geni-i2c"; 1711 reg = <0 0x0099c000 0 0x4000>; 1712 #address-cells = <1>; 1713 #size-cells = <0>; 1714 clock-names = "se"; 1715 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1716 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1717 power-domains = <&rpmhpd SC8280XP_CX>; 1718 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1719 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1720 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1721 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1722 1723 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>, 1724 <&gpi_dma0 1 7 QCOM_GPI_I2C>; 1725 dma-names = "tx", 1726 "rx"; 1727 1728 status = "disabled"; 1729 }; 1730 1731 spi7: spi@99c000 { 1732 compatible = "qcom,geni-spi"; 1733 reg = <0 0x0099c000 0 0x4000>; 1734 #address-cells = <1>; 1735 #size-cells = <0>; 1736 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1737 clock-names = "se"; 1738 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1739 power-domains = <&rpmhpd SC8280XP_CX>; 1740 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1741 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1742 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1743 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1744 1745 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>, 1746 <&gpi_dma0 1 7 QCOM_GPI_SPI>; 1747 dma-names = "tx", 1748 "rx"; 1749 1750 status = "disabled"; 1751 }; 1752 }; 1753 1754 gpi_dma1: dma-controller@a00000 { 1755 compatible = "qcom,sc8280xp-gpi-dma", "qcom,sm6350-gpi-dma"; 1756 reg = <0 0x00a00000 0 0x60000>; 1757 1758 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 1759 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 1760 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 1761 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1762 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1763 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 1764 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 1765 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 1766 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 1767 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 1768 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 1769 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; 1770 1771 dma-channels = <12>; 1772 dma-channel-mask = <0xfff>; 1773 #dma-cells = <3>; 1774 1775 iommus = <&apps_smmu 0x96 0x0>; 1776 1777 status = "disabled"; 1778 }; 1779 1780 qup1: geniqup@ac0000 { 1781 compatible = "qcom,geni-se-qup"; 1782 reg = <0 0x00ac0000 0 0x6000>; 1783 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1784 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1785 clock-names = "m-ahb", "s-ahb"; 1786 iommus = <&apps_smmu 0x83 0>; 1787 1788 #address-cells = <2>; 1789 #size-cells = <2>; 1790 ranges; 1791 1792 status = "disabled"; 1793 1794 i2c8: i2c@a80000 { 1795 compatible = "qcom,geni-i2c"; 1796 reg = <0 0x00a80000 0 0x4000>; 1797 #address-cells = <1>; 1798 #size-cells = <0>; 1799 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1800 clock-names = "se"; 1801 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1802 power-domains = <&rpmhpd SC8280XP_CX>; 1803 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1804 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1805 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1806 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1807 1808 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1809 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1810 dma-names = "tx", 1811 "rx"; 1812 1813 status = "disabled"; 1814 }; 1815 1816 spi8: spi@a80000 { 1817 compatible = "qcom,geni-spi"; 1818 reg = <0 0x00a80000 0 0x4000>; 1819 #address-cells = <1>; 1820 #size-cells = <0>; 1821 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1822 clock-names = "se"; 1823 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1824 power-domains = <&rpmhpd SC8280XP_CX>; 1825 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1826 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1827 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1828 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1829 1830 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1831 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1832 dma-names = "tx", 1833 "rx"; 1834 1835 status = "disabled"; 1836 }; 1837 1838 i2c9: i2c@a84000 { 1839 compatible = "qcom,geni-i2c"; 1840 reg = <0 0x00a84000 0 0x4000>; 1841 #address-cells = <1>; 1842 #size-cells = <0>; 1843 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1844 clock-names = "se"; 1845 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1846 power-domains = <&rpmhpd SC8280XP_CX>; 1847 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1848 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1849 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1850 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1851 1852 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1853 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1854 dma-names = "tx", 1855 "rx"; 1856 1857 status = "disabled"; 1858 }; 1859 1860 spi9: spi@a84000 { 1861 compatible = "qcom,geni-spi"; 1862 reg = <0 0x00a84000 0 0x4000>; 1863 #address-cells = <1>; 1864 #size-cells = <0>; 1865 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1866 clock-names = "se"; 1867 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1868 power-domains = <&rpmhpd SC8280XP_CX>; 1869 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1870 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1871 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1872 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1873 1874 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1875 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1876 dma-names = "tx", 1877 "rx"; 1878 1879 status = "disabled"; 1880 }; 1881 1882 i2c10: i2c@a88000 { 1883 compatible = "qcom,geni-i2c"; 1884 reg = <0 0x00a88000 0 0x4000>; 1885 #address-cells = <1>; 1886 #size-cells = <0>; 1887 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1888 clock-names = "se"; 1889 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1890 power-domains = <&rpmhpd SC8280XP_CX>; 1891 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1892 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1893 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1894 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1895 1896 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1897 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1898 dma-names = "tx", 1899 "rx"; 1900 1901 status = "disabled"; 1902 }; 1903 1904 spi10: spi@a88000 { 1905 compatible = "qcom,geni-spi"; 1906 reg = <0 0x00a88000 0 0x4000>; 1907 #address-cells = <1>; 1908 #size-cells = <0>; 1909 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1910 clock-names = "se"; 1911 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1912 power-domains = <&rpmhpd SC8280XP_CX>; 1913 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1914 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1915 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1916 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1917 1918 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1919 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1920 dma-names = "tx", 1921 "rx"; 1922 1923 status = "disabled"; 1924 }; 1925 1926 i2c11: i2c@a8c000 { 1927 compatible = "qcom,geni-i2c"; 1928 reg = <0 0x00a8c000 0 0x4000>; 1929 #address-cells = <1>; 1930 #size-cells = <0>; 1931 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1932 clock-names = "se"; 1933 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1934 power-domains = <&rpmhpd SC8280XP_CX>; 1935 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1936 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1937 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1938 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1939 1940 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1941 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1942 dma-names = "tx", 1943 "rx"; 1944 1945 status = "disabled"; 1946 }; 1947 1948 spi11: spi@a8c000 { 1949 compatible = "qcom,geni-spi"; 1950 reg = <0 0x00a8c000 0 0x4000>; 1951 #address-cells = <1>; 1952 #size-cells = <0>; 1953 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1954 clock-names = "se"; 1955 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1956 power-domains = <&rpmhpd SC8280XP_CX>; 1957 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1958 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1959 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1960 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1961 1962 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1963 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1964 dma-names = "tx", 1965 "rx"; 1966 1967 status = "disabled"; 1968 }; 1969 1970 i2c12: i2c@a90000 { 1971 compatible = "qcom,geni-i2c"; 1972 reg = <0 0x00a90000 0 0x4000>; 1973 #address-cells = <1>; 1974 #size-cells = <0>; 1975 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1976 clock-names = "se"; 1977 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1978 power-domains = <&rpmhpd SC8280XP_CX>; 1979 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1980 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1981 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1982 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1983 1984 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1985 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1986 dma-names = "tx", 1987 "rx"; 1988 1989 status = "disabled"; 1990 }; 1991 1992 spi12: spi@a90000 { 1993 compatible = "qcom,geni-spi"; 1994 reg = <0 0x00a90000 0 0x4000>; 1995 #address-cells = <1>; 1996 #size-cells = <0>; 1997 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1998 clock-names = "se"; 1999 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 2000 power-domains = <&rpmhpd SC8280XP_CX>; 2001 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 2002 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 2003 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 2004 interconnect-names = "qup-core", "qup-config", "qup-memory"; 2005 2006 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 2007 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 2008 dma-names = "tx", 2009 "rx"; 2010 2011 status = "disabled"; 2012 }; 2013 2014 i2c13: i2c@a94000 { 2015 compatible = "qcom,geni-i2c"; 2016 reg = <0 0x00a94000 0 0x4000>; 2017 #address-cells = <1>; 2018 #size-cells = <0>; 2019 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 2020 clock-names = "se"; 2021 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 2022 power-domains = <&rpmhpd SC8280XP_CX>; 2023 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 2024 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 2025 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 2026 interconnect-names = "qup-core", "qup-config", "qup-memory"; 2027 2028 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 2029 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 2030 dma-names = "tx", 2031 "rx"; 2032 2033 status = "disabled"; 2034 }; 2035 2036 spi13: spi@a94000 { 2037 compatible = "qcom,geni-spi"; 2038 reg = <0 0x00a94000 0 0x4000>; 2039 #address-cells = <1>; 2040 #size-cells = <0>; 2041 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 2042 clock-names = "se"; 2043 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 2044 power-domains = <&rpmhpd SC8280XP_CX>; 2045 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 2046 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 2047 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 2048 interconnect-names = "qup-core", "qup-config", "qup-memory"; 2049 2050 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 2051 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 2052 dma-names = "tx", 2053 "rx"; 2054 2055 status = "disabled"; 2056 }; 2057 2058 i2c14: i2c@a98000 { 2059 compatible = "qcom,geni-i2c"; 2060 reg = <0 0x00a98000 0 0x4000>; 2061 #address-cells = <1>; 2062 #size-cells = <0>; 2063 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 2064 clock-names = "se"; 2065 interrupts = <GIC_SPI 835 IRQ_TYPE_LEVEL_HIGH>; 2066 power-domains = <&rpmhpd SC8280XP_CX>; 2067 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 2068 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 2069 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 2070 interconnect-names = "qup-core", "qup-config", "qup-memory"; 2071 2072 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, 2073 <&gpi_dma1 1 6 QCOM_GPI_I2C>; 2074 dma-names = "tx", 2075 "rx"; 2076 2077 status = "disabled"; 2078 }; 2079 2080 spi14: spi@a98000 { 2081 compatible = "qcom,geni-spi"; 2082 reg = <0 0x00a98000 0 0x4000>; 2083 #address-cells = <1>; 2084 #size-cells = <0>; 2085 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 2086 clock-names = "se"; 2087 interrupts = <GIC_SPI 835 IRQ_TYPE_LEVEL_HIGH>; 2088 power-domains = <&rpmhpd SC8280XP_CX>; 2089 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 2090 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 2091 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 2092 interconnect-names = "qup-core", "qup-config", "qup-memory"; 2093 2094 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>, 2095 <&gpi_dma1 1 6 QCOM_GPI_SPI>; 2096 dma-names = "tx", 2097 "rx"; 2098 2099 status = "disabled"; 2100 }; 2101 2102 i2c15: i2c@a9c000 { 2103 compatible = "qcom,geni-i2c"; 2104 reg = <0 0x00a9c000 0 0x4000>; 2105 #address-cells = <1>; 2106 #size-cells = <0>; 2107 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 2108 clock-names = "se"; 2109 interrupts = <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>; 2110 power-domains = <&rpmhpd SC8280XP_CX>; 2111 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 2112 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 2113 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 2114 interconnect-names = "qup-core", "qup-config", "qup-memory"; 2115 2116 dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>, 2117 <&gpi_dma1 1 7 QCOM_GPI_I2C>; 2118 dma-names = "tx", 2119 "rx"; 2120 2121 status = "disabled"; 2122 }; 2123 2124 spi15: spi@a9c000 { 2125 compatible = "qcom,geni-spi"; 2126 reg = <0 0x00a9c000 0 0x4000>; 2127 #address-cells = <1>; 2128 #size-cells = <0>; 2129 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 2130 clock-names = "se"; 2131 interrupts = <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>; 2132 power-domains = <&rpmhpd SC8280XP_CX>; 2133 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 2134 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 2135 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 2136 interconnect-names = "qup-core", "qup-config", "qup-memory"; 2137 2138 dmas = <&gpi_dma1 0 7 QCOM_GPI_SPI>, 2139 <&gpi_dma1 1 7 QCOM_GPI_SPI>; 2140 dma-names = "tx", 2141 "rx"; 2142 2143 status = "disabled"; 2144 }; 2145 }; 2146 2147 rng: rng@10d3000 { 2148 compatible = "qcom,prng-ee"; 2149 reg = <0 0x010d3000 0 0x1000>; 2150 clocks = <&rpmhcc RPMH_HWKM_CLK>; 2151 clock-names = "core"; 2152 }; 2153 2154 pcie4: pcie@1c00000 { 2155 device_type = "pci"; 2156 compatible = "qcom,pcie-sc8280xp"; 2157 reg = <0x0 0x01c00000 0x0 0x3000>, 2158 <0x0 0x30000000 0x0 0xf1d>, 2159 <0x0 0x30000f20 0x0 0xa8>, 2160 <0x0 0x30001000 0x0 0x1000>, 2161 <0x0 0x30100000 0x0 0x100000>, 2162 <0x0 0x01c03000 0x0 0x1000>; 2163 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; 2164 #address-cells = <3>; 2165 #size-cells = <2>; 2166 ranges = <0x01000000 0x0 0x00000000 0x0 0x30200000 0x0 0x100000>, 2167 <0x02000000 0x0 0x30300000 0x0 0x30300000 0x0 0x1d00000>; 2168 bus-range = <0x00 0xff>; 2169 2170 dma-coherent; 2171 2172 linux,pci-domain = <6>; 2173 num-lanes = <1>; 2174 2175 msi-map = <0x0 &its 0xe0000 0x10000>; 2176 2177 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 2178 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 2179 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 2180 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 2181 interrupt-names = "msi0", "msi1", "msi2", "msi3"; 2182 2183 #interrupt-cells = <1>; 2184 interrupt-map-mask = <0 0 0 0x7>; 2185 interrupt-map = <0 0 0 1 &intc 0 GIC_SPI GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 2186 <0 0 0 2 &intc 0 GIC_SPI GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 2187 <0 0 0 3 &intc 0 GIC_SPI GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, 2188 <0 0 0 4 &intc 0 GIC_SPI GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 2189 2190 clocks = <&gcc GCC_PCIE_4_AUX_CLK>, 2191 <&gcc GCC_PCIE_4_CFG_AHB_CLK>, 2192 <&gcc GCC_PCIE_4_MSTR_AXI_CLK>, 2193 <&gcc GCC_PCIE_4_SLV_AXI_CLK>, 2194 <&gcc GCC_PCIE_4_SLV_Q2A_AXI_CLK>, 2195 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, 2196 <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>, 2197 <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>, 2198 <&gcc GCC_CNOC_PCIE4_QX_CLK>; 2199 clock-names = "aux", 2200 "cfg", 2201 "bus_master", 2202 "bus_slave", 2203 "slave_q2a", 2204 "ddrss_sf_tbu", 2205 "noc_aggr_4", 2206 "noc_aggr_south_sf", 2207 "cnoc_qx"; 2208 2209 assigned-clocks = <&gcc GCC_PCIE_4_AUX_CLK>; 2210 assigned-clock-rates = <19200000>; 2211 2212 interconnects = <&aggre2_noc MASTER_PCIE_4 0 &mc_virt SLAVE_EBI1 0>, 2213 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_4 0>; 2214 interconnect-names = "pcie-mem", "cpu-pcie"; 2215 2216 resets = <&gcc GCC_PCIE_4_BCR>; 2217 reset-names = "pci"; 2218 2219 power-domains = <&gcc PCIE_4_GDSC>; 2220 required-opps = <&rpmhpd_opp_nom>; 2221 2222 phys = <&pcie4_phy>; 2223 phy-names = "pciephy"; 2224 2225 status = "disabled"; 2226 2227 pcie4_port0: pcie@0 { 2228 device_type = "pci"; 2229 reg = <0x0 0x0 0x0 0x0 0x0>; 2230 bus-range = <0x01 0xff>; 2231 2232 #address-cells = <3>; 2233 #size-cells = <2>; 2234 ranges; 2235 }; 2236 }; 2237 2238 pcie4_phy: phy@1c06000 { 2239 compatible = "qcom,sc8280xp-qmp-gen3x1-pcie-phy"; 2240 reg = <0x0 0x01c06000 0x0 0x2000>; 2241 2242 clocks = <&gcc GCC_PCIE_4_AUX_CLK>, 2243 <&gcc GCC_PCIE_4_CFG_AHB_CLK>, 2244 <&gcc GCC_PCIE_4_CLKREF_CLK>, 2245 <&gcc GCC_PCIE4_PHY_RCHNG_CLK>, 2246 <&gcc GCC_PCIE_4_PIPE_CLK>, 2247 <&gcc GCC_PCIE_4_PIPEDIV2_CLK>; 2248 clock-names = "aux", "cfg_ahb", "ref", "rchng", 2249 "pipe", "pipediv2"; 2250 2251 assigned-clocks = <&gcc GCC_PCIE4_PHY_RCHNG_CLK>; 2252 assigned-clock-rates = <100000000>; 2253 2254 power-domains = <&gcc PCIE_4_GDSC>; 2255 2256 resets = <&gcc GCC_PCIE_4_PHY_BCR>; 2257 reset-names = "phy"; 2258 2259 #clock-cells = <0>; 2260 clock-output-names = "pcie_4_pipe_clk"; 2261 2262 #phy-cells = <0>; 2263 2264 status = "disabled"; 2265 }; 2266 2267 pcie3b: pcie@1c08000 { 2268 device_type = "pci"; 2269 compatible = "qcom,pcie-sc8280xp"; 2270 reg = <0x0 0x01c08000 0x0 0x3000>, 2271 <0x0 0x32000000 0x0 0xf1d>, 2272 <0x0 0x32000f20 0x0 0xa8>, 2273 <0x0 0x32001000 0x0 0x1000>, 2274 <0x0 0x32100000 0x0 0x100000>, 2275 <0x0 0x01c0b000 0x0 0x1000>; 2276 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; 2277 #address-cells = <3>; 2278 #size-cells = <2>; 2279 ranges = <0x01000000 0x0 0x00000000 0x0 0x32200000 0x0 0x100000>, 2280 <0x02000000 0x0 0x32300000 0x0 0x32300000 0x0 0x1d00000>; 2281 bus-range = <0x00 0xff>; 2282 2283 dma-coherent; 2284 2285 linux,pci-domain = <5>; 2286 num-lanes = <2>; 2287 2288 msi-map = <0x0 &its 0xd0000 0x10000>; 2289 2290 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 2291 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 2292 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 2293 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 2294 interrupt-names = "msi0", "msi1", "msi2", "msi3"; 2295 2296 #interrupt-cells = <1>; 2297 interrupt-map-mask = <0 0 0 0x7>; 2298 interrupt-map = <0 0 0 1 &intc 0 GIC_SPI GIC_SPI 526 IRQ_TYPE_LEVEL_HIGH>, 2299 <0 0 0 2 &intc 0 GIC_SPI GIC_SPI 527 IRQ_TYPE_LEVEL_HIGH>, 2300 <0 0 0 3 &intc 0 GIC_SPI GIC_SPI 528 IRQ_TYPE_LEVEL_HIGH>, 2301 <0 0 0 4 &intc 0 GIC_SPI GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>; 2302 2303 clocks = <&gcc GCC_PCIE_3B_AUX_CLK>, 2304 <&gcc GCC_PCIE_3B_CFG_AHB_CLK>, 2305 <&gcc GCC_PCIE_3B_MSTR_AXI_CLK>, 2306 <&gcc GCC_PCIE_3B_SLV_AXI_CLK>, 2307 <&gcc GCC_PCIE_3B_SLV_Q2A_AXI_CLK>, 2308 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, 2309 <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>, 2310 <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>; 2311 clock-names = "aux", 2312 "cfg", 2313 "bus_master", 2314 "bus_slave", 2315 "slave_q2a", 2316 "ddrss_sf_tbu", 2317 "noc_aggr_4", 2318 "noc_aggr_south_sf"; 2319 2320 assigned-clocks = <&gcc GCC_PCIE_3B_AUX_CLK>; 2321 assigned-clock-rates = <19200000>; 2322 2323 interconnects = <&aggre2_noc MASTER_PCIE_3B 0 &mc_virt SLAVE_EBI1 0>, 2324 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_3B 0>; 2325 interconnect-names = "pcie-mem", "cpu-pcie"; 2326 2327 resets = <&gcc GCC_PCIE_3B_BCR>; 2328 reset-names = "pci"; 2329 2330 power-domains = <&gcc PCIE_3B_GDSC>; 2331 required-opps = <&rpmhpd_opp_nom>; 2332 2333 phys = <&pcie3b_phy>; 2334 phy-names = "pciephy"; 2335 2336 status = "disabled"; 2337 2338 pcie3b_port0: pcie@0 { 2339 device_type = "pci"; 2340 reg = <0x0 0x0 0x0 0x0 0x0>; 2341 bus-range = <0x01 0xff>; 2342 2343 #address-cells = <3>; 2344 #size-cells = <2>; 2345 ranges; 2346 }; 2347 }; 2348 2349 pcie3b_phy: phy@1c0e000 { 2350 compatible = "qcom,sc8280xp-qmp-gen3x2-pcie-phy"; 2351 reg = <0x0 0x01c0e000 0x0 0x2000>; 2352 2353 clocks = <&gcc GCC_PCIE_3B_AUX_CLK>, 2354 <&gcc GCC_PCIE_3B_CFG_AHB_CLK>, 2355 <&gcc GCC_PCIE_3A3B_CLKREF_CLK>, 2356 <&gcc GCC_PCIE3B_PHY_RCHNG_CLK>, 2357 <&gcc GCC_PCIE_3B_PIPE_CLK>, 2358 <&gcc GCC_PCIE_3B_PIPEDIV2_CLK>; 2359 clock-names = "aux", "cfg_ahb", "ref", "rchng", 2360 "pipe", "pipediv2"; 2361 2362 assigned-clocks = <&gcc GCC_PCIE3B_PHY_RCHNG_CLK>; 2363 assigned-clock-rates = <100000000>; 2364 2365 power-domains = <&gcc PCIE_3B_GDSC>; 2366 2367 resets = <&gcc GCC_PCIE_3B_PHY_BCR>; 2368 reset-names = "phy"; 2369 2370 #clock-cells = <0>; 2371 clock-output-names = "pcie_3b_pipe_clk"; 2372 2373 #phy-cells = <0>; 2374 2375 status = "disabled"; 2376 }; 2377 2378 pcie3a: pcie@1c10000 { 2379 device_type = "pci"; 2380 compatible = "qcom,pcie-sc8280xp"; 2381 reg = <0x0 0x01c10000 0x0 0x3000>, 2382 <0x0 0x34000000 0x0 0xf1d>, 2383 <0x0 0x34000f20 0x0 0xa8>, 2384 <0x0 0x34001000 0x0 0x1000>, 2385 <0x0 0x34100000 0x0 0x100000>, 2386 <0x0 0x01c13000 0x0 0x1000>; 2387 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; 2388 #address-cells = <3>; 2389 #size-cells = <2>; 2390 ranges = <0x01000000 0x0 0x00000000 0x0 0x34200000 0x0 0x100000>, 2391 <0x02000000 0x0 0x34300000 0x0 0x34300000 0x0 0x1d00000>; 2392 bus-range = <0x00 0xff>; 2393 2394 dma-coherent; 2395 2396 linux,pci-domain = <4>; 2397 num-lanes = <4>; 2398 2399 msi-map = <0x0 &its 0xc0000 0x10000>; 2400 2401 interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 2402 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 2403 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 2404 <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>; 2405 interrupt-names = "msi0", "msi1", "msi2", "msi3"; 2406 2407 #interrupt-cells = <1>; 2408 interrupt-map-mask = <0 0 0 0x7>; 2409 interrupt-map = <0 0 0 1 &intc 0 GIC_SPI GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH>, 2410 <0 0 0 2 &intc 0 GIC_SPI GIC_SPI 542 IRQ_TYPE_LEVEL_HIGH>, 2411 <0 0 0 3 &intc 0 GIC_SPI GIC_SPI 543 IRQ_TYPE_LEVEL_HIGH>, 2412 <0 0 0 4 &intc 0 GIC_SPI GIC_SPI 544 IRQ_TYPE_LEVEL_HIGH>; 2413 2414 clocks = <&gcc GCC_PCIE_3A_AUX_CLK>, 2415 <&gcc GCC_PCIE_3A_CFG_AHB_CLK>, 2416 <&gcc GCC_PCIE_3A_MSTR_AXI_CLK>, 2417 <&gcc GCC_PCIE_3A_SLV_AXI_CLK>, 2418 <&gcc GCC_PCIE_3A_SLV_Q2A_AXI_CLK>, 2419 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, 2420 <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>, 2421 <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>; 2422 clock-names = "aux", 2423 "cfg", 2424 "bus_master", 2425 "bus_slave", 2426 "slave_q2a", 2427 "ddrss_sf_tbu", 2428 "noc_aggr_4", 2429 "noc_aggr_south_sf"; 2430 2431 assigned-clocks = <&gcc GCC_PCIE_3A_AUX_CLK>; 2432 assigned-clock-rates = <19200000>; 2433 2434 interconnects = <&aggre2_noc MASTER_PCIE_3A 0 &mc_virt SLAVE_EBI1 0>, 2435 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_3A 0>; 2436 interconnect-names = "pcie-mem", "cpu-pcie"; 2437 2438 resets = <&gcc GCC_PCIE_3A_BCR>; 2439 reset-names = "pci"; 2440 2441 power-domains = <&gcc PCIE_3A_GDSC>; 2442 required-opps = <&rpmhpd_opp_nom>; 2443 2444 phys = <&pcie3a_phy>; 2445 phy-names = "pciephy"; 2446 2447 status = "disabled"; 2448 2449 pcie3a_port0: pcie@0 { 2450 device_type = "pci"; 2451 reg = <0x0 0x0 0x0 0x0 0x0>; 2452 bus-range = <0x01 0xff>; 2453 2454 #address-cells = <3>; 2455 #size-cells = <2>; 2456 ranges; 2457 }; 2458 }; 2459 2460 pcie3a_phy: phy@1c14000 { 2461 compatible = "qcom,sc8280xp-qmp-gen3x4-pcie-phy"; 2462 reg = <0x0 0x01c14000 0x0 0x2000>, 2463 <0x0 0x01c16000 0x0 0x2000>; 2464 2465 clocks = <&gcc GCC_PCIE_3A_AUX_CLK>, 2466 <&gcc GCC_PCIE_3A_CFG_AHB_CLK>, 2467 <&gcc GCC_PCIE_3A3B_CLKREF_CLK>, 2468 <&gcc GCC_PCIE3A_PHY_RCHNG_CLK>, 2469 <&gcc GCC_PCIE_3A_PIPE_CLK>, 2470 <&gcc GCC_PCIE_3A_PIPEDIV2_CLK>; 2471 clock-names = "aux", "cfg_ahb", "ref", "rchng", 2472 "pipe", "pipediv2"; 2473 2474 assigned-clocks = <&gcc GCC_PCIE3A_PHY_RCHNG_CLK>; 2475 assigned-clock-rates = <100000000>; 2476 2477 power-domains = <&gcc PCIE_3A_GDSC>; 2478 2479 resets = <&gcc GCC_PCIE_3A_PHY_BCR>; 2480 reset-names = "phy"; 2481 2482 qcom,4ln-config-sel = <&tcsr 0xa044 1>; 2483 2484 #clock-cells = <0>; 2485 clock-output-names = "pcie_3a_pipe_clk"; 2486 2487 #phy-cells = <0>; 2488 2489 status = "disabled"; 2490 }; 2491 2492 pcie2b: pcie@1c18000 { 2493 device_type = "pci"; 2494 compatible = "qcom,pcie-sc8280xp"; 2495 reg = <0x0 0x01c18000 0x0 0x3000>, 2496 <0x0 0x38000000 0x0 0xf1d>, 2497 <0x0 0x38000f20 0x0 0xa8>, 2498 <0x0 0x38001000 0x0 0x1000>, 2499 <0x0 0x38100000 0x0 0x100000>, 2500 <0x0 0x01c1b000 0x0 0x1000>; 2501 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; 2502 #address-cells = <3>; 2503 #size-cells = <2>; 2504 ranges = <0x01000000 0x0 0x00000000 0x0 0x38200000 0x0 0x100000>, 2505 <0x02000000 0x0 0x38300000 0x0 0x38300000 0x0 0x1d00000>; 2506 bus-range = <0x00 0xff>; 2507 2508 dma-coherent; 2509 2510 linux,pci-domain = <3>; 2511 num-lanes = <2>; 2512 2513 msi-map = <0x0 &its 0xb0000 0x10000>; 2514 2515 interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>, 2516 <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 2517 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 2518 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>; 2519 interrupt-names = "msi0", "msi1", "msi2", "msi3"; 2520 2521 #interrupt-cells = <1>; 2522 interrupt-map-mask = <0 0 0 0x7>; 2523 interrupt-map = <0 0 0 1 &intc 0 GIC_SPI GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>, 2524 <0 0 0 2 &intc 0 GIC_SPI GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>, 2525 <0 0 0 3 &intc 0 GIC_SPI GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>, 2526 <0 0 0 4 &intc 0 GIC_SPI GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>; 2527 2528 clocks = <&gcc GCC_PCIE_2B_AUX_CLK>, 2529 <&gcc GCC_PCIE_2B_CFG_AHB_CLK>, 2530 <&gcc GCC_PCIE_2B_MSTR_AXI_CLK>, 2531 <&gcc GCC_PCIE_2B_SLV_AXI_CLK>, 2532 <&gcc GCC_PCIE_2B_SLV_Q2A_AXI_CLK>, 2533 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, 2534 <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>, 2535 <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>; 2536 clock-names = "aux", 2537 "cfg", 2538 "bus_master", 2539 "bus_slave", 2540 "slave_q2a", 2541 "ddrss_sf_tbu", 2542 "noc_aggr_4", 2543 "noc_aggr_south_sf"; 2544 2545 assigned-clocks = <&gcc GCC_PCIE_2B_AUX_CLK>; 2546 assigned-clock-rates = <19200000>; 2547 2548 interconnects = <&aggre2_noc MASTER_PCIE_2B 0 &mc_virt SLAVE_EBI1 0>, 2549 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_2B 0>; 2550 interconnect-names = "pcie-mem", "cpu-pcie"; 2551 2552 resets = <&gcc GCC_PCIE_2B_BCR>; 2553 reset-names = "pci"; 2554 2555 power-domains = <&gcc PCIE_2B_GDSC>; 2556 required-opps = <&rpmhpd_opp_nom>; 2557 2558 phys = <&pcie2b_phy>; 2559 phy-names = "pciephy"; 2560 2561 status = "disabled"; 2562 2563 pcie2b_port0: pcie@0 { 2564 device_type = "pci"; 2565 reg = <0x0 0x0 0x0 0x0 0x0>; 2566 bus-range = <0x01 0xff>; 2567 2568 #address-cells = <3>; 2569 #size-cells = <2>; 2570 ranges; 2571 }; 2572 }; 2573 2574 pcie2b_phy: phy@1c1e000 { 2575 compatible = "qcom,sc8280xp-qmp-gen3x2-pcie-phy"; 2576 reg = <0x0 0x01c1e000 0x0 0x2000>; 2577 2578 clocks = <&gcc GCC_PCIE_2B_AUX_CLK>, 2579 <&gcc GCC_PCIE_2B_CFG_AHB_CLK>, 2580 <&gcc GCC_PCIE_2A2B_CLKREF_CLK>, 2581 <&gcc GCC_PCIE2B_PHY_RCHNG_CLK>, 2582 <&gcc GCC_PCIE_2B_PIPE_CLK>, 2583 <&gcc GCC_PCIE_2B_PIPEDIV2_CLK>; 2584 clock-names = "aux", "cfg_ahb", "ref", "rchng", 2585 "pipe", "pipediv2"; 2586 2587 assigned-clocks = <&gcc GCC_PCIE2B_PHY_RCHNG_CLK>; 2588 assigned-clock-rates = <100000000>; 2589 2590 power-domains = <&gcc PCIE_2B_GDSC>; 2591 2592 resets = <&gcc GCC_PCIE_2B_PHY_BCR>; 2593 reset-names = "phy"; 2594 2595 #clock-cells = <0>; 2596 clock-output-names = "pcie_2b_pipe_clk"; 2597 2598 #phy-cells = <0>; 2599 2600 status = "disabled"; 2601 }; 2602 2603 pcie2a: pcie@1c20000 { 2604 device_type = "pci"; 2605 compatible = "qcom,pcie-sc8280xp"; 2606 reg = <0x0 0x01c20000 0x0 0x3000>, 2607 <0x0 0x3c000000 0x0 0xf1d>, 2608 <0x0 0x3c000f20 0x0 0xa8>, 2609 <0x0 0x3c001000 0x0 0x1000>, 2610 <0x0 0x3c100000 0x0 0x100000>, 2611 <0x0 0x01c23000 0x0 0x1000>; 2612 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; 2613 #address-cells = <3>; 2614 #size-cells = <2>; 2615 ranges = <0x01000000 0x0 0x00000000 0x0 0x3c200000 0x0 0x100000>, 2616 <0x02000000 0x0 0x3c300000 0x0 0x3c300000 0x0 0x1d00000>; 2617 bus-range = <0x00 0xff>; 2618 2619 dma-coherent; 2620 2621 linux,pci-domain = <2>; 2622 num-lanes = <4>; 2623 2624 msi-map = <0x0 &its 0xa0000 0x10000>; 2625 2626 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 2627 <GIC_SPI 523 IRQ_TYPE_LEVEL_HIGH>, 2628 <GIC_SPI 524 IRQ_TYPE_LEVEL_HIGH>, 2629 <GIC_SPI 525 IRQ_TYPE_LEVEL_HIGH>; 2630 interrupt-names = "msi0", "msi1", "msi2", "msi3"; 2631 2632 #interrupt-cells = <1>; 2633 interrupt-map-mask = <0 0 0 0x7>; 2634 interrupt-map = <0 0 0 1 &intc 0 GIC_SPI GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>, 2635 <0 0 0 2 &intc 0 GIC_SPI GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>, 2636 <0 0 0 3 &intc 0 GIC_SPI GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH>, 2637 <0 0 0 4 &intc 0 GIC_SPI GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH>; 2638 2639 clocks = <&gcc GCC_PCIE_2A_AUX_CLK>, 2640 <&gcc GCC_PCIE_2A_CFG_AHB_CLK>, 2641 <&gcc GCC_PCIE_2A_MSTR_AXI_CLK>, 2642 <&gcc GCC_PCIE_2A_SLV_AXI_CLK>, 2643 <&gcc GCC_PCIE_2A_SLV_Q2A_AXI_CLK>, 2644 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, 2645 <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>, 2646 <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>; 2647 clock-names = "aux", 2648 "cfg", 2649 "bus_master", 2650 "bus_slave", 2651 "slave_q2a", 2652 "ddrss_sf_tbu", 2653 "noc_aggr_4", 2654 "noc_aggr_south_sf"; 2655 2656 assigned-clocks = <&gcc GCC_PCIE_2A_AUX_CLK>; 2657 assigned-clock-rates = <19200000>; 2658 2659 interconnects = <&aggre2_noc MASTER_PCIE_2A 0 &mc_virt SLAVE_EBI1 0>, 2660 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_2A 0>; 2661 interconnect-names = "pcie-mem", "cpu-pcie"; 2662 2663 resets = <&gcc GCC_PCIE_2A_BCR>; 2664 reset-names = "pci"; 2665 2666 power-domains = <&gcc PCIE_2A_GDSC>; 2667 required-opps = <&rpmhpd_opp_nom>; 2668 2669 phys = <&pcie2a_phy>; 2670 phy-names = "pciephy"; 2671 2672 status = "disabled"; 2673 2674 pcie2a_port0: pcie@0 { 2675 device_type = "pci"; 2676 reg = <0x0 0x0 0x0 0x0 0x0>; 2677 bus-range = <0x01 0xff>; 2678 2679 #address-cells = <3>; 2680 #size-cells = <2>; 2681 ranges; 2682 }; 2683 }; 2684 2685 pcie2a_phy: phy@1c24000 { 2686 compatible = "qcom,sc8280xp-qmp-gen3x4-pcie-phy"; 2687 reg = <0x0 0x01c24000 0x0 0x2000>, 2688 <0x0 0x01c26000 0x0 0x2000>; 2689 2690 clocks = <&gcc GCC_PCIE_2A_AUX_CLK>, 2691 <&gcc GCC_PCIE_2A_CFG_AHB_CLK>, 2692 <&gcc GCC_PCIE_2A2B_CLKREF_CLK>, 2693 <&gcc GCC_PCIE2A_PHY_RCHNG_CLK>, 2694 <&gcc GCC_PCIE_2A_PIPE_CLK>, 2695 <&gcc GCC_PCIE_2A_PIPEDIV2_CLK>; 2696 clock-names = "aux", "cfg_ahb", "ref", "rchng", 2697 "pipe", "pipediv2"; 2698 2699 assigned-clocks = <&gcc GCC_PCIE2A_PHY_RCHNG_CLK>; 2700 assigned-clock-rates = <100000000>; 2701 2702 power-domains = <&gcc PCIE_2A_GDSC>; 2703 2704 resets = <&gcc GCC_PCIE_2A_PHY_BCR>; 2705 reset-names = "phy"; 2706 2707 qcom,4ln-config-sel = <&tcsr 0xa044 0>; 2708 2709 #clock-cells = <0>; 2710 clock-output-names = "pcie_2a_pipe_clk"; 2711 2712 #phy-cells = <0>; 2713 2714 status = "disabled"; 2715 }; 2716 2717 ufs_mem_hc: ufshc@1d84000 { 2718 compatible = "qcom,sc8280xp-ufshc", "qcom,ufshc", 2719 "jedec,ufs-2.0"; 2720 reg = <0 0x01d84000 0 0x3000>; 2721 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 2722 phys = <&ufs_mem_phy>; 2723 phy-names = "ufsphy"; 2724 lanes-per-direction = <2>; 2725 #reset-cells = <1>; 2726 resets = <&gcc GCC_UFS_PHY_BCR>; 2727 reset-names = "rst"; 2728 2729 power-domains = <&gcc UFS_PHY_GDSC>; 2730 required-opps = <&rpmhpd_opp_nom>; 2731 2732 iommus = <&apps_smmu 0xe0 0x0>; 2733 dma-coherent; 2734 2735 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, 2736 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 2737 <&gcc GCC_UFS_PHY_AHB_CLK>, 2738 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 2739 <&gcc GCC_UFS_REF_CLKREF_CLK>, 2740 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 2741 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 2742 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; 2743 clock-names = "core_clk", 2744 "bus_aggr_clk", 2745 "iface_clk", 2746 "core_clk_unipro", 2747 "ref_clk", 2748 "tx_lane0_sync_clk", 2749 "rx_lane0_sync_clk", 2750 "rx_lane1_sync_clk"; 2751 freq-table-hz = <75000000 300000000>, 2752 <0 0>, 2753 <0 0>, 2754 <75000000 300000000>, 2755 <0 0>, 2756 <0 0>, 2757 <0 0>, 2758 <0 0>; 2759 status = "disabled"; 2760 }; 2761 2762 ufs_mem_phy: phy@1d87000 { 2763 compatible = "qcom,sc8280xp-qmp-ufs-phy"; 2764 reg = <0 0x01d87000 0 0x1000>; 2765 2766 clocks = <&rpmhcc RPMH_CXO_CLK>, 2767 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, 2768 <&gcc GCC_UFS_CARD_CLKREF_CLK>; 2769 clock-names = "ref", 2770 "ref_aux", 2771 "qref"; 2772 2773 power-domains = <&gcc UFS_PHY_GDSC>; 2774 2775 resets = <&ufs_mem_hc 0>; 2776 reset-names = "ufsphy"; 2777 2778 #phy-cells = <0>; 2779 2780 status = "disabled"; 2781 }; 2782 2783 ufs_card_hc: ufshc@1da4000 { 2784 compatible = "qcom,sc8280xp-ufshc", "qcom,ufshc", 2785 "jedec,ufs-2.0"; 2786 reg = <0 0x01da4000 0 0x3000>; 2787 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 2788 phys = <&ufs_card_phy>; 2789 phy-names = "ufsphy"; 2790 lanes-per-direction = <2>; 2791 #reset-cells = <1>; 2792 resets = <&gcc GCC_UFS_CARD_BCR>; 2793 reset-names = "rst"; 2794 2795 power-domains = <&gcc UFS_CARD_GDSC>; 2796 2797 iommus = <&apps_smmu 0x4a0 0x0>; 2798 dma-coherent; 2799 2800 clocks = <&gcc GCC_UFS_CARD_AXI_CLK>, 2801 <&gcc GCC_AGGRE_UFS_CARD_AXI_CLK>, 2802 <&gcc GCC_UFS_CARD_AHB_CLK>, 2803 <&gcc GCC_UFS_CARD_UNIPRO_CORE_CLK>, 2804 <&gcc GCC_UFS_REF_CLKREF_CLK>, 2805 <&gcc GCC_UFS_CARD_TX_SYMBOL_0_CLK>, 2806 <&gcc GCC_UFS_CARD_RX_SYMBOL_0_CLK>, 2807 <&gcc GCC_UFS_CARD_RX_SYMBOL_1_CLK>; 2808 clock-names = "core_clk", 2809 "bus_aggr_clk", 2810 "iface_clk", 2811 "core_clk_unipro", 2812 "ref_clk", 2813 "tx_lane0_sync_clk", 2814 "rx_lane0_sync_clk", 2815 "rx_lane1_sync_clk"; 2816 freq-table-hz = <75000000 300000000>, 2817 <0 0>, 2818 <0 0>, 2819 <75000000 300000000>, 2820 <0 0>, 2821 <0 0>, 2822 <0 0>, 2823 <0 0>; 2824 status = "disabled"; 2825 }; 2826 2827 ufs_card_phy: phy@1da7000 { 2828 compatible = "qcom,sc8280xp-qmp-ufs-phy"; 2829 reg = <0 0x01da7000 0 0x1000>; 2830 2831 clocks = <&rpmhcc RPMH_CXO_CLK>, 2832 <&gcc GCC_UFS_CARD_PHY_AUX_CLK>, 2833 <&gcc GCC_UFS_1_CARD_CLKREF_CLK>; 2834 clock-names = "ref", 2835 "ref_aux", 2836 "qref"; 2837 2838 power-domains = <&gcc UFS_CARD_GDSC>; 2839 2840 resets = <&ufs_card_hc 0>; 2841 reset-names = "ufsphy"; 2842 2843 #phy-cells = <0>; 2844 2845 status = "disabled"; 2846 }; 2847 2848 tcsr_mutex: hwlock@1f40000 { 2849 compatible = "qcom,tcsr-mutex"; 2850 reg = <0x0 0x01f40000 0x0 0x20000>; 2851 #hwlock-cells = <1>; 2852 }; 2853 2854 tcsr: syscon@1fc0000 { 2855 compatible = "qcom,sc8280xp-tcsr", "syscon"; 2856 reg = <0x0 0x01fc0000 0x0 0x30000>; 2857 }; 2858 2859 remoteproc_slpi: remoteproc@2400000 { 2860 compatible = "qcom,sc8280xp-slpi-pas", "qcom,sm8350-slpi-pas"; 2861 reg = <0 0x02400000 0 0x10000>; 2862 2863 interrupts-extended = <&pdc 9 IRQ_TYPE_EDGE_RISING>, 2864 <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>, 2865 <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>, 2866 <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>, 2867 <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>; 2868 interrupt-names = "wdog", 2869 "fatal", 2870 "ready", 2871 "handover", 2872 "stop-ack"; 2873 2874 clocks = <&rpmhcc RPMH_CXO_CLK>; 2875 clock-names = "xo"; 2876 2877 power-domains = <&rpmhpd SC8280XP_LCX>, 2878 <&rpmhpd SC8280XP_LMX>; 2879 power-domain-names = "lcx", "lmx"; 2880 2881 memory-region = <&pil_slpi_mem>; 2882 2883 qcom,qmp = <&aoss_qmp>; 2884 2885 qcom,smem-states = <&smp2p_slpi_out 0>; 2886 qcom,smem-state-names = "stop"; 2887 2888 status = "disabled"; 2889 2890 glink-edge { 2891 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI 2892 IPCC_MPROC_SIGNAL_GLINK_QMP 2893 IRQ_TYPE_EDGE_RISING>; 2894 mboxes = <&ipcc IPCC_CLIENT_SLPI 2895 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2896 2897 label = "slpi"; 2898 qcom,remote-pid = <3>; 2899 2900 fastrpc { 2901 compatible = "qcom,fastrpc"; 2902 qcom,glink-channels = "fastrpcglink-apps-dsp"; 2903 label = "sdsp"; 2904 qcom,non-secure-domain; 2905 #address-cells = <1>; 2906 #size-cells = <0>; 2907 2908 compute-cb@1 { 2909 compatible = "qcom,fastrpc-compute-cb"; 2910 reg = <1>; 2911 iommus = <&apps_smmu 0x0521 0x0>; 2912 }; 2913 2914 compute-cb@2 { 2915 compatible = "qcom,fastrpc-compute-cb"; 2916 reg = <2>; 2917 iommus = <&apps_smmu 0x0522 0x0>; 2918 }; 2919 2920 compute-cb@3 { 2921 compatible = "qcom,fastrpc-compute-cb"; 2922 reg = <3>; 2923 iommus = <&apps_smmu 0x0523 0x0>; 2924 }; 2925 }; 2926 }; 2927 }; 2928 2929 remoteproc_adsp: remoteproc@3000000 { 2930 compatible = "qcom,sc8280xp-adsp-pas"; 2931 reg = <0 0x03000000 0 0x10000>; 2932 2933 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, 2934 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 2935 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 2936 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 2937 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>, 2938 <&smp2p_adsp_in 7 IRQ_TYPE_EDGE_RISING>; 2939 interrupt-names = "wdog", "fatal", "ready", 2940 "handover", "stop-ack", "shutdown-ack"; 2941 2942 clocks = <&rpmhcc RPMH_CXO_CLK>; 2943 clock-names = "xo"; 2944 2945 power-domains = <&rpmhpd SC8280XP_LCX>, 2946 <&rpmhpd SC8280XP_LMX>; 2947 power-domain-names = "lcx", "lmx"; 2948 2949 memory-region = <&pil_adsp_mem>; 2950 2951 qcom,qmp = <&aoss_qmp>; 2952 2953 qcom,smem-states = <&smp2p_adsp_out 0>; 2954 qcom,smem-state-names = "stop"; 2955 2956 status = "disabled"; 2957 2958 remoteproc_adsp_glink: glink-edge { 2959 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 2960 IPCC_MPROC_SIGNAL_GLINK_QMP 2961 IRQ_TYPE_EDGE_RISING>; 2962 mboxes = <&ipcc IPCC_CLIENT_LPASS 2963 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2964 2965 label = "lpass"; 2966 qcom,remote-pid = <2>; 2967 2968 gpr { 2969 compatible = "qcom,gpr"; 2970 qcom,glink-channels = "adsp_apps"; 2971 qcom,domain = <GPR_DOMAIN_ID_ADSP>; 2972 qcom,intents = <512 20>; 2973 #address-cells = <1>; 2974 #size-cells = <0>; 2975 2976 q6apm: service@1 { 2977 compatible = "qcom,q6apm"; 2978 reg = <GPR_APM_MODULE_IID>; 2979 #sound-dai-cells = <0>; 2980 qcom,protection-domain = "avs/audio", 2981 "msm/adsp/audio_pd"; 2982 q6apmdai: dais { 2983 compatible = "qcom,q6apm-dais"; 2984 iommus = <&apps_smmu 0x0c01 0x0>; 2985 }; 2986 2987 q6apmbedai: bedais { 2988 compatible = "qcom,q6apm-lpass-dais"; 2989 #sound-dai-cells = <1>; 2990 }; 2991 }; 2992 2993 q6prm: service@2 { 2994 compatible = "qcom,q6prm"; 2995 reg = <GPR_PRM_MODULE_IID>; 2996 qcom,protection-domain = "avs/audio", 2997 "msm/adsp/audio_pd"; 2998 q6prmcc: clock-controller { 2999 compatible = "qcom,q6prm-lpass-clocks"; 3000 #clock-cells = <2>; 3001 }; 3002 }; 3003 }; 3004 }; 3005 }; 3006 3007 rxmacro: rxmacro@3200000 { 3008 compatible = "qcom,sc8280xp-lpass-rx-macro"; 3009 reg = <0 0x03200000 0 0x1000>; 3010 clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3011 <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3012 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3013 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3014 <&vamacro>; 3015 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; 3016 assigned-clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3017 <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 3018 assigned-clock-rates = <19200000>, <19200000>; 3019 3020 clock-output-names = "mclk"; 3021 #clock-cells = <0>; 3022 #sound-dai-cells = <1>; 3023 3024 pinctrl-names = "default"; 3025 pinctrl-0 = <&rx_swr_default>; 3026 3027 status = "disabled"; 3028 }; 3029 3030 swr1: soundwire@3210000 { 3031 compatible = "qcom,soundwire-v1.6.0"; 3032 reg = <0 0x03210000 0 0x2000>; 3033 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 3034 clocks = <&rxmacro>; 3035 clock-names = "iface"; 3036 resets = <&lpass_audiocc LPASS_AUDIO_SWR_RX_CGCR>; 3037 reset-names = "swr_audio_cgcr"; 3038 label = "RX"; 3039 3040 qcom,din-ports = <0>; 3041 qcom,dout-ports = <5>; 3042 3043 qcom,ports-sinterval-low = /bits/ 8 <0x03 0x1f 0x1f 0x07 0x00>; 3044 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0B 0x01 0x00>; 3045 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0B 0x00 0x00>; 3046 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0x00 0xff 0xff>; 3047 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0x0f 0xff 0xff>; 3048 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>; 3049 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff>; 3050 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>; 3051 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>; 3052 3053 #sound-dai-cells = <1>; 3054 #address-cells = <2>; 3055 #size-cells = <0>; 3056 3057 status = "disabled"; 3058 }; 3059 3060 txmacro: txmacro@3220000 { 3061 compatible = "qcom,sc8280xp-lpass-tx-macro"; 3062 reg = <0 0x03220000 0 0x1000>; 3063 pinctrl-names = "default"; 3064 pinctrl-0 = <&tx_swr_default>; 3065 clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3066 <&q6prmcc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3067 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3068 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3069 <&vamacro>; 3070 3071 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; 3072 assigned-clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3073 <&q6prmcc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 3074 assigned-clock-rates = <19200000>, <19200000>; 3075 clock-output-names = "mclk"; 3076 3077 #clock-cells = <0>; 3078 #sound-dai-cells = <1>; 3079 3080 status = "disabled"; 3081 }; 3082 3083 wsamacro: codec@3240000 { 3084 compatible = "qcom,sc8280xp-lpass-wsa-macro"; 3085 reg = <0 0x03240000 0 0x1000>; 3086 clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3087 <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3088 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3089 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3090 <&vamacro>; 3091 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; 3092 assigned-clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3093 <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 3094 assigned-clock-rates = <19200000>, <19200000>; 3095 3096 #clock-cells = <0>; 3097 clock-output-names = "mclk"; 3098 #sound-dai-cells = <1>; 3099 3100 pinctrl-names = "default"; 3101 pinctrl-0 = <&wsa_swr_default>; 3102 3103 status = "disabled"; 3104 }; 3105 3106 swr0: soundwire@3250000 { 3107 reg = <0 0x03250000 0 0x2000>; 3108 compatible = "qcom,soundwire-v1.6.0"; 3109 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 3110 clocks = <&wsamacro>; 3111 clock-names = "iface"; 3112 resets = <&lpass_audiocc LPASS_AUDIO_SWR_WSA_CGCR>; 3113 reset-names = "swr_audio_cgcr"; 3114 label = "WSA"; 3115 3116 qcom,din-ports = <2>; 3117 qcom,dout-ports = <6>; 3118 3119 qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>; 3120 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>; 3121 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>; 3122 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 3123 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 3124 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 3125 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff 0x01 0xff 0xff>; 3126 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 3127 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 3128 3129 #sound-dai-cells = <1>; 3130 #address-cells = <2>; 3131 #size-cells = <0>; 3132 3133 status = "disabled"; 3134 }; 3135 3136 lpass_audiocc: clock-controller@32a9000 { 3137 compatible = "qcom,sc8280xp-lpassaudiocc"; 3138 reg = <0 0x032a9000 0 0x1000>; 3139 #clock-cells = <1>; 3140 #reset-cells = <1>; 3141 }; 3142 3143 swr2: soundwire@3330000 { 3144 compatible = "qcom,soundwire-v1.6.0"; 3145 reg = <0 0x03330000 0 0x2000>; 3146 interrupts = <GIC_SPI 959 IRQ_TYPE_LEVEL_HIGH>, 3147 <GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH>; 3148 interrupt-names = "core", "wakeup"; 3149 3150 clocks = <&txmacro>; 3151 clock-names = "iface"; 3152 resets = <&lpasscc LPASS_AUDIO_SWR_TX_CGCR>; 3153 reset-names = "swr_audio_cgcr"; 3154 label = "TX"; 3155 #sound-dai-cells = <1>; 3156 #address-cells = <2>; 3157 #size-cells = <0>; 3158 3159 qcom,din-ports = <4>; 3160 qcom,dout-ports = <0>; 3161 qcom,ports-sinterval-low = /bits/ 8 <0x01 0x01 0x03 0x03>; 3162 qcom,ports-offset1 = /bits/ 8 <0x01 0x00 0x02 0x00>; 3163 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00>; 3164 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff>; 3165 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff>; 3166 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff>; 3167 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff>; 3168 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff>; 3169 qcom,ports-lane-control = /bits/ 8 <0x00 0x01 0x00 0x01>; 3170 3171 status = "disabled"; 3172 }; 3173 3174 vamacro: codec@3370000 { 3175 compatible = "qcom,sc8280xp-lpass-va-macro"; 3176 reg = <0 0x03370000 0 0x1000>; 3177 clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3178 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3179 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3180 <&q6prmcc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 3181 clock-names = "mclk", "macro", "dcodec", "npl"; 3182 assigned-clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 3183 assigned-clock-rates = <19200000>; 3184 3185 #clock-cells = <0>; 3186 clock-output-names = "fsgen"; 3187 #sound-dai-cells = <1>; 3188 3189 status = "disabled"; 3190 }; 3191 3192 lpass_tlmm: pinctrl@33c0000 { 3193 compatible = "qcom,sc8280xp-lpass-lpi-pinctrl"; 3194 reg = <0 0x33c0000 0x0 0x20000>, 3195 <0 0x3550000 0x0 0x10000>; 3196 gpio-controller; 3197 #gpio-cells = <2>; 3198 gpio-ranges = <&lpass_tlmm 0 0 19>; 3199 3200 clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3201 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 3202 clock-names = "core", "audio"; 3203 3204 status = "disabled"; 3205 3206 tx_swr_default: tx-swr-default-state { 3207 clk-pins { 3208 pins = "gpio0"; 3209 function = "swr_tx_clk"; 3210 drive-strength = <2>; 3211 slew-rate = <1>; 3212 bias-disable; 3213 }; 3214 3215 data-pins { 3216 pins = "gpio1", "gpio2"; 3217 function = "swr_tx_data"; 3218 drive-strength = <2>; 3219 slew-rate = <1>; 3220 bias-bus-hold; 3221 }; 3222 }; 3223 3224 rx_swr_default: rx-swr-default-state { 3225 clk-pins { 3226 pins = "gpio3"; 3227 function = "swr_rx_clk"; 3228 drive-strength = <2>; 3229 slew-rate = <1>; 3230 bias-disable; 3231 }; 3232 3233 data-pins { 3234 pins = "gpio4", "gpio5"; 3235 function = "swr_rx_data"; 3236 drive-strength = <2>; 3237 slew-rate = <1>; 3238 bias-bus-hold; 3239 }; 3240 }; 3241 3242 dmic01_default: dmic01-default-state { 3243 clk-pins { 3244 pins = "gpio6"; 3245 function = "dmic1_clk"; 3246 drive-strength = <8>; 3247 output-high; 3248 }; 3249 3250 data-pins { 3251 pins = "gpio7"; 3252 function = "dmic1_data"; 3253 drive-strength = <8>; 3254 input-enable; 3255 }; 3256 }; 3257 3258 dmic01_sleep: dmic01-sleep-state { 3259 clk-pins { 3260 pins = "gpio6"; 3261 function = "dmic1_clk"; 3262 drive-strength = <2>; 3263 bias-disable; 3264 output-low; 3265 }; 3266 3267 data-pins { 3268 pins = "gpio7"; 3269 function = "dmic1_data"; 3270 drive-strength = <2>; 3271 bias-pull-down; 3272 input-enable; 3273 }; 3274 }; 3275 3276 dmic23_default: dmic23-default-state { 3277 clk-pins { 3278 pins = "gpio8"; 3279 function = "dmic2_clk"; 3280 drive-strength = <8>; 3281 output-high; 3282 }; 3283 3284 data-pins { 3285 pins = "gpio9"; 3286 function = "dmic2_data"; 3287 drive-strength = <8>; 3288 input-enable; 3289 }; 3290 }; 3291 3292 dmic23_sleep: dmic23-sleep-state { 3293 clk-pins { 3294 pins = "gpio8"; 3295 function = "dmic2_clk"; 3296 drive-strength = <2>; 3297 bias-disable; 3298 output-low; 3299 }; 3300 3301 data-pins { 3302 pins = "gpio9"; 3303 function = "dmic2_data"; 3304 drive-strength = <2>; 3305 bias-pull-down; 3306 input-enable; 3307 }; 3308 }; 3309 3310 wsa_swr_default: wsa-swr-default-state { 3311 clk-pins { 3312 pins = "gpio10"; 3313 function = "wsa_swr_clk"; 3314 drive-strength = <2>; 3315 slew-rate = <1>; 3316 bias-disable; 3317 }; 3318 3319 data-pins { 3320 pins = "gpio11"; 3321 function = "wsa_swr_data"; 3322 drive-strength = <2>; 3323 slew-rate = <1>; 3324 bias-bus-hold; 3325 }; 3326 }; 3327 3328 wsa2_swr_default: wsa2-swr-default-state { 3329 clk-pins { 3330 pins = "gpio15"; 3331 function = "wsa2_swr_clk"; 3332 drive-strength = <2>; 3333 slew-rate = <1>; 3334 bias-disable; 3335 }; 3336 3337 data-pins { 3338 pins = "gpio16"; 3339 function = "wsa2_swr_data"; 3340 drive-strength = <2>; 3341 slew-rate = <1>; 3342 bias-bus-hold; 3343 }; 3344 }; 3345 }; 3346 3347 lpasscc: clock-controller@33e0000 { 3348 compatible = "qcom,sc8280xp-lpasscc"; 3349 reg = <0 0x033e0000 0 0x12000>; 3350 #clock-cells = <1>; 3351 #reset-cells = <1>; 3352 }; 3353 3354 gpu: gpu@3d00000 { 3355 compatible = "qcom,adreno-690.0", "qcom,adreno"; 3356 3357 reg = <0 0x03d00000 0 0x40000>, 3358 <0 0x03d9e000 0 0x1000>, 3359 <0 0x03d61000 0 0x800>; 3360 reg-names = "kgsl_3d0_reg_memory", 3361 "cx_mem", 3362 "cx_dbgc"; 3363 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 3364 iommus = <&gpu_smmu 0 0xc00>, <&gpu_smmu 1 0xc00>; 3365 operating-points-v2 = <&gpu_opp_table>; 3366 3367 qcom,gmu = <&gmu>; 3368 interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>; 3369 interconnect-names = "gfx-mem"; 3370 #cooling-cells = <2>; 3371 3372 status = "disabled"; 3373 3374 gpu_zap_shader: zap-shader { 3375 memory-region = <&pil_gpu_mem>; 3376 }; 3377 3378 gpu_opp_table: opp-table { 3379 compatible = "operating-points-v2"; 3380 3381 opp-270000000 { 3382 opp-hz = /bits/ 64 <270000000>; 3383 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 3384 opp-peak-kBps = <451000>; 3385 }; 3386 3387 opp-410000000 { 3388 opp-hz = /bits/ 64 <410000000>; 3389 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 3390 opp-peak-kBps = <1555000>; 3391 }; 3392 3393 opp-500000000 { 3394 opp-hz = /bits/ 64 <500000000>; 3395 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 3396 opp-peak-kBps = <1555000>; 3397 }; 3398 3399 opp-547000000 { 3400 opp-hz = /bits/ 64 <547000000>; 3401 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 3402 opp-peak-kBps = <1555000>; 3403 }; 3404 3405 opp-606000000 { 3406 opp-hz = /bits/ 64 <606000000>; 3407 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 3408 opp-peak-kBps = <2736000>; 3409 }; 3410 3411 opp-640000000 { 3412 opp-hz = /bits/ 64 <640000000>; 3413 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 3414 opp-peak-kBps = <2736000>; 3415 }; 3416 3417 opp-655000000 { 3418 opp-hz = /bits/ 64 <655000000>; 3419 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 3420 opp-peak-kBps = <2736000>; 3421 }; 3422 3423 opp-690000000 { 3424 opp-hz = /bits/ 64 <690000000>; 3425 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 3426 opp-peak-kBps = <2736000>; 3427 }; 3428 }; 3429 }; 3430 3431 gmu: gmu@3d6a000 { 3432 compatible = "qcom,adreno-gmu-690.0", "qcom,adreno-gmu"; 3433 reg = <0 0x03d6a000 0 0x34000>, 3434 <0 0x03de0000 0 0x10000>, 3435 <0 0x0b290000 0 0x10000>; 3436 reg-names = "gmu", "rscc", "gmu_pdc"; 3437 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 3438 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 3439 interrupt-names = "hfi", "gmu"; 3440 clocks = <&gpucc GPU_CC_CX_GMU_CLK>, 3441 <&gpucc GPU_CC_CXO_CLK>, 3442 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 3443 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 3444 <&gpucc GPU_CC_AHB_CLK>, 3445 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 3446 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>; 3447 clock-names = "gmu", 3448 "cxo", 3449 "axi", 3450 "memnoc", 3451 "ahb", 3452 "hub", 3453 "smmu_vote"; 3454 power-domains = <&gpucc GPU_CC_CX_GDSC>, 3455 <&gpucc GPU_CC_GX_GDSC>; 3456 power-domain-names = "cx", 3457 "gx"; 3458 iommus = <&gpu_smmu 5 0xc00>; 3459 operating-points-v2 = <&gmu_opp_table>; 3460 3461 gmu_opp_table: opp-table { 3462 compatible = "operating-points-v2"; 3463 3464 opp-200000000 { 3465 opp-hz = /bits/ 64 <200000000>; 3466 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 3467 }; 3468 3469 opp-500000000 { 3470 opp-hz = /bits/ 64 <500000000>; 3471 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 3472 }; 3473 }; 3474 }; 3475 3476 gpucc: clock-controller@3d90000 { 3477 compatible = "qcom,sc8280xp-gpucc"; 3478 reg = <0 0x03d90000 0 0x9000>; 3479 clocks = <&rpmhcc RPMH_CXO_CLK>, 3480 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 3481 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 3482 clock-names = "bi_tcxo", 3483 "gcc_gpu_gpll0_clk_src", 3484 "gcc_gpu_gpll0_div_clk_src"; 3485 3486 power-domains = <&rpmhpd SC8280XP_GFX>; 3487 #clock-cells = <1>; 3488 #reset-cells = <1>; 3489 #power-domain-cells = <1>; 3490 }; 3491 3492 gpu_smmu: iommu@3da0000 { 3493 compatible = "qcom,sc8280xp-smmu-500", "qcom,adreno-smmu", 3494 "qcom,smmu-500", "arm,mmu-500"; 3495 reg = <0 0x03da0000 0 0x20000>; 3496 #iommu-cells = <2>; 3497 #global-interrupts = <2>; 3498 interrupts = <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>, 3499 <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, 3500 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, 3501 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, 3502 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, 3503 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 3504 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 3505 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 3506 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 3507 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, 3508 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, 3509 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>, 3510 <GIC_SPI 688 IRQ_TYPE_LEVEL_HIGH>, 3511 <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>; 3512 3513 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 3514 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, 3515 <&gpucc GPU_CC_AHB_CLK>, 3516 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, 3517 <&gpucc GPU_CC_CX_GMU_CLK>, 3518 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 3519 <&gpucc GPU_CC_HUB_AON_CLK>; 3520 clock-names = "gcc_gpu_memnoc_gfx_clk", 3521 "gcc_gpu_snoc_dvm_gfx_clk", 3522 "gpu_cc_ahb_clk", 3523 "gpu_cc_hlos1_vote_gpu_smmu_clk", 3524 "gpu_cc_cx_gmu_clk", 3525 "gpu_cc_hub_cx_int_clk", 3526 "gpu_cc_hub_aon_clk"; 3527 3528 power-domains = <&gpucc GPU_CC_CX_GDSC>; 3529 dma-coherent; 3530 }; 3531 3532 sdc2: mmc@8804000 { 3533 compatible = "qcom,sc8280xp-sdhci", "qcom,sdhci-msm-v5"; 3534 reg = <0 0x08804000 0 0x1000>; 3535 3536 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 3537 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 3538 interrupt-names = "hc_irq", "pwr_irq"; 3539 3540 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 3541 <&gcc GCC_SDCC2_APPS_CLK>, 3542 <&rpmhcc RPMH_CXO_CLK>; 3543 clock-names = "iface", "core", "xo"; 3544 resets = <&gcc GCC_SDCC2_BCR>; 3545 interconnects = <&aggre2_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, 3546 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>; 3547 interconnect-names = "sdhc-ddr","cpu-sdhc"; 3548 iommus = <&apps_smmu 0x4e0 0x0>; 3549 power-domains = <&rpmhpd SC8280XP_CX>; 3550 operating-points-v2 = <&sdc2_opp_table>; 3551 bus-width = <4>; 3552 dma-coherent; 3553 3554 status = "disabled"; 3555 3556 sdc2_opp_table: opp-table { 3557 compatible = "operating-points-v2"; 3558 3559 opp-100000000 { 3560 opp-hz = /bits/ 64 <100000000>; 3561 required-opps = <&rpmhpd_opp_low_svs>; 3562 opp-peak-kBps = <1800000 400000>; 3563 opp-avg-kBps = <100000 0>; 3564 }; 3565 3566 opp-202000000 { 3567 opp-hz = /bits/ 64 <202000000>; 3568 required-opps = <&rpmhpd_opp_svs_l1>; 3569 opp-peak-kBps = <5400000 1600000>; 3570 opp-avg-kBps = <200000 0>; 3571 }; 3572 }; 3573 }; 3574 3575 usb_0_hsphy: phy@88e5000 { 3576 compatible = "qcom,sc8280xp-usb-hs-phy", 3577 "qcom,usb-snps-hs-5nm-phy"; 3578 reg = <0 0x088e5000 0 0x400>; 3579 clocks = <&rpmhcc RPMH_CXO_CLK>; 3580 clock-names = "ref"; 3581 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 3582 3583 #phy-cells = <0>; 3584 3585 status = "disabled"; 3586 }; 3587 3588 usb_2_hsphy0: phy@88e7000 { 3589 compatible = "qcom,sc8280xp-usb-hs-phy", 3590 "qcom,usb-snps-hs-5nm-phy"; 3591 reg = <0 0x088e7000 0 0x400>; 3592 clocks = <&gcc GCC_USB2_HS0_CLKREF_CLK>; 3593 clock-names = "ref"; 3594 resets = <&gcc GCC_QUSB2PHY_HS0_MP_BCR>; 3595 3596 #phy-cells = <0>; 3597 3598 status = "disabled"; 3599 }; 3600 3601 usb_2_hsphy1: phy@88e8000 { 3602 compatible = "qcom,sc8280xp-usb-hs-phy", 3603 "qcom,usb-snps-hs-5nm-phy"; 3604 reg = <0 0x088e8000 0 0x400>; 3605 clocks = <&gcc GCC_USB2_HS1_CLKREF_CLK>; 3606 clock-names = "ref"; 3607 resets = <&gcc GCC_QUSB2PHY_HS1_MP_BCR>; 3608 3609 #phy-cells = <0>; 3610 3611 status = "disabled"; 3612 }; 3613 3614 usb_2_hsphy2: phy@88e9000 { 3615 compatible = "qcom,sc8280xp-usb-hs-phy", 3616 "qcom,usb-snps-hs-5nm-phy"; 3617 reg = <0 0x088e9000 0 0x400>; 3618 clocks = <&gcc GCC_USB2_HS2_CLKREF_CLK>; 3619 clock-names = "ref"; 3620 resets = <&gcc GCC_QUSB2PHY_HS2_MP_BCR>; 3621 3622 #phy-cells = <0>; 3623 3624 status = "disabled"; 3625 }; 3626 3627 usb_2_hsphy3: phy@88ea000 { 3628 compatible = "qcom,sc8280xp-usb-hs-phy", 3629 "qcom,usb-snps-hs-5nm-phy"; 3630 reg = <0 0x088ea000 0 0x400>; 3631 clocks = <&gcc GCC_USB2_HS3_CLKREF_CLK>; 3632 clock-names = "ref"; 3633 resets = <&gcc GCC_QUSB2PHY_HS3_MP_BCR>; 3634 3635 #phy-cells = <0>; 3636 3637 status = "disabled"; 3638 }; 3639 3640 usb_0_qmpphy: phy@88eb000 { 3641 compatible = "qcom,sc8280xp-qmp-usb43dp-phy"; 3642 reg = <0 0x088eb000 0 0x4000>; 3643 3644 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 3645 <&gcc GCC_USB4_EUD_CLKREF_CLK>, 3646 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 3647 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 3648 clock-names = "aux", "ref", "com_aux", "usb3_pipe"; 3649 3650 power-domains = <&gcc USB30_PRIM_GDSC>; 3651 3652 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, 3653 <&gcc GCC_USB4_DP_PHY_PRIM_BCR>; 3654 reset-names = "phy", "common"; 3655 3656 #clock-cells = <1>; 3657 #phy-cells = <1>; 3658 3659 status = "disabled"; 3660 3661 ports { 3662 #address-cells = <1>; 3663 #size-cells = <0>; 3664 3665 port@0 { 3666 reg = <0>; 3667 3668 usb_0_qmpphy_out: endpoint {}; 3669 }; 3670 3671 port@1 { 3672 reg = <1>; 3673 3674 usb_0_qmpphy_usb_ss_in: endpoint { 3675 remote-endpoint = <&usb_0_dwc3_ss>; 3676 }; 3677 }; 3678 3679 port@2 { 3680 reg = <2>; 3681 3682 usb_0_qmpphy_dp_in: endpoint {}; 3683 }; 3684 }; 3685 }; 3686 3687 usb_2_qmpphy0: phy@88ef000 { 3688 compatible = "qcom,sc8280xp-qmp-usb3-uni-phy"; 3689 reg = <0 0x088ef000 0 0x2000>; 3690 3691 clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>, 3692 <&gcc GCC_USB3_MP0_CLKREF_CLK>, 3693 <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>, 3694 <&gcc GCC_USB3_MP_PHY_PIPE_0_CLK>; 3695 clock-names = "aux", "ref", "com_aux", "pipe"; 3696 3697 resets = <&gcc GCC_USB3_UNIPHY_MP0_BCR>, 3698 <&gcc GCC_USB3UNIPHY_PHY_MP0_BCR>; 3699 reset-names = "phy", "phy_phy"; 3700 3701 power-domains = <&gcc USB30_MP_GDSC>; 3702 3703 #clock-cells = <0>; 3704 clock-output-names = "usb2_phy0_pipe_clk"; 3705 3706 #phy-cells = <0>; 3707 3708 status = "disabled"; 3709 }; 3710 3711 usb_2_qmpphy1: phy@88f1000 { 3712 compatible = "qcom,sc8280xp-qmp-usb3-uni-phy"; 3713 reg = <0 0x088f1000 0 0x2000>; 3714 3715 clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>, 3716 <&gcc GCC_USB3_MP1_CLKREF_CLK>, 3717 <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>, 3718 <&gcc GCC_USB3_MP_PHY_PIPE_1_CLK>; 3719 clock-names = "aux", "ref", "com_aux", "pipe"; 3720 3721 resets = <&gcc GCC_USB3_UNIPHY_MP1_BCR>, 3722 <&gcc GCC_USB3UNIPHY_PHY_MP1_BCR>; 3723 reset-names = "phy", "phy_phy"; 3724 3725 power-domains = <&gcc USB30_MP_GDSC>; 3726 3727 #clock-cells = <0>; 3728 clock-output-names = "usb2_phy1_pipe_clk"; 3729 3730 #phy-cells = <0>; 3731 3732 status = "disabled"; 3733 }; 3734 3735 refgen: regulator@8900000 { 3736 compatible = "qcom,sc8280xp-refgen-regulator", 3737 "qcom,sm8250-refgen-regulator"; 3738 reg = <0x0 0x08900000 0x0 0x96>; 3739 }; 3740 3741 usb_1_hsphy: phy@8902000 { 3742 compatible = "qcom,sc8280xp-usb-hs-phy", 3743 "qcom,usb-snps-hs-5nm-phy"; 3744 reg = <0 0x08902000 0 0x400>; 3745 #phy-cells = <0>; 3746 3747 clocks = <&rpmhcc RPMH_CXO_CLK>; 3748 clock-names = "ref"; 3749 3750 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 3751 3752 status = "disabled"; 3753 }; 3754 3755 usb_1_qmpphy: phy@8903000 { 3756 compatible = "qcom,sc8280xp-qmp-usb43dp-phy"; 3757 reg = <0 0x08903000 0 0x4000>; 3758 3759 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, 3760 <&gcc GCC_USB4_CLKREF_CLK>, 3761 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>, 3762 <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; 3763 clock-names = "aux", "ref", "com_aux", "usb3_pipe"; 3764 3765 power-domains = <&gcc USB30_SEC_GDSC>; 3766 3767 resets = <&gcc GCC_USB3_PHY_SEC_BCR>, 3768 <&gcc GCC_USB4_1_DP_PHY_PRIM_BCR>; 3769 reset-names = "phy", "common"; 3770 3771 #clock-cells = <1>; 3772 #phy-cells = <1>; 3773 3774 status = "disabled"; 3775 3776 ports { 3777 #address-cells = <1>; 3778 #size-cells = <0>; 3779 3780 port@0 { 3781 reg = <0>; 3782 3783 usb_1_qmpphy_out: endpoint {}; 3784 }; 3785 3786 port@1 { 3787 reg = <1>; 3788 3789 usb_1_qmpphy_usb_ss_in: endpoint { 3790 remote-endpoint = <&usb_1_dwc3_ss>; 3791 }; 3792 }; 3793 3794 port@2 { 3795 reg = <2>; 3796 3797 usb_1_qmpphy_dp_in: endpoint {}; 3798 }; 3799 }; 3800 }; 3801 3802 mdss1_dp0_phy: phy@8909a00 { 3803 compatible = "qcom,sc8280xp-dp-phy"; 3804 reg = <0 0x08909a00 0 0x19c>, 3805 <0 0x08909200 0 0xec>, 3806 <0 0x08909600 0 0xec>, 3807 <0 0x08909000 0 0x1c8>; 3808 3809 clocks = <&dispcc1 DISP_CC_MDSS_DPTX0_AUX_CLK>, 3810 <&dispcc1 DISP_CC_MDSS_AHB_CLK>; 3811 clock-names = "aux", "cfg_ahb"; 3812 power-domains = <&rpmhpd SC8280XP_MX>; 3813 3814 #clock-cells = <1>; 3815 #phy-cells = <0>; 3816 3817 status = "disabled"; 3818 }; 3819 3820 mdss1_dp1_phy: phy@890ca00 { 3821 compatible = "qcom,sc8280xp-dp-phy"; 3822 reg = <0 0x0890ca00 0 0x19c>, 3823 <0 0x0890c200 0 0xec>, 3824 <0 0x0890c600 0 0xec>, 3825 <0 0x0890c000 0 0x1c8>; 3826 3827 clocks = <&dispcc1 DISP_CC_MDSS_DPTX1_AUX_CLK>, 3828 <&dispcc1 DISP_CC_MDSS_AHB_CLK>; 3829 clock-names = "aux", "cfg_ahb"; 3830 power-domains = <&rpmhpd SC8280XP_MX>; 3831 3832 #clock-cells = <1>; 3833 #phy-cells = <0>; 3834 3835 status = "disabled"; 3836 }; 3837 3838 pmu@9091000 { 3839 compatible = "qcom,sc8280xp-llcc-bwmon", "qcom,sc7280-llcc-bwmon"; 3840 reg = <0 0x09091000 0 0x1000>; 3841 3842 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 3843 3844 interconnects = <&mc_virt MASTER_LLCC 3 &mc_virt SLAVE_EBI1 3>; 3845 3846 operating-points-v2 = <&llcc_bwmon_opp_table>; 3847 3848 llcc_bwmon_opp_table: opp-table { 3849 compatible = "operating-points-v2"; 3850 3851 opp-0 { 3852 opp-peak-kBps = <762000>; 3853 }; 3854 opp-1 { 3855 opp-peak-kBps = <1720000>; 3856 }; 3857 opp-2 { 3858 opp-peak-kBps = <2086000>; 3859 }; 3860 opp-3 { 3861 opp-peak-kBps = <2597000>; 3862 }; 3863 opp-4 { 3864 opp-peak-kBps = <2929000>; 3865 }; 3866 opp-5 { 3867 opp-peak-kBps = <3879000>; 3868 }; 3869 opp-6 { 3870 opp-peak-kBps = <5161000>; 3871 }; 3872 opp-7 { 3873 opp-peak-kBps = <5931000>; 3874 }; 3875 opp-8 { 3876 opp-peak-kBps = <6515000>; 3877 }; 3878 opp-9 { 3879 opp-peak-kBps = <7980000>; 3880 }; 3881 opp-10 { 3882 opp-peak-kBps = <8136000>; 3883 }; 3884 opp-11 { 3885 opp-peak-kBps = <10437000>; 3886 }; 3887 opp-12 { 3888 opp-peak-kBps = <12191000>; 3889 }; 3890 }; 3891 }; 3892 3893 pmu@90b6400 { 3894 compatible = "qcom,sc8280xp-cpu-bwmon", "qcom,sdm845-bwmon"; 3895 reg = <0 0x090b6400 0 0x600>; 3896 3897 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 3898 3899 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &gem_noc SLAVE_LLCC 3>; 3900 operating-points-v2 = <&cpu_bwmon_opp_table>; 3901 3902 cpu_bwmon_opp_table: opp-table { 3903 compatible = "operating-points-v2"; 3904 3905 opp-0 { 3906 opp-peak-kBps = <2288000>; 3907 }; 3908 opp-1 { 3909 opp-peak-kBps = <4577000>; 3910 }; 3911 opp-2 { 3912 opp-peak-kBps = <7110000>; 3913 }; 3914 opp-3 { 3915 opp-peak-kBps = <9155000>; 3916 }; 3917 opp-4 { 3918 opp-peak-kBps = <12298000>; 3919 }; 3920 opp-5 { 3921 opp-peak-kBps = <14236000>; 3922 }; 3923 opp-6 { 3924 opp-peak-kBps = <15258001>; 3925 }; 3926 }; 3927 }; 3928 3929 system-cache-controller@9200000 { 3930 compatible = "qcom,sc8280xp-llcc"; 3931 reg = <0 0x09200000 0 0x58000>, <0 0x09280000 0 0x58000>, 3932 <0 0x09300000 0 0x58000>, <0 0x09380000 0 0x58000>, 3933 <0 0x09400000 0 0x58000>, <0 0x09480000 0 0x58000>, 3934 <0 0x09500000 0 0x58000>, <0 0x09580000 0 0x58000>, 3935 <0 0x09600000 0 0x58000>; 3936 reg-names = "llcc0_base", "llcc1_base", "llcc2_base", 3937 "llcc3_base", "llcc4_base", "llcc5_base", 3938 "llcc6_base", "llcc7_base", "llcc_broadcast_base"; 3939 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 3940 }; 3941 3942 usb_2: usb@a4f8800 { 3943 compatible = "qcom,sc8280xp-dwc3-mp", "qcom,dwc3"; 3944 reg = <0 0x0a4f8800 0 0x400>; 3945 #address-cells = <2>; 3946 #size-cells = <2>; 3947 ranges; 3948 3949 clocks = <&gcc GCC_CFG_NOC_USB3_MP_AXI_CLK>, 3950 <&gcc GCC_USB30_MP_MASTER_CLK>, 3951 <&gcc GCC_AGGRE_USB3_MP_AXI_CLK>, 3952 <&gcc GCC_USB30_MP_SLEEP_CLK>, 3953 <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>, 3954 <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>, 3955 <&gcc GCC_AGGRE_USB_NOC_NORTH_AXI_CLK>, 3956 <&gcc GCC_AGGRE_USB_NOC_SOUTH_AXI_CLK>, 3957 <&gcc GCC_SYS_NOC_USB_AXI_CLK>; 3958 clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi", 3959 "noc_aggr", "noc_aggr_north", "noc_aggr_south", "noc_sys"; 3960 3961 assigned-clocks = <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>, 3962 <&gcc GCC_USB30_MP_MASTER_CLK>; 3963 assigned-clock-rates = <19200000>, <200000000>; 3964 3965 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 3966 <&intc GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 3967 <&intc GIC_SPI 857 IRQ_TYPE_LEVEL_HIGH>, 3968 <&intc GIC_SPI 856 IRQ_TYPE_LEVEL_HIGH>, 3969 <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 3970 <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 3971 <&intc GIC_SPI 860 IRQ_TYPE_LEVEL_HIGH>, 3972 <&intc GIC_SPI 859 IRQ_TYPE_LEVEL_HIGH>, 3973 <&pdc 127 IRQ_TYPE_EDGE_BOTH>, 3974 <&pdc 126 IRQ_TYPE_EDGE_BOTH>, 3975 <&pdc 129 IRQ_TYPE_EDGE_BOTH>, 3976 <&pdc 128 IRQ_TYPE_EDGE_BOTH>, 3977 <&pdc 131 IRQ_TYPE_EDGE_BOTH>, 3978 <&pdc 130 IRQ_TYPE_EDGE_BOTH>, 3979 <&pdc 133 IRQ_TYPE_EDGE_BOTH>, 3980 <&pdc 132 IRQ_TYPE_EDGE_BOTH>, 3981 <&pdc 16 IRQ_TYPE_LEVEL_HIGH>, 3982 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; 3983 3984 interrupt-names = "pwr_event_1", "pwr_event_2", 3985 "pwr_event_3", "pwr_event_4", 3986 "hs_phy_1", "hs_phy_2", 3987 "hs_phy_3", "hs_phy_4", 3988 "dp_hs_phy_1", "dm_hs_phy_1", 3989 "dp_hs_phy_2", "dm_hs_phy_2", 3990 "dp_hs_phy_3", "dm_hs_phy_3", 3991 "dp_hs_phy_4", "dm_hs_phy_4", 3992 "ss_phy_1", "ss_phy_2"; 3993 3994 power-domains = <&gcc USB30_MP_GDSC>; 3995 required-opps = <&rpmhpd_opp_nom>; 3996 3997 resets = <&gcc GCC_USB30_MP_BCR>; 3998 3999 interconnects = <&aggre1_noc MASTER_USB3_MP 0 &mc_virt SLAVE_EBI1 0>, 4000 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_MP 0>; 4001 interconnect-names = "usb-ddr", "apps-usb"; 4002 4003 wakeup-source; 4004 4005 status = "disabled"; 4006 4007 usb_2_dwc3: usb@a400000 { 4008 compatible = "snps,dwc3"; 4009 reg = <0 0x0a400000 0 0xcd00>; 4010 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 4011 iommus = <&apps_smmu 0x800 0x0>; 4012 phys = <&usb_2_hsphy0>, <&usb_2_qmpphy0>, 4013 <&usb_2_hsphy1>, <&usb_2_qmpphy1>, 4014 <&usb_2_hsphy2>, 4015 <&usb_2_hsphy3>; 4016 phy-names = "usb2-0", "usb3-0", 4017 "usb2-1", "usb3-1", 4018 "usb2-2", 4019 "usb2-3"; 4020 dr_mode = "host"; 4021 snps,dis-u1-entry-quirk; 4022 snps,dis-u2-entry-quirk; 4023 }; 4024 }; 4025 4026 usb_0: usb@a6f8800 { 4027 compatible = "qcom,sc8280xp-dwc3", "qcom,dwc3"; 4028 reg = <0 0x0a6f8800 0 0x400>; 4029 #address-cells = <2>; 4030 #size-cells = <2>; 4031 ranges; 4032 4033 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 4034 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 4035 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 4036 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 4037 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 4038 <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>, 4039 <&gcc GCC_AGGRE_USB_NOC_NORTH_AXI_CLK>, 4040 <&gcc GCC_AGGRE_USB_NOC_SOUTH_AXI_CLK>, 4041 <&gcc GCC_SYS_NOC_USB_AXI_CLK>; 4042 clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi", 4043 "noc_aggr", "noc_aggr_north", "noc_aggr_south", "noc_sys"; 4044 4045 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 4046 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 4047 assigned-clock-rates = <19200000>, <200000000>; 4048 4049 interrupts-extended = <&intc GIC_SPI 804 IRQ_TYPE_LEVEL_HIGH>, 4050 <&intc GIC_SPI 805 IRQ_TYPE_LEVEL_HIGH>, 4051 <&pdc 14 IRQ_TYPE_EDGE_BOTH>, 4052 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 4053 <&pdc 138 IRQ_TYPE_LEVEL_HIGH>; 4054 interrupt-names = "pwr_event", 4055 "hs_phy_irq", 4056 "dp_hs_phy_irq", 4057 "dm_hs_phy_irq", 4058 "ss_phy_irq"; 4059 4060 power-domains = <&gcc USB30_PRIM_GDSC>; 4061 required-opps = <&rpmhpd_opp_nom>; 4062 4063 resets = <&gcc GCC_USB30_PRIM_BCR>; 4064 4065 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>, 4066 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>; 4067 interconnect-names = "usb-ddr", "apps-usb"; 4068 4069 wakeup-source; 4070 4071 status = "disabled"; 4072 4073 usb_0_dwc3: usb@a600000 { 4074 compatible = "snps,dwc3"; 4075 reg = <0 0x0a600000 0 0xcd00>; 4076 interrupts = <GIC_SPI 803 IRQ_TYPE_LEVEL_HIGH>; 4077 iommus = <&apps_smmu 0x820 0x0>; 4078 phys = <&usb_0_hsphy>, <&usb_0_qmpphy QMP_USB43DP_USB3_PHY>; 4079 phy-names = "usb2-phy", "usb3-phy"; 4080 snps,dis-u1-entry-quirk; 4081 snps,dis-u2-entry-quirk; 4082 4083 ports { 4084 #address-cells = <1>; 4085 #size-cells = <0>; 4086 4087 port@0 { 4088 reg = <0>; 4089 4090 usb_0_dwc3_hs: endpoint { 4091 }; 4092 }; 4093 4094 port@1 { 4095 reg = <1>; 4096 4097 usb_0_dwc3_ss: endpoint { 4098 remote-endpoint = <&usb_0_qmpphy_usb_ss_in>; 4099 }; 4100 }; 4101 }; 4102 }; 4103 }; 4104 4105 usb_1: usb@a8f8800 { 4106 compatible = "qcom,sc8280xp-dwc3", "qcom,dwc3"; 4107 reg = <0 0x0a8f8800 0 0x400>; 4108 #address-cells = <2>; 4109 #size-cells = <2>; 4110 ranges; 4111 4112 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 4113 <&gcc GCC_USB30_SEC_MASTER_CLK>, 4114 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 4115 <&gcc GCC_USB30_SEC_SLEEP_CLK>, 4116 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 4117 <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>, 4118 <&gcc GCC_AGGRE_USB_NOC_NORTH_AXI_CLK>, 4119 <&gcc GCC_AGGRE_USB_NOC_SOUTH_AXI_CLK>, 4120 <&gcc GCC_SYS_NOC_USB_AXI_CLK>; 4121 clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi", 4122 "noc_aggr", "noc_aggr_north", "noc_aggr_south", "noc_sys"; 4123 4124 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 4125 <&gcc GCC_USB30_SEC_MASTER_CLK>; 4126 assigned-clock-rates = <19200000>, <200000000>; 4127 4128 interrupts-extended = <&intc GIC_SPI 811 IRQ_TYPE_LEVEL_HIGH>, 4129 <&intc GIC_SPI 790 IRQ_TYPE_LEVEL_HIGH>, 4130 <&pdc 12 IRQ_TYPE_EDGE_BOTH>, 4131 <&pdc 13 IRQ_TYPE_EDGE_BOTH>, 4132 <&pdc 136 IRQ_TYPE_LEVEL_HIGH>; 4133 interrupt-names = "pwr_event", 4134 "hs_phy_irq", 4135 "dp_hs_phy_irq", 4136 "dm_hs_phy_irq", 4137 "ss_phy_irq"; 4138 4139 power-domains = <&gcc USB30_SEC_GDSC>; 4140 required-opps = <&rpmhpd_opp_nom>; 4141 4142 resets = <&gcc GCC_USB30_SEC_BCR>; 4143 4144 interconnects = <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI1 0>, 4145 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_1 0>; 4146 interconnect-names = "usb-ddr", "apps-usb"; 4147 4148 wakeup-source; 4149 4150 status = "disabled"; 4151 4152 usb_1_dwc3: usb@a800000 { 4153 compatible = "snps,dwc3"; 4154 reg = <0 0x0a800000 0 0xcd00>; 4155 interrupts = <GIC_SPI 810 IRQ_TYPE_LEVEL_HIGH>; 4156 iommus = <&apps_smmu 0x860 0x0>; 4157 phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>; 4158 phy-names = "usb2-phy", "usb3-phy"; 4159 snps,dis-u1-entry-quirk; 4160 snps,dis-u2-entry-quirk; 4161 4162 ports { 4163 #address-cells = <1>; 4164 #size-cells = <0>; 4165 4166 port@0 { 4167 reg = <0>; 4168 4169 usb_1_dwc3_hs: endpoint { 4170 }; 4171 }; 4172 4173 port@1 { 4174 reg = <1>; 4175 4176 usb_1_dwc3_ss: endpoint { 4177 remote-endpoint = <&usb_1_qmpphy_usb_ss_in>; 4178 }; 4179 }; 4180 }; 4181 }; 4182 }; 4183 4184 cci0: cci@ac4a000 { 4185 compatible = "qcom,sc8280xp-cci", "qcom,msm8996-cci"; 4186 reg = <0 0x0ac4a000 0 0x1000>; 4187 4188 interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>; 4189 4190 clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>, 4191 <&camcc CAMCC_SLOW_AHB_CLK_SRC>, 4192 <&camcc CAMCC_CPAS_AHB_CLK>, 4193 <&camcc CAMCC_CCI_0_CLK>; 4194 clock-names = "camnoc_axi", 4195 "slow_ahb_src", 4196 "cpas_ahb", 4197 "cci"; 4198 4199 power-domains = <&camcc TITAN_TOP_GDSC>; 4200 4201 pinctrl-0 = <&cci0_default>; 4202 pinctrl-1 = <&cci0_sleep>; 4203 pinctrl-names = "default", "sleep"; 4204 4205 #address-cells = <1>; 4206 #size-cells = <0>; 4207 4208 status = "disabled"; 4209 4210 cci0_i2c0: i2c-bus@0 { 4211 reg = <0>; 4212 clock-frequency = <1000000>; 4213 #address-cells = <1>; 4214 #size-cells = <0>; 4215 }; 4216 4217 cci0_i2c1: i2c-bus@1 { 4218 reg = <1>; 4219 clock-frequency = <1000000>; 4220 #address-cells = <1>; 4221 #size-cells = <0>; 4222 }; 4223 }; 4224 4225 cci1: cci@ac4b000 { 4226 compatible = "qcom,sc8280xp-cci", "qcom,msm8996-cci"; 4227 reg = <0 0x0ac4b000 0 0x1000>; 4228 4229 interrupts = <GIC_SPI 271 IRQ_TYPE_EDGE_RISING>; 4230 4231 clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>, 4232 <&camcc CAMCC_SLOW_AHB_CLK_SRC>, 4233 <&camcc CAMCC_CPAS_AHB_CLK>, 4234 <&camcc CAMCC_CCI_1_CLK>; 4235 clock-names = "camnoc_axi", 4236 "slow_ahb_src", 4237 "cpas_ahb", 4238 "cci"; 4239 4240 power-domains = <&camcc TITAN_TOP_GDSC>; 4241 4242 pinctrl-0 = <&cci1_default>; 4243 pinctrl-1 = <&cci1_sleep>; 4244 pinctrl-names = "default", "sleep"; 4245 4246 #address-cells = <1>; 4247 #size-cells = <0>; 4248 4249 status = "disabled"; 4250 4251 cci1_i2c0: i2c-bus@0 { 4252 reg = <0>; 4253 clock-frequency = <1000000>; 4254 #address-cells = <1>; 4255 #size-cells = <0>; 4256 }; 4257 4258 cci1_i2c1: i2c-bus@1 { 4259 reg = <1>; 4260 clock-frequency = <1000000>; 4261 #address-cells = <1>; 4262 #size-cells = <0>; 4263 }; 4264 }; 4265 4266 cci2: cci@ac4c000 { 4267 compatible = "qcom,sc8280xp-cci", "qcom,msm8996-cci"; 4268 reg = <0 0x0ac4c000 0 0x1000>; 4269 4270 interrupts = <GIC_SPI 651 IRQ_TYPE_EDGE_RISING>; 4271 4272 clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>, 4273 <&camcc CAMCC_SLOW_AHB_CLK_SRC>, 4274 <&camcc CAMCC_CPAS_AHB_CLK>, 4275 <&camcc CAMCC_CCI_2_CLK>; 4276 clock-names = "camnoc_axi", 4277 "slow_ahb_src", 4278 "cpas_ahb", 4279 "cci"; 4280 power-domains = <&camcc TITAN_TOP_GDSC>; 4281 4282 pinctrl-0 = <&cci2_default>; 4283 pinctrl-1 = <&cci2_sleep>; 4284 pinctrl-names = "default", "sleep"; 4285 4286 #address-cells = <1>; 4287 #size-cells = <0>; 4288 4289 status = "disabled"; 4290 4291 cci2_i2c0: i2c-bus@0 { 4292 reg = <0>; 4293 clock-frequency = <1000000>; 4294 #address-cells = <1>; 4295 #size-cells = <0>; 4296 }; 4297 4298 cci2_i2c1: i2c-bus@1 { 4299 reg = <1>; 4300 clock-frequency = <1000000>; 4301 #address-cells = <1>; 4302 #size-cells = <0>; 4303 }; 4304 }; 4305 4306 cci3: cci@ac4d000 { 4307 compatible = "qcom,sc8280xp-cci", "qcom,msm8996-cci"; 4308 reg = <0 0x0ac4d000 0 0x1000>; 4309 4310 interrupts = <GIC_SPI 650 IRQ_TYPE_EDGE_RISING>; 4311 4312 clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>, 4313 <&camcc CAMCC_SLOW_AHB_CLK_SRC>, 4314 <&camcc CAMCC_CPAS_AHB_CLK>, 4315 <&camcc CAMCC_CCI_3_CLK>; 4316 clock-names = "camnoc_axi", 4317 "slow_ahb_src", 4318 "cpas_ahb", 4319 "cci"; 4320 4321 power-domains = <&camcc TITAN_TOP_GDSC>; 4322 4323 pinctrl-0 = <&cci3_default>; 4324 pinctrl-1 = <&cci3_sleep>; 4325 pinctrl-names = "default", "sleep"; 4326 4327 #address-cells = <1>; 4328 #size-cells = <0>; 4329 4330 status = "disabled"; 4331 4332 cci3_i2c0: i2c-bus@0 { 4333 reg = <0>; 4334 clock-frequency = <1000000>; 4335 #address-cells = <1>; 4336 #size-cells = <0>; 4337 }; 4338 4339 cci3_i2c1: i2c-bus@1 { 4340 reg = <1>; 4341 clock-frequency = <1000000>; 4342 #address-cells = <1>; 4343 #size-cells = <0>; 4344 }; 4345 }; 4346 4347 camss: camss@ac5a000 { 4348 compatible = "qcom,sc8280xp-camss"; 4349 4350 reg = <0 0x0ac5a000 0 0x2000>, 4351 <0 0x0ac5c000 0 0x2000>, 4352 <0 0x0ac65000 0 0x2000>, 4353 <0 0x0ac67000 0 0x2000>, 4354 <0 0x0acaf000 0 0x4000>, 4355 <0 0x0acb3000 0 0x1000>, 4356 <0 0x0acb6000 0 0x4000>, 4357 <0 0x0acba000 0 0x1000>, 4358 <0 0x0acbd000 0 0x4000>, 4359 <0 0x0acc1000 0 0x1000>, 4360 <0 0x0acc4000 0 0x4000>, 4361 <0 0x0acc8000 0 0x1000>, 4362 <0 0x0accb000 0 0x4000>, 4363 <0 0x0accf000 0 0x1000>, 4364 <0 0x0acd2000 0 0x4000>, 4365 <0 0x0acd6000 0 0x1000>, 4366 <0 0x0acd9000 0 0x4000>, 4367 <0 0x0acdd000 0 0x1000>, 4368 <0 0x0ace0000 0 0x4000>, 4369 <0 0x0ace4000 0 0x1000>; 4370 reg-names = "csiphy2", 4371 "csiphy3", 4372 "csiphy0", 4373 "csiphy1", 4374 "vfe0", 4375 "csid0", 4376 "vfe1", 4377 "csid1", 4378 "vfe2", 4379 "csid2", 4380 "vfe_lite0", 4381 "csid0_lite", 4382 "vfe_lite1", 4383 "csid1_lite", 4384 "vfe_lite2", 4385 "csid2_lite", 4386 "vfe_lite3", 4387 "csid3_lite", 4388 "vfe3", 4389 "csid3"; 4390 4391 interrupts = <GIC_SPI 359 IRQ_TYPE_EDGE_RISING>, 4392 <GIC_SPI 360 IRQ_TYPE_EDGE_RISING>, 4393 <GIC_SPI 448 IRQ_TYPE_EDGE_RISING>, 4394 <GIC_SPI 464 IRQ_TYPE_EDGE_RISING>, 4395 <GIC_SPI 465 IRQ_TYPE_EDGE_RISING>, 4396 <GIC_SPI 466 IRQ_TYPE_EDGE_RISING>, 4397 <GIC_SPI 467 IRQ_TYPE_EDGE_RISING>, 4398 <GIC_SPI 468 IRQ_TYPE_EDGE_RISING>, 4399 <GIC_SPI 469 IRQ_TYPE_EDGE_RISING>, 4400 <GIC_SPI 477 IRQ_TYPE_EDGE_RISING>, 4401 <GIC_SPI 478 IRQ_TYPE_EDGE_RISING>, 4402 <GIC_SPI 479 IRQ_TYPE_EDGE_RISING>, 4403 <GIC_SPI 640 IRQ_TYPE_EDGE_RISING>, 4404 <GIC_SPI 641 IRQ_TYPE_EDGE_RISING>, 4405 <GIC_SPI 758 IRQ_TYPE_EDGE_RISING>, 4406 <GIC_SPI 759 IRQ_TYPE_EDGE_RISING>, 4407 <GIC_SPI 760 IRQ_TYPE_EDGE_RISING>, 4408 <GIC_SPI 761 IRQ_TYPE_EDGE_RISING>, 4409 <GIC_SPI 762 IRQ_TYPE_EDGE_RISING>, 4410 <GIC_SPI 764 IRQ_TYPE_EDGE_RISING>; 4411 interrupt-names = "csid1_lite", 4412 "vfe_lite1", 4413 "csiphy3", 4414 "csid0", 4415 "vfe0", 4416 "csid1", 4417 "vfe1", 4418 "csid0_lite", 4419 "vfe_lite0", 4420 "csiphy0", 4421 "csiphy1", 4422 "csiphy2", 4423 "csid2", 4424 "vfe2", 4425 "csid3_lite", 4426 "csid2_lite", 4427 "vfe_lite3", 4428 "vfe_lite2", 4429 "csid3", 4430 "vfe3"; 4431 4432 power-domains = <&camcc IFE_0_GDSC>, 4433 <&camcc IFE_1_GDSC>, 4434 <&camcc IFE_2_GDSC>, 4435 <&camcc IFE_3_GDSC>, 4436 <&camcc TITAN_TOP_GDSC>; 4437 power-domain-names = "ife0", 4438 "ife1", 4439 "ife2", 4440 "ife3", 4441 "top"; 4442 4443 clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>, 4444 <&camcc CAMCC_CPAS_AHB_CLK>, 4445 <&camcc CAMCC_CSIPHY0_CLK>, 4446 <&camcc CAMCC_CSI0PHYTIMER_CLK>, 4447 <&camcc CAMCC_CSIPHY1_CLK>, 4448 <&camcc CAMCC_CSI1PHYTIMER_CLK>, 4449 <&camcc CAMCC_CSIPHY2_CLK>, 4450 <&camcc CAMCC_CSI2PHYTIMER_CLK>, 4451 <&camcc CAMCC_CSIPHY3_CLK>, 4452 <&camcc CAMCC_CSI3PHYTIMER_CLK>, 4453 <&camcc CAMCC_IFE_0_AXI_CLK>, 4454 <&camcc CAMCC_IFE_0_CLK>, 4455 <&camcc CAMCC_IFE_0_CPHY_RX_CLK>, 4456 <&camcc CAMCC_IFE_0_CSID_CLK>, 4457 <&camcc CAMCC_IFE_1_AXI_CLK>, 4458 <&camcc CAMCC_IFE_1_CLK>, 4459 <&camcc CAMCC_IFE_1_CPHY_RX_CLK>, 4460 <&camcc CAMCC_IFE_1_CSID_CLK>, 4461 <&camcc CAMCC_IFE_2_AXI_CLK>, 4462 <&camcc CAMCC_IFE_2_CLK>, 4463 <&camcc CAMCC_IFE_2_CPHY_RX_CLK>, 4464 <&camcc CAMCC_IFE_2_CSID_CLK>, 4465 <&camcc CAMCC_IFE_3_AXI_CLK>, 4466 <&camcc CAMCC_IFE_3_CLK>, 4467 <&camcc CAMCC_IFE_3_CPHY_RX_CLK>, 4468 <&camcc CAMCC_IFE_3_CSID_CLK>, 4469 <&camcc CAMCC_IFE_LITE_0_CLK>, 4470 <&camcc CAMCC_IFE_LITE_0_CPHY_RX_CLK>, 4471 <&camcc CAMCC_IFE_LITE_0_CSID_CLK>, 4472 <&camcc CAMCC_IFE_LITE_1_CLK>, 4473 <&camcc CAMCC_IFE_LITE_1_CPHY_RX_CLK>, 4474 <&camcc CAMCC_IFE_LITE_1_CSID_CLK>, 4475 <&camcc CAMCC_IFE_LITE_2_CLK>, 4476 <&camcc CAMCC_IFE_LITE_2_CPHY_RX_CLK>, 4477 <&camcc CAMCC_IFE_LITE_2_CSID_CLK>, 4478 <&camcc CAMCC_IFE_LITE_3_CLK>, 4479 <&camcc CAMCC_IFE_LITE_3_CPHY_RX_CLK>, 4480 <&camcc CAMCC_IFE_LITE_3_CSID_CLK>, 4481 <&gcc GCC_CAMERA_HF_AXI_CLK>, 4482 <&gcc GCC_CAMERA_SF_AXI_CLK>; 4483 clock-names = "camnoc_axi", 4484 "cpas_ahb", 4485 "csiphy0", 4486 "csiphy0_timer", 4487 "csiphy1", 4488 "csiphy1_timer", 4489 "csiphy2", 4490 "csiphy2_timer", 4491 "csiphy3", 4492 "csiphy3_timer", 4493 "vfe0_axi", 4494 "vfe0", 4495 "vfe0_cphy_rx", 4496 "vfe0_csid", 4497 "vfe1_axi", 4498 "vfe1", 4499 "vfe1_cphy_rx", 4500 "vfe1_csid", 4501 "vfe2_axi", 4502 "vfe2", 4503 "vfe2_cphy_rx", 4504 "vfe2_csid", 4505 "vfe3_axi", 4506 "vfe3", 4507 "vfe3_cphy_rx", 4508 "vfe3_csid", 4509 "vfe_lite0", 4510 "vfe_lite0_cphy_rx", 4511 "vfe_lite0_csid", 4512 "vfe_lite1", 4513 "vfe_lite1_cphy_rx", 4514 "vfe_lite1_csid", 4515 "vfe_lite2", 4516 "vfe_lite2_cphy_rx", 4517 "vfe_lite2_csid", 4518 "vfe_lite3", 4519 "vfe_lite3_cphy_rx", 4520 "vfe_lite3_csid", 4521 "gcc_axi_hf", 4522 "gcc_axi_sf"; 4523 4524 iommus = <&apps_smmu 0x2000 0x4e0>, 4525 <&apps_smmu 0x2020 0x4e0>, 4526 <&apps_smmu 0x2040 0x4e0>, 4527 <&apps_smmu 0x2060 0x4e0>, 4528 <&apps_smmu 0x2080 0x4e0>, 4529 <&apps_smmu 0x20e0 0x4e0>, 4530 <&apps_smmu 0x20c0 0x4e0>, 4531 <&apps_smmu 0x20a0 0x4e0>, 4532 <&apps_smmu 0x2400 0x4e0>, 4533 <&apps_smmu 0x2420 0x4e0>, 4534 <&apps_smmu 0x2440 0x4e0>, 4535 <&apps_smmu 0x2460 0x4e0>, 4536 <&apps_smmu 0x2480 0x4e0>, 4537 <&apps_smmu 0x24e0 0x4e0>, 4538 <&apps_smmu 0x24c0 0x4e0>, 4539 <&apps_smmu 0x24a0 0x4e0>; 4540 4541 interconnects = <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_CAMERA_CFG 0>, 4542 <&mmss_noc MASTER_CAMNOC_HF 0 &mc_virt SLAVE_EBI1 0>, 4543 <&mmss_noc MASTER_CAMNOC_SF 0 &mc_virt SLAVE_EBI1 0>, 4544 <&mmss_noc MASTER_CAMNOC_ICP 0 &mc_virt SLAVE_EBI1 0>; 4545 interconnect-names = "cam_ahb", 4546 "cam_hf_mnoc", 4547 "cam_sf_mnoc", 4548 "cam_sf_icp_mnoc"; 4549 4550 status = "disabled"; 4551 4552 ports { 4553 #address-cells = <1>; 4554 #size-cells = <0>; 4555 4556 port@0 { 4557 reg = <0>; 4558 #address-cells = <1>; 4559 #size-cells = <0>; 4560 }; 4561 4562 port@1 { 4563 reg = <1>; 4564 #address-cells = <1>; 4565 #size-cells = <0>; 4566 }; 4567 4568 port@2 { 4569 reg = <2>; 4570 #address-cells = <1>; 4571 #size-cells = <0>; 4572 }; 4573 4574 port@3 { 4575 reg = <3>; 4576 #address-cells = <1>; 4577 #size-cells = <0>; 4578 }; 4579 }; 4580 }; 4581 4582 camcc: clock-controller@ad00000 { 4583 compatible = "qcom,sc8280xp-camcc"; 4584 reg = <0 0x0ad00000 0 0x20000>; 4585 clocks = <&gcc GCC_CAMERA_AHB_CLK>, 4586 <&rpmhcc RPMH_CXO_CLK>, 4587 <&rpmhcc RPMH_CXO_CLK_A>, 4588 <&sleep_clk>; 4589 power-domains = <&rpmhpd SC8280XP_MMCX>; 4590 required-opps = <&rpmhpd_opp_low_svs>; 4591 #clock-cells = <1>; 4592 #reset-cells = <1>; 4593 #power-domain-cells = <1>; 4594 }; 4595 4596 mdss0: display-subsystem@ae00000 { 4597 compatible = "qcom,sc8280xp-mdss"; 4598 reg = <0 0x0ae00000 0 0x1000>; 4599 reg-names = "mdss"; 4600 4601 clocks = <&gcc GCC_DISP_AHB_CLK>, 4602 <&dispcc0 DISP_CC_MDSS_AHB_CLK>, 4603 <&dispcc0 DISP_CC_MDSS_MDP_CLK>; 4604 clock-names = "iface", 4605 "ahb", 4606 "core"; 4607 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 4608 interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>, 4609 <&mmss_noc MASTER_MDP1 0 &mc_virt SLAVE_EBI1 0>; 4610 interconnect-names = "mdp0-mem", "mdp1-mem"; 4611 iommus = <&apps_smmu 0x1000 0x402>; 4612 power-domains = <&dispcc0 MDSS_GDSC>; 4613 resets = <&dispcc0 DISP_CC_MDSS_CORE_BCR>; 4614 4615 interrupt-controller; 4616 #interrupt-cells = <1>; 4617 #address-cells = <2>; 4618 #size-cells = <2>; 4619 ranges; 4620 4621 status = "disabled"; 4622 4623 mdss0_mdp: display-controller@ae01000 { 4624 compatible = "qcom,sc8280xp-dpu"; 4625 reg = <0 0x0ae01000 0 0x8f000>, 4626 <0 0x0aeb0000 0 0x3000>; 4627 reg-names = "mdp", "vbif"; 4628 4629 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 4630 <&gcc GCC_DISP_SF_AXI_CLK>, 4631 <&dispcc0 DISP_CC_MDSS_AHB_CLK>, 4632 <&dispcc0 DISP_CC_MDSS_MDP_LUT_CLK>, 4633 <&dispcc0 DISP_CC_MDSS_MDP_CLK>, 4634 <&dispcc0 DISP_CC_MDSS_VSYNC_CLK>; 4635 clock-names = "bus", 4636 "nrt_bus", 4637 "iface", 4638 "lut", 4639 "core", 4640 "vsync"; 4641 interrupt-parent = <&mdss0>; 4642 interrupts = <0>; 4643 power-domains = <&rpmhpd SC8280XP_MMCX>; 4644 4645 assigned-clocks = <&dispcc0 DISP_CC_MDSS_VSYNC_CLK>; 4646 assigned-clock-rates = <19200000>; 4647 operating-points-v2 = <&mdss0_mdp_opp_table>; 4648 4649 ports { 4650 #address-cells = <1>; 4651 #size-cells = <0>; 4652 4653 port@0 { 4654 reg = <0>; 4655 mdss0_intf0_out: endpoint { 4656 remote-endpoint = <&mdss0_dp0_in>; 4657 }; 4658 }; 4659 4660 port@4 { 4661 reg = <4>; 4662 mdss0_intf4_out: endpoint { 4663 remote-endpoint = <&mdss0_dp1_in>; 4664 }; 4665 }; 4666 4667 port@5 { 4668 reg = <5>; 4669 mdss0_intf5_out: endpoint { 4670 remote-endpoint = <&mdss0_dp3_in>; 4671 }; 4672 }; 4673 4674 port@6 { 4675 reg = <6>; 4676 mdss0_intf6_out: endpoint { 4677 remote-endpoint = <&mdss0_dp2_in>; 4678 }; 4679 }; 4680 }; 4681 4682 mdss0_mdp_opp_table: opp-table { 4683 compatible = "operating-points-v2"; 4684 4685 opp-200000000 { 4686 opp-hz = /bits/ 64 <200000000>; 4687 required-opps = <&rpmhpd_opp_low_svs>; 4688 }; 4689 4690 opp-300000000 { 4691 opp-hz = /bits/ 64 <300000000>; 4692 required-opps = <&rpmhpd_opp_svs>; 4693 }; 4694 4695 opp-375000000 { 4696 opp-hz = /bits/ 64 <375000000>; 4697 required-opps = <&rpmhpd_opp_svs_l1>; 4698 }; 4699 4700 opp-500000000 { 4701 opp-hz = /bits/ 64 <500000000>; 4702 required-opps = <&rpmhpd_opp_nom>; 4703 }; 4704 opp-600000000 { 4705 opp-hz = /bits/ 64 <600000000>; 4706 required-opps = <&rpmhpd_opp_turbo_l1>; 4707 }; 4708 }; 4709 }; 4710 4711 mdss0_dp0: displayport-controller@ae90000 { 4712 compatible = "qcom,sc8280xp-dp"; 4713 reg = <0 0xae90000 0 0x200>, 4714 <0 0xae90200 0 0x200>, 4715 <0 0xae90400 0 0x600>, 4716 <0 0xae91000 0 0x400>, 4717 <0 0xae91400 0 0x400>; 4718 interrupt-parent = <&mdss0>; 4719 interrupts = <12>; 4720 clocks = <&dispcc0 DISP_CC_MDSS_AHB_CLK>, 4721 <&dispcc0 DISP_CC_MDSS_DPTX0_AUX_CLK>, 4722 <&dispcc0 DISP_CC_MDSS_DPTX0_LINK_CLK>, 4723 <&dispcc0 DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, 4724 <&dispcc0 DISP_CC_MDSS_DPTX0_PIXEL0_CLK>, 4725 <&dispcc0 DISP_CC_MDSS_DPTX0_PIXEL1_CLK>; 4726 clock-names = "core_iface", "core_aux", 4727 "ctrl_link", 4728 "ctrl_link_iface", 4729 "stream_pixel", 4730 "stream_1_pixel"; 4731 4732 assigned-clocks = <&dispcc0 DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, 4733 <&dispcc0 DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>, 4734 <&dispcc0 DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>; 4735 assigned-clock-parents = <&usb_0_qmpphy QMP_USB43DP_DP_LINK_CLK>, 4736 <&usb_0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 4737 <&usb_0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 4738 4739 phys = <&usb_0_qmpphy QMP_USB43DP_DP_PHY>; 4740 phy-names = "dp"; 4741 4742 #sound-dai-cells = <0>; 4743 4744 operating-points-v2 = <&mdss0_dp0_opp_table>; 4745 power-domains = <&rpmhpd SC8280XP_MMCX>; 4746 4747 status = "disabled"; 4748 4749 ports { 4750 #address-cells = <1>; 4751 #size-cells = <0>; 4752 4753 port@0 { 4754 reg = <0>; 4755 4756 mdss0_dp0_in: endpoint { 4757 remote-endpoint = <&mdss0_intf0_out>; 4758 }; 4759 }; 4760 4761 port@1 { 4762 reg = <1>; 4763 4764 mdss0_dp0_out: endpoint { 4765 }; 4766 }; 4767 }; 4768 4769 mdss0_dp0_opp_table: opp-table { 4770 compatible = "operating-points-v2"; 4771 4772 opp-160000000 { 4773 opp-hz = /bits/ 64 <160000000>; 4774 required-opps = <&rpmhpd_opp_low_svs>; 4775 }; 4776 4777 opp-270000000 { 4778 opp-hz = /bits/ 64 <270000000>; 4779 required-opps = <&rpmhpd_opp_svs>; 4780 }; 4781 4782 opp-540000000 { 4783 opp-hz = /bits/ 64 <540000000>; 4784 required-opps = <&rpmhpd_opp_svs_l1>; 4785 }; 4786 4787 opp-810000000 { 4788 opp-hz = /bits/ 64 <810000000>; 4789 required-opps = <&rpmhpd_opp_nom>; 4790 }; 4791 }; 4792 }; 4793 4794 mdss0_dp1: displayport-controller@ae98000 { 4795 compatible = "qcom,sc8280xp-dp"; 4796 reg = <0 0xae98000 0 0x200>, 4797 <0 0xae98200 0 0x200>, 4798 <0 0xae98400 0 0x600>, 4799 <0 0xae99000 0 0x400>, 4800 <0 0xae99400 0 0x400>; 4801 interrupt-parent = <&mdss0>; 4802 interrupts = <13>; 4803 clocks = <&dispcc0 DISP_CC_MDSS_AHB_CLK>, 4804 <&dispcc0 DISP_CC_MDSS_DPTX1_AUX_CLK>, 4805 <&dispcc0 DISP_CC_MDSS_DPTX1_LINK_CLK>, 4806 <&dispcc0 DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>, 4807 <&dispcc0 DISP_CC_MDSS_DPTX1_PIXEL0_CLK>, 4808 <&dispcc0 DISP_CC_MDSS_DPTX1_PIXEL1_CLK>; 4809 clock-names = "core_iface", "core_aux", 4810 "ctrl_link", 4811 "ctrl_link_iface", "stream_pixel", 4812 "stream_1_pixel"; 4813 4814 assigned-clocks = <&dispcc0 DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>, 4815 <&dispcc0 DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>, 4816 <&dispcc0 DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC>; 4817 assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 4818 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 4819 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 4820 4821 phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>; 4822 phy-names = "dp"; 4823 4824 #sound-dai-cells = <0>; 4825 4826 operating-points-v2 = <&mdss0_dp1_opp_table>; 4827 power-domains = <&rpmhpd SC8280XP_MMCX>; 4828 4829 status = "disabled"; 4830 4831 ports { 4832 #address-cells = <1>; 4833 #size-cells = <0>; 4834 4835 port@0 { 4836 reg = <0>; 4837 4838 mdss0_dp1_in: endpoint { 4839 remote-endpoint = <&mdss0_intf4_out>; 4840 }; 4841 }; 4842 4843 port@1 { 4844 reg = <1>; 4845 4846 mdss0_dp1_out: endpoint { 4847 }; 4848 }; 4849 }; 4850 4851 mdss0_dp1_opp_table: opp-table { 4852 compatible = "operating-points-v2"; 4853 4854 opp-160000000 { 4855 opp-hz = /bits/ 64 <160000000>; 4856 required-opps = <&rpmhpd_opp_low_svs>; 4857 }; 4858 4859 opp-270000000 { 4860 opp-hz = /bits/ 64 <270000000>; 4861 required-opps = <&rpmhpd_opp_svs>; 4862 }; 4863 4864 opp-540000000 { 4865 opp-hz = /bits/ 64 <540000000>; 4866 required-opps = <&rpmhpd_opp_svs_l1>; 4867 }; 4868 4869 opp-810000000 { 4870 opp-hz = /bits/ 64 <810000000>; 4871 required-opps = <&rpmhpd_opp_nom>; 4872 }; 4873 }; 4874 }; 4875 4876 mdss0_dp2: displayport-controller@ae9a000 { 4877 compatible = "qcom,sc8280xp-dp"; 4878 reg = <0 0xae9a000 0 0x200>, 4879 <0 0xae9a200 0 0x200>, 4880 <0 0xae9a400 0 0x600>, 4881 <0 0xae9b000 0 0x400>, 4882 <0 0xae9b400 0 0x400>; 4883 4884 clocks = <&dispcc0 DISP_CC_MDSS_AHB_CLK>, 4885 <&dispcc0 DISP_CC_MDSS_DPTX2_AUX_CLK>, 4886 <&dispcc0 DISP_CC_MDSS_DPTX2_LINK_CLK>, 4887 <&dispcc0 DISP_CC_MDSS_DPTX2_LINK_INTF_CLK>, 4888 <&dispcc0 DISP_CC_MDSS_DPTX2_PIXEL0_CLK>, 4889 <&dispcc0 DISP_CC_MDSS_DPTX2_PIXEL1_CLK>; 4890 clock-names = "core_iface", "core_aux", 4891 "ctrl_link", 4892 "ctrl_link_iface", "stream_pixel", 4893 "stream_1_pixel"; 4894 interrupt-parent = <&mdss0>; 4895 interrupts = <14>; 4896 phys = <&mdss0_dp2_phy>; 4897 phy-names = "dp"; 4898 power-domains = <&rpmhpd SC8280XP_MMCX>; 4899 4900 assigned-clocks = <&dispcc0 DISP_CC_MDSS_DPTX2_LINK_CLK_SRC>, 4901 <&dispcc0 DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC>, 4902 <&dispcc0 DISP_CC_MDSS_DPTX2_PIXEL1_CLK_SRC>; 4903 assigned-clock-parents = <&mdss0_dp2_phy 0>, 4904 <&mdss0_dp2_phy 1>, 4905 <&mdss0_dp2_phy 1>; 4906 operating-points-v2 = <&mdss0_dp2_opp_table>; 4907 4908 #sound-dai-cells = <0>; 4909 4910 status = "disabled"; 4911 4912 ports { 4913 #address-cells = <1>; 4914 #size-cells = <0>; 4915 4916 port@0 { 4917 reg = <0>; 4918 mdss0_dp2_in: endpoint { 4919 remote-endpoint = <&mdss0_intf6_out>; 4920 }; 4921 }; 4922 4923 port@1 { 4924 reg = <1>; 4925 4926 mdss0_dp2_out: endpoint { 4927 }; 4928 }; 4929 }; 4930 4931 mdss0_dp2_opp_table: opp-table { 4932 compatible = "operating-points-v2"; 4933 4934 opp-160000000 { 4935 opp-hz = /bits/ 64 <160000000>; 4936 required-opps = <&rpmhpd_opp_low_svs>; 4937 }; 4938 4939 opp-270000000 { 4940 opp-hz = /bits/ 64 <270000000>; 4941 required-opps = <&rpmhpd_opp_svs>; 4942 }; 4943 4944 opp-540000000 { 4945 opp-hz = /bits/ 64 <540000000>; 4946 required-opps = <&rpmhpd_opp_svs_l1>; 4947 }; 4948 4949 opp-810000000 { 4950 opp-hz = /bits/ 64 <810000000>; 4951 required-opps = <&rpmhpd_opp_nom>; 4952 }; 4953 }; 4954 }; 4955 4956 mdss0_dp3: displayport-controller@aea0000 { 4957 compatible = "qcom,sc8280xp-dp"; 4958 reg = <0 0xaea0000 0 0x200>, 4959 <0 0xaea0200 0 0x200>, 4960 <0 0xaea0400 0 0x600>, 4961 <0 0xaea1000 0 0x400>, 4962 <0 0xaea1400 0 0x400>; 4963 4964 clocks = <&dispcc0 DISP_CC_MDSS_AHB_CLK>, 4965 <&dispcc0 DISP_CC_MDSS_DPTX3_AUX_CLK>, 4966 <&dispcc0 DISP_CC_MDSS_DPTX3_LINK_CLK>, 4967 <&dispcc0 DISP_CC_MDSS_DPTX3_LINK_INTF_CLK>, 4968 <&dispcc0 DISP_CC_MDSS_DPTX3_PIXEL0_CLK>; 4969 clock-names = "core_iface", "core_aux", 4970 "ctrl_link", 4971 "ctrl_link_iface", "stream_pixel"; 4972 interrupt-parent = <&mdss0>; 4973 interrupts = <15>; 4974 phys = <&mdss0_dp3_phy>; 4975 phy-names = "dp"; 4976 power-domains = <&rpmhpd SC8280XP_MMCX>; 4977 4978 assigned-clocks = <&dispcc0 DISP_CC_MDSS_DPTX3_LINK_CLK_SRC>, 4979 <&dispcc0 DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC>; 4980 assigned-clock-parents = <&mdss0_dp3_phy 0>, <&mdss0_dp3_phy 1>; 4981 operating-points-v2 = <&mdss0_dp3_opp_table>; 4982 4983 #sound-dai-cells = <0>; 4984 4985 status = "disabled"; 4986 4987 ports { 4988 #address-cells = <1>; 4989 #size-cells = <0>; 4990 4991 port@0 { 4992 reg = <0>; 4993 mdss0_dp3_in: endpoint { 4994 remote-endpoint = <&mdss0_intf5_out>; 4995 }; 4996 }; 4997 4998 port@1 { 4999 reg = <1>; 5000 5001 mdss0_dp3_out: endpoint { 5002 }; 5003 }; 5004 }; 5005 5006 mdss0_dp3_opp_table: opp-table { 5007 compatible = "operating-points-v2"; 5008 5009 opp-160000000 { 5010 opp-hz = /bits/ 64 <160000000>; 5011 required-opps = <&rpmhpd_opp_low_svs>; 5012 }; 5013 5014 opp-270000000 { 5015 opp-hz = /bits/ 64 <270000000>; 5016 required-opps = <&rpmhpd_opp_svs>; 5017 }; 5018 5019 opp-540000000 { 5020 opp-hz = /bits/ 64 <540000000>; 5021 required-opps = <&rpmhpd_opp_svs_l1>; 5022 }; 5023 5024 opp-810000000 { 5025 opp-hz = /bits/ 64 <810000000>; 5026 required-opps = <&rpmhpd_opp_nom>; 5027 }; 5028 }; 5029 }; 5030 }; 5031 5032 mdss0_dp2_phy: phy@aec2a00 { 5033 compatible = "qcom,sc8280xp-dp-phy"; 5034 reg = <0 0x0aec2a00 0 0x19c>, 5035 <0 0x0aec2200 0 0xec>, 5036 <0 0x0aec2600 0 0xec>, 5037 <0 0x0aec2000 0 0x1c8>; 5038 5039 clocks = <&dispcc0 DISP_CC_MDSS_DPTX2_AUX_CLK>, 5040 <&dispcc0 DISP_CC_MDSS_AHB_CLK>; 5041 clock-names = "aux", "cfg_ahb"; 5042 power-domains = <&rpmhpd SC8280XP_MX>; 5043 5044 #clock-cells = <1>; 5045 #phy-cells = <0>; 5046 5047 status = "disabled"; 5048 }; 5049 5050 mdss0_dp3_phy: phy@aec5a00 { 5051 compatible = "qcom,sc8280xp-dp-phy"; 5052 reg = <0 0x0aec5a00 0 0x19c>, 5053 <0 0x0aec5200 0 0xec>, 5054 <0 0x0aec5600 0 0xec>, 5055 <0 0x0aec5000 0 0x1c8>; 5056 5057 clocks = <&dispcc0 DISP_CC_MDSS_DPTX3_AUX_CLK>, 5058 <&dispcc0 DISP_CC_MDSS_AHB_CLK>; 5059 clock-names = "aux", "cfg_ahb"; 5060 power-domains = <&rpmhpd SC8280XP_MX>; 5061 5062 #clock-cells = <1>; 5063 #phy-cells = <0>; 5064 5065 status = "disabled"; 5066 }; 5067 5068 dispcc0: clock-controller@af00000 { 5069 compatible = "qcom,sc8280xp-dispcc0"; 5070 reg = <0 0x0af00000 0 0x20000>; 5071 5072 clocks = <&gcc GCC_DISP_AHB_CLK>, 5073 <&rpmhcc RPMH_CXO_CLK>, 5074 <&sleep_clk>, 5075 <&usb_0_qmpphy QMP_USB43DP_DP_LINK_CLK>, 5076 <&usb_0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 5077 <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 5078 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 5079 <&mdss0_dp2_phy 0>, 5080 <&mdss0_dp2_phy 1>, 5081 <&mdss0_dp3_phy 0>, 5082 <&mdss0_dp3_phy 1>, 5083 <0>, 5084 <0>, 5085 <0>, 5086 <0>; 5087 power-domains = <&rpmhpd SC8280XP_MMCX>; 5088 5089 #clock-cells = <1>; 5090 #power-domain-cells = <1>; 5091 #reset-cells = <1>; 5092 5093 status = "disabled"; 5094 }; 5095 5096 pdc: interrupt-controller@b220000 { 5097 compatible = "qcom,sc8280xp-pdc", "qcom,pdc"; 5098 reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>; 5099 qcom,pdc-ranges = <0 480 40>, 5100 <40 140 14>, 5101 <54 263 1>, 5102 <55 306 4>, 5103 <59 312 3>, 5104 <62 374 2>, 5105 <64 434 2>, 5106 <66 438 3>, 5107 <69 86 1>, 5108 <70 520 54>, 5109 <124 609 28>, 5110 <159 638 1>, 5111 <160 720 8>, 5112 <168 801 1>, 5113 <169 728 30>, 5114 <199 416 2>, 5115 <201 449 1>, 5116 <202 89 1>, 5117 <203 451 1>, 5118 <204 462 1>, 5119 <205 264 1>, 5120 <206 579 1>, 5121 <207 653 1>, 5122 <208 656 1>, 5123 <209 659 1>, 5124 <210 122 1>, 5125 <211 699 1>, 5126 <212 705 1>, 5127 <213 450 1>, 5128 <214 643 1>, 5129 <216 646 5>, 5130 <221 390 5>, 5131 <226 700 3>, 5132 <229 240 3>, 5133 <232 269 1>, 5134 <233 377 1>, 5135 <234 372 1>, 5136 <235 138 1>, 5137 <236 857 1>, 5138 <237 860 1>, 5139 <238 137 1>, 5140 <239 668 1>, 5141 <240 366 1>, 5142 <241 949 1>, 5143 <242 815 5>, 5144 <247 769 1>, 5145 <248 768 1>, 5146 <249 663 1>, 5147 <250 799 2>, 5148 <252 798 1>, 5149 <253 765 1>, 5150 <254 763 1>, 5151 <255 454 1>, 5152 <258 139 1>, 5153 <259 786 2>, 5154 <261 370 2>, 5155 <263 158 2>; 5156 #interrupt-cells = <2>; 5157 interrupt-parent = <&intc>; 5158 interrupt-controller; 5159 }; 5160 5161 tsens2: thermal-sensor@c251000 { 5162 compatible = "qcom,sc8280xp-tsens", "qcom,tsens-v2"; 5163 reg = <0 0x0c251000 0 0x1ff>, 5164 <0 0x0c224000 0 0x8>; 5165 #qcom,sensors = <11>; 5166 interrupts-extended = <&pdc 122 IRQ_TYPE_LEVEL_HIGH>, 5167 <&pdc 124 IRQ_TYPE_LEVEL_HIGH>; 5168 interrupt-names = "uplow", "critical"; 5169 #thermal-sensor-cells = <1>; 5170 }; 5171 5172 tsens3: thermal-sensor@c252000 { 5173 compatible = "qcom,sc8280xp-tsens", "qcom,tsens-v2"; 5174 reg = <0 0x0c252000 0 0x1ff>, 5175 <0 0x0c225000 0 0x8>; 5176 #qcom,sensors = <5>; 5177 interrupts-extended = <&pdc 123 IRQ_TYPE_LEVEL_HIGH>, 5178 <&pdc 125 IRQ_TYPE_LEVEL_HIGH>; 5179 interrupt-names = "uplow", "critical"; 5180 #thermal-sensor-cells = <1>; 5181 }; 5182 5183 tsens0: thermal-sensor@c263000 { 5184 compatible = "qcom,sc8280xp-tsens", "qcom,tsens-v2"; 5185 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 5186 <0 0x0c222000 0 0x8>; /* SROT */ 5187 #qcom,sensors = <14>; 5188 interrupts-extended = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>, 5189 <&pdc 28 IRQ_TYPE_LEVEL_HIGH>; 5190 interrupt-names = "uplow", "critical"; 5191 #thermal-sensor-cells = <1>; 5192 }; 5193 5194 restart@c264000 { 5195 compatible = "qcom,pshold"; 5196 reg = <0 0x0c264000 0 0x4>; 5197 /* TZ seems to block access */ 5198 status = "reserved"; 5199 }; 5200 5201 tsens1: thermal-sensor@c265000 { 5202 compatible = "qcom,sc8280xp-tsens", "qcom,tsens-v2"; 5203 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 5204 <0 0x0c223000 0 0x8>; /* SROT */ 5205 #qcom,sensors = <16>; 5206 interrupts-extended = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>, 5207 <&pdc 29 IRQ_TYPE_LEVEL_HIGH>; 5208 interrupt-names = "uplow", "critical"; 5209 #thermal-sensor-cells = <1>; 5210 }; 5211 5212 aoss_qmp: power-management@c300000 { 5213 compatible = "qcom,sc8280xp-aoss-qmp", "qcom,aoss-qmp"; 5214 reg = <0 0x0c300000 0 0x400>; 5215 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP IRQ_TYPE_EDGE_RISING>; 5216 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; 5217 5218 #clock-cells = <0>; 5219 }; 5220 5221 sram@c3f0000 { 5222 compatible = "qcom,rpmh-stats"; 5223 reg = <0 0x0c3f0000 0 0x400>; 5224 qcom,qmp = <&aoss_qmp>; 5225 }; 5226 5227 spmi_bus: spmi@c440000 { 5228 compatible = "qcom,spmi-pmic-arb"; 5229 reg = <0 0x0c440000 0 0x1100>, 5230 <0 0x0c600000 0 0x2000000>, 5231 <0 0x0e600000 0 0x100000>, 5232 <0 0x0e700000 0 0xa0000>, 5233 <0 0x0c40a000 0 0x26000>; 5234 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 5235 interrupt-names = "periph_irq"; 5236 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 5237 qcom,ee = <0>; 5238 qcom,channel = <0>; 5239 #address-cells = <2>; 5240 #size-cells = <0>; 5241 interrupt-controller; 5242 #interrupt-cells = <4>; 5243 }; 5244 5245 tlmm: pinctrl@f100000 { 5246 compatible = "qcom,sc8280xp-tlmm"; 5247 reg = <0 0x0f100000 0 0x300000>; 5248 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 5249 gpio-controller; 5250 #gpio-cells = <2>; 5251 interrupt-controller; 5252 #interrupt-cells = <2>; 5253 gpio-ranges = <&tlmm 0 0 230>; 5254 wakeup-parent = <&pdc>; 5255 5256 cci0_default: cci0-default-state { 5257 cci0_i2c0_default: cci0-i2c0-default-pins { 5258 /* cci_i2c_sda0, cci_i2c_scl0 */ 5259 pins = "gpio113", "gpio114"; 5260 function = "cci_i2c"; 5261 drive-strength = <2>; 5262 bias-pull-up; 5263 }; 5264 5265 cci0_i2c1_default: cci0-i2c1-default-pins { 5266 /* cci_i2c_sda1, cci_i2c_scl1 */ 5267 pins = "gpio115", "gpio116"; 5268 function = "cci_i2c"; 5269 drive-strength = <2>; 5270 bias-pull-up; 5271 }; 5272 }; 5273 5274 cci0_sleep: cci0-sleep-state { 5275 cci0_i2c0_sleep: cci0-i2c0-sleep-pins { 5276 /* cci_i2c_sda0, cci_i2c_scl0 */ 5277 pins = "gpio113", "gpio114"; 5278 function = "cci_i2c"; 5279 drive-strength = <2>; 5280 bias-pull-down; 5281 }; 5282 5283 cci0_i2c1_sleep: cci0-i2c1-sleep-pins { 5284 /* cci_i2c_sda1, cci_i2c_scl1 */ 5285 pins = "gpio115", "gpio116"; 5286 function = "cci_i2c"; 5287 drive-strength = <2>; 5288 bias-pull-down; 5289 }; 5290 }; 5291 5292 cci1_default: cci1-default-state { 5293 cci1_i2c0_default: cci1-i2c0-default-pins { 5294 /* cci_i2c_sda2, cci_i2c_scl2 */ 5295 pins = "gpio10","gpio11"; 5296 function = "cci_i2c"; 5297 drive-strength = <2>; 5298 bias-pull-up; 5299 }; 5300 5301 cci1_i2c1_default: cci1-i2c1-default-pins { 5302 /* cci_i2c_sda3, cci_i2c_scl3 */ 5303 pins = "gpio123","gpio124"; 5304 function = "cci_i2c"; 5305 drive-strength = <2>; 5306 bias-pull-up; 5307 }; 5308 }; 5309 5310 cci1_sleep: cci1-sleep-state { 5311 cci1_i2c0_sleep: cci1-i2c0-sleep-pins { 5312 /* cci_i2c_sda2, cci_i2c_scl2 */ 5313 pins = "gpio10","gpio11"; 5314 function = "cci_i2c"; 5315 drive-strength = <2>; 5316 bias-pull-down; 5317 }; 5318 5319 cci1_i2c1_sleep: cci1-i2c1-sleep-pins { 5320 /* cci_i2c_sda3, cci_i2c_scl3 */ 5321 pins = "gpio123","gpio124"; 5322 function = "cci_i2c"; 5323 drive-strength = <2>; 5324 bias-pull-down; 5325 }; 5326 }; 5327 5328 cci2_default: cci2-default-state { 5329 cci2_i2c0_default: cci2-i2c0-default-pins { 5330 /* cci_i2c_sda4, cci_i2c_scl4 */ 5331 pins = "gpio117","gpio118"; 5332 function = "cci_i2c"; 5333 drive-strength = <2>; 5334 bias-pull-up; 5335 }; 5336 5337 cci2_i2c1_default: cci2-i2c1-default-pins { 5338 /* cci_i2c_sda5, cci_i2c_scl5 */ 5339 pins = "gpio12","gpio13"; 5340 function = "cci_i2c"; 5341 drive-strength = <2>; 5342 bias-pull-up; 5343 }; 5344 }; 5345 5346 cci2_sleep: cci2-sleep-state { 5347 cci2_i2c0_sleep: cci2-i2c0-sleep-pins { 5348 /* cci_i2c_sda4, cci_i2c_scl4 */ 5349 pins = "gpio117","gpio118"; 5350 function = "cci_i2c"; 5351 drive-strength = <2>; 5352 bias-pull-down; 5353 }; 5354 5355 cci2_i2c1_sleep: cci2-i2c1-sleep-pins { 5356 /* cci_i2c_sda5, cci_i2c_scl5 */ 5357 pins = "gpio12","gpio13"; 5358 function = "cci_i2c"; 5359 drive-strength = <2>; 5360 bias-pull-down; 5361 }; 5362 }; 5363 5364 cci3_default: cci3-default-state { 5365 cci3_i2c0_default: cci3-i2c0-default-pins { 5366 /* cci_i2c_sda6, cci_i2c_scl6 */ 5367 pins = "gpio145","gpio146"; 5368 function = "cci_i2c"; 5369 drive-strength = <2>; 5370 bias-pull-up; 5371 }; 5372 5373 cci3_i2c1_default: cci3-i2c1-default-pins { 5374 /* cci_i2c_sda7, cci_i2c_scl7 */ 5375 pins = "gpio164","gpio165"; 5376 function = "cci_i2c"; 5377 drive-strength = <2>; 5378 bias-pull-up; 5379 }; 5380 }; 5381 5382 cci3_sleep: cci3-sleep-state { 5383 cci3_i2c0_sleep: cci3-i2c0-sleep-pins { 5384 /* cci_i2c_sda6, cci_i2c_scl6 */ 5385 pins = "gpio145","gpio146"; 5386 function = "cci_i2c"; 5387 drive-strength = <2>; 5388 bias-pull-down; 5389 }; 5390 5391 cci3_i2c1_sleep: cci3-i2c1-sleep-pins { 5392 /* cci_i2c_sda7, cci_i2c_scl7 */ 5393 pins = "gpio164","gpio165"; 5394 function = "cci_i2c"; 5395 drive-strength = <2>; 5396 bias-pull-down; 5397 }; 5398 }; 5399 5400 qup_uart18_default: qup-uart18-default-state { 5401 cts-pins { 5402 pins = "gpio66"; 5403 function = "qup18"; 5404 drive-strength = <2>; 5405 bias-disable; 5406 }; 5407 5408 rts-pins { 5409 pins = "gpio67"; 5410 function = "qup18"; 5411 drive-strength = <2>; 5412 bias-disable; 5413 }; 5414 5415 tx-pins { 5416 pins = "gpio68"; 5417 function = "qup18"; 5418 drive-strength = <2>; 5419 bias-disable; 5420 }; 5421 5422 rx-pins { 5423 pins = "gpio69"; 5424 function = "qup18"; 5425 drive-strength = <2>; 5426 bias-disable; 5427 }; 5428 }; 5429 }; 5430 5431 pcie_smmu: iommu@14f80000 { 5432 compatible = "arm,smmu-v3"; 5433 reg = <0 0x14f80000 0 0x80000>; 5434 #iommu-cells = <1>; 5435 interrupts = <GIC_SPI 951 IRQ_TYPE_EDGE_RISING>, 5436 <GIC_SPI 955 IRQ_TYPE_EDGE_RISING>, 5437 <GIC_SPI 953 IRQ_TYPE_EDGE_RISING>; 5438 interrupt-names = "eventq", 5439 "gerror", 5440 "cmdq-sync"; 5441 dma-coherent; 5442 status = "reserved"; /* Controlled by QHEE. */ 5443 }; 5444 5445 apps_smmu: iommu@15000000 { 5446 compatible = "qcom,sc8280xp-smmu-500", "arm,mmu-500"; 5447 reg = <0 0x15000000 0 0x100000>; 5448 #iommu-cells = <2>; 5449 #global-interrupts = <2>; 5450 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, 5451 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 5452 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 5453 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 5454 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 5455 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 5456 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 5457 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 5458 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 5459 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 5460 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 5461 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 5462 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 5463 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 5464 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 5465 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 5466 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 5467 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 5468 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 5469 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 5470 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 5471 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 5472 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 5473 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 5474 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 5475 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 5476 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 5477 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 5478 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 5479 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 5480 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 5481 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 5482 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 5483 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 5484 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 5485 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 5486 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 5487 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 5488 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 5489 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 5490 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 5491 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 5492 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 5493 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 5494 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 5495 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 5496 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 5497 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 5498 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 5499 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 5500 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 5501 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 5502 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 5503 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 5504 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 5505 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 5506 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 5507 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 5508 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 5509 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 5510 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 5511 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 5512 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 5513 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 5514 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 5515 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 5516 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 5517 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 5518 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 5519 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 5520 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 5521 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 5522 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 5523 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 5524 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 5525 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 5526 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 5527 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 5528 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 5529 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 5530 <GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH>, 5531 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 5532 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 5533 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 5534 <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>, 5535 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, 5536 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, 5537 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, 5538 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, 5539 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 5540 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, 5541 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>, 5542 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, 5543 <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>, 5544 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 5545 <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>, 5546 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 5547 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>, 5548 <GIC_SPI 708 IRQ_TYPE_LEVEL_HIGH>, 5549 <GIC_SPI 709 IRQ_TYPE_LEVEL_HIGH>, 5550 <GIC_SPI 710 IRQ_TYPE_LEVEL_HIGH>, 5551 <GIC_SPI 711 IRQ_TYPE_LEVEL_HIGH>, 5552 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>, 5553 <GIC_SPI 712 IRQ_TYPE_LEVEL_HIGH>, 5554 <GIC_SPI 713 IRQ_TYPE_LEVEL_HIGH>, 5555 <GIC_SPI 714 IRQ_TYPE_LEVEL_HIGH>, 5556 <GIC_SPI 715 IRQ_TYPE_LEVEL_HIGH>, 5557 <GIC_SPI 912 IRQ_TYPE_LEVEL_HIGH>, 5558 <GIC_SPI 911 IRQ_TYPE_LEVEL_HIGH>, 5559 <GIC_SPI 910 IRQ_TYPE_LEVEL_HIGH>, 5560 <GIC_SPI 909 IRQ_TYPE_LEVEL_HIGH>, 5561 <GIC_SPI 908 IRQ_TYPE_LEVEL_HIGH>, 5562 <GIC_SPI 907 IRQ_TYPE_LEVEL_HIGH>, 5563 <GIC_SPI 906 IRQ_TYPE_LEVEL_HIGH>, 5564 <GIC_SPI 905 IRQ_TYPE_LEVEL_HIGH>, 5565 <GIC_SPI 904 IRQ_TYPE_LEVEL_HIGH>, 5566 <GIC_SPI 903 IRQ_TYPE_LEVEL_HIGH>, 5567 <GIC_SPI 902 IRQ_TYPE_LEVEL_HIGH>, 5568 <GIC_SPI 901 IRQ_TYPE_LEVEL_HIGH>, 5569 <GIC_SPI 900 IRQ_TYPE_LEVEL_HIGH>, 5570 <GIC_SPI 899 IRQ_TYPE_LEVEL_HIGH>, 5571 <GIC_SPI 898 IRQ_TYPE_LEVEL_HIGH>, 5572 <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>, 5573 <GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>, 5574 <GIC_SPI 895 IRQ_TYPE_LEVEL_HIGH>, 5575 <GIC_SPI 894 IRQ_TYPE_LEVEL_HIGH>, 5576 <GIC_SPI 893 IRQ_TYPE_LEVEL_HIGH>, 5577 <GIC_SPI 892 IRQ_TYPE_LEVEL_HIGH>, 5578 <GIC_SPI 891 IRQ_TYPE_LEVEL_HIGH>, 5579 <GIC_SPI 890 IRQ_TYPE_LEVEL_HIGH>; 5580 dma-coherent; 5581 }; 5582 5583 intc: interrupt-controller@17a00000 { 5584 compatible = "arm,gic-v3"; 5585 interrupt-controller; 5586 #interrupt-cells = <3>; 5587 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ 5588 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ 5589 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 5590 #redistributor-regions = <1>; 5591 redistributor-stride = <0 0x20000>; 5592 5593 #address-cells = <2>; 5594 #size-cells = <2>; 5595 ranges; 5596 5597 its: msi-controller@17a40000 { 5598 compatible = "arm,gic-v3-its"; 5599 reg = <0 0x17a40000 0 0x20000>; 5600 msi-controller; 5601 #msi-cells = <1>; 5602 }; 5603 }; 5604 5605 watchdog@17c10000 { 5606 compatible = "qcom,apss-wdt-sc8280xp", "qcom,kpss-wdt"; 5607 reg = <0 0x17c10000 0 0x1000>; 5608 clocks = <&sleep_clk>; 5609 interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>; 5610 }; 5611 5612 timer@17c20000 { 5613 compatible = "arm,armv7-timer-mem"; 5614 reg = <0x0 0x17c20000 0x0 0x1000>; 5615 #address-cells = <1>; 5616 #size-cells = <1>; 5617 ranges = <0x0 0x0 0x0 0x20000000>; 5618 5619 frame@17c21000 { 5620 frame-number = <0>; 5621 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 5622 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 5623 reg = <0x17c21000 0x1000>, 5624 <0x17c22000 0x1000>; 5625 }; 5626 5627 frame@17c23000 { 5628 frame-number = <1>; 5629 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 5630 reg = <0x17c23000 0x1000>; 5631 status = "disabled"; 5632 }; 5633 5634 frame@17c25000 { 5635 frame-number = <2>; 5636 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 5637 reg = <0x17c25000 0x1000>; 5638 status = "disabled"; 5639 }; 5640 5641 frame@17c27000 { 5642 frame-number = <3>; 5643 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 5644 reg = <0x17c26000 0x1000>; 5645 status = "disabled"; 5646 }; 5647 5648 frame@17c29000 { 5649 frame-number = <4>; 5650 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 5651 reg = <0x17c29000 0x1000>; 5652 status = "disabled"; 5653 }; 5654 5655 frame@17c2b000 { 5656 frame-number = <5>; 5657 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 5658 reg = <0x17c2b000 0x1000>; 5659 status = "disabled"; 5660 }; 5661 5662 frame@17c2d000 { 5663 frame-number = <6>; 5664 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 5665 reg = <0x17c2d000 0x1000>; 5666 status = "disabled"; 5667 }; 5668 }; 5669 5670 apps_rsc: rsc@18200000 { 5671 compatible = "qcom,rpmh-rsc"; 5672 reg = <0x0 0x18200000 0x0 0x10000>, 5673 <0x0 0x18210000 0x0 0x10000>, 5674 <0x0 0x18220000 0x0 0x10000>; 5675 reg-names = "drv-0", "drv-1", "drv-2"; 5676 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 5677 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 5678 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 5679 qcom,tcs-offset = <0xd00>; 5680 qcom,drv-id = <2>; 5681 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>, 5682 <WAKE_TCS 3>, <CONTROL_TCS 1>; 5683 label = "apps_rsc"; 5684 power-domains = <&cluster_pd>; 5685 5686 apps_bcm_voter: bcm-voter { 5687 compatible = "qcom,bcm-voter"; 5688 }; 5689 5690 rpmhcc: clock-controller { 5691 compatible = "qcom,sc8280xp-rpmh-clk"; 5692 #clock-cells = <1>; 5693 clock-names = "xo"; 5694 clocks = <&xo_board_clk>; 5695 }; 5696 5697 rpmhpd: power-controller { 5698 compatible = "qcom,sc8280xp-rpmhpd"; 5699 #power-domain-cells = <1>; 5700 operating-points-v2 = <&rpmhpd_opp_table>; 5701 5702 rpmhpd_opp_table: opp-table { 5703 compatible = "operating-points-v2"; 5704 5705 rpmhpd_opp_ret: opp1 { 5706 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 5707 }; 5708 5709 rpmhpd_opp_min_svs: opp2 { 5710 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 5711 }; 5712 5713 rpmhpd_opp_low_svs: opp3 { 5714 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 5715 }; 5716 5717 rpmhpd_opp_svs: opp4 { 5718 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 5719 }; 5720 5721 rpmhpd_opp_svs_l1: opp5 { 5722 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 5723 }; 5724 5725 rpmhpd_opp_nom: opp6 { 5726 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 5727 }; 5728 5729 rpmhpd_opp_nom_l1: opp7 { 5730 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 5731 }; 5732 5733 rpmhpd_opp_nom_l2: opp8 { 5734 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 5735 }; 5736 5737 rpmhpd_opp_turbo: opp9 { 5738 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 5739 }; 5740 5741 rpmhpd_opp_turbo_l1: opp10 { 5742 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 5743 }; 5744 }; 5745 }; 5746 }; 5747 5748 epss_l3: interconnect@18590000 { 5749 compatible = "qcom,sc8280xp-epss-l3", "qcom,epss-l3"; 5750 reg = <0 0x18590000 0 0x1000>; 5751 5752 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 5753 clock-names = "xo", "alternate"; 5754 5755 #interconnect-cells = <1>; 5756 }; 5757 5758 cpufreq_hw: cpufreq@18591000 { 5759 compatible = "qcom,sc8280xp-cpufreq-epss", "qcom,cpufreq-epss"; 5760 reg = <0 0x18591000 0 0x1000>, 5761 <0 0x18592000 0 0x1000>; 5762 reg-names = "freq-domain0", "freq-domain1"; 5763 5764 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 5765 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 5766 interrupt-names = "dcvsh-irq-0", 5767 "dcvsh-irq-1"; 5768 5769 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 5770 clock-names = "xo", "alternate"; 5771 5772 #freq-domain-cells = <1>; 5773 #clock-cells = <1>; 5774 }; 5775 5776 remoteproc_nsp0: remoteproc@1b300000 { 5777 compatible = "qcom,sc8280xp-nsp0-pas"; 5778 reg = <0 0x1b300000 0 0x10000>; 5779 5780 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 5781 <&smp2p_nsp0_in 0 IRQ_TYPE_EDGE_RISING>, 5782 <&smp2p_nsp0_in 1 IRQ_TYPE_EDGE_RISING>, 5783 <&smp2p_nsp0_in 2 IRQ_TYPE_EDGE_RISING>, 5784 <&smp2p_nsp0_in 3 IRQ_TYPE_EDGE_RISING>; 5785 interrupt-names = "wdog", "fatal", "ready", 5786 "handover", "stop-ack"; 5787 5788 clocks = <&rpmhcc RPMH_CXO_CLK>; 5789 clock-names = "xo"; 5790 5791 power-domains = <&rpmhpd SC8280XP_NSP>; 5792 power-domain-names = "nsp"; 5793 5794 memory-region = <&pil_nsp0_mem>; 5795 5796 qcom,smem-states = <&smp2p_nsp0_out 0>; 5797 qcom,smem-state-names = "stop"; 5798 5799 interconnects = <&nspa_noc MASTER_CDSP_PROC 0 &mc_virt SLAVE_EBI1 0>; 5800 5801 status = "disabled"; 5802 5803 glink-edge { 5804 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 5805 IPCC_MPROC_SIGNAL_GLINK_QMP 5806 IRQ_TYPE_EDGE_RISING>; 5807 mboxes = <&ipcc IPCC_CLIENT_CDSP 5808 IPCC_MPROC_SIGNAL_GLINK_QMP>; 5809 5810 label = "nsp0"; 5811 qcom,remote-pid = <5>; 5812 5813 fastrpc { 5814 compatible = "qcom,fastrpc"; 5815 qcom,glink-channels = "fastrpcglink-apps-dsp"; 5816 label = "cdsp"; 5817 #address-cells = <1>; 5818 #size-cells = <0>; 5819 5820 compute-cb@1 { 5821 compatible = "qcom,fastrpc-compute-cb"; 5822 reg = <1>; 5823 iommus = <&apps_smmu 0x3181 0x0420>; 5824 }; 5825 5826 compute-cb@2 { 5827 compatible = "qcom,fastrpc-compute-cb"; 5828 reg = <2>; 5829 iommus = <&apps_smmu 0x3182 0x0420>; 5830 }; 5831 5832 compute-cb@3 { 5833 compatible = "qcom,fastrpc-compute-cb"; 5834 reg = <3>; 5835 iommus = <&apps_smmu 0x3183 0x0420>; 5836 }; 5837 5838 compute-cb@4 { 5839 compatible = "qcom,fastrpc-compute-cb"; 5840 reg = <4>; 5841 iommus = <&apps_smmu 0x3184 0x0420>; 5842 }; 5843 5844 compute-cb@5 { 5845 compatible = "qcom,fastrpc-compute-cb"; 5846 reg = <5>; 5847 iommus = <&apps_smmu 0x3185 0x0420>; 5848 }; 5849 5850 compute-cb@6 { 5851 compatible = "qcom,fastrpc-compute-cb"; 5852 reg = <6>; 5853 iommus = <&apps_smmu 0x3186 0x0420>; 5854 }; 5855 5856 compute-cb@7 { 5857 compatible = "qcom,fastrpc-compute-cb"; 5858 reg = <7>; 5859 iommus = <&apps_smmu 0x3187 0x0420>; 5860 }; 5861 5862 compute-cb@8 { 5863 compatible = "qcom,fastrpc-compute-cb"; 5864 reg = <8>; 5865 iommus = <&apps_smmu 0x3188 0x0420>; 5866 }; 5867 5868 compute-cb@9 { 5869 compatible = "qcom,fastrpc-compute-cb"; 5870 reg = <9>; 5871 iommus = <&apps_smmu 0x318b 0x0420>; 5872 }; 5873 5874 compute-cb@10 { 5875 compatible = "qcom,fastrpc-compute-cb"; 5876 reg = <10>; 5877 iommus = <&apps_smmu 0x318b 0x0420>; 5878 }; 5879 5880 compute-cb@11 { 5881 compatible = "qcom,fastrpc-compute-cb"; 5882 reg = <11>; 5883 iommus = <&apps_smmu 0x318c 0x0420>; 5884 }; 5885 5886 compute-cb@12 { 5887 compatible = "qcom,fastrpc-compute-cb"; 5888 reg = <12>; 5889 iommus = <&apps_smmu 0x318d 0x0420>; 5890 }; 5891 5892 compute-cb@13 { 5893 compatible = "qcom,fastrpc-compute-cb"; 5894 reg = <13>; 5895 iommus = <&apps_smmu 0x318e 0x0420>; 5896 }; 5897 5898 compute-cb@14 { 5899 compatible = "qcom,fastrpc-compute-cb"; 5900 reg = <14>; 5901 iommus = <&apps_smmu 0x318f 0x0420>; 5902 }; 5903 }; 5904 }; 5905 }; 5906 5907 remoteproc_nsp1: remoteproc@21300000 { 5908 compatible = "qcom,sc8280xp-nsp1-pas"; 5909 reg = <0 0x21300000 0 0x10000>; 5910 5911 interrupts-extended = <&intc GIC_SPI 887 IRQ_TYPE_EDGE_RISING>, 5912 <&smp2p_nsp1_in 0 IRQ_TYPE_EDGE_RISING>, 5913 <&smp2p_nsp1_in 1 IRQ_TYPE_EDGE_RISING>, 5914 <&smp2p_nsp1_in 2 IRQ_TYPE_EDGE_RISING>, 5915 <&smp2p_nsp1_in 3 IRQ_TYPE_EDGE_RISING>; 5916 interrupt-names = "wdog", "fatal", "ready", 5917 "handover", "stop-ack"; 5918 5919 clocks = <&rpmhcc RPMH_CXO_CLK>; 5920 clock-names = "xo"; 5921 5922 power-domains = <&rpmhpd SC8280XP_NSP>; 5923 power-domain-names = "nsp"; 5924 5925 memory-region = <&pil_nsp1_mem>; 5926 5927 qcom,smem-states = <&smp2p_nsp1_out 0>; 5928 qcom,smem-state-names = "stop"; 5929 5930 interconnects = <&nspb_noc MASTER_CDSP_PROC_B 0 &mc_virt SLAVE_EBI1 0>; 5931 5932 status = "disabled"; 5933 5934 glink-edge { 5935 interrupts-extended = <&ipcc IPCC_CLIENT_NSP1 5936 IPCC_MPROC_SIGNAL_GLINK_QMP 5937 IRQ_TYPE_EDGE_RISING>; 5938 mboxes = <&ipcc IPCC_CLIENT_NSP1 5939 IPCC_MPROC_SIGNAL_GLINK_QMP>; 5940 5941 label = "nsp1"; 5942 qcom,remote-pid = <12>; 5943 }; 5944 }; 5945 5946 mdss1: display-subsystem@22000000 { 5947 compatible = "qcom,sc8280xp-mdss"; 5948 reg = <0 0x22000000 0 0x1000>; 5949 reg-names = "mdss"; 5950 5951 clocks = <&gcc GCC_DISP_AHB_CLK>, 5952 <&dispcc1 DISP_CC_MDSS_AHB_CLK>, 5953 <&dispcc1 DISP_CC_MDSS_MDP_CLK>; 5954 clock-names = "iface", 5955 "ahb", 5956 "core"; 5957 interconnects = <&mmss_noc MASTER_MDP_CORE1_0 0 &mc_virt SLAVE_EBI1 0>, 5958 <&mmss_noc MASTER_MDP_CORE1_1 0 &mc_virt SLAVE_EBI1 0>; 5959 interconnect-names = "mdp0-mem", "mdp1-mem"; 5960 interrupts = <GIC_SPI 865 IRQ_TYPE_LEVEL_HIGH>; 5961 5962 iommus = <&apps_smmu 0x1800 0x402>; 5963 power-domains = <&dispcc1 MDSS_GDSC>; 5964 resets = <&dispcc1 DISP_CC_MDSS_CORE_BCR>; 5965 5966 interrupt-controller; 5967 #interrupt-cells = <1>; 5968 #address-cells = <2>; 5969 #size-cells = <2>; 5970 ranges; 5971 5972 status = "disabled"; 5973 5974 mdss1_mdp: display-controller@22001000 { 5975 compatible = "qcom,sc8280xp-dpu"; 5976 reg = <0 0x22001000 0 0x8f000>, 5977 <0 0x220b0000 0 0x3000>; 5978 reg-names = "mdp", "vbif"; 5979 5980 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 5981 <&gcc GCC_DISP_SF_AXI_CLK>, 5982 <&dispcc1 DISP_CC_MDSS_AHB_CLK>, 5983 <&dispcc1 DISP_CC_MDSS_MDP_LUT_CLK>, 5984 <&dispcc1 DISP_CC_MDSS_MDP_CLK>, 5985 <&dispcc1 DISP_CC_MDSS_VSYNC_CLK>; 5986 clock-names = "bus", 5987 "nrt_bus", 5988 "iface", 5989 "lut", 5990 "core", 5991 "vsync"; 5992 interrupt-parent = <&mdss1>; 5993 interrupts = <0>; 5994 power-domains = <&rpmhpd SC8280XP_MMCX>; 5995 5996 assigned-clocks = <&dispcc1 DISP_CC_MDSS_VSYNC_CLK>; 5997 assigned-clock-rates = <19200000>; 5998 operating-points-v2 = <&mdss1_mdp_opp_table>; 5999 6000 ports { 6001 #address-cells = <1>; 6002 #size-cells = <0>; 6003 6004 port@0 { 6005 reg = <0>; 6006 mdss1_intf0_out: endpoint { 6007 remote-endpoint = <&mdss1_dp0_in>; 6008 }; 6009 }; 6010 6011 port@4 { 6012 reg = <4>; 6013 mdss1_intf4_out: endpoint { 6014 remote-endpoint = <&mdss1_dp1_in>; 6015 }; 6016 }; 6017 6018 port@5 { 6019 reg = <5>; 6020 mdss1_intf5_out: endpoint { 6021 remote-endpoint = <&mdss1_dp3_in>; 6022 }; 6023 }; 6024 6025 port@6 { 6026 reg = <6>; 6027 mdss1_intf6_out: endpoint { 6028 remote-endpoint = <&mdss1_dp2_in>; 6029 }; 6030 }; 6031 }; 6032 6033 mdss1_mdp_opp_table: opp-table { 6034 compatible = "operating-points-v2"; 6035 6036 opp-200000000 { 6037 opp-hz = /bits/ 64 <200000000>; 6038 required-opps = <&rpmhpd_opp_low_svs>; 6039 }; 6040 6041 opp-300000000 { 6042 opp-hz = /bits/ 64 <300000000>; 6043 required-opps = <&rpmhpd_opp_svs>; 6044 }; 6045 6046 opp-375000000 { 6047 opp-hz = /bits/ 64 <375000000>; 6048 required-opps = <&rpmhpd_opp_svs_l1>; 6049 }; 6050 6051 opp-500000000 { 6052 opp-hz = /bits/ 64 <500000000>; 6053 required-opps = <&rpmhpd_opp_nom>; 6054 }; 6055 opp-600000000 { 6056 opp-hz = /bits/ 64 <600000000>; 6057 required-opps = <&rpmhpd_opp_turbo_l1>; 6058 }; 6059 }; 6060 }; 6061 6062 mdss1_dp0: displayport-controller@22090000 { 6063 compatible = "qcom,sc8280xp-dp"; 6064 reg = <0 0x22090000 0 0x200>, 6065 <0 0x22090200 0 0x200>, 6066 <0 0x22090400 0 0x600>, 6067 <0 0x22091000 0 0x400>, 6068 <0 0x22091400 0 0x400>; 6069 6070 clocks = <&dispcc1 DISP_CC_MDSS_AHB_CLK>, 6071 <&dispcc1 DISP_CC_MDSS_DPTX0_AUX_CLK>, 6072 <&dispcc1 DISP_CC_MDSS_DPTX0_LINK_CLK>, 6073 <&dispcc1 DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, 6074 <&dispcc1 DISP_CC_MDSS_DPTX0_PIXEL0_CLK>, 6075 <&dispcc1 DISP_CC_MDSS_DPTX0_PIXEL1_CLK>; 6076 clock-names = "core_iface", "core_aux", 6077 "ctrl_link", 6078 "ctrl_link_iface", "stream_pixel", 6079 "stream_1_pixel"; 6080 interrupt-parent = <&mdss1>; 6081 interrupts = <12>; 6082 phys = <&mdss1_dp0_phy>; 6083 phy-names = "dp"; 6084 power-domains = <&rpmhpd SC8280XP_MMCX>; 6085 6086 assigned-clocks = <&dispcc1 DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, 6087 <&dispcc1 DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>, 6088 <&dispcc1 DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>; 6089 assigned-clock-parents = <&mdss1_dp0_phy 0>, 6090 <&mdss1_dp0_phy 1>, 6091 <&mdss1_dp0_phy 1>; 6092 operating-points-v2 = <&mdss1_dp0_opp_table>; 6093 6094 #sound-dai-cells = <0>; 6095 6096 status = "disabled"; 6097 6098 ports { 6099 #address-cells = <1>; 6100 #size-cells = <0>; 6101 6102 port@0 { 6103 reg = <0>; 6104 mdss1_dp0_in: endpoint { 6105 remote-endpoint = <&mdss1_intf0_out>; 6106 }; 6107 }; 6108 6109 port@1 { 6110 reg = <1>; 6111 6112 mdss1_dp0_out: endpoint { 6113 }; 6114 }; 6115 }; 6116 6117 mdss1_dp0_opp_table: opp-table { 6118 compatible = "operating-points-v2"; 6119 6120 opp-160000000 { 6121 opp-hz = /bits/ 64 <160000000>; 6122 required-opps = <&rpmhpd_opp_low_svs>; 6123 }; 6124 6125 opp-270000000 { 6126 opp-hz = /bits/ 64 <270000000>; 6127 required-opps = <&rpmhpd_opp_svs>; 6128 }; 6129 6130 opp-540000000 { 6131 opp-hz = /bits/ 64 <540000000>; 6132 required-opps = <&rpmhpd_opp_svs_l1>; 6133 }; 6134 6135 opp-810000000 { 6136 opp-hz = /bits/ 64 <810000000>; 6137 required-opps = <&rpmhpd_opp_nom>; 6138 }; 6139 }; 6140 }; 6141 6142 mdss1_dp1: displayport-controller@22098000 { 6143 compatible = "qcom,sc8280xp-dp"; 6144 reg = <0 0x22098000 0 0x200>, 6145 <0 0x22098200 0 0x200>, 6146 <0 0x22098400 0 0x600>, 6147 <0 0x22099000 0 0x400>, 6148 <0 0x22099400 0 0x400>; 6149 6150 clocks = <&dispcc1 DISP_CC_MDSS_AHB_CLK>, 6151 <&dispcc1 DISP_CC_MDSS_DPTX1_AUX_CLK>, 6152 <&dispcc1 DISP_CC_MDSS_DPTX1_LINK_CLK>, 6153 <&dispcc1 DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>, 6154 <&dispcc1 DISP_CC_MDSS_DPTX1_PIXEL0_CLK>, 6155 <&dispcc1 DISP_CC_MDSS_DPTX1_PIXEL1_CLK>; 6156 clock-names = "core_iface", "core_aux", 6157 "ctrl_link", 6158 "ctrl_link_iface", "stream_pixel", 6159 "stream_1_pixel"; 6160 interrupt-parent = <&mdss1>; 6161 interrupts = <13>; 6162 phys = <&mdss1_dp1_phy>; 6163 phy-names = "dp"; 6164 power-domains = <&rpmhpd SC8280XP_MMCX>; 6165 6166 assigned-clocks = <&dispcc1 DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>, 6167 <&dispcc1 DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>, 6168 <&dispcc1 DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC>; 6169 assigned-clock-parents = <&mdss1_dp1_phy 0>, 6170 <&mdss1_dp1_phy 1>, 6171 <&mdss1_dp1_phy 1>; 6172 operating-points-v2 = <&mdss1_dp1_opp_table>; 6173 6174 #sound-dai-cells = <0>; 6175 6176 status = "disabled"; 6177 6178 ports { 6179 #address-cells = <1>; 6180 #size-cells = <0>; 6181 6182 port@0 { 6183 reg = <0>; 6184 mdss1_dp1_in: endpoint { 6185 remote-endpoint = <&mdss1_intf4_out>; 6186 }; 6187 }; 6188 6189 port@1 { 6190 reg = <1>; 6191 6192 mdss1_dp1_out: endpoint { 6193 }; 6194 }; 6195 }; 6196 6197 mdss1_dp1_opp_table: opp-table { 6198 compatible = "operating-points-v2"; 6199 6200 opp-160000000 { 6201 opp-hz = /bits/ 64 <160000000>; 6202 required-opps = <&rpmhpd_opp_low_svs>; 6203 }; 6204 6205 opp-270000000 { 6206 opp-hz = /bits/ 64 <270000000>; 6207 required-opps = <&rpmhpd_opp_svs>; 6208 }; 6209 6210 opp-540000000 { 6211 opp-hz = /bits/ 64 <540000000>; 6212 required-opps = <&rpmhpd_opp_svs_l1>; 6213 }; 6214 6215 opp-810000000 { 6216 opp-hz = /bits/ 64 <810000000>; 6217 required-opps = <&rpmhpd_opp_nom>; 6218 }; 6219 }; 6220 }; 6221 6222 mdss1_dp2: displayport-controller@2209a000 { 6223 compatible = "qcom,sc8280xp-dp"; 6224 reg = <0 0x2209a000 0 0x200>, 6225 <0 0x2209a200 0 0x200>, 6226 <0 0x2209a400 0 0x600>, 6227 <0 0x2209b000 0 0x400>, 6228 <0 0x2209b400 0 0x400>; 6229 6230 clocks = <&dispcc1 DISP_CC_MDSS_AHB_CLK>, 6231 <&dispcc1 DISP_CC_MDSS_DPTX2_AUX_CLK>, 6232 <&dispcc1 DISP_CC_MDSS_DPTX2_LINK_CLK>, 6233 <&dispcc1 DISP_CC_MDSS_DPTX2_LINK_INTF_CLK>, 6234 <&dispcc1 DISP_CC_MDSS_DPTX2_PIXEL0_CLK>, 6235 <&dispcc1 DISP_CC_MDSS_DPTX2_PIXEL1_CLK>; 6236 clock-names = "core_iface", "core_aux", 6237 "ctrl_link", 6238 "ctrl_link_iface", "stream_pixel", 6239 "stream_1_pixel"; 6240 interrupt-parent = <&mdss1>; 6241 interrupts = <14>; 6242 phys = <&mdss1_dp2_phy>; 6243 phy-names = "dp"; 6244 power-domains = <&rpmhpd SC8280XP_MMCX>; 6245 6246 assigned-clocks = <&dispcc1 DISP_CC_MDSS_DPTX2_LINK_CLK_SRC>, 6247 <&dispcc1 DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC>, 6248 <&dispcc1 DISP_CC_MDSS_DPTX2_PIXEL1_CLK_SRC>; 6249 assigned-clock-parents = <&mdss1_dp2_phy 0>, 6250 <&mdss1_dp2_phy 1>, 6251 <&mdss1_dp2_phy 1>; 6252 operating-points-v2 = <&mdss1_dp2_opp_table>; 6253 6254 #sound-dai-cells = <0>; 6255 6256 status = "disabled"; 6257 6258 ports { 6259 #address-cells = <1>; 6260 #size-cells = <0>; 6261 6262 port@0 { 6263 reg = <0>; 6264 mdss1_dp2_in: endpoint { 6265 remote-endpoint = <&mdss1_intf6_out>; 6266 }; 6267 }; 6268 6269 port@1 { 6270 reg = <1>; 6271 6272 mdss1_dp2_out: endpoint { 6273 }; 6274 }; 6275 }; 6276 6277 mdss1_dp2_opp_table: opp-table { 6278 compatible = "operating-points-v2"; 6279 6280 opp-160000000 { 6281 opp-hz = /bits/ 64 <160000000>; 6282 required-opps = <&rpmhpd_opp_low_svs>; 6283 }; 6284 6285 opp-270000000 { 6286 opp-hz = /bits/ 64 <270000000>; 6287 required-opps = <&rpmhpd_opp_svs>; 6288 }; 6289 6290 opp-540000000 { 6291 opp-hz = /bits/ 64 <540000000>; 6292 required-opps = <&rpmhpd_opp_svs_l1>; 6293 }; 6294 6295 opp-810000000 { 6296 opp-hz = /bits/ 64 <810000000>; 6297 required-opps = <&rpmhpd_opp_nom>; 6298 }; 6299 }; 6300 }; 6301 6302 mdss1_dp3: displayport-controller@220a0000 { 6303 compatible = "qcom,sc8280xp-dp"; 6304 reg = <0 0x220a0000 0 0x200>, 6305 <0 0x220a0200 0 0x200>, 6306 <0 0x220a0400 0 0x600>, 6307 <0 0x220a1000 0 0x400>, 6308 <0 0x220a1400 0 0x400>; 6309 6310 clocks = <&dispcc1 DISP_CC_MDSS_AHB_CLK>, 6311 <&dispcc1 DISP_CC_MDSS_DPTX3_AUX_CLK>, 6312 <&dispcc1 DISP_CC_MDSS_DPTX3_LINK_CLK>, 6313 <&dispcc1 DISP_CC_MDSS_DPTX3_LINK_INTF_CLK>, 6314 <&dispcc1 DISP_CC_MDSS_DPTX3_PIXEL0_CLK>; 6315 clock-names = "core_iface", "core_aux", 6316 "ctrl_link", 6317 "ctrl_link_iface", "stream_pixel"; 6318 interrupt-parent = <&mdss1>; 6319 interrupts = <15>; 6320 phys = <&mdss1_dp3_phy>; 6321 phy-names = "dp"; 6322 power-domains = <&rpmhpd SC8280XP_MMCX>; 6323 6324 assigned-clocks = <&dispcc1 DISP_CC_MDSS_DPTX3_LINK_CLK_SRC>, 6325 <&dispcc1 DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC>; 6326 assigned-clock-parents = <&mdss1_dp3_phy 0>, <&mdss1_dp3_phy 1>; 6327 operating-points-v2 = <&mdss1_dp3_opp_table>; 6328 6329 #sound-dai-cells = <0>; 6330 6331 status = "disabled"; 6332 6333 ports { 6334 #address-cells = <1>; 6335 #size-cells = <0>; 6336 6337 port@0 { 6338 reg = <0>; 6339 mdss1_dp3_in: endpoint { 6340 remote-endpoint = <&mdss1_intf5_out>; 6341 }; 6342 }; 6343 6344 port@1 { 6345 reg = <1>; 6346 6347 mdss1_dp3_out: endpoint { 6348 }; 6349 }; 6350 }; 6351 6352 mdss1_dp3_opp_table: opp-table { 6353 compatible = "operating-points-v2"; 6354 6355 opp-160000000 { 6356 opp-hz = /bits/ 64 <160000000>; 6357 required-opps = <&rpmhpd_opp_low_svs>; 6358 }; 6359 6360 opp-270000000 { 6361 opp-hz = /bits/ 64 <270000000>; 6362 required-opps = <&rpmhpd_opp_svs>; 6363 }; 6364 6365 opp-540000000 { 6366 opp-hz = /bits/ 64 <540000000>; 6367 required-opps = <&rpmhpd_opp_svs_l1>; 6368 }; 6369 6370 opp-810000000 { 6371 opp-hz = /bits/ 64 <810000000>; 6372 required-opps = <&rpmhpd_opp_nom>; 6373 }; 6374 }; 6375 }; 6376 }; 6377 6378 mdss1_dp2_phy: phy@220c2a00 { 6379 compatible = "qcom,sc8280xp-dp-phy"; 6380 reg = <0 0x220c2a00 0 0x19c>, 6381 <0 0x220c2200 0 0xec>, 6382 <0 0x220c2600 0 0xec>, 6383 <0 0x220c2000 0 0x1c8>; 6384 6385 clocks = <&dispcc1 DISP_CC_MDSS_DPTX2_AUX_CLK>, 6386 <&dispcc1 DISP_CC_MDSS_AHB_CLK>; 6387 clock-names = "aux", "cfg_ahb"; 6388 power-domains = <&rpmhpd SC8280XP_MX>; 6389 6390 #clock-cells = <1>; 6391 #phy-cells = <0>; 6392 6393 status = "disabled"; 6394 }; 6395 6396 mdss1_dp3_phy: phy@220c5a00 { 6397 compatible = "qcom,sc8280xp-dp-phy"; 6398 reg = <0 0x220c5a00 0 0x19c>, 6399 <0 0x220c5200 0 0xec>, 6400 <0 0x220c5600 0 0xec>, 6401 <0 0x220c5000 0 0x1c8>; 6402 6403 clocks = <&dispcc1 DISP_CC_MDSS_DPTX3_AUX_CLK>, 6404 <&dispcc1 DISP_CC_MDSS_AHB_CLK>; 6405 clock-names = "aux", "cfg_ahb"; 6406 power-domains = <&rpmhpd SC8280XP_MX>; 6407 6408 #clock-cells = <1>; 6409 #phy-cells = <0>; 6410 6411 status = "disabled"; 6412 }; 6413 6414 dispcc1: clock-controller@22100000 { 6415 compatible = "qcom,sc8280xp-dispcc1"; 6416 reg = <0 0x22100000 0 0x20000>; 6417 6418 clocks = <&gcc GCC_DISP_AHB_CLK>, 6419 <&rpmhcc RPMH_CXO_CLK>, 6420 <0>, 6421 <&mdss1_dp0_phy 0>, 6422 <&mdss1_dp0_phy 1>, 6423 <&mdss1_dp1_phy 0>, 6424 <&mdss1_dp1_phy 1>, 6425 <&mdss1_dp2_phy 0>, 6426 <&mdss1_dp2_phy 1>, 6427 <&mdss1_dp3_phy 0>, 6428 <&mdss1_dp3_phy 1>, 6429 <0>, 6430 <0>, 6431 <0>, 6432 <0>; 6433 power-domains = <&rpmhpd SC8280XP_MMCX>; 6434 6435 #clock-cells = <1>; 6436 #power-domain-cells = <1>; 6437 #reset-cells = <1>; 6438 6439 status = "disabled"; 6440 }; 6441 6442 ethernet1: ethernet@23000000 { 6443 compatible = "qcom,sc8280xp-ethqos"; 6444 reg = <0x0 0x23000000 0x0 0x10000>, 6445 <0x0 0x23016000 0x0 0x100>; 6446 reg-names = "stmmaceth", "rgmii"; 6447 6448 clocks = <&gcc GCC_EMAC1_AXI_CLK>, 6449 <&gcc GCC_EMAC1_SLV_AHB_CLK>, 6450 <&gcc GCC_EMAC1_PTP_CLK>, 6451 <&gcc GCC_EMAC1_RGMII_CLK>; 6452 clock-names = "stmmaceth", 6453 "pclk", 6454 "ptp_ref", 6455 "rgmii"; 6456 6457 interrupts = <GIC_SPI 929 IRQ_TYPE_LEVEL_HIGH>, 6458 <GIC_SPI 919 IRQ_TYPE_LEVEL_HIGH>; 6459 interrupt-names = "macirq", "eth_lpi"; 6460 6461 iommus = <&apps_smmu 0x40 0xf>; 6462 power-domains = <&gcc EMAC_1_GDSC>; 6463 6464 snps,tso; 6465 snps,pbl = <32>; 6466 rx-fifo-depth = <4096>; 6467 tx-fifo-depth = <4096>; 6468 6469 status = "disabled"; 6470 }; 6471 }; 6472 6473 sound: sound { 6474 }; 6475 6476 thermal-zones { 6477 cpu0-thermal { 6478 polling-delay-passive = <250>; 6479 6480 thermal-sensors = <&tsens0 1>; 6481 6482 trips { 6483 cpu-crit { 6484 temperature = <110000>; 6485 hysteresis = <1000>; 6486 type = "critical"; 6487 }; 6488 }; 6489 }; 6490 6491 cpu1-thermal { 6492 polling-delay-passive = <250>; 6493 6494 thermal-sensors = <&tsens0 2>; 6495 6496 trips { 6497 cpu-crit { 6498 temperature = <110000>; 6499 hysteresis = <1000>; 6500 type = "critical"; 6501 }; 6502 }; 6503 }; 6504 6505 cpu2-thermal { 6506 polling-delay-passive = <250>; 6507 6508 thermal-sensors = <&tsens0 3>; 6509 6510 trips { 6511 cpu-crit { 6512 temperature = <110000>; 6513 hysteresis = <1000>; 6514 type = "critical"; 6515 }; 6516 }; 6517 }; 6518 6519 cpu3-thermal { 6520 polling-delay-passive = <250>; 6521 6522 thermal-sensors = <&tsens0 4>; 6523 6524 trips { 6525 cpu-crit { 6526 temperature = <110000>; 6527 hysteresis = <1000>; 6528 type = "critical"; 6529 }; 6530 }; 6531 }; 6532 6533 cpu4-thermal { 6534 polling-delay-passive = <250>; 6535 6536 thermal-sensors = <&tsens0 5>; 6537 6538 trips { 6539 cpu-crit { 6540 temperature = <110000>; 6541 hysteresis = <1000>; 6542 type = "critical"; 6543 }; 6544 }; 6545 }; 6546 6547 cpu5-thermal { 6548 polling-delay-passive = <250>; 6549 6550 thermal-sensors = <&tsens0 6>; 6551 6552 trips { 6553 cpu-crit { 6554 temperature = <110000>; 6555 hysteresis = <1000>; 6556 type = "critical"; 6557 }; 6558 }; 6559 }; 6560 6561 cpu6-thermal { 6562 polling-delay-passive = <250>; 6563 6564 thermal-sensors = <&tsens0 7>; 6565 6566 trips { 6567 cpu-crit { 6568 temperature = <110000>; 6569 hysteresis = <1000>; 6570 type = "critical"; 6571 }; 6572 }; 6573 }; 6574 6575 cpu7-thermal { 6576 polling-delay-passive = <250>; 6577 6578 thermal-sensors = <&tsens0 8>; 6579 6580 trips { 6581 cpu-crit { 6582 temperature = <110000>; 6583 hysteresis = <1000>; 6584 type = "critical"; 6585 }; 6586 }; 6587 }; 6588 6589 cluster0-thermal { 6590 polling-delay-passive = <250>; 6591 6592 thermal-sensors = <&tsens0 9>; 6593 6594 trips { 6595 cpu-crit { 6596 temperature = <110000>; 6597 hysteresis = <1000>; 6598 type = "critical"; 6599 }; 6600 }; 6601 }; 6602 6603 gpu-thermal { 6604 polling-delay-passive = <250>; 6605 6606 thermal-sensors = <&tsens2 2>; 6607 6608 cooling-maps { 6609 map0 { 6610 trip = <&gpu_alert0>; 6611 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6612 }; 6613 }; 6614 6615 trips { 6616 gpu_alert0: trip-point0 { 6617 temperature = <85000>; 6618 hysteresis = <1000>; 6619 type = "passive"; 6620 }; 6621 6622 trip-point1 { 6623 temperature = <110000>; 6624 hysteresis = <1000>; 6625 type = "critical"; 6626 }; 6627 }; 6628 }; 6629 6630 mem-thermal { 6631 polling-delay-passive = <250>; 6632 6633 thermal-sensors = <&tsens1 15>; 6634 6635 trips { 6636 trip-point0 { 6637 temperature = <90000>; 6638 hysteresis = <2000>; 6639 type = "hot"; 6640 }; 6641 }; 6642 }; 6643 }; 6644 6645 timer { 6646 compatible = "arm,armv8-timer"; 6647 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 6648 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 6649 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 6650 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 6651 }; 6652}; 6653