1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2003-2008, Joseph Koshy 5 * Copyright (c) 2007 The FreeBSD Foundation 6 * All rights reserved. 7 * 8 * Portions of this software were developed by A. Joseph Koshy under 9 * sponsorship from the FreeBSD Foundation and Google, Inc. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 24 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 30 * SUCH DAMAGE. 31 */ 32 33 #ifndef _SYS_PMC_H_ 34 #define _SYS_PMC_H_ 35 36 #include <dev/hwpmc/pmc_events.h> 37 #include <sys/proc.h> 38 #include <sys/counter.h> 39 #include <machine/pmc_mdep.h> 40 #include <machine/profile.h> 41 #ifdef _KERNEL 42 #include <sys/epoch.h> 43 #include <ck_queue.h> 44 #endif 45 46 #define PMC_MODULE_NAME "hwpmc" 47 #define PMC_NAME_MAX 64 /* HW counter name size */ 48 #define PMC_CLASS_MAX 8 /* max #classes of PMCs per-system */ 49 50 /* 51 * Kernel<->userland API version number [MMmmpppp] 52 * 53 * Major numbers are to be incremented when an incompatible change to 54 * the ABI occurs that older clients will not be able to handle. 55 * 56 * Minor numbers are incremented when a backwards compatible change 57 * occurs that allows older correct programs to run unchanged. For 58 * example, when support for a new PMC type is added. 59 * 60 * The patch version is incremented for every bug fix. 61 */ 62 #define PMC_VERSION_MAJOR 0x0A 63 #define PMC_VERSION_MINOR 0x02 64 #define PMC_VERSION_PATCH 0x0000 65 66 #define PMC_VERSION (PMC_VERSION_MAJOR << 24 | \ 67 PMC_VERSION_MINOR << 16 | PMC_VERSION_PATCH) 68 69 #define PMC_CPUID_LEN 64 70 /* cpu model name for pmu lookup */ 71 extern char pmc_cpuid[PMC_CPUID_LEN]; 72 73 /* 74 * Kinds of CPUs known. 75 * 76 * We keep track of CPU variants that need to be distinguished in 77 * some way for PMC operations. CPU names are grouped by manufacturer 78 * and numbered sparsely in order to minimize changes to the ABI involved 79 * when new CPUs are added. 80 * 81 * Please keep the pmc(3) manual page in sync with this list. 82 */ 83 #define __PMC_CPUS() \ 84 __PMC_CPU(AMD_K8, 0x01, "AMD K8") \ 85 __PMC_CPU(INTEL_CORE, 0x87, "Intel Core Solo/Duo") \ 86 __PMC_CPU(INTEL_CORE2, 0x88, "Intel Core2") \ 87 __PMC_CPU(INTEL_CORE2EXTREME, 0x89, "Intel Core2 Extreme") \ 88 __PMC_CPU(INTEL_ATOM, 0x8A, "Intel Atom") \ 89 __PMC_CPU(INTEL_COREI7, 0x8B, "Intel Core i7") \ 90 __PMC_CPU(INTEL_WESTMERE, 0x8C, "Intel Westmere") \ 91 __PMC_CPU(INTEL_SANDYBRIDGE, 0x8D, "Intel Sandy Bridge") \ 92 __PMC_CPU(INTEL_IVYBRIDGE, 0x8E, "Intel Ivy Bridge") \ 93 __PMC_CPU(INTEL_SANDYBRIDGE_XEON, 0x8F, "Intel Sandy Bridge Xeon") \ 94 __PMC_CPU(INTEL_IVYBRIDGE_XEON, 0x90, "Intel Ivy Bridge Xeon") \ 95 __PMC_CPU(INTEL_HASWELL, 0x91, "Intel Haswell") \ 96 __PMC_CPU(INTEL_ATOM_SILVERMONT, 0x92, "Intel Atom Silvermont") \ 97 __PMC_CPU(INTEL_NEHALEM_EX, 0x93, "Intel Nehalem Xeon 7500") \ 98 __PMC_CPU(INTEL_WESTMERE_EX, 0x94, "Intel Westmere Xeon E7") \ 99 __PMC_CPU(INTEL_HASWELL_XEON, 0x95, "Intel Haswell Xeon E5 v3") \ 100 __PMC_CPU(INTEL_BROADWELL, 0x96, "Intel Broadwell") \ 101 __PMC_CPU(INTEL_BROADWELL_XEON, 0x97, "Intel Broadwell Xeon") \ 102 __PMC_CPU(INTEL_SKYLAKE, 0x98, "Intel Skylake") \ 103 __PMC_CPU(INTEL_SKYLAKE_XEON, 0x99, "Intel Skylake Xeon") \ 104 __PMC_CPU(INTEL_ATOM_GOLDMONT, 0x9A, "Intel Atom Goldmont") \ 105 __PMC_CPU(INTEL_ICELAKE, 0x9B, "Intel Icelake") \ 106 __PMC_CPU(INTEL_ICELAKE_XEON, 0x9C, "Intel Icelake Xeon") \ 107 __PMC_CPU(INTEL_ALDERLAKE, 0x9D, "Intel Alderlake") \ 108 __PMC_CPU(INTEL_ATOM_GOLDMONT_P, 0x9E, "Intel Atom Goldmont Plus") \ 109 __PMC_CPU(INTEL_ATOM_TREMONT, 0x9F, "Intel Atom Tremont") \ 110 __PMC_CPU(INTEL_EMERALD_RAPIDS, 0xA0, "Intel Emerald Rapids") \ 111 __PMC_CPU(INTEL_ALDERLAKEN, 0xA1, "Intel AlderlakeN") \ 112 __PMC_CPU(INTEL_GRANITE_RAPIDS, 0xA2, "Intel Granite Rapids") \ 113 __PMC_CPU(INTEL_METEOR_LAKE, 0xA3, "Intel Meteorlake") \ 114 __PMC_CPU(INTEL_SAPPHIRE_RAPIDS, 0xA4, "Intel Sapphire Rapids") \ 115 __PMC_CPU(PPC_7450, 0x300, "PowerPC MPC7450") \ 116 __PMC_CPU(PPC_E500, 0x340, "PowerPC e500 Core") \ 117 __PMC_CPU(PPC_970, 0x380, "IBM PowerPC 970") \ 118 __PMC_CPU(PPC_POWER8, 0x390, "IBM POWER8") \ 119 __PMC_CPU(GENERIC, 0x400, "Generic") \ 120 __PMC_CPU(ARMV7_CORTEX_A5, 0x500, "ARMv7 Cortex A5") \ 121 __PMC_CPU(ARMV7_CORTEX_A7, 0x501, "ARMv7 Cortex A7") \ 122 __PMC_CPU(ARMV7_CORTEX_A8, 0x502, "ARMv7 Cortex A8") \ 123 __PMC_CPU(ARMV7_CORTEX_A9, 0x503, "ARMv7 Cortex A9") \ 124 __PMC_CPU(ARMV7_CORTEX_A15, 0x504, "ARMv7 Cortex A15") \ 125 __PMC_CPU(ARMV7_CORTEX_A17, 0x505, "ARMv7 Cortex A17") \ 126 __PMC_CPU(ARMV8_CORTEX_A53, 0x600, "ARMv8 Cortex A53") \ 127 __PMC_CPU(ARMV8_CORTEX_A57, 0x601, "ARMv8 Cortex A57") \ 128 __PMC_CPU(ARMV8_CORTEX_A76, 0x602, "ARMv8 Cortex A76") 129 130 enum pmc_cputype { 131 #undef __PMC_CPU 132 #define __PMC_CPU(S,V,D) PMC_CPU_##S = V, 133 __PMC_CPUS() 134 }; 135 136 #define PMC_CPU_FIRST PMC_CPU_AMD_K8 137 #define PMC_CPU_LAST PMC_CPU_ARMV8_CORTEX_A76 138 139 /* 140 * Classes of PMCs 141 */ 142 #define __PMC_CLASSES() \ 143 __PMC_CLASS(TSC, 0x00, "CPU Timestamp counter") \ 144 __PMC_CLASS(K8, 0x02, "AMD K8 performance counters") \ 145 __PMC_CLASS(IBS, 0x03, "AMD IBS performance counters") \ 146 __PMC_CLASS(IAF, 0x06, "Intel Core2/Atom, fixed function") \ 147 __PMC_CLASS(IAP, 0x07, "Intel Core...Atom, programmable") \ 148 __PMC_CLASS(UCF, 0x08, "Intel Uncore fixed function") \ 149 __PMC_CLASS(UCP, 0x09, "Intel Uncore programmable") \ 150 __PMC_CLASS(PPC7450, 0x0D, "Motorola MPC7450 class") \ 151 __PMC_CLASS(PPC970, 0x0E, "IBM PowerPC 970 class") \ 152 __PMC_CLASS(SOFT, 0x0F, "Software events") \ 153 __PMC_CLASS(ARMV7, 0x10, "ARMv7") \ 154 __PMC_CLASS(ARMV8, 0x11, "ARMv8") \ 155 __PMC_CLASS(E500, 0x13, "Freescale e500 class") \ 156 __PMC_CLASS(POWER8, 0x15, "IBM POWER8 class") \ 157 __PMC_CLASS(DMC620_PMU_CD2, 0x16, "ARM DMC620 Memory Controller PMU CLKDIV2") \ 158 __PMC_CLASS(DMC620_PMU_C, 0x17, "ARM DMC620 Memory Controller PMU CLK") \ 159 __PMC_CLASS(CMN600_PMU, 0x18, "Arm CoreLink CMN600 Coherent Mesh Network PMU") \ 160 __PMC_CLASS(RAPL, 0x19, "AMD/Intel RAPL energy counters") 161 162 enum pmc_class { 163 #undef __PMC_CLASS 164 #define __PMC_CLASS(S,V,D) PMC_CLASS_##S = V, 165 __PMC_CLASSES() 166 }; 167 168 #define PMC_CLASS_FIRST PMC_CLASS_TSC 169 #define PMC_CLASS_LAST PMC_CLASS_RAPL 170 171 /* 172 * A PMC can be in the following states: 173 * 174 * Hardware states: 175 * DISABLED -- administratively prohibited from being used. 176 * FREE -- HW available for use 177 * Software states: 178 * ALLOCATED -- allocated 179 * STOPPED -- allocated, but not counting events 180 * RUNNING -- allocated, and in operation; 'pm_runcount' 181 * holds the number of CPUs using this PMC at 182 * a given instant 183 * DELETED -- being destroyed 184 */ 185 186 #define __PMC_HWSTATES() \ 187 __PMC_STATE(DISABLED) \ 188 __PMC_STATE(FREE) 189 190 #define __PMC_SWSTATES() \ 191 __PMC_STATE(ALLOCATED) \ 192 __PMC_STATE(STOPPED) \ 193 __PMC_STATE(RUNNING) \ 194 __PMC_STATE(DELETED) 195 196 #define __PMC_STATES() \ 197 __PMC_HWSTATES() \ 198 __PMC_SWSTATES() 199 200 enum pmc_state { 201 #undef __PMC_STATE 202 #define __PMC_STATE(S) PMC_STATE_##S, 203 __PMC_STATES() 204 __PMC_STATE(MAX) 205 }; 206 207 #define PMC_STATE_FIRST PMC_STATE_DISABLED 208 #define PMC_STATE_LAST PMC_STATE_DELETED 209 210 /* 211 * An allocated PMC may used as a 'global' counter or as a 212 * 'thread-private' one. Each such mode of use can be in either 213 * statistical sampling mode or in counting mode. Thus a PMC in use 214 * 215 * SS i.e., SYSTEM STATISTICAL -- system-wide statistical profiling 216 * SC i.e., SYSTEM COUNTER -- system-wide counting mode 217 * TS i.e., THREAD STATISTICAL -- thread virtual, statistical profiling 218 * TC i.e., THREAD COUNTER -- thread virtual, counting mode 219 * 220 * Statistical profiling modes rely on the PMC periodically delivering 221 * a interrupt to the CPU (when the configured number of events have 222 * been measured), so the PMC must have the ability to generate 223 * interrupts. 224 * 225 * In counting modes, the PMC counts its configured events, with the 226 * value of the PMC being read whenever needed by its owner process. 227 * 228 * The thread specific modes "virtualize" the PMCs -- the PMCs appear 229 * to be thread private and count events only when the profiled thread 230 * actually executes on the CPU. 231 * 232 * The system-wide "global" modes keep the PMCs running all the time 233 * and are used to measure the behaviour of the whole system. 234 */ 235 236 #define __PMC_MODES() \ 237 __PMC_MODE(SS, 0) \ 238 __PMC_MODE(SC, 1) \ 239 __PMC_MODE(TS, 2) \ 240 __PMC_MODE(TC, 3) 241 242 enum pmc_mode { 243 #undef __PMC_MODE 244 #define __PMC_MODE(M,N) PMC_MODE_##M = N, 245 __PMC_MODES() 246 }; 247 248 #define PMC_MODE_FIRST PMC_MODE_SS 249 #define PMC_MODE_LAST PMC_MODE_TC 250 251 #define PMC_IS_COUNTING_MODE(mode) \ 252 ((mode) == PMC_MODE_SC || (mode) == PMC_MODE_TC) 253 #define PMC_IS_SYSTEM_MODE(mode) \ 254 ((mode) == PMC_MODE_SS || (mode) == PMC_MODE_SC) 255 #define PMC_IS_SAMPLING_MODE(mode) \ 256 ((mode) == PMC_MODE_SS || (mode) == PMC_MODE_TS) 257 #define PMC_IS_VIRTUAL_MODE(mode) \ 258 ((mode) == PMC_MODE_TS || (mode) == PMC_MODE_TC) 259 260 /* 261 * PMC row disposition 262 */ 263 264 #define __PMC_DISPOSITIONS(N) \ 265 __PMC_DISP(STANDALONE) /* global/disabled counters */ \ 266 __PMC_DISP(FREE) /* free/available */ \ 267 __PMC_DISP(THREAD) /* thread-virtual PMCs */ \ 268 __PMC_DISP(UNKNOWN) /* sentinel */ 269 270 enum pmc_disp { 271 #undef __PMC_DISP 272 #define __PMC_DISP(D) PMC_DISP_##D , 273 __PMC_DISPOSITIONS() 274 }; 275 276 #define PMC_DISP_FIRST PMC_DISP_STANDALONE 277 #define PMC_DISP_LAST PMC_DISP_THREAD 278 279 /* 280 * Counter capabilities 281 * 282 * __PMC_CAPS(NAME, VALUE, DESCRIPTION) 283 */ 284 285 #define __PMC_CAPS() \ 286 __PMC_CAP(INTERRUPT, 0, "generate interrupts") \ 287 __PMC_CAP(USER, 1, "count user-mode events") \ 288 __PMC_CAP(SYSTEM, 2, "count system-mode events") \ 289 __PMC_CAP(EDGE, 3, "do edge detection of events") \ 290 __PMC_CAP(THRESHOLD, 4, "ignore events below a threshold") \ 291 __PMC_CAP(READ, 5, "read PMC counter") \ 292 __PMC_CAP(WRITE, 6, "reprogram PMC counter") \ 293 __PMC_CAP(INVERT, 7, "invert comparison sense") \ 294 __PMC_CAP(QUALIFIER, 8, "further qualify monitored events") \ 295 __PMC_CAP(PRECISE, 9, "perform precise sampling") \ 296 __PMC_CAP(TAGGING, 10, "tag upstream events") \ 297 __PMC_CAP(CASCADE, 11, "cascade counters") \ 298 __PMC_CAP(SYSWIDE, 12, "system wide counter") \ 299 __PMC_CAP(DOMWIDE, 13, "NUMA domain wide counter") 300 301 enum pmc_caps 302 { 303 #undef __PMC_CAP 304 #define __PMC_CAP(NAME, VALUE, DESCR) PMC_CAP_##NAME = (1 << VALUE) , 305 __PMC_CAPS() 306 }; 307 308 #define PMC_CAP_FIRST PMC_CAP_INTERRUPT 309 #define PMC_CAP_LAST PMC_CAP_DOMWIDE 310 311 /* 312 * PMC Event Numbers 313 * 314 * These are generated from the definitions in "dev/hwpmc/pmc_events.h". 315 */ 316 317 enum pmc_event { 318 #undef __PMC_EV 319 #undef __PMC_EV_BLOCK 320 #define __PMC_EV_BLOCK(C,V) PMC_EV_ ## C ## __BLOCK_START = (V) - 1 , 321 #define __PMC_EV(C,N) PMC_EV_ ## C ## _ ## N , 322 __PMC_EVENTS() 323 }; 324 325 /* 326 * PMC SYSCALL INTERFACE 327 */ 328 329 /* 330 * "PMC_OPS" -- these are the commands recognized by the kernel 331 * module, and are used when performing a system call from userland. 332 */ 333 #define __PMC_OPS() \ 334 __PMC_OP(CONFIGURELOG, "Set log file") \ 335 __PMC_OP(FLUSHLOG, "Flush log file") \ 336 __PMC_OP(GETCPUINFO, "Get system CPU information") \ 337 __PMC_OP(GETDRIVERSTATS, "Get driver statistics") \ 338 __PMC_OP(GETMODULEVERSION, "Get module version") \ 339 __PMC_OP(GETPMCINFO, "Get per-cpu PMC information") \ 340 __PMC_OP(PMCADMIN, "Set PMC state") \ 341 __PMC_OP(PMCALLOCATE, "Allocate and configure a PMC") \ 342 __PMC_OP(PMCATTACH, "Attach a PMC to a process") \ 343 __PMC_OP(PMCDETACH, "Detach a PMC from a process") \ 344 __PMC_OP(PMCGETMSR, "Get a PMC's hardware address") \ 345 __PMC_OP(PMCRELEASE, "Release a PMC") \ 346 __PMC_OP(PMCRW, "Read/Set a PMC") \ 347 __PMC_OP(PMCSETCOUNT, "Set initial count/sampling rate") \ 348 __PMC_OP(PMCSTART, "Start a PMC") \ 349 __PMC_OP(PMCSTOP, "Stop a PMC") \ 350 __PMC_OP(WRITELOG, "Write a cookie to the log file") \ 351 __PMC_OP(CLOSELOG, "Close log file") \ 352 __PMC_OP(GETDYNEVENTINFO, "Get dynamic events list") \ 353 __PMC_OP(GETCAPS, "Get capabilities") 354 355 enum pmc_ops { 356 #undef __PMC_OP 357 #define __PMC_OP(N, D) PMC_OP_##N, 358 __PMC_OPS() 359 }; 360 361 /* 362 * Flags used in operations on PMCs. 363 */ 364 365 #define PMC_F_UNUSED1 0x00000001 /* unused */ 366 #define PMC_F_DESCENDANTS 0x00000002 /*OP ALLOCATE track descendants */ 367 #define PMC_F_LOG_PROCCSW 0x00000004 /*OP ALLOCATE track ctx switches */ 368 #define PMC_F_LOG_PROCEXIT 0x00000008 /*OP ALLOCATE log proc exits */ 369 #define PMC_F_NEWVALUE 0x00000010 /*OP RW write new value */ 370 #define PMC_F_OLDVALUE 0x00000020 /*OP RW get old value */ 371 372 /* V2 API */ 373 #define PMC_F_CALLCHAIN 0x00000080 /*OP ALLOCATE capture callchains */ 374 #define PMC_F_USERCALLCHAIN 0x00000100 /*OP ALLOCATE use userspace stack */ 375 376 /* V10 API */ 377 #define PMC_F_EV_PMU 0x00000200 /* 378 * OP ALLOCATE: pm_ev has special 379 * userspace meaning; counter 380 * configuration is communicated 381 * through class-dependent fields 382 */ 383 384 /* internal flags */ 385 #define PMC_F_ATTACHED_TO_OWNER 0x00010000 /*attached to owner*/ 386 #define PMC_F_NEEDS_LOGFILE 0x00020000 /*needs log file */ 387 #define PMC_F_ATTACH_DONE 0x00040000 /*attached at least once */ 388 389 #define PMC_CALLCHAIN_DEPTH_MAX 512 390 391 #define PMC_CC_F_USERSPACE 0x01 /*userspace callchain*/ 392 #define PMC_CC_F_MULTIPART 0x02 /*multipart data*/ 393 394 /* 395 * Cookies used to denote allocated PMCs, and the values of PMCs. 396 */ 397 398 typedef uint32_t pmc_id_t; 399 typedef uint64_t pmc_value_t; 400 401 #define PMC_ID_INVALID (~ (pmc_id_t) 0) 402 403 /* 404 * PMC IDs have the following format: 405 * 406 * +-----------------------+-------+-----------+ 407 * | CPU | PMC MODE | CLASS | ROW INDEX | 408 * +-----------------------+-------+-----------+ 409 * 410 * where CPU is 12 bits, MODE 4, CLASS 8, and ROW INDEX 8 Field 'CPU' 411 * is set to the requested CPU for system-wide PMCs or PMC_CPU_ANY for 412 * process-mode PMCs. Field 'PMC MODE' is the allocated PMC mode. 413 * Field 'PMC CLASS' is the class of the PMC. Field 'ROW INDEX' is the 414 * row index for the PMC. 415 * 416 * The 'ROW INDEX' ranges over 0..NWPMCS where NHWPMCS is the total 417 * number of hardware PMCs on this cpu. 418 */ 419 420 #define PMC_ID_TO_ROWINDEX(ID) ((ID) & 0xFF) 421 #define PMC_ID_TO_CLASS(ID) (((ID) & 0xFF00) >> 8) 422 #define PMC_ID_TO_MODE(ID) (((ID) & 0xF0000) >> 16) 423 #define PMC_ID_TO_CPU(ID) (((ID) & 0xFFF00000) >> 20) 424 #define PMC_ID_MAKE_ID(CPU,MODE,CLASS,ROWINDEX) \ 425 ((((CPU) & 0xFFF) << 20) | (((MODE) & 0xF) << 16) | \ 426 (((CLASS) & 0xFF) << 8) | ((ROWINDEX) & 0xFF)) 427 428 /* 429 * Data structures for system calls supported by the pmc driver. 430 */ 431 432 /* 433 * OP PMCALLOCATE 434 * 435 * Allocate a PMC on the named CPU. 436 */ 437 438 #define PMC_CPU_ANY ~0 439 440 struct pmc_op_pmcallocate { 441 uint32_t pm_caps; /* PMC_CAP_* */ 442 uint32_t pm_cpu; /* CPU number or PMC_CPU_ANY */ 443 enum pmc_class pm_class; /* class of PMC desired */ 444 enum pmc_event pm_ev; /* [enum pmc_event] desired */ 445 uint32_t pm_flags; /* additional modifiers PMC_F_* */ 446 enum pmc_mode pm_mode; /* desired mode */ 447 pmc_id_t pm_pmcid; /* [return] process pmc id */ 448 pmc_value_t pm_count; /* initial/sample count */ 449 450 union pmc_md_op_pmcallocate pm_md; /* MD layer extensions */ 451 }; 452 453 /* 454 * OP PMCADMIN 455 * 456 * Set the administrative state (i.e., whether enabled or disabled) of 457 * a PMC 'pm_pmc' on CPU 'pm_cpu'. Note that 'pm_pmc' specifies an 458 * absolute PMC number and need not have been first allocated by the 459 * calling process. 460 */ 461 462 struct pmc_op_pmcadmin { 463 int pm_cpu; /* CPU# */ 464 uint32_t pm_flags; /* flags */ 465 int pm_pmc; /* PMC# */ 466 enum pmc_state pm_state; /* desired state */ 467 }; 468 469 /* 470 * OP PMCATTACH / OP PMCDETACH 471 * 472 * Attach/detach a PMC and a process. 473 */ 474 475 struct pmc_op_pmcattach { 476 pmc_id_t pm_pmc; /* PMC to attach to */ 477 pid_t pm_pid; /* target process */ 478 }; 479 480 /* 481 * OP PMCSETCOUNT 482 * 483 * Set the sampling rate (i.e., the reload count) for statistical counters. 484 * 'pm_pmcid' need to have been previously allocated using PMCALLOCATE. 485 */ 486 487 struct pmc_op_pmcsetcount { 488 pmc_value_t pm_count; /* initial/sample count */ 489 pmc_id_t pm_pmcid; /* PMC id to set */ 490 }; 491 492 /* 493 * OP PMCRW 494 * 495 * Read the value of a PMC named by 'pm_pmcid'. 'pm_pmcid' needs 496 * to have been previously allocated using PMCALLOCATE. 497 */ 498 499 struct pmc_op_pmcrw { 500 uint32_t pm_flags; /* PMC_F_{OLD,NEW}VALUE*/ 501 pmc_id_t pm_pmcid; /* pmc id */ 502 pmc_value_t pm_value; /* new&returned value */ 503 }; 504 505 /* 506 * OP GETPMCINFO 507 * 508 * retrieve PMC state for a named CPU. The caller is expected to 509 * allocate 'npmc' * 'struct pmc_info' bytes of space for the return 510 * values. 511 */ 512 513 struct pmc_info { 514 char pm_name[PMC_NAME_MAX]; /* pmc name */ 515 enum pmc_class pm_class; /* enum pmc_class */ 516 int pm_enabled; /* whether enabled */ 517 enum pmc_disp pm_rowdisp; /* FREE, THREAD or STANDLONE */ 518 pid_t pm_ownerpid; /* owner, or -1 */ 519 enum pmc_mode pm_mode; /* current mode [enum pmc_mode] */ 520 enum pmc_event pm_event; /* current event */ 521 uint32_t pm_flags; /* current flags */ 522 pmc_value_t pm_reloadcount; /* sampling counters only */ 523 }; 524 525 struct pmc_op_getpmcinfo { 526 int32_t pm_cpu; /* 0 <= cpu < mp_maxid */ 527 struct pmc_info pm_pmcs[]; /* space for 'npmc' structures */ 528 }; 529 530 /* 531 * OP GETCPUINFO 532 * 533 * Retrieve system CPU information. 534 */ 535 536 struct pmc_classinfo { 537 enum pmc_class pm_class; /* class id */ 538 uint32_t pm_caps; /* counter capabilities */ 539 uint32_t pm_width; /* width of the PMC */ 540 uint32_t pm_num; /* number of PMCs in class */ 541 }; 542 543 struct pmc_op_getcpuinfo { 544 enum pmc_cputype pm_cputype; /* what kind of CPU */ 545 uint32_t pm_ncpu; /* max CPU number */ 546 uint32_t pm_npmc; /* #PMCs per CPU */ 547 uint32_t pm_nclass; /* #classes of PMCs */ 548 struct pmc_classinfo pm_classes[PMC_CLASS_MAX]; 549 }; 550 551 /* 552 * OP CONFIGURELOG 553 * 554 * Configure a log file for writing system-wide statistics to. 555 */ 556 557 struct pmc_op_configurelog { 558 int pm_flags; 559 int pm_logfd; /* logfile fd (or -1) */ 560 }; 561 562 /* 563 * OP GETDRIVERSTATS 564 * 565 * Retrieve pmc(4) driver-wide statistics. 566 */ 567 #ifdef _KERNEL 568 struct pmc_driverstats { 569 counter_u64_t pm_intr_ignored; /* #interrupts ignored */ 570 counter_u64_t pm_intr_processed; /* #interrupts processed */ 571 counter_u64_t pm_intr_bufferfull; /* #interrupts with ENOSPC */ 572 counter_u64_t pm_syscalls; /* #syscalls */ 573 counter_u64_t pm_syscall_errors; /* #syscalls with errors */ 574 counter_u64_t pm_buffer_requests; /* #buffer requests */ 575 counter_u64_t pm_buffer_requests_failed; /* #failed buffer requests */ 576 counter_u64_t pm_log_sweeps; /* #sample buffer processing 577 passes */ 578 counter_u64_t pm_merges; /* merged k+u */ 579 counter_u64_t pm_overwrites; /* UR overwrites */ 580 }; 581 #endif 582 583 struct pmc_op_getdriverstats { 584 unsigned int pm_intr_ignored; /* #interrupts ignored */ 585 unsigned int pm_intr_processed; /* #interrupts processed */ 586 unsigned int pm_intr_bufferfull; /* #interrupts with ENOSPC */ 587 unsigned int pm_syscalls; /* #syscalls */ 588 unsigned int pm_syscall_errors; /* #syscalls with errors */ 589 unsigned int pm_buffer_requests; /* #buffer requests */ 590 unsigned int pm_buffer_requests_failed; /* #failed buffer requests */ 591 unsigned int pm_log_sweeps; /* #sample buffer processing 592 passes */ 593 }; 594 595 /* 596 * OP RELEASE / OP START / OP STOP 597 * 598 * Simple operations on a PMC id. 599 */ 600 601 struct pmc_op_simple { 602 pmc_id_t pm_pmcid; 603 }; 604 605 /* 606 * OP WRITELOG 607 * 608 * Flush the current log buffer and write 4 bytes of user data to it. 609 */ 610 611 struct pmc_op_writelog { 612 uint32_t pm_userdata; 613 }; 614 615 /* 616 * OP GETMSR 617 * 618 * Retrieve the machine specific address associated with the allocated 619 * PMC. This number can be used subsequently with a read-performance-counter 620 * instruction. 621 */ 622 623 struct pmc_op_getmsr { 624 uint32_t pm_msr; /* machine specific address */ 625 pmc_id_t pm_pmcid; /* allocated pmc id */ 626 }; 627 628 /* 629 * OP GETDYNEVENTINFO 630 * 631 * Retrieve a PMC dynamic class events list. 632 */ 633 634 struct pmc_dyn_event_descr { 635 char pm_ev_name[PMC_NAME_MAX]; 636 enum pmc_event pm_ev_code; 637 }; 638 639 struct pmc_op_getdyneventinfo { 640 enum pmc_class pm_class; 641 unsigned int pm_nevent; 642 struct pmc_dyn_event_descr pm_events[PMC_EV_DYN_COUNT]; 643 }; 644 645 /* 646 * OP GETCAPS 647 * 648 * Retrieve the PMC capabilties flags for this type of counter. 649 */ 650 651 struct pmc_op_caps { 652 pmc_id_t pm_pmcid; /* allocated pmc id */ 653 uint32_t pm_caps; /* capabilities */ 654 }; 655 656 #ifdef _KERNEL 657 658 #include <sys/malloc.h> 659 #include <sys/sysctl.h> 660 #include <sys/_cpuset.h> 661 662 #include <machine/frame.h> 663 664 #define PMC_HASH_SIZE 1024 665 #define PMC_MTXPOOL_SIZE 2048 666 #define PMC_LOG_BUFFER_SIZE 256 667 #define PMC_LOG_BUFFER_SIZE_MAX (16 * 1024) 668 #define PMC_NLOGBUFFERS_PCPU 32 669 #define PMC_NLOGBUFFERS_PCPU_MEM_MAX (32 * 1024) 670 #define PMC_NSAMPLES 256 671 #define PMC_CALLCHAIN_DEPTH 128 672 #define PMC_THREADLIST_MAX 128 673 674 #define PMC_SYSCTL_NAME_PREFIX "kern." PMC_MODULE_NAME "." 675 676 /* 677 * Locking keys 678 * 679 * (b) - pmc_bufferlist_mtx (spin lock) 680 * (k) - pmc_kthread_mtx (sleep lock) 681 * (o) - po->po_mtx (spin lock) 682 * (g) - global_epoch_preempt (epoch) 683 * (p) - pmc_sx (sx) 684 */ 685 686 /* 687 * PMC commands 688 */ 689 690 struct pmc_syscall_args { 691 register_t pmop_code; /* one of PMC_OP_* */ 692 void *pmop_data; /* syscall parameter */ 693 }; 694 695 /* 696 * Interface to processor specific s1tuff 697 */ 698 699 /* 700 * struct pmc_descr 701 * 702 * Machine independent (i.e., the common parts) of a human readable 703 * PMC description. 704 */ 705 706 struct pmc_descr { 707 char pd_name[PMC_NAME_MAX]; /* name */ 708 uint32_t pd_caps; /* capabilities */ 709 enum pmc_class pd_class; /* class of the PMC */ 710 uint32_t pd_width; /* width in bits */ 711 }; 712 713 /* 714 * struct pmc_target 715 * 716 * This structure records all the target processes associated with a 717 * PMC. 718 */ 719 720 struct pmc_target { 721 LIST_ENTRY(pmc_target) pt_next; 722 struct pmc_process *pt_process; /* target descriptor */ 723 }; 724 725 /* 726 * struct pmc 727 * 728 * Describes each allocated PMC. 729 * 730 * Each PMC has precisely one owner, namely the process that allocated 731 * the PMC. 732 * 733 * A PMC may be attached to multiple target processes. The 734 * 'pm_targets' field links all the target processes being monitored 735 * by this PMC. 736 * 737 * The 'pm_savedvalue' field is protected by a mutex. 738 * 739 * On a multi-cpu machine, multiple target threads associated with a 740 * process-virtual PMC could be concurrently executing on different 741 * CPUs. The 'pm_runcount' field is atomically incremented every time 742 * the PMC gets scheduled on a CPU and atomically decremented when it 743 * get descheduled. Deletion of a PMC is only permitted when this 744 * field is '0'. 745 * 746 */ 747 struct pmc_pcpu_state { 748 uint32_t pps_overflowcnt; /* count overflow interrupts */ 749 uint8_t pps_stalled; 750 uint8_t pps_cpustate; 751 } __aligned(CACHE_LINE_SIZE); 752 struct pmc { 753 LIST_HEAD(,pmc_target) pm_targets; /* list of target processes */ 754 LIST_ENTRY(pmc) pm_next; /* owner's list */ 755 756 /* 757 * System-wide PMCs are allocated on a CPU and are not moved 758 * around. For system-wide PMCs we record the CPU the PMC was 759 * allocated on in the 'CPU' field of the pmc ID. 760 * 761 * Virtual PMCs run on whichever CPU is currently executing 762 * their targets' threads. For these PMCs we need to save 763 * their current PMC counter values when they are taken off 764 * CPU. 765 */ 766 767 union { 768 pmc_value_t pm_savedvalue; /* Virtual PMCS */ 769 } pm_gv; 770 771 /* 772 * For sampling mode PMCs, we keep track of the PMC's "reload 773 * count", which is the counter value to be loaded in when 774 * arming the PMC for the next counting session. For counting 775 * modes on PMCs that are read-only (e.g., the x86 TSC), we 776 * keep track of the initial value at the start of 777 * counting-mode operation. 778 */ 779 780 union { 781 pmc_value_t pm_reloadcount; /* sampling PMC modes */ 782 pmc_value_t pm_initial; /* counting PMC modes */ 783 } pm_sc; 784 785 struct pmc_pcpu_state *pm_pcpu_state; 786 volatile cpuset_t pm_cpustate; /* CPUs where PMC should be active */ 787 uint32_t pm_caps; /* PMC capabilities */ 788 enum pmc_event pm_event; /* event being measured */ 789 uint32_t pm_flags; /* additional flags PMC_F_... */ 790 struct pmc_owner *pm_owner; /* owner thread state */ 791 counter_u64_t pm_runcount; /* #cpus currently on */ 792 enum pmc_state pm_state; /* current PMC state */ 793 794 /* 795 * The PMC ID field encodes the row-index for the PMC, its 796 * mode, class and the CPU# associated with the PMC. 797 */ 798 799 pmc_id_t pm_id; /* allocated PMC id */ 800 enum pmc_class pm_class; 801 802 /* md extensions */ 803 union pmc_md_pmc pm_md; 804 }; 805 806 /* 807 * Accessor macros for 'struct pmc' 808 */ 809 810 #define PMC_TO_MODE(P) PMC_ID_TO_MODE((P)->pm_id) 811 #define PMC_TO_CLASS(P) PMC_ID_TO_CLASS((P)->pm_id) 812 #define PMC_TO_ROWINDEX(P) PMC_ID_TO_ROWINDEX((P)->pm_id) 813 #define PMC_TO_CPU(P) PMC_ID_TO_CPU((P)->pm_id) 814 815 /* 816 * struct pmc_threadpmcstate 817 * 818 * Record per-PMC, per-thread state. 819 */ 820 struct pmc_threadpmcstate { 821 pmc_value_t pt_pmcval; /* per-thread reload count */ 822 }; 823 824 /* 825 * struct pmc_thread 826 * 827 * Record a 'target' thread being profiled. 828 */ 829 struct pmc_thread { 830 LIST_ENTRY(pmc_thread) pt_next; /* linked list */ 831 struct thread *pt_td; /* target thread */ 832 struct pmc_threadpmcstate pt_pmcs[]; /* per-PMC state */ 833 }; 834 835 /* 836 * struct pmc_process 837 * 838 * Record a 'target' process being profiled. 839 * 840 * The target process being profiled could be different from the owner 841 * process which allocated the PMCs. Each target process descriptor 842 * is associated with NHWPMC 'struct pmc *' pointers. Each PMC at a 843 * given hardware row-index 'n' will use slot 'n' of the 'pp_pmcs[]' 844 * array. The size of this structure is thus PMC architecture 845 * dependent. 846 * 847 */ 848 849 struct pmc_targetstate { 850 struct pmc *pp_pmc; /* target PMC */ 851 pmc_value_t pp_pmcval; /* per-process value */ 852 }; 853 854 struct pmc_process { 855 LIST_ENTRY(pmc_process) pp_next; /* hash chain */ 856 LIST_HEAD(,pmc_thread) pp_tds; /* list of threads */ 857 struct mtx *pp_tdslock; /* lock on pp_tds thread list */ 858 int pp_refcnt; /* reference count */ 859 uint32_t pp_flags; /* flags PMC_PP_* */ 860 struct proc *pp_proc; /* target process */ 861 struct pmc_targetstate pp_pmcs[]; /* NHWPMCs */ 862 }; 863 864 #define PMC_PP_ENABLE_MSR_ACCESS 0x00000001 865 866 /* 867 * struct pmc_owner 868 * 869 * We associate a PMC with an 'owner' process. 870 * 871 * A process can be associated with 0..NCPUS*NHWPMC PMCs during its 872 * lifetime, where NCPUS is the numbers of CPUS in the system and 873 * NHWPMC is the number of hardware PMCs per CPU. These are 874 * maintained in the list headed by the 'po_pmcs' to save on space. 875 * 876 */ 877 878 struct pmc_owner { 879 LIST_ENTRY(pmc_owner) po_next; /* hash chain */ 880 CK_LIST_ENTRY(pmc_owner) po_ssnext; /* (g/p) list of SS PMC owners */ 881 LIST_HEAD(, pmc) po_pmcs; /* owned PMC list */ 882 TAILQ_HEAD(, pmclog_buffer) po_logbuffers; /* (o) logbuffer list */ 883 struct mtx po_mtx; /* spin lock for (o) */ 884 struct proc *po_owner; /* owner proc */ 885 uint32_t po_flags; /* (k) flags PMC_PO_* */ 886 struct proc *po_kthread; /* (k) helper kthread */ 887 struct file *po_file; /* file reference */ 888 int po_error; /* recorded error */ 889 short po_sscount; /* # SS PMCs owned */ 890 short po_logprocmaps; /* global mappings done */ 891 struct pmclog_buffer *po_curbuf[MAXCPU]; /* current log buffer */ 892 }; 893 894 #define PMC_PO_OWNS_LOGFILE 0x00000001 /* has a log file */ 895 #define PMC_PO_SHUTDOWN 0x00000010 /* in the process of shutdown */ 896 #define PMC_PO_INITIAL_MAPPINGS_DONE 0x00000020 897 898 /* 899 * struct pmc_hw -- describe the state of the PMC hardware 900 * 901 * When in use, a HW PMC is associated with one allocated 'struct pmc' 902 * pointed to by field 'phw_pmc'. When inactive, this field is NULL. 903 * 904 * On an SMP box, one or more HW PMC's in process virtual mode with 905 * the same 'phw_pmc' could be executing on different CPUs. In order 906 * to handle this case correctly, we need to ensure that only 907 * incremental counts get added to the saved value in the associated 908 * 'struct pmc'. The 'phw_save' field is used to keep the saved PMC 909 * value at the time the hardware is started during this context 910 * switch (i.e., the difference between the new (hardware) count and 911 * the saved count is atomically added to the count field in 'struct 912 * pmc' at context switch time). 913 * 914 */ 915 916 struct pmc_hw { 917 uint32_t phw_state; /* see PHW_* macros below */ 918 struct pmc *phw_pmc; /* current thread PMC */ 919 }; 920 921 #define PMC_PHW_RI_MASK 0x000000FF 922 #define PMC_PHW_CPU_SHIFT 8 923 #define PMC_PHW_CPU_MASK 0x0000FF00 924 #define PMC_PHW_FLAGS_SHIFT 16 925 #define PMC_PHW_FLAGS_MASK 0xFFFF0000 926 927 #define PMC_PHW_INDEX_TO_STATE(ri) ((ri) & PMC_PHW_RI_MASK) 928 #define PMC_PHW_STATE_TO_INDEX(state) ((state) & PMC_PHW_RI_MASK) 929 #define PMC_PHW_CPU_TO_STATE(cpu) (((cpu) << PMC_PHW_CPU_SHIFT) & \ 930 PMC_PHW_CPU_MASK) 931 #define PMC_PHW_STATE_TO_CPU(state) (((state) & PMC_PHW_CPU_MASK) >> \ 932 PMC_PHW_CPU_SHIFT) 933 #define PMC_PHW_FLAGS_TO_STATE(flags) (((flags) << PMC_PHW_FLAGS_SHIFT) & \ 934 PMC_PHW_FLAGS_MASK) 935 #define PMC_PHW_STATE_TO_FLAGS(state) (((state) & PMC_PHW_FLAGS_MASK) >> \ 936 PMC_PHW_FLAGS_SHIFT) 937 #define PMC_PHW_FLAG_IS_ENABLED (PMC_PHW_FLAGS_TO_STATE(0x01)) 938 #define PMC_PHW_FLAG_IS_SHAREABLE (PMC_PHW_FLAGS_TO_STATE(0x02)) 939 940 /* 941 * struct pmc_sample 942 * 943 * Space for N (tunable) PC samples and associated control data. 944 */ 945 946 struct pmc_sample { 947 uint16_t ps_nsamples; /* callchain depth */ 948 uint16_t ps_nsamples_actual; 949 uint16_t ps_cpu; /* cpu number */ 950 uint16_t ps_flags; /* other flags */ 951 lwpid_t ps_tid; /* thread id */ 952 pid_t ps_pid; /* process PID or -1 */ 953 int ps_ticks; /* ticks at sample time */ 954 /* pad */ 955 struct thread *ps_td; /* which thread */ 956 struct pmc *ps_pmc; /* interrupting PMC */ 957 uintptr_t *ps_pc; /* (const) callchain start */ 958 uint64_t ps_tsc; /* tsc value */ 959 }; 960 961 #define PMC_SAMPLE_FREE ((uint16_t) 0) 962 #define PMC_USER_CALLCHAIN_PENDING ((uint16_t) 0xFFFF) 963 964 struct pmc_samplebuffer { 965 volatile uint64_t ps_prodidx; /* producer index */ 966 volatile uint64_t ps_considx; /* consumer index */ 967 uintptr_t *ps_callchains; /* all saved call chains */ 968 struct pmc_sample ps_samples[]; /* array of sample entries */ 969 }; 970 971 #define PMC_CONS_SAMPLE(psb) \ 972 (&(psb)->ps_samples[(psb)->ps_considx & pmc_sample_mask]) 973 974 #define PMC_CONS_SAMPLE_OFF(psb, off) \ 975 (&(psb)->ps_samples[(off) & pmc_sample_mask]) 976 977 #define PMC_PROD_SAMPLE(psb) \ 978 (&(psb)->ps_samples[(psb)->ps_prodidx & pmc_sample_mask]) 979 980 981 /* 982 * struct pmc_multipart 983 * 984 * Multipart payload 985 */ 986 struct pmc_multipart { 987 char pl_type; 988 char pl_length; 989 uint64_t pl_mpdata[10]; 990 }; 991 992 /* 993 * struct pmc_cpustate 994 * 995 * A CPU is modelled as a collection of HW PMCs with space for additional 996 * flags. 997 */ 998 999 struct pmc_cpu { 1000 uint32_t pc_state; /* physical cpu number + flags */ 1001 struct pmc_samplebuffer *pc_sb[3]; /* space for samples */ 1002 struct pmc_hw *pc_hwpmcs[]; /* 'npmc' pointers */ 1003 }; 1004 1005 #define PMC_PCPU_CPU_MASK 0x000000FF 1006 #define PMC_PCPU_FLAGS_MASK 0xFFFFFF00 1007 #define PMC_PCPU_FLAGS_SHIFT 8 1008 #define PMC_PCPU_STATE_TO_CPU(S) ((S) & PMC_PCPU_CPU_MASK) 1009 #define PMC_PCPU_STATE_TO_FLAGS(S) (((S) & PMC_PCPU_FLAGS_MASK) >> PMC_PCPU_FLAGS_SHIFT) 1010 #define PMC_PCPU_FLAGS_TO_STATE(F) (((F) << PMC_PCPU_FLAGS_SHIFT) & PMC_PCPU_FLAGS_MASK) 1011 #define PMC_PCPU_CPU_TO_STATE(C) ((C) & PMC_PCPU_CPU_MASK) 1012 #define PMC_PCPU_FLAG_HTT (PMC_PCPU_FLAGS_TO_STATE(0x1)) 1013 1014 /* 1015 * struct pmc_binding 1016 * 1017 * CPU binding information. 1018 */ 1019 1020 struct pmc_binding { 1021 int pb_bound; /* is bound? */ 1022 int pb_cpu; /* if so, to which CPU */ 1023 u_char pb_priority; /* Thread active priority. */ 1024 }; 1025 1026 struct pmc_mdep; 1027 1028 /* 1029 * struct pmc_classdep 1030 * 1031 * PMC class-dependent operations. 1032 */ 1033 struct pmc_classdep { 1034 uint32_t pcd_caps; /* class capabilities */ 1035 enum pmc_class pcd_class; /* class id */ 1036 int pcd_num; /* number of PMCs */ 1037 int pcd_ri; /* row index of the first PMC in class */ 1038 int pcd_width; /* width of the PMC */ 1039 1040 /* configuring/reading/writing the hardware PMCs */ 1041 int (*pcd_config_pmc)(int _cpu, int _ri, struct pmc *_pm); 1042 int (*pcd_get_config)(int _cpu, int _ri, struct pmc **_ppm); 1043 int (*pcd_read_pmc)(int _cpu, int _ri, struct pmc *_pm, 1044 pmc_value_t *_value); 1045 int (*pcd_write_pmc)(int _cpu, int _ri, struct pmc *_pm, 1046 pmc_value_t _value); 1047 1048 /* pmc allocation/release */ 1049 int (*pcd_allocate_pmc)(int _cpu, int _ri, struct pmc *_t, 1050 const struct pmc_op_pmcallocate *_a); 1051 int (*pcd_release_pmc)(int _cpu, int _ri, struct pmc *_pm); 1052 1053 /* starting and stopping PMCs */ 1054 int (*pcd_start_pmc)(int _cpu, int _ri, struct pmc *_pm); 1055 int (*pcd_stop_pmc)(int _cpu, int _ri, struct pmc *_pm); 1056 1057 /* description */ 1058 int (*pcd_describe)(int _cpu, int _ri, struct pmc_info *_pi, 1059 struct pmc **_ppmc); 1060 int (*pcd_get_caps)(int _ri, uint32_t *_caps); 1061 1062 /* class-dependent initialization & finalization */ 1063 int (*pcd_pcpu_init)(struct pmc_mdep *_md, int _cpu); 1064 int (*pcd_pcpu_fini)(struct pmc_mdep *_md, int _cpu); 1065 1066 /* machine-specific interface */ 1067 int (*pcd_get_msr)(int _ri, uint32_t *_msr); 1068 }; 1069 1070 /* 1071 * struct pmc_mdep 1072 * 1073 * Machine dependent bits needed per CPU type. 1074 */ 1075 1076 struct pmc_mdep { 1077 uint32_t pmd_cputype; /* from enum pmc_cputype */ 1078 uint32_t pmd_npmc; /* number of PMCs per CPU */ 1079 uint32_t pmd_nclass; /* number of PMC classes present */ 1080 1081 /* 1082 * Machine dependent methods. 1083 */ 1084 1085 /* thread context switch in/out */ 1086 int (*pmd_switch_in)(struct pmc_cpu *_p, struct pmc_process *_pp); 1087 int (*pmd_switch_out)(struct pmc_cpu *_p, struct pmc_process *_pp); 1088 1089 /* handle a PMC interrupt */ 1090 int (*pmd_intr)(struct trapframe *_tf); 1091 1092 /* 1093 * PMC class dependent information. 1094 */ 1095 struct pmc_classdep pmd_classdep[]; 1096 }; 1097 1098 /* 1099 * Per-CPU state. This is an array of 'mp_ncpu' pointers 1100 * to struct pmc_cpu descriptors. 1101 */ 1102 1103 extern struct pmc_cpu **pmc_pcpu; 1104 1105 /* driver statistics */ 1106 extern struct pmc_driverstats pmc_stats; 1107 1108 #if defined(HWPMC_DEBUG) 1109 1110 /* HWPMC_DEBUG without KTR will compile but is a no-op. */ 1111 #if !defined(KTR) || !defined(KTR_COMPILE) || ((KTR_COMPILE & KTR_SUBSYS) == 0) 1112 #error "HWPMC_DEBUG requires KTR and KTR_COMPILE=KTR_SUBSYS -- see ktr(4)" 1113 #endif 1114 1115 #include <sys/ktr.h> 1116 1117 #define __pmcdbg_used /* unused variable annotation */ 1118 1119 /* 1120 * Debug flags, major flag groups. 1121 * 1122 * Please keep the DEBUGGING section of the hwpmc(4) man page in sync. 1123 */ 1124 struct pmc_debugflags { 1125 int pdb_CPU; 1126 int pdb_CSW; 1127 int pdb_LOG; 1128 int pdb_MDP; 1129 int pdb_MOD; 1130 int pdb_OWN; 1131 int pdb_PMC; 1132 int pdb_PRC; 1133 int pdb_SAM; 1134 }; 1135 1136 extern struct pmc_debugflags pmc_debugflags; 1137 1138 #define KTR_PMC KTR_SUBSYS 1139 1140 #define PMC_DEBUG_STRSIZE 128 1141 #define PMC_DEBUG_DEFAULT_FLAGS { 0, 0, 0, 0, 0, 0, 0, 0, 0 } 1142 1143 #define PMCDBG0(M, N, L, F) do { \ 1144 if (pmc_debugflags.pdb_ ## M & (1 << PMC_DEBUG_MIN_ ## N)) \ 1145 CTR0(KTR_PMC, #M ":" #N ":" #L ": " F); \ 1146 } while (0) 1147 #define PMCDBG1(M, N, L, F, p1) do { \ 1148 if (pmc_debugflags.pdb_ ## M & (1 << PMC_DEBUG_MIN_ ## N)) \ 1149 CTR1(KTR_PMC, #M ":" #N ":" #L ": " F, p1); \ 1150 } while (0) 1151 #define PMCDBG2(M, N, L, F, p1, p2) do { \ 1152 if (pmc_debugflags.pdb_ ## M & (1 << PMC_DEBUG_MIN_ ## N)) \ 1153 CTR2(KTR_PMC, #M ":" #N ":" #L ": " F, p1, p2); \ 1154 } while (0) 1155 #define PMCDBG3(M, N, L, F, p1, p2, p3) do { \ 1156 if (pmc_debugflags.pdb_ ## M & (1 << PMC_DEBUG_MIN_ ## N)) \ 1157 CTR3(KTR_PMC, #M ":" #N ":" #L ": " F, p1, p2, p3); \ 1158 } while (0) 1159 #define PMCDBG4(M, N, L, F, p1, p2, p3, p4) do { \ 1160 if (pmc_debugflags.pdb_ ## M & (1 << PMC_DEBUG_MIN_ ## N)) \ 1161 CTR4(KTR_PMC, #M ":" #N ":" #L ": " F, p1, p2, p3, p4);\ 1162 } while (0) 1163 #define PMCDBG5(M, N, L, F, p1, p2, p3, p4, p5) do { \ 1164 if (pmc_debugflags.pdb_ ## M & (1 << PMC_DEBUG_MIN_ ## N)) \ 1165 CTR5(KTR_PMC, #M ":" #N ":" #L ": " F, p1, p2, p3, p4, \ 1166 p5); \ 1167 } while (0) 1168 #define PMCDBG6(M, N, L, F, p1, p2, p3, p4, p5, p6) do { \ 1169 if (pmc_debugflags.pdb_ ## M & (1 << PMC_DEBUG_MIN_ ## N)) \ 1170 CTR6(KTR_PMC, #M ":" #N ":" #L ": " F, p1, p2, p3, p4, \ 1171 p5, p6); \ 1172 } while (0) 1173 1174 /* Major numbers */ 1175 #define PMC_DEBUG_MAJ_CPU 0 /* cpu switches */ 1176 #define PMC_DEBUG_MAJ_CSW 1 /* context switches */ 1177 #define PMC_DEBUG_MAJ_LOG 2 /* logging */ 1178 #define PMC_DEBUG_MAJ_MDP 3 /* machine dependent */ 1179 #define PMC_DEBUG_MAJ_MOD 4 /* misc module infrastructure */ 1180 #define PMC_DEBUG_MAJ_OWN 5 /* owner */ 1181 #define PMC_DEBUG_MAJ_PMC 6 /* pmc management */ 1182 #define PMC_DEBUG_MAJ_PRC 7 /* processes */ 1183 #define PMC_DEBUG_MAJ_SAM 8 /* sampling */ 1184 1185 /* Minor numbers */ 1186 1187 /* Common (8 bits) */ 1188 #define PMC_DEBUG_MIN_ALL 0 /* allocation */ 1189 #define PMC_DEBUG_MIN_REL 1 /* release */ 1190 #define PMC_DEBUG_MIN_OPS 2 /* ops: start, stop, ... */ 1191 #define PMC_DEBUG_MIN_INI 3 /* init */ 1192 #define PMC_DEBUG_MIN_FND 4 /* find */ 1193 1194 /* MODULE */ 1195 #define PMC_DEBUG_MIN_PMH 14 /* pmc_hook */ 1196 #define PMC_DEBUG_MIN_PMS 15 /* pmc_syscall */ 1197 1198 /* OWN */ 1199 #define PMC_DEBUG_MIN_ORM 8 /* owner remove */ 1200 #define PMC_DEBUG_MIN_OMR 9 /* owner maybe remove */ 1201 1202 /* PROCESSES */ 1203 #define PMC_DEBUG_MIN_TLK 8 /* link target */ 1204 #define PMC_DEBUG_MIN_TUL 9 /* unlink target */ 1205 #define PMC_DEBUG_MIN_EXT 10 /* process exit */ 1206 #define PMC_DEBUG_MIN_EXC 11 /* process exec */ 1207 #define PMC_DEBUG_MIN_FRK 12 /* process fork */ 1208 #define PMC_DEBUG_MIN_ATT 13 /* attach/detach */ 1209 #define PMC_DEBUG_MIN_SIG 14 /* signalling */ 1210 1211 /* CONTEXT SWITCHES */ 1212 #define PMC_DEBUG_MIN_SWI 8 /* switch in */ 1213 #define PMC_DEBUG_MIN_SWO 9 /* switch out */ 1214 1215 /* PMC */ 1216 #define PMC_DEBUG_MIN_REG 8 /* pmc register */ 1217 #define PMC_DEBUG_MIN_ALR 9 /* allocate row */ 1218 1219 /* MACHINE DEPENDENT LAYER */ 1220 #define PMC_DEBUG_MIN_REA 8 /* read */ 1221 #define PMC_DEBUG_MIN_WRI 9 /* write */ 1222 #define PMC_DEBUG_MIN_CFG 10 /* config */ 1223 #define PMC_DEBUG_MIN_STA 11 /* start */ 1224 #define PMC_DEBUG_MIN_STO 12 /* stop */ 1225 #define PMC_DEBUG_MIN_INT 13 /* interrupts */ 1226 1227 /* CPU */ 1228 #define PMC_DEBUG_MIN_BND 8 /* bind */ 1229 #define PMC_DEBUG_MIN_SEL 9 /* select */ 1230 1231 /* LOG */ 1232 #define PMC_DEBUG_MIN_GTB 8 /* get buf */ 1233 #define PMC_DEBUG_MIN_SIO 9 /* schedule i/o */ 1234 #define PMC_DEBUG_MIN_FLS 10 /* flush */ 1235 #define PMC_DEBUG_MIN_SAM 11 /* sample */ 1236 #define PMC_DEBUG_MIN_CLO 12 /* close */ 1237 1238 #else 1239 #define __pmcdbg_used __unused 1240 #define PMCDBG0(M, N, L, F) /* nothing */ 1241 #define PMCDBG1(M, N, L, F, p1) 1242 #define PMCDBG2(M, N, L, F, p1, p2) 1243 #define PMCDBG3(M, N, L, F, p1, p2, p3) 1244 #define PMCDBG4(M, N, L, F, p1, p2, p3, p4) 1245 #define PMCDBG5(M, N, L, F, p1, p2, p3, p4, p5) 1246 #define PMCDBG6(M, N, L, F, p1, p2, p3, p4, p5, p6) 1247 #endif 1248 1249 /* declare a dedicated memory pool */ 1250 MALLOC_DECLARE(M_PMC); 1251 1252 /* 1253 * Functions 1254 */ 1255 1256 struct pmc_mdep *pmc_md_initialize(void); /* MD init function */ 1257 void pmc_md_finalize(struct pmc_mdep *_md); /* MD fini function */ 1258 int pmc_getrowdisp(int _ri); 1259 int pmc_process_interrupt_mp(int _ring, struct pmc *_pm, 1260 struct trapframe *_tf, struct pmc_multipart *mp); 1261 int pmc_process_interrupt(int _ring, struct pmc *_pm, 1262 struct trapframe *_tf); 1263 int pmc_save_kernel_callchain(uintptr_t *_cc, int _maxsamples, 1264 struct trapframe *_tf); 1265 int pmc_save_user_callchain(uintptr_t *_cc, int _maxsamples, 1266 struct trapframe *_tf); 1267 void pmc_restore_cpu_binding(struct pmc_binding *pb); 1268 void pmc_save_cpu_binding(struct pmc_binding *pb); 1269 void pmc_select_cpu(int cpu); 1270 struct pmc_mdep *pmc_mdep_alloc(int nclasses); 1271 void pmc_mdep_free(struct pmc_mdep *md); 1272 uint64_t pmc_rdtsc(void); 1273 #endif /* _KERNEL */ 1274 #endif /* _SYS_PMC_H_ */ 1275