1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2014-2015, 2022 MediaTek Inc.
4 * Author: Chaotian.Jing <chaotian.jing@mediatek.com>
5 */
6
7 #include <linux/module.h>
8 #include <linux/bitfield.h>
9 #include <linux/bitops.h>
10 #include <linux/clk.h>
11 #include <linux/delay.h>
12 #include <linux/dma-mapping.h>
13 #include <linux/iopoll.h>
14 #include <linux/ioport.h>
15 #include <linux/irq.h>
16 #include <linux/of.h>
17 #include <linux/pinctrl/consumer.h>
18 #include <linux/platform_device.h>
19 #include <linux/pm.h>
20 #include <linux/pm_runtime.h>
21 #include <linux/pm_wakeirq.h>
22 #include <linux/regulator/consumer.h>
23 #include <linux/slab.h>
24 #include <linux/spinlock.h>
25 #include <linux/interrupt.h>
26 #include <linux/reset.h>
27
28 #include <linux/mmc/card.h>
29 #include <linux/mmc/core.h>
30 #include <linux/mmc/host.h>
31 #include <linux/mmc/mmc.h>
32 #include <linux/mmc/sd.h>
33 #include <linux/mmc/sdio.h>
34 #include <linux/mmc/slot-gpio.h>
35
36 #include "cqhci.h"
37 #include "mmc_hsq.h"
38
39 #define MAX_BD_NUM 1024
40 #define MSDC_NR_CLOCKS 3
41
42 /*--------------------------------------------------------------------------*/
43 /* Common Definition */
44 /*--------------------------------------------------------------------------*/
45 #define MSDC_BUS_1BITS 0x0
46 #define MSDC_BUS_4BITS 0x1
47 #define MSDC_BUS_8BITS 0x2
48
49 #define MSDC_BURST_64B 0x6
50
51 /*--------------------------------------------------------------------------*/
52 /* Register Offset */
53 /*--------------------------------------------------------------------------*/
54 #define MSDC_CFG 0x0
55 #define MSDC_IOCON 0x04
56 #define MSDC_PS 0x08
57 #define MSDC_INT 0x0c
58 #define MSDC_INTEN 0x10
59 #define MSDC_FIFOCS 0x14
60 #define SDC_CFG 0x30
61 #define SDC_CMD 0x34
62 #define SDC_ARG 0x38
63 #define SDC_STS 0x3c
64 #define SDC_RESP0 0x40
65 #define SDC_RESP1 0x44
66 #define SDC_RESP2 0x48
67 #define SDC_RESP3 0x4c
68 #define SDC_BLK_NUM 0x50
69 #define SDC_ADV_CFG0 0x64
70 #define MSDC_NEW_RX_CFG 0x68
71 #define EMMC_IOCON 0x7c
72 #define SDC_ACMD_RESP 0x80
73 #define DMA_SA_H4BIT 0x8c
74 #define MSDC_DMA_SA 0x90
75 #define MSDC_DMA_CTRL 0x98
76 #define MSDC_DMA_CFG 0x9c
77 #define MSDC_PATCH_BIT 0xb0
78 #define MSDC_PATCH_BIT1 0xb4
79 #define MSDC_PATCH_BIT2 0xb8
80 #define MSDC_PAD_TUNE 0xec
81 #define MSDC_PAD_TUNE0 0xf0
82 #define PAD_DS_TUNE 0x188
83 #define PAD_CMD_TUNE 0x18c
84 #define EMMC51_CFG0 0x204
85 #define EMMC50_CFG0 0x208
86 #define EMMC50_CFG1 0x20c
87 #define EMMC50_CFG2 0x21c
88 #define EMMC50_CFG3 0x220
89 #define SDC_FIFO_CFG 0x228
90 #define CQHCI_SETTING 0x7fc
91
92 /*--------------------------------------------------------------------------*/
93 /* Top Pad Register Offset */
94 /*--------------------------------------------------------------------------*/
95 #define EMMC_TOP_CONTROL 0x00
96 #define EMMC_TOP_CMD 0x04
97 #define EMMC50_PAD_DS_TUNE 0x0c
98 #define LOOP_TEST_CONTROL 0x30
99
100 /*--------------------------------------------------------------------------*/
101 /* Register Mask */
102 /*--------------------------------------------------------------------------*/
103
104 /* MSDC_CFG mask */
105 #define MSDC_CFG_MODE BIT(0) /* RW */
106 #define MSDC_CFG_CKPDN BIT(1) /* RW */
107 #define MSDC_CFG_RST BIT(2) /* RW */
108 #define MSDC_CFG_PIO BIT(3) /* RW */
109 #define MSDC_CFG_CKDRVEN BIT(4) /* RW */
110 #define MSDC_CFG_BV18SDT BIT(5) /* RW */
111 #define MSDC_CFG_BV18PSS BIT(6) /* R */
112 #define MSDC_CFG_CKSTB BIT(7) /* R */
113 #define MSDC_CFG_CKDIV GENMASK(15, 8) /* RW */
114 #define MSDC_CFG_CKMOD GENMASK(17, 16) /* RW */
115 #define MSDC_CFG_HS400_CK_MODE BIT(18) /* RW */
116 #define MSDC_CFG_HS400_CK_MODE_EXTRA BIT(22) /* RW */
117 #define MSDC_CFG_CKDIV_EXTRA GENMASK(19, 8) /* RW */
118 #define MSDC_CFG_CKMOD_EXTRA GENMASK(21, 20) /* RW */
119
120 /* MSDC_IOCON mask */
121 #define MSDC_IOCON_SDR104CKS BIT(0) /* RW */
122 #define MSDC_IOCON_RSPL BIT(1) /* RW */
123 #define MSDC_IOCON_DSPL BIT(2) /* RW */
124 #define MSDC_IOCON_DDLSEL BIT(3) /* RW */
125 #define MSDC_IOCON_DDR50CKD BIT(4) /* RW */
126 #define MSDC_IOCON_DSPLSEL BIT(5) /* RW */
127 #define MSDC_IOCON_W_DSPL BIT(8) /* RW */
128 #define MSDC_IOCON_D0SPL BIT(16) /* RW */
129 #define MSDC_IOCON_D1SPL BIT(17) /* RW */
130 #define MSDC_IOCON_D2SPL BIT(18) /* RW */
131 #define MSDC_IOCON_D3SPL BIT(19) /* RW */
132 #define MSDC_IOCON_D4SPL BIT(20) /* RW */
133 #define MSDC_IOCON_D5SPL BIT(21) /* RW */
134 #define MSDC_IOCON_D6SPL BIT(22) /* RW */
135 #define MSDC_IOCON_D7SPL BIT(23) /* RW */
136 #define MSDC_IOCON_RISCSZ GENMASK(25, 24) /* RW */
137
138 /* MSDC_PS mask */
139 #define MSDC_PS_CDEN BIT(0) /* RW */
140 #define MSDC_PS_CDSTS BIT(1) /* R */
141 #define MSDC_PS_CDDEBOUNCE GENMASK(15, 12) /* RW */
142 #define MSDC_PS_DAT GENMASK(23, 16) /* R */
143 #define MSDC_PS_DATA1 BIT(17) /* R */
144 #define MSDC_PS_CMD BIT(24) /* R */
145 #define MSDC_PS_WP BIT(31) /* R */
146
147 /* MSDC_INT mask */
148 #define MSDC_INT_MMCIRQ BIT(0) /* W1C */
149 #define MSDC_INT_CDSC BIT(1) /* W1C */
150 #define MSDC_INT_ACMDRDY BIT(3) /* W1C */
151 #define MSDC_INT_ACMDTMO BIT(4) /* W1C */
152 #define MSDC_INT_ACMDCRCERR BIT(5) /* W1C */
153 #define MSDC_INT_DMAQ_EMPTY BIT(6) /* W1C */
154 #define MSDC_INT_SDIOIRQ BIT(7) /* W1C */
155 #define MSDC_INT_CMDRDY BIT(8) /* W1C */
156 #define MSDC_INT_CMDTMO BIT(9) /* W1C */
157 #define MSDC_INT_RSPCRCERR BIT(10) /* W1C */
158 #define MSDC_INT_CSTA BIT(11) /* R */
159 #define MSDC_INT_XFER_COMPL BIT(12) /* W1C */
160 #define MSDC_INT_DXFER_DONE BIT(13) /* W1C */
161 #define MSDC_INT_DATTMO BIT(14) /* W1C */
162 #define MSDC_INT_DATCRCERR BIT(15) /* W1C */
163 #define MSDC_INT_ACMD19_DONE BIT(16) /* W1C */
164 #define MSDC_INT_DMA_BDCSERR BIT(17) /* W1C */
165 #define MSDC_INT_DMA_GPDCSERR BIT(18) /* W1C */
166 #define MSDC_INT_DMA_PROTECT BIT(19) /* W1C */
167 #define MSDC_INT_CMDQ BIT(28) /* W1C */
168
169 /* MSDC_INTEN mask */
170 #define MSDC_INTEN_MMCIRQ BIT(0) /* RW */
171 #define MSDC_INTEN_CDSC BIT(1) /* RW */
172 #define MSDC_INTEN_ACMDRDY BIT(3) /* RW */
173 #define MSDC_INTEN_ACMDTMO BIT(4) /* RW */
174 #define MSDC_INTEN_ACMDCRCERR BIT(5) /* RW */
175 #define MSDC_INTEN_DMAQ_EMPTY BIT(6) /* RW */
176 #define MSDC_INTEN_SDIOIRQ BIT(7) /* RW */
177 #define MSDC_INTEN_CMDRDY BIT(8) /* RW */
178 #define MSDC_INTEN_CMDTMO BIT(9) /* RW */
179 #define MSDC_INTEN_RSPCRCERR BIT(10) /* RW */
180 #define MSDC_INTEN_CSTA BIT(11) /* RW */
181 #define MSDC_INTEN_XFER_COMPL BIT(12) /* RW */
182 #define MSDC_INTEN_DXFER_DONE BIT(13) /* RW */
183 #define MSDC_INTEN_DATTMO BIT(14) /* RW */
184 #define MSDC_INTEN_DATCRCERR BIT(15) /* RW */
185 #define MSDC_INTEN_ACMD19_DONE BIT(16) /* RW */
186 #define MSDC_INTEN_DMA_BDCSERR BIT(17) /* RW */
187 #define MSDC_INTEN_DMA_GPDCSERR BIT(18) /* RW */
188 #define MSDC_INTEN_DMA_PROTECT BIT(19) /* RW */
189
190 /* MSDC_FIFOCS mask */
191 #define MSDC_FIFOCS_RXCNT GENMASK(7, 0) /* R */
192 #define MSDC_FIFOCS_TXCNT GENMASK(23, 16) /* R */
193 #define MSDC_FIFOCS_CLR BIT(31) /* RW */
194
195 /* SDC_CFG mask */
196 #define SDC_CFG_SDIOINTWKUP BIT(0) /* RW */
197 #define SDC_CFG_INSWKUP BIT(1) /* RW */
198 #define SDC_CFG_WRDTOC GENMASK(14, 2) /* RW */
199 #define SDC_CFG_BUSWIDTH GENMASK(17, 16) /* RW */
200 #define SDC_CFG_SDIO BIT(19) /* RW */
201 #define SDC_CFG_SDIOIDE BIT(20) /* RW */
202 #define SDC_CFG_INTATGAP BIT(21) /* RW */
203 #define SDC_CFG_DTOC GENMASK(31, 24) /* RW */
204
205 /* SDC_STS mask */
206 #define SDC_STS_SDCBUSY BIT(0) /* RW */
207 #define SDC_STS_CMDBUSY BIT(1) /* RW */
208 #define SDC_STS_SWR_COMPL BIT(31) /* RW */
209
210 /* SDC_ADV_CFG0 mask */
211 #define SDC_DAT1_IRQ_TRIGGER BIT(19) /* RW */
212 #define SDC_RX_ENHANCE_EN BIT(20) /* RW */
213 #define SDC_NEW_TX_EN BIT(31) /* RW */
214
215 /* MSDC_NEW_RX_CFG mask */
216 #define MSDC_NEW_RX_PATH_SEL BIT(0) /* RW */
217
218 /* DMA_SA_H4BIT mask */
219 #define DMA_ADDR_HIGH_4BIT GENMASK(3, 0) /* RW */
220
221 /* MSDC_DMA_CTRL mask */
222 #define MSDC_DMA_CTRL_START BIT(0) /* W */
223 #define MSDC_DMA_CTRL_STOP BIT(1) /* W */
224 #define MSDC_DMA_CTRL_RESUME BIT(2) /* W */
225 #define MSDC_DMA_CTRL_MODE BIT(8) /* RW */
226 #define MSDC_DMA_CTRL_LASTBUF BIT(10) /* RW */
227 #define MSDC_DMA_CTRL_BRUSTSZ GENMASK(14, 12) /* RW */
228
229 /* MSDC_DMA_CFG mask */
230 #define MSDC_DMA_CFG_STS BIT(0) /* R */
231 #define MSDC_DMA_CFG_DECSEN BIT(1) /* RW */
232 #define MSDC_DMA_CFG_AHBHPROT2 BIT(9) /* RW */
233 #define MSDC_DMA_CFG_ACTIVEEN BIT(13) /* RW */
234 #define MSDC_DMA_CFG_CS12B16B BIT(16) /* RW */
235
236 /* MSDC_PATCH_BIT mask */
237 #define MSDC_PATCH_BIT_ODDSUPP BIT(1) /* RW */
238 #define MSDC_PATCH_BIT_DIS_WRMON BIT(2) /* RW */
239 #define MSDC_PATCH_BIT_RD_DAT_SEL BIT(3) /* RW */
240 #define MSDC_PATCH_BIT_DESCUP_SEL BIT(6) /* RW */
241 #define MSDC_INT_DAT_LATCH_CK_SEL GENMASK(9, 7)
242 #define MSDC_CKGEN_MSDC_DLY_SEL GENMASK(14, 10)
243 #define MSDC_PATCH_BIT_IODSSEL BIT(16) /* RW */
244 #define MSDC_PATCH_BIT_IOINTSEL BIT(17) /* RW */
245 #define MSDC_PATCH_BIT_BUSYDLY GENMASK(21, 18) /* RW */
246 #define MSDC_PATCH_BIT_WDOD GENMASK(25, 22) /* RW */
247 #define MSDC_PATCH_BIT_IDRTSEL BIT(26) /* RW */
248 #define MSDC_PATCH_BIT_CMDFSEL BIT(27) /* RW */
249 #define MSDC_PATCH_BIT_INTDLSEL BIT(28) /* RW */
250 #define MSDC_PATCH_BIT_SPCPUSH BIT(29) /* RW */
251 #define MSDC_PATCH_BIT_DECRCTMO BIT(30) /* RW */
252
253 /* MSDC_PATCH_BIT1 mask */
254 #define MSDC_PB1_WRDAT_CRC_TACNTR GENMASK(2, 0) /* RW */
255 #define MSDC_PATCH_BIT1_CMDTA GENMASK(5, 3) /* RW */
256 #define MSDC_PB1_BUSY_CHECK_SEL BIT(7) /* RW */
257 #define MSDC_PATCH_BIT1_STOP_DLY GENMASK(11, 8) /* RW */
258 #define MSDC_PB1_DDR_CMD_FIX_SEL BIT(14) /* RW */
259 #define MSDC_PB1_SINGLE_BURST BIT(16) /* RW */
260 #define MSDC_PB1_RSVD20 GENMASK(18, 17) /* RW */
261 #define MSDC_PB1_AUTO_SYNCST_CLR BIT(19) /* RW */
262 #define MSDC_PB1_MARK_POP_WATER BIT(20) /* RW */
263 #define MSDC_PB1_LP_DCM_EN BIT(21) /* RW */
264 #define MSDC_PB1_RSVD3 BIT(22) /* RW */
265 #define MSDC_PB1_AHB_GDMA_HCLK BIT(23) /* RW */
266 #define MSDC_PB1_MSDC_CLK_ENFEAT GENMASK(31, 24) /* RW */
267
268 /* MSDC_PATCH_BIT2 mask */
269 #define MSDC_PATCH_BIT2_CFGRESP BIT(15) /* RW */
270 #define MSDC_PATCH_BIT2_CFGCRCSTS BIT(28) /* RW */
271 #define MSDC_PB2_SUPPORT_64G BIT(1) /* RW */
272 #define MSDC_PB2_RESPWAIT GENMASK(3, 2) /* RW */
273 #define MSDC_PB2_RESPSTSENSEL GENMASK(18, 16) /* RW */
274 #define MSDC_PB2_POP_EN_CNT GENMASK(23, 20) /* RW */
275 #define MSDC_PB2_CFGCRCSTSEDGE BIT(25) /* RW */
276 #define MSDC_PB2_CRCSTSENSEL GENMASK(31, 29) /* RW */
277
278 #define MSDC_PAD_TUNE_DATWRDLY GENMASK(4, 0) /* RW */
279 #define MSDC_PAD_TUNE_DATRRDLY GENMASK(12, 8) /* RW */
280 #define MSDC_PAD_TUNE_DATRRDLY2 GENMASK(12, 8) /* RW */
281 #define MSDC_PAD_TUNE_CMDRDLY GENMASK(20, 16) /* RW */
282 #define MSDC_PAD_TUNE_CMDRDLY2 GENMASK(20, 16) /* RW */
283 #define MSDC_PAD_TUNE_CMDRRDLY GENMASK(26, 22) /* RW */
284 #define MSDC_PAD_TUNE_CLKTDLY GENMASK(31, 27) /* RW */
285 #define MSDC_PAD_TUNE_RXDLYSEL BIT(15) /* RW */
286 #define MSDC_PAD_TUNE_RD_SEL BIT(13) /* RW */
287 #define MSDC_PAD_TUNE_CMD_SEL BIT(21) /* RW */
288 #define MSDC_PAD_TUNE_RD2_SEL BIT(13) /* RW */
289 #define MSDC_PAD_TUNE_CMD2_SEL BIT(21) /* RW */
290
291 #define PAD_DS_TUNE_DLY_SEL BIT(0) /* RW */
292 #define PAD_DS_TUNE_DLY2_SEL BIT(1) /* RW */
293 #define PAD_DS_TUNE_DLY1 GENMASK(6, 2) /* RW */
294 #define PAD_DS_TUNE_DLY2 GENMASK(11, 7) /* RW */
295 #define PAD_DS_TUNE_DLY3 GENMASK(16, 12) /* RW */
296
297 #define PAD_CMD_TUNE_RX_DLY3 GENMASK(5, 1) /* RW */
298
299 /* EMMC51_CFG0 mask */
300 #define CMDQ_RDAT_CNT GENMASK(21, 12) /* RW */
301
302 #define EMMC50_CFG_PADCMD_LATCHCK BIT(0) /* RW */
303 #define EMMC50_CFG_CRCSTS_EDGE BIT(3) /* RW */
304 #define EMMC50_CFG_CFCSTS_SEL BIT(4) /* RW */
305 #define EMMC50_CFG_CMD_RESP_SEL BIT(9) /* RW */
306
307 /* EMMC50_CFG1 mask */
308 #define EMMC50_CFG1_DS_CFG BIT(28) /* RW */
309
310 /* EMMC50_CFG2 mask */
311 #define EMMC50_CFG2_AXI_SET_LEN GENMASK(27, 24) /* RW */
312
313 #define EMMC50_CFG3_OUTS_WR GENMASK(4, 0) /* RW */
314
315 #define SDC_FIFO_CFG_WRVALIDSEL BIT(24) /* RW */
316 #define SDC_FIFO_CFG_RDVALIDSEL BIT(25) /* RW */
317
318 /* CQHCI_SETTING */
319 #define CQHCI_RD_CMD_WND_SEL BIT(14) /* RW */
320 #define CQHCI_WR_CMD_WND_SEL BIT(15) /* RW */
321
322 /* EMMC_TOP_CONTROL mask */
323 #define PAD_RXDLY_SEL BIT(0) /* RW */
324 #define DELAY_EN BIT(1) /* RW */
325 #define PAD_DAT_RD_RXDLY2 GENMASK(6, 2) /* RW */
326 #define PAD_DAT_RD_RXDLY GENMASK(11, 7) /* RW */
327 #define PAD_DAT_RD_RXDLY2_SEL BIT(12) /* RW */
328 #define PAD_DAT_RD_RXDLY_SEL BIT(13) /* RW */
329 #define DATA_K_VALUE_SEL BIT(14) /* RW */
330 #define SDC_RX_ENH_EN BIT(15) /* TW */
331
332 /* EMMC_TOP_CMD mask */
333 #define PAD_CMD_RXDLY2 GENMASK(4, 0) /* RW */
334 #define PAD_CMD_RXDLY GENMASK(9, 5) /* RW */
335 #define PAD_CMD_RD_RXDLY2_SEL BIT(10) /* RW */
336 #define PAD_CMD_RD_RXDLY_SEL BIT(11) /* RW */
337 #define PAD_CMD_TX_DLY GENMASK(16, 12) /* RW */
338
339 /* EMMC50_PAD_DS_TUNE mask */
340 #define PAD_DS_DLY_SEL BIT(16) /* RW */
341 #define PAD_DS_DLY2_SEL BIT(15) /* RW */
342 #define PAD_DS_DLY1 GENMASK(14, 10) /* RW */
343 #define PAD_DS_DLY3 GENMASK(4, 0) /* RW */
344
345 /* LOOP_TEST_CONTROL mask */
346 #define TEST_LOOP_DSCLK_MUX_SEL BIT(0) /* RW */
347 #define TEST_LOOP_LATCH_MUX_SEL BIT(1) /* RW */
348 #define LOOP_EN_SEL_CLK BIT(20) /* RW */
349 #define TEST_HS400_CMD_LOOP_MUX_SEL BIT(31) /* RW */
350
351 #define REQ_CMD_EIO BIT(0)
352 #define REQ_CMD_TMO BIT(1)
353 #define REQ_DAT_ERR BIT(2)
354 #define REQ_STOP_EIO BIT(3)
355 #define REQ_STOP_TMO BIT(4)
356 #define REQ_CMD_BUSY BIT(5)
357
358 #define MSDC_PREPARE_FLAG BIT(0)
359 #define MSDC_ASYNC_FLAG BIT(1)
360 #define MSDC_MMAP_FLAG BIT(2)
361
362 #define MTK_MMC_AUTOSUSPEND_DELAY 50
363 #define CMD_TIMEOUT (HZ/10 * 5) /* 100ms x5 */
364 #define DAT_TIMEOUT (HZ * 5) /* 1000ms x5 */
365
366 #define DEFAULT_DEBOUNCE (8) /* 8 cycles CD debounce */
367
368 #define TUNING_REG2_FIXED_OFFEST 4
369 #define PAD_DELAY_HALF 32 /* PAD delay cells */
370 #define PAD_DELAY_FULL 64
371 /*--------------------------------------------------------------------------*/
372 /* Descriptor Structure */
373 /*--------------------------------------------------------------------------*/
374 struct mt_gpdma_desc {
375 u32 gpd_info;
376 #define GPDMA_DESC_HWO BIT(0)
377 #define GPDMA_DESC_BDP BIT(1)
378 #define GPDMA_DESC_CHECKSUM GENMASK(15, 8)
379 #define GPDMA_DESC_INT BIT(16)
380 #define GPDMA_DESC_NEXT_H4 GENMASK(27, 24)
381 #define GPDMA_DESC_PTR_H4 GENMASK(31, 28)
382 u32 next;
383 u32 ptr;
384 u32 gpd_data_len;
385 #define GPDMA_DESC_BUFLEN GENMASK(15, 0)
386 #define GPDMA_DESC_EXTLEN GENMASK(23, 16)
387 u32 arg;
388 u32 blknum;
389 u32 cmd;
390 };
391
392 struct mt_bdma_desc {
393 u32 bd_info;
394 #define BDMA_DESC_EOL BIT(0)
395 #define BDMA_DESC_CHECKSUM GENMASK(15, 8)
396 #define BDMA_DESC_BLKPAD BIT(17)
397 #define BDMA_DESC_DWPAD BIT(18)
398 #define BDMA_DESC_NEXT_H4 GENMASK(27, 24)
399 #define BDMA_DESC_PTR_H4 GENMASK(31, 28)
400 u32 next;
401 u32 ptr;
402 u32 bd_data_len;
403 #define BDMA_DESC_BUFLEN GENMASK(15, 0)
404 #define BDMA_DESC_BUFLEN_EXT GENMASK(23, 0)
405 };
406
407 struct msdc_dma {
408 struct scatterlist *sg; /* I/O scatter list */
409 struct mt_gpdma_desc *gpd; /* pointer to gpd array */
410 struct mt_bdma_desc *bd; /* pointer to bd array */
411 dma_addr_t gpd_addr; /* the physical address of gpd array */
412 dma_addr_t bd_addr; /* the physical address of bd array */
413 };
414
415 struct msdc_save_para {
416 u32 msdc_cfg;
417 u32 iocon;
418 u32 sdc_cfg;
419 u32 pad_tune;
420 u32 patch_bit0;
421 u32 patch_bit1;
422 u32 patch_bit2;
423 u32 pad_ds_tune;
424 u32 pad_cmd_tune;
425 u32 emmc50_cfg0;
426 u32 emmc50_cfg3;
427 u32 sdc_fifo_cfg;
428 u32 emmc_top_control;
429 u32 emmc_top_cmd;
430 u32 emmc50_pad_ds_tune;
431 u32 loop_test_control;
432 };
433
434 struct mtk_mmc_compatible {
435 u8 clk_div_bits;
436 bool recheck_sdio_irq;
437 bool hs400_tune; /* only used for MT8173 */
438 bool needs_top_base;
439 u32 pad_tune_reg;
440 bool async_fifo;
441 bool data_tune;
442 bool busy_check;
443 bool stop_clk_fix;
444 u8 stop_dly_sel;
445 u8 pop_en_cnt;
446 bool enhance_rx;
447 bool support_64g;
448 bool use_internal_cd;
449 bool support_new_tx;
450 bool support_new_rx;
451 };
452
453 struct msdc_tune_para {
454 u32 iocon;
455 u32 pad_tune;
456 u32 pad_cmd_tune;
457 u32 emmc_top_control;
458 u32 emmc_top_cmd;
459 };
460
461 struct msdc_delay_phase {
462 u8 maxlen;
463 u8 start;
464 u8 final_phase;
465 };
466
467 struct msdc_host {
468 struct device *dev;
469 const struct mtk_mmc_compatible *dev_comp;
470 int cmd_rsp;
471
472 spinlock_t lock;
473 struct mmc_request *mrq;
474 struct mmc_command *cmd;
475 struct mmc_data *data;
476 int error;
477
478 void __iomem *base; /* host base address */
479 void __iomem *top_base; /* host top register base address */
480
481 struct msdc_dma dma; /* dma channel */
482 u64 dma_mask;
483
484 u32 timeout_ns; /* data timeout ns */
485 u32 timeout_clks; /* data timeout clks */
486
487 struct pinctrl *pinctrl;
488 struct pinctrl_state *pins_default;
489 struct pinctrl_state *pins_uhs;
490 struct pinctrl_state *pins_eint;
491 struct delayed_work req_timeout;
492 int irq; /* host interrupt */
493 int eint_irq; /* interrupt from sdio device for waking up system */
494 struct reset_control *reset;
495
496 struct clk *src_clk; /* msdc source clock */
497 struct clk *h_clk; /* msdc h_clk */
498 struct clk *bus_clk; /* bus clock which used to access register */
499 struct clk *src_clk_cg; /* msdc source clock control gate */
500 struct clk *sys_clk_cg; /* msdc subsys clock control gate */
501 struct clk *crypto_clk; /* msdc crypto clock control gate */
502 struct clk_bulk_data bulk_clks[MSDC_NR_CLOCKS];
503 u32 mclk; /* mmc subsystem clock frequency */
504 u32 src_clk_freq; /* source clock frequency */
505 unsigned char timing;
506 bool vqmmc_enabled;
507 u32 latch_ck;
508 u32 hs400_ds_delay;
509 u32 hs400_ds_dly3;
510 u32 hs200_cmd_int_delay; /* cmd internal delay for HS200/SDR104 */
511 u32 hs400_cmd_int_delay; /* cmd internal delay for HS400 */
512 u32 tuning_step;
513 bool hs400_cmd_resp_sel_rising;
514 /* cmd response sample selection for HS400 */
515 bool hs400_mode; /* current eMMC will run at hs400 mode */
516 bool hs400_tuning; /* hs400 mode online tuning */
517 bool internal_cd; /* Use internal card-detect logic */
518 bool cqhci; /* support eMMC hw cmdq */
519 bool hsq_en; /* Host Software Queue is enabled */
520 struct msdc_save_para save_para; /* used when gate HCLK */
521 struct msdc_tune_para def_tune_para; /* default tune setting */
522 struct msdc_tune_para saved_tune_para; /* tune result of CMD21/CMD19 */
523 struct cqhci_host *cq_host;
524 u32 cq_ssc1_time;
525 };
526
527 static const struct mtk_mmc_compatible mt2701_compat = {
528 .clk_div_bits = 12,
529 .recheck_sdio_irq = true,
530 .hs400_tune = false,
531 .pad_tune_reg = MSDC_PAD_TUNE0,
532 .async_fifo = true,
533 .data_tune = true,
534 .busy_check = false,
535 .stop_clk_fix = false,
536 .enhance_rx = false,
537 .support_64g = false,
538 };
539
540 static const struct mtk_mmc_compatible mt2712_compat = {
541 .clk_div_bits = 12,
542 .recheck_sdio_irq = false,
543 .hs400_tune = false,
544 .pad_tune_reg = MSDC_PAD_TUNE0,
545 .async_fifo = true,
546 .data_tune = true,
547 .busy_check = true,
548 .stop_clk_fix = true,
549 .stop_dly_sel = 3,
550 .enhance_rx = true,
551 .support_64g = true,
552 };
553
554 static const struct mtk_mmc_compatible mt6779_compat = {
555 .clk_div_bits = 12,
556 .recheck_sdio_irq = false,
557 .hs400_tune = false,
558 .pad_tune_reg = MSDC_PAD_TUNE0,
559 .async_fifo = true,
560 .data_tune = true,
561 .busy_check = true,
562 .stop_clk_fix = true,
563 .stop_dly_sel = 3,
564 .enhance_rx = true,
565 .support_64g = true,
566 };
567
568 static const struct mtk_mmc_compatible mt6795_compat = {
569 .clk_div_bits = 8,
570 .recheck_sdio_irq = false,
571 .hs400_tune = true,
572 .pad_tune_reg = MSDC_PAD_TUNE,
573 .async_fifo = false,
574 .data_tune = false,
575 .busy_check = false,
576 .stop_clk_fix = false,
577 .enhance_rx = false,
578 .support_64g = false,
579 };
580
581 static const struct mtk_mmc_compatible mt7620_compat = {
582 .clk_div_bits = 8,
583 .recheck_sdio_irq = true,
584 .hs400_tune = false,
585 .pad_tune_reg = MSDC_PAD_TUNE,
586 .async_fifo = false,
587 .data_tune = false,
588 .busy_check = false,
589 .stop_clk_fix = false,
590 .enhance_rx = false,
591 .use_internal_cd = true,
592 };
593
594 static const struct mtk_mmc_compatible mt7622_compat = {
595 .clk_div_bits = 12,
596 .recheck_sdio_irq = true,
597 .hs400_tune = false,
598 .pad_tune_reg = MSDC_PAD_TUNE0,
599 .async_fifo = true,
600 .data_tune = true,
601 .busy_check = true,
602 .stop_clk_fix = true,
603 .stop_dly_sel = 3,
604 .enhance_rx = true,
605 .support_64g = false,
606 };
607
608 static const struct mtk_mmc_compatible mt7986_compat = {
609 .clk_div_bits = 12,
610 .recheck_sdio_irq = true,
611 .hs400_tune = false,
612 .needs_top_base = true,
613 .pad_tune_reg = MSDC_PAD_TUNE0,
614 .async_fifo = true,
615 .data_tune = true,
616 .busy_check = true,
617 .stop_clk_fix = true,
618 .stop_dly_sel = 3,
619 .enhance_rx = true,
620 .support_64g = true,
621 };
622
623 static const struct mtk_mmc_compatible mt8135_compat = {
624 .clk_div_bits = 8,
625 .recheck_sdio_irq = true,
626 .hs400_tune = false,
627 .pad_tune_reg = MSDC_PAD_TUNE,
628 .async_fifo = false,
629 .data_tune = false,
630 .busy_check = false,
631 .stop_clk_fix = false,
632 .enhance_rx = false,
633 .support_64g = false,
634 };
635
636 static const struct mtk_mmc_compatible mt8173_compat = {
637 .clk_div_bits = 8,
638 .recheck_sdio_irq = true,
639 .hs400_tune = true,
640 .pad_tune_reg = MSDC_PAD_TUNE,
641 .async_fifo = false,
642 .data_tune = false,
643 .busy_check = false,
644 .stop_clk_fix = false,
645 .enhance_rx = false,
646 .support_64g = false,
647 };
648
649 static const struct mtk_mmc_compatible mt8183_compat = {
650 .clk_div_bits = 12,
651 .recheck_sdio_irq = false,
652 .hs400_tune = false,
653 .needs_top_base = true,
654 .pad_tune_reg = MSDC_PAD_TUNE0,
655 .async_fifo = true,
656 .data_tune = true,
657 .busy_check = true,
658 .stop_clk_fix = true,
659 .stop_dly_sel = 3,
660 .enhance_rx = true,
661 .support_64g = true,
662 };
663
664 static const struct mtk_mmc_compatible mt8516_compat = {
665 .clk_div_bits = 12,
666 .recheck_sdio_irq = true,
667 .hs400_tune = false,
668 .pad_tune_reg = MSDC_PAD_TUNE0,
669 .async_fifo = true,
670 .data_tune = true,
671 .busy_check = true,
672 .stop_clk_fix = true,
673 .stop_dly_sel = 3,
674 };
675
676 static const struct mtk_mmc_compatible mt8196_compat = {
677 .clk_div_bits = 12,
678 .recheck_sdio_irq = false,
679 .hs400_tune = false,
680 .needs_top_base = true,
681 .pad_tune_reg = MSDC_PAD_TUNE0,
682 .async_fifo = true,
683 .data_tune = true,
684 .busy_check = true,
685 .stop_clk_fix = true,
686 .stop_dly_sel = 1,
687 .pop_en_cnt = 2,
688 .enhance_rx = true,
689 .support_64g = true,
690 .support_new_tx = true,
691 .support_new_rx = true,
692 };
693
694 static const struct of_device_id msdc_of_ids[] = {
695 { .compatible = "mediatek,mt2701-mmc", .data = &mt2701_compat},
696 { .compatible = "mediatek,mt2712-mmc", .data = &mt2712_compat},
697 { .compatible = "mediatek,mt6779-mmc", .data = &mt6779_compat},
698 { .compatible = "mediatek,mt6795-mmc", .data = &mt6795_compat},
699 { .compatible = "mediatek,mt7620-mmc", .data = &mt7620_compat},
700 { .compatible = "mediatek,mt7622-mmc", .data = &mt7622_compat},
701 { .compatible = "mediatek,mt7986-mmc", .data = &mt7986_compat},
702 { .compatible = "mediatek,mt7988-mmc", .data = &mt7986_compat},
703 { .compatible = "mediatek,mt8135-mmc", .data = &mt8135_compat},
704 { .compatible = "mediatek,mt8173-mmc", .data = &mt8173_compat},
705 { .compatible = "mediatek,mt8183-mmc", .data = &mt8183_compat},
706 { .compatible = "mediatek,mt8196-mmc", .data = &mt8196_compat},
707 { .compatible = "mediatek,mt8516-mmc", .data = &mt8516_compat},
708
709 {}
710 };
711 MODULE_DEVICE_TABLE(of, msdc_of_ids);
712
sdr_set_bits(void __iomem * reg,u32 bs)713 static void sdr_set_bits(void __iomem *reg, u32 bs)
714 {
715 u32 val = readl(reg);
716
717 val |= bs;
718 writel(val, reg);
719 }
720
sdr_clr_bits(void __iomem * reg,u32 bs)721 static void sdr_clr_bits(void __iomem *reg, u32 bs)
722 {
723 u32 val = readl(reg);
724
725 val &= ~bs;
726 writel(val, reg);
727 }
728
sdr_set_field(void __iomem * reg,u32 field,u32 val)729 static void sdr_set_field(void __iomem *reg, u32 field, u32 val)
730 {
731 unsigned int tv = readl(reg);
732
733 tv &= ~field;
734 tv |= ((val) << (ffs((unsigned int)field) - 1));
735 writel(tv, reg);
736 }
737
sdr_get_field(void __iomem * reg,u32 field,u32 * val)738 static void sdr_get_field(void __iomem *reg, u32 field, u32 *val)
739 {
740 unsigned int tv = readl(reg);
741
742 *val = ((tv & field) >> (ffs((unsigned int)field) - 1));
743 }
744
msdc_reset_hw(struct msdc_host * host)745 static void msdc_reset_hw(struct msdc_host *host)
746 {
747 u32 val;
748
749 sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_RST);
750 readl_poll_timeout_atomic(host->base + MSDC_CFG, val, !(val & MSDC_CFG_RST), 0, 0);
751
752 sdr_set_bits(host->base + MSDC_FIFOCS, MSDC_FIFOCS_CLR);
753 readl_poll_timeout_atomic(host->base + MSDC_FIFOCS, val,
754 !(val & MSDC_FIFOCS_CLR), 0, 0);
755
756 val = readl(host->base + MSDC_INT);
757 writel(val, host->base + MSDC_INT);
758 }
759
760 static void msdc_cmd_next(struct msdc_host *host,
761 struct mmc_request *mrq, struct mmc_command *cmd);
762 static void __msdc_enable_sdio_irq(struct msdc_host *host, int enb);
763
764 static const u32 cmd_ints_mask = MSDC_INTEN_CMDRDY | MSDC_INTEN_RSPCRCERR |
765 MSDC_INTEN_CMDTMO | MSDC_INTEN_ACMDRDY |
766 MSDC_INTEN_ACMDCRCERR | MSDC_INTEN_ACMDTMO;
767 static const u32 data_ints_mask = MSDC_INTEN_XFER_COMPL | MSDC_INTEN_DATTMO |
768 MSDC_INTEN_DATCRCERR | MSDC_INTEN_DMA_BDCSERR |
769 MSDC_INTEN_DMA_GPDCSERR | MSDC_INTEN_DMA_PROTECT;
770
msdc_dma_calcs(u8 * buf,u32 len)771 static u8 msdc_dma_calcs(u8 *buf, u32 len)
772 {
773 u32 i, sum = 0;
774
775 for (i = 0; i < len; i++)
776 sum += buf[i];
777 return 0xff - (u8) sum;
778 }
779
msdc_dma_setup(struct msdc_host * host,struct msdc_dma * dma,struct mmc_data * data)780 static inline void msdc_dma_setup(struct msdc_host *host, struct msdc_dma *dma,
781 struct mmc_data *data)
782 {
783 unsigned int j, dma_len;
784 dma_addr_t dma_address;
785 u32 dma_ctrl;
786 struct scatterlist *sg;
787 struct mt_gpdma_desc *gpd;
788 struct mt_bdma_desc *bd;
789
790 sg = data->sg;
791
792 gpd = dma->gpd;
793 bd = dma->bd;
794
795 /* modify gpd */
796 gpd->gpd_info |= GPDMA_DESC_HWO;
797 gpd->gpd_info |= GPDMA_DESC_BDP;
798 /* need to clear first. use these bits to calc checksum */
799 gpd->gpd_info &= ~GPDMA_DESC_CHECKSUM;
800 gpd->gpd_info |= msdc_dma_calcs((u8 *) gpd, 16) << 8;
801
802 /* modify bd */
803 for_each_sg(data->sg, sg, data->sg_count, j) {
804 dma_address = sg_dma_address(sg);
805 dma_len = sg_dma_len(sg);
806
807 /* init bd */
808 bd[j].bd_info &= ~BDMA_DESC_BLKPAD;
809 bd[j].bd_info &= ~BDMA_DESC_DWPAD;
810 bd[j].ptr = lower_32_bits(dma_address);
811 if (host->dev_comp->support_64g) {
812 bd[j].bd_info &= ~BDMA_DESC_PTR_H4;
813 bd[j].bd_info |= (upper_32_bits(dma_address) & 0xf)
814 << 28;
815 }
816
817 if (host->dev_comp->support_64g) {
818 bd[j].bd_data_len &= ~BDMA_DESC_BUFLEN_EXT;
819 bd[j].bd_data_len |= (dma_len & BDMA_DESC_BUFLEN_EXT);
820 } else {
821 bd[j].bd_data_len &= ~BDMA_DESC_BUFLEN;
822 bd[j].bd_data_len |= (dma_len & BDMA_DESC_BUFLEN);
823 }
824
825 if (j == data->sg_count - 1) /* the last bd */
826 bd[j].bd_info |= BDMA_DESC_EOL;
827 else
828 bd[j].bd_info &= ~BDMA_DESC_EOL;
829
830 /* checksum need to clear first */
831 bd[j].bd_info &= ~BDMA_DESC_CHECKSUM;
832 bd[j].bd_info |= msdc_dma_calcs((u8 *)(&bd[j]), 16) << 8;
833 }
834
835 sdr_set_field(host->base + MSDC_DMA_CFG, MSDC_DMA_CFG_DECSEN, 1);
836 dma_ctrl = readl_relaxed(host->base + MSDC_DMA_CTRL);
837 dma_ctrl &= ~(MSDC_DMA_CTRL_BRUSTSZ | MSDC_DMA_CTRL_MODE);
838 dma_ctrl |= (MSDC_BURST_64B << 12 | BIT(8));
839 writel_relaxed(dma_ctrl, host->base + MSDC_DMA_CTRL);
840 if (host->dev_comp->support_64g)
841 sdr_set_field(host->base + DMA_SA_H4BIT, DMA_ADDR_HIGH_4BIT,
842 upper_32_bits(dma->gpd_addr) & 0xf);
843 writel(lower_32_bits(dma->gpd_addr), host->base + MSDC_DMA_SA);
844 }
845
msdc_prepare_data(struct msdc_host * host,struct mmc_data * data)846 static void msdc_prepare_data(struct msdc_host *host, struct mmc_data *data)
847 {
848 if (!(data->host_cookie & MSDC_PREPARE_FLAG)) {
849 data->host_cookie |= MSDC_PREPARE_FLAG;
850 data->sg_count = dma_map_sg(host->dev, data->sg, data->sg_len,
851 mmc_get_dma_dir(data));
852 }
853 }
854
msdc_unprepare_data(struct msdc_host * host,struct mmc_data * data)855 static void msdc_unprepare_data(struct msdc_host *host, struct mmc_data *data)
856 {
857 if (data->host_cookie & MSDC_ASYNC_FLAG)
858 return;
859
860 if (data->host_cookie & MSDC_PREPARE_FLAG) {
861 dma_unmap_sg(host->dev, data->sg, data->sg_len,
862 mmc_get_dma_dir(data));
863 data->host_cookie &= ~MSDC_PREPARE_FLAG;
864 }
865 }
866
msdc_timeout_cal(struct msdc_host * host,u64 ns,u64 clks)867 static u64 msdc_timeout_cal(struct msdc_host *host, u64 ns, u64 clks)
868 {
869 struct mmc_host *mmc = mmc_from_priv(host);
870 u64 timeout;
871 u32 clk_ns, mode = 0;
872
873 if (mmc->actual_clock == 0) {
874 timeout = 0;
875 } else {
876 clk_ns = 1000000000U / mmc->actual_clock;
877 timeout = ns + clk_ns - 1;
878 do_div(timeout, clk_ns);
879 timeout += clks;
880 /* in 1048576 sclk cycle unit */
881 timeout = DIV_ROUND_UP(timeout, BIT(20));
882 if (host->dev_comp->clk_div_bits == 8)
883 sdr_get_field(host->base + MSDC_CFG,
884 MSDC_CFG_CKMOD, &mode);
885 else
886 sdr_get_field(host->base + MSDC_CFG,
887 MSDC_CFG_CKMOD_EXTRA, &mode);
888 /*DDR mode will double the clk cycles for data timeout */
889 timeout = mode >= 2 ? timeout * 2 : timeout;
890 timeout = timeout > 1 ? timeout - 1 : 0;
891 }
892 return timeout;
893 }
894
895 /* clock control primitives */
msdc_set_timeout(struct msdc_host * host,u64 ns,u64 clks)896 static void msdc_set_timeout(struct msdc_host *host, u64 ns, u64 clks)
897 {
898 u64 timeout;
899
900 host->timeout_ns = ns;
901 host->timeout_clks = clks;
902
903 timeout = msdc_timeout_cal(host, ns, clks);
904 sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC,
905 min_t(u32, timeout, 255));
906 }
907
msdc_set_busy_timeout(struct msdc_host * host,u64 ns,u64 clks)908 static void msdc_set_busy_timeout(struct msdc_host *host, u64 ns, u64 clks)
909 {
910 u64 timeout;
911
912 timeout = msdc_timeout_cal(host, ns, clks);
913 sdr_set_field(host->base + SDC_CFG, SDC_CFG_WRDTOC,
914 min_t(u32, timeout, 8191));
915 }
916
msdc_gate_clock(struct msdc_host * host)917 static void msdc_gate_clock(struct msdc_host *host)
918 {
919 clk_bulk_disable_unprepare(MSDC_NR_CLOCKS, host->bulk_clks);
920 clk_disable_unprepare(host->crypto_clk);
921 clk_disable_unprepare(host->src_clk_cg);
922 clk_disable_unprepare(host->src_clk);
923 clk_disable_unprepare(host->bus_clk);
924 clk_disable_unprepare(host->h_clk);
925 }
926
msdc_ungate_clock(struct msdc_host * host)927 static int msdc_ungate_clock(struct msdc_host *host)
928 {
929 u32 val;
930 int ret;
931
932 clk_prepare_enable(host->h_clk);
933 clk_prepare_enable(host->bus_clk);
934 clk_prepare_enable(host->src_clk);
935 clk_prepare_enable(host->src_clk_cg);
936 clk_prepare_enable(host->crypto_clk);
937 ret = clk_bulk_prepare_enable(MSDC_NR_CLOCKS, host->bulk_clks);
938 if (ret) {
939 dev_err(host->dev, "Cannot enable pclk/axi/ahb clock gates\n");
940 return ret;
941 }
942
943 return readl_poll_timeout(host->base + MSDC_CFG, val,
944 (val & MSDC_CFG_CKSTB), 1, 20000);
945 }
946
msdc_new_tx_setting(struct msdc_host * host)947 static void msdc_new_tx_setting(struct msdc_host *host)
948 {
949 u32 val;
950
951 if (!host->top_base)
952 return;
953
954 val = readl(host->top_base + LOOP_TEST_CONTROL);
955 val |= TEST_LOOP_DSCLK_MUX_SEL;
956 val |= TEST_LOOP_LATCH_MUX_SEL;
957 val &= ~TEST_HS400_CMD_LOOP_MUX_SEL;
958
959 switch (host->timing) {
960 case MMC_TIMING_LEGACY:
961 case MMC_TIMING_MMC_HS:
962 case MMC_TIMING_SD_HS:
963 case MMC_TIMING_UHS_SDR12:
964 case MMC_TIMING_UHS_SDR25:
965 case MMC_TIMING_UHS_DDR50:
966 case MMC_TIMING_MMC_DDR52:
967 val &= ~LOOP_EN_SEL_CLK;
968 break;
969 case MMC_TIMING_UHS_SDR50:
970 case MMC_TIMING_UHS_SDR104:
971 case MMC_TIMING_MMC_HS200:
972 case MMC_TIMING_MMC_HS400:
973 val |= LOOP_EN_SEL_CLK;
974 break;
975 default:
976 break;
977 }
978 writel(val, host->top_base + LOOP_TEST_CONTROL);
979 }
980
msdc_set_mclk(struct msdc_host * host,unsigned char timing,u32 hz)981 static void msdc_set_mclk(struct msdc_host *host, unsigned char timing, u32 hz)
982 {
983 struct mmc_host *mmc = mmc_from_priv(host);
984 u32 mode;
985 u32 flags;
986 u32 div;
987 u32 sclk;
988 u32 tune_reg = host->dev_comp->pad_tune_reg;
989 u32 val;
990 bool timing_changed;
991
992 if (!hz) {
993 dev_dbg(host->dev, "set mclk to 0\n");
994 host->mclk = 0;
995 mmc->actual_clock = 0;
996 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN);
997 return;
998 }
999
1000 if (host->timing != timing)
1001 timing_changed = true;
1002 else
1003 timing_changed = false;
1004
1005 flags = readl(host->base + MSDC_INTEN);
1006 sdr_clr_bits(host->base + MSDC_INTEN, flags);
1007 if (host->dev_comp->clk_div_bits == 8)
1008 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_HS400_CK_MODE);
1009 else
1010 sdr_clr_bits(host->base + MSDC_CFG,
1011 MSDC_CFG_HS400_CK_MODE_EXTRA);
1012 if (timing == MMC_TIMING_UHS_DDR50 ||
1013 timing == MMC_TIMING_MMC_DDR52 ||
1014 timing == MMC_TIMING_MMC_HS400) {
1015 if (timing == MMC_TIMING_MMC_HS400)
1016 mode = 0x3;
1017 else
1018 mode = 0x2; /* ddr mode and use divisor */
1019
1020 if (hz >= (host->src_clk_freq >> 2)) {
1021 div = 0; /* mean div = 1/4 */
1022 sclk = host->src_clk_freq >> 2; /* sclk = clk / 4 */
1023 } else {
1024 div = (host->src_clk_freq + ((hz << 2) - 1)) / (hz << 2);
1025 sclk = (host->src_clk_freq >> 2) / div;
1026 div = (div >> 1);
1027 }
1028
1029 if (timing == MMC_TIMING_MMC_HS400 &&
1030 hz >= (host->src_clk_freq >> 1)) {
1031 if (host->dev_comp->clk_div_bits == 8)
1032 sdr_set_bits(host->base + MSDC_CFG,
1033 MSDC_CFG_HS400_CK_MODE);
1034 else
1035 sdr_set_bits(host->base + MSDC_CFG,
1036 MSDC_CFG_HS400_CK_MODE_EXTRA);
1037 sclk = host->src_clk_freq >> 1;
1038 div = 0; /* div is ignore when bit18 is set */
1039 }
1040 } else if (hz >= host->src_clk_freq) {
1041 mode = 0x1; /* no divisor */
1042 div = 0;
1043 sclk = host->src_clk_freq;
1044 } else {
1045 mode = 0x0; /* use divisor */
1046 if (hz >= (host->src_clk_freq >> 1)) {
1047 div = 0; /* mean div = 1/2 */
1048 sclk = host->src_clk_freq >> 1; /* sclk = clk / 2 */
1049 } else {
1050 div = (host->src_clk_freq + ((hz << 2) - 1)) / (hz << 2);
1051 sclk = (host->src_clk_freq >> 2) / div;
1052 }
1053 }
1054 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN);
1055
1056 clk_disable_unprepare(host->src_clk_cg);
1057 if (host->dev_comp->clk_div_bits == 8)
1058 sdr_set_field(host->base + MSDC_CFG,
1059 MSDC_CFG_CKMOD | MSDC_CFG_CKDIV,
1060 (mode << 8) | div);
1061 else
1062 sdr_set_field(host->base + MSDC_CFG,
1063 MSDC_CFG_CKMOD_EXTRA | MSDC_CFG_CKDIV_EXTRA,
1064 (mode << 12) | div);
1065
1066 clk_prepare_enable(host->src_clk_cg);
1067 readl_poll_timeout(host->base + MSDC_CFG, val, (val & MSDC_CFG_CKSTB), 0, 0);
1068 sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN);
1069 mmc->actual_clock = sclk;
1070 host->mclk = hz;
1071 host->timing = timing;
1072 /* need because clk changed. */
1073 msdc_set_timeout(host, host->timeout_ns, host->timeout_clks);
1074 sdr_set_bits(host->base + MSDC_INTEN, flags);
1075
1076 /*
1077 * mmc_select_hs400() will drop to 50Mhz and High speed mode,
1078 * tune result of hs200/200Mhz is not suitable for 50Mhz
1079 */
1080 if (mmc->actual_clock <= 52000000) {
1081 writel(host->def_tune_para.iocon, host->base + MSDC_IOCON);
1082 if (host->top_base) {
1083 writel(host->def_tune_para.emmc_top_control,
1084 host->top_base + EMMC_TOP_CONTROL);
1085 writel(host->def_tune_para.emmc_top_cmd,
1086 host->top_base + EMMC_TOP_CMD);
1087 } else {
1088 writel(host->def_tune_para.pad_tune,
1089 host->base + tune_reg);
1090 }
1091 } else {
1092 writel(host->saved_tune_para.iocon, host->base + MSDC_IOCON);
1093 writel(host->saved_tune_para.pad_cmd_tune,
1094 host->base + PAD_CMD_TUNE);
1095 if (host->top_base) {
1096 writel(host->saved_tune_para.emmc_top_control,
1097 host->top_base + EMMC_TOP_CONTROL);
1098 writel(host->saved_tune_para.emmc_top_cmd,
1099 host->top_base + EMMC_TOP_CMD);
1100 } else {
1101 writel(host->saved_tune_para.pad_tune,
1102 host->base + tune_reg);
1103 }
1104 }
1105
1106 if (timing == MMC_TIMING_MMC_HS400 &&
1107 host->dev_comp->hs400_tune)
1108 sdr_set_field(host->base + tune_reg,
1109 MSDC_PAD_TUNE_CMDRRDLY,
1110 host->hs400_cmd_int_delay);
1111 if (host->dev_comp->support_new_tx && timing_changed)
1112 msdc_new_tx_setting(host);
1113
1114 dev_dbg(host->dev, "sclk: %d, timing: %d\n", mmc->actual_clock,
1115 timing);
1116 }
1117
msdc_cmd_find_resp(struct msdc_host * host,struct mmc_command * cmd)1118 static inline u32 msdc_cmd_find_resp(struct msdc_host *host,
1119 struct mmc_command *cmd)
1120 {
1121 u32 resp;
1122
1123 switch (mmc_resp_type(cmd)) {
1124 /* Actually, R1, R5, R6, R7 are the same */
1125 case MMC_RSP_R1:
1126 resp = 0x1;
1127 break;
1128 case MMC_RSP_R1B:
1129 case MMC_RSP_R1B_NO_CRC:
1130 resp = 0x7;
1131 break;
1132 case MMC_RSP_R2:
1133 resp = 0x2;
1134 break;
1135 case MMC_RSP_R3:
1136 resp = 0x3;
1137 break;
1138 case MMC_RSP_NONE:
1139 default:
1140 resp = 0x0;
1141 break;
1142 }
1143
1144 return resp;
1145 }
1146
msdc_cmd_prepare_raw_cmd(struct msdc_host * host,struct mmc_request * mrq,struct mmc_command * cmd)1147 static inline u32 msdc_cmd_prepare_raw_cmd(struct msdc_host *host,
1148 struct mmc_request *mrq, struct mmc_command *cmd)
1149 {
1150 struct mmc_host *mmc = mmc_from_priv(host);
1151 /* rawcmd :
1152 * vol_swt << 30 | auto_cmd << 28 | blklen << 16 | go_irq << 15 |
1153 * stop << 14 | rw << 13 | dtype << 11 | rsptyp << 7 | brk << 6 | opcode
1154 */
1155 u32 opcode = cmd->opcode;
1156 u32 resp = msdc_cmd_find_resp(host, cmd);
1157 u32 rawcmd = (opcode & 0x3f) | ((resp & 0x7) << 7);
1158
1159 host->cmd_rsp = resp;
1160
1161 if ((opcode == SD_IO_RW_DIRECT && cmd->flags == (unsigned int) -1) ||
1162 opcode == MMC_STOP_TRANSMISSION)
1163 rawcmd |= BIT(14);
1164 else if (opcode == SD_SWITCH_VOLTAGE)
1165 rawcmd |= BIT(30);
1166 else if (opcode == SD_APP_SEND_SCR ||
1167 opcode == SD_APP_SEND_NUM_WR_BLKS ||
1168 (opcode == SD_SWITCH && mmc_cmd_type(cmd) == MMC_CMD_ADTC) ||
1169 (opcode == SD_APP_SD_STATUS && mmc_cmd_type(cmd) == MMC_CMD_ADTC) ||
1170 (opcode == MMC_SEND_EXT_CSD && mmc_cmd_type(cmd) == MMC_CMD_ADTC))
1171 rawcmd |= BIT(11);
1172
1173 if (cmd->data) {
1174 struct mmc_data *data = cmd->data;
1175
1176 if (mmc_op_multi(opcode)) {
1177 if (mmc_card_mmc(mmc->card) && mrq->sbc &&
1178 !(mrq->sbc->arg & 0xFFFF0000))
1179 rawcmd |= BIT(29); /* AutoCMD23 */
1180 }
1181
1182 rawcmd |= ((data->blksz & 0xFFF) << 16);
1183 if (data->flags & MMC_DATA_WRITE)
1184 rawcmd |= BIT(13);
1185 if (data->blocks > 1)
1186 rawcmd |= BIT(12);
1187 else
1188 rawcmd |= BIT(11);
1189 /* Always use dma mode */
1190 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_PIO);
1191
1192 if (host->timeout_ns != data->timeout_ns ||
1193 host->timeout_clks != data->timeout_clks)
1194 msdc_set_timeout(host, data->timeout_ns,
1195 data->timeout_clks);
1196
1197 writel(data->blocks, host->base + SDC_BLK_NUM);
1198 }
1199 return rawcmd;
1200 }
1201
msdc_start_data(struct msdc_host * host,struct mmc_command * cmd,struct mmc_data * data)1202 static void msdc_start_data(struct msdc_host *host, struct mmc_command *cmd,
1203 struct mmc_data *data)
1204 {
1205 bool read;
1206
1207 WARN_ON(host->data);
1208 host->data = data;
1209 read = data->flags & MMC_DATA_READ;
1210
1211 mod_delayed_work(system_wq, &host->req_timeout, DAT_TIMEOUT);
1212 msdc_dma_setup(host, &host->dma, data);
1213 sdr_set_bits(host->base + MSDC_INTEN, data_ints_mask);
1214 sdr_set_field(host->base + MSDC_DMA_CTRL, MSDC_DMA_CTRL_START, 1);
1215 dev_dbg(host->dev, "DMA start\n");
1216 dev_dbg(host->dev, "%s: cmd=%d DMA data: %d blocks; read=%d\n",
1217 __func__, cmd->opcode, data->blocks, read);
1218 }
1219
msdc_auto_cmd_done(struct msdc_host * host,int events,struct mmc_command * cmd)1220 static int msdc_auto_cmd_done(struct msdc_host *host, int events,
1221 struct mmc_command *cmd)
1222 {
1223 u32 *rsp = cmd->resp;
1224
1225 rsp[0] = readl(host->base + SDC_ACMD_RESP);
1226
1227 if (events & MSDC_INT_ACMDRDY) {
1228 cmd->error = 0;
1229 } else {
1230 msdc_reset_hw(host);
1231 if (events & MSDC_INT_ACMDCRCERR) {
1232 cmd->error = -EILSEQ;
1233 host->error |= REQ_STOP_EIO;
1234 } else if (events & MSDC_INT_ACMDTMO) {
1235 cmd->error = -ETIMEDOUT;
1236 host->error |= REQ_STOP_TMO;
1237 }
1238 dev_err(host->dev,
1239 "%s: AUTO_CMD%d arg=%08X; rsp %08X; cmd_error=%d\n",
1240 __func__, cmd->opcode, cmd->arg, rsp[0], cmd->error);
1241 }
1242 return cmd->error;
1243 }
1244
1245 /*
1246 * msdc_recheck_sdio_irq - recheck whether the SDIO irq is lost
1247 *
1248 * Host controller may lost interrupt in some special case.
1249 * Add SDIO irq recheck mechanism to make sure all interrupts
1250 * can be processed immediately
1251 */
msdc_recheck_sdio_irq(struct msdc_host * host)1252 static void msdc_recheck_sdio_irq(struct msdc_host *host)
1253 {
1254 struct mmc_host *mmc = mmc_from_priv(host);
1255 u32 reg_int, reg_inten, reg_ps;
1256
1257 if (mmc->caps & MMC_CAP_SDIO_IRQ) {
1258 reg_inten = readl(host->base + MSDC_INTEN);
1259 if (reg_inten & MSDC_INTEN_SDIOIRQ) {
1260 reg_int = readl(host->base + MSDC_INT);
1261 reg_ps = readl(host->base + MSDC_PS);
1262 if (!(reg_int & MSDC_INT_SDIOIRQ ||
1263 reg_ps & MSDC_PS_DATA1)) {
1264 __msdc_enable_sdio_irq(host, 0);
1265 sdio_signal_irq(mmc);
1266 }
1267 }
1268 }
1269 }
1270
msdc_track_cmd_data(struct msdc_host * host,struct mmc_command * cmd)1271 static void msdc_track_cmd_data(struct msdc_host *host, struct mmc_command *cmd)
1272 {
1273 if (host->error &&
1274 ((!mmc_op_tuning(cmd->opcode) && !host->hs400_tuning) ||
1275 cmd->error == -ETIMEDOUT))
1276 dev_warn(host->dev, "%s: cmd=%d arg=%08X; host->error=0x%08X\n",
1277 __func__, cmd->opcode, cmd->arg, host->error);
1278 }
1279
msdc_request_done(struct msdc_host * host,struct mmc_request * mrq)1280 static void msdc_request_done(struct msdc_host *host, struct mmc_request *mrq)
1281 {
1282 struct mmc_host *mmc = mmc_from_priv(host);
1283 unsigned long flags;
1284 bool hsq_req_done;
1285
1286 /*
1287 * No need check the return value of cancel_delayed_work, as only ONE
1288 * path will go here!
1289 */
1290 cancel_delayed_work(&host->req_timeout);
1291
1292 /*
1293 * If the request was handled from Host Software Queue, there's almost
1294 * nothing to do here, and we also don't need to reset mrq as any race
1295 * condition would not have any room to happen, since HSQ stores the
1296 * "scheduled" mrqs in an internal array of mrq slots anyway.
1297 * However, if the controller experienced an error, we still want to
1298 * reset it as soon as possible.
1299 *
1300 * Note that non-HSQ requests will still be happening at times, even
1301 * though it is enabled, and that's what is going to reset host->mrq.
1302 * Also, msdc_unprepare_data() is going to be called by HSQ when needed
1303 * as HSQ request finalization will eventually call the .post_req()
1304 * callback of this driver which, in turn, unprepares the data.
1305 */
1306 hsq_req_done = host->hsq_en ? mmc_hsq_finalize_request(mmc, mrq) : false;
1307 if (hsq_req_done) {
1308 if (host->error)
1309 msdc_reset_hw(host);
1310 return;
1311 }
1312
1313 spin_lock_irqsave(&host->lock, flags);
1314 host->mrq = NULL;
1315 spin_unlock_irqrestore(&host->lock, flags);
1316
1317 msdc_track_cmd_data(host, mrq->cmd);
1318 if (mrq->data)
1319 msdc_unprepare_data(host, mrq->data);
1320 if (host->error)
1321 msdc_reset_hw(host);
1322 mmc_request_done(mmc, mrq);
1323 if (host->dev_comp->recheck_sdio_irq)
1324 msdc_recheck_sdio_irq(host);
1325 }
1326
1327 /* returns true if command is fully handled; returns false otherwise */
msdc_cmd_done(struct msdc_host * host,int events,struct mmc_request * mrq,struct mmc_command * cmd)1328 static bool msdc_cmd_done(struct msdc_host *host, int events,
1329 struct mmc_request *mrq, struct mmc_command *cmd)
1330 {
1331 bool done = false;
1332 bool sbc_error;
1333 unsigned long flags;
1334 u32 *rsp;
1335
1336 if (mrq->sbc && cmd == mrq->cmd &&
1337 (events & (MSDC_INT_ACMDRDY | MSDC_INT_ACMDCRCERR
1338 | MSDC_INT_ACMDTMO)))
1339 msdc_auto_cmd_done(host, events, mrq->sbc);
1340
1341 sbc_error = mrq->sbc && mrq->sbc->error;
1342
1343 if (!sbc_error && !(events & (MSDC_INT_CMDRDY
1344 | MSDC_INT_RSPCRCERR
1345 | MSDC_INT_CMDTMO)))
1346 return done;
1347
1348 spin_lock_irqsave(&host->lock, flags);
1349 done = !host->cmd;
1350 host->cmd = NULL;
1351 spin_unlock_irqrestore(&host->lock, flags);
1352
1353 if (done)
1354 return true;
1355 rsp = cmd->resp;
1356
1357 sdr_clr_bits(host->base + MSDC_INTEN, cmd_ints_mask);
1358
1359 if (cmd->flags & MMC_RSP_PRESENT) {
1360 if (cmd->flags & MMC_RSP_136) {
1361 rsp[0] = readl(host->base + SDC_RESP3);
1362 rsp[1] = readl(host->base + SDC_RESP2);
1363 rsp[2] = readl(host->base + SDC_RESP1);
1364 rsp[3] = readl(host->base + SDC_RESP0);
1365 } else {
1366 rsp[0] = readl(host->base + SDC_RESP0);
1367 }
1368 }
1369
1370 if (!sbc_error && !(events & MSDC_INT_CMDRDY)) {
1371 if ((events & MSDC_INT_CMDTMO && !host->hs400_tuning) ||
1372 (!mmc_op_tuning(cmd->opcode) && !host->hs400_tuning))
1373 /*
1374 * should not clear fifo/interrupt as the tune data
1375 * may have already come when cmd19/cmd21 gets response
1376 * CRC error.
1377 */
1378 msdc_reset_hw(host);
1379 if (events & MSDC_INT_RSPCRCERR &&
1380 mmc_resp_type(cmd) != MMC_RSP_R1B_NO_CRC) {
1381 cmd->error = -EILSEQ;
1382 host->error |= REQ_CMD_EIO;
1383 } else if (events & MSDC_INT_CMDTMO) {
1384 cmd->error = -ETIMEDOUT;
1385 host->error |= REQ_CMD_TMO;
1386 }
1387 }
1388 if (cmd->error)
1389 dev_dbg(host->dev,
1390 "%s: cmd=%d arg=%08X; rsp %08X; cmd_error=%d\n",
1391 __func__, cmd->opcode, cmd->arg, rsp[0],
1392 cmd->error);
1393
1394 msdc_cmd_next(host, mrq, cmd);
1395 return true;
1396 }
1397
1398 /* It is the core layer's responsibility to ensure card status
1399 * is correct before issue a request. but host design do below
1400 * checks recommended.
1401 */
msdc_cmd_is_ready(struct msdc_host * host,struct mmc_request * mrq,struct mmc_command * cmd)1402 static inline bool msdc_cmd_is_ready(struct msdc_host *host,
1403 struct mmc_request *mrq, struct mmc_command *cmd)
1404 {
1405 u32 val;
1406 int ret;
1407
1408 /* The max busy time we can endure is 20ms */
1409 ret = readl_poll_timeout_atomic(host->base + SDC_STS, val,
1410 !(val & SDC_STS_CMDBUSY), 1, 20000);
1411 if (ret) {
1412 dev_err(host->dev, "CMD bus busy detected\n");
1413 host->error |= REQ_CMD_BUSY;
1414 msdc_cmd_done(host, MSDC_INT_CMDTMO, mrq, cmd);
1415 return false;
1416 }
1417
1418 if (mmc_resp_type(cmd) == MMC_RSP_R1B || cmd->data) {
1419 /* R1B or with data, should check SDCBUSY */
1420 ret = readl_poll_timeout_atomic(host->base + SDC_STS, val,
1421 !(val & SDC_STS_SDCBUSY), 1, 20000);
1422 if (ret) {
1423 dev_err(host->dev, "Controller busy detected\n");
1424 host->error |= REQ_CMD_BUSY;
1425 msdc_cmd_done(host, MSDC_INT_CMDTMO, mrq, cmd);
1426 return false;
1427 }
1428 }
1429 return true;
1430 }
1431
msdc_start_command(struct msdc_host * host,struct mmc_request * mrq,struct mmc_command * cmd)1432 static void msdc_start_command(struct msdc_host *host,
1433 struct mmc_request *mrq, struct mmc_command *cmd)
1434 {
1435 u32 rawcmd;
1436 unsigned long flags;
1437
1438 WARN_ON(host->cmd);
1439 host->cmd = cmd;
1440
1441 mod_delayed_work(system_wq, &host->req_timeout, DAT_TIMEOUT);
1442 if (!msdc_cmd_is_ready(host, mrq, cmd))
1443 return;
1444
1445 if ((readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_TXCNT) >> 16 ||
1446 readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_RXCNT) {
1447 dev_err(host->dev, "TX/RX FIFO non-empty before start of IO. Reset\n");
1448 msdc_reset_hw(host);
1449 }
1450
1451 cmd->error = 0;
1452 rawcmd = msdc_cmd_prepare_raw_cmd(host, mrq, cmd);
1453
1454 spin_lock_irqsave(&host->lock, flags);
1455 sdr_set_bits(host->base + MSDC_INTEN, cmd_ints_mask);
1456 spin_unlock_irqrestore(&host->lock, flags);
1457
1458 writel(cmd->arg, host->base + SDC_ARG);
1459 writel(rawcmd, host->base + SDC_CMD);
1460 }
1461
msdc_cmd_next(struct msdc_host * host,struct mmc_request * mrq,struct mmc_command * cmd)1462 static void msdc_cmd_next(struct msdc_host *host,
1463 struct mmc_request *mrq, struct mmc_command *cmd)
1464 {
1465 if ((cmd->error && !host->hs400_tuning &&
1466 !(cmd->error == -EILSEQ &&
1467 mmc_op_tuning(cmd->opcode))) ||
1468 (mrq->sbc && mrq->sbc->error))
1469 msdc_request_done(host, mrq);
1470 else if (cmd == mrq->sbc)
1471 msdc_start_command(host, mrq, mrq->cmd);
1472 else if (!cmd->data)
1473 msdc_request_done(host, mrq);
1474 else
1475 msdc_start_data(host, cmd, cmd->data);
1476 }
1477
msdc_ops_request(struct mmc_host * mmc,struct mmc_request * mrq)1478 static void msdc_ops_request(struct mmc_host *mmc, struct mmc_request *mrq)
1479 {
1480 struct msdc_host *host = mmc_priv(mmc);
1481
1482 host->error = 0;
1483 WARN_ON(!host->hsq_en && host->mrq);
1484 host->mrq = mrq;
1485
1486 if (mrq->data)
1487 msdc_prepare_data(host, mrq->data);
1488
1489 /* if SBC is required, we have HW option and SW option.
1490 * if HW option is enabled, and SBC does not have "special" flags,
1491 * use HW option, otherwise use SW option
1492 */
1493 if (mrq->sbc && (!mmc_card_mmc(mmc->card) ||
1494 (mrq->sbc->arg & 0xFFFF0000)))
1495 msdc_start_command(host, mrq, mrq->sbc);
1496 else
1497 msdc_start_command(host, mrq, mrq->cmd);
1498 }
1499
msdc_pre_req(struct mmc_host * mmc,struct mmc_request * mrq)1500 static void msdc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq)
1501 {
1502 struct msdc_host *host = mmc_priv(mmc);
1503 struct mmc_data *data = mrq->data;
1504
1505 if (!data)
1506 return;
1507
1508 msdc_prepare_data(host, data);
1509 data->host_cookie |= MSDC_ASYNC_FLAG;
1510 }
1511
msdc_post_req(struct mmc_host * mmc,struct mmc_request * mrq,int err)1512 static void msdc_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
1513 int err)
1514 {
1515 struct msdc_host *host = mmc_priv(mmc);
1516 struct mmc_data *data = mrq->data;
1517
1518 if (!data)
1519 return;
1520
1521 if (data->host_cookie) {
1522 data->host_cookie &= ~MSDC_ASYNC_FLAG;
1523 msdc_unprepare_data(host, data);
1524 }
1525 }
1526
msdc_data_xfer_next(struct msdc_host * host,struct mmc_request * mrq)1527 static void msdc_data_xfer_next(struct msdc_host *host, struct mmc_request *mrq)
1528 {
1529 if (mmc_op_multi(mrq->cmd->opcode) && mrq->stop && !mrq->stop->error &&
1530 !mrq->sbc)
1531 msdc_start_command(host, mrq, mrq->stop);
1532 else
1533 msdc_request_done(host, mrq);
1534 }
1535
msdc_data_xfer_done(struct msdc_host * host,u32 events,struct mmc_request * mrq,struct mmc_data * data)1536 static void msdc_data_xfer_done(struct msdc_host *host, u32 events,
1537 struct mmc_request *mrq, struct mmc_data *data)
1538 {
1539 struct mmc_command *stop;
1540 unsigned long flags;
1541 bool done;
1542 unsigned int check_data = events &
1543 (MSDC_INT_XFER_COMPL | MSDC_INT_DATCRCERR | MSDC_INT_DATTMO
1544 | MSDC_INT_DMA_BDCSERR | MSDC_INT_DMA_GPDCSERR
1545 | MSDC_INT_DMA_PROTECT);
1546 u32 val;
1547 int ret;
1548
1549 spin_lock_irqsave(&host->lock, flags);
1550 done = !host->data;
1551 if (check_data)
1552 host->data = NULL;
1553 spin_unlock_irqrestore(&host->lock, flags);
1554
1555 if (done)
1556 return;
1557 stop = data->stop;
1558
1559 if (check_data || (stop && stop->error)) {
1560 dev_dbg(host->dev, "DMA status: 0x%8X\n",
1561 readl(host->base + MSDC_DMA_CFG));
1562 sdr_set_field(host->base + MSDC_DMA_CTRL, MSDC_DMA_CTRL_STOP,
1563 1);
1564
1565 ret = readl_poll_timeout_atomic(host->base + MSDC_DMA_CTRL, val,
1566 !(val & MSDC_DMA_CTRL_STOP), 1, 20000);
1567 if (ret)
1568 dev_dbg(host->dev, "DMA stop timed out\n");
1569
1570 ret = readl_poll_timeout_atomic(host->base + MSDC_DMA_CFG, val,
1571 !(val & MSDC_DMA_CFG_STS), 1, 20000);
1572 if (ret)
1573 dev_dbg(host->dev, "DMA inactive timed out\n");
1574
1575 sdr_clr_bits(host->base + MSDC_INTEN, data_ints_mask);
1576 dev_dbg(host->dev, "DMA stop\n");
1577
1578 if ((events & MSDC_INT_XFER_COMPL) && (!stop || !stop->error)) {
1579 data->bytes_xfered = data->blocks * data->blksz;
1580 } else {
1581 dev_dbg(host->dev, "interrupt events: %x\n", events);
1582 msdc_reset_hw(host);
1583 host->error |= REQ_DAT_ERR;
1584 data->bytes_xfered = 0;
1585
1586 if (events & MSDC_INT_DATTMO)
1587 data->error = -ETIMEDOUT;
1588 else if (events & MSDC_INT_DATCRCERR)
1589 data->error = -EILSEQ;
1590
1591 dev_dbg(host->dev, "%s: cmd=%d; blocks=%d",
1592 __func__, mrq->cmd->opcode, data->blocks);
1593 dev_dbg(host->dev, "data_error=%d xfer_size=%d\n",
1594 (int)data->error, data->bytes_xfered);
1595 }
1596
1597 msdc_data_xfer_next(host, mrq);
1598 }
1599 }
1600
msdc_set_buswidth(struct msdc_host * host,u32 width)1601 static void msdc_set_buswidth(struct msdc_host *host, u32 width)
1602 {
1603 u32 val = readl(host->base + SDC_CFG);
1604
1605 val &= ~SDC_CFG_BUSWIDTH;
1606
1607 switch (width) {
1608 default:
1609 case MMC_BUS_WIDTH_1:
1610 val |= (MSDC_BUS_1BITS << 16);
1611 break;
1612 case MMC_BUS_WIDTH_4:
1613 val |= (MSDC_BUS_4BITS << 16);
1614 break;
1615 case MMC_BUS_WIDTH_8:
1616 val |= (MSDC_BUS_8BITS << 16);
1617 break;
1618 }
1619
1620 writel(val, host->base + SDC_CFG);
1621 dev_dbg(host->dev, "Bus Width = %d", width);
1622 }
1623
msdc_ops_switch_volt(struct mmc_host * mmc,struct mmc_ios * ios)1624 static int msdc_ops_switch_volt(struct mmc_host *mmc, struct mmc_ios *ios)
1625 {
1626 struct msdc_host *host = mmc_priv(mmc);
1627 int ret;
1628
1629 if (!IS_ERR(mmc->supply.vqmmc)) {
1630 if (ios->signal_voltage != MMC_SIGNAL_VOLTAGE_330 &&
1631 ios->signal_voltage != MMC_SIGNAL_VOLTAGE_180) {
1632 dev_err(host->dev, "Unsupported signal voltage!\n");
1633 return -EINVAL;
1634 }
1635
1636 ret = mmc_regulator_set_vqmmc(mmc, ios);
1637 if (ret < 0) {
1638 dev_dbg(host->dev, "Regulator set error %d (%d)\n",
1639 ret, ios->signal_voltage);
1640 return ret;
1641 }
1642
1643 /* Apply different pinctrl settings for different signal voltage */
1644 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180)
1645 pinctrl_select_state(host->pinctrl, host->pins_uhs);
1646 else
1647 pinctrl_select_state(host->pinctrl, host->pins_default);
1648 }
1649 return 0;
1650 }
1651
msdc_card_busy(struct mmc_host * mmc)1652 static int msdc_card_busy(struct mmc_host *mmc)
1653 {
1654 struct msdc_host *host = mmc_priv(mmc);
1655 u32 status = readl(host->base + MSDC_PS);
1656
1657 /* only check if data0 is low */
1658 return !(status & BIT(16));
1659 }
1660
msdc_request_timeout(struct work_struct * work)1661 static void msdc_request_timeout(struct work_struct *work)
1662 {
1663 struct msdc_host *host = container_of(work, struct msdc_host,
1664 req_timeout.work);
1665
1666 /* simulate HW timeout status */
1667 dev_err(host->dev, "%s: aborting cmd/data/mrq\n", __func__);
1668 if (host->mrq) {
1669 dev_err(host->dev, "%s: aborting mrq=%p cmd=%d\n", __func__,
1670 host->mrq, host->mrq->cmd->opcode);
1671 if (host->cmd) {
1672 dev_err(host->dev, "%s: aborting cmd=%d\n",
1673 __func__, host->cmd->opcode);
1674 msdc_cmd_done(host, MSDC_INT_CMDTMO, host->mrq,
1675 host->cmd);
1676 } else if (host->data) {
1677 dev_err(host->dev, "%s: abort data: cmd%d; %d blocks\n",
1678 __func__, host->mrq->cmd->opcode,
1679 host->data->blocks);
1680 msdc_data_xfer_done(host, MSDC_INT_DATTMO, host->mrq,
1681 host->data);
1682 }
1683 }
1684 }
1685
__msdc_enable_sdio_irq(struct msdc_host * host,int enb)1686 static void __msdc_enable_sdio_irq(struct msdc_host *host, int enb)
1687 {
1688 if (enb) {
1689 sdr_set_bits(host->base + MSDC_INTEN, MSDC_INTEN_SDIOIRQ);
1690 sdr_set_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE);
1691 if (host->dev_comp->recheck_sdio_irq)
1692 msdc_recheck_sdio_irq(host);
1693 } else {
1694 sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INTEN_SDIOIRQ);
1695 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE);
1696 }
1697 }
1698
msdc_enable_sdio_irq(struct mmc_host * mmc,int enb)1699 static void msdc_enable_sdio_irq(struct mmc_host *mmc, int enb)
1700 {
1701 struct msdc_host *host = mmc_priv(mmc);
1702 unsigned long flags;
1703 int ret;
1704
1705 spin_lock_irqsave(&host->lock, flags);
1706 __msdc_enable_sdio_irq(host, enb);
1707 spin_unlock_irqrestore(&host->lock, flags);
1708
1709 if (mmc_card_enable_async_irq(mmc->card) && host->pins_eint) {
1710 if (enb) {
1711 /*
1712 * In dev_pm_set_dedicated_wake_irq_reverse(), eint pin will be set to
1713 * GPIO mode. We need to restore it to SDIO DAT1 mode after that.
1714 * Since the current pinstate is pins_uhs, to ensure pinctrl select take
1715 * affect successfully, we change the pinstate to pins_eint firstly.
1716 */
1717 pinctrl_select_state(host->pinctrl, host->pins_eint);
1718 ret = dev_pm_set_dedicated_wake_irq_reverse(host->dev, host->eint_irq);
1719
1720 if (ret) {
1721 dev_err(host->dev, "Failed to register SDIO wakeup irq!\n");
1722 host->pins_eint = NULL;
1723 pm_runtime_get_noresume(host->dev);
1724 } else {
1725 dev_dbg(host->dev, "SDIO eint irq: %d!\n", host->eint_irq);
1726 }
1727
1728 pinctrl_select_state(host->pinctrl, host->pins_uhs);
1729 } else {
1730 dev_pm_clear_wake_irq(host->dev);
1731 }
1732 } else {
1733 if (enb) {
1734 /* Ensure host->pins_eint is NULL */
1735 host->pins_eint = NULL;
1736 pm_runtime_get_noresume(host->dev);
1737 } else {
1738 pm_runtime_put_noidle(host->dev);
1739 }
1740 }
1741 }
1742
msdc_cmdq_irq(struct msdc_host * host,u32 intsts)1743 static irqreturn_t msdc_cmdq_irq(struct msdc_host *host, u32 intsts)
1744 {
1745 struct mmc_host *mmc = mmc_from_priv(host);
1746 int cmd_err = 0, dat_err = 0;
1747
1748 if (intsts & MSDC_INT_RSPCRCERR) {
1749 cmd_err = -EILSEQ;
1750 dev_err(host->dev, "%s: CMD CRC ERR", __func__);
1751 } else if (intsts & MSDC_INT_CMDTMO) {
1752 cmd_err = -ETIMEDOUT;
1753 dev_err(host->dev, "%s: CMD TIMEOUT ERR", __func__);
1754 }
1755
1756 if (intsts & MSDC_INT_DATCRCERR) {
1757 dat_err = -EILSEQ;
1758 dev_err(host->dev, "%s: DATA CRC ERR", __func__);
1759 } else if (intsts & MSDC_INT_DATTMO) {
1760 dat_err = -ETIMEDOUT;
1761 dev_err(host->dev, "%s: DATA TIMEOUT ERR", __func__);
1762 }
1763
1764 if (cmd_err || dat_err) {
1765 dev_err(host->dev, "cmd_err = %d, dat_err = %d, intsts = 0x%x",
1766 cmd_err, dat_err, intsts);
1767 }
1768
1769 return cqhci_irq(mmc, 0, cmd_err, dat_err);
1770 }
1771
msdc_irq(int irq,void * dev_id)1772 static irqreturn_t msdc_irq(int irq, void *dev_id)
1773 {
1774 struct msdc_host *host = (struct msdc_host *) dev_id;
1775 struct mmc_host *mmc = mmc_from_priv(host);
1776
1777 while (true) {
1778 struct mmc_request *mrq;
1779 struct mmc_command *cmd;
1780 struct mmc_data *data;
1781 u32 events, event_mask;
1782
1783 spin_lock(&host->lock);
1784 events = readl(host->base + MSDC_INT);
1785 event_mask = readl(host->base + MSDC_INTEN);
1786 if ((events & event_mask) & MSDC_INT_SDIOIRQ)
1787 __msdc_enable_sdio_irq(host, 0);
1788 /* clear interrupts */
1789 writel(events & event_mask, host->base + MSDC_INT);
1790
1791 mrq = host->mrq;
1792 cmd = host->cmd;
1793 data = host->data;
1794 spin_unlock(&host->lock);
1795
1796 if ((events & event_mask) & MSDC_INT_SDIOIRQ)
1797 sdio_signal_irq(mmc);
1798
1799 if ((events & event_mask) & MSDC_INT_CDSC) {
1800 if (host->internal_cd)
1801 mmc_detect_change(mmc, msecs_to_jiffies(20));
1802 events &= ~MSDC_INT_CDSC;
1803 }
1804
1805 if (!(events & (event_mask & ~MSDC_INT_SDIOIRQ)))
1806 break;
1807
1808 if ((mmc->caps2 & MMC_CAP2_CQE) &&
1809 (events & MSDC_INT_CMDQ)) {
1810 msdc_cmdq_irq(host, events);
1811 /* clear interrupts */
1812 writel(events, host->base + MSDC_INT);
1813 return IRQ_HANDLED;
1814 }
1815
1816 if (!mrq) {
1817 dev_err(host->dev,
1818 "%s: MRQ=NULL; events=%08X; event_mask=%08X\n",
1819 __func__, events, event_mask);
1820 WARN_ON(1);
1821 break;
1822 }
1823
1824 dev_dbg(host->dev, "%s: events=%08X\n", __func__, events);
1825
1826 if (cmd)
1827 msdc_cmd_done(host, events, mrq, cmd);
1828 else if (data)
1829 msdc_data_xfer_done(host, events, mrq, data);
1830 }
1831
1832 return IRQ_HANDLED;
1833 }
1834
msdc_init_hw(struct msdc_host * host)1835 static void msdc_init_hw(struct msdc_host *host)
1836 {
1837 u32 val, pb1_val, pb2_val;
1838 u32 tune_reg = host->dev_comp->pad_tune_reg;
1839 struct mmc_host *mmc = mmc_from_priv(host);
1840
1841 if (host->reset) {
1842 reset_control_assert(host->reset);
1843 usleep_range(10, 50);
1844 reset_control_deassert(host->reset);
1845 }
1846
1847 /* New tx/rx enable bit need to be 0->1 for hardware check */
1848 if (host->dev_comp->support_new_tx) {
1849 sdr_clr_bits(host->base + SDC_ADV_CFG0, SDC_NEW_TX_EN);
1850 sdr_set_bits(host->base + SDC_ADV_CFG0, SDC_NEW_TX_EN);
1851 msdc_new_tx_setting(host);
1852 }
1853 if (host->dev_comp->support_new_rx) {
1854 sdr_clr_bits(host->base + MSDC_NEW_RX_CFG, MSDC_NEW_RX_PATH_SEL);
1855 sdr_set_bits(host->base + MSDC_NEW_RX_CFG, MSDC_NEW_RX_PATH_SEL);
1856 }
1857
1858 /* Configure to MMC/SD mode, clock free running */
1859 sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_MODE | MSDC_CFG_CKPDN);
1860
1861 /* Reset */
1862 msdc_reset_hw(host);
1863
1864 /* Disable and clear all interrupts */
1865 writel(0, host->base + MSDC_INTEN);
1866 val = readl(host->base + MSDC_INT);
1867 writel(val, host->base + MSDC_INT);
1868
1869 /* Configure card detection */
1870 if (host->internal_cd) {
1871 sdr_set_field(host->base + MSDC_PS, MSDC_PS_CDDEBOUNCE,
1872 DEFAULT_DEBOUNCE);
1873 sdr_set_bits(host->base + MSDC_PS, MSDC_PS_CDEN);
1874 sdr_set_bits(host->base + MSDC_INTEN, MSDC_INTEN_CDSC);
1875 sdr_set_bits(host->base + SDC_CFG, SDC_CFG_INSWKUP);
1876 } else {
1877 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_INSWKUP);
1878 sdr_clr_bits(host->base + MSDC_PS, MSDC_PS_CDEN);
1879 sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INTEN_CDSC);
1880 }
1881
1882 if (host->top_base) {
1883 writel(0, host->top_base + EMMC_TOP_CONTROL);
1884 writel(0, host->top_base + EMMC_TOP_CMD);
1885 } else {
1886 writel(0, host->base + tune_reg);
1887 }
1888 writel(0, host->base + MSDC_IOCON);
1889 sdr_set_field(host->base + MSDC_IOCON, MSDC_IOCON_DDLSEL, 0);
1890
1891 /*
1892 * Patch bit 0 and 1 are completely rewritten, but for patch bit 2
1893 * defaults are retained and, if necessary, only some bits are fixed
1894 * up: read the PB2 register here for later usage in this function.
1895 */
1896 pb2_val = readl(host->base + MSDC_PATCH_BIT2);
1897
1898 /* Enable odd number support for 8-bit data bus */
1899 val = MSDC_PATCH_BIT_ODDSUPP;
1900
1901 /* Disable SD command register write monitor */
1902 val |= MSDC_PATCH_BIT_DIS_WRMON;
1903
1904 /* Issue transfer done interrupt after GPD update */
1905 val |= MSDC_PATCH_BIT_DESCUP_SEL;
1906
1907 /* Extend R1B busy detection delay (in clock cycles) */
1908 val |= FIELD_PREP(MSDC_PATCH_BIT_BUSYDLY, 15);
1909
1910 /* Enable CRC phase timeout during data write operation */
1911 val |= MSDC_PATCH_BIT_DECRCTMO;
1912
1913 /* Set CKGEN delay to one stage */
1914 val |= FIELD_PREP(MSDC_CKGEN_MSDC_DLY_SEL, 1);
1915
1916 /* First MSDC_PATCH_BIT setup is done: pull the trigger! */
1917 writel(val, host->base + MSDC_PATCH_BIT);
1918
1919 /* Set wr data, crc status, cmd response turnaround period for UHS104 */
1920 pb1_val = FIELD_PREP(MSDC_PB1_WRDAT_CRC_TACNTR, 1);
1921 pb1_val |= FIELD_PREP(MSDC_PATCH_BIT1_CMDTA, 1);
1922 pb1_val |= MSDC_PB1_DDR_CMD_FIX_SEL;
1923
1924 /* Support 'single' burst type only when AXI_LEN is 0 */
1925 sdr_get_field(host->base + EMMC50_CFG2, EMMC50_CFG2_AXI_SET_LEN, &val);
1926 if (!val)
1927 pb1_val |= MSDC_PB1_SINGLE_BURST;
1928
1929 /* Set auto sync state clear, block gap stop clk */
1930 pb1_val |= MSDC_PB1_RSVD20 | MSDC_PB1_AUTO_SYNCST_CLR | MSDC_PB1_MARK_POP_WATER;
1931
1932 /* Set low power DCM, use HCLK for GDMA, use MSDC CLK for everything else */
1933 pb1_val |= MSDC_PB1_LP_DCM_EN | MSDC_PB1_RSVD3 |
1934 MSDC_PB1_AHB_GDMA_HCLK | MSDC_PB1_MSDC_CLK_ENFEAT;
1935
1936 /* If needed, enable R1b command busy check at controller init time */
1937 if (!host->dev_comp->busy_check)
1938 pb1_val |= MSDC_PB1_BUSY_CHECK_SEL;
1939
1940 if (host->dev_comp->stop_clk_fix) {
1941 if (host->dev_comp->stop_dly_sel)
1942 pb1_val |= FIELD_PREP(MSDC_PATCH_BIT1_STOP_DLY,
1943 host->dev_comp->stop_dly_sel);
1944
1945 if (host->dev_comp->pop_en_cnt) {
1946 pb2_val &= ~MSDC_PB2_POP_EN_CNT;
1947 pb2_val |= FIELD_PREP(MSDC_PB2_POP_EN_CNT,
1948 host->dev_comp->pop_en_cnt);
1949 }
1950
1951 sdr_clr_bits(host->base + SDC_FIFO_CFG, SDC_FIFO_CFG_WRVALIDSEL);
1952 sdr_clr_bits(host->base + SDC_FIFO_CFG, SDC_FIFO_CFG_RDVALIDSEL);
1953 }
1954
1955 if (host->dev_comp->async_fifo) {
1956 /* Set CMD response timeout multiplier to 65 + (16 * 3) cycles */
1957 pb2_val &= ~MSDC_PB2_RESPWAIT;
1958 pb2_val |= FIELD_PREP(MSDC_PB2_RESPWAIT, 3);
1959
1960 /* eMMC4.5: Select async FIFO path for CMD resp and CRC status */
1961 pb2_val &= ~MSDC_PATCH_BIT2_CFGRESP;
1962 pb2_val |= MSDC_PATCH_BIT2_CFGCRCSTS;
1963
1964 if (!host->dev_comp->enhance_rx) {
1965 /* eMMC4.5: Delay 2T for CMD resp and CRC status EN signals */
1966 pb2_val &= ~(MSDC_PB2_RESPSTSENSEL | MSDC_PB2_CRCSTSENSEL);
1967 pb2_val |= FIELD_PREP(MSDC_PB2_RESPSTSENSEL, 2);
1968 pb2_val |= FIELD_PREP(MSDC_PB2_CRCSTSENSEL, 2);
1969 } else if (host->top_base) {
1970 sdr_set_bits(host->top_base + EMMC_TOP_CONTROL, SDC_RX_ENH_EN);
1971 } else {
1972 sdr_set_bits(host->base + SDC_ADV_CFG0, SDC_RX_ENHANCE_EN);
1973 }
1974 }
1975
1976 if (host->dev_comp->support_64g)
1977 pb2_val |= MSDC_PB2_SUPPORT_64G;
1978
1979 /* Patch Bit 1/2 setup is done: pull the trigger! */
1980 writel(pb1_val, host->base + MSDC_PATCH_BIT1);
1981 writel(pb2_val, host->base + MSDC_PATCH_BIT2);
1982 sdr_set_bits(host->base + EMMC50_CFG0, EMMC50_CFG_CFCSTS_SEL);
1983
1984 if (host->dev_comp->data_tune) {
1985 if (host->top_base) {
1986 u32 top_ctl_val = readl(host->top_base + EMMC_TOP_CONTROL);
1987 u32 top_cmd_val = readl(host->top_base + EMMC_TOP_CMD);
1988
1989 top_cmd_val |= PAD_CMD_RD_RXDLY_SEL;
1990 top_ctl_val |= PAD_DAT_RD_RXDLY_SEL;
1991 top_ctl_val &= ~DATA_K_VALUE_SEL;
1992 if (host->tuning_step > PAD_DELAY_HALF) {
1993 top_cmd_val |= PAD_CMD_RD_RXDLY2_SEL;
1994 top_ctl_val |= PAD_DAT_RD_RXDLY2_SEL;
1995 }
1996
1997 writel(top_ctl_val, host->top_base + EMMC_TOP_CONTROL);
1998 writel(top_cmd_val, host->top_base + EMMC_TOP_CMD);
1999 } else {
2000 sdr_set_bits(host->base + tune_reg,
2001 MSDC_PAD_TUNE_RD_SEL |
2002 MSDC_PAD_TUNE_CMD_SEL);
2003 if (host->tuning_step > PAD_DELAY_HALF)
2004 sdr_set_bits(host->base + tune_reg + TUNING_REG2_FIXED_OFFEST,
2005 MSDC_PAD_TUNE_RD2_SEL |
2006 MSDC_PAD_TUNE_CMD2_SEL);
2007 }
2008 } else {
2009 /* choose clock tune */
2010 if (host->top_base)
2011 sdr_set_bits(host->top_base + EMMC_TOP_CONTROL,
2012 PAD_RXDLY_SEL);
2013 else
2014 sdr_set_bits(host->base + tune_reg,
2015 MSDC_PAD_TUNE_RXDLYSEL);
2016 }
2017
2018 if (mmc->caps2 & MMC_CAP2_NO_SDIO) {
2019 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIO);
2020 sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INTEN_SDIOIRQ);
2021 sdr_clr_bits(host->base + SDC_ADV_CFG0, SDC_DAT1_IRQ_TRIGGER);
2022 } else {
2023 /* Configure to enable SDIO mode, otherwise SDIO CMD5 fails */
2024 sdr_set_bits(host->base + SDC_CFG, SDC_CFG_SDIO);
2025
2026 /* Config SDIO device detect interrupt function */
2027 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE);
2028 sdr_set_bits(host->base + SDC_ADV_CFG0, SDC_DAT1_IRQ_TRIGGER);
2029 }
2030
2031 /* Configure to default data timeout */
2032 sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC, 3);
2033
2034 host->def_tune_para.iocon = readl(host->base + MSDC_IOCON);
2035 host->saved_tune_para.iocon = readl(host->base + MSDC_IOCON);
2036 if (host->top_base) {
2037 host->def_tune_para.emmc_top_control =
2038 readl(host->top_base + EMMC_TOP_CONTROL);
2039 host->def_tune_para.emmc_top_cmd =
2040 readl(host->top_base + EMMC_TOP_CMD);
2041 host->saved_tune_para.emmc_top_control =
2042 readl(host->top_base + EMMC_TOP_CONTROL);
2043 host->saved_tune_para.emmc_top_cmd =
2044 readl(host->top_base + EMMC_TOP_CMD);
2045 } else {
2046 host->def_tune_para.pad_tune = readl(host->base + tune_reg);
2047 host->saved_tune_para.pad_tune = readl(host->base + tune_reg);
2048 }
2049 dev_dbg(host->dev, "init hardware done!");
2050 }
2051
msdc_deinit_hw(struct msdc_host * host)2052 static void msdc_deinit_hw(struct msdc_host *host)
2053 {
2054 u32 val;
2055
2056 if (host->internal_cd) {
2057 /* Disabled card-detect */
2058 sdr_clr_bits(host->base + MSDC_PS, MSDC_PS_CDEN);
2059 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_INSWKUP);
2060 }
2061
2062 /* Disable and clear all interrupts */
2063 writel(0, host->base + MSDC_INTEN);
2064
2065 val = readl(host->base + MSDC_INT);
2066 writel(val, host->base + MSDC_INT);
2067 }
2068
2069 /* init gpd and bd list in msdc_drv_probe */
msdc_init_gpd_bd(struct msdc_host * host,struct msdc_dma * dma)2070 static void msdc_init_gpd_bd(struct msdc_host *host, struct msdc_dma *dma)
2071 {
2072 struct mt_gpdma_desc *gpd = dma->gpd;
2073 struct mt_bdma_desc *bd = dma->bd;
2074 dma_addr_t dma_addr;
2075 int i;
2076
2077 memset(gpd, 0, sizeof(struct mt_gpdma_desc) * 2);
2078
2079 dma_addr = dma->gpd_addr + sizeof(struct mt_gpdma_desc);
2080 gpd->gpd_info = GPDMA_DESC_BDP; /* hwo, cs, bd pointer */
2081 /* gpd->next is must set for desc DMA
2082 * That's why must alloc 2 gpd structure.
2083 */
2084 gpd->next = lower_32_bits(dma_addr);
2085 if (host->dev_comp->support_64g)
2086 gpd->gpd_info |= (upper_32_bits(dma_addr) & 0xf) << 24;
2087
2088 dma_addr = dma->bd_addr;
2089 gpd->ptr = lower_32_bits(dma->bd_addr); /* physical address */
2090 if (host->dev_comp->support_64g)
2091 gpd->gpd_info |= (upper_32_bits(dma_addr) & 0xf) << 28;
2092
2093 memset(bd, 0, sizeof(struct mt_bdma_desc) * MAX_BD_NUM);
2094 for (i = 0; i < (MAX_BD_NUM - 1); i++) {
2095 dma_addr = dma->bd_addr + sizeof(*bd) * (i + 1);
2096 bd[i].next = lower_32_bits(dma_addr);
2097 if (host->dev_comp->support_64g)
2098 bd[i].bd_info |= (upper_32_bits(dma_addr) & 0xf) << 24;
2099 }
2100 }
2101
msdc_ops_set_ios(struct mmc_host * mmc,struct mmc_ios * ios)2102 static void msdc_ops_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
2103 {
2104 struct msdc_host *host = mmc_priv(mmc);
2105 int ret;
2106
2107 msdc_set_buswidth(host, ios->bus_width);
2108
2109 /* Suspend/Resume will do power off/on */
2110 switch (ios->power_mode) {
2111 case MMC_POWER_UP:
2112 if (!IS_ERR(mmc->supply.vmmc)) {
2113 msdc_init_hw(host);
2114 ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc,
2115 ios->vdd);
2116 if (ret) {
2117 dev_err(host->dev, "Failed to set vmmc power!\n");
2118 return;
2119 }
2120 }
2121 break;
2122 case MMC_POWER_ON:
2123 if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) {
2124 ret = regulator_enable(mmc->supply.vqmmc);
2125 if (ret)
2126 dev_err(host->dev, "Failed to set vqmmc power!\n");
2127 else
2128 host->vqmmc_enabled = true;
2129 }
2130 break;
2131 case MMC_POWER_OFF:
2132 if (!IS_ERR(mmc->supply.vmmc))
2133 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
2134
2135 if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) {
2136 regulator_disable(mmc->supply.vqmmc);
2137 host->vqmmc_enabled = false;
2138 }
2139 break;
2140 default:
2141 break;
2142 }
2143
2144 if (host->mclk != ios->clock || host->timing != ios->timing)
2145 msdc_set_mclk(host, ios->timing, ios->clock);
2146 }
2147
test_delay_bit(u64 delay,u32 bit)2148 static u64 test_delay_bit(u64 delay, u32 bit)
2149 {
2150 bit %= PAD_DELAY_FULL;
2151 return delay & BIT_ULL(bit);
2152 }
2153
get_delay_len(u64 delay,u32 start_bit)2154 static int get_delay_len(u64 delay, u32 start_bit)
2155 {
2156 int i;
2157
2158 for (i = 0; i < (PAD_DELAY_FULL - start_bit); i++) {
2159 if (test_delay_bit(delay, start_bit + i) == 0)
2160 return i;
2161 }
2162 return PAD_DELAY_FULL - start_bit;
2163 }
2164
get_best_delay(struct msdc_host * host,u64 delay)2165 static struct msdc_delay_phase get_best_delay(struct msdc_host *host, u64 delay)
2166 {
2167 int start = 0, len = 0;
2168 int start_final = 0, len_final = 0;
2169 u8 final_phase = 0xff;
2170 struct msdc_delay_phase delay_phase = { 0, };
2171
2172 if (delay == 0) {
2173 dev_err(host->dev, "phase error: [map:%016llx]\n", delay);
2174 delay_phase.final_phase = final_phase;
2175 return delay_phase;
2176 }
2177
2178 while (start < PAD_DELAY_FULL) {
2179 len = get_delay_len(delay, start);
2180 if (len_final < len) {
2181 start_final = start;
2182 len_final = len;
2183 }
2184 start += len ? len : 1;
2185 if (!upper_32_bits(delay) && len >= 12 && start_final < 4)
2186 break;
2187 }
2188
2189 /* The rule is that to find the smallest delay cell */
2190 if (start_final == 0)
2191 final_phase = (start_final + len_final / 3) % PAD_DELAY_FULL;
2192 else
2193 final_phase = (start_final + len_final / 2) % PAD_DELAY_FULL;
2194 dev_dbg(host->dev, "phase: [map:%016llx] [maxlen:%d] [final:%d]\n",
2195 delay, len_final, final_phase);
2196
2197 delay_phase.maxlen = len_final;
2198 delay_phase.start = start_final;
2199 delay_phase.final_phase = final_phase;
2200 return delay_phase;
2201 }
2202
msdc_set_cmd_delay(struct msdc_host * host,u32 value)2203 static inline void msdc_set_cmd_delay(struct msdc_host *host, u32 value)
2204 {
2205 u32 tune_reg = host->dev_comp->pad_tune_reg;
2206
2207 if (host->top_base) {
2208 u32 regval = readl(host->top_base + EMMC_TOP_CMD);
2209
2210 regval &= ~(PAD_CMD_RXDLY | PAD_CMD_RXDLY2);
2211
2212 if (value < PAD_DELAY_HALF) {
2213 regval |= FIELD_PREP(PAD_CMD_RXDLY, value);
2214 } else {
2215 regval |= FIELD_PREP(PAD_CMD_RXDLY, PAD_DELAY_HALF - 1);
2216 regval |= FIELD_PREP(PAD_CMD_RXDLY2, value - PAD_DELAY_HALF);
2217 }
2218 writel(regval, host->top_base + EMMC_TOP_CMD);
2219 } else {
2220 if (value < PAD_DELAY_HALF) {
2221 sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_CMDRDLY, value);
2222 sdr_set_field(host->base + tune_reg + TUNING_REG2_FIXED_OFFEST,
2223 MSDC_PAD_TUNE_CMDRDLY2, 0);
2224 } else {
2225 sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_CMDRDLY,
2226 PAD_DELAY_HALF - 1);
2227 sdr_set_field(host->base + tune_reg + TUNING_REG2_FIXED_OFFEST,
2228 MSDC_PAD_TUNE_CMDRDLY2, value - PAD_DELAY_HALF);
2229 }
2230 }
2231 }
2232
msdc_set_data_delay(struct msdc_host * host,u32 value)2233 static inline void msdc_set_data_delay(struct msdc_host *host, u32 value)
2234 {
2235 u32 tune_reg = host->dev_comp->pad_tune_reg;
2236
2237 if (host->top_base) {
2238 u32 regval = readl(host->top_base + EMMC_TOP_CONTROL);
2239
2240 regval &= ~(PAD_DAT_RD_RXDLY | PAD_DAT_RD_RXDLY2);
2241
2242 if (value < PAD_DELAY_HALF) {
2243 regval |= FIELD_PREP(PAD_DAT_RD_RXDLY, value);
2244 regval |= FIELD_PREP(PAD_DAT_RD_RXDLY2, value);
2245 } else {
2246 regval |= FIELD_PREP(PAD_DAT_RD_RXDLY, PAD_DELAY_HALF - 1);
2247 regval |= FIELD_PREP(PAD_DAT_RD_RXDLY2, value - PAD_DELAY_HALF);
2248 }
2249 writel(regval, host->top_base + EMMC_TOP_CONTROL);
2250 } else {
2251 if (value < PAD_DELAY_HALF) {
2252 sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_DATRRDLY, value);
2253 sdr_set_field(host->base + tune_reg + TUNING_REG2_FIXED_OFFEST,
2254 MSDC_PAD_TUNE_DATRRDLY2, 0);
2255 } else {
2256 sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_DATRRDLY,
2257 PAD_DELAY_HALF - 1);
2258 sdr_set_field(host->base + tune_reg + TUNING_REG2_FIXED_OFFEST,
2259 MSDC_PAD_TUNE_DATRRDLY2, value - PAD_DELAY_HALF);
2260 }
2261 }
2262 }
2263
msdc_set_data_sample_edge(struct msdc_host * host,bool rising)2264 static inline void msdc_set_data_sample_edge(struct msdc_host *host, bool rising)
2265 {
2266 u32 value = rising ? 0 : 1;
2267
2268 if (host->dev_comp->support_new_rx) {
2269 sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_PATCH_BIT_RD_DAT_SEL, value);
2270 sdr_set_field(host->base + MSDC_PATCH_BIT2, MSDC_PB2_CFGCRCSTSEDGE, value);
2271 } else {
2272 sdr_set_field(host->base + MSDC_IOCON, MSDC_IOCON_DSPL, value);
2273 sdr_set_field(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL, value);
2274 }
2275 }
2276
msdc_tune_response(struct mmc_host * mmc,u32 opcode)2277 static int msdc_tune_response(struct mmc_host *mmc, u32 opcode)
2278 {
2279 struct msdc_host *host = mmc_priv(mmc);
2280 u64 rise_delay = 0, fall_delay = 0;
2281 struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0,};
2282 struct msdc_delay_phase internal_delay_phase;
2283 u8 final_delay, final_maxlen;
2284 u32 internal_delay = 0;
2285 u32 tune_reg = host->dev_comp->pad_tune_reg;
2286 int cmd_err;
2287 int i, j;
2288
2289 if (mmc->ios.timing == MMC_TIMING_MMC_HS200 ||
2290 mmc->ios.timing == MMC_TIMING_UHS_SDR104)
2291 sdr_set_field(host->base + tune_reg,
2292 MSDC_PAD_TUNE_CMDRRDLY,
2293 host->hs200_cmd_int_delay);
2294
2295 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2296 for (i = 0; i < host->tuning_step; i++) {
2297 msdc_set_cmd_delay(host, i);
2298 /*
2299 * Using the same parameters, it may sometimes pass the test,
2300 * but sometimes it may fail. To make sure the parameters are
2301 * more stable, we test each set of parameters 3 times.
2302 */
2303 for (j = 0; j < 3; j++) {
2304 mmc_send_tuning(mmc, opcode, &cmd_err);
2305 if (!cmd_err) {
2306 rise_delay |= BIT_ULL(i);
2307 } else {
2308 rise_delay &= ~BIT_ULL(i);
2309 break;
2310 }
2311 }
2312 }
2313 final_rise_delay = get_best_delay(host, rise_delay);
2314 /* if rising edge has enough margin, then do not scan falling edge */
2315 if (final_rise_delay.maxlen >= 12 ||
2316 (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4))
2317 goto skip_fall;
2318
2319 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2320 for (i = 0; i < host->tuning_step; i++) {
2321 msdc_set_cmd_delay(host, i);
2322 /*
2323 * Using the same parameters, it may sometimes pass the test,
2324 * but sometimes it may fail. To make sure the parameters are
2325 * more stable, we test each set of parameters 3 times.
2326 */
2327 for (j = 0; j < 3; j++) {
2328 mmc_send_tuning(mmc, opcode, &cmd_err);
2329 if (!cmd_err) {
2330 fall_delay |= BIT_ULL(i);
2331 } else {
2332 fall_delay &= ~BIT_ULL(i);
2333 break;
2334 }
2335 }
2336 }
2337 final_fall_delay = get_best_delay(host, fall_delay);
2338
2339 skip_fall:
2340 final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen);
2341 if (final_fall_delay.maxlen >= 12 && final_fall_delay.start < 4)
2342 final_maxlen = final_fall_delay.maxlen;
2343 if (final_maxlen == final_rise_delay.maxlen) {
2344 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2345 final_delay = final_rise_delay.final_phase;
2346 } else {
2347 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2348 final_delay = final_fall_delay.final_phase;
2349 }
2350 msdc_set_cmd_delay(host, final_delay);
2351
2352 if (host->dev_comp->async_fifo || host->hs200_cmd_int_delay)
2353 goto skip_internal;
2354
2355 for (i = 0; i < host->tuning_step; i++) {
2356 sdr_set_field(host->base + tune_reg,
2357 MSDC_PAD_TUNE_CMDRRDLY, i);
2358 mmc_send_tuning(mmc, opcode, &cmd_err);
2359 if (!cmd_err)
2360 internal_delay |= BIT_ULL(i);
2361 }
2362 dev_dbg(host->dev, "Final internal delay: 0x%x\n", internal_delay);
2363 internal_delay_phase = get_best_delay(host, internal_delay);
2364 sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_CMDRRDLY,
2365 internal_delay_phase.final_phase);
2366 skip_internal:
2367 dev_dbg(host->dev, "Final cmd pad delay: %x\n", final_delay);
2368 return final_delay == 0xff ? -EIO : 0;
2369 }
2370
hs400_tune_response(struct mmc_host * mmc,u32 opcode)2371 static int hs400_tune_response(struct mmc_host *mmc, u32 opcode)
2372 {
2373 struct msdc_host *host = mmc_priv(mmc);
2374 u32 cmd_delay = 0;
2375 struct msdc_delay_phase final_cmd_delay = { 0,};
2376 u8 final_delay;
2377 int cmd_err;
2378 int i, j;
2379
2380 /* select EMMC50 PAD CMD tune */
2381 sdr_set_bits(host->base + PAD_CMD_TUNE, BIT(0));
2382 sdr_set_field(host->base + MSDC_PATCH_BIT1, MSDC_PATCH_BIT1_CMDTA, 2);
2383
2384 if (mmc->ios.timing == MMC_TIMING_MMC_HS200 ||
2385 mmc->ios.timing == MMC_TIMING_UHS_SDR104)
2386 sdr_set_field(host->base + MSDC_PAD_TUNE,
2387 MSDC_PAD_TUNE_CMDRRDLY,
2388 host->hs200_cmd_int_delay);
2389
2390 if (host->hs400_cmd_resp_sel_rising)
2391 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2392 else
2393 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2394
2395 for (i = 0; i < PAD_DELAY_HALF; i++) {
2396 sdr_set_field(host->base + PAD_CMD_TUNE,
2397 PAD_CMD_TUNE_RX_DLY3, i);
2398 /*
2399 * Using the same parameters, it may sometimes pass the test,
2400 * but sometimes it may fail. To make sure the parameters are
2401 * more stable, we test each set of parameters 3 times.
2402 */
2403 for (j = 0; j < 3; j++) {
2404 mmc_send_tuning(mmc, opcode, &cmd_err);
2405 if (!cmd_err) {
2406 cmd_delay |= BIT(i);
2407 } else {
2408 cmd_delay &= ~BIT(i);
2409 break;
2410 }
2411 }
2412 }
2413 final_cmd_delay = get_best_delay(host, cmd_delay);
2414 sdr_set_field(host->base + PAD_CMD_TUNE, PAD_CMD_TUNE_RX_DLY3,
2415 final_cmd_delay.final_phase);
2416 final_delay = final_cmd_delay.final_phase;
2417
2418 dev_dbg(host->dev, "Final cmd pad delay: %x\n", final_delay);
2419 return final_delay == 0xff ? -EIO : 0;
2420 }
2421
msdc_tune_data(struct mmc_host * mmc,u32 opcode)2422 static int msdc_tune_data(struct mmc_host *mmc, u32 opcode)
2423 {
2424 struct msdc_host *host = mmc_priv(mmc);
2425 u64 rise_delay = 0, fall_delay = 0;
2426 struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0,};
2427 u8 final_delay, final_maxlen;
2428 int i, ret;
2429
2430 sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_INT_DAT_LATCH_CK_SEL,
2431 host->latch_ck);
2432 msdc_set_data_sample_edge(host, true);
2433 for (i = 0; i < host->tuning_step; i++) {
2434 msdc_set_data_delay(host, i);
2435 ret = mmc_send_tuning(mmc, opcode, NULL);
2436 if (!ret)
2437 rise_delay |= BIT_ULL(i);
2438 }
2439 final_rise_delay = get_best_delay(host, rise_delay);
2440 /* if rising edge has enough margin, then do not scan falling edge */
2441 if (final_rise_delay.maxlen >= 12 ||
2442 (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4))
2443 goto skip_fall;
2444
2445 msdc_set_data_sample_edge(host, false);
2446 for (i = 0; i < host->tuning_step; i++) {
2447 msdc_set_data_delay(host, i);
2448 ret = mmc_send_tuning(mmc, opcode, NULL);
2449 if (!ret)
2450 fall_delay |= BIT_ULL(i);
2451 }
2452 final_fall_delay = get_best_delay(host, fall_delay);
2453
2454 skip_fall:
2455 final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen);
2456 if (final_maxlen == final_rise_delay.maxlen) {
2457 msdc_set_data_sample_edge(host, true);
2458 final_delay = final_rise_delay.final_phase;
2459 } else {
2460 msdc_set_data_sample_edge(host, false);
2461 final_delay = final_fall_delay.final_phase;
2462 }
2463 msdc_set_data_delay(host, final_delay);
2464
2465 dev_dbg(host->dev, "Final data pad delay: %x\n", final_delay);
2466 return final_delay == 0xff ? -EIO : 0;
2467 }
2468
2469 /*
2470 * MSDC IP which supports data tune + async fifo can do CMD/DAT tune
2471 * together, which can save the tuning time.
2472 */
msdc_tune_together(struct mmc_host * mmc,u32 opcode)2473 static int msdc_tune_together(struct mmc_host *mmc, u32 opcode)
2474 {
2475 struct msdc_host *host = mmc_priv(mmc);
2476 u64 rise_delay = 0, fall_delay = 0;
2477 struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0,};
2478 u8 final_delay, final_maxlen;
2479 int i, ret;
2480
2481 sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_INT_DAT_LATCH_CK_SEL,
2482 host->latch_ck);
2483
2484 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2485 msdc_set_data_sample_edge(host, true);
2486 for (i = 0; i < host->tuning_step; i++) {
2487 msdc_set_cmd_delay(host, i);
2488 msdc_set_data_delay(host, i);
2489 ret = mmc_send_tuning(mmc, opcode, NULL);
2490 if (!ret)
2491 rise_delay |= BIT_ULL(i);
2492 }
2493 final_rise_delay = get_best_delay(host, rise_delay);
2494 /* if rising edge has enough margin, then do not scan falling edge */
2495 if (final_rise_delay.maxlen >= 12 ||
2496 (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4))
2497 goto skip_fall;
2498
2499 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2500 msdc_set_data_sample_edge(host, false);
2501 for (i = 0; i < host->tuning_step; i++) {
2502 msdc_set_cmd_delay(host, i);
2503 msdc_set_data_delay(host, i);
2504 ret = mmc_send_tuning(mmc, opcode, NULL);
2505 if (!ret)
2506 fall_delay |= BIT_ULL(i);
2507 }
2508 final_fall_delay = get_best_delay(host, fall_delay);
2509
2510 skip_fall:
2511 final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen);
2512 if (final_maxlen == final_rise_delay.maxlen) {
2513 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2514 msdc_set_data_sample_edge(host, true);
2515 final_delay = final_rise_delay.final_phase;
2516 } else {
2517 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2518 msdc_set_data_sample_edge(host, false);
2519 final_delay = final_fall_delay.final_phase;
2520 }
2521
2522 msdc_set_cmd_delay(host, final_delay);
2523 msdc_set_data_delay(host, final_delay);
2524
2525 dev_dbg(host->dev, "Final pad delay: %x\n", final_delay);
2526 return final_delay == 0xff ? -EIO : 0;
2527 }
2528
msdc_execute_tuning(struct mmc_host * mmc,u32 opcode)2529 static int msdc_execute_tuning(struct mmc_host *mmc, u32 opcode)
2530 {
2531 struct msdc_host *host = mmc_priv(mmc);
2532 int ret;
2533 u32 tune_reg = host->dev_comp->pad_tune_reg;
2534
2535 if (host->dev_comp->data_tune && host->dev_comp->async_fifo) {
2536 ret = msdc_tune_together(mmc, opcode);
2537 if (host->hs400_mode) {
2538 msdc_set_data_sample_edge(host, true);
2539 msdc_set_data_delay(host, 0);
2540 }
2541 goto tune_done;
2542 }
2543 if (host->hs400_mode &&
2544 host->dev_comp->hs400_tune)
2545 ret = hs400_tune_response(mmc, opcode);
2546 else
2547 ret = msdc_tune_response(mmc, opcode);
2548 if (ret == -EIO) {
2549 dev_err(host->dev, "Tune response fail!\n");
2550 return ret;
2551 }
2552 if (host->hs400_mode == false) {
2553 ret = msdc_tune_data(mmc, opcode);
2554 if (ret == -EIO)
2555 dev_err(host->dev, "Tune data fail!\n");
2556 }
2557
2558 tune_done:
2559 host->saved_tune_para.iocon = readl(host->base + MSDC_IOCON);
2560 host->saved_tune_para.pad_tune = readl(host->base + tune_reg);
2561 host->saved_tune_para.pad_cmd_tune = readl(host->base + PAD_CMD_TUNE);
2562 if (host->top_base) {
2563 host->saved_tune_para.emmc_top_control = readl(host->top_base +
2564 EMMC_TOP_CONTROL);
2565 host->saved_tune_para.emmc_top_cmd = readl(host->top_base +
2566 EMMC_TOP_CMD);
2567 }
2568 return ret;
2569 }
2570
msdc_prepare_hs400_tuning(struct mmc_host * mmc,struct mmc_ios * ios)2571 static int msdc_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios)
2572 {
2573 struct msdc_host *host = mmc_priv(mmc);
2574
2575 host->hs400_mode = true;
2576
2577 if (host->top_base) {
2578 if (host->hs400_ds_dly3)
2579 sdr_set_field(host->top_base + EMMC50_PAD_DS_TUNE,
2580 PAD_DS_DLY3, host->hs400_ds_dly3);
2581 if (host->hs400_ds_delay)
2582 writel(host->hs400_ds_delay,
2583 host->top_base + EMMC50_PAD_DS_TUNE);
2584 } else {
2585 if (host->hs400_ds_dly3)
2586 sdr_set_field(host->base + PAD_DS_TUNE,
2587 PAD_DS_TUNE_DLY3, host->hs400_ds_dly3);
2588 if (host->hs400_ds_delay)
2589 writel(host->hs400_ds_delay, host->base + PAD_DS_TUNE);
2590 }
2591 /* hs400 mode must set it to 0 */
2592 sdr_clr_bits(host->base + MSDC_PATCH_BIT2, MSDC_PATCH_BIT2_CFGCRCSTS);
2593 /* to improve read performance, set outstanding to 2 */
2594 sdr_set_field(host->base + EMMC50_CFG3, EMMC50_CFG3_OUTS_WR, 2);
2595
2596 return 0;
2597 }
2598
msdc_execute_hs400_tuning(struct mmc_host * mmc,struct mmc_card * card)2599 static int msdc_execute_hs400_tuning(struct mmc_host *mmc, struct mmc_card *card)
2600 {
2601 struct msdc_host *host = mmc_priv(mmc);
2602 struct msdc_delay_phase dly1_delay;
2603 u32 val, result_dly1 = 0;
2604 u8 *ext_csd;
2605 int i, ret;
2606
2607 if (host->top_base) {
2608 sdr_set_bits(host->top_base + EMMC50_PAD_DS_TUNE,
2609 PAD_DS_DLY_SEL);
2610 sdr_clr_bits(host->top_base + EMMC50_PAD_DS_TUNE,
2611 PAD_DS_DLY2_SEL);
2612 } else {
2613 sdr_set_bits(host->base + PAD_DS_TUNE, PAD_DS_TUNE_DLY_SEL);
2614 sdr_clr_bits(host->base + PAD_DS_TUNE, PAD_DS_TUNE_DLY2_SEL);
2615 }
2616
2617 host->hs400_tuning = true;
2618 for (i = 0; i < PAD_DELAY_HALF; i++) {
2619 if (host->top_base)
2620 sdr_set_field(host->top_base + EMMC50_PAD_DS_TUNE,
2621 PAD_DS_DLY1, i);
2622 else
2623 sdr_set_field(host->base + PAD_DS_TUNE,
2624 PAD_DS_TUNE_DLY1, i);
2625 ret = mmc_get_ext_csd(card, &ext_csd);
2626 if (!ret) {
2627 result_dly1 |= BIT(i);
2628 kfree(ext_csd);
2629 }
2630 }
2631 host->hs400_tuning = false;
2632
2633 dly1_delay = get_best_delay(host, result_dly1);
2634 if (dly1_delay.maxlen == 0) {
2635 dev_err(host->dev, "Failed to get DLY1 delay!\n");
2636 goto fail;
2637 }
2638 if (host->top_base)
2639 sdr_set_field(host->top_base + EMMC50_PAD_DS_TUNE,
2640 PAD_DS_DLY1, dly1_delay.final_phase);
2641 else
2642 sdr_set_field(host->base + PAD_DS_TUNE,
2643 PAD_DS_TUNE_DLY1, dly1_delay.final_phase);
2644
2645 if (host->top_base)
2646 val = readl(host->top_base + EMMC50_PAD_DS_TUNE);
2647 else
2648 val = readl(host->base + PAD_DS_TUNE);
2649
2650 dev_info(host->dev, "Final PAD_DS_TUNE: 0x%x\n", val);
2651
2652 return 0;
2653
2654 fail:
2655 dev_err(host->dev, "Failed to tuning DS pin delay!\n");
2656 return -EIO;
2657 }
2658
msdc_hw_reset(struct mmc_host * mmc)2659 static void msdc_hw_reset(struct mmc_host *mmc)
2660 {
2661 struct msdc_host *host = mmc_priv(mmc);
2662
2663 sdr_set_bits(host->base + EMMC_IOCON, 1);
2664 udelay(10); /* 10us is enough */
2665 sdr_clr_bits(host->base + EMMC_IOCON, 1);
2666 }
2667
msdc_ack_sdio_irq(struct mmc_host * mmc)2668 static void msdc_ack_sdio_irq(struct mmc_host *mmc)
2669 {
2670 unsigned long flags;
2671 struct msdc_host *host = mmc_priv(mmc);
2672
2673 spin_lock_irqsave(&host->lock, flags);
2674 __msdc_enable_sdio_irq(host, 1);
2675 spin_unlock_irqrestore(&host->lock, flags);
2676 }
2677
msdc_get_cd(struct mmc_host * mmc)2678 static int msdc_get_cd(struct mmc_host *mmc)
2679 {
2680 struct msdc_host *host = mmc_priv(mmc);
2681 int val;
2682
2683 if (mmc->caps & MMC_CAP_NONREMOVABLE)
2684 return 1;
2685
2686 if (!host->internal_cd)
2687 return mmc_gpio_get_cd(mmc);
2688
2689 val = readl(host->base + MSDC_PS) & MSDC_PS_CDSTS;
2690 if (mmc->caps2 & MMC_CAP2_CD_ACTIVE_HIGH)
2691 return !!val;
2692 else
2693 return !val;
2694 }
2695
msdc_hs400_enhanced_strobe(struct mmc_host * mmc,struct mmc_ios * ios)2696 static void msdc_hs400_enhanced_strobe(struct mmc_host *mmc,
2697 struct mmc_ios *ios)
2698 {
2699 struct msdc_host *host = mmc_priv(mmc);
2700
2701 if (ios->enhanced_strobe) {
2702 msdc_prepare_hs400_tuning(mmc, ios);
2703 sdr_set_field(host->base + EMMC50_CFG0, EMMC50_CFG_PADCMD_LATCHCK, 1);
2704 sdr_set_field(host->base + EMMC50_CFG0, EMMC50_CFG_CMD_RESP_SEL, 1);
2705 sdr_set_field(host->base + EMMC50_CFG1, EMMC50_CFG1_DS_CFG, 1);
2706
2707 sdr_clr_bits(host->base + CQHCI_SETTING, CQHCI_RD_CMD_WND_SEL);
2708 sdr_clr_bits(host->base + CQHCI_SETTING, CQHCI_WR_CMD_WND_SEL);
2709 sdr_clr_bits(host->base + EMMC51_CFG0, CMDQ_RDAT_CNT);
2710 } else {
2711 sdr_set_field(host->base + EMMC50_CFG0, EMMC50_CFG_PADCMD_LATCHCK, 0);
2712 sdr_set_field(host->base + EMMC50_CFG0, EMMC50_CFG_CMD_RESP_SEL, 0);
2713 sdr_set_field(host->base + EMMC50_CFG1, EMMC50_CFG1_DS_CFG, 0);
2714
2715 sdr_set_bits(host->base + CQHCI_SETTING, CQHCI_RD_CMD_WND_SEL);
2716 sdr_set_bits(host->base + CQHCI_SETTING, CQHCI_WR_CMD_WND_SEL);
2717 sdr_set_field(host->base + EMMC51_CFG0, CMDQ_RDAT_CNT, 0xb4);
2718 }
2719 }
2720
msdc_cqe_cit_cal(struct msdc_host * host,u64 timer_ns)2721 static void msdc_cqe_cit_cal(struct msdc_host *host, u64 timer_ns)
2722 {
2723 struct mmc_host *mmc = mmc_from_priv(host);
2724 struct cqhci_host *cq_host = mmc->cqe_private;
2725 u8 itcfmul;
2726 u64 hclk_freq, value;
2727
2728 /*
2729 * On MediaTek SoCs the MSDC controller's CQE uses msdc_hclk as ITCFVAL
2730 * so we multiply/divide the HCLK frequency by ITCFMUL to calculate the
2731 * Send Status Command Idle Timer (CIT) value.
2732 */
2733 hclk_freq = (u64)clk_get_rate(host->h_clk);
2734 itcfmul = CQHCI_ITCFMUL(cqhci_readl(cq_host, CQHCI_CAP));
2735 switch (itcfmul) {
2736 case 0x0:
2737 do_div(hclk_freq, 1000);
2738 break;
2739 case 0x1:
2740 do_div(hclk_freq, 100);
2741 break;
2742 case 0x2:
2743 do_div(hclk_freq, 10);
2744 break;
2745 case 0x3:
2746 break;
2747 case 0x4:
2748 hclk_freq = hclk_freq * 10;
2749 break;
2750 default:
2751 host->cq_ssc1_time = 0x40;
2752 return;
2753 }
2754
2755 value = hclk_freq * timer_ns;
2756 do_div(value, 1000000000);
2757 host->cq_ssc1_time = value;
2758 }
2759
msdc_cqe_enable(struct mmc_host * mmc)2760 static void msdc_cqe_enable(struct mmc_host *mmc)
2761 {
2762 struct msdc_host *host = mmc_priv(mmc);
2763 struct cqhci_host *cq_host = mmc->cqe_private;
2764
2765 /* enable cmdq irq */
2766 writel(MSDC_INT_CMDQ, host->base + MSDC_INTEN);
2767 /* enable busy check */
2768 sdr_set_bits(host->base + MSDC_PATCH_BIT1, MSDC_PB1_BUSY_CHECK_SEL);
2769 /* default write data / busy timeout 20s */
2770 msdc_set_busy_timeout(host, 20 * 1000000000ULL, 0);
2771 /* default read data timeout 1s */
2772 msdc_set_timeout(host, 1000000000ULL, 0);
2773
2774 /* Set the send status command idle timer */
2775 cqhci_writel(cq_host, host->cq_ssc1_time, CQHCI_SSC1);
2776 }
2777
msdc_cqe_disable(struct mmc_host * mmc,bool recovery)2778 static void msdc_cqe_disable(struct mmc_host *mmc, bool recovery)
2779 {
2780 struct msdc_host *host = mmc_priv(mmc);
2781 unsigned int val = 0;
2782
2783 /* disable cmdq irq */
2784 sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INT_CMDQ);
2785 /* disable busy check */
2786 sdr_clr_bits(host->base + MSDC_PATCH_BIT1, MSDC_PB1_BUSY_CHECK_SEL);
2787
2788 val = readl(host->base + MSDC_INT);
2789 writel(val, host->base + MSDC_INT);
2790
2791 if (recovery) {
2792 sdr_set_field(host->base + MSDC_DMA_CTRL,
2793 MSDC_DMA_CTRL_STOP, 1);
2794 if (WARN_ON(readl_poll_timeout(host->base + MSDC_DMA_CTRL, val,
2795 !(val & MSDC_DMA_CTRL_STOP), 1, 3000)))
2796 return;
2797 if (WARN_ON(readl_poll_timeout(host->base + MSDC_DMA_CFG, val,
2798 !(val & MSDC_DMA_CFG_STS), 1, 3000)))
2799 return;
2800 msdc_reset_hw(host);
2801 }
2802 }
2803
msdc_cqe_pre_enable(struct mmc_host * mmc)2804 static void msdc_cqe_pre_enable(struct mmc_host *mmc)
2805 {
2806 struct cqhci_host *cq_host = mmc->cqe_private;
2807 u32 reg;
2808
2809 reg = cqhci_readl(cq_host, CQHCI_CFG);
2810 reg |= CQHCI_ENABLE;
2811 cqhci_writel(cq_host, reg, CQHCI_CFG);
2812 }
2813
msdc_cqe_post_disable(struct mmc_host * mmc)2814 static void msdc_cqe_post_disable(struct mmc_host *mmc)
2815 {
2816 struct cqhci_host *cq_host = mmc->cqe_private;
2817 u32 reg;
2818
2819 reg = cqhci_readl(cq_host, CQHCI_CFG);
2820 reg &= ~CQHCI_ENABLE;
2821 cqhci_writel(cq_host, reg, CQHCI_CFG);
2822 }
2823
2824 static const struct mmc_host_ops mt_msdc_ops = {
2825 .post_req = msdc_post_req,
2826 .pre_req = msdc_pre_req,
2827 .request = msdc_ops_request,
2828 .set_ios = msdc_ops_set_ios,
2829 .get_ro = mmc_gpio_get_ro,
2830 .get_cd = msdc_get_cd,
2831 .hs400_enhanced_strobe = msdc_hs400_enhanced_strobe,
2832 .enable_sdio_irq = msdc_enable_sdio_irq,
2833 .ack_sdio_irq = msdc_ack_sdio_irq,
2834 .start_signal_voltage_switch = msdc_ops_switch_volt,
2835 .card_busy = msdc_card_busy,
2836 .execute_tuning = msdc_execute_tuning,
2837 .prepare_hs400_tuning = msdc_prepare_hs400_tuning,
2838 .execute_hs400_tuning = msdc_execute_hs400_tuning,
2839 .card_hw_reset = msdc_hw_reset,
2840 };
2841
2842 static const struct cqhci_host_ops msdc_cmdq_ops = {
2843 .enable = msdc_cqe_enable,
2844 .disable = msdc_cqe_disable,
2845 .pre_enable = msdc_cqe_pre_enable,
2846 .post_disable = msdc_cqe_post_disable,
2847 };
2848
msdc_of_property_parse(struct platform_device * pdev,struct msdc_host * host)2849 static void msdc_of_property_parse(struct platform_device *pdev,
2850 struct msdc_host *host)
2851 {
2852 struct mmc_host *mmc = mmc_from_priv(host);
2853
2854 of_property_read_u32(pdev->dev.of_node, "mediatek,latch-ck",
2855 &host->latch_ck);
2856
2857 of_property_read_u32(pdev->dev.of_node, "hs400-ds-delay",
2858 &host->hs400_ds_delay);
2859
2860 of_property_read_u32(pdev->dev.of_node, "mediatek,hs400-ds-dly3",
2861 &host->hs400_ds_dly3);
2862
2863 of_property_read_u32(pdev->dev.of_node, "mediatek,hs200-cmd-int-delay",
2864 &host->hs200_cmd_int_delay);
2865
2866 of_property_read_u32(pdev->dev.of_node, "mediatek,hs400-cmd-int-delay",
2867 &host->hs400_cmd_int_delay);
2868
2869 if (of_property_read_bool(pdev->dev.of_node,
2870 "mediatek,hs400-cmd-resp-sel-rising"))
2871 host->hs400_cmd_resp_sel_rising = true;
2872 else
2873 host->hs400_cmd_resp_sel_rising = false;
2874
2875 if (of_property_read_u32(pdev->dev.of_node, "mediatek,tuning-step",
2876 &host->tuning_step)) {
2877 if (mmc->caps2 & MMC_CAP2_NO_MMC)
2878 host->tuning_step = PAD_DELAY_FULL;
2879 else
2880 host->tuning_step = PAD_DELAY_HALF;
2881 }
2882
2883 if (of_property_read_bool(pdev->dev.of_node,
2884 "supports-cqe"))
2885 host->cqhci = true;
2886 else
2887 host->cqhci = false;
2888 }
2889
msdc_of_clock_parse(struct platform_device * pdev,struct msdc_host * host)2890 static int msdc_of_clock_parse(struct platform_device *pdev,
2891 struct msdc_host *host)
2892 {
2893 int ret;
2894
2895 host->src_clk = devm_clk_get(&pdev->dev, "source");
2896 if (IS_ERR(host->src_clk))
2897 return PTR_ERR(host->src_clk);
2898
2899 host->h_clk = devm_clk_get(&pdev->dev, "hclk");
2900 if (IS_ERR(host->h_clk))
2901 return PTR_ERR(host->h_clk);
2902
2903 host->bus_clk = devm_clk_get_optional(&pdev->dev, "bus_clk");
2904 if (IS_ERR(host->bus_clk))
2905 host->bus_clk = NULL;
2906
2907 /*source clock control gate is optional clock*/
2908 host->src_clk_cg = devm_clk_get_optional(&pdev->dev, "source_cg");
2909 if (IS_ERR(host->src_clk_cg))
2910 return PTR_ERR(host->src_clk_cg);
2911
2912 /*
2913 * Fallback for legacy device-trees: src_clk and HCLK use the same
2914 * bit to control gating but they are parented to a different mux,
2915 * hence if our intention is to gate only the source, required
2916 * during a clk mode switch to avoid hw hangs, we need to gate
2917 * its parent (specified as a different clock only on new DTs).
2918 */
2919 if (!host->src_clk_cg) {
2920 host->src_clk_cg = clk_get_parent(host->src_clk);
2921 if (IS_ERR(host->src_clk_cg))
2922 return PTR_ERR(host->src_clk_cg);
2923 }
2924
2925 /* If present, always enable for this clock gate */
2926 host->sys_clk_cg = devm_clk_get_optional_enabled(&pdev->dev, "sys_cg");
2927 if (IS_ERR(host->sys_clk_cg))
2928 host->sys_clk_cg = NULL;
2929
2930 host->bulk_clks[0].id = "pclk_cg";
2931 host->bulk_clks[1].id = "axi_cg";
2932 host->bulk_clks[2].id = "ahb_cg";
2933 ret = devm_clk_bulk_get_optional(&pdev->dev, MSDC_NR_CLOCKS,
2934 host->bulk_clks);
2935 if (ret) {
2936 dev_err(&pdev->dev, "Cannot get pclk/axi/ahb clock gates\n");
2937 return ret;
2938 }
2939
2940 return 0;
2941 }
2942
msdc_drv_probe(struct platform_device * pdev)2943 static int msdc_drv_probe(struct platform_device *pdev)
2944 {
2945 struct mmc_host *mmc;
2946 struct msdc_host *host;
2947 int ret;
2948
2949 if (!pdev->dev.of_node) {
2950 dev_err(&pdev->dev, "No DT found\n");
2951 return -EINVAL;
2952 }
2953
2954 /* Allocate MMC host for this device */
2955 mmc = devm_mmc_alloc_host(&pdev->dev, sizeof(struct msdc_host));
2956 if (!mmc)
2957 return -ENOMEM;
2958
2959 host = mmc_priv(mmc);
2960 ret = mmc_of_parse(mmc);
2961 if (ret)
2962 return ret;
2963
2964 host->base = devm_platform_ioremap_resource(pdev, 0);
2965 if (IS_ERR(host->base))
2966 return PTR_ERR(host->base);
2967
2968 host->dev_comp = of_device_get_match_data(&pdev->dev);
2969
2970 if (host->dev_comp->needs_top_base) {
2971 host->top_base = devm_platform_ioremap_resource(pdev, 1);
2972 if (IS_ERR(host->top_base))
2973 return PTR_ERR(host->top_base);
2974 }
2975
2976 ret = mmc_regulator_get_supply(mmc);
2977 if (ret)
2978 return ret;
2979
2980 ret = msdc_of_clock_parse(pdev, host);
2981 if (ret)
2982 return ret;
2983
2984 host->reset = devm_reset_control_get_optional_exclusive(&pdev->dev,
2985 "hrst");
2986 if (IS_ERR(host->reset))
2987 return PTR_ERR(host->reset);
2988
2989 /* only eMMC has crypto property */
2990 if (!(mmc->caps2 & MMC_CAP2_NO_MMC)) {
2991 host->crypto_clk = devm_clk_get_optional(&pdev->dev, "crypto");
2992 if (IS_ERR(host->crypto_clk))
2993 return PTR_ERR(host->crypto_clk);
2994 else if (host->crypto_clk)
2995 mmc->caps2 |= MMC_CAP2_CRYPTO;
2996 }
2997
2998 host->irq = platform_get_irq(pdev, 0);
2999 if (host->irq < 0)
3000 return host->irq;
3001
3002 host->pinctrl = devm_pinctrl_get(&pdev->dev);
3003 if (IS_ERR(host->pinctrl))
3004 return dev_err_probe(&pdev->dev, PTR_ERR(host->pinctrl),
3005 "Cannot find pinctrl");
3006
3007 host->pins_default = pinctrl_lookup_state(host->pinctrl, "default");
3008 if (IS_ERR(host->pins_default)) {
3009 dev_err(&pdev->dev, "Cannot find pinctrl default!\n");
3010 return PTR_ERR(host->pins_default);
3011 }
3012
3013 host->pins_uhs = pinctrl_lookup_state(host->pinctrl, "state_uhs");
3014 if (IS_ERR(host->pins_uhs)) {
3015 dev_err(&pdev->dev, "Cannot find pinctrl uhs!\n");
3016 return PTR_ERR(host->pins_uhs);
3017 }
3018
3019 /* Support for SDIO eint irq ? */
3020 if ((mmc->pm_caps & MMC_PM_WAKE_SDIO_IRQ) && (mmc->pm_caps & MMC_PM_KEEP_POWER)) {
3021 host->eint_irq = platform_get_irq_byname_optional(pdev, "sdio_wakeup");
3022 if (host->eint_irq > 0) {
3023 host->pins_eint = pinctrl_lookup_state(host->pinctrl, "state_eint");
3024 if (IS_ERR(host->pins_eint)) {
3025 dev_err(&pdev->dev, "Cannot find pinctrl eint!\n");
3026 host->pins_eint = NULL;
3027 } else {
3028 device_init_wakeup(&pdev->dev, true);
3029 }
3030 }
3031 }
3032
3033 msdc_of_property_parse(pdev, host);
3034
3035 host->dev = &pdev->dev;
3036 host->src_clk_freq = clk_get_rate(host->src_clk);
3037 /* Set host parameters to mmc */
3038 mmc->ops = &mt_msdc_ops;
3039 if (host->dev_comp->clk_div_bits == 8)
3040 mmc->f_min = DIV_ROUND_UP(host->src_clk_freq, 4 * 255);
3041 else
3042 mmc->f_min = DIV_ROUND_UP(host->src_clk_freq, 4 * 4095);
3043
3044 if (!(mmc->caps & MMC_CAP_NONREMOVABLE) &&
3045 !mmc_host_can_gpio_cd(mmc) &&
3046 host->dev_comp->use_internal_cd) {
3047 /*
3048 * Is removable but no GPIO declared, so
3049 * use internal functionality.
3050 */
3051 host->internal_cd = true;
3052 }
3053
3054 if (mmc->caps & MMC_CAP_SDIO_IRQ)
3055 mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD;
3056
3057 mmc->caps |= MMC_CAP_CMD23;
3058 if (host->cqhci)
3059 mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD;
3060 /* MMC core transfer sizes tunable parameters */
3061 mmc->max_segs = MAX_BD_NUM;
3062 if (host->dev_comp->support_64g)
3063 mmc->max_seg_size = BDMA_DESC_BUFLEN_EXT;
3064 else
3065 mmc->max_seg_size = BDMA_DESC_BUFLEN;
3066 mmc->max_blk_size = 2048;
3067 mmc->max_req_size = 512 * 1024;
3068 mmc->max_blk_count = mmc->max_req_size / 512;
3069 if (host->dev_comp->support_64g)
3070 host->dma_mask = DMA_BIT_MASK(36);
3071 else
3072 host->dma_mask = DMA_BIT_MASK(32);
3073 mmc_dev(mmc)->dma_mask = &host->dma_mask;
3074
3075 host->timeout_clks = 3 * 1048576;
3076 host->dma.gpd = dma_alloc_coherent(&pdev->dev,
3077 2 * sizeof(struct mt_gpdma_desc),
3078 &host->dma.gpd_addr, GFP_KERNEL);
3079 host->dma.bd = dma_alloc_coherent(&pdev->dev,
3080 MAX_BD_NUM * sizeof(struct mt_bdma_desc),
3081 &host->dma.bd_addr, GFP_KERNEL);
3082 if (!host->dma.gpd || !host->dma.bd) {
3083 ret = -ENOMEM;
3084 goto release_mem;
3085 }
3086 msdc_init_gpd_bd(host, &host->dma);
3087 INIT_DELAYED_WORK(&host->req_timeout, msdc_request_timeout);
3088 spin_lock_init(&host->lock);
3089
3090 platform_set_drvdata(pdev, mmc);
3091 ret = msdc_ungate_clock(host);
3092 if (ret) {
3093 dev_err(&pdev->dev, "Cannot ungate clocks!\n");
3094 goto release_clk;
3095 }
3096 msdc_init_hw(host);
3097
3098 if (mmc->caps2 & MMC_CAP2_CQE) {
3099 host->cq_host = devm_kzalloc(mmc->parent,
3100 sizeof(*host->cq_host),
3101 GFP_KERNEL);
3102 if (!host->cq_host) {
3103 ret = -ENOMEM;
3104 goto release;
3105 }
3106 host->cq_host->caps |= CQHCI_TASK_DESC_SZ_128;
3107 host->cq_host->mmio = host->base + 0x800;
3108 host->cq_host->ops = &msdc_cmdq_ops;
3109 ret = cqhci_init(host->cq_host, mmc, true);
3110 if (ret)
3111 goto release;
3112 mmc->max_segs = 128;
3113 /* cqhci 16bit length */
3114 /* 0 size, means 65536 so we don't have to -1 here */
3115 mmc->max_seg_size = 64 * 1024;
3116 /* Reduce CIT to 0x40 that corresponds to 2.35us */
3117 msdc_cqe_cit_cal(host, 2350);
3118 } else if (mmc->caps2 & MMC_CAP2_NO_SDIO) {
3119 /* Use HSQ on eMMC/SD (but not on SDIO) if HW CQE not supported */
3120 struct mmc_hsq *hsq = devm_kzalloc(&pdev->dev, sizeof(*hsq), GFP_KERNEL);
3121 if (!hsq) {
3122 ret = -ENOMEM;
3123 goto release;
3124 }
3125
3126 ret = mmc_hsq_init(hsq, mmc);
3127 if (ret)
3128 goto release;
3129
3130 host->hsq_en = true;
3131 }
3132
3133 ret = devm_request_irq(&pdev->dev, host->irq, msdc_irq,
3134 IRQF_TRIGGER_NONE, pdev->name, host);
3135 if (ret)
3136 goto release;
3137
3138 pm_runtime_set_active(host->dev);
3139 pm_runtime_set_autosuspend_delay(host->dev, MTK_MMC_AUTOSUSPEND_DELAY);
3140 pm_runtime_use_autosuspend(host->dev);
3141 pm_runtime_enable(host->dev);
3142 ret = mmc_add_host(mmc);
3143
3144 if (ret)
3145 goto end;
3146
3147 return 0;
3148 end:
3149 pm_runtime_disable(host->dev);
3150 release:
3151 msdc_deinit_hw(host);
3152 release_clk:
3153 msdc_gate_clock(host);
3154 platform_set_drvdata(pdev, NULL);
3155 release_mem:
3156 device_init_wakeup(&pdev->dev, false);
3157 if (host->dma.gpd)
3158 dma_free_coherent(&pdev->dev,
3159 2 * sizeof(struct mt_gpdma_desc),
3160 host->dma.gpd, host->dma.gpd_addr);
3161 if (host->dma.bd)
3162 dma_free_coherent(&pdev->dev,
3163 MAX_BD_NUM * sizeof(struct mt_bdma_desc),
3164 host->dma.bd, host->dma.bd_addr);
3165 return ret;
3166 }
3167
msdc_drv_remove(struct platform_device * pdev)3168 static void msdc_drv_remove(struct platform_device *pdev)
3169 {
3170 struct mmc_host *mmc;
3171 struct msdc_host *host;
3172
3173 mmc = platform_get_drvdata(pdev);
3174 host = mmc_priv(mmc);
3175
3176 pm_runtime_get_sync(host->dev);
3177
3178 platform_set_drvdata(pdev, NULL);
3179 mmc_remove_host(mmc);
3180 msdc_deinit_hw(host);
3181 msdc_gate_clock(host);
3182
3183 pm_runtime_disable(host->dev);
3184 pm_runtime_put_noidle(host->dev);
3185 dma_free_coherent(&pdev->dev,
3186 2 * sizeof(struct mt_gpdma_desc),
3187 host->dma.gpd, host->dma.gpd_addr);
3188 dma_free_coherent(&pdev->dev, MAX_BD_NUM * sizeof(struct mt_bdma_desc),
3189 host->dma.bd, host->dma.bd_addr);
3190 device_init_wakeup(&pdev->dev, false);
3191 }
3192
msdc_save_reg(struct msdc_host * host)3193 static void msdc_save_reg(struct msdc_host *host)
3194 {
3195 u32 tune_reg = host->dev_comp->pad_tune_reg;
3196
3197 host->save_para.msdc_cfg = readl(host->base + MSDC_CFG);
3198 host->save_para.iocon = readl(host->base + MSDC_IOCON);
3199 host->save_para.sdc_cfg = readl(host->base + SDC_CFG);
3200 host->save_para.patch_bit0 = readl(host->base + MSDC_PATCH_BIT);
3201 host->save_para.patch_bit1 = readl(host->base + MSDC_PATCH_BIT1);
3202 host->save_para.patch_bit2 = readl(host->base + MSDC_PATCH_BIT2);
3203 host->save_para.pad_ds_tune = readl(host->base + PAD_DS_TUNE);
3204 host->save_para.pad_cmd_tune = readl(host->base + PAD_CMD_TUNE);
3205 host->save_para.emmc50_cfg0 = readl(host->base + EMMC50_CFG0);
3206 host->save_para.emmc50_cfg3 = readl(host->base + EMMC50_CFG3);
3207 host->save_para.sdc_fifo_cfg = readl(host->base + SDC_FIFO_CFG);
3208 if (host->top_base) {
3209 host->save_para.emmc_top_control =
3210 readl(host->top_base + EMMC_TOP_CONTROL);
3211 host->save_para.emmc_top_cmd =
3212 readl(host->top_base + EMMC_TOP_CMD);
3213 host->save_para.emmc50_pad_ds_tune =
3214 readl(host->top_base + EMMC50_PAD_DS_TUNE);
3215 host->save_para.loop_test_control =
3216 readl(host->top_base + LOOP_TEST_CONTROL);
3217 } else {
3218 host->save_para.pad_tune = readl(host->base + tune_reg);
3219 }
3220 }
3221
msdc_restore_reg(struct msdc_host * host)3222 static void msdc_restore_reg(struct msdc_host *host)
3223 {
3224 struct mmc_host *mmc = mmc_from_priv(host);
3225 u32 tune_reg = host->dev_comp->pad_tune_reg;
3226
3227 if (host->dev_comp->support_new_tx) {
3228 sdr_clr_bits(host->base + SDC_ADV_CFG0, SDC_NEW_TX_EN);
3229 sdr_set_bits(host->base + SDC_ADV_CFG0, SDC_NEW_TX_EN);
3230 }
3231 if (host->dev_comp->support_new_rx) {
3232 sdr_clr_bits(host->base + MSDC_NEW_RX_CFG, MSDC_NEW_RX_PATH_SEL);
3233 sdr_set_bits(host->base + MSDC_NEW_RX_CFG, MSDC_NEW_RX_PATH_SEL);
3234 }
3235
3236 writel(host->save_para.msdc_cfg, host->base + MSDC_CFG);
3237 writel(host->save_para.iocon, host->base + MSDC_IOCON);
3238 writel(host->save_para.sdc_cfg, host->base + SDC_CFG);
3239 writel(host->save_para.patch_bit0, host->base + MSDC_PATCH_BIT);
3240 writel(host->save_para.patch_bit1, host->base + MSDC_PATCH_BIT1);
3241 writel(host->save_para.patch_bit2, host->base + MSDC_PATCH_BIT2);
3242 writel(host->save_para.pad_ds_tune, host->base + PAD_DS_TUNE);
3243 writel(host->save_para.pad_cmd_tune, host->base + PAD_CMD_TUNE);
3244 writel(host->save_para.emmc50_cfg0, host->base + EMMC50_CFG0);
3245 writel(host->save_para.emmc50_cfg3, host->base + EMMC50_CFG3);
3246 writel(host->save_para.sdc_fifo_cfg, host->base + SDC_FIFO_CFG);
3247 if (host->top_base) {
3248 writel(host->save_para.emmc_top_control,
3249 host->top_base + EMMC_TOP_CONTROL);
3250 writel(host->save_para.emmc_top_cmd,
3251 host->top_base + EMMC_TOP_CMD);
3252 writel(host->save_para.emmc50_pad_ds_tune,
3253 host->top_base + EMMC50_PAD_DS_TUNE);
3254 writel(host->save_para.loop_test_control,
3255 host->top_base + LOOP_TEST_CONTROL);
3256 } else {
3257 writel(host->save_para.pad_tune, host->base + tune_reg);
3258 }
3259
3260 if (sdio_irq_claimed(mmc))
3261 __msdc_enable_sdio_irq(host, 1);
3262 }
3263
msdc_runtime_suspend(struct device * dev)3264 static int __maybe_unused msdc_runtime_suspend(struct device *dev)
3265 {
3266 struct mmc_host *mmc = dev_get_drvdata(dev);
3267 struct msdc_host *host = mmc_priv(mmc);
3268
3269 if (host->hsq_en)
3270 mmc_hsq_suspend(mmc);
3271
3272 msdc_save_reg(host);
3273
3274 if (sdio_irq_claimed(mmc)) {
3275 if (host->pins_eint) {
3276 disable_irq(host->irq);
3277 pinctrl_select_state(host->pinctrl, host->pins_eint);
3278 }
3279
3280 __msdc_enable_sdio_irq(host, 0);
3281 }
3282 msdc_gate_clock(host);
3283 return 0;
3284 }
3285
msdc_runtime_resume(struct device * dev)3286 static int __maybe_unused msdc_runtime_resume(struct device *dev)
3287 {
3288 struct mmc_host *mmc = dev_get_drvdata(dev);
3289 struct msdc_host *host = mmc_priv(mmc);
3290 int ret;
3291
3292 ret = msdc_ungate_clock(host);
3293 if (ret)
3294 return ret;
3295
3296 msdc_restore_reg(host);
3297
3298 if (sdio_irq_claimed(mmc) && host->pins_eint) {
3299 pinctrl_select_state(host->pinctrl, host->pins_uhs);
3300 enable_irq(host->irq);
3301 }
3302
3303 if (host->hsq_en)
3304 mmc_hsq_resume(mmc);
3305
3306 return 0;
3307 }
3308
msdc_suspend(struct device * dev)3309 static int __maybe_unused msdc_suspend(struct device *dev)
3310 {
3311 struct mmc_host *mmc = dev_get_drvdata(dev);
3312 struct msdc_host *host = mmc_priv(mmc);
3313 int ret;
3314 u32 val;
3315
3316 if (mmc->caps2 & MMC_CAP2_CQE) {
3317 ret = cqhci_suspend(mmc);
3318 if (ret)
3319 return ret;
3320 val = readl(host->base + MSDC_INT);
3321 writel(val, host->base + MSDC_INT);
3322 }
3323
3324 /*
3325 * Bump up runtime PM usage counter otherwise dev->power.needs_force_resume will
3326 * not be marked as 1, pm_runtime_force_resume() will go out directly.
3327 */
3328 if (sdio_irq_claimed(mmc) && host->pins_eint)
3329 pm_runtime_get_noresume(dev);
3330
3331 return pm_runtime_force_suspend(dev);
3332 }
3333
msdc_resume(struct device * dev)3334 static int __maybe_unused msdc_resume(struct device *dev)
3335 {
3336 struct mmc_host *mmc = dev_get_drvdata(dev);
3337 struct msdc_host *host = mmc_priv(mmc);
3338
3339 if (sdio_irq_claimed(mmc) && host->pins_eint)
3340 pm_runtime_put_noidle(dev);
3341
3342 return pm_runtime_force_resume(dev);
3343 }
3344
3345 static const struct dev_pm_ops msdc_dev_pm_ops = {
3346 SET_SYSTEM_SLEEP_PM_OPS(msdc_suspend, msdc_resume)
3347 SET_RUNTIME_PM_OPS(msdc_runtime_suspend, msdc_runtime_resume, NULL)
3348 };
3349
3350 static struct platform_driver mt_msdc_driver = {
3351 .probe = msdc_drv_probe,
3352 .remove = msdc_drv_remove,
3353 .driver = {
3354 .name = "mtk-msdc",
3355 .probe_type = PROBE_PREFER_ASYNCHRONOUS,
3356 .of_match_table = msdc_of_ids,
3357 .pm = &msdc_dev_pm_ops,
3358 },
3359 };
3360
3361 module_platform_driver(mt_msdc_driver);
3362 MODULE_LICENSE("GPL v2");
3363 MODULE_DESCRIPTION("MediaTek SD/MMC Card Driver");
3364