1 /*-
2 * SPDX-License-Identifier: BSD-4-Clause
3 *
4 * Copyright (c) 1991 Regents of the University of California.
5 * All rights reserved.
6 * Copyright (c) 1994 John S. Dyson
7 * All rights reserved.
8 * Copyright (c) 1994 David Greenman
9 * All rights reserved.
10 * Copyright (c) 2005-2010 Alan L. Cox <alc@cs.rice.edu>
11 * All rights reserved.
12 *
13 * This code is derived from software contributed to Berkeley by
14 * the Systems Programming Group of the University of Utah Computer
15 * Science Department and William Jolitz of UUNET Technologies Inc.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions
19 * are met:
20 * 1. Redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer.
22 * 2. Redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution.
25 * 3. All advertising materials mentioning features or use of this software
26 * must display the following acknowledgement:
27 * This product includes software developed by the University of
28 * California, Berkeley and its contributors.
29 * 4. Neither the name of the University nor the names of its contributors
30 * may be used to endorse or promote products derived from this software
31 * without specific prior written permission.
32 *
33 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
34 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
35 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
36 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
37 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
38 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
39 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
40 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
41 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
42 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
43 * SUCH DAMAGE.
44 */
45 /*-
46 * Copyright (c) 2003 Networks Associates Technology, Inc.
47 * All rights reserved.
48 * Copyright (c) 2018 The FreeBSD Foundation
49 * All rights reserved.
50 *
51 * This software was developed for the FreeBSD Project by Jake Burkholder,
52 * Safeport Network Services, and Network Associates Laboratories, the
53 * Security Research Division of Network Associates, Inc. under
54 * DARPA/SPAWAR contract N66001-01-C-8035 ("CBOSS"), as part of the DARPA
55 * CHATS research program.
56 *
57 * Portions of this software were developed by
58 * Konstantin Belousov <kib@FreeBSD.org> under sponsorship from
59 * the FreeBSD Foundation.
60 *
61 * Redistribution and use in source and binary forms, with or without
62 * modification, are permitted provided that the following conditions
63 * are met:
64 * 1. Redistributions of source code must retain the above copyright
65 * notice, this list of conditions and the following disclaimer.
66 * 2. Redistributions in binary form must reproduce the above copyright
67 * notice, this list of conditions and the following disclaimer in the
68 * documentation and/or other materials provided with the distribution.
69 *
70 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
71 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
72 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
73 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
74 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
75 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
76 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
77 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
78 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
79 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
80 * SUCH DAMAGE.
81 */
82
83 #include <sys/cdefs.h>
84 /*
85 * Manages physical address maps.
86 *
87 * Since the information managed by this module is
88 * also stored by the logical address mapping module,
89 * this module may throw away valid virtual-to-physical
90 * mappings at almost any time. However, invalidations
91 * of virtual-to-physical mappings must be done as
92 * requested.
93 *
94 * In order to cope with hardware architectures which
95 * make virtual-to-physical map invalidates expensive,
96 * this module may delay invalidate or reduced protection
97 * operations until such time as they are actually
98 * necessary. This module is given full information as
99 * to which processors are currently using which maps,
100 * and to when physical maps must be made correct.
101 */
102
103 #include "opt_apic.h"
104 #include "opt_cpu.h"
105 #include "opt_pmap.h"
106 #include "opt_smp.h"
107 #include "opt_vm.h"
108
109 #include <sys/param.h>
110 #include <sys/systm.h>
111 #include <sys/kernel.h>
112 #include <sys/ktr.h>
113 #include <sys/lock.h>
114 #include <sys/malloc.h>
115 #include <sys/mman.h>
116 #include <sys/msgbuf.h>
117 #include <sys/mutex.h>
118 #include <sys/proc.h>
119 #include <sys/rwlock.h>
120 #include <sys/sbuf.h>
121 #include <sys/sf_buf.h>
122 #include <sys/sx.h>
123 #include <sys/vmmeter.h>
124 #include <sys/sched.h>
125 #include <sys/sysctl.h>
126 #include <sys/smp.h>
127 #include <sys/vmem.h>
128
129 #include <vm/vm.h>
130 #include <vm/vm_param.h>
131 #include <vm/vm_kern.h>
132 #include <vm/vm_page.h>
133 #include <vm/vm_map.h>
134 #include <vm/vm_object.h>
135 #include <vm/vm_extern.h>
136 #include <vm/vm_pageout.h>
137 #include <vm/vm_pager.h>
138 #include <vm/vm_phys.h>
139 #include <vm/vm_radix.h>
140 #include <vm/vm_reserv.h>
141 #include <vm/uma.h>
142
143 #ifdef DEV_APIC
144 #include <sys/bus.h>
145 #include <machine/intr_machdep.h>
146 #include <x86/apicvar.h>
147 #endif
148 #include <x86/ifunc.h>
149 #include <machine/bootinfo.h>
150 #include <machine/cpu.h>
151 #include <machine/cputypes.h>
152 #include <machine/md_var.h>
153 #include <machine/pcb.h>
154 #include <machine/specialreg.h>
155 #ifdef SMP
156 #include <machine/smp.h>
157 #endif
158 #include <machine/pmap_base.h>
159
160 #ifdef PV_STATS
161 #define PV_STAT(x) do { x ; } while (0)
162 #else
163 #define PV_STAT(x) do { } while (0)
164 #endif
165
166 #define pa_index(pa) ((pa) >> PDRSHIFT)
167 #define pa_to_pvh(pa) (&pv_table[pa_index(pa)])
168
169 /*
170 * PTmap is recursive pagemap at top of virtual address space.
171 * Within PTmap, the page directory can be found (third indirection).
172 */
173 #define PTmap ((pt_entry_t *)(PTDPTDI << PDRSHIFT))
174 #define PTD ((pd_entry_t *)((PTDPTDI << PDRSHIFT) + (PTDPTDI * PAGE_SIZE)))
175 #define PTDpde ((pd_entry_t *)((PTDPTDI << PDRSHIFT) + (PTDPTDI * PAGE_SIZE) + \
176 (PTDPTDI * PDESIZE)))
177
178 /*
179 * Translate a virtual address to the kernel virtual address of its page table
180 * entry (PTE). This can be used recursively. If the address of a PTE as
181 * previously returned by this macro is itself given as the argument, then the
182 * address of the page directory entry (PDE) that maps the PTE will be
183 * returned.
184 *
185 * This macro may be used before pmap_bootstrap() is called.
186 */
187 #define vtopte(va) (PTmap + i386_btop(va))
188
189 /*
190 * Get PDEs and PTEs for user/kernel address space
191 */
192 #define pmap_pde(m, v) (&((m)->pm_pdir[(vm_offset_t)(v) >> PDRSHIFT]))
193 #define pdir_pde(m, v) (m[(vm_offset_t)(v) >> PDRSHIFT])
194
195 #define pmap_pde_v(pte) ((*(int *)pte & PG_V) != 0)
196 #define pmap_pte_w(pte) ((*(int *)pte & PG_W) != 0)
197 #define pmap_pte_m(pte) ((*(int *)pte & PG_M) != 0)
198 #define pmap_pte_u(pte) ((*(int *)pte & PG_A) != 0)
199 #define pmap_pte_v(pte) ((*(int *)pte & PG_V) != 0)
200
201 #define pmap_pte_set_w(pte, v) ((v) ? atomic_set_int((u_int *)(pte), PG_W) : \
202 atomic_clear_int((u_int *)(pte), PG_W))
203 #define pmap_pte_set_prot(pte, v) ((*(int *)pte &= ~PG_PROT), (*(int *)pte |= (v)))
204
205 static int pgeflag = 0; /* PG_G or-in */
206 static int pseflag = 0; /* PG_PS or-in */
207
208 static int nkpt = NKPT;
209
210 #ifdef PMAP_PAE_COMP
211 pt_entry_t pg_nx;
212 static uma_zone_t pdptzone;
213 #else
214 #define pg_nx 0
215 #endif
216
217 _Static_assert(VM_MAXUSER_ADDRESS == VADDR(TRPTDI, 0), "VM_MAXUSER_ADDRESS");
218 _Static_assert(VM_MAX_KERNEL_ADDRESS <= VADDR(PTDPTDI, 0),
219 "VM_MAX_KERNEL_ADDRESS");
220 _Static_assert(PMAP_MAP_LOW == VADDR(LOWPTDI, 0), "PMAP_MAP_LOW");
221 _Static_assert(KERNLOAD == (KERNPTDI << PDRSHIFT), "KERNLOAD");
222
223 extern int pat_works;
224 extern int pg_ps_enabled;
225
226 extern int elf32_nxstack;
227
228 #define PAT_INDEX_SIZE 8
229 static int pat_index[PAT_INDEX_SIZE]; /* cache mode to PAT index conversion */
230
231 /*
232 * pmap_mapdev support pre initialization (i.e. console)
233 */
234 #define PMAP_PREINIT_MAPPING_COUNT 8
235 static struct pmap_preinit_mapping {
236 vm_paddr_t pa;
237 vm_offset_t va;
238 vm_size_t sz;
239 int mode;
240 } pmap_preinit_mapping[PMAP_PREINIT_MAPPING_COUNT];
241 static int pmap_initialized;
242
243 static struct rwlock_padalign pvh_global_lock;
244
245 /*
246 * Data for the pv entry allocation mechanism
247 */
248 static TAILQ_HEAD(pch, pv_chunk) pv_chunks = TAILQ_HEAD_INITIALIZER(pv_chunks);
249 extern int pv_entry_max, pv_entry_count;
250 static int pv_entry_high_water = 0;
251 static struct md_page *pv_table;
252 extern int shpgperproc;
253
254 static struct pv_chunk *pv_chunkbase; /* KVA block for pv_chunks */
255 static int pv_maxchunks; /* How many chunks we have KVA for */
256 static vm_offset_t pv_vafree; /* freelist stored in the PTE */
257
258 /*
259 * All those kernel PT submaps that BSD is so fond of
260 */
261 static pt_entry_t *CMAP3;
262 static pd_entry_t *KPTD;
263 static caddr_t CADDR3;
264
265 /*
266 * Crashdump maps.
267 */
268 static caddr_t crashdumpmap;
269
270 static pt_entry_t *PMAP1 = NULL, *PMAP2, *PMAP3;
271 static pt_entry_t *PADDR1 = NULL, *PADDR2, *PADDR3;
272 #ifdef SMP
273 static int PMAP1cpu, PMAP3cpu;
274 extern int PMAP1changedcpu;
275 #endif
276 extern int PMAP1changed;
277 extern int PMAP1unchanged;
278 static struct mtx PMAP2mutex;
279
280 /*
281 * Internal flags for pmap_enter()'s helper functions.
282 */
283 #define PMAP_ENTER_NORECLAIM 0x1000000 /* Don't reclaim PV entries. */
284 #define PMAP_ENTER_NOREPLACE 0x2000000 /* Don't replace mappings. */
285
286 static void free_pv_chunk(struct pv_chunk *pc);
287 static void free_pv_entry(pmap_t pmap, pv_entry_t pv);
288 static pv_entry_t get_pv_entry(pmap_t pmap, bool try);
289 static void pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa);
290 static bool pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, pd_entry_t pde,
291 u_int flags);
292 #if VM_NRESERVLEVEL > 0
293 static void pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa);
294 #endif
295 static void pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va);
296 static pv_entry_t pmap_pvh_remove(struct md_page *pvh, pmap_t pmap,
297 vm_offset_t va);
298 static int pmap_pvh_wired_mappings(struct md_page *pvh, int count);
299
300 static void pmap_abort_ptp(pmap_t pmap, vm_offset_t va, vm_page_t mpte);
301 static bool pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va);
302 static int pmap_enter_4mpage(pmap_t pmap, vm_offset_t va, vm_page_t m,
303 vm_prot_t prot);
304 static int pmap_enter_pde(pmap_t pmap, vm_offset_t va, pd_entry_t newpde,
305 u_int flags, vm_page_t m);
306 static vm_page_t pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va,
307 vm_page_t m, vm_prot_t prot, vm_page_t mpte);
308 static int pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte, bool promoted,
309 bool allpte_PG_A_set);
310 static void pmap_invalidate_pde_page(pmap_t pmap, vm_offset_t va,
311 pd_entry_t pde);
312 static void pmap_fill_ptp(pt_entry_t *firstpte, pt_entry_t newpte);
313 static bool pmap_is_modified_pvh(struct md_page *pvh);
314 static bool pmap_is_referenced_pvh(struct md_page *pvh);
315 static void pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode);
316 static void pmap_kenter_pde(vm_offset_t va, pd_entry_t newpde);
317 static void pmap_pde_attr(pd_entry_t *pde, int cache_bits);
318 #if VM_NRESERVLEVEL > 0
319 static bool pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va,
320 vm_page_t mpte);
321 #endif
322 static bool pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva,
323 vm_prot_t prot);
324 static void pmap_pte_attr(pt_entry_t *pte, int cache_bits);
325 static void pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva,
326 struct spglist *free);
327 static int pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t sva,
328 struct spglist *free);
329 static vm_page_t pmap_remove_pt_page(pmap_t pmap, vm_offset_t va);
330 static void pmap_remove_page(pmap_t pmap, vm_offset_t va, struct spglist *free);
331 static bool pmap_remove_ptes(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
332 struct spglist *free);
333 static void pmap_remove_entry(pmap_t pmap, vm_page_t m, vm_offset_t va);
334 static void pmap_insert_entry(pmap_t pmap, vm_offset_t va, vm_page_t m);
335 static bool pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va,
336 vm_page_t m);
337 static void pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde,
338 pd_entry_t newpde);
339 static void pmap_update_pde_invalidate(vm_offset_t va, pd_entry_t newpde);
340
341 static vm_page_t pmap_allocpte(pmap_t pmap, vm_offset_t va, u_int flags);
342
343 static vm_page_t _pmap_allocpte(pmap_t pmap, u_int ptepindex, u_int flags);
344 static void _pmap_unwire_ptp(pmap_t pmap, vm_page_t m, struct spglist *free);
345 static pt_entry_t *pmap_pte_quick(pmap_t pmap, vm_offset_t va);
346 static void pmap_pte_release(pt_entry_t *pte);
347 static int pmap_unuse_pt(pmap_t, vm_offset_t, struct spglist *);
348 #ifdef PMAP_PAE_COMP
349 static void *pmap_pdpt_allocf(uma_zone_t zone, vm_size_t bytes, int domain,
350 uint8_t *flags, int wait);
351 #endif
352 static void pmap_init_trm(void);
353 static void pmap_invalidate_all_int(pmap_t pmap);
354
355 static __inline void pagezero(void *page);
356
357 CTASSERT(1 << PDESHIFT == sizeof(pd_entry_t));
358 CTASSERT(1 << PTESHIFT == sizeof(pt_entry_t));
359
360 extern char _end[];
361 extern u_long physfree; /* phys addr of next free page */
362 extern u_long vm86phystk;/* PA of vm86/bios stack */
363 extern u_long vm86paddr;/* address of vm86 region */
364 extern int vm86pa; /* phys addr of vm86 region */
365 extern u_long KERNend; /* phys addr end of kernel (just after bss) */
366 #ifdef PMAP_PAE_COMP
367 pd_entry_t *IdlePTD_pae; /* phys addr of kernel PTD */
368 pdpt_entry_t *IdlePDPT; /* phys addr of kernel PDPT */
369 pt_entry_t *KPTmap_pae; /* address of kernel page tables */
370 #define IdlePTD IdlePTD_pae
371 #define KPTmap KPTmap_pae
372 #else
373 pd_entry_t *IdlePTD_nopae;
374 pt_entry_t *KPTmap_nopae;
375 #define IdlePTD IdlePTD_nopae
376 #define KPTmap KPTmap_nopae
377 #endif
378 extern u_long KPTphys; /* phys addr of kernel page tables */
379 extern u_long tramp_idleptd;
380
381 static u_long
allocpages(u_int cnt,u_long * physfree)382 allocpages(u_int cnt, u_long *physfree)
383 {
384 u_long res;
385
386 res = *physfree;
387 *physfree += PAGE_SIZE * cnt;
388 bzero((void *)res, PAGE_SIZE * cnt);
389 return (res);
390 }
391
392 static void
pmap_cold_map(u_long pa,u_long va,u_long cnt)393 pmap_cold_map(u_long pa, u_long va, u_long cnt)
394 {
395 pt_entry_t *pt;
396
397 for (pt = (pt_entry_t *)KPTphys + atop(va); cnt > 0;
398 cnt--, pt++, va += PAGE_SIZE, pa += PAGE_SIZE)
399 *pt = pa | PG_V | PG_RW | PG_A | PG_M;
400 }
401
402 static void
pmap_cold_mapident(u_long pa,u_long cnt)403 pmap_cold_mapident(u_long pa, u_long cnt)
404 {
405
406 pmap_cold_map(pa, pa, cnt);
407 }
408
409 _Static_assert(LOWPTDI * 2 * NBPDR == KERNBASE,
410 "Broken double-map of zero PTD");
411
412 static void
__CONCAT(PMTYPE,remap_lower)413 __CONCAT(PMTYPE, remap_lower)(bool enable)
414 {
415 int i;
416
417 for (i = 0; i < LOWPTDI; i++)
418 IdlePTD[i] = enable ? IdlePTD[LOWPTDI + i] : 0;
419 load_cr3(rcr3()); /* invalidate TLB */
420 }
421
422 /*
423 * Called from locore.s before paging is enabled. Sets up the first
424 * kernel page table. Since kernel is mapped with PA == VA, this code
425 * does not require relocations.
426 */
427 void
__CONCAT(PMTYPE,cold)428 __CONCAT(PMTYPE, cold)(void)
429 {
430 pt_entry_t *pt;
431 u_long a;
432 u_int cr3, ncr4;
433
434 physfree = (u_long)&_end;
435 if (bootinfo.bi_esymtab != 0)
436 physfree = bootinfo.bi_esymtab;
437 if (bootinfo.bi_kernend != 0)
438 physfree = bootinfo.bi_kernend;
439 physfree = roundup2(physfree, NBPDR);
440 KERNend = physfree;
441
442 /* Allocate Kernel Page Tables */
443 KPTphys = allocpages(NKPT, &physfree);
444 KPTmap = (pt_entry_t *)KPTphys;
445
446 /* Allocate Page Table Directory */
447 #ifdef PMAP_PAE_COMP
448 /* XXX only need 32 bytes (easier for now) */
449 IdlePDPT = (pdpt_entry_t *)allocpages(1, &physfree);
450 #endif
451 IdlePTD = (pd_entry_t *)allocpages(NPGPTD, &physfree);
452
453 /*
454 * Allocate KSTACK. Leave a guard page between IdlePTD and
455 * proc0kstack, to control stack overflow for thread0 and
456 * prevent corruption of the page table. We leak the guard
457 * physical memory due to 1:1 mappings.
458 */
459 allocpages(1, &physfree);
460 proc0kstack = allocpages(TD0_KSTACK_PAGES, &physfree);
461
462 /* vm86/bios stack */
463 vm86phystk = allocpages(1, &physfree);
464
465 /* pgtable + ext + IOPAGES */
466 vm86paddr = vm86pa = allocpages(3, &physfree);
467
468 /* Install page tables into PTD. Page table page 1 is wasted. */
469 for (a = 0; a < NKPT; a++)
470 IdlePTD[a] = (KPTphys + ptoa(a)) | PG_V | PG_RW | PG_A | PG_M;
471
472 #ifdef PMAP_PAE_COMP
473 /* PAE install PTD pointers into PDPT */
474 for (a = 0; a < NPGPTD; a++)
475 IdlePDPT[a] = ((u_int)IdlePTD + ptoa(a)) | PG_V;
476 #endif
477
478 /*
479 * Install recursive mapping for kernel page tables into
480 * itself.
481 */
482 for (a = 0; a < NPGPTD; a++)
483 IdlePTD[PTDPTDI + a] = ((u_int)IdlePTD + ptoa(a)) | PG_V |
484 PG_RW;
485
486 /*
487 * Initialize page table pages mapping physical address zero
488 * through the (physical) end of the kernel. Many of these
489 * pages must be reserved, and we reserve them all and map
490 * them linearly for convenience. We do this even if we've
491 * enabled PSE above; we'll just switch the corresponding
492 * kernel PDEs before we turn on paging.
493 *
494 * This and all other page table entries allow read and write
495 * access for various reasons. Kernel mappings never have any
496 * access restrictions.
497 */
498 pmap_cold_mapident(0, atop(NBPDR) * LOWPTDI);
499 pmap_cold_map(0, NBPDR * LOWPTDI, atop(NBPDR) * LOWPTDI);
500 pmap_cold_mapident(KERNBASE, atop(KERNend - KERNBASE));
501
502 /* Map page table directory */
503 #ifdef PMAP_PAE_COMP
504 pmap_cold_mapident((u_long)IdlePDPT, 1);
505 #endif
506 pmap_cold_mapident((u_long)IdlePTD, NPGPTD);
507
508 /* Map early KPTmap. It is really pmap_cold_mapident. */
509 pmap_cold_map(KPTphys, (u_long)KPTmap, NKPT);
510
511 /* Map proc0kstack */
512 pmap_cold_mapident(proc0kstack, TD0_KSTACK_PAGES);
513 /* ISA hole already mapped */
514
515 pmap_cold_mapident(vm86phystk, 1);
516 pmap_cold_mapident(vm86pa, 3);
517
518 /* Map page 0 into the vm86 page table */
519 *(pt_entry_t *)vm86pa = 0 | PG_RW | PG_U | PG_A | PG_M | PG_V;
520
521 /* ...likewise for the ISA hole for vm86 */
522 for (pt = (pt_entry_t *)vm86pa + atop(ISA_HOLE_START), a = 0;
523 a < atop(ISA_HOLE_LENGTH); a++, pt++)
524 *pt = (ISA_HOLE_START + ptoa(a)) | PG_RW | PG_U | PG_A |
525 PG_M | PG_V;
526
527 /* Enable PSE, PGE, VME, and PAE if configured. */
528 ncr4 = 0;
529 if ((cpu_feature & CPUID_PSE) != 0) {
530 ncr4 |= CR4_PSE;
531 pseflag = PG_PS;
532 /*
533 * Superpage mapping of the kernel text. Existing 4k
534 * page table pages are wasted.
535 */
536 for (a = KERNBASE; a < KERNend; a += NBPDR)
537 IdlePTD[a >> PDRSHIFT] = a | PG_PS | PG_A | PG_M |
538 PG_RW | PG_V;
539 }
540 if ((cpu_feature & CPUID_PGE) != 0) {
541 ncr4 |= CR4_PGE;
542 pgeflag = PG_G;
543 }
544 ncr4 |= (cpu_feature & CPUID_VME) != 0 ? CR4_VME : 0;
545 #ifdef PMAP_PAE_COMP
546 ncr4 |= CR4_PAE;
547 #endif
548 if (ncr4 != 0)
549 load_cr4(rcr4() | ncr4);
550
551 /* Now enable paging */
552 #ifdef PMAP_PAE_COMP
553 cr3 = (u_int)IdlePDPT;
554 if ((cpu_feature & CPUID_PAT) == 0)
555 wbinvd();
556 #else
557 cr3 = (u_int)IdlePTD;
558 #endif
559 tramp_idleptd = cr3;
560 load_cr3(cr3);
561 load_cr0(rcr0() | CR0_PG);
562
563 /*
564 * Now running relocated at KERNBASE where the system is
565 * linked to run.
566 */
567
568 /*
569 * Remove the lowest part of the double mapping of low memory
570 * to get some null pointer checks.
571 */
572 __CONCAT(PMTYPE, remap_lower)(false);
573
574 kernel_vm_end = /* 0 + */ NKPT * NBPDR;
575 #ifdef PMAP_PAE_COMP
576 i386_pmap_VM_NFREEORDER = VM_NFREEORDER_PAE;
577 i386_pmap_VM_LEVEL_0_ORDER = VM_LEVEL_0_ORDER_PAE;
578 i386_pmap_PDRSHIFT = PDRSHIFT_PAE;
579 #else
580 i386_pmap_VM_NFREEORDER = VM_NFREEORDER_NOPAE;
581 i386_pmap_VM_LEVEL_0_ORDER = VM_LEVEL_0_ORDER_NOPAE;
582 i386_pmap_PDRSHIFT = PDRSHIFT_NOPAE;
583 #endif
584 }
585
586 static void
__CONCAT(PMTYPE,set_nx)587 __CONCAT(PMTYPE, set_nx)(void)
588 {
589
590 #ifdef PMAP_PAE_COMP
591 if ((amd_feature & AMDID_NX) == 0)
592 return;
593 pg_nx = PG_NX;
594 elf32_nxstack = 1;
595 /* EFER.EFER_NXE is set in initializecpu(). */
596 #endif
597 }
598
599 /*
600 * Bootstrap the system enough to run with virtual memory.
601 *
602 * On the i386 this is called after pmap_cold() created initial
603 * kernel page table and enabled paging, and just syncs the pmap
604 * module with what has already been done.
605 */
606 static void
__CONCAT(PMTYPE,bootstrap)607 __CONCAT(PMTYPE, bootstrap)(vm_paddr_t firstaddr)
608 {
609 vm_offset_t va;
610 pt_entry_t *pte, *unused __unused;
611 struct pcpu *pc;
612 u_long res;
613 int i;
614
615 res = atop(firstaddr - (vm_paddr_t)KERNLOAD);
616
617 /*
618 * Initialize the first available kernel virtual address.
619 * However, using "firstaddr" may waste a few pages of the
620 * kernel virtual address space, because pmap_cold() may not
621 * have mapped every physical page that it allocated.
622 * Preferably, pmap_cold() would provide a first unused
623 * virtual address in addition to "firstaddr".
624 */
625 virtual_avail = (vm_offset_t)firstaddr;
626 virtual_end = VM_MAX_KERNEL_ADDRESS;
627
628 /*
629 * Initialize the kernel pmap (which is statically allocated).
630 * Count bootstrap data as being resident in case any of this data is
631 * later unmapped (using pmap_remove()) and freed.
632 */
633 PMAP_LOCK_INIT(kernel_pmap);
634 kernel_pmap->pm_pdir = IdlePTD;
635 #ifdef PMAP_PAE_COMP
636 kernel_pmap->pm_pdpt = IdlePDPT;
637 #endif
638 CPU_FILL(&kernel_pmap->pm_active); /* don't allow deactivation */
639 kernel_pmap->pm_stats.resident_count = res;
640 TAILQ_INIT(&kernel_pmap->pm_pvchunk);
641 vm_radix_init(&kernel_pmap->pm_root);
642
643 /*
644 * Initialize the global pv list lock.
645 */
646 rw_init(&pvh_global_lock, "pmap pv global");
647
648 /*
649 * Reserve some special page table entries/VA space for temporary
650 * mapping of pages.
651 */
652 #define SYSMAP(c, p, v, n) \
653 v = (c)va; va += ((n)*PAGE_SIZE); p = pte; pte += (n);
654
655 va = virtual_avail;
656 pte = vtopte(va);
657
658 /*
659 * Initialize temporary map objects on the current CPU for use
660 * during early boot.
661 * CMAP1/CMAP2 are used for zeroing and copying pages.
662 * CMAP3 is used for the boot-time memory test.
663 */
664 pc = get_pcpu();
665 mtx_init(&pc->pc_cmap_lock, "SYSMAPS", NULL, MTX_DEF);
666 SYSMAP(caddr_t, pc->pc_cmap_pte1, pc->pc_cmap_addr1, 1)
667 SYSMAP(caddr_t, pc->pc_cmap_pte2, pc->pc_cmap_addr2, 1)
668 SYSMAP(vm_offset_t, pte, pc->pc_qmap_addr, 1)
669
670 SYSMAP(caddr_t, CMAP3, CADDR3, 1);
671
672 /*
673 * Crashdump maps.
674 */
675 SYSMAP(caddr_t, unused, crashdumpmap, MAXDUMPPGS)
676
677 /*
678 * ptvmmap is used for reading arbitrary physical pages via /dev/mem.
679 */
680 SYSMAP(caddr_t, unused, ptvmmap, 1)
681
682 /*
683 * msgbufp is used to map the system message buffer.
684 */
685 SYSMAP(struct msgbuf *, unused, msgbufp, atop(round_page(msgbufsize)))
686
687 /*
688 * KPTmap is used by pmap_kextract().
689 *
690 * KPTmap is first initialized by pmap_cold(). However, that initial
691 * KPTmap can only support NKPT page table pages. Here, a larger
692 * KPTmap is created that can support KVA_PAGES page table pages.
693 */
694 SYSMAP(pt_entry_t *, KPTD, KPTmap, KVA_PAGES)
695
696 for (i = 0; i < NKPT; i++)
697 KPTD[i] = (KPTphys + ptoa(i)) | PG_RW | PG_V;
698
699 /*
700 * PADDR1 and PADDR2 are used by pmap_pte_quick() and pmap_pte(),
701 * respectively.
702 */
703 SYSMAP(pt_entry_t *, PMAP1, PADDR1, 1)
704 SYSMAP(pt_entry_t *, PMAP2, PADDR2, 1)
705 SYSMAP(pt_entry_t *, PMAP3, PADDR3, 1)
706
707 mtx_init(&PMAP2mutex, "PMAP2", NULL, MTX_DEF);
708
709 virtual_avail = va;
710
711 /*
712 * Initialize the PAT MSR if present.
713 * pmap_init_pat() clears and sets CR4_PGE, which, as a
714 * side-effect, invalidates stale PG_G TLB entries that might
715 * have been created in our pre-boot environment. We assume
716 * that PAT support implies PGE and in reverse, PGE presence
717 * comes with PAT. Both features were added for Pentium Pro.
718 */
719 pmap_init_pat();
720 }
721
722 static void
pmap_init_reserved_pages(void)723 pmap_init_reserved_pages(void)
724 {
725 struct pcpu *pc;
726 vm_offset_t pages;
727 int i;
728
729 #ifdef PMAP_PAE_COMP
730 if (!pae_mode)
731 return;
732 #else
733 if (pae_mode)
734 return;
735 #endif
736 CPU_FOREACH(i) {
737 pc = pcpu_find(i);
738 mtx_init(&pc->pc_copyout_mlock, "cpmlk", NULL, MTX_DEF |
739 MTX_NEW);
740 pc->pc_copyout_maddr = kva_alloc(ptoa(2));
741 if (pc->pc_copyout_maddr == 0)
742 panic("unable to allocate non-sleepable copyout KVA");
743 sx_init(&pc->pc_copyout_slock, "cpslk");
744 pc->pc_copyout_saddr = kva_alloc(ptoa(2));
745 if (pc->pc_copyout_saddr == 0)
746 panic("unable to allocate sleepable copyout KVA");
747 pc->pc_pmap_eh_va = kva_alloc(ptoa(1));
748 if (pc->pc_pmap_eh_va == 0)
749 panic("unable to allocate pmap_extract_and_hold KVA");
750 pc->pc_pmap_eh_ptep = (char *)vtopte(pc->pc_pmap_eh_va);
751
752 /*
753 * Skip if the mappings have already been initialized,
754 * i.e. this is the BSP.
755 */
756 if (pc->pc_cmap_addr1 != 0)
757 continue;
758
759 mtx_init(&pc->pc_cmap_lock, "SYSMAPS", NULL, MTX_DEF);
760 pages = kva_alloc(PAGE_SIZE * 3);
761 if (pages == 0)
762 panic("unable to allocate CMAP KVA");
763 pc->pc_cmap_pte1 = vtopte(pages);
764 pc->pc_cmap_pte2 = vtopte(pages + PAGE_SIZE);
765 pc->pc_cmap_addr1 = (caddr_t)pages;
766 pc->pc_cmap_addr2 = (caddr_t)(pages + PAGE_SIZE);
767 pc->pc_qmap_addr = pages + ptoa(2);
768 }
769 }
770
771 SYSINIT(rpages_init, SI_SUB_CPU, SI_ORDER_ANY, pmap_init_reserved_pages, NULL);
772
773 /*
774 * Setup the PAT MSR.
775 */
776 static void
__CONCAT(PMTYPE,init_pat)777 __CONCAT(PMTYPE, init_pat)(void)
778 {
779 int pat_table[PAT_INDEX_SIZE];
780 uint64_t pat_msr;
781 u_long cr0, cr4;
782 int i;
783
784 /* Set default PAT index table. */
785 for (i = 0; i < PAT_INDEX_SIZE; i++)
786 pat_table[i] = -1;
787 pat_table[PAT_WRITE_BACK] = 0;
788 pat_table[PAT_WRITE_THROUGH] = 1;
789 pat_table[PAT_UNCACHEABLE] = 3;
790 pat_table[PAT_WRITE_COMBINING] = 3;
791 pat_table[PAT_WRITE_PROTECTED] = 3;
792 pat_table[PAT_UNCACHED] = 3;
793
794 /*
795 * Bail if this CPU doesn't implement PAT.
796 * We assume that PAT support implies PGE.
797 */
798 if ((cpu_feature & CPUID_PAT) == 0) {
799 for (i = 0; i < PAT_INDEX_SIZE; i++)
800 pat_index[i] = pat_table[i];
801 pat_works = 0;
802 return;
803 }
804
805 /*
806 * Due to some Intel errata, we can only safely use the lower 4
807 * PAT entries.
808 *
809 * Intel Pentium III Processor Specification Update
810 * Errata E.27 (Upper Four PAT Entries Not Usable With Mode B
811 * or Mode C Paging)
812 *
813 * Intel Pentium IV Processor Specification Update
814 * Errata N46 (PAT Index MSB May Be Calculated Incorrectly)
815 */
816 if (cpu_vendor_id == CPU_VENDOR_INTEL &&
817 !(CPUID_TO_FAMILY(cpu_id) == 6 && CPUID_TO_MODEL(cpu_id) >= 0xe))
818 pat_works = 0;
819
820 /* Initialize default PAT entries. */
821 pat_msr = PAT_VALUE(0, PAT_WRITE_BACK) |
822 PAT_VALUE(1, PAT_WRITE_THROUGH) |
823 PAT_VALUE(2, PAT_UNCACHED) |
824 PAT_VALUE(3, PAT_UNCACHEABLE) |
825 PAT_VALUE(4, PAT_WRITE_BACK) |
826 PAT_VALUE(5, PAT_WRITE_THROUGH) |
827 PAT_VALUE(6, PAT_UNCACHED) |
828 PAT_VALUE(7, PAT_UNCACHEABLE);
829
830 if (pat_works) {
831 /*
832 * Leave the indices 0-3 at the default of WB, WT, UC-, and UC.
833 * Program 5 and 6 as WP and WC.
834 * Leave 4 and 7 as WB and UC.
835 */
836 pat_msr &= ~(PAT_MASK(5) | PAT_MASK(6));
837 pat_msr |= PAT_VALUE(5, PAT_WRITE_PROTECTED) |
838 PAT_VALUE(6, PAT_WRITE_COMBINING);
839 pat_table[PAT_UNCACHED] = 2;
840 pat_table[PAT_WRITE_PROTECTED] = 5;
841 pat_table[PAT_WRITE_COMBINING] = 6;
842 } else {
843 /*
844 * Just replace PAT Index 2 with WC instead of UC-.
845 */
846 pat_msr &= ~PAT_MASK(2);
847 pat_msr |= PAT_VALUE(2, PAT_WRITE_COMBINING);
848 pat_table[PAT_WRITE_COMBINING] = 2;
849 }
850
851 /* Disable PGE. */
852 cr4 = rcr4();
853 load_cr4(cr4 & ~CR4_PGE);
854
855 /* Disable caches (CD = 1, NW = 0). */
856 cr0 = rcr0();
857 load_cr0((cr0 & ~CR0_NW) | CR0_CD);
858
859 /* Flushes caches and TLBs. */
860 wbinvd();
861 invltlb();
862
863 /* Update PAT and index table. */
864 wrmsr(MSR_PAT, pat_msr);
865 for (i = 0; i < PAT_INDEX_SIZE; i++)
866 pat_index[i] = pat_table[i];
867
868 /* Flush caches and TLBs again. */
869 wbinvd();
870 invltlb();
871
872 /* Restore caches and PGE. */
873 load_cr0(cr0);
874 load_cr4(cr4);
875 }
876
877 #ifdef PMAP_PAE_COMP
878 static void *
pmap_pdpt_allocf(uma_zone_t zone,vm_size_t bytes,int domain,uint8_t * sflagsp,int flags)879 pmap_pdpt_allocf(uma_zone_t zone, vm_size_t bytes, int domain, uint8_t *sflagsp,
880 int flags)
881 {
882
883 /* Inform UMA that this allocator uses kernel_map/object. */
884 *sflagsp = UMA_SLAB_KERNEL;
885 /* contig allocations cannot be NEVERFREED */
886 flags &= ~M_NEVERFREED;
887 return ((void *)kmem_alloc_contig_domainset(DOMAINSET_FIXED(domain),
888 bytes, flags, 0x0ULL, 0xffffffffULL, 1, 0, VM_MEMATTR_DEFAULT));
889 }
890 #endif
891
892 /*
893 * Abuse the pte nodes for unmapped kva to thread a kva freelist through.
894 * Requirements:
895 * - Must deal with pages in order to ensure that none of the PG_* bits
896 * are ever set, PG_V in particular.
897 * - Assumes we can write to ptes without pte_store() atomic ops, even
898 * on PAE systems. This should be ok.
899 * - Assumes nothing will ever test these addresses for 0 to indicate
900 * no mapping instead of correctly checking PG_V.
901 * - Assumes a vm_offset_t will fit in a pte (true for i386).
902 * Because PG_V is never set, there can be no mappings to invalidate.
903 */
904 static vm_offset_t
pmap_ptelist_alloc(vm_offset_t * head)905 pmap_ptelist_alloc(vm_offset_t *head)
906 {
907 pt_entry_t *pte;
908 vm_offset_t va;
909
910 va = *head;
911 if (va == 0)
912 panic("pmap_ptelist_alloc: exhausted ptelist KVA");
913 pte = vtopte(va);
914 *head = *pte;
915 if (*head & PG_V)
916 panic("pmap_ptelist_alloc: va with PG_V set!");
917 *pte = 0;
918 return (va);
919 }
920
921 static void
pmap_ptelist_free(vm_offset_t * head,vm_offset_t va)922 pmap_ptelist_free(vm_offset_t *head, vm_offset_t va)
923 {
924 pt_entry_t *pte;
925
926 if (va & PG_V)
927 panic("pmap_ptelist_free: freeing va with PG_V set!");
928 pte = vtopte(va);
929 *pte = *head; /* virtual! PG_V is 0 though */
930 *head = va;
931 }
932
933 static void
pmap_ptelist_init(vm_offset_t * head,void * base,int npages)934 pmap_ptelist_init(vm_offset_t *head, void *base, int npages)
935 {
936 int i;
937 vm_offset_t va;
938
939 *head = 0;
940 for (i = npages - 1; i >= 0; i--) {
941 va = (vm_offset_t)base + i * PAGE_SIZE;
942 pmap_ptelist_free(head, va);
943 }
944 }
945
946 /*
947 * Initialize the pmap module.
948 *
949 * Called by vm_mem_init(), to initialize any structures that the pmap
950 * system needs to map virtual memory.
951 */
952 static void
__CONCAT(PMTYPE,init)953 __CONCAT(PMTYPE, init)(void)
954 {
955 struct pmap_preinit_mapping *ppim;
956 vm_page_t mpte;
957 vm_size_t s;
958 int i, pv_npg;
959
960 /*
961 * Initialize the vm page array entries for the kernel pmap's
962 * page table pages.
963 */
964 PMAP_LOCK(kernel_pmap);
965 for (i = 0; i < NKPT; i++) {
966 mpte = PHYS_TO_VM_PAGE(KPTphys + ptoa(i));
967 KASSERT(mpte >= vm_page_array &&
968 mpte < &vm_page_array[vm_page_array_size],
969 ("pmap_init: page table page is out of range"));
970 mpte->pindex = i + KPTDI;
971 mpte->phys_addr = KPTphys + ptoa(i);
972 mpte->ref_count = 1;
973
974 /*
975 * Collect the page table pages that were replaced by a 2/4MB
976 * page. They are filled with equivalent 4KB page mappings.
977 */
978 if (pseflag != 0 &&
979 KERNBASE <= i << PDRSHIFT && i << PDRSHIFT < KERNend &&
980 pmap_insert_pt_page(kernel_pmap, mpte, true, true))
981 panic("pmap_init: pmap_insert_pt_page failed");
982 }
983 PMAP_UNLOCK(kernel_pmap);
984 vm_wire_add(NKPT);
985
986 /*
987 * Initialize the address space (zone) for the pv entries. Set a
988 * high water mark so that the system can recover from excessive
989 * numbers of pv entries.
990 */
991 TUNABLE_INT_FETCH("vm.pmap.shpgperproc", &shpgperproc);
992 pv_entry_max = shpgperproc * maxproc + vm_cnt.v_page_count;
993 TUNABLE_INT_FETCH("vm.pmap.pv_entry_max", &pv_entry_max);
994 pv_entry_max = roundup(pv_entry_max, _NPCPV);
995 pv_entry_high_water = 9 * (pv_entry_max / 10);
996
997 /*
998 * If the kernel is running on a virtual machine, then it must assume
999 * that MCA is enabled by the hypervisor. Moreover, the kernel must
1000 * be prepared for the hypervisor changing the vendor and family that
1001 * are reported by CPUID. Consequently, the workaround for AMD Family
1002 * 10h Erratum 383 is enabled if the processor's feature set does not
1003 * include at least one feature that is only supported by older Intel
1004 * or newer AMD processors.
1005 */
1006 if (vm_guest != VM_GUEST_NO && (cpu_feature & CPUID_SS) == 0 &&
1007 (cpu_feature2 & (CPUID2_SSSE3 | CPUID2_SSE41 | CPUID2_AESNI |
1008 CPUID2_AVX | CPUID2_XSAVE)) == 0 && (amd_feature2 & (AMDID2_XOP |
1009 AMDID2_FMA4)) == 0)
1010 workaround_erratum383 = 1;
1011
1012 /*
1013 * Are large page mappings supported and enabled?
1014 */
1015 TUNABLE_INT_FETCH("vm.pmap.pg_ps_enabled", &pg_ps_enabled);
1016 if (pseflag == 0)
1017 pg_ps_enabled = 0;
1018 else if (pg_ps_enabled) {
1019 KASSERT(MAXPAGESIZES > 1 && pagesizes[1] == 0,
1020 ("pmap_init: can't assign to pagesizes[1]"));
1021 pagesizes[1] = NBPDR;
1022 }
1023
1024 /*
1025 * Calculate the size of the pv head table for superpages.
1026 * Handle the possibility that "vm_phys_segs[...].end" is zero.
1027 */
1028 pv_npg = trunc_4mpage(vm_phys_segs[vm_phys_nsegs - 1].end -
1029 PAGE_SIZE) / NBPDR + 1;
1030
1031 /*
1032 * Allocate memory for the pv head table for superpages.
1033 */
1034 s = (vm_size_t)(pv_npg * sizeof(struct md_page));
1035 s = round_page(s);
1036 pv_table = kmem_malloc(s, M_WAITOK | M_ZERO);
1037 for (i = 0; i < pv_npg; i++)
1038 TAILQ_INIT(&pv_table[i].pv_list);
1039
1040 pv_maxchunks = MAX(pv_entry_max / _NPCPV, maxproc);
1041 pv_chunkbase = (struct pv_chunk *)kva_alloc(PAGE_SIZE * pv_maxchunks);
1042 if (pv_chunkbase == NULL)
1043 panic("pmap_init: not enough kvm for pv chunks");
1044 pmap_ptelist_init(&pv_vafree, pv_chunkbase, pv_maxchunks);
1045 #ifdef PMAP_PAE_COMP
1046 pdptzone = uma_zcreate("PDPT", NPGPTD * sizeof(pdpt_entry_t), NULL,
1047 NULL, NULL, NULL, (NPGPTD * sizeof(pdpt_entry_t)) - 1,
1048 UMA_ZONE_CONTIG | UMA_ZONE_VM | UMA_ZONE_NOFREE);
1049 uma_zone_set_allocf(pdptzone, pmap_pdpt_allocf);
1050 #endif
1051
1052 pmap_initialized = 1;
1053 pmap_init_trm();
1054
1055 if (!bootverbose)
1056 return;
1057 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
1058 ppim = pmap_preinit_mapping + i;
1059 if (ppim->va == 0)
1060 continue;
1061 printf("PPIM %u: PA=%#jx, VA=%#x, size=%#x, mode=%#x\n", i,
1062 (uintmax_t)ppim->pa, ppim->va, ppim->sz, ppim->mode);
1063 }
1064
1065 }
1066
1067 extern u_long pmap_pde_demotions;
1068 extern u_long pmap_pde_mappings;
1069 extern u_long pmap_pde_p_failures;
1070 extern u_long pmap_pde_promotions;
1071
1072 /***************************************************
1073 * Low level helper routines.....
1074 ***************************************************/
1075
1076 static bool
__CONCAT(PMTYPE,is_valid_memattr)1077 __CONCAT(PMTYPE, is_valid_memattr)(pmap_t pmap __unused, vm_memattr_t mode)
1078 {
1079
1080 return (mode >= 0 && mode < PAT_INDEX_SIZE &&
1081 pat_index[(int)mode] >= 0);
1082 }
1083
1084 /*
1085 * Determine the appropriate bits to set in a PTE or PDE for a specified
1086 * caching mode.
1087 */
1088 static int
__CONCAT(PMTYPE,cache_bits)1089 __CONCAT(PMTYPE, cache_bits)(pmap_t pmap, int mode, bool is_pde)
1090 {
1091 int cache_bits, pat_flag, pat_idx;
1092
1093 if (!pmap_is_valid_memattr(pmap, mode))
1094 panic("Unknown caching mode %d\n", mode);
1095
1096 /* The PAT bit is different for PTE's and PDE's. */
1097 pat_flag = is_pde ? PG_PDE_PAT : PG_PTE_PAT;
1098
1099 /* Map the caching mode to a PAT index. */
1100 pat_idx = pat_index[mode];
1101
1102 /* Map the 3-bit index value into the PAT, PCD, and PWT bits. */
1103 cache_bits = 0;
1104 if (pat_idx & 0x4)
1105 cache_bits |= pat_flag;
1106 if (pat_idx & 0x2)
1107 cache_bits |= PG_NC_PCD;
1108 if (pat_idx & 0x1)
1109 cache_bits |= PG_NC_PWT;
1110 return (cache_bits);
1111 }
1112
1113 static int
pmap_pat_index(pmap_t pmap,pt_entry_t pte,bool is_pde)1114 pmap_pat_index(pmap_t pmap, pt_entry_t pte, bool is_pde)
1115 {
1116 int pat_flag, pat_idx;
1117
1118 if ((cpu_feature & CPUID_PAT) == 0)
1119 return (0);
1120
1121 pat_idx = 0;
1122 /* The PAT bit is different for PTE's and PDE's. */
1123 pat_flag = is_pde ? PG_PDE_PAT : PG_PTE_PAT;
1124
1125 if ((pte & pat_flag) != 0)
1126 pat_idx |= 0x4;
1127 if ((pte & PG_NC_PCD) != 0)
1128 pat_idx |= 0x2;
1129 if ((pte & PG_NC_PWT) != 0)
1130 pat_idx |= 0x1;
1131
1132 /* See pmap_init_pat(). */
1133 if (pat_works) {
1134 if (pat_idx == 4)
1135 pat_idx = 0;
1136 if (pat_idx == 7)
1137 pat_idx = 3;
1138 } else {
1139 /* XXXKIB */
1140 }
1141
1142 return (pat_idx);
1143 }
1144
1145 static bool
__CONCAT(PMTYPE,ps_enabled)1146 __CONCAT(PMTYPE, ps_enabled)(pmap_t pmap __unused)
1147 {
1148
1149 return (pg_ps_enabled);
1150 }
1151
1152 /*
1153 * The caller is responsible for maintaining TLB consistency.
1154 */
1155 static void
pmap_kenter_pde(vm_offset_t va,pd_entry_t newpde)1156 pmap_kenter_pde(vm_offset_t va, pd_entry_t newpde)
1157 {
1158 pd_entry_t *pde;
1159
1160 pde = pmap_pde(kernel_pmap, va);
1161 pde_store(pde, newpde);
1162 }
1163
1164 /*
1165 * After changing the page size for the specified virtual address in the page
1166 * table, flush the corresponding entries from the processor's TLB. Only the
1167 * calling processor's TLB is affected.
1168 *
1169 * The calling thread must be pinned to a processor.
1170 */
1171 static void
pmap_update_pde_invalidate(vm_offset_t va,pd_entry_t newpde)1172 pmap_update_pde_invalidate(vm_offset_t va, pd_entry_t newpde)
1173 {
1174
1175 if ((newpde & PG_PS) == 0)
1176 /* Demotion: flush a specific 2MB page mapping. */
1177 invlpg(va);
1178 else /* if ((newpde & PG_G) == 0) */
1179 /*
1180 * Promotion: flush every 4KB page mapping from the TLB
1181 * because there are too many to flush individually.
1182 */
1183 invltlb();
1184 }
1185
1186 #ifdef SMP
1187
1188 static void
pmap_curcpu_cb_dummy(pmap_t pmap __unused,vm_offset_t addr1 __unused,vm_offset_t addr2 __unused)1189 pmap_curcpu_cb_dummy(pmap_t pmap __unused, vm_offset_t addr1 __unused,
1190 vm_offset_t addr2 __unused)
1191 {
1192 }
1193
1194 /*
1195 * For SMP, these functions have to use the IPI mechanism for coherence.
1196 *
1197 * N.B.: Before calling any of the following TLB invalidation functions,
1198 * the calling processor must ensure that all stores updating a non-
1199 * kernel page table are globally performed. Otherwise, another
1200 * processor could cache an old, pre-update entry without being
1201 * invalidated. This can happen one of two ways: (1) The pmap becomes
1202 * active on another processor after its pm_active field is checked by
1203 * one of the following functions but before a store updating the page
1204 * table is globally performed. (2) The pmap becomes active on another
1205 * processor before its pm_active field is checked but due to
1206 * speculative loads one of the following functions stills reads the
1207 * pmap as inactive on the other processor.
1208 *
1209 * The kernel page table is exempt because its pm_active field is
1210 * immutable. The kernel page table is always active on every
1211 * processor.
1212 */
1213 static void
pmap_invalidate_page_int(pmap_t pmap,vm_offset_t va)1214 pmap_invalidate_page_int(pmap_t pmap, vm_offset_t va)
1215 {
1216 cpuset_t *mask, other_cpus;
1217 u_int cpuid;
1218
1219 sched_pin();
1220 if (pmap == kernel_pmap) {
1221 invlpg(va);
1222 mask = &all_cpus;
1223 } else if (!CPU_CMP(&pmap->pm_active, &all_cpus)) {
1224 mask = &all_cpus;
1225 } else {
1226 cpuid = PCPU_GET(cpuid);
1227 other_cpus = all_cpus;
1228 CPU_CLR(cpuid, &other_cpus);
1229 CPU_AND(&other_cpus, &other_cpus, &pmap->pm_active);
1230 mask = &other_cpus;
1231 }
1232 smp_masked_invlpg(*mask, va, pmap, pmap_curcpu_cb_dummy);
1233 sched_unpin();
1234 }
1235
1236 /* 4k PTEs -- Chosen to exceed the total size of Broadwell L2 TLB */
1237 #define PMAP_INVLPG_THRESHOLD (4 * 1024 * PAGE_SIZE)
1238
1239 static void
pmap_invalidate_range_int(pmap_t pmap,vm_offset_t sva,vm_offset_t eva)1240 pmap_invalidate_range_int(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
1241 {
1242 cpuset_t *mask, other_cpus;
1243 vm_offset_t addr;
1244 u_int cpuid;
1245
1246 if (eva - sva >= PMAP_INVLPG_THRESHOLD) {
1247 pmap_invalidate_all_int(pmap);
1248 return;
1249 }
1250
1251 sched_pin();
1252 if (pmap == kernel_pmap) {
1253 for (addr = sva; addr < eva; addr += PAGE_SIZE)
1254 invlpg(addr);
1255 mask = &all_cpus;
1256 } else if (!CPU_CMP(&pmap->pm_active, &all_cpus)) {
1257 mask = &all_cpus;
1258 } else {
1259 cpuid = PCPU_GET(cpuid);
1260 other_cpus = all_cpus;
1261 CPU_CLR(cpuid, &other_cpus);
1262 CPU_AND(&other_cpus, &other_cpus, &pmap->pm_active);
1263 mask = &other_cpus;
1264 }
1265 smp_masked_invlpg_range(*mask, sva, eva, pmap, pmap_curcpu_cb_dummy);
1266 sched_unpin();
1267 }
1268
1269 static void
pmap_invalidate_all_int(pmap_t pmap)1270 pmap_invalidate_all_int(pmap_t pmap)
1271 {
1272 cpuset_t *mask, other_cpus;
1273 u_int cpuid;
1274
1275 sched_pin();
1276 if (pmap == kernel_pmap) {
1277 invltlb();
1278 mask = &all_cpus;
1279 } else if (!CPU_CMP(&pmap->pm_active, &all_cpus)) {
1280 mask = &all_cpus;
1281 } else {
1282 cpuid = PCPU_GET(cpuid);
1283 other_cpus = all_cpus;
1284 CPU_CLR(cpuid, &other_cpus);
1285 CPU_AND(&other_cpus, &other_cpus, &pmap->pm_active);
1286 mask = &other_cpus;
1287 }
1288 smp_masked_invltlb(*mask, pmap, pmap_curcpu_cb_dummy);
1289 sched_unpin();
1290 }
1291
1292 static void
pmap_invalidate_cache_curcpu_cb(pmap_t pmap __unused,vm_offset_t addr1 __unused,vm_offset_t addr2 __unused)1293 pmap_invalidate_cache_curcpu_cb(pmap_t pmap __unused,
1294 vm_offset_t addr1 __unused, vm_offset_t addr2 __unused)
1295 {
1296 wbinvd();
1297 }
1298
1299 static void
__CONCAT(PMTYPE,invalidate_cache)1300 __CONCAT(PMTYPE, invalidate_cache)(void)
1301 {
1302 smp_cache_flush(pmap_invalidate_cache_curcpu_cb);
1303 }
1304
1305 struct pde_action {
1306 cpuset_t invalidate; /* processors that invalidate their TLB */
1307 vm_offset_t va;
1308 pd_entry_t *pde;
1309 pd_entry_t newpde;
1310 u_int store; /* processor that updates the PDE */
1311 };
1312
1313 static void
pmap_update_pde_kernel(void * arg)1314 pmap_update_pde_kernel(void *arg)
1315 {
1316 struct pde_action *act = arg;
1317 pd_entry_t *pde;
1318
1319 if (act->store == PCPU_GET(cpuid)) {
1320 pde = pmap_pde(kernel_pmap, act->va);
1321 pde_store(pde, act->newpde);
1322 }
1323 }
1324
1325 static void
pmap_update_pde_user(void * arg)1326 pmap_update_pde_user(void *arg)
1327 {
1328 struct pde_action *act = arg;
1329
1330 if (act->store == PCPU_GET(cpuid))
1331 pde_store(act->pde, act->newpde);
1332 }
1333
1334 static void
pmap_update_pde_teardown(void * arg)1335 pmap_update_pde_teardown(void *arg)
1336 {
1337 struct pde_action *act = arg;
1338
1339 if (CPU_ISSET(PCPU_GET(cpuid), &act->invalidate))
1340 pmap_update_pde_invalidate(act->va, act->newpde);
1341 }
1342
1343 /*
1344 * Change the page size for the specified virtual address in a way that
1345 * prevents any possibility of the TLB ever having two entries that map the
1346 * same virtual address using different page sizes. This is the recommended
1347 * workaround for Erratum 383 on AMD Family 10h processors. It prevents a
1348 * machine check exception for a TLB state that is improperly diagnosed as a
1349 * hardware error.
1350 */
1351 static void
pmap_update_pde(pmap_t pmap,vm_offset_t va,pd_entry_t * pde,pd_entry_t newpde)1352 pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, pd_entry_t newpde)
1353 {
1354 struct pde_action act;
1355 cpuset_t active, other_cpus;
1356 u_int cpuid;
1357
1358 sched_pin();
1359 cpuid = PCPU_GET(cpuid);
1360 other_cpus = all_cpus;
1361 CPU_CLR(cpuid, &other_cpus);
1362 if (pmap == kernel_pmap)
1363 active = all_cpus;
1364 else
1365 active = pmap->pm_active;
1366 if (CPU_OVERLAP(&active, &other_cpus)) {
1367 act.store = cpuid;
1368 act.invalidate = active;
1369 act.va = va;
1370 act.pde = pde;
1371 act.newpde = newpde;
1372 CPU_SET(cpuid, &active);
1373 smp_rendezvous_cpus(active,
1374 smp_no_rendezvous_barrier, pmap == kernel_pmap ?
1375 pmap_update_pde_kernel : pmap_update_pde_user,
1376 pmap_update_pde_teardown, &act);
1377 } else {
1378 if (pmap == kernel_pmap)
1379 pmap_kenter_pde(va, newpde);
1380 else
1381 pde_store(pde, newpde);
1382 if (CPU_ISSET(cpuid, &active))
1383 pmap_update_pde_invalidate(va, newpde);
1384 }
1385 sched_unpin();
1386 }
1387 #else /* !SMP */
1388 /*
1389 * Normal, non-SMP, 486+ invalidation functions.
1390 * We inline these within pmap.c for speed.
1391 */
1392 static void
pmap_invalidate_page_int(pmap_t pmap,vm_offset_t va)1393 pmap_invalidate_page_int(pmap_t pmap, vm_offset_t va)
1394 {
1395
1396 if (pmap == kernel_pmap)
1397 invlpg(va);
1398 }
1399
1400 static void
pmap_invalidate_range_int(pmap_t pmap,vm_offset_t sva,vm_offset_t eva)1401 pmap_invalidate_range_int(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
1402 {
1403 vm_offset_t addr;
1404
1405 if (pmap == kernel_pmap)
1406 for (addr = sva; addr < eva; addr += PAGE_SIZE)
1407 invlpg(addr);
1408 }
1409
1410 static void
pmap_invalidate_all_int(pmap_t pmap)1411 pmap_invalidate_all_int(pmap_t pmap)
1412 {
1413
1414 if (pmap == kernel_pmap)
1415 invltlb();
1416 }
1417
1418 static void
__CONCAT(PMTYPE,invalidate_cache)1419 __CONCAT(PMTYPE, invalidate_cache)(void)
1420 {
1421
1422 wbinvd();
1423 }
1424
1425 static void
pmap_update_pde(pmap_t pmap,vm_offset_t va,pd_entry_t * pde,pd_entry_t newpde)1426 pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, pd_entry_t newpde)
1427 {
1428
1429 if (pmap == kernel_pmap)
1430 pmap_kenter_pde(va, newpde);
1431 else
1432 pde_store(pde, newpde);
1433 if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active))
1434 pmap_update_pde_invalidate(va, newpde);
1435 }
1436 #endif /* !SMP */
1437
1438 static void
__CONCAT(PMTYPE,invalidate_page)1439 __CONCAT(PMTYPE, invalidate_page)(pmap_t pmap, vm_offset_t va)
1440 {
1441
1442 pmap_invalidate_page_int(pmap, va);
1443 }
1444
1445 static void
__CONCAT(PMTYPE,invalidate_range)1446 __CONCAT(PMTYPE, invalidate_range)(pmap_t pmap, vm_offset_t sva,
1447 vm_offset_t eva)
1448 {
1449
1450 pmap_invalidate_range_int(pmap, sva, eva);
1451 }
1452
1453 static void
__CONCAT(PMTYPE,invalidate_all)1454 __CONCAT(PMTYPE, invalidate_all)(pmap_t pmap)
1455 {
1456
1457 pmap_invalidate_all_int(pmap);
1458 }
1459
1460 static void
pmap_invalidate_pde_page(pmap_t pmap,vm_offset_t va,pd_entry_t pde)1461 pmap_invalidate_pde_page(pmap_t pmap, vm_offset_t va, pd_entry_t pde)
1462 {
1463
1464 /*
1465 * When the PDE has PG_PROMOTED set, the 2- or 4MB page mapping was
1466 * created by a promotion that did not invalidate the 512 or 1024 4KB
1467 * page mappings that might exist in the TLB. Consequently, at this
1468 * point, the TLB may hold both 4KB and 2- or 4MB page mappings for
1469 * the address range [va, va + NBPDR). Therefore, the entire range
1470 * must be invalidated here. In contrast, when PG_PROMOTED is clear,
1471 * the TLB will not hold any 4KB page mappings for the address range
1472 * [va, va + NBPDR), and so a single INVLPG suffices to invalidate the
1473 * 2- or 4MB page mapping from the TLB.
1474 */
1475 if ((pde & PG_PROMOTED) != 0)
1476 pmap_invalidate_range_int(pmap, va, va + NBPDR - 1);
1477 else
1478 pmap_invalidate_page_int(pmap, va);
1479 }
1480
1481 /*
1482 * Are we current address space or kernel?
1483 */
1484 static __inline int
pmap_is_current(pmap_t pmap)1485 pmap_is_current(pmap_t pmap)
1486 {
1487
1488 return (pmap == kernel_pmap);
1489 }
1490
1491 /*
1492 * If the given pmap is not the current or kernel pmap, the returned pte must
1493 * be released by passing it to pmap_pte_release().
1494 */
1495 static pt_entry_t *
__CONCAT(PMTYPE,pte)1496 __CONCAT(PMTYPE, pte)(pmap_t pmap, vm_offset_t va)
1497 {
1498 pd_entry_t newpf;
1499 pd_entry_t *pde;
1500
1501 pde = pmap_pde(pmap, va);
1502 if (*pde & PG_PS)
1503 return (pde);
1504 if (*pde != 0) {
1505 /* are we current address space or kernel? */
1506 if (pmap_is_current(pmap))
1507 return (vtopte(va));
1508 mtx_lock(&PMAP2mutex);
1509 newpf = *pde & PG_FRAME;
1510 if ((*PMAP2 & PG_FRAME) != newpf) {
1511 *PMAP2 = newpf | PG_RW | PG_V | PG_A | PG_M;
1512 pmap_invalidate_page_int(kernel_pmap,
1513 (vm_offset_t)PADDR2);
1514 }
1515 return (PADDR2 + (i386_btop(va) & (NPTEPG - 1)));
1516 }
1517 return (NULL);
1518 }
1519
1520 /*
1521 * Releases a pte that was obtained from pmap_pte(). Be prepared for the pte
1522 * being NULL.
1523 */
1524 static __inline void
pmap_pte_release(pt_entry_t * pte)1525 pmap_pte_release(pt_entry_t *pte)
1526 {
1527
1528 if ((pt_entry_t *)((vm_offset_t)pte & ~PAGE_MASK) == PADDR2)
1529 mtx_unlock(&PMAP2mutex);
1530 }
1531
1532 /*
1533 * NB: The sequence of updating a page table followed by accesses to the
1534 * corresponding pages is subject to the situation described in the "AMD64
1535 * Architecture Programmer's Manual Volume 2: System Programming" rev. 3.23,
1536 * "7.3.1 Special Coherency Considerations". Therefore, issuing the INVLPG
1537 * right after modifying the PTE bits is crucial.
1538 */
1539 static __inline void
invlcaddr(void * caddr)1540 invlcaddr(void *caddr)
1541 {
1542
1543 invlpg((u_int)caddr);
1544 }
1545
1546 /*
1547 * Super fast pmap_pte routine best used when scanning
1548 * the pv lists. This eliminates many coarse-grained
1549 * invltlb calls. Note that many of the pv list
1550 * scans are across different pmaps. It is very wasteful
1551 * to do an entire invltlb for checking a single mapping.
1552 *
1553 * If the given pmap is not the current pmap, pvh_global_lock
1554 * must be held and curthread pinned to a CPU.
1555 */
1556 static pt_entry_t *
pmap_pte_quick(pmap_t pmap,vm_offset_t va)1557 pmap_pte_quick(pmap_t pmap, vm_offset_t va)
1558 {
1559 pd_entry_t newpf;
1560 pd_entry_t *pde;
1561
1562 pde = pmap_pde(pmap, va);
1563 if (*pde & PG_PS)
1564 return (pde);
1565 if (*pde != 0) {
1566 /* are we current address space or kernel? */
1567 if (pmap_is_current(pmap))
1568 return (vtopte(va));
1569 rw_assert(&pvh_global_lock, RA_WLOCKED);
1570 KASSERT(curthread->td_pinned > 0, ("curthread not pinned"));
1571 newpf = *pde & PG_FRAME;
1572 if ((*PMAP1 & PG_FRAME) != newpf) {
1573 *PMAP1 = newpf | PG_RW | PG_V | PG_A | PG_M;
1574 #ifdef SMP
1575 PMAP1cpu = PCPU_GET(cpuid);
1576 #endif
1577 invlcaddr(PADDR1);
1578 PMAP1changed++;
1579 } else
1580 #ifdef SMP
1581 if (PMAP1cpu != PCPU_GET(cpuid)) {
1582 PMAP1cpu = PCPU_GET(cpuid);
1583 invlcaddr(PADDR1);
1584 PMAP1changedcpu++;
1585 } else
1586 #endif
1587 PMAP1unchanged++;
1588 return (PADDR1 + (i386_btop(va) & (NPTEPG - 1)));
1589 }
1590 return (0);
1591 }
1592
1593 static pt_entry_t *
pmap_pte_quick3(pmap_t pmap,vm_offset_t va)1594 pmap_pte_quick3(pmap_t pmap, vm_offset_t va)
1595 {
1596 pd_entry_t newpf;
1597 pd_entry_t *pde;
1598
1599 pde = pmap_pde(pmap, va);
1600 if (*pde & PG_PS)
1601 return (pde);
1602 if (*pde != 0) {
1603 rw_assert(&pvh_global_lock, RA_WLOCKED);
1604 KASSERT(curthread->td_pinned > 0, ("curthread not pinned"));
1605 newpf = *pde & PG_FRAME;
1606 if ((*PMAP3 & PG_FRAME) != newpf) {
1607 *PMAP3 = newpf | PG_RW | PG_V | PG_A | PG_M;
1608 #ifdef SMP
1609 PMAP3cpu = PCPU_GET(cpuid);
1610 #endif
1611 invlcaddr(PADDR3);
1612 PMAP1changed++;
1613 } else
1614 #ifdef SMP
1615 if (PMAP3cpu != PCPU_GET(cpuid)) {
1616 PMAP3cpu = PCPU_GET(cpuid);
1617 invlcaddr(PADDR3);
1618 PMAP1changedcpu++;
1619 } else
1620 #endif
1621 PMAP1unchanged++;
1622 return (PADDR3 + (i386_btop(va) & (NPTEPG - 1)));
1623 }
1624 return (0);
1625 }
1626
1627 static pt_entry_t
pmap_pte_ufast(pmap_t pmap,vm_offset_t va,pd_entry_t pde)1628 pmap_pte_ufast(pmap_t pmap, vm_offset_t va, pd_entry_t pde)
1629 {
1630 pt_entry_t *eh_ptep, pte, *ptep;
1631
1632 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1633 pde &= PG_FRAME;
1634 critical_enter();
1635 eh_ptep = (pt_entry_t *)PCPU_GET(pmap_eh_ptep);
1636 if ((*eh_ptep & PG_FRAME) != pde) {
1637 *eh_ptep = pde | PG_RW | PG_V | PG_A | PG_M;
1638 invlcaddr((void *)PCPU_GET(pmap_eh_va));
1639 }
1640 ptep = (pt_entry_t *)PCPU_GET(pmap_eh_va) + (i386_btop(va) &
1641 (NPTEPG - 1));
1642 pte = *ptep;
1643 critical_exit();
1644 return (pte);
1645 }
1646
1647 /*
1648 * Extract from the kernel page table the physical address that is mapped by
1649 * the given virtual address "va".
1650 *
1651 * This function may be used before pmap_bootstrap() is called.
1652 */
1653 static vm_paddr_t
__CONCAT(PMTYPE,kextract)1654 __CONCAT(PMTYPE, kextract)(vm_offset_t va)
1655 {
1656 vm_paddr_t pa;
1657
1658 if ((pa = pte_load(&PTD[va >> PDRSHIFT])) & PG_PS) {
1659 pa = (pa & PG_PS_FRAME) | (va & PDRMASK);
1660 } else {
1661 /*
1662 * Beware of a concurrent promotion that changes the PDE at
1663 * this point! For example, vtopte() must not be used to
1664 * access the PTE because it would use the new PDE. It is,
1665 * however, safe to use the old PDE because the page table
1666 * page is preserved by the promotion.
1667 */
1668 pa = KPTmap[i386_btop(va)];
1669 pa = (pa & PG_FRAME) | (va & PAGE_MASK);
1670 }
1671 return (pa);
1672 }
1673
1674 /*
1675 * Routine: pmap_extract
1676 * Function:
1677 * Extract the physical page address associated
1678 * with the given map/virtual_address pair.
1679 */
1680 static vm_paddr_t
__CONCAT(PMTYPE,extract)1681 __CONCAT(PMTYPE, extract)(pmap_t pmap, vm_offset_t va)
1682 {
1683 vm_paddr_t rtval;
1684 pt_entry_t pte;
1685 pd_entry_t pde;
1686
1687 rtval = 0;
1688 PMAP_LOCK(pmap);
1689 pde = pmap->pm_pdir[va >> PDRSHIFT];
1690 if (pde != 0) {
1691 if ((pde & PG_PS) != 0)
1692 rtval = (pde & PG_PS_FRAME) | (va & PDRMASK);
1693 else {
1694 pte = pmap_pte_ufast(pmap, va, pde);
1695 rtval = (pte & PG_FRAME) | (va & PAGE_MASK);
1696 }
1697 }
1698 PMAP_UNLOCK(pmap);
1699 return (rtval);
1700 }
1701
1702 /*
1703 * Routine: pmap_extract_and_hold
1704 * Function:
1705 * Atomically extract and hold the physical page
1706 * with the given pmap and virtual address pair
1707 * if that mapping permits the given protection.
1708 */
1709 static vm_page_t
__CONCAT(PMTYPE,extract_and_hold)1710 __CONCAT(PMTYPE, extract_and_hold)(pmap_t pmap, vm_offset_t va, vm_prot_t prot)
1711 {
1712 pd_entry_t pde;
1713 pt_entry_t pte;
1714 vm_page_t m;
1715
1716 m = NULL;
1717 PMAP_LOCK(pmap);
1718 pde = *pmap_pde(pmap, va);
1719 if (pde != 0) {
1720 if (pde & PG_PS) {
1721 if ((pde & PG_RW) || (prot & VM_PROT_WRITE) == 0)
1722 m = PHYS_TO_VM_PAGE((pde & PG_PS_FRAME) |
1723 (va & PDRMASK));
1724 } else {
1725 pte = pmap_pte_ufast(pmap, va, pde);
1726 if (pte != 0 &&
1727 ((pte & PG_RW) || (prot & VM_PROT_WRITE) == 0))
1728 m = PHYS_TO_VM_PAGE(pte & PG_FRAME);
1729 }
1730 if (m != NULL && !vm_page_wire_mapped(m))
1731 m = NULL;
1732 }
1733 PMAP_UNLOCK(pmap);
1734 return (m);
1735 }
1736
1737 /***************************************************
1738 * Low level mapping routines.....
1739 ***************************************************/
1740
1741 /*
1742 * Add a wired page to the kva.
1743 * Note: not SMP coherent.
1744 *
1745 * This function may be used before pmap_bootstrap() is called.
1746 */
1747 static void
__CONCAT(PMTYPE,kenter)1748 __CONCAT(PMTYPE, kenter)(vm_offset_t va, vm_paddr_t pa)
1749 {
1750 pt_entry_t *pte;
1751
1752 pte = vtopte(va);
1753 pte_store(pte, pa | PG_RW | PG_V);
1754 }
1755
1756 static __inline void
pmap_kenter_attr(vm_offset_t va,vm_paddr_t pa,int mode)1757 pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode)
1758 {
1759 pt_entry_t *pte;
1760
1761 pte = vtopte(va);
1762 pte_store(pte, pa | PG_RW | PG_V | pmap_cache_bits(kernel_pmap,
1763 mode, false));
1764 }
1765
1766 /*
1767 * Remove a page from the kernel pagetables.
1768 * Note: not SMP coherent.
1769 *
1770 * This function may be used before pmap_bootstrap() is called.
1771 */
1772 static void
__CONCAT(PMTYPE,kremove)1773 __CONCAT(PMTYPE, kremove)(vm_offset_t va)
1774 {
1775 pt_entry_t *pte;
1776
1777 pte = vtopte(va);
1778 pte_clear(pte);
1779 }
1780
1781 /*
1782 * Used to map a range of physical addresses into kernel
1783 * virtual address space.
1784 *
1785 * The value passed in '*virt' is a suggested virtual address for
1786 * the mapping. Architectures which can support a direct-mapped
1787 * physical to virtual region can return the appropriate address
1788 * within that region, leaving '*virt' unchanged. Other
1789 * architectures should map the pages starting at '*virt' and
1790 * update '*virt' with the first usable address after the mapped
1791 * region.
1792 */
1793 static vm_offset_t
__CONCAT(PMTYPE,map)1794 __CONCAT(PMTYPE, map)(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end,
1795 int prot)
1796 {
1797 vm_offset_t va, sva;
1798 vm_paddr_t superpage_offset;
1799 pd_entry_t newpde;
1800
1801 va = *virt;
1802 /*
1803 * Does the physical address range's size and alignment permit at
1804 * least one superpage mapping to be created?
1805 */
1806 superpage_offset = start & PDRMASK;
1807 if ((end - start) - ((NBPDR - superpage_offset) & PDRMASK) >= NBPDR) {
1808 /*
1809 * Increase the starting virtual address so that its alignment
1810 * does not preclude the use of superpage mappings.
1811 */
1812 if ((va & PDRMASK) < superpage_offset)
1813 va = (va & ~PDRMASK) + superpage_offset;
1814 else if ((va & PDRMASK) > superpage_offset)
1815 va = ((va + PDRMASK) & ~PDRMASK) + superpage_offset;
1816 }
1817 sva = va;
1818 while (start < end) {
1819 if ((start & PDRMASK) == 0 && end - start >= NBPDR &&
1820 pseflag != 0) {
1821 KASSERT((va & PDRMASK) == 0,
1822 ("pmap_map: misaligned va %#x", va));
1823 newpde = start | PG_PS | PG_RW | PG_V;
1824 pmap_kenter_pde(va, newpde);
1825 va += NBPDR;
1826 start += NBPDR;
1827 } else {
1828 pmap_kenter(va, start);
1829 va += PAGE_SIZE;
1830 start += PAGE_SIZE;
1831 }
1832 }
1833 pmap_invalidate_range_int(kernel_pmap, sva, va);
1834 *virt = va;
1835 return (sva);
1836 }
1837
1838 /*
1839 * Add a list of wired pages to the kva
1840 * this routine is only used for temporary
1841 * kernel mappings that do not need to have
1842 * page modification or references recorded.
1843 * Note that old mappings are simply written
1844 * over. The page *must* be wired.
1845 * Note: SMP coherent. Uses a ranged shootdown IPI.
1846 */
1847 static void
__CONCAT(PMTYPE,qenter)1848 __CONCAT(PMTYPE, qenter)(vm_offset_t sva, vm_page_t *ma, int count)
1849 {
1850 pt_entry_t *endpte, oldpte, pa, *pte;
1851 vm_page_t m;
1852
1853 oldpte = 0;
1854 pte = vtopte(sva);
1855 endpte = pte + count;
1856 while (pte < endpte) {
1857 m = *ma++;
1858 pa = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(kernel_pmap,
1859 m->md.pat_mode, false);
1860 if ((*pte & (PG_FRAME | PG_PTE_CACHE)) != pa) {
1861 oldpte |= *pte;
1862 pte_store(pte, pa | pg_nx | PG_RW | PG_V);
1863 }
1864 pte++;
1865 }
1866 if (__predict_false((oldpte & PG_V) != 0))
1867 pmap_invalidate_range_int(kernel_pmap, sva, sva + count *
1868 PAGE_SIZE);
1869 }
1870
1871 /*
1872 * This routine tears out page mappings from the
1873 * kernel -- it is meant only for temporary mappings.
1874 * Note: SMP coherent. Uses a ranged shootdown IPI.
1875 */
1876 static void
__CONCAT(PMTYPE,qremove)1877 __CONCAT(PMTYPE, qremove)(vm_offset_t sva, int count)
1878 {
1879 vm_offset_t va;
1880
1881 va = sva;
1882 while (count-- > 0) {
1883 pmap_kremove(va);
1884 va += PAGE_SIZE;
1885 }
1886 pmap_invalidate_range_int(kernel_pmap, sva, va);
1887 }
1888
1889 /***************************************************
1890 * Page table page management routines.....
1891 ***************************************************/
1892 /*
1893 * Schedule the specified unused page table page to be freed. Specifically,
1894 * add the page to the specified list of pages that will be released to the
1895 * physical memory manager after the TLB has been updated.
1896 */
1897 static __inline void
pmap_add_delayed_free_list(vm_page_t m,struct spglist * free,bool set_PG_ZERO)1898 pmap_add_delayed_free_list(vm_page_t m, struct spglist *free, bool set_PG_ZERO)
1899 {
1900
1901 if (set_PG_ZERO)
1902 m->flags |= PG_ZERO;
1903 else
1904 m->flags &= ~PG_ZERO;
1905 SLIST_INSERT_HEAD(free, m, plinks.s.ss);
1906 }
1907
1908 /*
1909 * Inserts the specified page table page into the specified pmap's collection
1910 * of idle page table pages. Each of a pmap's page table pages is responsible
1911 * for mapping a distinct range of virtual addresses. The pmap's collection is
1912 * ordered by this virtual address range.
1913 *
1914 * If "promoted" is false, then the page table page "mpte" must be zero filled;
1915 * "mpte"'s valid field will be set to 0.
1916 *
1917 * If "promoted" is true and "allpte_PG_A_set" is false, then "mpte" must
1918 * contain valid mappings with identical attributes except for PG_A; "mpte"'s
1919 * valid field will be set to 1.
1920 *
1921 * If "promoted" and "allpte_PG_A_set" are both true, then "mpte" must contain
1922 * valid mappings with identical attributes including PG_A; "mpte"'s valid
1923 * field will be set to VM_PAGE_BITS_ALL.
1924 */
1925 static __inline int
pmap_insert_pt_page(pmap_t pmap,vm_page_t mpte,bool promoted,bool allpte_PG_A_set)1926 pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte, bool promoted,
1927 bool allpte_PG_A_set)
1928 {
1929
1930 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1931 KASSERT(promoted || !allpte_PG_A_set,
1932 ("a zero-filled PTP can't have PG_A set in every PTE"));
1933 mpte->valid = promoted ? (allpte_PG_A_set ? VM_PAGE_BITS_ALL : 1) : 0;
1934 return (vm_radix_insert(&pmap->pm_root, mpte));
1935 }
1936
1937 /*
1938 * Removes the page table page mapping the specified virtual address from the
1939 * specified pmap's collection of idle page table pages, and returns it.
1940 * Otherwise, returns NULL if there is no page table page corresponding to the
1941 * specified virtual address.
1942 */
1943 static __inline vm_page_t
pmap_remove_pt_page(pmap_t pmap,vm_offset_t va)1944 pmap_remove_pt_page(pmap_t pmap, vm_offset_t va)
1945 {
1946
1947 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1948 return (vm_radix_remove(&pmap->pm_root, va >> PDRSHIFT));
1949 }
1950
1951 /*
1952 * Decrements a page table page's reference count, which is used to record the
1953 * number of valid page table entries within the page. If the reference count
1954 * drops to zero, then the page table page is unmapped. Returns true if the
1955 * page table page was unmapped and false otherwise.
1956 */
1957 static inline bool
pmap_unwire_ptp(pmap_t pmap,vm_page_t m,struct spglist * free)1958 pmap_unwire_ptp(pmap_t pmap, vm_page_t m, struct spglist *free)
1959 {
1960
1961 --m->ref_count;
1962 if (m->ref_count == 0) {
1963 _pmap_unwire_ptp(pmap, m, free);
1964 return (true);
1965 } else
1966 return (false);
1967 }
1968
1969 static void
_pmap_unwire_ptp(pmap_t pmap,vm_page_t m,struct spglist * free)1970 _pmap_unwire_ptp(pmap_t pmap, vm_page_t m, struct spglist *free)
1971 {
1972
1973 /*
1974 * unmap the page table page
1975 */
1976 pmap->pm_pdir[m->pindex] = 0;
1977 --pmap->pm_stats.resident_count;
1978
1979 /*
1980 * There is not need to invalidate the recursive mapping since
1981 * we never instantiate such mapping for the usermode pmaps,
1982 * and never remove page table pages from the kernel pmap.
1983 * Put page on a list so that it is released since all TLB
1984 * shootdown is done.
1985 */
1986 MPASS(pmap != kernel_pmap);
1987 pmap_add_delayed_free_list(m, free, true);
1988 }
1989
1990 /*
1991 * After removing a page table entry, this routine is used to
1992 * conditionally free the page, and manage the reference count.
1993 */
1994 static int
pmap_unuse_pt(pmap_t pmap,vm_offset_t va,struct spglist * free)1995 pmap_unuse_pt(pmap_t pmap, vm_offset_t va, struct spglist *free)
1996 {
1997 pd_entry_t ptepde;
1998 vm_page_t mpte;
1999
2000 if (pmap == kernel_pmap)
2001 return (0);
2002 ptepde = *pmap_pde(pmap, va);
2003 mpte = PHYS_TO_VM_PAGE(ptepde & PG_FRAME);
2004 return (pmap_unwire_ptp(pmap, mpte, free));
2005 }
2006
2007 /*
2008 * Release a page table page reference after a failed attempt to create a
2009 * mapping.
2010 */
2011 static void
pmap_abort_ptp(pmap_t pmap,vm_offset_t va,vm_page_t mpte)2012 pmap_abort_ptp(pmap_t pmap, vm_offset_t va, vm_page_t mpte)
2013 {
2014 struct spglist free;
2015
2016 SLIST_INIT(&free);
2017 if (pmap_unwire_ptp(pmap, mpte, &free)) {
2018 /*
2019 * Although "va" was never mapped, paging-structure caches
2020 * could nonetheless have entries that refer to the freed
2021 * page table pages. Invalidate those entries.
2022 */
2023 pmap_invalidate_page_int(pmap, va);
2024 vm_page_free_pages_toq(&free, true);
2025 }
2026 }
2027
2028 /*
2029 * Initialize the pmap for the swapper process.
2030 */
2031 static void
__CONCAT(PMTYPE,pinit0)2032 __CONCAT(PMTYPE, pinit0)(pmap_t pmap)
2033 {
2034
2035 PMAP_LOCK_INIT(pmap);
2036 pmap->pm_pdir = IdlePTD;
2037 #ifdef PMAP_PAE_COMP
2038 pmap->pm_pdpt = IdlePDPT;
2039 #endif
2040 vm_radix_init(&pmap->pm_root);
2041 CPU_ZERO(&pmap->pm_active);
2042 TAILQ_INIT(&pmap->pm_pvchunk);
2043 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
2044 pmap_activate_boot(pmap);
2045 }
2046
2047 /*
2048 * Initialize a preallocated and zeroed pmap structure,
2049 * such as one in a vmspace structure.
2050 */
2051 static int
__CONCAT(PMTYPE,pinit)2052 __CONCAT(PMTYPE, pinit)(pmap_t pmap)
2053 {
2054 int i;
2055
2056 /*
2057 * No need to allocate page table space yet but we do need a valid
2058 * page directory table.
2059 */
2060 if (pmap->pm_pdir == NULL) {
2061 pmap->pm_pdir = (pd_entry_t *)kva_alloc(NBPTD);
2062 if (pmap->pm_pdir == NULL)
2063 return (0);
2064 #ifdef PMAP_PAE_COMP
2065 pmap->pm_pdpt = uma_zalloc(pdptzone, M_WAITOK | M_ZERO);
2066 KASSERT(((vm_offset_t)pmap->pm_pdpt &
2067 ((NPGPTD * sizeof(pdpt_entry_t)) - 1)) == 0,
2068 ("pmap_pinit: pdpt misaligned"));
2069 KASSERT(pmap_kextract((vm_offset_t)pmap->pm_pdpt) < (4ULL<<30),
2070 ("pmap_pinit: pdpt above 4g"));
2071 #endif
2072 vm_radix_init(&pmap->pm_root);
2073 }
2074 KASSERT(vm_radix_is_empty(&pmap->pm_root),
2075 ("pmap_pinit: pmap has reserved page table page(s)"));
2076
2077 /*
2078 * allocate the page directory page(s)
2079 */
2080 for (i = 0; i < NPGPTD; i++) {
2081 pmap->pm_ptdpg[i] = vm_page_alloc_noobj(VM_ALLOC_WIRED |
2082 VM_ALLOC_ZERO | VM_ALLOC_WAITOK);
2083 #ifdef PMAP_PAE_COMP
2084 pmap->pm_pdpt[i] = VM_PAGE_TO_PHYS(pmap->pm_ptdpg[i]) | PG_V;
2085 #endif
2086 }
2087
2088 pmap_qenter((vm_offset_t)pmap->pm_pdir, pmap->pm_ptdpg, NPGPTD);
2089 #ifdef PMAP_PAE_COMP
2090 if ((cpu_feature & CPUID_PAT) == 0) {
2091 pmap_invalidate_cache_range(
2092 trunc_page((vm_offset_t)pmap->pm_pdpt),
2093 round_page((vm_offset_t)pmap->pm_pdpt +
2094 NPGPTD * sizeof(pdpt_entry_t)));
2095 }
2096 #endif
2097
2098 /* Install the trampoline mapping. */
2099 pmap->pm_pdir[TRPTDI] = PTD[TRPTDI];
2100
2101 CPU_ZERO(&pmap->pm_active);
2102 TAILQ_INIT(&pmap->pm_pvchunk);
2103 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
2104
2105 return (1);
2106 }
2107
2108 /*
2109 * this routine is called if the page table page is not
2110 * mapped correctly.
2111 */
2112 static vm_page_t
_pmap_allocpte(pmap_t pmap,u_int ptepindex,u_int flags)2113 _pmap_allocpte(pmap_t pmap, u_int ptepindex, u_int flags)
2114 {
2115 vm_paddr_t ptepa;
2116 vm_page_t m;
2117
2118 /*
2119 * Allocate a page table page.
2120 */
2121 if ((m = vm_page_alloc_noobj(VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL) {
2122 if ((flags & PMAP_ENTER_NOSLEEP) == 0) {
2123 PMAP_UNLOCK(pmap);
2124 rw_wunlock(&pvh_global_lock);
2125 vm_wait(NULL);
2126 rw_wlock(&pvh_global_lock);
2127 PMAP_LOCK(pmap);
2128 }
2129
2130 /*
2131 * Indicate the need to retry. While waiting, the page table
2132 * page may have been allocated.
2133 */
2134 return (NULL);
2135 }
2136 m->pindex = ptepindex;
2137
2138 /*
2139 * Map the pagetable page into the process address space, if
2140 * it isn't already there.
2141 */
2142
2143 pmap->pm_stats.resident_count++;
2144
2145 ptepa = VM_PAGE_TO_PHYS(m);
2146 KASSERT((pmap->pm_pdir[ptepindex] & PG_V) == 0,
2147 ("%s: page directory entry %#jx is valid",
2148 __func__, (uintmax_t)pmap->pm_pdir[ptepindex]));
2149 pmap->pm_pdir[ptepindex] =
2150 (pd_entry_t)(ptepa | PG_U | PG_RW | PG_V | PG_A | PG_M);
2151
2152 return (m);
2153 }
2154
2155 static vm_page_t
pmap_allocpte(pmap_t pmap,vm_offset_t va,u_int flags)2156 pmap_allocpte(pmap_t pmap, vm_offset_t va, u_int flags)
2157 {
2158 u_int ptepindex;
2159 pd_entry_t ptepa;
2160 vm_page_t m;
2161
2162 /*
2163 * Calculate pagetable page index
2164 */
2165 ptepindex = va >> PDRSHIFT;
2166 retry:
2167 /*
2168 * Get the page directory entry
2169 */
2170 ptepa = pmap->pm_pdir[ptepindex];
2171
2172 /*
2173 * This supports switching from a 4MB page to a
2174 * normal 4K page.
2175 */
2176 if (ptepa & PG_PS) {
2177 (void)pmap_demote_pde(pmap, &pmap->pm_pdir[ptepindex], va);
2178 ptepa = pmap->pm_pdir[ptepindex];
2179 }
2180
2181 /*
2182 * If the page table page is mapped, we just increment the
2183 * hold count, and activate it.
2184 */
2185 if (ptepa) {
2186 m = PHYS_TO_VM_PAGE(ptepa & PG_FRAME);
2187 m->ref_count++;
2188 } else {
2189 /*
2190 * Here if the pte page isn't mapped, or if it has
2191 * been deallocated.
2192 */
2193 m = _pmap_allocpte(pmap, ptepindex, flags);
2194 if (m == NULL && (flags & PMAP_ENTER_NOSLEEP) == 0)
2195 goto retry;
2196 }
2197 return (m);
2198 }
2199
2200 /***************************************************
2201 * Pmap allocation/deallocation routines.
2202 ***************************************************/
2203
2204 /*
2205 * Release any resources held by the given physical map.
2206 * Called when a pmap initialized by pmap_pinit is being released.
2207 * Should only be called if the map contains no valid mappings.
2208 */
2209 static void
__CONCAT(PMTYPE,release)2210 __CONCAT(PMTYPE, release)(pmap_t pmap)
2211 {
2212 vm_page_t m;
2213 int i;
2214
2215 KASSERT(pmap->pm_stats.resident_count == 0,
2216 ("pmap_release: pmap resident count %ld != 0",
2217 pmap->pm_stats.resident_count));
2218 KASSERT(vm_radix_is_empty(&pmap->pm_root),
2219 ("pmap_release: pmap has reserved page table page(s)"));
2220 KASSERT(CPU_EMPTY(&pmap->pm_active),
2221 ("releasing active pmap %p", pmap));
2222
2223 pmap_qremove((vm_offset_t)pmap->pm_pdir, NPGPTD);
2224
2225 for (i = 0; i < NPGPTD; i++) {
2226 m = pmap->pm_ptdpg[i];
2227 #ifdef PMAP_PAE_COMP
2228 KASSERT(VM_PAGE_TO_PHYS(m) == (pmap->pm_pdpt[i] & PG_FRAME),
2229 ("pmap_release: got wrong ptd page"));
2230 #endif
2231 vm_page_unwire_noq(m);
2232 vm_page_free(m);
2233 }
2234 }
2235
2236 /*
2237 * grow the number of kernel page table entries, if needed
2238 */
2239 static int
__CONCAT(PMTYPE,growkernel)2240 __CONCAT(PMTYPE, growkernel)(vm_offset_t addr)
2241 {
2242 vm_paddr_t ptppaddr;
2243 vm_page_t nkpg;
2244 pd_entry_t newpdir;
2245
2246 mtx_assert(&kernel_map->system_mtx, MA_OWNED);
2247 addr = roundup2(addr, NBPDR);
2248 if (addr - 1 >= vm_map_max(kernel_map))
2249 addr = vm_map_max(kernel_map);
2250 while (kernel_vm_end < addr) {
2251 if (pdir_pde(PTD, kernel_vm_end)) {
2252 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK;
2253 if (kernel_vm_end - 1 >= vm_map_max(kernel_map)) {
2254 kernel_vm_end = vm_map_max(kernel_map);
2255 break;
2256 }
2257 continue;
2258 }
2259
2260 nkpg = vm_page_alloc_noobj(VM_ALLOC_INTERRUPT |
2261 VM_ALLOC_NOFREE | VM_ALLOC_WIRED | VM_ALLOC_ZERO);
2262 if (nkpg == NULL)
2263 return (KERN_RESOURCE_SHORTAGE);
2264 nkpg->pindex = kernel_vm_end >> PDRSHIFT;
2265 nkpt++;
2266
2267 ptppaddr = VM_PAGE_TO_PHYS(nkpg);
2268 newpdir = (pd_entry_t) (ptppaddr | PG_V | PG_RW | PG_A | PG_M);
2269 pdir_pde(KPTD, kernel_vm_end) = newpdir;
2270
2271 pmap_kenter_pde(kernel_vm_end, newpdir);
2272 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK;
2273 if (kernel_vm_end - 1 >= vm_map_max(kernel_map)) {
2274 kernel_vm_end = vm_map_max(kernel_map);
2275 break;
2276 }
2277 }
2278
2279 return (KERN_SUCCESS);
2280 }
2281
2282 /***************************************************
2283 * page management routines.
2284 ***************************************************/
2285
2286 static const uint32_t pc_freemask[_NPCM] = {
2287 [0 ... _NPCM - 2] = PC_FREEN,
2288 [_NPCM - 1] = PC_FREEL
2289 };
2290
2291 #ifdef PV_STATS
2292 extern int pc_chunk_count, pc_chunk_allocs, pc_chunk_frees, pc_chunk_tryfail;
2293 extern long pv_entry_frees, pv_entry_allocs;
2294 extern int pv_entry_spare;
2295 #endif
2296
2297 /*
2298 * We are in a serious low memory condition. Resort to
2299 * drastic measures to free some pages so we can allocate
2300 * another pv entry chunk.
2301 */
2302 static vm_page_t
pmap_pv_reclaim(pmap_t locked_pmap)2303 pmap_pv_reclaim(pmap_t locked_pmap)
2304 {
2305 struct pch newtail;
2306 struct pv_chunk *pc;
2307 struct md_page *pvh;
2308 pd_entry_t *pde;
2309 pmap_t pmap;
2310 pt_entry_t *pte, tpte;
2311 pv_entry_t pv;
2312 vm_offset_t va;
2313 vm_page_t m, m_pc;
2314 struct spglist free;
2315 uint32_t inuse;
2316 int bit, field, freed;
2317
2318 PMAP_LOCK_ASSERT(locked_pmap, MA_OWNED);
2319 pmap = NULL;
2320 m_pc = NULL;
2321 SLIST_INIT(&free);
2322 TAILQ_INIT(&newtail);
2323 while ((pc = TAILQ_FIRST(&pv_chunks)) != NULL && (pv_vafree == 0 ||
2324 SLIST_EMPTY(&free))) {
2325 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
2326 if (pmap != pc->pc_pmap) {
2327 if (pmap != NULL) {
2328 pmap_invalidate_all_int(pmap);
2329 if (pmap != locked_pmap)
2330 PMAP_UNLOCK(pmap);
2331 }
2332 pmap = pc->pc_pmap;
2333 /* Avoid deadlock and lock recursion. */
2334 if (pmap > locked_pmap)
2335 PMAP_LOCK(pmap);
2336 else if (pmap != locked_pmap && !PMAP_TRYLOCK(pmap)) {
2337 pmap = NULL;
2338 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru);
2339 continue;
2340 }
2341 }
2342
2343 /*
2344 * Destroy every non-wired, 4 KB page mapping in the chunk.
2345 */
2346 freed = 0;
2347 for (field = 0; field < _NPCM; field++) {
2348 for (inuse = ~pc->pc_map[field] & pc_freemask[field];
2349 inuse != 0; inuse &= ~(1UL << bit)) {
2350 bit = bsfl(inuse);
2351 pv = &pc->pc_pventry[field * 32 + bit];
2352 va = pv->pv_va;
2353 pde = pmap_pde(pmap, va);
2354 if ((*pde & PG_PS) != 0)
2355 continue;
2356 pte = __CONCAT(PMTYPE, pte)(pmap, va);
2357 tpte = *pte;
2358 if ((tpte & PG_W) == 0)
2359 tpte = pte_load_clear(pte);
2360 pmap_pte_release(pte);
2361 if ((tpte & PG_W) != 0)
2362 continue;
2363 KASSERT(tpte != 0,
2364 ("pmap_pv_reclaim: pmap %p va %x zero pte",
2365 pmap, va));
2366 if ((tpte & PG_G) != 0)
2367 pmap_invalidate_page_int(pmap, va);
2368 m = PHYS_TO_VM_PAGE(tpte & PG_FRAME);
2369 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
2370 vm_page_dirty(m);
2371 if ((tpte & PG_A) != 0)
2372 vm_page_aflag_set(m, PGA_REFERENCED);
2373 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
2374 if (TAILQ_EMPTY(&m->md.pv_list) &&
2375 (m->flags & PG_FICTITIOUS) == 0) {
2376 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
2377 if (TAILQ_EMPTY(&pvh->pv_list)) {
2378 vm_page_aflag_clear(m,
2379 PGA_WRITEABLE);
2380 }
2381 }
2382 pc->pc_map[field] |= 1UL << bit;
2383 pmap_unuse_pt(pmap, va, &free);
2384 freed++;
2385 }
2386 }
2387 if (freed == 0) {
2388 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru);
2389 continue;
2390 }
2391 /* Every freed mapping is for a 4 KB page. */
2392 pmap->pm_stats.resident_count -= freed;
2393 PV_STAT(pv_entry_frees += freed);
2394 PV_STAT(pv_entry_spare += freed);
2395 pv_entry_count -= freed;
2396 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2397 for (field = 0; field < _NPCM; field++)
2398 if (pc->pc_map[field] != pc_freemask[field]) {
2399 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc,
2400 pc_list);
2401 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru);
2402
2403 /*
2404 * One freed pv entry in locked_pmap is
2405 * sufficient.
2406 */
2407 if (pmap == locked_pmap)
2408 goto out;
2409 break;
2410 }
2411 if (field == _NPCM) {
2412 PV_STAT(pv_entry_spare -= _NPCPV);
2413 PV_STAT(pc_chunk_count--);
2414 PV_STAT(pc_chunk_frees++);
2415 /* Entire chunk is free; return it. */
2416 m_pc = PHYS_TO_VM_PAGE(pmap_kextract((vm_offset_t)pc));
2417 pmap_qremove((vm_offset_t)pc, 1);
2418 pmap_ptelist_free(&pv_vafree, (vm_offset_t)pc);
2419 break;
2420 }
2421 }
2422 out:
2423 TAILQ_CONCAT(&pv_chunks, &newtail, pc_lru);
2424 if (pmap != NULL) {
2425 pmap_invalidate_all_int(pmap);
2426 if (pmap != locked_pmap)
2427 PMAP_UNLOCK(pmap);
2428 }
2429 if (m_pc == NULL && pv_vafree != 0 && SLIST_EMPTY(&free)) {
2430 m_pc = SLIST_FIRST(&free);
2431 SLIST_REMOVE_HEAD(&free, plinks.s.ss);
2432 /* Recycle a freed page table page. */
2433 m_pc->ref_count = 1;
2434 }
2435 vm_page_free_pages_toq(&free, true);
2436 return (m_pc);
2437 }
2438
2439 /*
2440 * free the pv_entry back to the free list
2441 */
2442 static void
free_pv_entry(pmap_t pmap,pv_entry_t pv)2443 free_pv_entry(pmap_t pmap, pv_entry_t pv)
2444 {
2445 struct pv_chunk *pc;
2446 int idx, field, bit;
2447
2448 rw_assert(&pvh_global_lock, RA_WLOCKED);
2449 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2450 PV_STAT(pv_entry_frees++);
2451 PV_STAT(pv_entry_spare++);
2452 pv_entry_count--;
2453 pc = pv_to_chunk(pv);
2454 idx = pv - &pc->pc_pventry[0];
2455 field = idx / 32;
2456 bit = idx % 32;
2457 pc->pc_map[field] |= 1ul << bit;
2458 for (idx = 0; idx < _NPCM; idx++)
2459 if (pc->pc_map[idx] != pc_freemask[idx]) {
2460 /*
2461 * 98% of the time, pc is already at the head of the
2462 * list. If it isn't already, move it to the head.
2463 */
2464 if (__predict_false(TAILQ_FIRST(&pmap->pm_pvchunk) !=
2465 pc)) {
2466 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2467 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc,
2468 pc_list);
2469 }
2470 return;
2471 }
2472 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2473 free_pv_chunk(pc);
2474 }
2475
2476 static void
free_pv_chunk(struct pv_chunk * pc)2477 free_pv_chunk(struct pv_chunk *pc)
2478 {
2479 vm_page_t m;
2480
2481 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
2482 PV_STAT(pv_entry_spare -= _NPCPV);
2483 PV_STAT(pc_chunk_count--);
2484 PV_STAT(pc_chunk_frees++);
2485 /* entire chunk is free, return it */
2486 m = PHYS_TO_VM_PAGE(pmap_kextract((vm_offset_t)pc));
2487 pmap_qremove((vm_offset_t)pc, 1);
2488 vm_page_unwire_noq(m);
2489 vm_page_free(m);
2490 pmap_ptelist_free(&pv_vafree, (vm_offset_t)pc);
2491 }
2492
2493 /*
2494 * get a new pv_entry, allocating a block from the system
2495 * when needed.
2496 */
2497 static pv_entry_t
get_pv_entry(pmap_t pmap,bool try)2498 get_pv_entry(pmap_t pmap, bool try)
2499 {
2500 static const struct timeval printinterval = { 60, 0 };
2501 static struct timeval lastprint;
2502 int bit, field;
2503 pv_entry_t pv;
2504 struct pv_chunk *pc;
2505 vm_page_t m;
2506
2507 rw_assert(&pvh_global_lock, RA_WLOCKED);
2508 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2509 PV_STAT(pv_entry_allocs++);
2510 pv_entry_count++;
2511 if (pv_entry_count > pv_entry_high_water)
2512 if (ratecheck(&lastprint, &printinterval))
2513 printf("Approaching the limit on PV entries, consider "
2514 "increasing either the vm.pmap.shpgperproc or the "
2515 "vm.pmap.pv_entry_max tunable.\n");
2516 retry:
2517 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
2518 if (pc != NULL) {
2519 for (field = 0; field < _NPCM; field++) {
2520 if (pc->pc_map[field]) {
2521 bit = bsfl(pc->pc_map[field]);
2522 break;
2523 }
2524 }
2525 if (field < _NPCM) {
2526 pv = &pc->pc_pventry[field * 32 + bit];
2527 pc->pc_map[field] &= ~(1ul << bit);
2528 /* If this was the last item, move it to tail */
2529 for (field = 0; field < _NPCM; field++)
2530 if (pc->pc_map[field] != 0) {
2531 PV_STAT(pv_entry_spare--);
2532 return (pv); /* not full, return */
2533 }
2534 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2535 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
2536 PV_STAT(pv_entry_spare--);
2537 return (pv);
2538 }
2539 }
2540 /*
2541 * Access to the ptelist "pv_vafree" is synchronized by the pvh
2542 * global lock. If "pv_vafree" is currently non-empty, it will
2543 * remain non-empty until pmap_ptelist_alloc() completes.
2544 */
2545 if (pv_vafree == 0 ||
2546 (m = vm_page_alloc_noobj(VM_ALLOC_WIRED)) == NULL) {
2547 if (try) {
2548 pv_entry_count--;
2549 PV_STAT(pc_chunk_tryfail++);
2550 return (NULL);
2551 }
2552 m = pmap_pv_reclaim(pmap);
2553 if (m == NULL)
2554 goto retry;
2555 }
2556 PV_STAT(pc_chunk_count++);
2557 PV_STAT(pc_chunk_allocs++);
2558 pc = (struct pv_chunk *)pmap_ptelist_alloc(&pv_vafree);
2559 pmap_qenter((vm_offset_t)pc, &m, 1);
2560 pc->pc_pmap = pmap;
2561 pc->pc_map[0] = pc_freemask[0] & ~1ul; /* preallocated bit 0 */
2562 for (field = 1; field < _NPCM; field++)
2563 pc->pc_map[field] = pc_freemask[field];
2564 TAILQ_INSERT_TAIL(&pv_chunks, pc, pc_lru);
2565 pv = &pc->pc_pventry[0];
2566 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
2567 PV_STAT(pv_entry_spare += _NPCPV - 1);
2568 return (pv);
2569 }
2570
2571 static __inline pv_entry_t
pmap_pvh_remove(struct md_page * pvh,pmap_t pmap,vm_offset_t va)2572 pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
2573 {
2574 pv_entry_t pv;
2575
2576 rw_assert(&pvh_global_lock, RA_WLOCKED);
2577 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
2578 if (pmap == PV_PMAP(pv) && va == pv->pv_va) {
2579 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
2580 break;
2581 }
2582 }
2583 return (pv);
2584 }
2585
2586 static void
pmap_pv_demote_pde(pmap_t pmap,vm_offset_t va,vm_paddr_t pa)2587 pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa)
2588 {
2589 struct md_page *pvh;
2590 pv_entry_t pv;
2591 vm_offset_t va_last;
2592 vm_page_t m;
2593
2594 rw_assert(&pvh_global_lock, RA_WLOCKED);
2595 KASSERT((pa & PDRMASK) == 0,
2596 ("pmap_pv_demote_pde: pa is not 4mpage aligned"));
2597
2598 /*
2599 * Transfer the 4mpage's pv entry for this mapping to the first
2600 * page's pv list.
2601 */
2602 pvh = pa_to_pvh(pa);
2603 va = trunc_4mpage(va);
2604 pv = pmap_pvh_remove(pvh, pmap, va);
2605 KASSERT(pv != NULL, ("pmap_pv_demote_pde: pv not found"));
2606 m = PHYS_TO_VM_PAGE(pa);
2607 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2608 /* Instantiate the remaining NPTEPG - 1 pv entries. */
2609 va_last = va + NBPDR - PAGE_SIZE;
2610 do {
2611 m++;
2612 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2613 ("pmap_pv_demote_pde: page %p is not managed", m));
2614 va += PAGE_SIZE;
2615 pmap_insert_entry(pmap, va, m);
2616 } while (va < va_last);
2617 }
2618
2619 #if VM_NRESERVLEVEL > 0
2620 static void
pmap_pv_promote_pde(pmap_t pmap,vm_offset_t va,vm_paddr_t pa)2621 pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa)
2622 {
2623 struct md_page *pvh;
2624 pv_entry_t pv;
2625 vm_offset_t va_last;
2626 vm_page_t m;
2627
2628 rw_assert(&pvh_global_lock, RA_WLOCKED);
2629 KASSERT((pa & PDRMASK) == 0,
2630 ("pmap_pv_promote_pde: pa is not 4mpage aligned"));
2631
2632 /*
2633 * Transfer the first page's pv entry for this mapping to the
2634 * 4mpage's pv list. Aside from avoiding the cost of a call
2635 * to get_pv_entry(), a transfer avoids the possibility that
2636 * get_pv_entry() calls pmap_collect() and that pmap_collect()
2637 * removes one of the mappings that is being promoted.
2638 */
2639 m = PHYS_TO_VM_PAGE(pa);
2640 va = trunc_4mpage(va);
2641 pv = pmap_pvh_remove(&m->md, pmap, va);
2642 KASSERT(pv != NULL, ("pmap_pv_promote_pde: pv not found"));
2643 pvh = pa_to_pvh(pa);
2644 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
2645 /* Free the remaining NPTEPG - 1 pv entries. */
2646 va_last = va + NBPDR - PAGE_SIZE;
2647 do {
2648 m++;
2649 va += PAGE_SIZE;
2650 pmap_pvh_free(&m->md, pmap, va);
2651 } while (va < va_last);
2652 }
2653 #endif /* VM_NRESERVLEVEL > 0 */
2654
2655 static void
pmap_pvh_free(struct md_page * pvh,pmap_t pmap,vm_offset_t va)2656 pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
2657 {
2658 pv_entry_t pv;
2659
2660 pv = pmap_pvh_remove(pvh, pmap, va);
2661 KASSERT(pv != NULL, ("pmap_pvh_free: pv not found"));
2662 free_pv_entry(pmap, pv);
2663 }
2664
2665 static void
pmap_remove_entry(pmap_t pmap,vm_page_t m,vm_offset_t va)2666 pmap_remove_entry(pmap_t pmap, vm_page_t m, vm_offset_t va)
2667 {
2668 struct md_page *pvh;
2669
2670 rw_assert(&pvh_global_lock, RA_WLOCKED);
2671 pmap_pvh_free(&m->md, pmap, va);
2672 if (TAILQ_EMPTY(&m->md.pv_list) && (m->flags & PG_FICTITIOUS) == 0) {
2673 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
2674 if (TAILQ_EMPTY(&pvh->pv_list))
2675 vm_page_aflag_clear(m, PGA_WRITEABLE);
2676 }
2677 }
2678
2679 /*
2680 * Create a pv entry for page at pa for
2681 * (pmap, va).
2682 */
2683 static void
pmap_insert_entry(pmap_t pmap,vm_offset_t va,vm_page_t m)2684 pmap_insert_entry(pmap_t pmap, vm_offset_t va, vm_page_t m)
2685 {
2686 pv_entry_t pv;
2687
2688 rw_assert(&pvh_global_lock, RA_WLOCKED);
2689 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2690 pv = get_pv_entry(pmap, false);
2691 pv->pv_va = va;
2692 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2693 }
2694
2695 /*
2696 * Conditionally create a pv entry.
2697 */
2698 static bool
pmap_try_insert_pv_entry(pmap_t pmap,vm_offset_t va,vm_page_t m)2699 pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, vm_page_t m)
2700 {
2701 pv_entry_t pv;
2702
2703 rw_assert(&pvh_global_lock, RA_WLOCKED);
2704 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2705 if (pv_entry_count < pv_entry_high_water &&
2706 (pv = get_pv_entry(pmap, true)) != NULL) {
2707 pv->pv_va = va;
2708 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2709 return (true);
2710 } else
2711 return (false);
2712 }
2713
2714 /*
2715 * Create the pv entries for each of the pages within a superpage.
2716 */
2717 static bool
pmap_pv_insert_pde(pmap_t pmap,vm_offset_t va,pd_entry_t pde,u_int flags)2718 pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, pd_entry_t pde, u_int flags)
2719 {
2720 struct md_page *pvh;
2721 pv_entry_t pv;
2722 bool noreclaim;
2723
2724 rw_assert(&pvh_global_lock, RA_WLOCKED);
2725 noreclaim = (flags & PMAP_ENTER_NORECLAIM) != 0;
2726 if ((noreclaim && pv_entry_count >= pv_entry_high_water) ||
2727 (pv = get_pv_entry(pmap, noreclaim)) == NULL)
2728 return (false);
2729 pv->pv_va = va;
2730 pvh = pa_to_pvh(pde & PG_PS_FRAME);
2731 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
2732 return (true);
2733 }
2734
2735 /*
2736 * Fills a page table page with mappings to consecutive physical pages.
2737 */
2738 static void
pmap_fill_ptp(pt_entry_t * firstpte,pt_entry_t newpte)2739 pmap_fill_ptp(pt_entry_t *firstpte, pt_entry_t newpte)
2740 {
2741 pt_entry_t *pte;
2742
2743 for (pte = firstpte; pte < firstpte + NPTEPG; pte++) {
2744 *pte = newpte;
2745 newpte += PAGE_SIZE;
2746 }
2747 }
2748
2749 /*
2750 * Tries to demote a 2- or 4MB page mapping. If demotion fails, the
2751 * 2- or 4MB page mapping is invalidated.
2752 */
2753 static bool
pmap_demote_pde(pmap_t pmap,pd_entry_t * pde,vm_offset_t va)2754 pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va)
2755 {
2756 pd_entry_t newpde, oldpde;
2757 pt_entry_t *firstpte, newpte;
2758 vm_paddr_t mptepa;
2759 vm_page_t mpte;
2760 struct spglist free;
2761 vm_offset_t sva;
2762
2763 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2764 oldpde = *pde;
2765 KASSERT((oldpde & (PG_PS | PG_V)) == (PG_PS | PG_V),
2766 ("pmap_demote_pde: oldpde is missing PG_PS and/or PG_V"));
2767 if ((oldpde & PG_A) == 0 || (mpte = pmap_remove_pt_page(pmap, va)) ==
2768 NULL) {
2769 KASSERT((oldpde & PG_W) == 0,
2770 ("pmap_demote_pde: page table page for a wired mapping"
2771 " is missing"));
2772
2773 /*
2774 * Invalidate the 2- or 4MB page mapping and return
2775 * "failure" if the mapping was never accessed or the
2776 * allocation of the new page table page fails.
2777 */
2778 if ((oldpde & PG_A) == 0 ||
2779 (mpte = vm_page_alloc_noobj(VM_ALLOC_WIRED)) == NULL) {
2780 SLIST_INIT(&free);
2781 sva = trunc_4mpage(va);
2782 pmap_remove_pde(pmap, pde, sva, &free);
2783 if ((oldpde & PG_G) == 0)
2784 pmap_invalidate_pde_page(pmap, sva, oldpde);
2785 vm_page_free_pages_toq(&free, true);
2786 CTR2(KTR_PMAP, "pmap_demote_pde: failure for va %#x"
2787 " in pmap %p", va, pmap);
2788 return (false);
2789 }
2790 mpte->pindex = va >> PDRSHIFT;
2791 if (pmap != kernel_pmap) {
2792 mpte->ref_count = NPTEPG;
2793 pmap->pm_stats.resident_count++;
2794 }
2795 }
2796 mptepa = VM_PAGE_TO_PHYS(mpte);
2797
2798 /*
2799 * If the page mapping is in the kernel's address space, then the
2800 * KPTmap can provide access to the page table page. Otherwise,
2801 * temporarily map the page table page (mpte) into the kernel's
2802 * address space at either PADDR1 or PADDR2.
2803 */
2804 if (pmap == kernel_pmap)
2805 firstpte = &KPTmap[i386_btop(trunc_4mpage(va))];
2806 else if (curthread->td_pinned > 0 && rw_wowned(&pvh_global_lock)) {
2807 if ((*PMAP1 & PG_FRAME) != mptepa) {
2808 *PMAP1 = mptepa | PG_RW | PG_V | PG_A | PG_M;
2809 #ifdef SMP
2810 PMAP1cpu = PCPU_GET(cpuid);
2811 #endif
2812 invlcaddr(PADDR1);
2813 PMAP1changed++;
2814 } else
2815 #ifdef SMP
2816 if (PMAP1cpu != PCPU_GET(cpuid)) {
2817 PMAP1cpu = PCPU_GET(cpuid);
2818 invlcaddr(PADDR1);
2819 PMAP1changedcpu++;
2820 } else
2821 #endif
2822 PMAP1unchanged++;
2823 firstpte = PADDR1;
2824 } else {
2825 mtx_lock(&PMAP2mutex);
2826 if ((*PMAP2 & PG_FRAME) != mptepa) {
2827 *PMAP2 = mptepa | PG_RW | PG_V | PG_A | PG_M;
2828 pmap_invalidate_page_int(kernel_pmap,
2829 (vm_offset_t)PADDR2);
2830 }
2831 firstpte = PADDR2;
2832 }
2833 newpde = mptepa | PG_M | PG_A | (oldpde & PG_U) | PG_RW | PG_V;
2834 KASSERT((oldpde & PG_A) != 0,
2835 ("pmap_demote_pde: oldpde is missing PG_A"));
2836 KASSERT((oldpde & (PG_M | PG_RW)) != PG_RW,
2837 ("pmap_demote_pde: oldpde is missing PG_M"));
2838 newpte = oldpde & ~PG_PS;
2839 if ((newpte & PG_PDE_PAT) != 0)
2840 newpte ^= PG_PDE_PAT | PG_PTE_PAT;
2841
2842 /*
2843 * If the PTP is not leftover from an earlier promotion or it does not
2844 * have PG_A set in every PTE, then fill it. The new PTEs will all
2845 * have PG_A set.
2846 */
2847 if (!vm_page_all_valid(mpte))
2848 pmap_fill_ptp(firstpte, newpte);
2849
2850 KASSERT((*firstpte & PG_FRAME) == (newpte & PG_FRAME),
2851 ("pmap_demote_pde: firstpte and newpte map different physical"
2852 " addresses"));
2853
2854 /*
2855 * If the mapping has changed attributes, update the PTEs.
2856 */
2857 if ((*firstpte & PG_PTE_PROMOTE) != (newpte & PG_PTE_PROMOTE))
2858 pmap_fill_ptp(firstpte, newpte);
2859
2860 /*
2861 * Demote the mapping. This pmap is locked. The old PDE has
2862 * PG_A set. If the old PDE has PG_RW set, it also has PG_M
2863 * set. Thus, there is no danger of a race with another
2864 * processor changing the setting of PG_A and/or PG_M between
2865 * the read above and the store below.
2866 */
2867 if (workaround_erratum383)
2868 pmap_update_pde(pmap, va, pde, newpde);
2869 else if (pmap == kernel_pmap)
2870 pmap_kenter_pde(va, newpde);
2871 else
2872 pde_store(pde, newpde);
2873 if (firstpte == PADDR2)
2874 mtx_unlock(&PMAP2mutex);
2875
2876 /*
2877 * Invalidate the recursive mapping of the page table page.
2878 */
2879 pmap_invalidate_page_int(pmap, (vm_offset_t)vtopte(va));
2880
2881 /*
2882 * Demote the pv entry. This depends on the earlier demotion
2883 * of the mapping. Specifically, the (re)creation of a per-
2884 * page pv entry might trigger the execution of pmap_collect(),
2885 * which might reclaim a newly (re)created per-page pv entry
2886 * and destroy the associated mapping. In order to destroy
2887 * the mapping, the PDE must have already changed from mapping
2888 * the 2mpage to referencing the page table page.
2889 */
2890 if ((oldpde & PG_MANAGED) != 0)
2891 pmap_pv_demote_pde(pmap, va, oldpde & PG_PS_FRAME);
2892
2893 pmap_pde_demotions++;
2894 CTR2(KTR_PMAP, "pmap_demote_pde: success for va %#x"
2895 " in pmap %p", va, pmap);
2896 return (true);
2897 }
2898
2899 /*
2900 * Removes a 2- or 4MB page mapping from the kernel pmap.
2901 */
2902 static void
pmap_remove_kernel_pde(pmap_t pmap,pd_entry_t * pde,vm_offset_t va)2903 pmap_remove_kernel_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va)
2904 {
2905 pd_entry_t newpde;
2906 vm_paddr_t mptepa;
2907 vm_page_t mpte;
2908
2909 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2910 mpte = pmap_remove_pt_page(pmap, va);
2911 if (mpte == NULL)
2912 panic("pmap_remove_kernel_pde: Missing pt page.");
2913
2914 mptepa = VM_PAGE_TO_PHYS(mpte);
2915 newpde = mptepa | PG_M | PG_A | PG_RW | PG_V;
2916
2917 /*
2918 * If this page table page was unmapped by a promotion, then it
2919 * contains valid mappings. Zero it to invalidate those mappings.
2920 */
2921 if (vm_page_any_valid(mpte))
2922 pagezero((void *)&KPTmap[i386_btop(trunc_4mpage(va))]);
2923
2924 /*
2925 * Remove the mapping.
2926 */
2927 if (workaround_erratum383)
2928 pmap_update_pde(pmap, va, pde, newpde);
2929 else
2930 pmap_kenter_pde(va, newpde);
2931
2932 /*
2933 * Invalidate the recursive mapping of the page table page.
2934 */
2935 pmap_invalidate_page_int(pmap, (vm_offset_t)vtopte(va));
2936 }
2937
2938 /*
2939 * pmap_remove_pde: do the things to unmap a superpage in a process
2940 */
2941 static void
pmap_remove_pde(pmap_t pmap,pd_entry_t * pdq,vm_offset_t sva,struct spglist * free)2942 pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva,
2943 struct spglist *free)
2944 {
2945 struct md_page *pvh;
2946 pd_entry_t oldpde;
2947 vm_offset_t eva, va;
2948 vm_page_t m, mpte;
2949
2950 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2951 KASSERT((sva & PDRMASK) == 0,
2952 ("pmap_remove_pde: sva is not 4mpage aligned"));
2953 oldpde = pte_load_clear(pdq);
2954 if (oldpde & PG_W)
2955 pmap->pm_stats.wired_count -= NBPDR / PAGE_SIZE;
2956
2957 /*
2958 * Machines that don't support invlpg, also don't support
2959 * PG_G.
2960 */
2961 if ((oldpde & PG_G) != 0)
2962 pmap_invalidate_pde_page(kernel_pmap, sva, oldpde);
2963
2964 pmap->pm_stats.resident_count -= NBPDR / PAGE_SIZE;
2965 if (oldpde & PG_MANAGED) {
2966 pvh = pa_to_pvh(oldpde & PG_PS_FRAME);
2967 pmap_pvh_free(pvh, pmap, sva);
2968 eva = sva + NBPDR;
2969 for (va = sva, m = PHYS_TO_VM_PAGE(oldpde & PG_PS_FRAME);
2970 va < eva; va += PAGE_SIZE, m++) {
2971 if ((oldpde & (PG_M | PG_RW)) == (PG_M | PG_RW))
2972 vm_page_dirty(m);
2973 if (oldpde & PG_A)
2974 vm_page_aflag_set(m, PGA_REFERENCED);
2975 if (TAILQ_EMPTY(&m->md.pv_list) &&
2976 TAILQ_EMPTY(&pvh->pv_list))
2977 vm_page_aflag_clear(m, PGA_WRITEABLE);
2978 }
2979 }
2980 if (pmap == kernel_pmap) {
2981 pmap_remove_kernel_pde(pmap, pdq, sva);
2982 } else {
2983 mpte = pmap_remove_pt_page(pmap, sva);
2984 if (mpte != NULL) {
2985 KASSERT(vm_page_any_valid(mpte),
2986 ("pmap_remove_pde: pte page not promoted"));
2987 pmap->pm_stats.resident_count--;
2988 KASSERT(mpte->ref_count == NPTEPG,
2989 ("pmap_remove_pde: pte page ref count error"));
2990 mpte->ref_count = 0;
2991 pmap_add_delayed_free_list(mpte, free, false);
2992 }
2993 }
2994 }
2995
2996 /*
2997 * pmap_remove_pte: do the things to unmap a page in a process
2998 */
2999 static int
pmap_remove_pte(pmap_t pmap,pt_entry_t * ptq,vm_offset_t va,struct spglist * free)3000 pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t va,
3001 struct spglist *free)
3002 {
3003 pt_entry_t oldpte;
3004 vm_page_t m;
3005
3006 rw_assert(&pvh_global_lock, RA_WLOCKED);
3007 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3008 oldpte = pte_load_clear(ptq);
3009 KASSERT(oldpte != 0,
3010 ("pmap_remove_pte: pmap %p va %x zero pte", pmap, va));
3011 if (oldpte & PG_W)
3012 pmap->pm_stats.wired_count -= 1;
3013 /*
3014 * Machines that don't support invlpg, also don't support
3015 * PG_G.
3016 */
3017 if (oldpte & PG_G)
3018 pmap_invalidate_page_int(kernel_pmap, va);
3019 pmap->pm_stats.resident_count -= 1;
3020 if (oldpte & PG_MANAGED) {
3021 m = PHYS_TO_VM_PAGE(oldpte & PG_FRAME);
3022 if ((oldpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
3023 vm_page_dirty(m);
3024 if (oldpte & PG_A)
3025 vm_page_aflag_set(m, PGA_REFERENCED);
3026 pmap_remove_entry(pmap, m, va);
3027 }
3028 return (pmap_unuse_pt(pmap, va, free));
3029 }
3030
3031 /*
3032 * Remove a single page from a process address space
3033 */
3034 static void
pmap_remove_page(pmap_t pmap,vm_offset_t va,struct spglist * free)3035 pmap_remove_page(pmap_t pmap, vm_offset_t va, struct spglist *free)
3036 {
3037 pt_entry_t *pte;
3038
3039 rw_assert(&pvh_global_lock, RA_WLOCKED);
3040 KASSERT(curthread->td_pinned > 0, ("curthread not pinned"));
3041 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3042 if ((pte = pmap_pte_quick(pmap, va)) == NULL || *pte == 0)
3043 return;
3044 pmap_remove_pte(pmap, pte, va, free);
3045 pmap_invalidate_page_int(pmap, va);
3046 }
3047
3048 /*
3049 * Removes the specified range of addresses from the page table page.
3050 */
3051 static bool
pmap_remove_ptes(pmap_t pmap,vm_offset_t sva,vm_offset_t eva,struct spglist * free)3052 pmap_remove_ptes(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
3053 struct spglist *free)
3054 {
3055 pt_entry_t *pte;
3056 bool anyvalid;
3057
3058 rw_assert(&pvh_global_lock, RA_WLOCKED);
3059 KASSERT(curthread->td_pinned > 0, ("curthread not pinned"));
3060 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3061 anyvalid = false;
3062 for (pte = pmap_pte_quick(pmap, sva); sva != eva; pte++,
3063 sva += PAGE_SIZE) {
3064 if (*pte == 0)
3065 continue;
3066
3067 /*
3068 * The TLB entry for a PG_G mapping is invalidated by
3069 * pmap_remove_pte().
3070 */
3071 if ((*pte & PG_G) == 0)
3072 anyvalid = true;
3073
3074 if (pmap_remove_pte(pmap, pte, sva, free))
3075 break;
3076 }
3077 return (anyvalid);
3078 }
3079
3080 /*
3081 * Remove the given range of addresses from the specified map.
3082 *
3083 * It is assumed that the start and end are properly
3084 * rounded to the page size.
3085 */
3086 static void
__CONCAT(PMTYPE,remove)3087 __CONCAT(PMTYPE, remove)(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
3088 {
3089 vm_offset_t pdnxt;
3090 pd_entry_t ptpaddr;
3091 struct spglist free;
3092 int anyvalid;
3093
3094 /*
3095 * Perform an unsynchronized read. This is, however, safe.
3096 */
3097 if (pmap->pm_stats.resident_count == 0)
3098 return;
3099
3100 anyvalid = 0;
3101 SLIST_INIT(&free);
3102
3103 rw_wlock(&pvh_global_lock);
3104 sched_pin();
3105 PMAP_LOCK(pmap);
3106
3107 /*
3108 * special handling of removing one page. a very
3109 * common operation and easy to short circuit some
3110 * code.
3111 */
3112 if ((sva + PAGE_SIZE == eva) &&
3113 ((pmap->pm_pdir[(sva >> PDRSHIFT)] & PG_PS) == 0)) {
3114 pmap_remove_page(pmap, sva, &free);
3115 goto out;
3116 }
3117
3118 for (; sva < eva; sva = pdnxt) {
3119 u_int pdirindex;
3120
3121 /*
3122 * Calculate index for next page table.
3123 */
3124 pdnxt = (sva + NBPDR) & ~PDRMASK;
3125 if (pdnxt < sva)
3126 pdnxt = eva;
3127 if (pmap->pm_stats.resident_count == 0)
3128 break;
3129
3130 pdirindex = sva >> PDRSHIFT;
3131 ptpaddr = pmap->pm_pdir[pdirindex];
3132
3133 /*
3134 * Weed out invalid mappings. Note: we assume that the page
3135 * directory table is always allocated, and in kernel virtual.
3136 */
3137 if (ptpaddr == 0)
3138 continue;
3139
3140 /*
3141 * Check for large page.
3142 */
3143 if ((ptpaddr & PG_PS) != 0) {
3144 /*
3145 * Are we removing the entire large page? If not,
3146 * demote the mapping and fall through.
3147 */
3148 if (sva + NBPDR == pdnxt && eva >= pdnxt) {
3149 /*
3150 * The TLB entry for a PG_G mapping is
3151 * invalidated by pmap_remove_pde().
3152 */
3153 if ((ptpaddr & PG_G) == 0)
3154 anyvalid = 1;
3155 pmap_remove_pde(pmap,
3156 &pmap->pm_pdir[pdirindex], sva, &free);
3157 continue;
3158 } else if (!pmap_demote_pde(pmap,
3159 &pmap->pm_pdir[pdirindex], sva)) {
3160 /* The large page mapping was destroyed. */
3161 continue;
3162 }
3163 }
3164
3165 /*
3166 * Limit our scan to either the end of the va represented
3167 * by the current page table page, or to the end of the
3168 * range being removed.
3169 */
3170 if (pdnxt > eva)
3171 pdnxt = eva;
3172
3173 if (pmap_remove_ptes(pmap, sva, pdnxt, &free))
3174 anyvalid = 1;
3175 }
3176 out:
3177 sched_unpin();
3178 if (anyvalid)
3179 pmap_invalidate_all_int(pmap);
3180 rw_wunlock(&pvh_global_lock);
3181 PMAP_UNLOCK(pmap);
3182 vm_page_free_pages_toq(&free, true);
3183 }
3184
3185 /*
3186 * Routine: pmap_remove_all
3187 * Function:
3188 * Removes this physical page from
3189 * all physical maps in which it resides.
3190 * Reflects back modify bits to the pager.
3191 *
3192 * Notes:
3193 * Original versions of this routine were very
3194 * inefficient because they iteratively called
3195 * pmap_remove (slow...)
3196 */
3197
3198 static void
__CONCAT(PMTYPE,remove_all)3199 __CONCAT(PMTYPE, remove_all)(vm_page_t m)
3200 {
3201 struct md_page *pvh;
3202 pv_entry_t pv;
3203 pmap_t pmap;
3204 pt_entry_t *pte, tpte;
3205 pd_entry_t *pde;
3206 vm_offset_t va;
3207 struct spglist free;
3208
3209 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3210 ("pmap_remove_all: page %p is not managed", m));
3211 SLIST_INIT(&free);
3212 rw_wlock(&pvh_global_lock);
3213 sched_pin();
3214 if ((m->flags & PG_FICTITIOUS) != 0)
3215 goto small_mappings;
3216 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
3217 while ((pv = TAILQ_FIRST(&pvh->pv_list)) != NULL) {
3218 va = pv->pv_va;
3219 pmap = PV_PMAP(pv);
3220 PMAP_LOCK(pmap);
3221 pde = pmap_pde(pmap, va);
3222 (void)pmap_demote_pde(pmap, pde, va);
3223 PMAP_UNLOCK(pmap);
3224 }
3225 small_mappings:
3226 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) {
3227 pmap = PV_PMAP(pv);
3228 PMAP_LOCK(pmap);
3229 pmap->pm_stats.resident_count--;
3230 pde = pmap_pde(pmap, pv->pv_va);
3231 KASSERT((*pde & PG_PS) == 0, ("pmap_remove_all: found"
3232 " a 4mpage in page %p's pv list", m));
3233 pte = pmap_pte_quick(pmap, pv->pv_va);
3234 tpte = pte_load_clear(pte);
3235 KASSERT(tpte != 0, ("pmap_remove_all: pmap %p va %x zero pte",
3236 pmap, pv->pv_va));
3237 if (tpte & PG_W)
3238 pmap->pm_stats.wired_count--;
3239 if (tpte & PG_A)
3240 vm_page_aflag_set(m, PGA_REFERENCED);
3241
3242 /*
3243 * Update the vm_page_t clean and reference bits.
3244 */
3245 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
3246 vm_page_dirty(m);
3247 pmap_unuse_pt(pmap, pv->pv_va, &free);
3248 pmap_invalidate_page_int(pmap, pv->pv_va);
3249 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
3250 free_pv_entry(pmap, pv);
3251 PMAP_UNLOCK(pmap);
3252 }
3253 vm_page_aflag_clear(m, PGA_WRITEABLE);
3254 sched_unpin();
3255 rw_wunlock(&pvh_global_lock);
3256 vm_page_free_pages_toq(&free, true);
3257 }
3258
3259 /*
3260 * pmap_protect_pde: do the things to protect a 4mpage in a process
3261 */
3262 static bool
pmap_protect_pde(pmap_t pmap,pd_entry_t * pde,vm_offset_t sva,vm_prot_t prot)3263 pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva, vm_prot_t prot)
3264 {
3265 pd_entry_t newpde, oldpde;
3266 vm_page_t m, mt;
3267 bool anychanged;
3268
3269 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3270 KASSERT((sva & PDRMASK) == 0,
3271 ("pmap_protect_pde: sva is not 4mpage aligned"));
3272 anychanged = false;
3273 retry:
3274 oldpde = newpde = *pde;
3275 if ((prot & VM_PROT_WRITE) == 0) {
3276 if ((oldpde & (PG_MANAGED | PG_M | PG_RW)) ==
3277 (PG_MANAGED | PG_M | PG_RW)) {
3278 m = PHYS_TO_VM_PAGE(oldpde & PG_PS_FRAME);
3279 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
3280 vm_page_dirty(mt);
3281 }
3282 newpde &= ~(PG_RW | PG_M);
3283 }
3284 #ifdef PMAP_PAE_COMP
3285 if ((prot & VM_PROT_EXECUTE) == 0 && !i386_read_exec)
3286 newpde |= pg_nx;
3287 #endif
3288 if (newpde != oldpde) {
3289 /*
3290 * As an optimization to future operations on this PDE, clear
3291 * PG_PROMOTED. The impending invalidation will remove any
3292 * lingering 4KB page mappings from the TLB.
3293 */
3294 if (!pde_cmpset(pde, oldpde, newpde & ~PG_PROMOTED))
3295 goto retry;
3296 if ((oldpde & PG_G) != 0)
3297 pmap_invalidate_pde_page(kernel_pmap, sva, oldpde);
3298 else
3299 anychanged = true;
3300 }
3301 return (anychanged);
3302 }
3303
3304 /*
3305 * Set the physical protection on the
3306 * specified range of this map as requested.
3307 */
3308 static void
__CONCAT(PMTYPE,protect)3309 __CONCAT(PMTYPE, protect)(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
3310 vm_prot_t prot)
3311 {
3312 vm_offset_t pdnxt;
3313 pd_entry_t ptpaddr;
3314 pt_entry_t *pte;
3315 bool anychanged, pv_lists_locked;
3316
3317 KASSERT((prot & ~VM_PROT_ALL) == 0, ("invalid prot %x", prot));
3318 if (prot == VM_PROT_NONE) {
3319 pmap_remove(pmap, sva, eva);
3320 return;
3321 }
3322
3323 #ifdef PMAP_PAE_COMP
3324 if ((prot & (VM_PROT_WRITE | VM_PROT_EXECUTE)) ==
3325 (VM_PROT_WRITE | VM_PROT_EXECUTE))
3326 return;
3327 #else
3328 if (prot & VM_PROT_WRITE)
3329 return;
3330 #endif
3331
3332 if (pmap_is_current(pmap))
3333 pv_lists_locked = false;
3334 else {
3335 pv_lists_locked = true;
3336 resume:
3337 rw_wlock(&pvh_global_lock);
3338 sched_pin();
3339 }
3340 anychanged = false;
3341
3342 PMAP_LOCK(pmap);
3343 for (; sva < eva; sva = pdnxt) {
3344 pt_entry_t obits, pbits;
3345 u_int pdirindex;
3346
3347 pdnxt = (sva + NBPDR) & ~PDRMASK;
3348 if (pdnxt < sva)
3349 pdnxt = eva;
3350
3351 pdirindex = sva >> PDRSHIFT;
3352 ptpaddr = pmap->pm_pdir[pdirindex];
3353
3354 /*
3355 * Weed out invalid mappings. Note: we assume that the page
3356 * directory table is always allocated, and in kernel virtual.
3357 */
3358 if (ptpaddr == 0)
3359 continue;
3360
3361 /*
3362 * Check for large page.
3363 */
3364 if ((ptpaddr & PG_PS) != 0) {
3365 /*
3366 * Are we protecting the entire large page? If not,
3367 * demote the mapping and fall through.
3368 */
3369 if (sva + NBPDR == pdnxt && eva >= pdnxt) {
3370 /*
3371 * The TLB entry for a PG_G mapping is
3372 * invalidated by pmap_protect_pde().
3373 */
3374 if (pmap_protect_pde(pmap,
3375 &pmap->pm_pdir[pdirindex], sva, prot))
3376 anychanged = true;
3377 continue;
3378 } else {
3379 if (!pv_lists_locked) {
3380 pv_lists_locked = true;
3381 if (!rw_try_wlock(&pvh_global_lock)) {
3382 if (anychanged)
3383 pmap_invalidate_all_int(
3384 pmap);
3385 PMAP_UNLOCK(pmap);
3386 goto resume;
3387 }
3388 sched_pin();
3389 }
3390 if (!pmap_demote_pde(pmap,
3391 &pmap->pm_pdir[pdirindex], sva)) {
3392 /*
3393 * The large page mapping was
3394 * destroyed.
3395 */
3396 continue;
3397 }
3398 }
3399 }
3400
3401 if (pdnxt > eva)
3402 pdnxt = eva;
3403
3404 for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++,
3405 sva += PAGE_SIZE) {
3406 vm_page_t m;
3407
3408 retry:
3409 /*
3410 * Regardless of whether a pte is 32 or 64 bits in
3411 * size, PG_RW, PG_A, and PG_M are among the least
3412 * significant 32 bits.
3413 */
3414 obits = pbits = *pte;
3415 if ((pbits & PG_V) == 0)
3416 continue;
3417
3418 if ((prot & VM_PROT_WRITE) == 0) {
3419 if ((pbits & (PG_MANAGED | PG_M | PG_RW)) ==
3420 (PG_MANAGED | PG_M | PG_RW)) {
3421 m = PHYS_TO_VM_PAGE(pbits & PG_FRAME);
3422 vm_page_dirty(m);
3423 }
3424 pbits &= ~(PG_RW | PG_M);
3425 }
3426 #ifdef PMAP_PAE_COMP
3427 if ((prot & VM_PROT_EXECUTE) == 0 && !i386_read_exec)
3428 pbits |= pg_nx;
3429 #endif
3430
3431 if (pbits != obits) {
3432 #ifdef PMAP_PAE_COMP
3433 if (!atomic_cmpset_64(pte, obits, pbits))
3434 goto retry;
3435 #else
3436 if (!atomic_cmpset_int((u_int *)pte, obits,
3437 pbits))
3438 goto retry;
3439 #endif
3440 if (obits & PG_G)
3441 pmap_invalidate_page_int(pmap, sva);
3442 else
3443 anychanged = true;
3444 }
3445 }
3446 }
3447 if (anychanged)
3448 pmap_invalidate_all_int(pmap);
3449 if (pv_lists_locked) {
3450 sched_unpin();
3451 rw_wunlock(&pvh_global_lock);
3452 }
3453 PMAP_UNLOCK(pmap);
3454 }
3455
3456 #if VM_NRESERVLEVEL > 0
3457 /*
3458 * Tries to promote the 512 or 1024, contiguous 4KB page mappings that are
3459 * within a single page table page (PTP) to a single 2- or 4MB page mapping.
3460 * For promotion to occur, two conditions must be met: (1) the 4KB page
3461 * mappings must map aligned, contiguous physical memory and (2) the 4KB page
3462 * mappings must have identical characteristics.
3463 *
3464 * Managed (PG_MANAGED) mappings within the kernel address space are not
3465 * promoted. The reason is that kernel PDEs are replicated in each pmap but
3466 * pmap_clear_ptes() and pmap_ts_referenced() only read the PDE from the kernel
3467 * pmap.
3468 */
3469 static bool
pmap_promote_pde(pmap_t pmap,pd_entry_t * pde,vm_offset_t va,vm_page_t mpte)3470 pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va, vm_page_t mpte)
3471 {
3472 pd_entry_t newpde;
3473 pt_entry_t allpte_PG_A, *firstpte, oldpte, pa, *pte;
3474 #ifdef KTR
3475 vm_offset_t oldpteva;
3476 #endif
3477
3478 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3479 if (!pg_ps_enabled)
3480 return (false);
3481
3482 /*
3483 * Examine the first PTE in the specified PTP. Abort if this PTE is
3484 * either invalid or does not map the first 4KB physical page
3485 * within a 2- or 4MB page.
3486 */
3487 firstpte = pmap_pte_quick(pmap, trunc_4mpage(va));
3488 setpde:
3489 newpde = *firstpte;
3490 if ((newpde & ((PG_FRAME & PDRMASK) | PG_V)) != PG_V) {
3491 pmap_pde_p_failures++;
3492 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x"
3493 " in pmap %p", va, pmap);
3494 return (false);
3495 }
3496 if ((*firstpte & PG_MANAGED) != 0 && pmap == kernel_pmap) {
3497 pmap_pde_p_failures++;
3498 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x"
3499 " in pmap %p", va, pmap);
3500 return (false);
3501 }
3502
3503 /*
3504 * Both here and in the below "for" loop, to allow for repromotion
3505 * after MADV_FREE, conditionally write protect a clean PTE before
3506 * possibly aborting the promotion due to other PTE attributes. Why?
3507 * Suppose that MADV_FREE is applied to a part of a superpage, the
3508 * address range [S, E). pmap_advise() will demote the superpage
3509 * mapping, destroy the 4KB page mapping at the end of [S, E), and
3510 * clear PG_M and PG_A in the PTEs for the rest of [S, E). Later,
3511 * imagine that the memory in [S, E) is recycled, but the last 4KB
3512 * page in [S, E) is not the last to be rewritten, or simply accessed.
3513 * In other words, there is still a 4KB page in [S, E), call it P,
3514 * that is writeable but PG_M and PG_A are clear in P's PTE. Unless
3515 * we write protect P before aborting the promotion, if and when P is
3516 * finally rewritten, there won't be a page fault to trigger
3517 * repromotion.
3518 */
3519 if ((newpde & (PG_M | PG_RW)) == PG_RW) {
3520 /*
3521 * When PG_M is already clear, PG_RW can be cleared without
3522 * a TLB invalidation.
3523 */
3524 if (!atomic_cmpset_int((u_int *)firstpte, newpde, newpde &
3525 ~PG_RW))
3526 goto setpde;
3527 newpde &= ~PG_RW;
3528 CTR2(KTR_PMAP, "pmap_promote_pde: protect for va %#lx"
3529 " in pmap %p", va & ~PDRMASK, pmap);
3530 }
3531
3532 /*
3533 * Examine each of the other PTEs in the specified PTP. Abort if this
3534 * PTE maps an unexpected 4KB physical page or does not have identical
3535 * characteristics to the first PTE.
3536 */
3537 allpte_PG_A = newpde & PG_A;
3538 pa = (newpde & (PG_PS_FRAME | PG_V)) + NBPDR - PAGE_SIZE;
3539 for (pte = firstpte + NPTEPG - 1; pte > firstpte; pte--) {
3540 setpte:
3541 oldpte = *pte;
3542 if ((oldpte & (PG_FRAME | PG_V)) != pa) {
3543 pmap_pde_p_failures++;
3544 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x"
3545 " in pmap %p", va, pmap);
3546 return (false);
3547 }
3548 if ((oldpte & (PG_M | PG_RW)) == PG_RW) {
3549 /*
3550 * When PG_M is already clear, PG_RW can be cleared
3551 * without a TLB invalidation.
3552 */
3553 if (!atomic_cmpset_int((u_int *)pte, oldpte,
3554 oldpte & ~PG_RW))
3555 goto setpte;
3556 oldpte &= ~PG_RW;
3557 #ifdef KTR
3558 oldpteva = (oldpte & PG_FRAME & PDRMASK) |
3559 (va & ~PDRMASK);
3560 #endif
3561 CTR2(KTR_PMAP, "pmap_promote_pde: protect for va %#x"
3562 " in pmap %p", oldpteva, pmap);
3563 }
3564 if ((oldpte & PG_PTE_PROMOTE) != (newpde & PG_PTE_PROMOTE)) {
3565 pmap_pde_p_failures++;
3566 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x"
3567 " in pmap %p", va, pmap);
3568 return (false);
3569 }
3570 allpte_PG_A &= oldpte;
3571 pa -= PAGE_SIZE;
3572 }
3573
3574 /*
3575 * Unless all PTEs have PG_A set, clear it from the superpage mapping,
3576 * so that promotions triggered by speculative mappings, such as
3577 * pmap_enter_quick(), don't automatically mark the underlying pages
3578 * as referenced.
3579 */
3580 newpde &= ~PG_A | allpte_PG_A;
3581
3582 /*
3583 * Save the PTP in its current state until the PDE mapping the
3584 * superpage is demoted by pmap_demote_pde() or destroyed by
3585 * pmap_remove_pde(). If PG_A is not set in every PTE, then request
3586 * that the PTP be refilled on demotion.
3587 */
3588 if (mpte == NULL)
3589 mpte = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
3590 KASSERT(mpte >= vm_page_array &&
3591 mpte < &vm_page_array[vm_page_array_size],
3592 ("pmap_promote_pde: page table page is out of range"));
3593 KASSERT(mpte->pindex == va >> PDRSHIFT,
3594 ("pmap_promote_pde: page table page's pindex is wrong"));
3595 if (pmap_insert_pt_page(pmap, mpte, true, allpte_PG_A != 0)) {
3596 pmap_pde_p_failures++;
3597 CTR2(KTR_PMAP,
3598 "pmap_promote_pde: failure for va %#x in pmap %p", va,
3599 pmap);
3600 return (false);
3601 }
3602
3603 /*
3604 * Promote the pv entries.
3605 */
3606 if ((newpde & PG_MANAGED) != 0)
3607 pmap_pv_promote_pde(pmap, va, newpde & PG_PS_FRAME);
3608
3609 /*
3610 * Propagate the PAT index to its proper position.
3611 */
3612 if ((newpde & PG_PTE_PAT) != 0)
3613 newpde ^= PG_PDE_PAT | PG_PTE_PAT;
3614
3615 /*
3616 * Map the superpage.
3617 */
3618 if (workaround_erratum383)
3619 pmap_update_pde(pmap, va, pde, PG_PS | newpde);
3620 else if (pmap == kernel_pmap)
3621 pmap_kenter_pde(va, PG_PROMOTED | PG_PS | newpde);
3622 else
3623 pde_store(pde, PG_PROMOTED | PG_PS | newpde);
3624
3625 pmap_pde_promotions++;
3626 CTR2(KTR_PMAP, "pmap_promote_pde: success for va %#x"
3627 " in pmap %p", va, pmap);
3628 return (true);
3629 }
3630 #endif /* VM_NRESERVLEVEL > 0 */
3631
3632 /*
3633 * Insert the given physical page (p) at
3634 * the specified virtual address (v) in the
3635 * target physical map with the protection requested.
3636 *
3637 * If specified, the page will be wired down, meaning
3638 * that the related pte can not be reclaimed.
3639 *
3640 * NB: This is the only routine which MAY NOT lazy-evaluate
3641 * or lose information. That is, this routine must actually
3642 * insert this page into the given map NOW.
3643 */
3644 static int
__CONCAT(PMTYPE,enter)3645 __CONCAT(PMTYPE, enter)(pmap_t pmap, vm_offset_t va, vm_page_t m,
3646 vm_prot_t prot, u_int flags, int8_t psind)
3647 {
3648 pd_entry_t *pde;
3649 pt_entry_t *pte;
3650 pt_entry_t newpte, origpte;
3651 pv_entry_t pv;
3652 vm_paddr_t opa, pa;
3653 vm_page_t mpte, om;
3654 int rv;
3655
3656 va = trunc_page(va);
3657 KASSERT((pmap == kernel_pmap && va < VM_MAX_KERNEL_ADDRESS) ||
3658 (pmap != kernel_pmap && va < VM_MAXUSER_ADDRESS),
3659 ("pmap_enter: toobig k%d %#x", pmap == kernel_pmap, va));
3660 KASSERT(va < PMAP_TRM_MIN_ADDRESS,
3661 ("pmap_enter: invalid to pmap_enter into trampoline (va: 0x%x)",
3662 va));
3663 KASSERT(pmap != kernel_pmap || (m->oflags & VPO_UNMANAGED) != 0 ||
3664 !VA_IS_CLEANMAP(va),
3665 ("pmap_enter: managed mapping within the clean submap"));
3666 if ((m->oflags & VPO_UNMANAGED) == 0)
3667 VM_PAGE_OBJECT_BUSY_ASSERT(m);
3668 KASSERT((flags & PMAP_ENTER_RESERVED) == 0,
3669 ("pmap_enter: flags %u has reserved bits set", flags));
3670 pa = VM_PAGE_TO_PHYS(m);
3671 newpte = (pt_entry_t)(pa | PG_A | PG_V);
3672 if ((flags & VM_PROT_WRITE) != 0)
3673 newpte |= PG_M;
3674 if ((prot & VM_PROT_WRITE) != 0)
3675 newpte |= PG_RW;
3676 KASSERT((newpte & (PG_M | PG_RW)) != PG_M,
3677 ("pmap_enter: flags includes VM_PROT_WRITE but prot doesn't"));
3678 #ifdef PMAP_PAE_COMP
3679 if ((prot & VM_PROT_EXECUTE) == 0 && !i386_read_exec)
3680 newpte |= pg_nx;
3681 #endif
3682 if ((flags & PMAP_ENTER_WIRED) != 0)
3683 newpte |= PG_W;
3684 if (pmap != kernel_pmap)
3685 newpte |= PG_U;
3686 newpte |= pmap_cache_bits(pmap, m->md.pat_mode, psind > 0);
3687 if ((m->oflags & VPO_UNMANAGED) == 0)
3688 newpte |= PG_MANAGED;
3689
3690 rw_wlock(&pvh_global_lock);
3691 PMAP_LOCK(pmap);
3692 sched_pin();
3693 if (psind == 1) {
3694 /* Assert the required virtual and physical alignment. */
3695 KASSERT((va & PDRMASK) == 0, ("pmap_enter: va unaligned"));
3696 KASSERT(m->psind > 0, ("pmap_enter: m->psind < psind"));
3697 rv = pmap_enter_pde(pmap, va, newpte | PG_PS, flags, m);
3698 goto out;
3699 }
3700
3701 pde = pmap_pde(pmap, va);
3702 if (pmap != kernel_pmap) {
3703 /*
3704 * va is for UVA.
3705 * In the case that a page table page is not resident,
3706 * we are creating it here. pmap_allocpte() handles
3707 * demotion.
3708 */
3709 mpte = pmap_allocpte(pmap, va, flags);
3710 if (mpte == NULL) {
3711 KASSERT((flags & PMAP_ENTER_NOSLEEP) != 0,
3712 ("pmap_allocpte failed with sleep allowed"));
3713 rv = KERN_RESOURCE_SHORTAGE;
3714 goto out;
3715 }
3716 } else {
3717 /*
3718 * va is for KVA, so pmap_demote_pde() will never fail
3719 * to install a page table page. PG_V is also
3720 * asserted by pmap_demote_pde().
3721 */
3722 mpte = NULL;
3723 KASSERT(pde != NULL && (*pde & PG_V) != 0,
3724 ("KVA %#x invalid pde pdir %#jx", va,
3725 (uintmax_t)pmap->pm_pdir[PTDPTDI]));
3726 if ((*pde & PG_PS) != 0)
3727 pmap_demote_pde(pmap, pde, va);
3728 }
3729 pte = pmap_pte_quick(pmap, va);
3730
3731 /*
3732 * Page Directory table entry is not valid, which should not
3733 * happen. We should have either allocated the page table
3734 * page or demoted the existing mapping above.
3735 */
3736 if (pte == NULL) {
3737 panic("pmap_enter: invalid page directory pdir=%#jx, va=%#x",
3738 (uintmax_t)pmap->pm_pdir[PTDPTDI], va);
3739 }
3740
3741 origpte = *pte;
3742 pv = NULL;
3743
3744 /*
3745 * Is the specified virtual address already mapped?
3746 */
3747 if ((origpte & PG_V) != 0) {
3748 /*
3749 * Wiring change, just update stats. We don't worry about
3750 * wiring PT pages as they remain resident as long as there
3751 * are valid mappings in them. Hence, if a user page is wired,
3752 * the PT page will be also.
3753 */
3754 if ((newpte & PG_W) != 0 && (origpte & PG_W) == 0)
3755 pmap->pm_stats.wired_count++;
3756 else if ((newpte & PG_W) == 0 && (origpte & PG_W) != 0)
3757 pmap->pm_stats.wired_count--;
3758
3759 /*
3760 * Remove the extra PT page reference.
3761 */
3762 if (mpte != NULL) {
3763 mpte->ref_count--;
3764 KASSERT(mpte->ref_count > 0,
3765 ("pmap_enter: missing reference to page table page,"
3766 " va: 0x%x", va));
3767 }
3768
3769 /*
3770 * Has the physical page changed?
3771 */
3772 opa = origpte & PG_FRAME;
3773 if (opa == pa) {
3774 /*
3775 * No, might be a protection or wiring change.
3776 */
3777 if ((origpte & PG_MANAGED) != 0 &&
3778 (newpte & PG_RW) != 0)
3779 vm_page_aflag_set(m, PGA_WRITEABLE);
3780 if (((origpte ^ newpte) & ~(PG_M | PG_A)) == 0)
3781 goto unchanged;
3782 goto validate;
3783 }
3784
3785 /*
3786 * The physical page has changed. Temporarily invalidate
3787 * the mapping. This ensures that all threads sharing the
3788 * pmap keep a consistent view of the mapping, which is
3789 * necessary for the correct handling of COW faults. It
3790 * also permits reuse of the old mapping's PV entry,
3791 * avoiding an allocation.
3792 *
3793 * For consistency, handle unmanaged mappings the same way.
3794 */
3795 origpte = pte_load_clear(pte);
3796 KASSERT((origpte & PG_FRAME) == opa,
3797 ("pmap_enter: unexpected pa update for %#x", va));
3798 if ((origpte & PG_MANAGED) != 0) {
3799 om = PHYS_TO_VM_PAGE(opa);
3800
3801 /*
3802 * The pmap lock is sufficient to synchronize with
3803 * concurrent calls to pmap_page_test_mappings() and
3804 * pmap_ts_referenced().
3805 */
3806 if ((origpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
3807 vm_page_dirty(om);
3808 if ((origpte & PG_A) != 0) {
3809 pmap_invalidate_page_int(pmap, va);
3810 vm_page_aflag_set(om, PGA_REFERENCED);
3811 }
3812 pv = pmap_pvh_remove(&om->md, pmap, va);
3813 KASSERT(pv != NULL,
3814 ("pmap_enter: no PV entry for %#x", va));
3815 if ((newpte & PG_MANAGED) == 0)
3816 free_pv_entry(pmap, pv);
3817 if ((om->a.flags & PGA_WRITEABLE) != 0 &&
3818 TAILQ_EMPTY(&om->md.pv_list) &&
3819 ((om->flags & PG_FICTITIOUS) != 0 ||
3820 TAILQ_EMPTY(&pa_to_pvh(opa)->pv_list)))
3821 vm_page_aflag_clear(om, PGA_WRITEABLE);
3822 } else {
3823 /*
3824 * Since this mapping is unmanaged, assume that PG_A
3825 * is set.
3826 */
3827 pmap_invalidate_page_int(pmap, va);
3828 }
3829 origpte = 0;
3830 } else {
3831 /*
3832 * Increment the counters.
3833 */
3834 if ((newpte & PG_W) != 0)
3835 pmap->pm_stats.wired_count++;
3836 pmap->pm_stats.resident_count++;
3837 }
3838
3839 /*
3840 * Enter on the PV list if part of our managed memory.
3841 */
3842 if ((newpte & PG_MANAGED) != 0) {
3843 if (pv == NULL) {
3844 pv = get_pv_entry(pmap, false);
3845 pv->pv_va = va;
3846 }
3847 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
3848 if ((newpte & PG_RW) != 0)
3849 vm_page_aflag_set(m, PGA_WRITEABLE);
3850 }
3851
3852 /*
3853 * Update the PTE.
3854 */
3855 if ((origpte & PG_V) != 0) {
3856 validate:
3857 origpte = pte_load_store(pte, newpte);
3858 KASSERT((origpte & PG_FRAME) == pa,
3859 ("pmap_enter: unexpected pa update for %#x", va));
3860 if ((newpte & PG_M) == 0 && (origpte & (PG_M | PG_RW)) ==
3861 (PG_M | PG_RW)) {
3862 if ((origpte & PG_MANAGED) != 0)
3863 vm_page_dirty(m);
3864
3865 /*
3866 * Although the PTE may still have PG_RW set, TLB
3867 * invalidation may nonetheless be required because
3868 * the PTE no longer has PG_M set.
3869 */
3870 }
3871 #ifdef PMAP_PAE_COMP
3872 else if ((origpte & PG_NX) != 0 || (newpte & PG_NX) == 0) {
3873 /*
3874 * This PTE change does not require TLB invalidation.
3875 */
3876 goto unchanged;
3877 }
3878 #endif
3879 if ((origpte & PG_A) != 0)
3880 pmap_invalidate_page_int(pmap, va);
3881 } else
3882 pte_store_zero(pte, newpte);
3883
3884 unchanged:
3885
3886 #if VM_NRESERVLEVEL > 0
3887 /*
3888 * If both the page table page and the reservation are fully
3889 * populated, then attempt promotion.
3890 */
3891 if ((mpte == NULL || mpte->ref_count == NPTEPG) &&
3892 (m->flags & PG_FICTITIOUS) == 0 &&
3893 vm_reserv_level_iffullpop(m) == 0)
3894 (void)pmap_promote_pde(pmap, pde, va, mpte);
3895 #endif
3896
3897 rv = KERN_SUCCESS;
3898 out:
3899 sched_unpin();
3900 rw_wunlock(&pvh_global_lock);
3901 PMAP_UNLOCK(pmap);
3902 return (rv);
3903 }
3904
3905 /*
3906 * Tries to create a read- and/or execute-only 2 or 4 MB page mapping. Returns
3907 * KERN_SUCCESS if the mapping was created. Otherwise, returns an error
3908 * value. See pmap_enter_pde() for the possible error values when "no sleep",
3909 * "no replace", and "no reclaim" are specified.
3910 */
3911 static int
pmap_enter_4mpage(pmap_t pmap,vm_offset_t va,vm_page_t m,vm_prot_t prot)3912 pmap_enter_4mpage(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
3913 {
3914 pd_entry_t newpde;
3915
3916 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3917 newpde = VM_PAGE_TO_PHYS(m) |
3918 pmap_cache_bits(pmap, m->md.pat_mode, true) | PG_PS | PG_V;
3919 if ((m->oflags & VPO_UNMANAGED) == 0)
3920 newpde |= PG_MANAGED;
3921 #ifdef PMAP_PAE_COMP
3922 if ((prot & VM_PROT_EXECUTE) == 0 && !i386_read_exec)
3923 newpde |= pg_nx;
3924 #endif
3925 if (pmap != kernel_pmap)
3926 newpde |= PG_U;
3927 return (pmap_enter_pde(pmap, va, newpde, PMAP_ENTER_NOSLEEP |
3928 PMAP_ENTER_NOREPLACE | PMAP_ENTER_NORECLAIM, NULL));
3929 }
3930
3931 /*
3932 * Returns true if every page table entry in the page table page that maps
3933 * the specified kernel virtual address is zero.
3934 */
3935 static bool
pmap_every_pte_zero(vm_offset_t va)3936 pmap_every_pte_zero(vm_offset_t va)
3937 {
3938 pt_entry_t *pt_end, *pte;
3939
3940 KASSERT((va & PDRMASK) == 0, ("va is misaligned"));
3941 pte = vtopte(va);
3942 for (pt_end = pte + NPTEPG; pte < pt_end; pte++) {
3943 if (*pte != 0)
3944 return (false);
3945 }
3946 return (true);
3947 }
3948
3949 /*
3950 * Tries to create the specified 2 or 4 MB page mapping. Returns KERN_SUCCESS
3951 * if the mapping was created, and one of KERN_FAILURE, KERN_NO_SPACE,
3952 * or KERN_RESOURCE_SHORTAGE otherwise. Returns KERN_FAILURE if
3953 * PMAP_ENTER_NOREPLACE was specified and a 4 KB page mapping already exists
3954 * within the 2 or 4 MB virtual address range starting at the specified virtual
3955 * address. Returns KERN_NO_SPACE if PMAP_ENTER_NOREPLACE was specified and a
3956 * 2 or 4 MB page mapping already exists at the specified virtual address.
3957 * Returns KERN_RESOURCE_SHORTAGE if PMAP_ENTER_NORECLAIM was specified and a
3958 * PV entry allocation failed.
3959 *
3960 * The parameter "m" is only used when creating a managed, writeable mapping.
3961 */
3962 static int
pmap_enter_pde(pmap_t pmap,vm_offset_t va,pd_entry_t newpde,u_int flags,vm_page_t m)3963 pmap_enter_pde(pmap_t pmap, vm_offset_t va, pd_entry_t newpde, u_int flags,
3964 vm_page_t m)
3965 {
3966 struct spglist free;
3967 pd_entry_t oldpde, *pde;
3968 vm_page_t mt;
3969 vm_page_t uwptpg;
3970
3971 rw_assert(&pvh_global_lock, RA_WLOCKED);
3972 KASSERT((newpde & (PG_M | PG_RW)) != PG_RW,
3973 ("pmap_enter_pde: newpde is missing PG_M"));
3974 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3975 pde = pmap_pde(pmap, va);
3976 oldpde = *pde;
3977 if ((oldpde & PG_V) != 0) {
3978 if ((flags & PMAP_ENTER_NOREPLACE) != 0) {
3979 if ((oldpde & PG_PS) != 0) {
3980 CTR2(KTR_PMAP,
3981 "pmap_enter_pde: no space for va %#lx"
3982 " in pmap %p", va, pmap);
3983 return (KERN_NO_SPACE);
3984 } else if (pmap != kernel_pmap ||
3985 !pmap_every_pte_zero(va)) {
3986 CTR2(KTR_PMAP,
3987 "pmap_enter_pde: failure for va %#lx"
3988 " in pmap %p", va, pmap);
3989 return (KERN_FAILURE);
3990 }
3991 }
3992 /* Break the existing mapping(s). */
3993 SLIST_INIT(&free);
3994 if ((oldpde & PG_PS) != 0) {
3995 /*
3996 * If the PDE resulted from a promotion, then a
3997 * reserved PT page could be freed.
3998 */
3999 (void)pmap_remove_pde(pmap, pde, va, &free);
4000 if ((oldpde & PG_G) == 0)
4001 pmap_invalidate_pde_page(pmap, va, oldpde);
4002 } else {
4003 if (pmap_remove_ptes(pmap, va, va + NBPDR, &free))
4004 pmap_invalidate_all_int(pmap);
4005 }
4006 if (pmap != kernel_pmap) {
4007 vm_page_free_pages_toq(&free, true);
4008 KASSERT(*pde == 0, ("pmap_enter_pde: non-zero pde %p",
4009 pde));
4010 } else {
4011 KASSERT(SLIST_EMPTY(&free),
4012 ("pmap_enter_pde: freed kernel page table page"));
4013
4014 /*
4015 * Both pmap_remove_pde() and pmap_remove_ptes() will
4016 * leave the kernel page table page zero filled.
4017 */
4018 mt = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
4019 if (pmap_insert_pt_page(pmap, mt, false, false))
4020 panic("pmap_enter_pde: trie insert failed");
4021 }
4022 }
4023
4024 /*
4025 * Allocate a leaf ptpage for wired userspace pages.
4026 */
4027 uwptpg = NULL;
4028 if ((newpde & PG_W) != 0 && pmap != kernel_pmap) {
4029 uwptpg = vm_page_alloc_noobj(VM_ALLOC_WIRED);
4030 if (uwptpg == NULL) {
4031 return (KERN_RESOURCE_SHORTAGE);
4032 }
4033 uwptpg->pindex = va >> PDRSHIFT;
4034 if (pmap_insert_pt_page(pmap, uwptpg, true, false)) {
4035 vm_page_unwire_noq(uwptpg);
4036 vm_page_free(uwptpg);
4037 return (KERN_RESOURCE_SHORTAGE);
4038 }
4039 pmap->pm_stats.resident_count++;
4040 uwptpg->ref_count = NPTEPG;
4041 }
4042 if ((newpde & PG_MANAGED) != 0) {
4043 /*
4044 * Abort this mapping if its PV entry could not be created.
4045 */
4046 if (!pmap_pv_insert_pde(pmap, va, newpde, flags)) {
4047 if (uwptpg != NULL) {
4048 mt = pmap_remove_pt_page(pmap, va);
4049 KASSERT(mt == uwptpg,
4050 ("removed pt page %p, expected %p", mt,
4051 uwptpg));
4052 pmap->pm_stats.resident_count--;
4053 uwptpg->ref_count = 1;
4054 vm_page_unwire_noq(uwptpg);
4055 vm_page_free(uwptpg);
4056 }
4057 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
4058 " in pmap %p", va, pmap);
4059 return (KERN_RESOURCE_SHORTAGE);
4060 }
4061 if ((newpde & PG_RW) != 0) {
4062 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
4063 vm_page_aflag_set(mt, PGA_WRITEABLE);
4064 }
4065 }
4066
4067 /*
4068 * Increment counters.
4069 */
4070 if ((newpde & PG_W) != 0)
4071 pmap->pm_stats.wired_count += NBPDR / PAGE_SIZE;
4072 pmap->pm_stats.resident_count += NBPDR / PAGE_SIZE;
4073
4074 /*
4075 * Map the superpage. (This is not a promoted mapping; there will not
4076 * be any lingering 4KB page mappings in the TLB.)
4077 */
4078 pde_store(pde, newpde);
4079
4080 pmap_pde_mappings++;
4081 CTR2(KTR_PMAP, "pmap_enter_pde: success for va %#lx in pmap %p",
4082 va, pmap);
4083 return (KERN_SUCCESS);
4084 }
4085
4086 /*
4087 * Maps a sequence of resident pages belonging to the same object.
4088 * The sequence begins with the given page m_start. This page is
4089 * mapped at the given virtual address start. Each subsequent page is
4090 * mapped at a virtual address that is offset from start by the same
4091 * amount as the page is offset from m_start within the object. The
4092 * last page in the sequence is the page with the largest offset from
4093 * m_start that can be mapped at a virtual address less than the given
4094 * virtual address end. Not every virtual page between start and end
4095 * is mapped; only those for which a resident page exists with the
4096 * corresponding offset from m_start are mapped.
4097 */
4098 static void
__CONCAT(PMTYPE,enter_object)4099 __CONCAT(PMTYPE, enter_object)(pmap_t pmap, vm_offset_t start, vm_offset_t end,
4100 vm_page_t m_start, vm_prot_t prot)
4101 {
4102 struct pctrie_iter pages;
4103 vm_offset_t va;
4104 vm_page_t m, mpte;
4105 int rv;
4106
4107 VM_OBJECT_ASSERT_LOCKED(m_start->object);
4108
4109 mpte = NULL;
4110 vm_page_iter_limit_init(&pages, m_start->object,
4111 m_start->pindex + atop(end - start));
4112 m = vm_radix_iter_lookup(&pages, m_start->pindex);
4113 rw_wlock(&pvh_global_lock);
4114 PMAP_LOCK(pmap);
4115 while (m != NULL) {
4116 va = start + ptoa(m->pindex - m_start->pindex);
4117 if ((va & PDRMASK) == 0 && va + NBPDR <= end &&
4118 m->psind == 1 && pg_ps_enabled &&
4119 ((rv = pmap_enter_4mpage(pmap, va, m, prot)) ==
4120 KERN_SUCCESS || rv == KERN_NO_SPACE)) {
4121 m = vm_radix_iter_jump(&pages, NBPDR / PAGE_SIZE);
4122 } else {
4123 mpte = pmap_enter_quick_locked(pmap, va, m, prot, mpte);
4124 m = vm_radix_iter_step(&pages);
4125 }
4126 }
4127 rw_wunlock(&pvh_global_lock);
4128 PMAP_UNLOCK(pmap);
4129 }
4130
4131 /*
4132 * this code makes some *MAJOR* assumptions:
4133 * 1. Current pmap & pmap exists.
4134 * 2. Not wired.
4135 * 3. Read access.
4136 * 4. No page table pages.
4137 * but is *MUCH* faster than pmap_enter...
4138 */
4139
4140 static void
__CONCAT(PMTYPE,enter_quick)4141 __CONCAT(PMTYPE, enter_quick)(pmap_t pmap, vm_offset_t va, vm_page_t m,
4142 vm_prot_t prot)
4143 {
4144
4145 rw_wlock(&pvh_global_lock);
4146 PMAP_LOCK(pmap);
4147 (void)pmap_enter_quick_locked(pmap, va, m, prot, NULL);
4148 rw_wunlock(&pvh_global_lock);
4149 PMAP_UNLOCK(pmap);
4150 }
4151
4152 static vm_page_t
pmap_enter_quick_locked(pmap_t pmap,vm_offset_t va,vm_page_t m,vm_prot_t prot,vm_page_t mpte)4153 pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, vm_page_t m,
4154 vm_prot_t prot, vm_page_t mpte)
4155 {
4156 pt_entry_t newpte, *pte;
4157 pd_entry_t *pde;
4158
4159 KASSERT(pmap != kernel_pmap || !VA_IS_CLEANMAP(va) ||
4160 (m->oflags & VPO_UNMANAGED) != 0,
4161 ("pmap_enter_quick_locked: managed mapping within the clean submap"));
4162 rw_assert(&pvh_global_lock, RA_WLOCKED);
4163 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
4164 pde = NULL;
4165
4166 /*
4167 * In the case that a page table page is not
4168 * resident, we are creating it here.
4169 */
4170 if (pmap != kernel_pmap) {
4171 u_int ptepindex;
4172 pd_entry_t ptepa;
4173
4174 /*
4175 * Calculate pagetable page index
4176 */
4177 ptepindex = va >> PDRSHIFT;
4178 if (mpte && (mpte->pindex == ptepindex)) {
4179 mpte->ref_count++;
4180 } else {
4181 /*
4182 * Get the page directory entry
4183 */
4184 pde = &pmap->pm_pdir[ptepindex];
4185 ptepa = *pde;
4186
4187 /*
4188 * If the page table page is mapped, we just increment
4189 * the hold count, and activate it.
4190 */
4191 if (ptepa) {
4192 if (ptepa & PG_PS)
4193 return (NULL);
4194 mpte = PHYS_TO_VM_PAGE(ptepa & PG_FRAME);
4195 mpte->ref_count++;
4196 } else {
4197 mpte = _pmap_allocpte(pmap, ptepindex,
4198 PMAP_ENTER_NOSLEEP);
4199 if (mpte == NULL)
4200 return (mpte);
4201 }
4202 }
4203 } else {
4204 mpte = NULL;
4205 }
4206
4207 sched_pin();
4208 pte = pmap_pte_quick(pmap, va);
4209 if (*pte) {
4210 if (mpte != NULL)
4211 mpte->ref_count--;
4212 sched_unpin();
4213 return (NULL);
4214 }
4215
4216 /*
4217 * Enter on the PV list if part of our managed memory.
4218 */
4219 if ((m->oflags & VPO_UNMANAGED) == 0 &&
4220 !pmap_try_insert_pv_entry(pmap, va, m)) {
4221 if (mpte != NULL)
4222 pmap_abort_ptp(pmap, va, mpte);
4223 sched_unpin();
4224 return (NULL);
4225 }
4226
4227 /*
4228 * Increment counters
4229 */
4230 pmap->pm_stats.resident_count++;
4231
4232 newpte = VM_PAGE_TO_PHYS(m) | PG_V |
4233 pmap_cache_bits(pmap, m->md.pat_mode, false);
4234 if ((m->oflags & VPO_UNMANAGED) == 0)
4235 newpte |= PG_MANAGED;
4236 #ifdef PMAP_PAE_COMP
4237 if ((prot & VM_PROT_EXECUTE) == 0 && !i386_read_exec)
4238 newpte |= pg_nx;
4239 #endif
4240 if (pmap != kernel_pmap)
4241 newpte |= PG_U;
4242 pte_store_zero(pte, newpte);
4243
4244 #if VM_NRESERVLEVEL > 0
4245 /*
4246 * If both the PTP and the reservation are fully populated, then
4247 * attempt promotion.
4248 */
4249 if ((prot & VM_PROT_NO_PROMOTE) == 0 &&
4250 (mpte == NULL || mpte->ref_count == NPTEPG) &&
4251 (m->flags & PG_FICTITIOUS) == 0 &&
4252 vm_reserv_level_iffullpop(m) == 0) {
4253 if (pde == NULL)
4254 pde = pmap_pde(pmap, va);
4255
4256 /*
4257 * If promotion succeeds, then the next call to this function
4258 * should not be given the unmapped PTP as a hint.
4259 */
4260 if (pmap_promote_pde(pmap, pde, va, mpte))
4261 mpte = NULL;
4262 }
4263 #endif
4264
4265 sched_unpin();
4266 return (mpte);
4267 }
4268
4269 /*
4270 * Make a temporary mapping for a physical address. This is only intended
4271 * to be used for panic dumps.
4272 */
4273 static void *
__CONCAT(PMTYPE,kenter_temporary)4274 __CONCAT(PMTYPE, kenter_temporary)(vm_paddr_t pa, int i)
4275 {
4276 vm_offset_t va;
4277
4278 va = (vm_offset_t)crashdumpmap + (i * PAGE_SIZE);
4279 pmap_kenter(va, pa);
4280 invlpg(va);
4281 return ((void *)crashdumpmap);
4282 }
4283
4284 /*
4285 * This code maps large physical mmap regions into the
4286 * processor address space. Note that some shortcuts
4287 * are taken, but the code works.
4288 */
4289 static void
__CONCAT(PMTYPE,object_init_pt)4290 __CONCAT(PMTYPE, object_init_pt)(pmap_t pmap, vm_offset_t addr,
4291 vm_object_t object, vm_pindex_t pindex, vm_size_t size)
4292 {
4293 struct pctrie_iter pages;
4294 pd_entry_t *pde;
4295 vm_paddr_t pa, ptepa;
4296 vm_page_t p;
4297 int pat_mode;
4298
4299 VM_OBJECT_ASSERT_WLOCKED(object);
4300 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG,
4301 ("pmap_object_init_pt: non-device object"));
4302 if (pg_ps_enabled &&
4303 (addr & (NBPDR - 1)) == 0 && (size & (NBPDR - 1)) == 0) {
4304 if (!vm_object_populate(object, pindex, pindex + atop(size)))
4305 return;
4306 vm_page_iter_init(&pages, object);
4307 p = vm_radix_iter_lookup(&pages, pindex);
4308 KASSERT(vm_page_all_valid(p),
4309 ("pmap_object_init_pt: invalid page %p", p));
4310 pat_mode = p->md.pat_mode;
4311
4312 /*
4313 * Abort the mapping if the first page is not physically
4314 * aligned to a 2/4MB page boundary.
4315 */
4316 ptepa = VM_PAGE_TO_PHYS(p);
4317 if (ptepa & (NBPDR - 1))
4318 return;
4319
4320 /*
4321 * Skip the first page. Abort the mapping if the rest of
4322 * the pages are not physically contiguous or have differing
4323 * memory attributes.
4324 */
4325 for (pa = ptepa + PAGE_SIZE; pa < ptepa + size;
4326 pa += PAGE_SIZE) {
4327 p = vm_radix_iter_next(&pages);
4328 KASSERT(vm_page_all_valid(p),
4329 ("pmap_object_init_pt: invalid page %p", p));
4330 if (pa != VM_PAGE_TO_PHYS(p) ||
4331 pat_mode != p->md.pat_mode)
4332 return;
4333 }
4334
4335 /*
4336 * Map using 2/4MB pages. Since "ptepa" is 2/4M aligned and
4337 * "size" is a multiple of 2/4M, adding the PAT setting to
4338 * "pa" will not affect the termination of this loop.
4339 */
4340 PMAP_LOCK(pmap);
4341 for (pa = ptepa | pmap_cache_bits(pmap, pat_mode, true);
4342 pa < ptepa + size; pa += NBPDR) {
4343 pde = pmap_pde(pmap, addr);
4344 if (*pde == 0) {
4345 pde_store(pde, pa | PG_PS | PG_M | PG_A |
4346 PG_U | PG_RW | PG_V);
4347 pmap->pm_stats.resident_count += NBPDR /
4348 PAGE_SIZE;
4349 pmap_pde_mappings++;
4350 }
4351 /* Else continue on if the PDE is already valid. */
4352 addr += NBPDR;
4353 }
4354 PMAP_UNLOCK(pmap);
4355 }
4356 }
4357
4358 /*
4359 * Clear the wired attribute from the mappings for the specified range of
4360 * addresses in the given pmap. Every valid mapping within that range
4361 * must have the wired attribute set. In contrast, invalid mappings
4362 * cannot have the wired attribute set, so they are ignored.
4363 *
4364 * The wired attribute of the page table entry is not a hardware feature,
4365 * so there is no need to invalidate any TLB entries.
4366 */
4367 static void
__CONCAT(PMTYPE,unwire)4368 __CONCAT(PMTYPE, unwire)(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
4369 {
4370 vm_offset_t pdnxt;
4371 pd_entry_t *pde;
4372 pt_entry_t *pte;
4373 bool pv_lists_locked;
4374
4375 if (pmap_is_current(pmap))
4376 pv_lists_locked = false;
4377 else {
4378 pv_lists_locked = true;
4379 resume:
4380 rw_wlock(&pvh_global_lock);
4381 sched_pin();
4382 }
4383 PMAP_LOCK(pmap);
4384 for (; sva < eva; sva = pdnxt) {
4385 pdnxt = (sva + NBPDR) & ~PDRMASK;
4386 if (pdnxt < sva)
4387 pdnxt = eva;
4388 pde = pmap_pde(pmap, sva);
4389 if ((*pde & PG_V) == 0)
4390 continue;
4391 if ((*pde & PG_PS) != 0) {
4392 if ((*pde & PG_W) == 0)
4393 panic("pmap_unwire: pde %#jx is missing PG_W",
4394 (uintmax_t)*pde);
4395
4396 /*
4397 * Are we unwiring the entire large page? If not,
4398 * demote the mapping and fall through.
4399 */
4400 if (sva + NBPDR == pdnxt && eva >= pdnxt) {
4401 /*
4402 * Regardless of whether a pde (or pte) is 32
4403 * or 64 bits in size, PG_W is among the least
4404 * significant 32 bits.
4405 */
4406 atomic_clear_int((u_int *)pde, PG_W);
4407 pmap->pm_stats.wired_count -= NBPDR /
4408 PAGE_SIZE;
4409 continue;
4410 } else {
4411 if (!pv_lists_locked) {
4412 pv_lists_locked = true;
4413 if (!rw_try_wlock(&pvh_global_lock)) {
4414 PMAP_UNLOCK(pmap);
4415 /* Repeat sva. */
4416 goto resume;
4417 }
4418 sched_pin();
4419 }
4420 if (!pmap_demote_pde(pmap, pde, sva))
4421 panic("pmap_unwire: demotion failed");
4422 }
4423 }
4424 if (pdnxt > eva)
4425 pdnxt = eva;
4426 for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++,
4427 sva += PAGE_SIZE) {
4428 if ((*pte & PG_V) == 0)
4429 continue;
4430 if ((*pte & PG_W) == 0)
4431 panic("pmap_unwire: pte %#jx is missing PG_W",
4432 (uintmax_t)*pte);
4433
4434 /*
4435 * PG_W must be cleared atomically. Although the pmap
4436 * lock synchronizes access to PG_W, another processor
4437 * could be setting PG_M and/or PG_A concurrently.
4438 *
4439 * PG_W is among the least significant 32 bits.
4440 */
4441 atomic_clear_int((u_int *)pte, PG_W);
4442 pmap->pm_stats.wired_count--;
4443 }
4444 }
4445 if (pv_lists_locked) {
4446 sched_unpin();
4447 rw_wunlock(&pvh_global_lock);
4448 }
4449 PMAP_UNLOCK(pmap);
4450 }
4451
4452 /*
4453 * Copy the range specified by src_addr/len
4454 * from the source map to the range dst_addr/len
4455 * in the destination map.
4456 *
4457 * This routine is only advisory and need not do anything. Since
4458 * current pmap is always the kernel pmap when executing in
4459 * kernel, and we do not copy from the kernel pmap to a user
4460 * pmap, this optimization is not usable in 4/4G full split i386
4461 * world.
4462 */
4463
4464 static void
__CONCAT(PMTYPE,copy)4465 __CONCAT(PMTYPE, copy)(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr,
4466 vm_size_t len, vm_offset_t src_addr)
4467 {
4468 pt_entry_t *src_pte, *dst_pte, ptetemp;
4469 pd_entry_t srcptepaddr;
4470 vm_page_t dstmpte, srcmpte;
4471 vm_offset_t addr, end_addr, pdnxt;
4472 u_int ptepindex;
4473
4474 if (dst_addr != src_addr)
4475 return;
4476
4477 end_addr = src_addr + len;
4478
4479 rw_wlock(&pvh_global_lock);
4480 if (dst_pmap < src_pmap) {
4481 PMAP_LOCK(dst_pmap);
4482 PMAP_LOCK(src_pmap);
4483 } else {
4484 PMAP_LOCK(src_pmap);
4485 PMAP_LOCK(dst_pmap);
4486 }
4487 sched_pin();
4488 for (addr = src_addr; addr < end_addr; addr = pdnxt) {
4489 KASSERT(addr < PMAP_TRM_MIN_ADDRESS,
4490 ("pmap_copy: invalid to pmap_copy the trampoline"));
4491
4492 pdnxt = (addr + NBPDR) & ~PDRMASK;
4493 if (pdnxt < addr)
4494 pdnxt = end_addr;
4495 ptepindex = addr >> PDRSHIFT;
4496
4497 srcptepaddr = src_pmap->pm_pdir[ptepindex];
4498 if (srcptepaddr == 0)
4499 continue;
4500
4501 if (srcptepaddr & PG_PS) {
4502 if ((addr & PDRMASK) != 0 || addr + NBPDR > end_addr)
4503 continue;
4504 if (dst_pmap->pm_pdir[ptepindex] == 0 &&
4505 ((srcptepaddr & PG_MANAGED) == 0 ||
4506 pmap_pv_insert_pde(dst_pmap, addr, srcptepaddr,
4507 PMAP_ENTER_NORECLAIM))) {
4508 dst_pmap->pm_pdir[ptepindex] = srcptepaddr &
4509 ~PG_W;
4510 dst_pmap->pm_stats.resident_count +=
4511 NBPDR / PAGE_SIZE;
4512 pmap_pde_mappings++;
4513 }
4514 continue;
4515 }
4516
4517 srcmpte = PHYS_TO_VM_PAGE(srcptepaddr & PG_FRAME);
4518 KASSERT(srcmpte->ref_count > 0,
4519 ("pmap_copy: source page table page is unused"));
4520
4521 if (pdnxt > end_addr)
4522 pdnxt = end_addr;
4523
4524 src_pte = pmap_pte_quick3(src_pmap, addr);
4525 while (addr < pdnxt) {
4526 ptetemp = *src_pte;
4527 /*
4528 * we only virtual copy managed pages
4529 */
4530 if ((ptetemp & PG_MANAGED) != 0) {
4531 dstmpte = pmap_allocpte(dst_pmap, addr,
4532 PMAP_ENTER_NOSLEEP);
4533 if (dstmpte == NULL)
4534 goto out;
4535 dst_pte = pmap_pte_quick(dst_pmap, addr);
4536 if (*dst_pte == 0 &&
4537 pmap_try_insert_pv_entry(dst_pmap, addr,
4538 PHYS_TO_VM_PAGE(ptetemp & PG_FRAME))) {
4539 /*
4540 * Clear the wired, modified, and
4541 * accessed (referenced) bits
4542 * during the copy.
4543 */
4544 *dst_pte = ptetemp & ~(PG_W | PG_M |
4545 PG_A);
4546 dst_pmap->pm_stats.resident_count++;
4547 } else {
4548 pmap_abort_ptp(dst_pmap, addr, dstmpte);
4549 goto out;
4550 }
4551 if (dstmpte->ref_count >= srcmpte->ref_count)
4552 break;
4553 }
4554 addr += PAGE_SIZE;
4555 src_pte++;
4556 }
4557 }
4558 out:
4559 sched_unpin();
4560 rw_wunlock(&pvh_global_lock);
4561 PMAP_UNLOCK(src_pmap);
4562 PMAP_UNLOCK(dst_pmap);
4563 }
4564
4565 /*
4566 * Zero 1 page of virtual memory mapped from a hardware page by the caller.
4567 */
4568 static __inline void
pagezero(void * page)4569 pagezero(void *page)
4570 {
4571 #if defined(I686_CPU)
4572 if (cpu_class == CPUCLASS_686) {
4573 if (cpu_feature & CPUID_SSE2)
4574 sse2_pagezero(page);
4575 else
4576 i686_pagezero(page);
4577 } else
4578 #endif
4579 bzero(page, PAGE_SIZE);
4580 }
4581
4582 /*
4583 * Zero the specified hardware page.
4584 */
4585 static void
__CONCAT(PMTYPE,zero_page)4586 __CONCAT(PMTYPE, zero_page)(vm_page_t m)
4587 {
4588 pt_entry_t *cmap_pte2;
4589 struct pcpu *pc;
4590
4591 sched_pin();
4592 pc = get_pcpu();
4593 cmap_pte2 = pc->pc_cmap_pte2;
4594 mtx_lock(&pc->pc_cmap_lock);
4595 if (*cmap_pte2)
4596 panic("pmap_zero_page: CMAP2 busy");
4597 *cmap_pte2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) | PG_A | PG_M |
4598 pmap_cache_bits(kernel_pmap, m->md.pat_mode, false);
4599 invlcaddr(pc->pc_cmap_addr2);
4600 pagezero(pc->pc_cmap_addr2);
4601 *cmap_pte2 = 0;
4602
4603 /*
4604 * Unpin the thread before releasing the lock. Otherwise the thread
4605 * could be rescheduled while still bound to the current CPU, only
4606 * to unpin itself immediately upon resuming execution.
4607 */
4608 sched_unpin();
4609 mtx_unlock(&pc->pc_cmap_lock);
4610 }
4611
4612 /*
4613 * Zero an area within a single hardware page. off and size must not
4614 * cover an area beyond a single hardware page.
4615 */
4616 static void
__CONCAT(PMTYPE,zero_page_area)4617 __CONCAT(PMTYPE, zero_page_area)(vm_page_t m, int off, int size)
4618 {
4619 pt_entry_t *cmap_pte2;
4620 struct pcpu *pc;
4621
4622 sched_pin();
4623 pc = get_pcpu();
4624 cmap_pte2 = pc->pc_cmap_pte2;
4625 mtx_lock(&pc->pc_cmap_lock);
4626 if (*cmap_pte2)
4627 panic("pmap_zero_page_area: CMAP2 busy");
4628 *cmap_pte2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) | PG_A | PG_M |
4629 pmap_cache_bits(kernel_pmap, m->md.pat_mode, false);
4630 invlcaddr(pc->pc_cmap_addr2);
4631 if (off == 0 && size == PAGE_SIZE)
4632 pagezero(pc->pc_cmap_addr2);
4633 else
4634 bzero(pc->pc_cmap_addr2 + off, size);
4635 *cmap_pte2 = 0;
4636 sched_unpin();
4637 mtx_unlock(&pc->pc_cmap_lock);
4638 }
4639
4640 /*
4641 * Copy 1 specified hardware page to another.
4642 */
4643 static void
__CONCAT(PMTYPE,copy_page)4644 __CONCAT(PMTYPE, copy_page)(vm_page_t src, vm_page_t dst)
4645 {
4646 pt_entry_t *cmap_pte1, *cmap_pte2;
4647 struct pcpu *pc;
4648
4649 sched_pin();
4650 pc = get_pcpu();
4651 cmap_pte1 = pc->pc_cmap_pte1;
4652 cmap_pte2 = pc->pc_cmap_pte2;
4653 mtx_lock(&pc->pc_cmap_lock);
4654 if (*cmap_pte1)
4655 panic("pmap_copy_page: CMAP1 busy");
4656 if (*cmap_pte2)
4657 panic("pmap_copy_page: CMAP2 busy");
4658 *cmap_pte1 = PG_V | VM_PAGE_TO_PHYS(src) | PG_A |
4659 pmap_cache_bits(kernel_pmap, src->md.pat_mode, false);
4660 invlcaddr(pc->pc_cmap_addr1);
4661 *cmap_pte2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(dst) | PG_A | PG_M |
4662 pmap_cache_bits(kernel_pmap, dst->md.pat_mode, false);
4663 invlcaddr(pc->pc_cmap_addr2);
4664 bcopy(pc->pc_cmap_addr1, pc->pc_cmap_addr2, PAGE_SIZE);
4665 *cmap_pte1 = 0;
4666 *cmap_pte2 = 0;
4667 sched_unpin();
4668 mtx_unlock(&pc->pc_cmap_lock);
4669 }
4670
4671 static void
__CONCAT(PMTYPE,copy_pages)4672 __CONCAT(PMTYPE, copy_pages)(vm_page_t ma[], vm_offset_t a_offset,
4673 vm_page_t mb[], vm_offset_t b_offset, int xfersize)
4674 {
4675 vm_page_t a_pg, b_pg;
4676 char *a_cp, *b_cp;
4677 vm_offset_t a_pg_offset, b_pg_offset;
4678 pt_entry_t *cmap_pte1, *cmap_pte2;
4679 struct pcpu *pc;
4680 int cnt;
4681
4682 sched_pin();
4683 pc = get_pcpu();
4684 cmap_pte1 = pc->pc_cmap_pte1;
4685 cmap_pte2 = pc->pc_cmap_pte2;
4686 mtx_lock(&pc->pc_cmap_lock);
4687 if (*cmap_pte1 != 0)
4688 panic("pmap_copy_pages: CMAP1 busy");
4689 if (*cmap_pte2 != 0)
4690 panic("pmap_copy_pages: CMAP2 busy");
4691 while (xfersize > 0) {
4692 a_pg = ma[a_offset >> PAGE_SHIFT];
4693 a_pg_offset = a_offset & PAGE_MASK;
4694 cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
4695 b_pg = mb[b_offset >> PAGE_SHIFT];
4696 b_pg_offset = b_offset & PAGE_MASK;
4697 cnt = min(cnt, PAGE_SIZE - b_pg_offset);
4698 *cmap_pte1 = PG_V | VM_PAGE_TO_PHYS(a_pg) | PG_A |
4699 pmap_cache_bits(kernel_pmap, a_pg->md.pat_mode, false);
4700 invlcaddr(pc->pc_cmap_addr1);
4701 *cmap_pte2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(b_pg) | PG_A |
4702 PG_M | pmap_cache_bits(kernel_pmap, b_pg->md.pat_mode,
4703 false);
4704 invlcaddr(pc->pc_cmap_addr2);
4705 a_cp = pc->pc_cmap_addr1 + a_pg_offset;
4706 b_cp = pc->pc_cmap_addr2 + b_pg_offset;
4707 bcopy(a_cp, b_cp, cnt);
4708 a_offset += cnt;
4709 b_offset += cnt;
4710 xfersize -= cnt;
4711 }
4712 *cmap_pte1 = 0;
4713 *cmap_pte2 = 0;
4714 sched_unpin();
4715 mtx_unlock(&pc->pc_cmap_lock);
4716 }
4717
4718 /*
4719 * Returns true if the pmap's pv is one of the first
4720 * 16 pvs linked to from this page. This count may
4721 * be changed upwards or downwards in the future; it
4722 * is only necessary that true be returned for a small
4723 * subset of pmaps for proper page aging.
4724 */
4725 static bool
__CONCAT(PMTYPE,page_exists_quick)4726 __CONCAT(PMTYPE, page_exists_quick)(pmap_t pmap, vm_page_t m)
4727 {
4728 struct md_page *pvh;
4729 pv_entry_t pv;
4730 int loops = 0;
4731 bool rv;
4732
4733 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4734 ("pmap_page_exists_quick: page %p is not managed", m));
4735 rv = false;
4736 rw_wlock(&pvh_global_lock);
4737 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
4738 if (PV_PMAP(pv) == pmap) {
4739 rv = true;
4740 break;
4741 }
4742 loops++;
4743 if (loops >= 16)
4744 break;
4745 }
4746 if (!rv && loops < 16 && (m->flags & PG_FICTITIOUS) == 0) {
4747 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4748 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
4749 if (PV_PMAP(pv) == pmap) {
4750 rv = true;
4751 break;
4752 }
4753 loops++;
4754 if (loops >= 16)
4755 break;
4756 }
4757 }
4758 rw_wunlock(&pvh_global_lock);
4759 return (rv);
4760 }
4761
4762 /*
4763 * pmap_page_wired_mappings:
4764 *
4765 * Return the number of managed mappings to the given physical page
4766 * that are wired.
4767 */
4768 static int
__CONCAT(PMTYPE,page_wired_mappings)4769 __CONCAT(PMTYPE, page_wired_mappings)(vm_page_t m)
4770 {
4771 int count;
4772
4773 count = 0;
4774 if ((m->oflags & VPO_UNMANAGED) != 0)
4775 return (count);
4776 rw_wlock(&pvh_global_lock);
4777 count = pmap_pvh_wired_mappings(&m->md, count);
4778 if ((m->flags & PG_FICTITIOUS) == 0) {
4779 count = pmap_pvh_wired_mappings(pa_to_pvh(VM_PAGE_TO_PHYS(m)),
4780 count);
4781 }
4782 rw_wunlock(&pvh_global_lock);
4783 return (count);
4784 }
4785
4786 /*
4787 * pmap_pvh_wired_mappings:
4788 *
4789 * Return the updated number "count" of managed mappings that are wired.
4790 */
4791 static int
pmap_pvh_wired_mappings(struct md_page * pvh,int count)4792 pmap_pvh_wired_mappings(struct md_page *pvh, int count)
4793 {
4794 pmap_t pmap;
4795 pt_entry_t *pte;
4796 pv_entry_t pv;
4797
4798 rw_assert(&pvh_global_lock, RA_WLOCKED);
4799 sched_pin();
4800 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
4801 pmap = PV_PMAP(pv);
4802 PMAP_LOCK(pmap);
4803 pte = pmap_pte_quick(pmap, pv->pv_va);
4804 if ((*pte & PG_W) != 0)
4805 count++;
4806 PMAP_UNLOCK(pmap);
4807 }
4808 sched_unpin();
4809 return (count);
4810 }
4811
4812 /*
4813 * Returns true if the given page is mapped individually or as part of
4814 * a 4mpage. Otherwise, returns false.
4815 */
4816 static bool
__CONCAT(PMTYPE,page_is_mapped)4817 __CONCAT(PMTYPE, page_is_mapped)(vm_page_t m)
4818 {
4819 bool rv;
4820
4821 if ((m->oflags & VPO_UNMANAGED) != 0)
4822 return (false);
4823 rw_wlock(&pvh_global_lock);
4824 rv = !TAILQ_EMPTY(&m->md.pv_list) ||
4825 ((m->flags & PG_FICTITIOUS) == 0 &&
4826 !TAILQ_EMPTY(&pa_to_pvh(VM_PAGE_TO_PHYS(m))->pv_list));
4827 rw_wunlock(&pvh_global_lock);
4828 return (rv);
4829 }
4830
4831 /*
4832 * Remove all pages from specified address space
4833 * this aids process exit speeds. Also, this code
4834 * is special cased for current process only, but
4835 * can have the more generic (and slightly slower)
4836 * mode enabled. This is much faster than pmap_remove
4837 * in the case of running down an entire address space.
4838 */
4839 static void
__CONCAT(PMTYPE,remove_pages)4840 __CONCAT(PMTYPE, remove_pages)(pmap_t pmap)
4841 {
4842 pt_entry_t *pte, tpte;
4843 vm_page_t m, mpte, mt;
4844 pv_entry_t pv;
4845 struct md_page *pvh;
4846 struct pv_chunk *pc, *npc;
4847 struct spglist free;
4848 int field, idx;
4849 int32_t bit;
4850 uint32_t inuse, bitmask;
4851 int allfree;
4852
4853 if (pmap != PCPU_GET(curpmap)) {
4854 printf("warning: pmap_remove_pages called with non-current pmap\n");
4855 return;
4856 }
4857 SLIST_INIT(&free);
4858 rw_wlock(&pvh_global_lock);
4859 PMAP_LOCK(pmap);
4860 sched_pin();
4861 TAILQ_FOREACH_SAFE(pc, &pmap->pm_pvchunk, pc_list, npc) {
4862 KASSERT(pc->pc_pmap == pmap, ("Wrong pmap %p %p", pmap,
4863 pc->pc_pmap));
4864 allfree = 1;
4865 for (field = 0; field < _NPCM; field++) {
4866 inuse = ~pc->pc_map[field] & pc_freemask[field];
4867 while (inuse != 0) {
4868 bit = bsfl(inuse);
4869 bitmask = 1UL << bit;
4870 idx = field * 32 + bit;
4871 pv = &pc->pc_pventry[idx];
4872 inuse &= ~bitmask;
4873
4874 pte = pmap_pde(pmap, pv->pv_va);
4875 tpte = *pte;
4876 if ((tpte & PG_PS) == 0) {
4877 pte = pmap_pte_quick(pmap, pv->pv_va);
4878 tpte = *pte & ~PG_PTE_PAT;
4879 }
4880
4881 if (tpte == 0) {
4882 printf(
4883 "TPTE at %p IS ZERO @ VA %08x\n",
4884 pte, pv->pv_va);
4885 panic("bad pte");
4886 }
4887
4888 /*
4889 * We cannot remove wired pages from a process' mapping at this time
4890 */
4891 if (tpte & PG_W) {
4892 allfree = 0;
4893 continue;
4894 }
4895
4896 m = PHYS_TO_VM_PAGE(tpte & PG_FRAME);
4897 KASSERT(m->phys_addr == (tpte & PG_FRAME),
4898 ("vm_page_t %p phys_addr mismatch %016jx %016jx",
4899 m, (uintmax_t)m->phys_addr,
4900 (uintmax_t)tpte));
4901
4902 KASSERT((m->flags & PG_FICTITIOUS) != 0 ||
4903 m < &vm_page_array[vm_page_array_size],
4904 ("pmap_remove_pages: bad tpte %#jx",
4905 (uintmax_t)tpte));
4906
4907 pte_clear(pte);
4908
4909 /*
4910 * Update the vm_page_t clean/reference bits.
4911 */
4912 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
4913 if ((tpte & PG_PS) != 0) {
4914 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
4915 vm_page_dirty(mt);
4916 } else
4917 vm_page_dirty(m);
4918 }
4919
4920 /* Mark free */
4921 PV_STAT(pv_entry_frees++);
4922 PV_STAT(pv_entry_spare++);
4923 pv_entry_count--;
4924 pc->pc_map[field] |= bitmask;
4925 if ((tpte & PG_PS) != 0) {
4926 pmap->pm_stats.resident_count -= NBPDR / PAGE_SIZE;
4927 pvh = pa_to_pvh(tpte & PG_PS_FRAME);
4928 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
4929 if (TAILQ_EMPTY(&pvh->pv_list)) {
4930 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
4931 if (TAILQ_EMPTY(&mt->md.pv_list))
4932 vm_page_aflag_clear(mt, PGA_WRITEABLE);
4933 }
4934 mpte = pmap_remove_pt_page(pmap, pv->pv_va);
4935 if (mpte != NULL) {
4936 KASSERT(vm_page_any_valid(mpte),
4937 ("pmap_remove_pages: pte page not promoted"));
4938 pmap->pm_stats.resident_count--;
4939 KASSERT(mpte->ref_count == NPTEPG,
4940 ("pmap_remove_pages: pte page ref count error"));
4941 mpte->ref_count = 0;
4942 pmap_add_delayed_free_list(mpte, &free, false);
4943 }
4944 } else {
4945 pmap->pm_stats.resident_count--;
4946 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
4947 if (TAILQ_EMPTY(&m->md.pv_list) &&
4948 (m->flags & PG_FICTITIOUS) == 0) {
4949 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4950 if (TAILQ_EMPTY(&pvh->pv_list))
4951 vm_page_aflag_clear(m, PGA_WRITEABLE);
4952 }
4953 pmap_unuse_pt(pmap, pv->pv_va, &free);
4954 }
4955 }
4956 }
4957 if (allfree) {
4958 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
4959 free_pv_chunk(pc);
4960 }
4961 }
4962 sched_unpin();
4963 pmap_invalidate_all_int(pmap);
4964 rw_wunlock(&pvh_global_lock);
4965 PMAP_UNLOCK(pmap);
4966 vm_page_free_pages_toq(&free, true);
4967 }
4968
4969 /*
4970 * pmap_is_modified:
4971 *
4972 * Return whether or not the specified physical page was modified
4973 * in any physical maps.
4974 */
4975 static bool
__CONCAT(PMTYPE,is_modified)4976 __CONCAT(PMTYPE, is_modified)(vm_page_t m)
4977 {
4978 bool rv;
4979
4980 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4981 ("pmap_is_modified: page %p is not managed", m));
4982
4983 /*
4984 * If the page is not busied then this check is racy.
4985 */
4986 if (!pmap_page_is_write_mapped(m))
4987 return (false);
4988 rw_wlock(&pvh_global_lock);
4989 rv = pmap_is_modified_pvh(&m->md) ||
4990 ((m->flags & PG_FICTITIOUS) == 0 &&
4991 pmap_is_modified_pvh(pa_to_pvh(VM_PAGE_TO_PHYS(m))));
4992 rw_wunlock(&pvh_global_lock);
4993 return (rv);
4994 }
4995
4996 /*
4997 * Returns true if any of the given mappings were used to modify
4998 * physical memory. Otherwise, returns false. Both page and 2mpage
4999 * mappings are supported.
5000 */
5001 static bool
pmap_is_modified_pvh(struct md_page * pvh)5002 pmap_is_modified_pvh(struct md_page *pvh)
5003 {
5004 pv_entry_t pv;
5005 pt_entry_t *pte;
5006 pmap_t pmap;
5007 bool rv;
5008
5009 rw_assert(&pvh_global_lock, RA_WLOCKED);
5010 rv = false;
5011 sched_pin();
5012 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
5013 pmap = PV_PMAP(pv);
5014 PMAP_LOCK(pmap);
5015 pte = pmap_pte_quick(pmap, pv->pv_va);
5016 rv = (*pte & (PG_M | PG_RW)) == (PG_M | PG_RW);
5017 PMAP_UNLOCK(pmap);
5018 if (rv)
5019 break;
5020 }
5021 sched_unpin();
5022 return (rv);
5023 }
5024
5025 /*
5026 * pmap_is_prefaultable:
5027 *
5028 * Return whether or not the specified virtual address is elgible
5029 * for prefault.
5030 */
5031 static bool
__CONCAT(PMTYPE,is_prefaultable)5032 __CONCAT(PMTYPE, is_prefaultable)(pmap_t pmap, vm_offset_t addr)
5033 {
5034 pd_entry_t pde;
5035 bool rv;
5036
5037 rv = false;
5038 PMAP_LOCK(pmap);
5039 pde = *pmap_pde(pmap, addr);
5040 if (pde != 0 && (pde & PG_PS) == 0)
5041 rv = pmap_pte_ufast(pmap, addr, pde) == 0;
5042 PMAP_UNLOCK(pmap);
5043 return (rv);
5044 }
5045
5046 /*
5047 * pmap_is_referenced:
5048 *
5049 * Return whether or not the specified physical page was referenced
5050 * in any physical maps.
5051 */
5052 static bool
__CONCAT(PMTYPE,is_referenced)5053 __CONCAT(PMTYPE, is_referenced)(vm_page_t m)
5054 {
5055 bool rv;
5056
5057 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5058 ("pmap_is_referenced: page %p is not managed", m));
5059 rw_wlock(&pvh_global_lock);
5060 rv = pmap_is_referenced_pvh(&m->md) ||
5061 ((m->flags & PG_FICTITIOUS) == 0 &&
5062 pmap_is_referenced_pvh(pa_to_pvh(VM_PAGE_TO_PHYS(m))));
5063 rw_wunlock(&pvh_global_lock);
5064 return (rv);
5065 }
5066
5067 /*
5068 * Returns true if any of the given mappings were referenced and false
5069 * otherwise. Both page and 4mpage mappings are supported.
5070 */
5071 static bool
pmap_is_referenced_pvh(struct md_page * pvh)5072 pmap_is_referenced_pvh(struct md_page *pvh)
5073 {
5074 pv_entry_t pv;
5075 pt_entry_t *pte;
5076 pmap_t pmap;
5077 bool rv;
5078
5079 rw_assert(&pvh_global_lock, RA_WLOCKED);
5080 rv = false;
5081 sched_pin();
5082 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
5083 pmap = PV_PMAP(pv);
5084 PMAP_LOCK(pmap);
5085 pte = pmap_pte_quick(pmap, pv->pv_va);
5086 rv = (*pte & (PG_A | PG_V)) == (PG_A | PG_V);
5087 PMAP_UNLOCK(pmap);
5088 if (rv)
5089 break;
5090 }
5091 sched_unpin();
5092 return (rv);
5093 }
5094
5095 /*
5096 * Clear the write and modified bits in each of the given page's mappings.
5097 */
5098 static void
__CONCAT(PMTYPE,remove_write)5099 __CONCAT(PMTYPE, remove_write)(vm_page_t m)
5100 {
5101 struct md_page *pvh;
5102 pv_entry_t next_pv, pv;
5103 pmap_t pmap;
5104 pd_entry_t *pde;
5105 pt_entry_t oldpte, *pte;
5106 vm_offset_t va;
5107
5108 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5109 ("pmap_remove_write: page %p is not managed", m));
5110 vm_page_assert_busied(m);
5111
5112 if (!pmap_page_is_write_mapped(m))
5113 return;
5114 rw_wlock(&pvh_global_lock);
5115 sched_pin();
5116 if ((m->flags & PG_FICTITIOUS) != 0)
5117 goto small_mappings;
5118 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
5119 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
5120 va = pv->pv_va;
5121 pmap = PV_PMAP(pv);
5122 PMAP_LOCK(pmap);
5123 pde = pmap_pde(pmap, va);
5124 if ((*pde & PG_RW) != 0)
5125 (void)pmap_demote_pde(pmap, pde, va);
5126 PMAP_UNLOCK(pmap);
5127 }
5128 small_mappings:
5129 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
5130 pmap = PV_PMAP(pv);
5131 PMAP_LOCK(pmap);
5132 pde = pmap_pde(pmap, pv->pv_va);
5133 KASSERT((*pde & PG_PS) == 0, ("pmap_clear_write: found"
5134 " a 4mpage in page %p's pv list", m));
5135 pte = pmap_pte_quick(pmap, pv->pv_va);
5136 retry:
5137 oldpte = *pte;
5138 if ((oldpte & PG_RW) != 0) {
5139 /*
5140 * Regardless of whether a pte is 32 or 64 bits
5141 * in size, PG_RW and PG_M are among the least
5142 * significant 32 bits.
5143 */
5144 if (!atomic_cmpset_int((u_int *)pte, oldpte,
5145 oldpte & ~(PG_RW | PG_M)))
5146 goto retry;
5147 if ((oldpte & PG_M) != 0)
5148 vm_page_dirty(m);
5149 pmap_invalidate_page_int(pmap, pv->pv_va);
5150 }
5151 PMAP_UNLOCK(pmap);
5152 }
5153 vm_page_aflag_clear(m, PGA_WRITEABLE);
5154 sched_unpin();
5155 rw_wunlock(&pvh_global_lock);
5156 }
5157
5158 /*
5159 * pmap_ts_referenced:
5160 *
5161 * Return a count of reference bits for a page, clearing those bits.
5162 * It is not necessary for every reference bit to be cleared, but it
5163 * is necessary that 0 only be returned when there are truly no
5164 * reference bits set.
5165 *
5166 * As an optimization, update the page's dirty field if a modified bit is
5167 * found while counting reference bits. This opportunistic update can be
5168 * performed at low cost and can eliminate the need for some future calls
5169 * to pmap_is_modified(). However, since this function stops after
5170 * finding PMAP_TS_REFERENCED_MAX reference bits, it may not detect some
5171 * dirty pages. Those dirty pages will only be detected by a future call
5172 * to pmap_is_modified().
5173 */
5174 static int
__CONCAT(PMTYPE,ts_referenced)5175 __CONCAT(PMTYPE, ts_referenced)(vm_page_t m)
5176 {
5177 struct md_page *pvh;
5178 pv_entry_t pv, pvf;
5179 pmap_t pmap;
5180 pd_entry_t *pde;
5181 pt_entry_t *pte;
5182 vm_paddr_t pa;
5183 int rtval = 0;
5184
5185 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5186 ("pmap_ts_referenced: page %p is not managed", m));
5187 pa = VM_PAGE_TO_PHYS(m);
5188 pvh = pa_to_pvh(pa);
5189 rw_wlock(&pvh_global_lock);
5190 sched_pin();
5191 if ((m->flags & PG_FICTITIOUS) != 0 ||
5192 (pvf = TAILQ_FIRST(&pvh->pv_list)) == NULL)
5193 goto small_mappings;
5194 pv = pvf;
5195 do {
5196 pmap = PV_PMAP(pv);
5197 PMAP_LOCK(pmap);
5198 pde = pmap_pde(pmap, pv->pv_va);
5199 if ((*pde & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
5200 /*
5201 * Although "*pde" is mapping a 2/4MB page, because
5202 * this function is called at a 4KB page granularity,
5203 * we only update the 4KB page under test.
5204 */
5205 vm_page_dirty(m);
5206 }
5207 if ((*pde & PG_A) != 0) {
5208 /*
5209 * Since this reference bit is shared by either 1024
5210 * or 512 4KB pages, it should not be cleared every
5211 * time it is tested. Apply a simple "hash" function
5212 * on the physical page number, the virtual superpage
5213 * number, and the pmap address to select one 4KB page
5214 * out of the 1024 or 512 on which testing the
5215 * reference bit will result in clearing that bit.
5216 * This function is designed to avoid the selection of
5217 * the same 4KB page for every 2- or 4MB page mapping.
5218 *
5219 * On demotion, a mapping that hasn't been referenced
5220 * is simply destroyed. To avoid the possibility of a
5221 * subsequent page fault on a demoted wired mapping,
5222 * always leave its reference bit set. Moreover,
5223 * since the superpage is wired, the current state of
5224 * its reference bit won't affect page replacement.
5225 */
5226 if ((((pa >> PAGE_SHIFT) ^ (pv->pv_va >> PDRSHIFT) ^
5227 (uintptr_t)pmap) & (NPTEPG - 1)) == 0 &&
5228 (*pde & PG_W) == 0) {
5229 atomic_clear_int((u_int *)pde, PG_A);
5230 pmap_invalidate_page_int(pmap, pv->pv_va);
5231 }
5232 rtval++;
5233 }
5234 PMAP_UNLOCK(pmap);
5235 /* Rotate the PV list if it has more than one entry. */
5236 if (TAILQ_NEXT(pv, pv_next) != NULL) {
5237 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
5238 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
5239 }
5240 if (rtval >= PMAP_TS_REFERENCED_MAX)
5241 goto out;
5242 } while ((pv = TAILQ_FIRST(&pvh->pv_list)) != pvf);
5243 small_mappings:
5244 if ((pvf = TAILQ_FIRST(&m->md.pv_list)) == NULL)
5245 goto out;
5246 pv = pvf;
5247 do {
5248 pmap = PV_PMAP(pv);
5249 PMAP_LOCK(pmap);
5250 pde = pmap_pde(pmap, pv->pv_va);
5251 KASSERT((*pde & PG_PS) == 0,
5252 ("pmap_ts_referenced: found a 4mpage in page %p's pv list",
5253 m));
5254 pte = pmap_pte_quick(pmap, pv->pv_va);
5255 if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW))
5256 vm_page_dirty(m);
5257 if ((*pte & PG_A) != 0) {
5258 atomic_clear_int((u_int *)pte, PG_A);
5259 pmap_invalidate_page_int(pmap, pv->pv_va);
5260 rtval++;
5261 }
5262 PMAP_UNLOCK(pmap);
5263 /* Rotate the PV list if it has more than one entry. */
5264 if (TAILQ_NEXT(pv, pv_next) != NULL) {
5265 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
5266 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
5267 }
5268 } while ((pv = TAILQ_FIRST(&m->md.pv_list)) != pvf && rtval <
5269 PMAP_TS_REFERENCED_MAX);
5270 out:
5271 sched_unpin();
5272 rw_wunlock(&pvh_global_lock);
5273 return (rtval);
5274 }
5275
5276 /*
5277 * Apply the given advice to the specified range of addresses within the
5278 * given pmap. Depending on the advice, clear the referenced and/or
5279 * modified flags in each mapping and set the mapped page's dirty field.
5280 */
5281 static void
__CONCAT(PMTYPE,advise)5282 __CONCAT(PMTYPE, advise)(pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
5283 int advice)
5284 {
5285 pd_entry_t oldpde, *pde;
5286 pt_entry_t *pte;
5287 vm_offset_t va, pdnxt;
5288 vm_page_t m;
5289 bool anychanged, pv_lists_locked;
5290
5291 if (advice != MADV_DONTNEED && advice != MADV_FREE)
5292 return;
5293 if (pmap_is_current(pmap))
5294 pv_lists_locked = false;
5295 else {
5296 pv_lists_locked = true;
5297 resume:
5298 rw_wlock(&pvh_global_lock);
5299 sched_pin();
5300 }
5301 anychanged = false;
5302 PMAP_LOCK(pmap);
5303 for (; sva < eva; sva = pdnxt) {
5304 pdnxt = (sva + NBPDR) & ~PDRMASK;
5305 if (pdnxt < sva)
5306 pdnxt = eva;
5307 pde = pmap_pde(pmap, sva);
5308 oldpde = *pde;
5309 if ((oldpde & PG_V) == 0)
5310 continue;
5311 else if ((oldpde & PG_PS) != 0) {
5312 if ((oldpde & PG_MANAGED) == 0)
5313 continue;
5314 if (!pv_lists_locked) {
5315 pv_lists_locked = true;
5316 if (!rw_try_wlock(&pvh_global_lock)) {
5317 if (anychanged)
5318 pmap_invalidate_all_int(pmap);
5319 PMAP_UNLOCK(pmap);
5320 goto resume;
5321 }
5322 sched_pin();
5323 }
5324 if (!pmap_demote_pde(pmap, pde, sva)) {
5325 /*
5326 * The large page mapping was destroyed.
5327 */
5328 continue;
5329 }
5330
5331 /*
5332 * Unless the page mappings are wired, remove the
5333 * mapping to a single page so that a subsequent
5334 * access may repromote. Choosing the last page
5335 * within the address range [sva, min(pdnxt, eva))
5336 * generally results in more repromotions. Since the
5337 * underlying page table page is fully populated, this
5338 * removal never frees a page table page.
5339 */
5340 if ((oldpde & PG_W) == 0) {
5341 va = eva;
5342 if (va > pdnxt)
5343 va = pdnxt;
5344 va -= PAGE_SIZE;
5345 KASSERT(va >= sva,
5346 ("pmap_advise: no address gap"));
5347 pte = pmap_pte_quick(pmap, va);
5348 KASSERT((*pte & PG_V) != 0,
5349 ("pmap_advise: invalid PTE"));
5350 pmap_remove_pte(pmap, pte, va, NULL);
5351 anychanged = true;
5352 }
5353 }
5354 if (pdnxt > eva)
5355 pdnxt = eva;
5356 va = pdnxt;
5357 for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++,
5358 sva += PAGE_SIZE) {
5359 if ((*pte & (PG_MANAGED | PG_V)) != (PG_MANAGED | PG_V))
5360 goto maybe_invlrng;
5361 else if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
5362 if (advice == MADV_DONTNEED) {
5363 /*
5364 * Future calls to pmap_is_modified()
5365 * can be avoided by making the page
5366 * dirty now.
5367 */
5368 m = PHYS_TO_VM_PAGE(*pte & PG_FRAME);
5369 vm_page_dirty(m);
5370 }
5371 atomic_clear_int((u_int *)pte, PG_M | PG_A);
5372 } else if ((*pte & PG_A) != 0)
5373 atomic_clear_int((u_int *)pte, PG_A);
5374 else
5375 goto maybe_invlrng;
5376 if ((*pte & PG_G) != 0) {
5377 if (va == pdnxt)
5378 va = sva;
5379 } else
5380 anychanged = true;
5381 continue;
5382 maybe_invlrng:
5383 if (va != pdnxt) {
5384 pmap_invalidate_range_int(pmap, va, sva);
5385 va = pdnxt;
5386 }
5387 }
5388 if (va != pdnxt)
5389 pmap_invalidate_range_int(pmap, va, sva);
5390 }
5391 if (anychanged)
5392 pmap_invalidate_all_int(pmap);
5393 if (pv_lists_locked) {
5394 sched_unpin();
5395 rw_wunlock(&pvh_global_lock);
5396 }
5397 PMAP_UNLOCK(pmap);
5398 }
5399
5400 /*
5401 * Clear the modify bits on the specified physical page.
5402 */
5403 static void
__CONCAT(PMTYPE,clear_modify)5404 __CONCAT(PMTYPE, clear_modify)(vm_page_t m)
5405 {
5406 struct md_page *pvh;
5407 pv_entry_t next_pv, pv;
5408 pmap_t pmap;
5409 pd_entry_t oldpde, *pde;
5410 pt_entry_t *pte;
5411 vm_offset_t va;
5412
5413 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5414 ("pmap_clear_modify: page %p is not managed", m));
5415 vm_page_assert_busied(m);
5416
5417 if (!pmap_page_is_write_mapped(m))
5418 return;
5419 rw_wlock(&pvh_global_lock);
5420 sched_pin();
5421 if ((m->flags & PG_FICTITIOUS) != 0)
5422 goto small_mappings;
5423 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
5424 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
5425 va = pv->pv_va;
5426 pmap = PV_PMAP(pv);
5427 PMAP_LOCK(pmap);
5428 pde = pmap_pde(pmap, va);
5429 oldpde = *pde;
5430 /* If oldpde has PG_RW set, then it also has PG_M set. */
5431 if ((oldpde & PG_RW) != 0 &&
5432 pmap_demote_pde(pmap, pde, va) &&
5433 (oldpde & PG_W) == 0) {
5434 /*
5435 * Write protect the mapping to a single page so that
5436 * a subsequent write access may repromote.
5437 */
5438 va += VM_PAGE_TO_PHYS(m) - (oldpde & PG_PS_FRAME);
5439 pte = pmap_pte_quick(pmap, va);
5440 /*
5441 * Regardless of whether a pte is 32 or 64 bits
5442 * in size, PG_RW and PG_M are among the least
5443 * significant 32 bits.
5444 */
5445 atomic_clear_int((u_int *)pte, PG_M | PG_RW);
5446 vm_page_dirty(m);
5447 pmap_invalidate_page_int(pmap, va);
5448 }
5449 PMAP_UNLOCK(pmap);
5450 }
5451 small_mappings:
5452 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
5453 pmap = PV_PMAP(pv);
5454 PMAP_LOCK(pmap);
5455 pde = pmap_pde(pmap, pv->pv_va);
5456 KASSERT((*pde & PG_PS) == 0, ("pmap_clear_modify: found"
5457 " a 4mpage in page %p's pv list", m));
5458 pte = pmap_pte_quick(pmap, pv->pv_va);
5459 if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
5460 /*
5461 * Regardless of whether a pte is 32 or 64 bits
5462 * in size, PG_M is among the least significant
5463 * 32 bits.
5464 */
5465 atomic_clear_int((u_int *)pte, PG_M);
5466 pmap_invalidate_page_int(pmap, pv->pv_va);
5467 }
5468 PMAP_UNLOCK(pmap);
5469 }
5470 sched_unpin();
5471 rw_wunlock(&pvh_global_lock);
5472 }
5473
5474 /*
5475 * Miscellaneous support routines follow
5476 */
5477
5478 /* Adjust the cache mode for a 4KB page mapped via a PTE. */
5479 static __inline void
pmap_pte_attr(pt_entry_t * pte,int cache_bits)5480 pmap_pte_attr(pt_entry_t *pte, int cache_bits)
5481 {
5482 u_int opte, npte;
5483
5484 /*
5485 * The cache mode bits are all in the low 32-bits of the
5486 * PTE, so we can just spin on updating the low 32-bits.
5487 */
5488 do {
5489 opte = *(u_int *)pte;
5490 npte = opte & ~PG_PTE_CACHE;
5491 npte |= cache_bits;
5492 } while (npte != opte && !atomic_cmpset_int((u_int *)pte, opte, npte));
5493 }
5494
5495 /* Adjust the cache mode for a 2/4MB page mapped via a PDE. */
5496 static __inline void
pmap_pde_attr(pd_entry_t * pde,int cache_bits)5497 pmap_pde_attr(pd_entry_t *pde, int cache_bits)
5498 {
5499 u_int opde, npde;
5500
5501 /*
5502 * The cache mode bits are all in the low 32-bits of the
5503 * PDE, so we can just spin on updating the low 32-bits.
5504 */
5505 do {
5506 opde = *(u_int *)pde;
5507 npde = opde & ~PG_PDE_CACHE;
5508 npde |= cache_bits;
5509 } while (npde != opde && !atomic_cmpset_int((u_int *)pde, opde, npde));
5510 }
5511
5512 /*
5513 * Map a set of physical memory pages into the kernel virtual
5514 * address space. Return a pointer to where it is mapped. This
5515 * routine is intended to be used for mapping device memory,
5516 * NOT real memory.
5517 */
5518 static void *
__CONCAT(PMTYPE,mapdev_attr)5519 __CONCAT(PMTYPE, mapdev_attr)(vm_paddr_t pa, vm_size_t size, int mode,
5520 int flags)
5521 {
5522 struct pmap_preinit_mapping *ppim;
5523 vm_offset_t va, offset;
5524 vm_page_t m;
5525 vm_size_t tmpsize;
5526 int i;
5527
5528 offset = pa & PAGE_MASK;
5529 size = round_page(offset + size);
5530 pa = pa & PG_FRAME;
5531
5532 if (pa < PMAP_MAP_LOW && pa + size <= PMAP_MAP_LOW) {
5533 va = pa + PMAP_MAP_LOW;
5534 if ((flags & MAPDEV_SETATTR) == 0)
5535 return ((void *)(va + offset));
5536 } else if (!pmap_initialized) {
5537 va = 0;
5538 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
5539 ppim = pmap_preinit_mapping + i;
5540 if (ppim->va == 0) {
5541 ppim->pa = pa;
5542 ppim->sz = size;
5543 ppim->mode = mode;
5544 ppim->va = virtual_avail;
5545 virtual_avail += size;
5546 va = ppim->va;
5547 break;
5548 }
5549 }
5550 if (va == 0)
5551 panic("%s: too many preinit mappings", __func__);
5552 } else {
5553 /*
5554 * If we have a preinit mapping, re-use it.
5555 */
5556 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
5557 ppim = pmap_preinit_mapping + i;
5558 if (ppim->pa == pa && ppim->sz == size &&
5559 (ppim->mode == mode ||
5560 (flags & MAPDEV_SETATTR) == 0))
5561 return ((void *)(ppim->va + offset));
5562 }
5563 va = kva_alloc(size);
5564 if (va == 0)
5565 panic("%s: Couldn't allocate KVA", __func__);
5566 }
5567 for (tmpsize = 0; tmpsize < size; tmpsize += PAGE_SIZE) {
5568 if ((flags & MAPDEV_SETATTR) == 0 && pmap_initialized) {
5569 m = PHYS_TO_VM_PAGE(pa);
5570 if (m != NULL && VM_PAGE_TO_PHYS(m) == pa) {
5571 pmap_kenter_attr(va + tmpsize, pa + tmpsize,
5572 m->md.pat_mode);
5573 continue;
5574 }
5575 }
5576 pmap_kenter_attr(va + tmpsize, pa + tmpsize, mode);
5577 }
5578 pmap_invalidate_range_int(kernel_pmap, va, va + tmpsize);
5579 pmap_invalidate_cache_range(va, va + size);
5580 return ((void *)(va + offset));
5581 }
5582
5583 static void
__CONCAT(PMTYPE,unmapdev)5584 __CONCAT(PMTYPE, unmapdev)(void *p, vm_size_t size)
5585 {
5586 struct pmap_preinit_mapping *ppim;
5587 vm_offset_t offset, va;
5588 int i;
5589
5590 va = (vm_offset_t)p;
5591 if (va >= PMAP_MAP_LOW && va <= KERNBASE && va + size <= KERNBASE)
5592 return;
5593 offset = va & PAGE_MASK;
5594 size = round_page(offset + size);
5595 va = trunc_page(va);
5596 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
5597 ppim = pmap_preinit_mapping + i;
5598 if (ppim->va == va && ppim->sz == size) {
5599 if (pmap_initialized)
5600 return;
5601 ppim->pa = 0;
5602 ppim->va = 0;
5603 ppim->sz = 0;
5604 ppim->mode = 0;
5605 if (va + size == virtual_avail)
5606 virtual_avail = va;
5607 return;
5608 }
5609 }
5610 if (pmap_initialized) {
5611 pmap_qremove(va, atop(size));
5612 kva_free(va, size);
5613 }
5614 }
5615
5616 /*
5617 * Sets the memory attribute for the specified page.
5618 */
5619 static void
__CONCAT(PMTYPE,page_set_memattr)5620 __CONCAT(PMTYPE, page_set_memattr)(vm_page_t m, vm_memattr_t ma)
5621 {
5622 if (m->md.pat_mode == ma)
5623 return;
5624
5625 m->md.pat_mode = ma;
5626 if ((m->flags & PG_FICTITIOUS) != 0)
5627 return;
5628
5629 /*
5630 * If "m" is a normal page, flush it from the cache.
5631 * See pmap_invalidate_cache_range().
5632 *
5633 * First, try to find an existing mapping of the page by sf
5634 * buffer. sf_buf_invalidate_cache() modifies mapping and
5635 * flushes the cache.
5636 */
5637 if (sf_buf_invalidate_cache(m))
5638 return;
5639
5640 /*
5641 * If page is not mapped by sf buffer, but CPU does not
5642 * support self snoop, map the page transient and do
5643 * invalidation. In the worst case, whole cache is flushed by
5644 * pmap_invalidate_cache_range().
5645 */
5646 if ((cpu_feature & CPUID_SS) == 0)
5647 pmap_flush_page(m);
5648 }
5649
5650 static void
__CONCAT(PMTYPE,flush_page)5651 __CONCAT(PMTYPE, flush_page)(vm_page_t m)
5652 {
5653 pt_entry_t *cmap_pte2;
5654 struct pcpu *pc;
5655 vm_offset_t sva, eva;
5656 bool useclflushopt;
5657
5658 useclflushopt = (cpu_stdext_feature & CPUID_STDEXT_CLFLUSHOPT) != 0;
5659 if (useclflushopt || (cpu_feature & CPUID_CLFSH) != 0) {
5660 sched_pin();
5661 pc = get_pcpu();
5662 cmap_pte2 = pc->pc_cmap_pte2;
5663 mtx_lock(&pc->pc_cmap_lock);
5664 if (*cmap_pte2)
5665 panic("pmap_flush_page: CMAP2 busy");
5666 *cmap_pte2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) |
5667 PG_A | PG_M | pmap_cache_bits(kernel_pmap, m->md.pat_mode,
5668 false);
5669 invlcaddr(pc->pc_cmap_addr2);
5670 sva = (vm_offset_t)pc->pc_cmap_addr2;
5671 eva = sva + PAGE_SIZE;
5672
5673 /*
5674 * Use mfence or sfence despite the ordering implied by
5675 * mtx_{un,}lock() because clflush on non-Intel CPUs
5676 * and clflushopt are not guaranteed to be ordered by
5677 * any other instruction.
5678 */
5679 if (useclflushopt)
5680 sfence();
5681 else if (cpu_vendor_id != CPU_VENDOR_INTEL)
5682 mfence();
5683 for (; sva < eva; sva += cpu_clflush_line_size) {
5684 if (useclflushopt)
5685 clflushopt(sva);
5686 else
5687 clflush(sva);
5688 }
5689 if (useclflushopt)
5690 sfence();
5691 else if (cpu_vendor_id != CPU_VENDOR_INTEL)
5692 mfence();
5693 *cmap_pte2 = 0;
5694 sched_unpin();
5695 mtx_unlock(&pc->pc_cmap_lock);
5696 } else
5697 pmap_invalidate_cache();
5698 }
5699
5700 /*
5701 * Changes the specified virtual address range's memory type to that given by
5702 * the parameter "mode". The specified virtual address range must be
5703 * completely contained within either the kernel map.
5704 *
5705 * Returns zero if the change completed successfully, and either EINVAL or
5706 * ENOMEM if the change failed. Specifically, EINVAL is returned if some part
5707 * of the virtual address range was not mapped, and ENOMEM is returned if
5708 * there was insufficient memory available to complete the change.
5709 */
5710 static int
__CONCAT(PMTYPE,change_attr)5711 __CONCAT(PMTYPE, change_attr)(vm_offset_t va, vm_size_t size, int mode)
5712 {
5713 vm_offset_t base, offset, tmpva;
5714 pd_entry_t *pde;
5715 pt_entry_t *pte;
5716 int cache_bits_pte, cache_bits_pde;
5717 bool changed;
5718
5719 base = trunc_page(va);
5720 offset = va & PAGE_MASK;
5721 size = round_page(offset + size);
5722
5723 /*
5724 * Only supported on kernel virtual addresses above the recursive map.
5725 */
5726 if (base < VM_MIN_KERNEL_ADDRESS)
5727 return (EINVAL);
5728
5729 cache_bits_pde = pmap_cache_bits(kernel_pmap, mode, true);
5730 cache_bits_pte = pmap_cache_bits(kernel_pmap, mode, false);
5731 changed = false;
5732
5733 /*
5734 * Pages that aren't mapped aren't supported. Also break down
5735 * 2/4MB pages into 4KB pages if required.
5736 */
5737 PMAP_LOCK(kernel_pmap);
5738 for (tmpva = base; tmpva < base + size; ) {
5739 pde = pmap_pde(kernel_pmap, tmpva);
5740 if (*pde == 0) {
5741 PMAP_UNLOCK(kernel_pmap);
5742 return (EINVAL);
5743 }
5744 if (*pde & PG_PS) {
5745 /*
5746 * If the current 2/4MB page already has
5747 * the required memory type, then we need not
5748 * demote this page. Just increment tmpva to
5749 * the next 2/4MB page frame.
5750 */
5751 if ((*pde & PG_PDE_CACHE) == cache_bits_pde) {
5752 tmpva = trunc_4mpage(tmpva) + NBPDR;
5753 continue;
5754 }
5755
5756 /*
5757 * If the current offset aligns with a 2/4MB
5758 * page frame and there is at least 2/4MB left
5759 * within the range, then we need not break
5760 * down this page into 4KB pages.
5761 */
5762 if ((tmpva & PDRMASK) == 0 &&
5763 tmpva + PDRMASK < base + size) {
5764 tmpva += NBPDR;
5765 continue;
5766 }
5767 if (!pmap_demote_pde(kernel_pmap, pde, tmpva)) {
5768 PMAP_UNLOCK(kernel_pmap);
5769 return (ENOMEM);
5770 }
5771 }
5772 pte = vtopte(tmpva);
5773 if (*pte == 0) {
5774 PMAP_UNLOCK(kernel_pmap);
5775 return (EINVAL);
5776 }
5777 tmpva += PAGE_SIZE;
5778 }
5779 PMAP_UNLOCK(kernel_pmap);
5780
5781 /*
5782 * Ok, all the pages exist, so run through them updating their
5783 * cache mode if required.
5784 */
5785 for (tmpva = base; tmpva < base + size; ) {
5786 pde = pmap_pde(kernel_pmap, tmpva);
5787 if (*pde & PG_PS) {
5788 if ((*pde & PG_PDE_CACHE) != cache_bits_pde) {
5789 pmap_pde_attr(pde, cache_bits_pde);
5790 changed = true;
5791 }
5792 tmpva = trunc_4mpage(tmpva) + NBPDR;
5793 } else {
5794 pte = vtopte(tmpva);
5795 if ((*pte & PG_PTE_CACHE) != cache_bits_pte) {
5796 pmap_pte_attr(pte, cache_bits_pte);
5797 changed = true;
5798 }
5799 tmpva += PAGE_SIZE;
5800 }
5801 }
5802
5803 /*
5804 * Flush CPU caches to make sure any data isn't cached that
5805 * shouldn't be, etc.
5806 */
5807 if (changed) {
5808 pmap_invalidate_range_int(kernel_pmap, base, tmpva);
5809 pmap_invalidate_cache_range(base, tmpva);
5810 }
5811 return (0);
5812 }
5813
5814 /*
5815 * Perform the pmap work for mincore(2). If the page is not both referenced and
5816 * modified by this pmap, returns its physical address so that the caller can
5817 * find other mappings.
5818 */
5819 static int
__CONCAT(PMTYPE,mincore)5820 __CONCAT(PMTYPE, mincore)(pmap_t pmap, vm_offset_t addr, vm_paddr_t *pap)
5821 {
5822 pd_entry_t pde;
5823 pt_entry_t pte;
5824 vm_paddr_t pa;
5825 int val;
5826
5827 PMAP_LOCK(pmap);
5828 pde = *pmap_pde(pmap, addr);
5829 if (pde != 0) {
5830 if ((pde & PG_PS) != 0) {
5831 pte = pde;
5832 /* Compute the physical address of the 4KB page. */
5833 pa = ((pde & PG_PS_FRAME) | (addr & PDRMASK)) &
5834 PG_FRAME;
5835 val = MINCORE_PSIND(1);
5836 } else {
5837 pte = pmap_pte_ufast(pmap, addr, pde);
5838 pa = pte & PG_FRAME;
5839 val = 0;
5840 }
5841 } else {
5842 pte = 0;
5843 pa = 0;
5844 val = 0;
5845 }
5846 if ((pte & PG_V) != 0) {
5847 val |= MINCORE_INCORE;
5848 if ((pte & (PG_M | PG_RW)) == (PG_M | PG_RW))
5849 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER;
5850 if ((pte & PG_A) != 0)
5851 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER;
5852 }
5853 if ((val & (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER)) !=
5854 (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER) &&
5855 (pte & (PG_MANAGED | PG_V)) == (PG_MANAGED | PG_V)) {
5856 *pap = pa;
5857 }
5858 PMAP_UNLOCK(pmap);
5859 return (val);
5860 }
5861
5862 static void
__CONCAT(PMTYPE,activate)5863 __CONCAT(PMTYPE, activate)(struct thread *td)
5864 {
5865 pmap_t pmap, oldpmap;
5866 u_int cpuid;
5867 u_int32_t cr3;
5868
5869 critical_enter();
5870 pmap = vmspace_pmap(td->td_proc->p_vmspace);
5871 oldpmap = PCPU_GET(curpmap);
5872 cpuid = PCPU_GET(cpuid);
5873 #if defined(SMP)
5874 CPU_CLR_ATOMIC(cpuid, &oldpmap->pm_active);
5875 CPU_SET_ATOMIC(cpuid, &pmap->pm_active);
5876 #else
5877 CPU_CLR(cpuid, &oldpmap->pm_active);
5878 CPU_SET(cpuid, &pmap->pm_active);
5879 #endif
5880 #ifdef PMAP_PAE_COMP
5881 cr3 = vtophys(pmap->pm_pdpt);
5882 #else
5883 cr3 = vtophys(pmap->pm_pdir);
5884 #endif
5885 /*
5886 * pmap_activate is for the current thread on the current cpu
5887 */
5888 td->td_pcb->pcb_cr3 = cr3;
5889 PCPU_SET(curpmap, pmap);
5890 critical_exit();
5891 }
5892
5893 static void
__CONCAT(PMTYPE,activate_boot)5894 __CONCAT(PMTYPE, activate_boot)(pmap_t pmap)
5895 {
5896 u_int cpuid;
5897
5898 cpuid = PCPU_GET(cpuid);
5899 #if defined(SMP)
5900 CPU_SET_ATOMIC(cpuid, &pmap->pm_active);
5901 #else
5902 CPU_SET(cpuid, &pmap->pm_active);
5903 #endif
5904 PCPU_SET(curpmap, pmap);
5905 }
5906
5907 /*
5908 * Increase the starting virtual address of the given mapping if a
5909 * different alignment might result in more superpage mappings.
5910 */
5911 static void
__CONCAT(PMTYPE,align_superpage)5912 __CONCAT(PMTYPE, align_superpage)(vm_object_t object, vm_ooffset_t offset,
5913 vm_offset_t *addr, vm_size_t size)
5914 {
5915 vm_offset_t superpage_offset;
5916
5917 if (size < NBPDR)
5918 return;
5919 if (object != NULL && (object->flags & OBJ_COLORED) != 0)
5920 offset += ptoa(object->pg_color);
5921 superpage_offset = offset & PDRMASK;
5922 if (size - ((NBPDR - superpage_offset) & PDRMASK) < NBPDR ||
5923 (*addr & PDRMASK) == superpage_offset)
5924 return;
5925 if ((*addr & PDRMASK) < superpage_offset)
5926 *addr = (*addr & ~PDRMASK) + superpage_offset;
5927 else
5928 *addr = ((*addr + PDRMASK) & ~PDRMASK) + superpage_offset;
5929 }
5930
5931 static vm_offset_t
__CONCAT(PMTYPE,quick_enter_page)5932 __CONCAT(PMTYPE, quick_enter_page)(vm_page_t m)
5933 {
5934 vm_offset_t qaddr;
5935 pt_entry_t *pte;
5936
5937 critical_enter();
5938 qaddr = PCPU_GET(qmap_addr);
5939 pte = vtopte(qaddr);
5940
5941 KASSERT(*pte == 0,
5942 ("pmap_quick_enter_page: PTE busy %#jx", (uintmax_t)*pte));
5943 *pte = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) | PG_A | PG_M |
5944 pmap_cache_bits(kernel_pmap, pmap_page_get_memattr(m), false);
5945 invlpg(qaddr);
5946
5947 return (qaddr);
5948 }
5949
5950 static void
__CONCAT(PMTYPE,quick_remove_page)5951 __CONCAT(PMTYPE, quick_remove_page)(vm_offset_t addr)
5952 {
5953 vm_offset_t qaddr;
5954 pt_entry_t *pte;
5955
5956 qaddr = PCPU_GET(qmap_addr);
5957 pte = vtopte(qaddr);
5958
5959 KASSERT(*pte != 0, ("pmap_quick_remove_page: PTE not in use"));
5960 KASSERT(addr == qaddr, ("pmap_quick_remove_page: invalid address"));
5961
5962 *pte = 0;
5963 critical_exit();
5964 }
5965
5966 static vmem_t *pmap_trm_arena;
5967 static vmem_addr_t pmap_trm_arena_last = PMAP_TRM_MIN_ADDRESS;
5968 static int trm_guard = PAGE_SIZE;
5969
5970 static int
pmap_trm_import(void * unused __unused,vmem_size_t size,int flags,vmem_addr_t * addrp)5971 pmap_trm_import(void *unused __unused, vmem_size_t size, int flags,
5972 vmem_addr_t *addrp)
5973 {
5974 vm_page_t m;
5975 vmem_addr_t af, addr, prev_addr;
5976 pt_entry_t *trm_pte;
5977
5978 prev_addr = atomic_load_int(&pmap_trm_arena_last);
5979 size = round_page(size) + trm_guard;
5980 for (;;) {
5981 if (prev_addr + size < prev_addr || prev_addr + size < size ||
5982 prev_addr + size > PMAP_TRM_MAX_ADDRESS)
5983 return (ENOMEM);
5984 addr = prev_addr + size;
5985 if (atomic_fcmpset_int(&pmap_trm_arena_last, &prev_addr, addr))
5986 break;
5987 }
5988 prev_addr += trm_guard;
5989 trm_pte = PTmap + atop(prev_addr);
5990 for (af = prev_addr; af < addr; af += PAGE_SIZE) {
5991 m = vm_page_alloc_noobj(VM_ALLOC_WIRED | VM_ALLOC_WAITOK);
5992 pte_store(&trm_pte[atop(af - prev_addr)], VM_PAGE_TO_PHYS(m) |
5993 PG_M | PG_A | PG_RW | PG_V | pgeflag |
5994 pmap_cache_bits(kernel_pmap, VM_MEMATTR_DEFAULT, false));
5995 }
5996 *addrp = prev_addr;
5997 return (0);
5998 }
5999
6000 void
pmap_init_trm(void)6001 pmap_init_trm(void)
6002 {
6003 vm_page_t pd_m;
6004
6005 TUNABLE_INT_FETCH("machdep.trm_guard", &trm_guard);
6006 if ((trm_guard & PAGE_MASK) != 0)
6007 trm_guard = 0;
6008 pmap_trm_arena = vmem_create("i386trampoline", 0, 0, 1, 0, M_WAITOK);
6009 vmem_set_import(pmap_trm_arena, pmap_trm_import, NULL, NULL, PAGE_SIZE);
6010 pd_m = vm_page_alloc_noobj(VM_ALLOC_WIRED | VM_ALLOC_WAITOK |
6011 VM_ALLOC_ZERO);
6012 PTD[TRPTDI] = VM_PAGE_TO_PHYS(pd_m) | PG_M | PG_A | PG_RW | PG_V |
6013 pmap_cache_bits(kernel_pmap, VM_MEMATTR_DEFAULT, true);
6014 }
6015
6016 static void *
__CONCAT(PMTYPE,trm_alloc)6017 __CONCAT(PMTYPE, trm_alloc)(size_t size, int flags)
6018 {
6019 vmem_addr_t res;
6020 int error;
6021
6022 MPASS((flags & ~(M_WAITOK | M_NOWAIT | M_ZERO)) == 0);
6023 error = vmem_xalloc(pmap_trm_arena, roundup2(size, 4), sizeof(int),
6024 0, 0, VMEM_ADDR_MIN, VMEM_ADDR_MAX, flags | M_FIRSTFIT, &res);
6025 if (error != 0)
6026 return (NULL);
6027 if ((flags & M_ZERO) != 0)
6028 bzero((void *)res, size);
6029 return ((void *)res);
6030 }
6031
6032 static void
__CONCAT(PMTYPE,trm_free)6033 __CONCAT(PMTYPE, trm_free)(void *addr, size_t size)
6034 {
6035
6036 vmem_free(pmap_trm_arena, (uintptr_t)addr, roundup2(size, 4));
6037 }
6038
6039 static void
__CONCAT(PMTYPE,ksetrw)6040 __CONCAT(PMTYPE, ksetrw)(vm_offset_t va)
6041 {
6042
6043 *vtopte(va) |= PG_RW;
6044 }
6045
6046 static void
__CONCAT(PMTYPE,remap_lowptdi)6047 __CONCAT(PMTYPE, remap_lowptdi)(bool enable)
6048 {
6049
6050 PTD[KPTDI] = enable ? PTD[LOWPTDI] : 0;
6051 invltlb_glob();
6052 }
6053
6054 static vm_offset_t
__CONCAT(PMTYPE,get_map_low)6055 __CONCAT(PMTYPE, get_map_low)(void)
6056 {
6057
6058 return (PMAP_MAP_LOW);
6059 }
6060
6061 static vm_offset_t
__CONCAT(PMTYPE,get_vm_maxuser_address)6062 __CONCAT(PMTYPE, get_vm_maxuser_address)(void)
6063 {
6064
6065 return (VM_MAXUSER_ADDRESS);
6066 }
6067
6068 static vm_paddr_t
__CONCAT(PMTYPE,pg_frame)6069 __CONCAT(PMTYPE, pg_frame)(vm_paddr_t pa)
6070 {
6071
6072 return (pa & PG_FRAME);
6073 }
6074
6075 static void
__CONCAT(PMTYPE,sf_buf_map)6076 __CONCAT(PMTYPE, sf_buf_map)(struct sf_buf *sf)
6077 {
6078 pt_entry_t opte, *ptep;
6079
6080 /*
6081 * Update the sf_buf's virtual-to-physical mapping, flushing the
6082 * virtual address from the TLB. Since the reference count for
6083 * the sf_buf's old mapping was zero, that mapping is not
6084 * currently in use. Consequently, there is no need to exchange
6085 * the old and new PTEs atomically, even under PAE.
6086 */
6087 ptep = vtopte(sf->kva);
6088 opte = *ptep;
6089 *ptep = VM_PAGE_TO_PHYS(sf->m) | PG_RW | PG_V |
6090 pmap_cache_bits(kernel_pmap, sf->m->md.pat_mode, false);
6091
6092 /*
6093 * Avoid unnecessary TLB invalidations: If the sf_buf's old
6094 * virtual-to-physical mapping was not used, then any processor
6095 * that has invalidated the sf_buf's virtual address from its TLB
6096 * since the last used mapping need not invalidate again.
6097 */
6098 #ifdef SMP
6099 if ((opte & (PG_V | PG_A)) == (PG_V | PG_A))
6100 CPU_ZERO(&sf->cpumask);
6101 #else
6102 if ((opte & (PG_V | PG_A)) == (PG_V | PG_A))
6103 pmap_invalidate_page_int(kernel_pmap, sf->kva);
6104 #endif
6105 }
6106
6107 static void
__CONCAT(PMTYPE,cp_slow0_map)6108 __CONCAT(PMTYPE, cp_slow0_map)(vm_offset_t kaddr, int plen, vm_page_t *ma)
6109 {
6110 pt_entry_t *pte;
6111 int i;
6112
6113 for (i = 0, pte = vtopte(kaddr); i < plen; i++, pte++) {
6114 *pte = PG_V | PG_RW | PG_A | PG_M | VM_PAGE_TO_PHYS(ma[i]) |
6115 pmap_cache_bits(kernel_pmap, pmap_page_get_memattr(ma[i]),
6116 false);
6117 invlpg(kaddr + ptoa(i));
6118 }
6119 }
6120
6121 static u_int
__CONCAT(PMTYPE,get_kcr3)6122 __CONCAT(PMTYPE, get_kcr3)(void)
6123 {
6124
6125 #ifdef PMAP_PAE_COMP
6126 return ((u_int)IdlePDPT);
6127 #else
6128 return ((u_int)IdlePTD);
6129 #endif
6130 }
6131
6132 static u_int
__CONCAT(PMTYPE,get_cr3)6133 __CONCAT(PMTYPE, get_cr3)(pmap_t pmap)
6134 {
6135
6136 #ifdef PMAP_PAE_COMP
6137 return ((u_int)vtophys(pmap->pm_pdpt));
6138 #else
6139 return ((u_int)vtophys(pmap->pm_pdir));
6140 #endif
6141 }
6142
6143 static caddr_t
__CONCAT(PMTYPE,cmap3)6144 __CONCAT(PMTYPE, cmap3)(vm_paddr_t pa, u_int pte_bits)
6145 {
6146 pt_entry_t *pte;
6147
6148 pte = CMAP3;
6149 *pte = pa | pte_bits;
6150 invltlb();
6151 return (CADDR3);
6152 }
6153
6154 static void
__CONCAT(PMTYPE,basemem_setup)6155 __CONCAT(PMTYPE, basemem_setup)(u_int basemem)
6156 {
6157 pt_entry_t *pte;
6158 int i;
6159
6160 /*
6161 * Map pages between basemem and ISA_HOLE_START, if any, r/w into
6162 * the vm86 page table so that vm86 can scribble on them using
6163 * the vm86 map too. XXX: why 2 ways for this and only 1 way for
6164 * page 0, at least as initialized here?
6165 */
6166 pte = (pt_entry_t *)vm86paddr;
6167 for (i = basemem / 4; i < 160; i++)
6168 pte[i] = (i << PAGE_SHIFT) | PG_V | PG_RW | PG_U;
6169 }
6170
6171 struct bios16_pmap_handle {
6172 pt_entry_t *pte;
6173 pd_entry_t *ptd;
6174 pt_entry_t orig_ptd;
6175 };
6176
6177 static void *
__CONCAT(PMTYPE,bios16_enter)6178 __CONCAT(PMTYPE, bios16_enter)(void)
6179 {
6180 struct bios16_pmap_handle *h;
6181
6182 /*
6183 * no page table, so create one and install it.
6184 */
6185 h = malloc(sizeof(struct bios16_pmap_handle), M_TEMP, M_WAITOK);
6186 h->pte = (pt_entry_t *)malloc(PAGE_SIZE, M_TEMP, M_WAITOK);
6187 h->ptd = IdlePTD;
6188 *h->pte = vm86phystk | PG_RW | PG_V;
6189 h->orig_ptd = *h->ptd;
6190 *h->ptd = vtophys(h->pte) | PG_RW | PG_V;
6191 pmap_invalidate_all_int(kernel_pmap); /* XXX insurance for now */
6192 return (h);
6193 }
6194
6195 static void
__CONCAT(PMTYPE,bios16_leave)6196 __CONCAT(PMTYPE, bios16_leave)(void *arg)
6197 {
6198 struct bios16_pmap_handle *h;
6199
6200 h = arg;
6201 *h->ptd = h->orig_ptd; /* remove page table */
6202 /*
6203 * XXX only needs to be invlpg(0) but that doesn't work on the 386
6204 */
6205 pmap_invalidate_all_int(kernel_pmap);
6206 free(h->pte, M_TEMP); /* ... and free it */
6207 }
6208
6209 struct pmap_kernel_map_range {
6210 vm_offset_t sva;
6211 pt_entry_t attrs;
6212 int ptes;
6213 int pdes;
6214 int pdpes;
6215 };
6216
6217 static void
sysctl_kmaps_dump(struct sbuf * sb,struct pmap_kernel_map_range * range,vm_offset_t eva)6218 sysctl_kmaps_dump(struct sbuf *sb, struct pmap_kernel_map_range *range,
6219 vm_offset_t eva)
6220 {
6221 const char *mode;
6222 int i, pat_idx;
6223
6224 if (eva <= range->sva)
6225 return;
6226
6227 pat_idx = pmap_pat_index(kernel_pmap, range->attrs, true);
6228 for (i = 0; i < PAT_INDEX_SIZE; i++)
6229 if (pat_index[i] == pat_idx)
6230 break;
6231
6232 switch (i) {
6233 case PAT_WRITE_BACK:
6234 mode = "WB";
6235 break;
6236 case PAT_WRITE_THROUGH:
6237 mode = "WT";
6238 break;
6239 case PAT_UNCACHEABLE:
6240 mode = "UC";
6241 break;
6242 case PAT_UNCACHED:
6243 mode = "U-";
6244 break;
6245 case PAT_WRITE_PROTECTED:
6246 mode = "WP";
6247 break;
6248 case PAT_WRITE_COMBINING:
6249 mode = "WC";
6250 break;
6251 default:
6252 printf("%s: unknown PAT mode %#x for range 0x%08x-0x%08x\n",
6253 __func__, pat_idx, range->sva, eva);
6254 mode = "??";
6255 break;
6256 }
6257
6258 sbuf_printf(sb, "0x%08x-0x%08x r%c%c%c%c %s %d %d %d\n",
6259 range->sva, eva,
6260 (range->attrs & PG_RW) != 0 ? 'w' : '-',
6261 (range->attrs & pg_nx) != 0 ? '-' : 'x',
6262 (range->attrs & PG_U) != 0 ? 'u' : 's',
6263 (range->attrs & PG_G) != 0 ? 'g' : '-',
6264 mode, range->pdpes, range->pdes, range->ptes);
6265
6266 /* Reset to sentinel value. */
6267 range->sva = 0xffffffff;
6268 }
6269
6270 /*
6271 * Determine whether the attributes specified by a page table entry match those
6272 * being tracked by the current range. This is not quite as simple as a direct
6273 * flag comparison since some PAT modes have multiple representations.
6274 */
6275 static bool
sysctl_kmaps_match(struct pmap_kernel_map_range * range,pt_entry_t attrs)6276 sysctl_kmaps_match(struct pmap_kernel_map_range *range, pt_entry_t attrs)
6277 {
6278 pt_entry_t diff, mask;
6279
6280 mask = pg_nx | PG_G | PG_RW | PG_U | PG_PDE_CACHE;
6281 diff = (range->attrs ^ attrs) & mask;
6282 if (diff == 0)
6283 return (true);
6284 if ((diff & ~PG_PDE_PAT) == 0 &&
6285 pmap_pat_index(kernel_pmap, range->attrs, true) ==
6286 pmap_pat_index(kernel_pmap, attrs, true))
6287 return (true);
6288 return (false);
6289 }
6290
6291 static void
sysctl_kmaps_reinit(struct pmap_kernel_map_range * range,vm_offset_t va,pt_entry_t attrs)6292 sysctl_kmaps_reinit(struct pmap_kernel_map_range *range, vm_offset_t va,
6293 pt_entry_t attrs)
6294 {
6295
6296 memset(range, 0, sizeof(*range));
6297 range->sva = va;
6298 range->attrs = attrs;
6299 }
6300
6301 /*
6302 * Given a leaf PTE, derive the mapping's attributes. If they do not match
6303 * those of the current run, dump the address range and its attributes, and
6304 * begin a new run.
6305 */
6306 static void
sysctl_kmaps_check(struct sbuf * sb,struct pmap_kernel_map_range * range,vm_offset_t va,pd_entry_t pde,pt_entry_t pte)6307 sysctl_kmaps_check(struct sbuf *sb, struct pmap_kernel_map_range *range,
6308 vm_offset_t va, pd_entry_t pde, pt_entry_t pte)
6309 {
6310 pt_entry_t attrs;
6311
6312 attrs = pde & (PG_RW | PG_U | pg_nx);
6313
6314 if ((pde & PG_PS) != 0) {
6315 attrs |= pde & (PG_G | PG_PDE_CACHE);
6316 } else if (pte != 0) {
6317 attrs |= pte & pg_nx;
6318 attrs &= pg_nx | (pte & (PG_RW | PG_U));
6319 attrs |= pte & (PG_G | PG_PTE_CACHE);
6320
6321 /* Canonicalize by always using the PDE PAT bit. */
6322 if ((attrs & PG_PTE_PAT) != 0)
6323 attrs ^= PG_PDE_PAT | PG_PTE_PAT;
6324 }
6325
6326 if (range->sva > va || !sysctl_kmaps_match(range, attrs)) {
6327 sysctl_kmaps_dump(sb, range, va);
6328 sysctl_kmaps_reinit(range, va, attrs);
6329 }
6330 }
6331
6332 static int
__CONCAT(PMTYPE,sysctl_kmaps)6333 __CONCAT(PMTYPE, sysctl_kmaps)(SYSCTL_HANDLER_ARGS)
6334 {
6335 struct pmap_kernel_map_range range;
6336 struct sbuf sbuf, *sb;
6337 pd_entry_t pde;
6338 pt_entry_t *pt, pte;
6339 vm_offset_t sva;
6340 int error;
6341 u_int i, k;
6342
6343 error = sysctl_wire_old_buffer(req, 0);
6344 if (error != 0)
6345 return (error);
6346 sb = &sbuf;
6347 sbuf_new_for_sysctl(sb, NULL, PAGE_SIZE, req);
6348
6349 /* Sentinel value. */
6350 range.sva = 0xffffffff;
6351
6352 /*
6353 * Iterate over the kernel page tables without holding the
6354 * kernel pmap lock. Kernel page table pages are never freed,
6355 * so at worst we will observe inconsistencies in the output.
6356 */
6357 for (sva = 0, i = 0; i < NPTEPG * NPGPTD * NPDEPG ;) {
6358 if (i == 0)
6359 sbuf_printf(sb, "\nLow PDE:\n");
6360 else if (i == LOWPTDI * NPTEPG)
6361 sbuf_printf(sb, "Low PDE dup:\n");
6362 else if (i == PTDPTDI * NPTEPG)
6363 sbuf_printf(sb, "Recursive map:\n");
6364 else if (i == KERNPTDI * NPTEPG)
6365 sbuf_printf(sb, "Kernel base:\n");
6366 else if (i == TRPTDI * NPTEPG)
6367 sbuf_printf(sb, "Trampoline:\n");
6368 pde = IdlePTD[sva >> PDRSHIFT];
6369 if ((pde & PG_V) == 0) {
6370 sva = rounddown2(sva, NBPDR);
6371 sysctl_kmaps_dump(sb, &range, sva);
6372 sva += NBPDR;
6373 i += NPTEPG;
6374 continue;
6375 }
6376 if ((pde & PG_PS) != 0) {
6377 sysctl_kmaps_check(sb, &range, sva, pde, 0);
6378 range.pdes++;
6379 sva += NBPDR;
6380 i += NPTEPG;
6381 continue;
6382 }
6383 for (pt = vtopte(sva), k = 0; k < NPTEPG; i++, k++, pt++,
6384 sva += PAGE_SIZE) {
6385 pte = *pt;
6386 if ((pte & PG_V) == 0) {
6387 sysctl_kmaps_dump(sb, &range, sva);
6388 continue;
6389 }
6390 sysctl_kmaps_check(sb, &range, sva, pde, pte);
6391 range.ptes++;
6392 }
6393 }
6394
6395 error = sbuf_finish(sb);
6396 sbuf_delete(sb);
6397 return (error);
6398 }
6399
6400 #define PMM(a) \
6401 .pm_##a = __CONCAT(PMTYPE, a),
6402
6403 struct pmap_methods __CONCAT(PMTYPE, methods) = {
6404 PMM(ksetrw)
6405 PMM(remap_lower)
6406 PMM(remap_lowptdi)
6407 PMM(align_superpage)
6408 PMM(quick_enter_page)
6409 PMM(quick_remove_page)
6410 PMM(trm_alloc)
6411 PMM(trm_free)
6412 PMM(get_map_low)
6413 PMM(get_vm_maxuser_address)
6414 PMM(kextract)
6415 PMM(pg_frame)
6416 PMM(sf_buf_map)
6417 PMM(cp_slow0_map)
6418 PMM(get_kcr3)
6419 PMM(get_cr3)
6420 PMM(cmap3)
6421 PMM(basemem_setup)
6422 PMM(set_nx)
6423 PMM(bios16_enter)
6424 PMM(bios16_leave)
6425 PMM(bootstrap)
6426 PMM(is_valid_memattr)
6427 PMM(cache_bits)
6428 PMM(ps_enabled)
6429 PMM(pinit0)
6430 PMM(pinit)
6431 PMM(activate)
6432 PMM(activate_boot)
6433 PMM(advise)
6434 PMM(clear_modify)
6435 PMM(change_attr)
6436 PMM(mincore)
6437 PMM(copy)
6438 PMM(copy_page)
6439 PMM(copy_pages)
6440 PMM(zero_page)
6441 PMM(zero_page_area)
6442 PMM(enter)
6443 PMM(enter_object)
6444 PMM(enter_quick)
6445 PMM(kenter_temporary)
6446 PMM(object_init_pt)
6447 PMM(unwire)
6448 PMM(page_exists_quick)
6449 PMM(page_wired_mappings)
6450 PMM(page_is_mapped)
6451 PMM(remove_pages)
6452 PMM(is_modified)
6453 PMM(is_prefaultable)
6454 PMM(is_referenced)
6455 PMM(remove_write)
6456 PMM(ts_referenced)
6457 PMM(mapdev_attr)
6458 PMM(unmapdev)
6459 PMM(page_set_memattr)
6460 PMM(extract)
6461 PMM(extract_and_hold)
6462 PMM(map)
6463 PMM(qenter)
6464 PMM(qremove)
6465 PMM(release)
6466 PMM(remove)
6467 PMM(protect)
6468 PMM(remove_all)
6469 PMM(init)
6470 PMM(init_pat)
6471 PMM(growkernel)
6472 PMM(invalidate_page)
6473 PMM(invalidate_range)
6474 PMM(invalidate_all)
6475 PMM(invalidate_cache)
6476 PMM(flush_page)
6477 PMM(kenter)
6478 PMM(kremove)
6479 PMM(sysctl_kmaps)
6480 };
6481