1 /*-
2 * Copyright (c) 2013-2021, Mellanox Technologies, Ltd. All rights reserved.
3 * Copyright (c) 2022 NVIDIA corporation & affiliates.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 */
26
27 #include "opt_rss.h"
28 #include "opt_ratelimit.h"
29 #include "opt_ipsec.h"
30
31 #include <linux/kmod.h>
32 #include <linux/module.h>
33 #include <linux/errno.h>
34 #include <linux/pci.h>
35 #include <linux/dma-mapping.h>
36 #include <linux/slab.h>
37 #include <linux/io-mapping.h>
38 #include <linux/interrupt.h>
39 #include <linux/hardirq.h>
40 #include <dev/mlx5/driver.h>
41 #include <dev/mlx5/cq.h>
42 #include <dev/mlx5/qp.h>
43 #include <dev/mlx5/srq.h>
44 #include <dev/mlx5/mpfs.h>
45 #include <dev/mlx5/vport.h>
46 #include <linux/delay.h>
47 #include <dev/mlx5/mlx5_ifc.h>
48 #include <dev/mlx5/mlx5_fpga/core.h>
49 #include <dev/mlx5/mlx5_lib/mlx5.h>
50 #include <dev/mlx5/mlx5_core/mlx5_core.h>
51 #include <dev/mlx5/mlx5_core/eswitch.h>
52 #include <dev/mlx5/mlx5_core/fs_core.h>
53 #include <dev/mlx5/mlx5_core/diag_cnt.h>
54 #ifdef PCI_IOV
55 #include <sys/nv.h>
56 #include <sys/socket.h>
57 #include <dev/pci/pci_iov.h>
58 #include <sys/iov_schema.h>
59 #include <sys/iov.h>
60 #include <net/if.h>
61 #include <net/if_vlan_var.h>
62 #endif
63
64 static const char mlx5_version[] = "Mellanox Core driver "
65 DRIVER_VERSION " (" DRIVER_RELDATE ")";
66 MODULE_DESCRIPTION("Mellanox ConnectX-4 and onwards core driver");
67 MODULE_LICENSE("Dual BSD/GPL");
68 MODULE_DEPEND(mlx5, linuxkpi, 1, 1, 1);
69 MODULE_DEPEND(mlx5, mlxfw, 1, 1, 1);
70 MODULE_DEPEND(mlx5, firmware, 1, 1, 1);
71 #ifdef IPSEC_OFFLOAD
72 MODULE_DEPEND(mlx5, ipsec, 1, 1, 1);
73 #endif
74 MODULE_VERSION(mlx5, 1);
75
76 SYSCTL_NODE(_hw, OID_AUTO, mlx5, CTLFLAG_RW | CTLFLAG_MPSAFE, 0,
77 "mlx5 hardware controls");
78
79 int mlx5_core_debug_mask;
80 SYSCTL_INT(_hw_mlx5, OID_AUTO, debug_mask, CTLFLAG_RWTUN,
81 &mlx5_core_debug_mask, 0,
82 "debug mask: 1 = dump cmd data, 2 = dump cmd exec time, 3 = both. Default=0");
83
84 #define MLX5_DEFAULT_PROF 2
85 static int mlx5_prof_sel = MLX5_DEFAULT_PROF;
86 SYSCTL_INT(_hw_mlx5, OID_AUTO, prof_sel, CTLFLAG_RWTUN,
87 &mlx5_prof_sel, 0,
88 "profile selector. Valid range 0 - 2");
89
90 static int mlx5_fast_unload_enabled = 1;
91 SYSCTL_INT(_hw_mlx5, OID_AUTO, fast_unload_enabled, CTLFLAG_RWTUN,
92 &mlx5_fast_unload_enabled, 0,
93 "Set to enable fast unload. Clear to disable.");
94
95 static int mlx5_core_comp_eq_size = 1024;
96 SYSCTL_INT(_hw_mlx5, OID_AUTO, comp_eq_size, CTLFLAG_RDTUN | CTLFLAG_MPSAFE,
97 &mlx5_core_comp_eq_size, 0,
98 "Set default completion EQ size between 1024 and 16384 inclusivly. Value should be power of two.");
99
100 static LIST_HEAD(intf_list);
101
102 LIST_HEAD(mlx5_dev_list);
103 DEFINE_MUTEX(mlx5_intf_mutex);
104
105 struct mlx5_device_context {
106 struct list_head list;
107 struct mlx5_interface *intf;
108 void *context;
109 };
110
111 enum {
112 MLX5_ATOMIC_REQ_MODE_BE = 0x0,
113 MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS = 0x1,
114 };
115
116 static struct mlx5_profile profiles[] = {
117 [0] = {
118 .mask = 0,
119 },
120 [1] = {
121 .mask = MLX5_PROF_MASK_QP_SIZE,
122 .log_max_qp = 12,
123 },
124 [2] = {
125 .mask = MLX5_PROF_MASK_QP_SIZE |
126 MLX5_PROF_MASK_MR_CACHE,
127 .log_max_qp = 17,
128 .mr_cache[0] = {
129 .size = 500,
130 .limit = 250
131 },
132 .mr_cache[1] = {
133 .size = 500,
134 .limit = 250
135 },
136 .mr_cache[2] = {
137 .size = 500,
138 .limit = 250
139 },
140 .mr_cache[3] = {
141 .size = 500,
142 .limit = 250
143 },
144 .mr_cache[4] = {
145 .size = 500,
146 .limit = 250
147 },
148 .mr_cache[5] = {
149 .size = 500,
150 .limit = 250
151 },
152 .mr_cache[6] = {
153 .size = 500,
154 .limit = 250
155 },
156 .mr_cache[7] = {
157 .size = 500,
158 .limit = 250
159 },
160 .mr_cache[8] = {
161 .size = 500,
162 .limit = 250
163 },
164 .mr_cache[9] = {
165 .size = 500,
166 .limit = 250
167 },
168 .mr_cache[10] = {
169 .size = 500,
170 .limit = 250
171 },
172 .mr_cache[11] = {
173 .size = 500,
174 .limit = 250
175 },
176 .mr_cache[12] = {
177 .size = 64,
178 .limit = 32
179 },
180 .mr_cache[13] = {
181 .size = 32,
182 .limit = 16
183 },
184 .mr_cache[14] = {
185 .size = 16,
186 .limit = 8
187 },
188 },
189 [3] = {
190 .mask = MLX5_PROF_MASK_QP_SIZE,
191 .log_max_qp = 17,
192 },
193 };
194
195 static int
mlx5_core_get_comp_eq_size(void)196 mlx5_core_get_comp_eq_size(void)
197 {
198 int value = mlx5_core_comp_eq_size;
199
200 if (value < 1024)
201 value = 1024;
202 else if (value > 16384)
203 value = 16384;
204
205 /* make value power of two, rounded down */
206 while (value & (value - 1))
207 value &= (value - 1);
208 return (value);
209 }
210
mlx5_set_driver_version(struct mlx5_core_dev * dev)211 static void mlx5_set_driver_version(struct mlx5_core_dev *dev)
212 {
213 const size_t driver_ver_sz =
214 MLX5_FLD_SZ_BYTES(set_driver_version_in, driver_version);
215 u8 in[MLX5_ST_SZ_BYTES(set_driver_version_in)] = {};
216 u8 out[MLX5_ST_SZ_BYTES(set_driver_version_out)] = {};
217 char *string;
218
219 if (!MLX5_CAP_GEN(dev, driver_version))
220 return;
221
222 string = MLX5_ADDR_OF(set_driver_version_in, in, driver_version);
223
224 snprintf(string, driver_ver_sz, "FreeBSD,mlx5_core,%u.%u.%u," DRIVER_VERSION,
225 __FreeBSD_version / 100000, (__FreeBSD_version / 1000) % 100,
226 __FreeBSD_version % 1000);
227
228 /* Send the command */
229 MLX5_SET(set_driver_version_in, in, opcode,
230 MLX5_CMD_OP_SET_DRIVER_VERSION);
231
232 mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
233 }
234
235 #ifdef PCI_IOV
236 static const char iov_mac_addr_name[] = "mac-addr";
237 static const char iov_vlan_name[] = "vlan";
238 static const char iov_node_guid_name[] = "node-guid";
239 static const char iov_port_guid_name[] = "port-guid";
240 #endif
241
set_dma_caps(struct pci_dev * pdev)242 static int set_dma_caps(struct pci_dev *pdev)
243 {
244 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
245 int err;
246
247 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
248 if (err) {
249 mlx5_core_warn(dev, "couldn't set 64-bit PCI DMA mask\n");
250 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
251 if (err) {
252 mlx5_core_err(dev, "Can't set PCI DMA mask, aborting\n");
253 return err;
254 }
255 }
256
257 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
258 if (err) {
259 mlx5_core_warn(dev, "couldn't set 64-bit consistent PCI DMA mask\n");
260 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
261 if (err) {
262 mlx5_core_err(dev, "Can't set consistent PCI DMA mask, aborting\n");
263 return err;
264 }
265 }
266
267 dma_set_max_seg_size(&pdev->dev, 2u * 1024 * 1024 * 1024);
268 return err;
269 }
270
mlx5_pci_read_power_status(struct mlx5_core_dev * dev,u16 * p_power,u8 * p_status)271 int mlx5_pci_read_power_status(struct mlx5_core_dev *dev,
272 u16 *p_power, u8 *p_status)
273 {
274 u32 in[MLX5_ST_SZ_DW(mpein_reg)] = {};
275 u32 out[MLX5_ST_SZ_DW(mpein_reg)] = {};
276 int err;
277
278 err = mlx5_core_access_reg(dev, in, sizeof(in), out, sizeof(out),
279 MLX5_ACCESS_REG_SUMMARY_CTRL_ID_MPEIN, 0, 0);
280
281 *p_status = MLX5_GET(mpein_reg, out, pwr_status);
282 *p_power = MLX5_GET(mpein_reg, out, pci_power);
283 return err;
284 }
285
mlx5_pci_enable_device(struct mlx5_core_dev * dev)286 static int mlx5_pci_enable_device(struct mlx5_core_dev *dev)
287 {
288 struct pci_dev *pdev = dev->pdev;
289 int err = 0;
290
291 mutex_lock(&dev->pci_status_mutex);
292 if (dev->pci_status == MLX5_PCI_STATUS_DISABLED) {
293 err = pci_enable_device(pdev);
294 if (!err)
295 dev->pci_status = MLX5_PCI_STATUS_ENABLED;
296 }
297 mutex_unlock(&dev->pci_status_mutex);
298
299 return err;
300 }
301
mlx5_pci_disable_device(struct mlx5_core_dev * dev)302 static void mlx5_pci_disable_device(struct mlx5_core_dev *dev)
303 {
304 struct pci_dev *pdev = dev->pdev;
305
306 mutex_lock(&dev->pci_status_mutex);
307 if (dev->pci_status == MLX5_PCI_STATUS_ENABLED) {
308 pci_disable_device(pdev);
309 dev->pci_status = MLX5_PCI_STATUS_DISABLED;
310 }
311 mutex_unlock(&dev->pci_status_mutex);
312 }
313
request_bar(struct pci_dev * pdev)314 static int request_bar(struct pci_dev *pdev)
315 {
316 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
317 int err = 0;
318
319 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
320 mlx5_core_err(dev, "Missing registers BAR, aborting\n");
321 return -ENODEV;
322 }
323
324 err = pci_request_regions(pdev, DRIVER_NAME);
325 if (err)
326 mlx5_core_err(dev, "Couldn't get PCI resources, aborting\n");
327
328 return err;
329 }
330
release_bar(struct pci_dev * pdev)331 static void release_bar(struct pci_dev *pdev)
332 {
333 pci_release_regions(pdev);
334 }
335
mlx5_enable_msix(struct mlx5_core_dev * dev)336 static int mlx5_enable_msix(struct mlx5_core_dev *dev)
337 {
338 struct mlx5_priv *priv = &dev->priv;
339 struct mlx5_eq_table *table = &priv->eq_table;
340 int num_eqs = 1 << MLX5_CAP_GEN(dev, log_max_eq);
341 int limit = dev->msix_eqvec;
342 int nvec = MLX5_EQ_VEC_COMP_BASE;
343 int i;
344
345 if (limit > 0)
346 nvec += limit;
347 else
348 nvec += MLX5_CAP_GEN(dev, num_ports) * num_online_cpus();
349
350 if (nvec > num_eqs)
351 nvec = num_eqs;
352 if (nvec > 256)
353 nvec = 256; /* limit of firmware API */
354 if (nvec <= MLX5_EQ_VEC_COMP_BASE)
355 return -ENOMEM;
356
357 priv->msix_arr = kzalloc(nvec * sizeof(*priv->msix_arr), GFP_KERNEL);
358
359 for (i = 0; i < nvec; i++)
360 priv->msix_arr[i].entry = i;
361
362 nvec = pci_enable_msix_range(dev->pdev, priv->msix_arr,
363 MLX5_EQ_VEC_COMP_BASE + 1, nvec);
364 if (nvec < 0)
365 return nvec;
366
367 table->num_comp_vectors = nvec - MLX5_EQ_VEC_COMP_BASE;
368 return 0;
369 }
370
mlx5_disable_msix(struct mlx5_core_dev * dev)371 static void mlx5_disable_msix(struct mlx5_core_dev *dev)
372 {
373 struct mlx5_priv *priv = &dev->priv;
374
375 pci_disable_msix(dev->pdev);
376 kfree(priv->msix_arr);
377 }
378
379 struct mlx5_reg_host_endianess {
380 u8 he;
381 u8 rsvd[15];
382 };
383
384
385 #define CAP_MASK(pos, size) ((u64)((1 << (size)) - 1) << (pos))
386
387 enum {
388 MLX5_CAP_BITS_RW_MASK = CAP_MASK(MLX5_CAP_OFF_CMDIF_CSUM, 2) |
389 MLX5_DEV_CAP_FLAG_DCT |
390 MLX5_DEV_CAP_FLAG_DRAIN_SIGERR,
391 };
392
to_fw_pkey_sz(struct mlx5_core_dev * dev,u32 size)393 static u16 to_fw_pkey_sz(struct mlx5_core_dev *dev, u32 size)
394 {
395 switch (size) {
396 case 128:
397 return 0;
398 case 256:
399 return 1;
400 case 512:
401 return 2;
402 case 1024:
403 return 3;
404 case 2048:
405 return 4;
406 case 4096:
407 return 5;
408 default:
409 mlx5_core_warn(dev, "invalid pkey table size %d\n", size);
410 return 0;
411 }
412 }
413
mlx5_core_get_caps_mode(struct mlx5_core_dev * dev,enum mlx5_cap_type cap_type,enum mlx5_cap_mode cap_mode)414 static int mlx5_core_get_caps_mode(struct mlx5_core_dev *dev,
415 enum mlx5_cap_type cap_type,
416 enum mlx5_cap_mode cap_mode)
417 {
418 u8 in[MLX5_ST_SZ_BYTES(query_hca_cap_in)];
419 int out_sz = MLX5_ST_SZ_BYTES(query_hca_cap_out);
420 void *out, *hca_caps;
421 u16 opmod = (cap_type << 1) | (cap_mode & 0x01);
422 int err;
423
424 memset(in, 0, sizeof(in));
425 out = kzalloc(out_sz, GFP_KERNEL);
426
427 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);
428 MLX5_SET(query_hca_cap_in, in, op_mod, opmod);
429 err = mlx5_cmd_exec(dev, in, sizeof(in), out, out_sz);
430 if (err) {
431 mlx5_core_warn(dev,
432 "QUERY_HCA_CAP : type(%x) opmode(%x) Failed(%d)\n",
433 cap_type, cap_mode, err);
434 goto query_ex;
435 }
436
437 hca_caps = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
438
439 switch (cap_mode) {
440 case HCA_CAP_OPMOD_GET_MAX:
441 memcpy(dev->hca_caps_max[cap_type], hca_caps,
442 MLX5_UN_SZ_BYTES(hca_cap_union));
443 break;
444 case HCA_CAP_OPMOD_GET_CUR:
445 memcpy(dev->hca_caps_cur[cap_type], hca_caps,
446 MLX5_UN_SZ_BYTES(hca_cap_union));
447 break;
448 default:
449 mlx5_core_warn(dev,
450 "Tried to query dev cap type(%x) with wrong opmode(%x)\n",
451 cap_type, cap_mode);
452 err = -EINVAL;
453 break;
454 }
455 query_ex:
456 kfree(out);
457 return err;
458 }
459
mlx5_core_get_caps(struct mlx5_core_dev * dev,enum mlx5_cap_type cap_type)460 int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type)
461 {
462 int ret;
463
464 ret = mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_CUR);
465 if (ret)
466 return ret;
467
468 return mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_MAX);
469 }
470
set_caps(struct mlx5_core_dev * dev,void * in,int in_sz)471 static int set_caps(struct mlx5_core_dev *dev, void *in, int in_sz)
472 {
473 u32 out[MLX5_ST_SZ_DW(set_hca_cap_out)] = {0};
474
475 MLX5_SET(set_hca_cap_in, in, opcode, MLX5_CMD_OP_SET_HCA_CAP);
476
477 return mlx5_cmd_exec(dev, in, in_sz, out, sizeof(out));
478 }
479
handle_hca_cap(struct mlx5_core_dev * dev)480 static int handle_hca_cap(struct mlx5_core_dev *dev)
481 {
482 void *set_ctx = NULL;
483 struct mlx5_profile *prof = dev->profile;
484 int err = -ENOMEM;
485 int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in);
486 void *set_hca_cap;
487
488 set_ctx = kzalloc(set_sz, GFP_KERNEL);
489
490 err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL);
491 if (err)
492 goto query_ex;
493
494 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx,
495 capability);
496 memcpy(set_hca_cap, dev->hca_caps_cur[MLX5_CAP_GENERAL],
497 MLX5_ST_SZ_BYTES(cmd_hca_cap));
498
499 mlx5_core_dbg(dev, "Current Pkey table size %d Setting new size %d\n",
500 mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(dev, pkey_table_size)),
501 128);
502 /* we limit the size of the pkey table to 128 entries for now */
503 MLX5_SET(cmd_hca_cap, set_hca_cap, pkey_table_size,
504 to_fw_pkey_sz(dev, 128));
505
506 if (prof->mask & MLX5_PROF_MASK_QP_SIZE)
507 MLX5_SET(cmd_hca_cap, set_hca_cap, log_max_qp,
508 prof->log_max_qp);
509
510 /* disable cmdif checksum */
511 MLX5_SET(cmd_hca_cap, set_hca_cap, cmdif_checksum, 0);
512
513 /* Enable 4K UAR only when HCA supports it and page size is bigger
514 * than 4K.
515 */
516 if (MLX5_CAP_GEN_MAX(dev, uar_4k) && PAGE_SIZE > 4096)
517 MLX5_SET(cmd_hca_cap, set_hca_cap, uar_4k, 1);
518
519 /* enable drain sigerr */
520 MLX5_SET(cmd_hca_cap, set_hca_cap, drain_sigerr, 1);
521
522 MLX5_SET(cmd_hca_cap, set_hca_cap, log_uar_page_sz, PAGE_SHIFT - 12);
523
524 err = set_caps(dev, set_ctx, set_sz);
525
526 query_ex:
527 kfree(set_ctx);
528 return err;
529 }
530
handle_hca_cap_atomic(struct mlx5_core_dev * dev)531 static int handle_hca_cap_atomic(struct mlx5_core_dev *dev)
532 {
533 void *set_ctx;
534 void *set_hca_cap;
535 int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in);
536 int req_endianness;
537 int err;
538
539 if (MLX5_CAP_GEN(dev, atomic)) {
540 err = mlx5_core_get_caps(dev, MLX5_CAP_ATOMIC);
541 if (err)
542 return err;
543 } else {
544 return 0;
545 }
546
547 req_endianness =
548 MLX5_CAP_ATOMIC(dev,
549 supported_atomic_req_8B_endianess_mode_1);
550
551 if (req_endianness != MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS)
552 return 0;
553
554 set_ctx = kzalloc(set_sz, GFP_KERNEL);
555 if (!set_ctx)
556 return -ENOMEM;
557
558 MLX5_SET(set_hca_cap_in, set_ctx, op_mod,
559 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC << 1);
560 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability);
561
562 /* Set requestor to host endianness */
563 MLX5_SET(atomic_caps, set_hca_cap, atomic_req_8B_endianess_mode,
564 MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS);
565
566 err = set_caps(dev, set_ctx, set_sz);
567
568 kfree(set_ctx);
569 return err;
570 }
571
handle_hca_cap_2(struct mlx5_core_dev * dev)572 static int handle_hca_cap_2(struct mlx5_core_dev *dev)
573 {
574 int err;
575
576 if (MLX5_CAP_GEN_MAX(dev, hca_cap_2)) {
577 err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL_2);
578 if (err)
579 return err;
580 }
581
582 return 0;
583 }
584
set_hca_ctrl(struct mlx5_core_dev * dev)585 static int set_hca_ctrl(struct mlx5_core_dev *dev)
586 {
587 struct mlx5_reg_host_endianess he_in;
588 struct mlx5_reg_host_endianess he_out;
589 int err;
590
591 if (MLX5_CAP_GEN(dev, port_type) == MLX5_CAP_PORT_TYPE_ETH &&
592 !MLX5_CAP_GEN(dev, roce))
593 return 0;
594
595 memset(&he_in, 0, sizeof(he_in));
596 he_in.he = MLX5_SET_HOST_ENDIANNESS;
597 err = mlx5_core_access_reg(dev, &he_in, sizeof(he_in),
598 &he_out, sizeof(he_out),
599 MLX5_REG_HOST_ENDIANNESS, 0, 1);
600 return err;
601 }
602
mlx5_core_set_hca_defaults(struct mlx5_core_dev * dev)603 static int mlx5_core_set_hca_defaults(struct mlx5_core_dev *dev)
604 {
605 int ret = 0;
606
607 /* Disable local_lb by default */
608 if (MLX5_CAP_GEN(dev, port_type) == MLX5_CAP_PORT_TYPE_ETH)
609 ret = mlx5_nic_vport_update_local_lb(dev, false);
610
611 return ret;
612 }
613
mlx5_core_enable_hca(struct mlx5_core_dev * dev,u16 func_id)614 static int mlx5_core_enable_hca(struct mlx5_core_dev *dev, u16 func_id)
615 {
616 u32 out[MLX5_ST_SZ_DW(enable_hca_out)] = {0};
617 u32 in[MLX5_ST_SZ_DW(enable_hca_in)] = {0};
618
619 MLX5_SET(enable_hca_in, in, opcode, MLX5_CMD_OP_ENABLE_HCA);
620 MLX5_SET(enable_hca_in, in, function_id, func_id);
621 return mlx5_cmd_exec(dev, &in, sizeof(in), &out, sizeof(out));
622 }
623
mlx5_core_disable_hca(struct mlx5_core_dev * dev)624 static int mlx5_core_disable_hca(struct mlx5_core_dev *dev)
625 {
626 u32 out[MLX5_ST_SZ_DW(disable_hca_out)] = {0};
627 u32 in[MLX5_ST_SZ_DW(disable_hca_in)] = {0};
628
629 MLX5_SET(disable_hca_in, in, opcode, MLX5_CMD_OP_DISABLE_HCA);
630 return mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
631 }
632
mlx5_core_set_issi(struct mlx5_core_dev * dev)633 static int mlx5_core_set_issi(struct mlx5_core_dev *dev)
634 {
635 u32 query_in[MLX5_ST_SZ_DW(query_issi_in)] = {0};
636 u32 query_out[MLX5_ST_SZ_DW(query_issi_out)] = {0};
637 u32 sup_issi;
638 int err;
639
640 MLX5_SET(query_issi_in, query_in, opcode, MLX5_CMD_OP_QUERY_ISSI);
641
642 err = mlx5_cmd_exec(dev, query_in, sizeof(query_in), query_out, sizeof(query_out));
643 if (err) {
644 u32 syndrome;
645 u8 status;
646
647 mlx5_cmd_mbox_status(query_out, &status, &syndrome);
648 if (status == MLX5_CMD_STAT_BAD_OP_ERR) {
649 mlx5_core_dbg(dev, "Only ISSI 0 is supported\n");
650 return 0;
651 }
652
653 mlx5_core_err(dev, "failed to query ISSI\n");
654 return err;
655 }
656
657 sup_issi = MLX5_GET(query_issi_out, query_out, supported_issi_dw0);
658
659 if (sup_issi & (1 << 1)) {
660 u32 set_in[MLX5_ST_SZ_DW(set_issi_in)] = {0};
661 u32 set_out[MLX5_ST_SZ_DW(set_issi_out)] = {0};
662
663 MLX5_SET(set_issi_in, set_in, opcode, MLX5_CMD_OP_SET_ISSI);
664 MLX5_SET(set_issi_in, set_in, current_issi, 1);
665
666 err = mlx5_cmd_exec(dev, set_in, sizeof(set_in), set_out, sizeof(set_out));
667 if (err) {
668 mlx5_core_err(dev, "failed to set ISSI=1 err(%d)\n", err);
669 return err;
670 }
671
672 dev->issi = 1;
673
674 return 0;
675 } else if (sup_issi & (1 << 0)) {
676 return 0;
677 }
678
679 return -ENOTSUPP;
680 }
681
682
mlx5_vector2eqn(struct mlx5_core_dev * dev,int vector,int * eqn,int * irqn)683 int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn, int *irqn)
684 {
685 struct mlx5_eq_table *table = &dev->priv.eq_table;
686 struct mlx5_eq *eq;
687 int err = -ENOENT;
688
689 spin_lock(&table->lock);
690 list_for_each_entry(eq, &table->comp_eqs_list, list) {
691 if (eq->index == vector) {
692 *eqn = eq->eqn;
693 *irqn = eq->irqn;
694 err = 0;
695 break;
696 }
697 }
698 spin_unlock(&table->lock);
699
700 return err;
701 }
702 EXPORT_SYMBOL(mlx5_vector2eqn);
703
free_comp_eqs(struct mlx5_core_dev * dev)704 static void free_comp_eqs(struct mlx5_core_dev *dev)
705 {
706 struct mlx5_eq_table *table = &dev->priv.eq_table;
707 struct mlx5_eq *eq, *n;
708
709 spin_lock(&table->lock);
710 list_for_each_entry_safe(eq, n, &table->comp_eqs_list, list) {
711 list_del(&eq->list);
712 spin_unlock(&table->lock);
713 if (mlx5_destroy_unmap_eq(dev, eq))
714 mlx5_core_warn(dev, "failed to destroy EQ 0x%x\n",
715 eq->eqn);
716 kfree(eq);
717 spin_lock(&table->lock);
718 }
719 spin_unlock(&table->lock);
720 }
721
alloc_comp_eqs(struct mlx5_core_dev * dev)722 static int alloc_comp_eqs(struct mlx5_core_dev *dev)
723 {
724 struct mlx5_eq_table *table = &dev->priv.eq_table;
725 struct mlx5_eq *eq;
726 int ncomp_vec;
727 int nent;
728 int err;
729 int i;
730
731 INIT_LIST_HEAD(&table->comp_eqs_list);
732 ncomp_vec = table->num_comp_vectors;
733 nent = mlx5_core_get_comp_eq_size();
734 for (i = 0; i < ncomp_vec; i++) {
735 eq = kzalloc_node(sizeof(*eq), GFP_KERNEL, dev->priv.numa_node);
736
737 err = mlx5_create_map_eq(dev, eq,
738 i + MLX5_EQ_VEC_COMP_BASE, nent, 0);
739 if (err) {
740 kfree(eq);
741 goto clean;
742 }
743 mlx5_core_dbg(dev, "allocated completion EQN %d\n", eq->eqn);
744 eq->index = i;
745 spin_lock(&table->lock);
746 list_add_tail(&eq->list, &table->comp_eqs_list);
747 spin_unlock(&table->lock);
748 }
749
750 return 0;
751
752 clean:
753 free_comp_eqs(dev);
754 return err;
755 }
756
fw_initializing(struct mlx5_core_dev * dev)757 static inline int fw_initializing(struct mlx5_core_dev *dev)
758 {
759 return ioread32be(&dev->iseg->initializing) >> 31;
760 }
761
wait_fw_init(struct mlx5_core_dev * dev,u32 max_wait_mili,u32 warn_time_mili)762 static int wait_fw_init(struct mlx5_core_dev *dev, u32 max_wait_mili,
763 u32 warn_time_mili)
764 {
765 unsigned long warn = jiffies + msecs_to_jiffies(warn_time_mili);
766 unsigned long end = jiffies + msecs_to_jiffies(max_wait_mili);
767 int err = 0;
768
769 MPASS(max_wait_mili > warn_time_mili);
770
771 while (fw_initializing(dev) == 1) {
772 if (time_after(jiffies, end)) {
773 err = -EBUSY;
774 break;
775 }
776 if (warn_time_mili && time_after(jiffies, warn)) {
777 mlx5_core_warn(dev,
778 "Waiting for FW initialization, timeout abort in %lu s\n",
779 (unsigned long)(jiffies_to_msecs(end - warn) / 1000));
780 warn = jiffies + msecs_to_jiffies(warn_time_mili);
781 }
782 msleep(FW_INIT_WAIT_MS);
783 }
784
785 if (err != 0)
786 mlx5_core_dbg(dev, "Full initializing bit dword = 0x%x\n",
787 ioread32be(&dev->iseg->initializing));
788
789 return err;
790 }
791
mlx5_add_device(struct mlx5_interface * intf,struct mlx5_priv * priv)792 static void mlx5_add_device(struct mlx5_interface *intf, struct mlx5_priv *priv)
793 {
794 struct mlx5_device_context *dev_ctx;
795 struct mlx5_core_dev *dev = container_of(priv, struct mlx5_core_dev, priv);
796
797 dev_ctx = kzalloc_node(sizeof(*dev_ctx), GFP_KERNEL, priv->numa_node);
798 if (!dev_ctx)
799 return;
800
801 dev_ctx->intf = intf;
802 CURVNET_SET_QUIET(vnet0);
803 dev_ctx->context = intf->add(dev);
804 CURVNET_RESTORE();
805
806 if (dev_ctx->context) {
807 spin_lock_irq(&priv->ctx_lock);
808 list_add_tail(&dev_ctx->list, &priv->ctx_list);
809 spin_unlock_irq(&priv->ctx_lock);
810 } else {
811 kfree(dev_ctx);
812 }
813 }
814
mlx5_remove_device(struct mlx5_interface * intf,struct mlx5_priv * priv)815 static void mlx5_remove_device(struct mlx5_interface *intf, struct mlx5_priv *priv)
816 {
817 struct mlx5_device_context *dev_ctx;
818 struct mlx5_core_dev *dev = container_of(priv, struct mlx5_core_dev, priv);
819
820 list_for_each_entry(dev_ctx, &priv->ctx_list, list)
821 if (dev_ctx->intf == intf) {
822 spin_lock_irq(&priv->ctx_lock);
823 list_del(&dev_ctx->list);
824 spin_unlock_irq(&priv->ctx_lock);
825
826 intf->remove(dev, dev_ctx->context);
827 kfree(dev_ctx);
828 return;
829 }
830 }
831
832 int
mlx5_register_device(struct mlx5_core_dev * dev)833 mlx5_register_device(struct mlx5_core_dev *dev)
834 {
835 struct mlx5_priv *priv = &dev->priv;
836 struct mlx5_interface *intf;
837
838 mutex_lock(&mlx5_intf_mutex);
839 list_add_tail(&priv->dev_list, &mlx5_dev_list);
840 list_for_each_entry(intf, &intf_list, list)
841 mlx5_add_device(intf, priv);
842 mutex_unlock(&mlx5_intf_mutex);
843
844 return 0;
845 }
846
847 void
mlx5_unregister_device(struct mlx5_core_dev * dev)848 mlx5_unregister_device(struct mlx5_core_dev *dev)
849 {
850 struct mlx5_priv *priv = &dev->priv;
851 struct mlx5_interface *intf;
852
853 mutex_lock(&mlx5_intf_mutex);
854 list_for_each_entry(intf, &intf_list, list)
855 mlx5_remove_device(intf, priv);
856 list_del(&priv->dev_list);
857 mutex_unlock(&mlx5_intf_mutex);
858 }
859
mlx5_register_interface(struct mlx5_interface * intf)860 int mlx5_register_interface(struct mlx5_interface *intf)
861 {
862 struct mlx5_priv *priv;
863
864 if (!intf->add || !intf->remove)
865 return -EINVAL;
866
867 mutex_lock(&mlx5_intf_mutex);
868 list_add_tail(&intf->list, &intf_list);
869 list_for_each_entry(priv, &mlx5_dev_list, dev_list)
870 mlx5_add_device(intf, priv);
871 mutex_unlock(&mlx5_intf_mutex);
872
873 return 0;
874 }
875 EXPORT_SYMBOL(mlx5_register_interface);
876
mlx5_unregister_interface(struct mlx5_interface * intf)877 void mlx5_unregister_interface(struct mlx5_interface *intf)
878 {
879 struct mlx5_priv *priv;
880
881 mutex_lock(&mlx5_intf_mutex);
882 list_for_each_entry(priv, &mlx5_dev_list, dev_list)
883 mlx5_remove_device(intf, priv);
884 list_del(&intf->list);
885 mutex_unlock(&mlx5_intf_mutex);
886 }
887 EXPORT_SYMBOL(mlx5_unregister_interface);
888
mlx5_get_protocol_dev(struct mlx5_core_dev * mdev,int protocol)889 void *mlx5_get_protocol_dev(struct mlx5_core_dev *mdev, int protocol)
890 {
891 struct mlx5_priv *priv = &mdev->priv;
892 struct mlx5_device_context *dev_ctx;
893 unsigned long flags;
894 void *result = NULL;
895
896 spin_lock_irqsave(&priv->ctx_lock, flags);
897
898 list_for_each_entry(dev_ctx, &mdev->priv.ctx_list, list)
899 if ((dev_ctx->intf->protocol == protocol) &&
900 dev_ctx->intf->get_dev) {
901 result = dev_ctx->intf->get_dev(dev_ctx->context);
902 break;
903 }
904
905 spin_unlock_irqrestore(&priv->ctx_lock, flags);
906
907 return result;
908 }
909 EXPORT_SYMBOL(mlx5_get_protocol_dev);
910
911 static int mlx5_auto_fw_update;
912 SYSCTL_INT(_hw_mlx5, OID_AUTO, auto_fw_update, CTLFLAG_RDTUN | CTLFLAG_NOFETCH,
913 &mlx5_auto_fw_update, 0,
914 "Allow automatic firmware update on driver start");
915 static int
mlx5_firmware_update(struct mlx5_core_dev * dev)916 mlx5_firmware_update(struct mlx5_core_dev *dev)
917 {
918 const struct firmware *fw;
919 int err;
920
921 TUNABLE_INT_FETCH("hw.mlx5.auto_fw_update", &mlx5_auto_fw_update);
922 if (!mlx5_auto_fw_update)
923 return (0);
924 fw = firmware_get("mlx5fw_mfa");
925 if (fw) {
926 err = mlx5_firmware_flash(dev, fw);
927 firmware_put(fw, FIRMWARE_UNLOAD);
928 }
929 else
930 return (-ENOENT);
931
932 return err;
933 }
934
mlx5_pci_init(struct mlx5_core_dev * dev,struct mlx5_priv * priv)935 static int mlx5_pci_init(struct mlx5_core_dev *dev, struct mlx5_priv *priv)
936 {
937 struct pci_dev *pdev = dev->pdev;
938 int err;
939
940 pdev = dev->pdev;
941 pci_set_drvdata(dev->pdev, dev);
942 strncpy(priv->name, dev_name(&pdev->dev), MLX5_MAX_NAME_LEN);
943 priv->name[MLX5_MAX_NAME_LEN - 1] = 0;
944
945 mutex_init(&priv->pgdir_mutex);
946 INIT_LIST_HEAD(&priv->pgdir_list);
947 spin_lock_init(&priv->mkey_lock);
948
949 err = mlx5_pci_enable_device(dev);
950 if (err) {
951 mlx5_core_err(dev, "Cannot enable PCI device, aborting\n");
952 goto err_dbg;
953 }
954
955 err = request_bar(pdev);
956 if (err) {
957 mlx5_core_err(dev, "error requesting BARs, aborting\n");
958 goto err_disable;
959 }
960
961 pci_set_master(pdev);
962
963 err = set_dma_caps(pdev);
964 if (err) {
965 mlx5_core_err(dev, "Failed setting DMA capabilities mask, aborting\n");
966 goto err_clr_master;
967 }
968
969 dev->iseg_base = pci_resource_start(dev->pdev, 0);
970 dev->iseg = ioremap(dev->iseg_base, sizeof(*dev->iseg));
971 if (!dev->iseg) {
972 err = -ENOMEM;
973 mlx5_core_err(dev, "Failed mapping initialization segment, aborting\n");
974 goto err_clr_master;
975 }
976
977 return 0;
978
979 err_clr_master:
980 release_bar(dev->pdev);
981 err_disable:
982 mlx5_pci_disable_device(dev);
983 err_dbg:
984 return err;
985 }
986
mlx5_pci_close(struct mlx5_core_dev * dev,struct mlx5_priv * priv)987 static void mlx5_pci_close(struct mlx5_core_dev *dev, struct mlx5_priv *priv)
988 {
989 #ifdef PCI_IOV
990 if (MLX5_CAP_GEN(dev, eswitch_flow_table))
991 pci_iov_detach(dev->pdev->dev.bsddev);
992 #endif
993 iounmap(dev->iseg);
994 release_bar(dev->pdev);
995 mlx5_pci_disable_device(dev);
996 }
997
mlx5_init_once(struct mlx5_core_dev * dev,struct mlx5_priv * priv)998 static int mlx5_init_once(struct mlx5_core_dev *dev, struct mlx5_priv *priv)
999 {
1000 int err;
1001
1002 err = mlx5_vsc_find_cap(dev);
1003 if (err)
1004 mlx5_core_warn(dev, "Unable to find vendor specific capabilities\n");
1005
1006 err = mlx5_query_hca_caps(dev);
1007 if (err) {
1008 mlx5_core_err(dev, "query hca failed\n");
1009 goto out;
1010 }
1011
1012 err = mlx5_query_board_id(dev);
1013 if (err) {
1014 mlx5_core_err(dev, "query board id failed\n");
1015 goto out;
1016 }
1017
1018 err = mlx5_eq_init(dev);
1019 if (err) {
1020 mlx5_core_err(dev, "failed to initialize eq\n");
1021 goto out;
1022 }
1023
1024 MLX5_INIT_DOORBELL_LOCK(&priv->cq_uar_lock);
1025
1026 err = mlx5_init_cq_table(dev);
1027 if (err) {
1028 mlx5_core_err(dev, "failed to initialize cq table\n");
1029 goto err_eq_cleanup;
1030 }
1031
1032 mlx5_init_qp_table(dev);
1033 mlx5_init_srq_table(dev);
1034 mlx5_init_mr_table(dev);
1035
1036 mlx5_init_reserved_gids(dev);
1037 mlx5_fpga_init(dev);
1038
1039 #ifdef RATELIMIT
1040 err = mlx5_init_rl_table(dev);
1041 if (err) {
1042 mlx5_core_err(dev, "Failed to init rate limiting\n");
1043 goto err_tables_cleanup;
1044 }
1045 #endif
1046 return 0;
1047
1048 #ifdef RATELIMIT
1049 err_tables_cleanup:
1050 mlx5_cleanup_mr_table(dev);
1051 mlx5_cleanup_srq_table(dev);
1052 mlx5_cleanup_qp_table(dev);
1053 mlx5_cleanup_cq_table(dev);
1054 #endif
1055
1056 err_eq_cleanup:
1057 mlx5_eq_cleanup(dev);
1058
1059 out:
1060 return err;
1061 }
1062
mlx5_cleanup_once(struct mlx5_core_dev * dev)1063 static void mlx5_cleanup_once(struct mlx5_core_dev *dev)
1064 {
1065 #ifdef RATELIMIT
1066 mlx5_cleanup_rl_table(dev);
1067 #endif
1068 mlx5_fpga_cleanup(dev);
1069 mlx5_cleanup_reserved_gids(dev);
1070 mlx5_cleanup_mr_table(dev);
1071 mlx5_cleanup_srq_table(dev);
1072 mlx5_cleanup_qp_table(dev);
1073 mlx5_cleanup_cq_table(dev);
1074 mlx5_eq_cleanup(dev);
1075 }
1076
mlx5_load_one(struct mlx5_core_dev * dev,struct mlx5_priv * priv,bool boot)1077 static int mlx5_load_one(struct mlx5_core_dev *dev, struct mlx5_priv *priv,
1078 bool boot)
1079 {
1080 int err;
1081
1082 mutex_lock(&dev->intf_state_mutex);
1083 if (test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) {
1084 mlx5_core_warn(dev, "interface is up, NOP\n");
1085 goto out;
1086 }
1087
1088 mlx5_core_dbg(dev, "firmware version: %d.%d.%d\n",
1089 fw_rev_maj(dev), fw_rev_min(dev), fw_rev_sub(dev));
1090
1091 /*
1092 * On load removing any previous indication of internal error,
1093 * device is up
1094 */
1095 dev->state = MLX5_DEVICE_STATE_UP;
1096
1097 /* wait for firmware to accept initialization segments configurations
1098 */
1099 err = wait_fw_init(dev, FW_PRE_INIT_TIMEOUT_MILI,
1100 FW_INIT_WARN_MESSAGE_INTERVAL);
1101 if (err) {
1102 dev_err(&dev->pdev->dev,
1103 "Firmware over %d MS in pre-initializing state, aborting\n",
1104 FW_PRE_INIT_TIMEOUT_MILI);
1105 goto out_err;
1106 }
1107
1108 err = mlx5_cmd_init(dev);
1109 if (err) {
1110 mlx5_core_err(dev,
1111 "Failed initializing command interface, aborting\n");
1112 goto out_err;
1113 }
1114
1115 err = wait_fw_init(dev, FW_INIT_TIMEOUT_MILI, 0);
1116 if (err) {
1117 mlx5_core_err(dev,
1118 "Firmware over %d MS in initializing state, aborting\n",
1119 FW_INIT_TIMEOUT_MILI);
1120 goto err_cmd_cleanup;
1121 }
1122
1123 err = mlx5_core_enable_hca(dev, 0);
1124 if (err) {
1125 mlx5_core_err(dev, "enable hca failed\n");
1126 goto err_cmd_cleanup;
1127 }
1128
1129 err = mlx5_core_set_issi(dev);
1130 if (err) {
1131 mlx5_core_err(dev, "failed to set issi\n");
1132 goto err_disable_hca;
1133 }
1134
1135 err = mlx5_pagealloc_start(dev);
1136 if (err) {
1137 mlx5_core_err(dev, "mlx5_pagealloc_start failed\n");
1138 goto err_disable_hca;
1139 }
1140
1141 err = mlx5_satisfy_startup_pages(dev, 1);
1142 if (err) {
1143 mlx5_core_err(dev, "failed to allocate boot pages\n");
1144 goto err_pagealloc_stop;
1145 }
1146
1147 err = set_hca_ctrl(dev);
1148 if (err) {
1149 mlx5_core_err(dev, "set_hca_ctrl failed\n");
1150 goto reclaim_boot_pages;
1151 }
1152
1153 err = handle_hca_cap(dev);
1154 if (err) {
1155 mlx5_core_err(dev, "handle_hca_cap failed\n");
1156 goto reclaim_boot_pages;
1157 }
1158
1159 err = handle_hca_cap_atomic(dev);
1160 if (err) {
1161 mlx5_core_err(dev, "handle_hca_cap_atomic failed\n");
1162 goto reclaim_boot_pages;
1163 }
1164
1165 err = handle_hca_cap_2(dev);
1166 if (err) {
1167 mlx5_core_err(dev, "handle_hca_cap_2 failed\n");
1168 goto reclaim_boot_pages;
1169 }
1170
1171 err = mlx5_satisfy_startup_pages(dev, 0);
1172 if (err) {
1173 mlx5_core_err(dev, "failed to allocate init pages\n");
1174 goto reclaim_boot_pages;
1175 }
1176
1177 err = mlx5_cmd_init_hca(dev);
1178 if (err) {
1179 mlx5_core_err(dev, "init hca failed\n");
1180 goto reclaim_boot_pages;
1181 }
1182
1183 mlx5_set_driver_version(dev);
1184
1185 mlx5_start_health_poll(dev);
1186
1187 if (boot && (err = mlx5_init_once(dev, priv))) {
1188 mlx5_core_err(dev, "sw objs init failed\n");
1189 goto err_stop_poll;
1190 }
1191
1192 dev->priv.uar = mlx5_get_uars_page(dev);
1193 if (IS_ERR(dev->priv.uar)) {
1194 mlx5_core_err(dev, "Failed allocating uar, aborting\n");
1195 err = PTR_ERR(dev->priv.uar);
1196 goto err_cleanup_once;
1197 }
1198
1199 err = mlx5_enable_msix(dev);
1200 if (err) {
1201 mlx5_core_err(dev, "enable msix failed\n");
1202 goto err_cleanup_uar;
1203 }
1204
1205 err = mlx5_start_eqs(dev);
1206 if (err) {
1207 mlx5_core_err(dev, "Failed to start pages and async EQs\n");
1208 goto err_disable_msix;
1209 }
1210
1211 err = alloc_comp_eqs(dev);
1212 if (err) {
1213 mlx5_core_err(dev, "Failed to alloc completion EQs\n");
1214 goto err_stop_eqs;
1215 }
1216
1217 err = mlx5_fs_core_init(dev);
1218 if (err) {
1219 mlx5_core_err(dev, "flow steering init %d\n", err);
1220 goto err_free_comp_eqs;
1221 }
1222
1223 err = mlx5_core_set_hca_defaults(dev);
1224 if (err) {
1225 mlx5_core_err(dev, "Failed to set HCA defaults %d\n", err);
1226 goto err_free_comp_eqs;
1227 }
1228
1229 err = mlx5_mpfs_init(dev);
1230 if (err) {
1231 mlx5_core_err(dev, "mpfs init failed %d\n", err);
1232 goto err_fs;
1233 }
1234
1235 err = mlx5_fpga_device_start(dev);
1236 if (err) {
1237 mlx5_core_err(dev, "fpga device start failed %d\n", err);
1238 goto err_mpfs;
1239 }
1240
1241 err = mlx5_diag_cnt_init(dev);
1242 if (err) {
1243 mlx5_core_err(dev, "diag cnt init failed %d\n", err);
1244 goto err_fpga;
1245 }
1246
1247 err = mlx5_register_device(dev);
1248 if (err) {
1249 mlx5_core_err(dev, "mlx5_register_device failed %d\n", err);
1250 goto err_diag_cnt;
1251 }
1252
1253 set_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1254
1255 out:
1256 mutex_unlock(&dev->intf_state_mutex);
1257 return 0;
1258
1259 err_diag_cnt:
1260 mlx5_diag_cnt_cleanup(dev);
1261
1262 err_fpga:
1263 mlx5_fpga_device_stop(dev);
1264
1265 err_mpfs:
1266 mlx5_mpfs_destroy(dev);
1267
1268 err_fs:
1269 mlx5_cleanup_fs(dev);
1270
1271 err_free_comp_eqs:
1272 free_comp_eqs(dev);
1273
1274 err_stop_eqs:
1275 mlx5_stop_eqs(dev);
1276
1277 err_disable_msix:
1278 mlx5_disable_msix(dev);
1279
1280 err_cleanup_uar:
1281 mlx5_put_uars_page(dev, dev->priv.uar);
1282
1283 err_cleanup_once:
1284 if (boot)
1285 mlx5_cleanup_once(dev);
1286
1287 err_stop_poll:
1288 mlx5_stop_health_poll(dev, boot);
1289 if (mlx5_cmd_teardown_hca(dev)) {
1290 mlx5_core_err(dev, "tear_down_hca failed, skip cleanup\n");
1291 goto out_err;
1292 }
1293
1294 reclaim_boot_pages:
1295 mlx5_reclaim_startup_pages(dev);
1296
1297 err_pagealloc_stop:
1298 mlx5_pagealloc_stop(dev);
1299
1300 err_disable_hca:
1301 mlx5_core_disable_hca(dev);
1302
1303 err_cmd_cleanup:
1304 mlx5_cmd_cleanup(dev);
1305
1306 out_err:
1307 dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR;
1308 mutex_unlock(&dev->intf_state_mutex);
1309
1310 return err;
1311 }
1312
mlx5_unload_one(struct mlx5_core_dev * dev,struct mlx5_priv * priv,bool cleanup)1313 static int mlx5_unload_one(struct mlx5_core_dev *dev, struct mlx5_priv *priv,
1314 bool cleanup)
1315 {
1316 int err = 0;
1317
1318 if (cleanup)
1319 mlx5_drain_health_recovery(dev);
1320
1321 mutex_lock(&dev->intf_state_mutex);
1322 if (!test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) {
1323 mlx5_core_warn(dev, "%s: interface is down, NOP\n", __func__);
1324 if (cleanup)
1325 mlx5_cleanup_once(dev);
1326 goto out;
1327 }
1328
1329 mlx5_unregister_device(dev);
1330
1331 mlx5_eswitch_cleanup(dev->priv.eswitch);
1332 mlx5_diag_cnt_cleanup(dev);
1333 mlx5_fpga_device_stop(dev);
1334 mlx5_mpfs_destroy(dev);
1335 mlx5_fs_core_cleanup(dev);
1336 mlx5_wait_for_reclaim_vfs_pages(dev);
1337 free_comp_eqs(dev);
1338 mlx5_stop_eqs(dev);
1339 mlx5_disable_msix(dev);
1340 mlx5_put_uars_page(dev, dev->priv.uar);
1341 if (cleanup)
1342 mlx5_cleanup_once(dev);
1343 mlx5_stop_health_poll(dev, cleanup);
1344 err = mlx5_cmd_teardown_hca(dev);
1345 if (err) {
1346 mlx5_core_err(dev, "tear_down_hca failed, skip cleanup\n");
1347 goto out;
1348 }
1349 mlx5_pagealloc_stop(dev);
1350 mlx5_reclaim_startup_pages(dev);
1351 mlx5_core_disable_hca(dev);
1352 mlx5_cmd_cleanup(dev);
1353
1354 out:
1355 clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1356 mutex_unlock(&dev->intf_state_mutex);
1357 return err;
1358 }
1359
mlx5_core_event(struct mlx5_core_dev * dev,enum mlx5_dev_event event,unsigned long param)1360 void mlx5_core_event(struct mlx5_core_dev *dev, enum mlx5_dev_event event,
1361 unsigned long param)
1362 {
1363 struct mlx5_priv *priv = &dev->priv;
1364 struct mlx5_device_context *dev_ctx;
1365 unsigned long flags;
1366
1367 spin_lock_irqsave(&priv->ctx_lock, flags);
1368
1369 list_for_each_entry(dev_ctx, &priv->ctx_list, list)
1370 if (dev_ctx->intf->event)
1371 dev_ctx->intf->event(dev, dev_ctx->context, event, param);
1372
1373 spin_unlock_irqrestore(&priv->ctx_lock, flags);
1374 }
1375
1376 struct mlx5_core_event_handler {
1377 void (*event)(struct mlx5_core_dev *dev,
1378 enum mlx5_dev_event event,
1379 void *data);
1380 };
1381
1382 #define MLX5_STATS_DESC(a, b, c, d, e, ...) d, e,
1383
1384 #define MLX5_PORT_MODULE_ERROR_STATS(m) \
1385 m(+1, u64, power_budget_exceeded, "power_budget", "Module Power Budget Exceeded") \
1386 m(+1, u64, long_range, "long_range", "Module Long Range for non MLNX cable/module") \
1387 m(+1, u64, bus_stuck, "bus_stuck", "Module Bus stuck(I2C or data shorted)") \
1388 m(+1, u64, no_eeprom, "no_eeprom", "No EEPROM/retry timeout") \
1389 m(+1, u64, enforce_part_number, "enforce_part_number", "Module Enforce part number list") \
1390 m(+1, u64, unknown_id, "unknown_id", "Module Unknown identifier") \
1391 m(+1, u64, high_temp, "high_temp", "Module High Temperature") \
1392 m(+1, u64, cable_shorted, "cable_shorted", "Module Cable is shorted") \
1393 m(+1, u64, pmd_type_not_enabled, "pmd_type_not_enabled", "PMD type is not enabled") \
1394 m(+1, u64, laster_tec_failure, "laster_tec_failure", "Laster TEC failure") \
1395 m(+1, u64, high_current, "high_current", "High current") \
1396 m(+1, u64, high_voltage, "high_voltage", "High voltage") \
1397 m(+1, u64, pcie_sys_power_slot_exceeded, "pcie_sys_power_slot_exceeded", "PCIe system power slot Exceeded") \
1398 m(+1, u64, high_power, "high_power", "High power") \
1399 m(+1, u64, module_state_machine_fault, "module_state_machine_fault", "Module State Machine fault")
1400
1401 static const char *mlx5_pme_err_desc[] = {
1402 MLX5_PORT_MODULE_ERROR_STATS(MLX5_STATS_DESC)
1403 };
1404
init_one(struct pci_dev * pdev,const struct pci_device_id * id)1405 static int init_one(struct pci_dev *pdev,
1406 const struct pci_device_id *id)
1407 {
1408 struct mlx5_core_dev *dev;
1409 struct mlx5_priv *priv;
1410 device_t bsddev = pdev->dev.bsddev;
1411 #ifdef PCI_IOV
1412 nvlist_t *pf_schema, *vf_schema;
1413 int num_vfs, sriov_pos;
1414 #endif
1415 int i,err;
1416 int numa_node;
1417 struct sysctl_oid *pme_sysctl_node;
1418 struct sysctl_oid *pme_err_sysctl_node;
1419 struct sysctl_oid *cap_sysctl_node;
1420 struct sysctl_oid *current_cap_sysctl_node;
1421 struct sysctl_oid *max_cap_sysctl_node;
1422
1423 printk_once("mlx5: %s", mlx5_version);
1424
1425 numa_node = dev_to_node(&pdev->dev);
1426
1427 dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, numa_node);
1428
1429 priv = &dev->priv;
1430 priv->numa_node = numa_node;
1431
1432 if (id)
1433 priv->pci_dev_data = id->driver_data;
1434
1435 if (mlx5_prof_sel < 0 || mlx5_prof_sel >= ARRAY_SIZE(profiles)) {
1436 device_printf(bsddev,
1437 "WARN: selected profile out of range, selecting default (%d)\n",
1438 MLX5_DEFAULT_PROF);
1439 mlx5_prof_sel = MLX5_DEFAULT_PROF;
1440 }
1441 dev->profile = &profiles[mlx5_prof_sel];
1442 dev->pdev = pdev;
1443 dev->event = mlx5_core_event;
1444
1445 /* Set desc */
1446 device_set_desc(bsddev, mlx5_version);
1447
1448 sysctl_ctx_init(&dev->sysctl_ctx);
1449 SYSCTL_ADD_INT(&dev->sysctl_ctx,
1450 SYSCTL_CHILDREN(device_get_sysctl_tree(bsddev)),
1451 OID_AUTO, "msix_eqvec", CTLFLAG_RDTUN, &dev->msix_eqvec, 0,
1452 "Maximum number of MSIX event queue vectors, if set");
1453 SYSCTL_ADD_INT(&dev->sysctl_ctx,
1454 SYSCTL_CHILDREN(device_get_sysctl_tree(bsddev)),
1455 OID_AUTO, "power_status", CTLFLAG_RD, &dev->pwr_status, 0,
1456 "0:Invalid 1:Sufficient 2:Insufficient");
1457 SYSCTL_ADD_INT(&dev->sysctl_ctx,
1458 SYSCTL_CHILDREN(device_get_sysctl_tree(bsddev)),
1459 OID_AUTO, "power_value", CTLFLAG_RD, &dev->pwr_value, 0,
1460 "Current power value in Watts");
1461
1462 pme_sysctl_node = SYSCTL_ADD_NODE(&dev->sysctl_ctx,
1463 SYSCTL_CHILDREN(device_get_sysctl_tree(bsddev)),
1464 OID_AUTO, "pme_stats", CTLFLAG_RD | CTLFLAG_MPSAFE, NULL,
1465 "Port module event statistics");
1466 if (pme_sysctl_node == NULL) {
1467 err = -ENOMEM;
1468 goto clean_sysctl_ctx;
1469 }
1470 pme_err_sysctl_node = SYSCTL_ADD_NODE(&dev->sysctl_ctx,
1471 SYSCTL_CHILDREN(pme_sysctl_node),
1472 OID_AUTO, "errors", CTLFLAG_RD | CTLFLAG_MPSAFE, NULL,
1473 "Port module event error statistics");
1474 if (pme_err_sysctl_node == NULL) {
1475 err = -ENOMEM;
1476 goto clean_sysctl_ctx;
1477 }
1478 SYSCTL_ADD_U64(&dev->sysctl_ctx,
1479 SYSCTL_CHILDREN(pme_sysctl_node), OID_AUTO,
1480 "module_plug", CTLFLAG_RD | CTLFLAG_MPSAFE,
1481 &dev->priv.pme_stats.status_counters[MLX5_MODULE_STATUS_PLUGGED_ENABLED],
1482 0, "Number of time module plugged");
1483 SYSCTL_ADD_U64(&dev->sysctl_ctx,
1484 SYSCTL_CHILDREN(pme_sysctl_node), OID_AUTO,
1485 "module_unplug", CTLFLAG_RD | CTLFLAG_MPSAFE,
1486 &dev->priv.pme_stats.status_counters[MLX5_MODULE_STATUS_UNPLUGGED],
1487 0, "Number of time module unplugged");
1488 for (i = 0 ; i < MLX5_MODULE_EVENT_ERROR_NUM; i++) {
1489 SYSCTL_ADD_U64(&dev->sysctl_ctx,
1490 SYSCTL_CHILDREN(pme_err_sysctl_node), OID_AUTO,
1491 mlx5_pme_err_desc[2 * i], CTLFLAG_RD | CTLFLAG_MPSAFE,
1492 &dev->priv.pme_stats.error_counters[i],
1493 0, mlx5_pme_err_desc[2 * i + 1]);
1494 }
1495
1496 cap_sysctl_node = SYSCTL_ADD_NODE(&dev->sysctl_ctx,
1497 SYSCTL_CHILDREN(device_get_sysctl_tree(bsddev)),
1498 OID_AUTO, "caps", CTLFLAG_RD | CTLFLAG_MPSAFE, NULL,
1499 "hardware capabilities raw bitstrings");
1500 if (cap_sysctl_node == NULL) {
1501 err = -ENOMEM;
1502 goto clean_sysctl_ctx;
1503 }
1504 current_cap_sysctl_node = SYSCTL_ADD_NODE(&dev->sysctl_ctx,
1505 SYSCTL_CHILDREN(cap_sysctl_node),
1506 OID_AUTO, "current", CTLFLAG_RD | CTLFLAG_MPSAFE, NULL,
1507 "");
1508 if (current_cap_sysctl_node == NULL) {
1509 err = -ENOMEM;
1510 goto clean_sysctl_ctx;
1511 }
1512 max_cap_sysctl_node = SYSCTL_ADD_NODE(&dev->sysctl_ctx,
1513 SYSCTL_CHILDREN(cap_sysctl_node),
1514 OID_AUTO, "max", CTLFLAG_RD | CTLFLAG_MPSAFE, NULL,
1515 "");
1516 if (max_cap_sysctl_node == NULL) {
1517 err = -ENOMEM;
1518 goto clean_sysctl_ctx;
1519 }
1520 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx,
1521 SYSCTL_CHILDREN(current_cap_sysctl_node),
1522 OID_AUTO, "general", CTLFLAG_RD | CTLFLAG_MPSAFE,
1523 &dev->hca_caps_cur[MLX5_CAP_GENERAL],
1524 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", "");
1525 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx,
1526 SYSCTL_CHILDREN(max_cap_sysctl_node),
1527 OID_AUTO, "general", CTLFLAG_RD | CTLFLAG_MPSAFE,
1528 &dev->hca_caps_max[MLX5_CAP_GENERAL],
1529 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", "");
1530 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx,
1531 SYSCTL_CHILDREN(current_cap_sysctl_node),
1532 OID_AUTO, "ether", CTLFLAG_RD | CTLFLAG_MPSAFE,
1533 &dev->hca_caps_cur[MLX5_CAP_ETHERNET_OFFLOADS],
1534 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", "");
1535 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx,
1536 SYSCTL_CHILDREN(max_cap_sysctl_node),
1537 OID_AUTO, "ether", CTLFLAG_RD | CTLFLAG_MPSAFE,
1538 &dev->hca_caps_max[MLX5_CAP_ETHERNET_OFFLOADS],
1539 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", "");
1540 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx,
1541 SYSCTL_CHILDREN(current_cap_sysctl_node),
1542 OID_AUTO, "odp", CTLFLAG_RD | CTLFLAG_MPSAFE,
1543 &dev->hca_caps_cur[MLX5_CAP_ODP],
1544 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", "");
1545 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx,
1546 SYSCTL_CHILDREN(max_cap_sysctl_node),
1547 OID_AUTO, "odp", CTLFLAG_RD | CTLFLAG_MPSAFE,
1548 &dev->hca_caps_max[MLX5_CAP_ODP],
1549 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", "");
1550 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx,
1551 SYSCTL_CHILDREN(current_cap_sysctl_node),
1552 OID_AUTO, "atomic", CTLFLAG_RD | CTLFLAG_MPSAFE,
1553 &dev->hca_caps_cur[MLX5_CAP_ATOMIC],
1554 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", "");
1555 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx,
1556 SYSCTL_CHILDREN(max_cap_sysctl_node),
1557 OID_AUTO, "atomic", CTLFLAG_RD | CTLFLAG_MPSAFE,
1558 &dev->hca_caps_max[MLX5_CAP_ATOMIC],
1559 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", "");
1560 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx,
1561 SYSCTL_CHILDREN(current_cap_sysctl_node),
1562 OID_AUTO, "roce", CTLFLAG_RD | CTLFLAG_MPSAFE,
1563 &dev->hca_caps_cur[MLX5_CAP_ROCE],
1564 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", "");
1565 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx,
1566 SYSCTL_CHILDREN(max_cap_sysctl_node),
1567 OID_AUTO, "roce", CTLFLAG_RD | CTLFLAG_MPSAFE,
1568 &dev->hca_caps_max[MLX5_CAP_ROCE],
1569 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", "");
1570 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx,
1571 SYSCTL_CHILDREN(current_cap_sysctl_node),
1572 OID_AUTO, "ipoib", CTLFLAG_RD | CTLFLAG_MPSAFE,
1573 &dev->hca_caps_cur[MLX5_CAP_IPOIB_OFFLOADS],
1574 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", "");
1575 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx,
1576 SYSCTL_CHILDREN(max_cap_sysctl_node),
1577 OID_AUTO, "ipoib", CTLFLAG_RD | CTLFLAG_MPSAFE,
1578 &dev->hca_caps_max[MLX5_CAP_IPOIB_OFFLOADS],
1579 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", "");
1580 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx,
1581 SYSCTL_CHILDREN(current_cap_sysctl_node),
1582 OID_AUTO, "eoib", CTLFLAG_RD | CTLFLAG_MPSAFE,
1583 &dev->hca_caps_cur[MLX5_CAP_EOIB_OFFLOADS],
1584 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", "");
1585 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx,
1586 SYSCTL_CHILDREN(max_cap_sysctl_node),
1587 OID_AUTO, "eoib", CTLFLAG_RD | CTLFLAG_MPSAFE,
1588 &dev->hca_caps_max[MLX5_CAP_EOIB_OFFLOADS],
1589 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", "");
1590 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx,
1591 SYSCTL_CHILDREN(current_cap_sysctl_node),
1592 OID_AUTO, "flow_table", CTLFLAG_RD | CTLFLAG_MPSAFE,
1593 &dev->hca_caps_cur[MLX5_CAP_FLOW_TABLE],
1594 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", "");
1595 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx,
1596 SYSCTL_CHILDREN(max_cap_sysctl_node),
1597 OID_AUTO, "flow_table", CTLFLAG_RD | CTLFLAG_MPSAFE,
1598 &dev->hca_caps_max[MLX5_CAP_FLOW_TABLE],
1599 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", "");
1600 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx,
1601 SYSCTL_CHILDREN(current_cap_sysctl_node),
1602 OID_AUTO, "eswitch_flow_table", CTLFLAG_RD | CTLFLAG_MPSAFE,
1603 &dev->hca_caps_cur[MLX5_CAP_ESWITCH_FLOW_TABLE],
1604 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", "");
1605 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx,
1606 SYSCTL_CHILDREN(max_cap_sysctl_node),
1607 OID_AUTO, "eswitch_flow_table", CTLFLAG_RD | CTLFLAG_MPSAFE,
1608 &dev->hca_caps_max[MLX5_CAP_ESWITCH_FLOW_TABLE],
1609 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", "");
1610 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx,
1611 SYSCTL_CHILDREN(current_cap_sysctl_node),
1612 OID_AUTO, "eswitch", CTLFLAG_RD | CTLFLAG_MPSAFE,
1613 &dev->hca_caps_cur[MLX5_CAP_ESWITCH],
1614 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", "");
1615 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx,
1616 SYSCTL_CHILDREN(max_cap_sysctl_node),
1617 OID_AUTO, "eswitch", CTLFLAG_RD | CTLFLAG_MPSAFE,
1618 &dev->hca_caps_max[MLX5_CAP_ESWITCH],
1619 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", "");
1620 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx,
1621 SYSCTL_CHILDREN(current_cap_sysctl_node),
1622 OID_AUTO, "snapshot", CTLFLAG_RD | CTLFLAG_MPSAFE,
1623 &dev->hca_caps_cur[MLX5_CAP_SNAPSHOT],
1624 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", "");
1625 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx,
1626 SYSCTL_CHILDREN(max_cap_sysctl_node),
1627 OID_AUTO, "snapshot", CTLFLAG_RD | CTLFLAG_MPSAFE,
1628 &dev->hca_caps_max[MLX5_CAP_SNAPSHOT],
1629 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", "");
1630 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx,
1631 SYSCTL_CHILDREN(current_cap_sysctl_node),
1632 OID_AUTO, "vector_calc", CTLFLAG_RD | CTLFLAG_MPSAFE,
1633 &dev->hca_caps_cur[MLX5_CAP_VECTOR_CALC],
1634 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", "");
1635 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx,
1636 SYSCTL_CHILDREN(max_cap_sysctl_node),
1637 OID_AUTO, "vector_calc", CTLFLAG_RD | CTLFLAG_MPSAFE,
1638 &dev->hca_caps_max[MLX5_CAP_VECTOR_CALC],
1639 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", "");
1640 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx,
1641 SYSCTL_CHILDREN(current_cap_sysctl_node),
1642 OID_AUTO, "qos", CTLFLAG_RD | CTLFLAG_MPSAFE,
1643 &dev->hca_caps_cur[MLX5_CAP_QOS],
1644 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", "");
1645 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx,
1646 SYSCTL_CHILDREN(max_cap_sysctl_node),
1647 OID_AUTO, "qos", CTLFLAG_RD | CTLFLAG_MPSAFE,
1648 &dev->hca_caps_max[MLX5_CAP_QOS],
1649 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", "");
1650 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx,
1651 SYSCTL_CHILDREN(current_cap_sysctl_node),
1652 OID_AUTO, "debug", CTLFLAG_RD | CTLFLAG_MPSAFE,
1653 &dev->hca_caps_cur[MLX5_CAP_DEBUG],
1654 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", "");
1655 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx,
1656 SYSCTL_CHILDREN(max_cap_sysctl_node),
1657 OID_AUTO, "debug", CTLFLAG_RD | CTLFLAG_MPSAFE,
1658 &dev->hca_caps_max[MLX5_CAP_DEBUG],
1659 MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", "");
1660 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx,
1661 SYSCTL_CHILDREN(cap_sysctl_node),
1662 OID_AUTO, "pcam", CTLFLAG_RD | CTLFLAG_MPSAFE,
1663 &dev->caps.pcam, sizeof(dev->caps.pcam), "IU", "");
1664 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx,
1665 SYSCTL_CHILDREN(cap_sysctl_node),
1666 OID_AUTO, "mcam", CTLFLAG_RD | CTLFLAG_MPSAFE,
1667 &dev->caps.mcam, sizeof(dev->caps.mcam), "IU", "");
1668 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx,
1669 SYSCTL_CHILDREN(cap_sysctl_node),
1670 OID_AUTO, "qcam", CTLFLAG_RD | CTLFLAG_MPSAFE,
1671 &dev->caps.qcam, sizeof(dev->caps.qcam), "IU", "");
1672 SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx,
1673 SYSCTL_CHILDREN(cap_sysctl_node),
1674 OID_AUTO, "fpga", CTLFLAG_RD | CTLFLAG_MPSAFE,
1675 &dev->caps.fpga, sizeof(dev->caps.fpga), "IU", "");
1676
1677 INIT_LIST_HEAD(&priv->ctx_list);
1678 spin_lock_init(&priv->ctx_lock);
1679 mutex_init(&dev->pci_status_mutex);
1680 mutex_init(&dev->intf_state_mutex);
1681
1682 mutex_init(&priv->bfregs.reg_head.lock);
1683 mutex_init(&priv->bfregs.wc_head.lock);
1684 INIT_LIST_HEAD(&priv->bfregs.reg_head.list);
1685 INIT_LIST_HEAD(&priv->bfregs.wc_head.list);
1686
1687 mtx_init(&dev->dump_lock, "mlx5dmp", NULL, MTX_DEF | MTX_NEW);
1688 err = mlx5_pci_init(dev, priv);
1689 if (err) {
1690 mlx5_core_err(dev, "mlx5_pci_init failed %d\n", err);
1691 goto clean_dev;
1692 }
1693
1694 err = mlx5_health_init(dev);
1695 if (err) {
1696 mlx5_core_err(dev, "mlx5_health_init failed %d\n", err);
1697 goto close_pci;
1698 }
1699
1700 mlx5_pagealloc_init(dev);
1701
1702 err = mlx5_fs_core_alloc(dev);
1703 if (err) {
1704 mlx5_core_err(dev, "Failed to alloc flow steering\n");
1705 goto clean_health;
1706 }
1707
1708 err = mlx5_load_one(dev, priv, true);
1709 if (err) {
1710 mlx5_core_err(dev, "mlx5_load_one failed %d\n", err);
1711 goto clean_fs;
1712 }
1713
1714 mlx5_fwdump_prep(dev);
1715
1716 mlx5_firmware_update(dev);
1717
1718 #ifdef PCI_IOV
1719 if (MLX5_CAP_GEN(dev, vport_group_manager)) {
1720 if (pci_find_extcap(bsddev, PCIZ_SRIOV, &sriov_pos) == 0) {
1721 num_vfs = pci_read_config(bsddev, sriov_pos +
1722 PCIR_SRIOV_TOTAL_VFS, 2);
1723 } else {
1724 mlx5_core_info(dev, "cannot find SR-IOV PCIe cap\n");
1725 num_vfs = 0;
1726 }
1727 err = mlx5_eswitch_init(dev, 1 + num_vfs);
1728 if (err == 0) {
1729 pf_schema = pci_iov_schema_alloc_node();
1730 vf_schema = pci_iov_schema_alloc_node();
1731 pci_iov_schema_add_unicast_mac(vf_schema,
1732 iov_mac_addr_name, 0, NULL);
1733 pci_iov_schema_add_vlan(vf_schema,
1734 iov_vlan_name, 0, 0);
1735 pci_iov_schema_add_uint64(vf_schema, iov_node_guid_name,
1736 0, 0);
1737 pci_iov_schema_add_uint64(vf_schema, iov_port_guid_name,
1738 0, 0);
1739 err = pci_iov_attach(bsddev, pf_schema, vf_schema);
1740 if (err == 0) {
1741 dev->iov_pf = true;
1742 } else {
1743 device_printf(bsddev,
1744 "Failed to initialize SR-IOV support, error %d\n",
1745 err);
1746 }
1747 } else {
1748 mlx5_core_err(dev, "eswitch init failed, error %d\n",
1749 err);
1750 }
1751 }
1752 #endif
1753
1754 pci_save_state(pdev);
1755 return 0;
1756
1757 clean_fs:
1758 mlx5_fs_core_free(dev);
1759 clean_health:
1760 mlx5_pagealloc_cleanup(dev);
1761 mlx5_health_cleanup(dev);
1762 close_pci:
1763 mlx5_pci_close(dev, priv);
1764 clean_dev:
1765 mtx_destroy(&dev->dump_lock);
1766 clean_sysctl_ctx:
1767 sysctl_ctx_free(&dev->sysctl_ctx);
1768 kfree(dev);
1769 return err;
1770 }
1771
remove_one(struct pci_dev * pdev)1772 static void remove_one(struct pci_dev *pdev)
1773 {
1774 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1775 struct mlx5_priv *priv = &dev->priv;
1776
1777 #ifdef PCI_IOV
1778 if (dev->iov_pf) {
1779 pci_iov_detach(pdev->dev.bsddev);
1780 mlx5_eswitch_disable_sriov(priv->eswitch);
1781 dev->iov_pf = false;
1782 }
1783 #endif
1784
1785 if (mlx5_unload_one(dev, priv, true)) {
1786 mlx5_core_err(dev, "mlx5_unload_one() failed, leaked %lld bytes\n",
1787 (long long)(dev->priv.fw_pages * MLX5_ADAPTER_PAGE_SIZE));
1788 }
1789
1790 mlx5_fs_core_free(dev);
1791 mlx5_pagealloc_cleanup(dev);
1792 mlx5_health_cleanup(dev);
1793 mlx5_fwdump_clean(dev);
1794 mlx5_pci_close(dev, priv);
1795 mtx_destroy(&dev->dump_lock);
1796 pci_set_drvdata(pdev, NULL);
1797 sysctl_ctx_free(&dev->sysctl_ctx);
1798 kfree(dev);
1799 }
1800
mlx5_pci_err_detected(struct pci_dev * pdev,pci_channel_state_t state)1801 static pci_ers_result_t mlx5_pci_err_detected(struct pci_dev *pdev,
1802 pci_channel_state_t state)
1803 {
1804 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1805 struct mlx5_priv *priv = &dev->priv;
1806
1807 mlx5_core_info(dev, "%s was called\n", __func__);
1808 mlx5_enter_error_state(dev, false);
1809 mlx5_unload_one(dev, priv, false);
1810
1811 if (state) {
1812 mlx5_drain_health_wq(dev);
1813 mlx5_pci_disable_device(dev);
1814 }
1815
1816 return state == pci_channel_io_perm_failure ?
1817 PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET;
1818 }
1819
mlx5_pci_slot_reset(struct pci_dev * pdev)1820 static pci_ers_result_t mlx5_pci_slot_reset(struct pci_dev *pdev)
1821 {
1822 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1823 int err = 0;
1824
1825 mlx5_core_info(dev,"%s was called\n", __func__);
1826
1827 err = mlx5_pci_enable_device(dev);
1828 if (err) {
1829 mlx5_core_err(dev, "mlx5_pci_enable_device failed with error code: %d\n"
1830 ,err);
1831 return PCI_ERS_RESULT_DISCONNECT;
1832 }
1833 pci_set_master(pdev);
1834 pci_set_powerstate(pdev->dev.bsddev, PCI_POWERSTATE_D0);
1835 pci_restore_state(pdev);
1836 pci_save_state(pdev);
1837
1838 return err ? PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_RECOVERED;
1839 }
1840
1841 /* wait for the device to show vital signs. For now we check
1842 * that we can read the device ID and that the health buffer
1843 * shows a non zero value which is different than 0xffffffff
1844 */
wait_vital(struct pci_dev * pdev)1845 static void wait_vital(struct pci_dev *pdev)
1846 {
1847 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1848 struct mlx5_core_health *health = &dev->priv.health;
1849 const int niter = 100;
1850 u32 count;
1851 u16 did;
1852 int i;
1853
1854 /* Wait for firmware to be ready after reset */
1855 msleep(1000);
1856 for (i = 0; i < niter; i++) {
1857 if (pci_read_config_word(pdev, 2, &did)) {
1858 mlx5_core_warn(dev, "failed reading config word\n");
1859 break;
1860 }
1861 if (did == pdev->device) {
1862 mlx5_core_info(dev,
1863 "device ID correctly read after %d iterations\n", i);
1864 break;
1865 }
1866 msleep(50);
1867 }
1868 if (i == niter)
1869 mlx5_core_warn(dev, "could not read device ID\n");
1870
1871 for (i = 0; i < niter; i++) {
1872 count = ioread32be(health->health_counter);
1873 if (count && count != 0xffffffff) {
1874 mlx5_core_info(dev,
1875 "Counter value 0x%x after %d iterations\n", count, i);
1876 break;
1877 }
1878 msleep(50);
1879 }
1880
1881 if (i == niter)
1882 mlx5_core_warn(dev, "could not read device ID\n");
1883 }
1884
mlx5_pci_resume(struct pci_dev * pdev)1885 static void mlx5_pci_resume(struct pci_dev *pdev)
1886 {
1887 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1888 struct mlx5_priv *priv = &dev->priv;
1889 int err;
1890
1891 mlx5_core_info(dev,"%s was called\n", __func__);
1892
1893 wait_vital(pdev);
1894
1895 err = mlx5_load_one(dev, priv, false);
1896 if (err)
1897 mlx5_core_err(dev,
1898 "mlx5_load_one failed with error code: %d\n" ,err);
1899 else
1900 mlx5_core_info(dev,"device recovered\n");
1901 }
1902
1903 static const struct pci_error_handlers mlx5_err_handler = {
1904 .error_detected = mlx5_pci_err_detected,
1905 .slot_reset = mlx5_pci_slot_reset,
1906 .resume = mlx5_pci_resume
1907 };
1908
1909 #ifdef PCI_IOV
1910 static int
mlx5_iov_init(device_t dev,uint16_t num_vfs,const nvlist_t * pf_config)1911 mlx5_iov_init(device_t dev, uint16_t num_vfs, const nvlist_t *pf_config)
1912 {
1913 struct pci_dev *pdev;
1914 struct mlx5_core_dev *core_dev;
1915 struct mlx5_priv *priv;
1916 int err;
1917
1918 pdev = device_get_softc(dev);
1919 core_dev = pci_get_drvdata(pdev);
1920 priv = &core_dev->priv;
1921
1922 if (priv->eswitch == NULL)
1923 return (ENXIO);
1924 if (priv->eswitch->total_vports < num_vfs + 1)
1925 num_vfs = priv->eswitch->total_vports - 1;
1926 err = mlx5_eswitch_enable_sriov(priv->eswitch, num_vfs);
1927 return (-err);
1928 }
1929
1930 static void
mlx5_iov_uninit(device_t dev)1931 mlx5_iov_uninit(device_t dev)
1932 {
1933 struct pci_dev *pdev;
1934 struct mlx5_core_dev *core_dev;
1935 struct mlx5_priv *priv;
1936
1937 pdev = device_get_softc(dev);
1938 core_dev = pci_get_drvdata(pdev);
1939 priv = &core_dev->priv;
1940
1941 mlx5_eswitch_disable_sriov(priv->eswitch);
1942 }
1943
1944 static int
mlx5_iov_add_vf(device_t dev,uint16_t vfnum,const nvlist_t * vf_config)1945 mlx5_iov_add_vf(device_t dev, uint16_t vfnum, const nvlist_t *vf_config)
1946 {
1947 struct pci_dev *pdev;
1948 struct mlx5_core_dev *core_dev;
1949 struct mlx5_priv *priv;
1950 const void *mac;
1951 size_t mac_size;
1952 uint64_t node_guid, port_guid;
1953 int error;
1954
1955 pdev = device_get_softc(dev);
1956 core_dev = pci_get_drvdata(pdev);
1957 priv = &core_dev->priv;
1958
1959 if (vfnum + 1 >= priv->eswitch->total_vports)
1960 return (ENXIO);
1961
1962 if (nvlist_exists_binary(vf_config, iov_mac_addr_name)) {
1963 mac = nvlist_get_binary(vf_config, iov_mac_addr_name,
1964 &mac_size);
1965 error = -mlx5_eswitch_set_vport_mac(priv->eswitch,
1966 vfnum + 1, __DECONST(u8 *, mac));
1967 if (error != 0) {
1968 mlx5_core_err(core_dev,
1969 "setting MAC for VF %d failed, error %d\n",
1970 vfnum + 1, error);
1971 }
1972 }
1973
1974 if (nvlist_exists_number(vf_config, iov_vlan_name)) {
1975 uint16_t vlan = nvlist_get_number(vf_config, iov_vlan_name);
1976
1977 if (vlan == DOT1Q_VID_NULL)
1978 error = ENOTSUP;
1979 else {
1980 if (vlan == VF_VLAN_TRUNK)
1981 vlan = DOT1Q_VID_NULL;
1982
1983 error = -mlx5_eswitch_set_vport_vlan(priv->eswitch,
1984 vfnum + 1, vlan, 0);
1985 }
1986 if (error != 0) {
1987 mlx5_core_err(core_dev,
1988 "setting VLAN for VF %d failed, error %d\n",
1989 vfnum + 1, error);
1990 }
1991 }
1992
1993 if (nvlist_exists_number(vf_config, iov_node_guid_name)) {
1994 node_guid = nvlist_get_number(vf_config, iov_node_guid_name);
1995 error = -mlx5_modify_nic_vport_node_guid(core_dev, vfnum + 1,
1996 node_guid);
1997 if (error != 0) {
1998 mlx5_core_err(core_dev,
1999 "modifying node GUID for VF %d failed, error %d\n",
2000 vfnum + 1, error);
2001 }
2002 }
2003
2004 if (nvlist_exists_number(vf_config, iov_port_guid_name)) {
2005 port_guid = nvlist_get_number(vf_config, iov_port_guid_name);
2006 error = -mlx5_modify_nic_vport_port_guid(core_dev, vfnum + 1,
2007 port_guid);
2008 if (error != 0) {
2009 mlx5_core_err(core_dev,
2010 "modifying port GUID for VF %d failed, error %d\n",
2011 vfnum + 1, error);
2012 }
2013 }
2014
2015 error = -mlx5_eswitch_set_vport_state(priv->eswitch, vfnum + 1,
2016 VPORT_STATE_FOLLOW);
2017 if (error != 0) {
2018 mlx5_core_err(core_dev,
2019 "upping vport for VF %d failed, error %d\n",
2020 vfnum + 1, error);
2021 }
2022 error = -mlx5_core_enable_hca(core_dev, vfnum + 1);
2023 if (error != 0) {
2024 mlx5_core_err(core_dev, "enabling VF %d failed, error %d\n",
2025 vfnum + 1, error);
2026 }
2027 return (error);
2028 }
2029 #endif
2030
mlx5_try_fast_unload(struct mlx5_core_dev * dev)2031 static int mlx5_try_fast_unload(struct mlx5_core_dev *dev)
2032 {
2033 bool fast_teardown, force_teardown;
2034 int err;
2035
2036 if (!mlx5_fast_unload_enabled) {
2037 mlx5_core_dbg(dev, "fast unload is disabled by user\n");
2038 return -EOPNOTSUPP;
2039 }
2040
2041 fast_teardown = MLX5_CAP_GEN(dev, fast_teardown);
2042 force_teardown = MLX5_CAP_GEN(dev, force_teardown);
2043
2044 mlx5_core_dbg(dev, "force teardown firmware support=%d\n", force_teardown);
2045 mlx5_core_dbg(dev, "fast teardown firmware support=%d\n", fast_teardown);
2046
2047 if (!fast_teardown && !force_teardown)
2048 return -EOPNOTSUPP;
2049
2050 if (dev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
2051 mlx5_core_dbg(dev, "Device in internal error state, giving up\n");
2052 return -EAGAIN;
2053 }
2054
2055 /* Panic tear down fw command will stop the PCI bus communication
2056 * with the HCA, so the health polll is no longer needed.
2057 */
2058 mlx5_drain_health_wq(dev);
2059 mlx5_stop_health_poll(dev, false);
2060
2061 err = mlx5_cmd_fast_teardown_hca(dev);
2062 if (!err)
2063 goto done;
2064
2065 err = mlx5_cmd_force_teardown_hca(dev);
2066 if (!err)
2067 goto done;
2068
2069 mlx5_core_dbg(dev, "Firmware couldn't do fast unload error: %d\n", err);
2070 mlx5_start_health_poll(dev);
2071 return err;
2072 done:
2073 mlx5_enter_error_state(dev, true);
2074 return 0;
2075 }
2076
mlx5_shutdown_disable_interrupts(struct mlx5_core_dev * mdev)2077 static void mlx5_shutdown_disable_interrupts(struct mlx5_core_dev *mdev)
2078 {
2079 int nvec = mdev->priv.eq_table.num_comp_vectors + MLX5_EQ_VEC_COMP_BASE;
2080 int x;
2081
2082 mdev->priv.disable_irqs = 1;
2083
2084 /* wait for all IRQ handlers to finish processing */
2085 for (x = 0; x != nvec; x++)
2086 synchronize_irq(mdev->priv.msix_arr[x].vector);
2087 }
2088
shutdown_one(struct pci_dev * pdev)2089 static void shutdown_one(struct pci_dev *pdev)
2090 {
2091 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
2092 struct mlx5_priv *priv = &dev->priv;
2093 int err;
2094
2095 /* enter polling mode */
2096 mlx5_cmd_use_polling(dev);
2097
2098 set_bit(MLX5_INTERFACE_STATE_TEARDOWN, &dev->intf_state);
2099
2100 /* disable all interrupts */
2101 mlx5_shutdown_disable_interrupts(dev);
2102
2103 err = mlx5_try_fast_unload(dev);
2104 if (err)
2105 mlx5_unload_one(dev, priv, false);
2106 mlx5_pci_disable_device(dev);
2107 }
2108
2109 /*
2110 * When adding device IDs, also update hca_table in
2111 * contrib/ofed/libmlx5/mlx5.c or libibverbs will reject the device.
2112 */
2113 static const struct pci_device_id mlx5_core_pci_table[] = {
2114 { PCI_VDEVICE(MELLANOX, 4113) }, /* Connect-IB */
2115 { PCI_VDEVICE(MELLANOX, 4114), .driver_data = MLX5_PCI_DEV_IS_VF}, /* Connect-IB VF */
2116 { PCI_VDEVICE(MELLANOX, 4115) }, /* ConnectX-4 */
2117 { PCI_VDEVICE(MELLANOX, 4116), .driver_data = MLX5_PCI_DEV_IS_VF}, /* ConnectX-4 VF */
2118 { PCI_VDEVICE(MELLANOX, 4117) }, /* ConnectX-4LX */
2119 { PCI_VDEVICE(MELLANOX, 4118), .driver_data = MLX5_PCI_DEV_IS_VF}, /* ConnectX-4LX VF */
2120 { PCI_VDEVICE(MELLANOX, 4119) }, /* ConnectX-5, PCIe 3.0 */
2121 { PCI_VDEVICE(MELLANOX, 4120), .driver_data = MLX5_PCI_DEV_IS_VF}, /* ConnectX-5 VF */
2122 { PCI_VDEVICE(MELLANOX, 4121) }, /* ConnectX-5 Ex */
2123 { PCI_VDEVICE(MELLANOX, 4122), .driver_data = MLX5_PCI_DEV_IS_VF}, /* ConnectX-5 Ex VF */
2124 { PCI_VDEVICE(MELLANOX, 4123) }, /* ConnectX-6 */
2125 { PCI_VDEVICE(MELLANOX, 4124), .driver_data = MLX5_PCI_DEV_IS_VF}, /* ConnectX-6 VF */
2126 { PCI_VDEVICE(MELLANOX, 4125) }, /* ConnectX-6 Dx */
2127 { PCI_VDEVICE(MELLANOX, 4126), .driver_data = MLX5_PCI_DEV_IS_VF}, /* ConnectX Family mlx5Gen Virtual Function */
2128 { PCI_VDEVICE(MELLANOX, 4127) }, /* ConnectX-6 LX */
2129 { PCI_VDEVICE(MELLANOX, 4128) },
2130 { PCI_VDEVICE(MELLANOX, 4129) }, /* ConnectX-7 */
2131 { PCI_VDEVICE(MELLANOX, 4130) },
2132 { PCI_VDEVICE(MELLANOX, 4131) }, /* ConnectX-8 */
2133 { PCI_VDEVICE(MELLANOX, 4132) },
2134 { PCI_VDEVICE(MELLANOX, 4133) }, /* ConnectX-9 */
2135 { PCI_VDEVICE(MELLANOX, 4134) },
2136 { PCI_VDEVICE(MELLANOX, 4135) },
2137 { PCI_VDEVICE(MELLANOX, 4136) },
2138 { PCI_VDEVICE(MELLANOX, 4137) },
2139 { PCI_VDEVICE(MELLANOX, 4138) },
2140 { PCI_VDEVICE(MELLANOX, 4139) },
2141 { PCI_VDEVICE(MELLANOX, 4140) },
2142 { PCI_VDEVICE(MELLANOX, 4141) },
2143 { PCI_VDEVICE(MELLANOX, 4142) },
2144 { PCI_VDEVICE(MELLANOX, 4143) },
2145 { PCI_VDEVICE(MELLANOX, 4144) },
2146 { PCI_VDEVICE(MELLANOX, 0xa2d2) }, /* BlueField integrated ConnectX-5 network controller */
2147 { PCI_VDEVICE(MELLANOX, 0xa2d3), .driver_data = MLX5_PCI_DEV_IS_VF }, /* BlueField integrated ConnectX-5 network controller VF */
2148 { PCI_VDEVICE(MELLANOX, 0xa2d6) }, /* BlueField-2 integrated ConnectX-6 Dx network controller */
2149 { PCI_VDEVICE(MELLANOX, 0xa2dc) }, /* BlueField-3 integrated ConnectX-7 network controller */
2150 { PCI_VDEVICE(MELLANOX, 0xa2df) }, /* BlueField-4 Family integrated network controller */
2151 { }
2152 };
2153
2154 MODULE_DEVICE_TABLE(pci, mlx5_core_pci_table);
2155
mlx5_disable_device(struct mlx5_core_dev * dev)2156 void mlx5_disable_device(struct mlx5_core_dev *dev)
2157 {
2158 mlx5_pci_err_detected(dev->pdev, 0);
2159 }
2160
mlx5_recover_device(struct mlx5_core_dev * dev)2161 void mlx5_recover_device(struct mlx5_core_dev *dev)
2162 {
2163 mlx5_pci_disable_device(dev);
2164 if (mlx5_pci_slot_reset(dev->pdev) == PCI_ERS_RESULT_RECOVERED)
2165 mlx5_pci_resume(dev->pdev);
2166 }
2167
2168 struct pci_driver mlx5_core_driver = {
2169 .name = DRIVER_NAME,
2170 .id_table = mlx5_core_pci_table,
2171 .shutdown = shutdown_one,
2172 .probe = init_one,
2173 .remove = remove_one,
2174 .err_handler = &mlx5_err_handler,
2175 #ifdef PCI_IOV
2176 .bsd_iov_init = mlx5_iov_init,
2177 .bsd_iov_uninit = mlx5_iov_uninit,
2178 .bsd_iov_add_vf = mlx5_iov_add_vf,
2179 #endif
2180 };
2181
init(void)2182 static int __init init(void)
2183 {
2184 int err;
2185
2186 err = pci_register_driver(&mlx5_core_driver);
2187 if (err)
2188 goto err_debug;
2189
2190 err = mlx5_ctl_init();
2191 if (err)
2192 goto err_ctl;
2193
2194 return 0;
2195
2196 err_ctl:
2197 pci_unregister_driver(&mlx5_core_driver);
2198
2199 err_debug:
2200 return err;
2201 }
2202
cleanup(void)2203 static void __exit cleanup(void)
2204 {
2205 mlx5_ctl_fini();
2206 pci_unregister_driver(&mlx5_core_driver);
2207 }
2208
2209 module_init_order(init, SI_ORDER_FIRST);
2210 module_exit_order(cleanup, SI_ORDER_FIRST);
2211